From 7c6fe4237c55f6bd6fdaf1c8a6b884fbfb99ab8d Mon Sep 17 00:00:00 2001
From: Federica Di Lauro <federicadilauro1998@gmail.com>
Date: Fri, 20 Sep 2019 14:51:36 +0200
Subject: [PATCH] encoder tick reading and reset (working)

---
 otto_controller_source/.cproject              |   262 +-
 otto_controller_source/.project               |     2 +-
 .../.settings/language.settings.xml           |     4 +-
 otto_controller_source/Debug/makefile         |     2 +-
 .../Debug/otto_controller_source.list         | 10695 ++++++++++------
 otto_controller_source/Inc/encoder.h          |    16 +-
 otto_controller_source/Inc/main.h             |    18 +
 otto_controller_source/Src/encoder.cpp        |    10 +-
 otto_controller_source/Src/main.cpp           |   156 +-
 .../Src/stm32f7xx_hal_msp.c                   |   139 +-
 .../otto_controller_source.elf.launch         |    63 +
 .../otto_controller_source.ioc                |    89 +-
 12 files changed, 7115 insertions(+), 4341 deletions(-)
 create mode 100644 otto_controller_source/otto_controller_source.elf.launch

diff --git a/otto_controller_source/.cproject b/otto_controller_source/.cproject
index ca66fa1..4b8602a 100644
--- a/otto_controller_source/.cproject
+++ b/otto_controller_source/.cproject
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
 	<storageModule moduleId="org.eclipse.cdt.core.settings">
-		<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.392773116">
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.392773116" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+		<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1423404867">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1423404867" moduleId="org.eclipse.cdt.core.settings" name="Debug">
 				<externalSettings/>
 				<extensions>
 					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
@@ -13,79 +13,84 @@
 				</extensions>
 			</storageModule>
 			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.2001961837" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.1636505489" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32F767ZITX_FLASH.ld}" valueType="string"/>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.258066408" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
 							</tool>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.1412377355" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script.1698241096" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script" value="${workspace_loc:/${ProjName}/STM32F767ZITX_FLASH.ld}" valueType="string"/>
-								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.input.201166165" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.input">
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.138451589" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script.1789704503" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script" value="${workspace_loc:/${ProjName}/STM32F767ZITX_FLASH.ld}" valueType="string"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.systemcalls.1760486295" name="System calls" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.systemcalls" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.systemcalls.value.minimalimplementation" valueType="enumerated"/>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.input.584666908" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.input">
 									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
 									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
 								</inputType>
 							</tool>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.1021096116" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.1133700284" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.657980404" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.1788883330" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.254728800" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.438568399" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1896903758" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1471961284" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.927776484" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.1436749526" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.1828627743" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.1426764725" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1854387244" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.219240410" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1374243137" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1540290355" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
 						</toolChain>
 					</folderInfo>
 					<sourceEntries>
@@ -97,8 +102,8 @@
 			</storageModule>
 			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
 		</cconfiguration>
-		<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.658373970">
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.658373970" moduleId="org.eclipse.cdt.core.settings" name="Release">
+		<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.764532190">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.764532190" moduleId="org.eclipse.cdt.core.settings" name="Release">
 				<externalSettings/>
 				<extensions>
 					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
@@ -109,77 +114,82 @@
 				</extensions>
 			</storageModule>
 			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.658373970" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">
-					<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.658373970." name="/" resourcePath="">
-						<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release.1118251392" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release">
-							<option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.1909234318" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.1647156367" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.version" value="7-2018-q2-update" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.873517583" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" value="STM32F767ZITx" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.10780868" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" value="0" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1671641280" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" value="0" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.951416612" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv5-d16" valueType="enumerated"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.1029154631" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1961364743" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" value="genericBoard" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1861892626" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.0 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || STM32F767ZITx || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Inc | ../Drivers/CMSIS/Include | ../Drivers/CMSIS/Device/ST/STM32F7xx/Include | ../Drivers/STM32F7xx_HAL_Driver/Inc | ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy || ../ ||  || USE_HAL_DRIVER | STM32F767xx ||  || Startup || Drivers | Src ||  || ${workspace_loc:/${ProjName}/STM32F767ZITX_FLASH.ld} || true" valueType="string"/>
-							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.822901705" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
-							<builder buildPath="${workspace_loc:/otto_controller_source}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1014969032" managedBuildOn="true" name="Gnu Make Builder.Release" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1292746606" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.1663320188" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.includepaths.526870196" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.includepaths" valueType="includePath">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.764532190" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">
+					<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.764532190." name="/" resourcePath="">
+						<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release.2146131005" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release">
+							<option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.965482614" name="Internal Toolchain Type" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.263454240" name="Internal Toolchain Version" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.version" value="7-2018-q2-update" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.967155777" name="Mcu" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" value="STM32F767ZITx" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.709038617" name="CpuId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.2120860729" name="CpuCoreId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.1137930867" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv5-d16" valueType="enumerated"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.443919812" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1986795066" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" value="genericBoard" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.642751136" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.0 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || STM32F767ZITx || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Inc | ../Drivers/CMSIS/Include | ../Drivers/CMSIS/Device/ST/STM32F7xx/Include | ../Drivers/STM32F7xx_HAL_Driver/Inc | ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy || ../ ||  || USE_HAL_DRIVER | STM32F767xx ||  || Startup || Drivers | Src ||  || ${workspace_loc:/${ProjName}/STM32F767ZITX_FLASH.ld} || true" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1829260208" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
+							<builder buildPath="${workspace_loc:/otto_controller_source}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1741400309" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.680634514" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.249517123" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.includepaths.1314150614" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.includepaths" valueType="includePath">
 									<listOptionValue builtIn="false" value="../"/>
 								</option>
-								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.1746253654" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.829541877" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
 							</tool>
-							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1095556557" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.1273271907" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.1480372733" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.o3" valueType="enumerated"/>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.1650510654" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1896784767" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.1139857994" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.1805849797" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.o3" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.2083337652" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
 									<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
 									<listOptionValue builtIn="false" value="STM32F767xx"/>
 								</option>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.1144360222" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
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+			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.684476551;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.684476551.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1094740916;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp.338374062">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1063767783;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1063767783.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1732776268;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp.1781778991">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1423404867;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1423404867.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1371315860;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1491934329">
+			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1660686100;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1660686100.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.299654497;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.943278979">
+			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
 		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.392773116;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.392773116.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.865555638;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1313427753">
 			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
 		</scannerConfigBuildInfo>
-		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.658373970;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.658373970.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1161486784;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp.1392539340">
+		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.764532190;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.764532190.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.2132053756;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp.1712882001">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1423404867;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1423404867.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.528233423;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp.1897529701">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.764532190;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.764532190.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1896784767;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.2475057">
 			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
 		</scannerConfigBuildInfo>
 	</storageModule>
diff --git a/otto_controller_source/.project b/otto_controller_source/.project
index bad74ba..264b008 100644
--- a/otto_controller_source/.project
+++ b/otto_controller_source/.project
@@ -22,10 +22,10 @@
 		<nature>com.st.stm32cube.ide.mcu.MCUProjectNature</nature>
 		<nature>com.st.stm32cube.ide.mcu.MCUCubeProjectNature</nature>
 		<nature>org.eclipse.cdt.core.cnature</nature>
-		<nature>org.eclipse.cdt.core.ccnature</nature>
 		<nature>com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature</nature>
 		<nature>com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
 	</natures>
 </projectDescription>
diff --git a/otto_controller_source/.settings/language.settings.xml b/otto_controller_source/.settings/language.settings.xml
index 318a89a..9fd44ba 100644
--- a/otto_controller_source/.settings/language.settings.xml
+++ b/otto_controller_source/.settings/language.settings.xml
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <project>
-	<configuration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.392773116" name="Debug">
+	<configuration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1423404867" name="Debug">
 		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
@@ -12,7 +12,7 @@
 			</provider>
 		</extension>
 	</configuration>
-	<configuration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.658373970" name="Release">
+	<configuration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.764532190" name="Release">
 		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
diff --git a/otto_controller_source/Debug/makefile b/otto_controller_source/Debug/makefile
index 9bbf4ce..25f8813 100644
--- a/otto_controller_source/Debug/makefile
+++ b/otto_controller_source/Debug/makefile
@@ -53,7 +53,7 @@ all: otto_controller_source.elf secondary-outputs
 
 # Tool invocations
 otto_controller_source.elf: $(OBJS) $(USER_OBJS) /home/fdila/Projects/otto/otto_controller_source/STM32F767ZITX_FLASH.ld
-	arm-none-eabi-g++ -o "otto_controller_source.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m7 -T"/home/fdila/Projects/otto/otto_controller_source/STM32F767ZITX_FLASH.ld" --specs=nosys.specs -Wl,-Map="otto_controller_source.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group
+	arm-none-eabi-g++ -o "otto_controller_source.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m7 -T"/home/fdila/Projects/otto/otto_controller_source/STM32F767ZITX_FLASH.ld" -Wl,-Map="otto_controller_source.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group
 	@echo 'Finished building target: $@'
 	@echo ' '
 
diff --git a/otto_controller_source/Debug/otto_controller_source.list b/otto_controller_source/Debug/otto_controller_source.list
index 2e09430..68f6f66 100644
--- a/otto_controller_source/Debug/otto_controller_source.list
+++ b/otto_controller_source/Debug/otto_controller_source.list
@@ -5,45 +5,45 @@ Sections:
 Idx Name          Size      VMA       LMA       File off  Algn
   0 .isr_vector   000001f8  08000000  08000000  00010000  2**0
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  1 .text         0000357c  080001f8  080001f8  000101f8  2**2
+  1 .text         00004240  080001f8  080001f8  000101f8  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, CODE
-  2 .rodata       00000020  08003774  08003774  00013774  2**2
+  2 .rodata       00000020  08004438  08004438  00014438  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  3 .ARM.extab    00000000  08003794  08003794  0002000c  2**0
+  3 .ARM.extab    00000000  08004458  08004458  0002000c  2**0
                   CONTENTS
-  4 .ARM          00000008  08003794  08003794  00013794  2**2
+  4 .ARM          00000008  08004458  08004458  00014458  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  5 .preinit_array 00000000  0800379c  0800379c  0002000c  2**0
+  5 .preinit_array 00000000  08004460  08004460  0002000c  2**0
                   CONTENTS, ALLOC, LOAD, DATA
-  6 .init_array   00000004  0800379c  0800379c  0001379c  2**2
+  6 .init_array   00000004  08004460  08004460  00014460  2**2
                   CONTENTS, ALLOC, LOAD, DATA
-  7 .fini_array   00000004  080037a0  080037a0  000137a0  2**2
+  7 .fini_array   00000004  08004464  08004464  00014464  2**2
                   CONTENTS, ALLOC, LOAD, DATA
-  8 .data         0000000c  20000000  080037a4  00020000  2**2
+  8 .data         0000000c  20000000  08004468  00020000  2**2
                   CONTENTS, ALLOC, LOAD, DATA
-  9 .bss          000001a0  2000000c  080037b0  0002000c  2**2
+  9 .bss          00000220  2000000c  08004474  0002000c  2**2
                   ALLOC
- 10 ._user_heap_stack 00000604  200001ac  080037b0  000201ac  2**0
+ 10 ._user_heap_stack 00000604  2000022c  08004474  0002022c  2**0
                   ALLOC
  11 .ARM.attributes 0000002e  00000000  00000000  0002000c  2**0
                   CONTENTS, READONLY
- 12 .debug_info   0000c0d2  00000000  00000000  0002003a  2**0
+ 12 .debug_info   0000cce7  00000000  00000000  0002003a  2**0
                   CONTENTS, READONLY, DEBUGGING
- 13 .debug_abbrev 00001986  00000000  00000000  0002c10c  2**0
+ 13 .debug_abbrev 00001c58  00000000  00000000  0002cd21  2**0
                   CONTENTS, READONLY, DEBUGGING
- 14 .debug_aranges 00000c58  00000000  00000000  0002da98  2**3
+ 14 .debug_aranges 00000cb0  00000000  00000000  0002e980  2**3
                   CONTENTS, READONLY, DEBUGGING
- 15 .debug_ranges 00000b80  00000000  00000000  0002e6f0  2**3
+ 15 .debug_ranges 00000bc8  00000000  00000000  0002f630  2**3
                   CONTENTS, READONLY, DEBUGGING
- 16 .debug_macro  0002722c  00000000  00000000  0002f270  2**0
+ 16 .debug_macro  000274ae  00000000  00000000  000301f8  2**0
                   CONTENTS, READONLY, DEBUGGING
- 17 .debug_line   00008e9c  00000000  00000000  0005649c  2**0
+ 17 .debug_line   00009674  00000000  00000000  000576a6  2**0
                   CONTENTS, READONLY, DEBUGGING
- 18 .debug_str    000f12d5  00000000  00000000  0005f338  2**0
+ 18 .debug_str    000f1566  00000000  00000000  00060d1a  2**0
                   CONTENTS, READONLY, DEBUGGING
- 19 .comment      0000007b  00000000  00000000  0015060d  2**0
+ 19 .comment      0000007b  00000000  00000000  00152280  2**0
                   CONTENTS, READONLY
- 20 .debug_frame  000033d0  00000000  00000000  00150688  2**2
+ 20 .debug_frame  00003510  00000000  00000000  001522fc  2**2
                   CONTENTS, READONLY, DEBUGGING
 
 Disassembly of section .text:
@@ -62,7 +62,7 @@ Disassembly of section .text:
  800020e:	bd10      	pop	{r4, pc}
  8000210:	2000000c 	.word	0x2000000c
  8000214:	00000000 	.word	0x00000000
- 8000218:	0800375c 	.word	0x0800375c
+ 8000218:	08004420 	.word	0x08004420
 
 0800021c <frame_dummy>:
  800021c:	b508      	push	{r3, lr}
@@ -74,7 +74,7 @@ Disassembly of section .text:
  800022a:	bd08      	pop	{r3, pc}
  800022c:	00000000 	.word	0x00000000
  8000230:	20000010 	.word	0x20000010
- 8000234:	0800375c 	.word	0x0800375c
+ 8000234:	08004420 	.word	0x08004420
 
 08000238 <__aeabi_uldivmod>:
  8000238:	b953      	cbnz	r3, 8000250 <__aeabi_uldivmod+0x18>
@@ -378,7 +378,7 @@ HAL_StatusTypeDef HAL_Init(void)
   
   /* Init the low level hardware */
   HAL_MspInit();
- 8000548:	f002 ff16 	bl	8003378 <HAL_MspInit>
+ 8000548:	f003 fcd2 	bl	8003ef0 <HAL_MspInit>
   
   /* Return function status */
   return HAL_OK;
@@ -479,7 +479,7 @@ __weak void HAL_IncTick(void)
  80005d0:	4770      	bx	lr
  80005d2:	bf00      	nop
  80005d4:	20000004 	.word	0x20000004
- 80005d8:	200001a8 	.word	0x200001a8
+ 80005d8:	20000228 	.word	0x20000228
 
 080005dc <HAL_GetTick>:
   * @note This function is declared as __weak to be overwritten in case of other 
@@ -499,7 +499,7 @@ __weak uint32_t HAL_GetTick(void)
  80005e8:	f85d 7b04 	ldr.w	r7, [sp], #4
  80005ec:	4770      	bx	lr
  80005ee:	bf00      	nop
- 80005f0:	200001a8 	.word	0x200001a8
+ 80005f0:	20000228 	.word	0x20000228
 
 080005f4 <__NVIC_SetPriorityGrouping>:
            In case of a conflict between priority grouping and available
@@ -1883,7 +1883,7 @@ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
  8000d28:	4770      	bx	lr
  8000d2a:	bf00      	nop
  8000d2c:	aaaaaaab 	.word	0xaaaaaaab
- 8000d30:	08003774 	.word	0x08003774
+ 8000d30:	08004438 	.word	0x08004438
  8000d34:	fffffc00 	.word	0xfffffc00
 
 08000d38 <DMA_CheckFifoParam>:
@@ -2577,6583 +2577,8874 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
  8001178:	40022400 	.word	0x40022400
  800117c:	40013c00 	.word	0x40013c00
 
-08001180 <HAL_RCC_OscConfig>:
+08001180 <HAL_GPIO_WritePin>:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+ 8001180:	b480      	push	{r7}
+ 8001182:	b083      	sub	sp, #12
+ 8001184:	af00      	add	r7, sp, #0
+ 8001186:	6078      	str	r0, [r7, #4]
+ 8001188:	460b      	mov	r3, r1
+ 800118a:	807b      	strh	r3, [r7, #2]
+ 800118c:	4613      	mov	r3, r2
+ 800118e:	707b      	strb	r3, [r7, #1]
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if(PinState != GPIO_PIN_RESET)
+ 8001190:	787b      	ldrb	r3, [r7, #1]
+ 8001192:	2b00      	cmp	r3, #0
+ 8001194:	d003      	beq.n	800119e <HAL_GPIO_WritePin+0x1e>
+  {
+    GPIOx->BSRR = GPIO_Pin;
+ 8001196:	887a      	ldrh	r2, [r7, #2]
+ 8001198:	687b      	ldr	r3, [r7, #4]
+ 800119a:	619a      	str	r2, [r3, #24]
+  }
+  else
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
+  }
+}
+ 800119c:	e003      	b.n	80011a6 <HAL_GPIO_WritePin+0x26>
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
+ 800119e:	887b      	ldrh	r3, [r7, #2]
+ 80011a0:	041a      	lsls	r2, r3, #16
+ 80011a2:	687b      	ldr	r3, [r7, #4]
+ 80011a4:	619a      	str	r2, [r3, #24]
+}
+ 80011a6:	bf00      	nop
+ 80011a8:	370c      	adds	r7, #12
+ 80011aa:	46bd      	mov	sp, r7
+ 80011ac:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80011b0:	4770      	bx	lr
+	...
+
+080011b4 <HAL_RCC_OscConfig>:
   *         supported by this function. User should request a transition to HSE Off
   *         first and then HSE On or HSE Bypass.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 {
- 8001180:	b580      	push	{r7, lr}
- 8001182:	b086      	sub	sp, #24
- 8001184:	af00      	add	r7, sp, #0
- 8001186:	6078      	str	r0, [r7, #4]
+ 80011b4:	b580      	push	{r7, lr}
+ 80011b6:	b086      	sub	sp, #24
+ 80011b8:	af00      	add	r7, sp, #0
+ 80011ba:	6078      	str	r0, [r7, #4]
   uint32_t tickstart;
   FlagStatus pwrclkchanged = RESET;
- 8001188:	2300      	movs	r3, #0
- 800118a:	75fb      	strb	r3, [r7, #23]
+ 80011bc:	2300      	movs	r3, #0
+ 80011be:	75fb      	strb	r3, [r7, #23]
 
   /* Check Null pointer */
   if(RCC_OscInitStruct == NULL)
- 800118c:	687b      	ldr	r3, [r7, #4]
- 800118e:	2b00      	cmp	r3, #0
- 8001190:	d101      	bne.n	8001196 <HAL_RCC_OscConfig+0x16>
+ 80011c0:	687b      	ldr	r3, [r7, #4]
+ 80011c2:	2b00      	cmp	r3, #0
+ 80011c4:	d101      	bne.n	80011ca <HAL_RCC_OscConfig+0x16>
   {
     return HAL_ERROR;
- 8001192:	2301      	movs	r3, #1
- 8001194:	e25e      	b.n	8001654 <HAL_RCC_OscConfig+0x4d4>
+ 80011c6:	2301      	movs	r3, #1
+ 80011c8:	e25e      	b.n	8001688 <HAL_RCC_OscConfig+0x4d4>
 
   /* Check the parameters */
   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
 
   /*------------------------------- HSE Configuration ------------------------*/
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- 8001196:	687b      	ldr	r3, [r7, #4]
- 8001198:	681b      	ldr	r3, [r3, #0]
- 800119a:	f003 0301 	and.w	r3, r3, #1
- 800119e:	2b00      	cmp	r3, #0
- 80011a0:	f000 8087 	beq.w	80012b2 <HAL_RCC_OscConfig+0x132>
+ 80011ca:	687b      	ldr	r3, [r7, #4]
+ 80011cc:	681b      	ldr	r3, [r3, #0]
+ 80011ce:	f003 0301 	and.w	r3, r3, #1
+ 80011d2:	2b00      	cmp	r3, #0
+ 80011d4:	f000 8087 	beq.w	80012e6 <HAL_RCC_OscConfig+0x132>
   {
     /* Check the parameters */
     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
     /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
- 80011a4:	4b96      	ldr	r3, [pc, #600]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 80011a6:	689b      	ldr	r3, [r3, #8]
- 80011a8:	f003 030c 	and.w	r3, r3, #12
- 80011ac:	2b04      	cmp	r3, #4
- 80011ae:	d00c      	beq.n	80011ca <HAL_RCC_OscConfig+0x4a>
+ 80011d8:	4b96      	ldr	r3, [pc, #600]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 80011da:	689b      	ldr	r3, [r3, #8]
+ 80011dc:	f003 030c 	and.w	r3, r3, #12
+ 80011e0:	2b04      	cmp	r3, #4
+ 80011e2:	d00c      	beq.n	80011fe <HAL_RCC_OscConfig+0x4a>
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
- 80011b0:	4b93      	ldr	r3, [pc, #588]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 80011b2:	689b      	ldr	r3, [r3, #8]
- 80011b4:	f003 030c 	and.w	r3, r3, #12
- 80011b8:	2b08      	cmp	r3, #8
- 80011ba:	d112      	bne.n	80011e2 <HAL_RCC_OscConfig+0x62>
- 80011bc:	4b90      	ldr	r3, [pc, #576]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 80011be:	685b      	ldr	r3, [r3, #4]
- 80011c0:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
- 80011c4:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
- 80011c8:	d10b      	bne.n	80011e2 <HAL_RCC_OscConfig+0x62>
+ 80011e4:	4b93      	ldr	r3, [pc, #588]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 80011e6:	689b      	ldr	r3, [r3, #8]
+ 80011e8:	f003 030c 	and.w	r3, r3, #12
+ 80011ec:	2b08      	cmp	r3, #8
+ 80011ee:	d112      	bne.n	8001216 <HAL_RCC_OscConfig+0x62>
+ 80011f0:	4b90      	ldr	r3, [pc, #576]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 80011f2:	685b      	ldr	r3, [r3, #4]
+ 80011f4:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
+ 80011f8:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
+ 80011fc:	d10b      	bne.n	8001216 <HAL_RCC_OscConfig+0x62>
     {
       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 80011ca:	4b8d      	ldr	r3, [pc, #564]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 80011cc:	681b      	ldr	r3, [r3, #0]
- 80011ce:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 80011d2:	2b00      	cmp	r3, #0
- 80011d4:	d06c      	beq.n	80012b0 <HAL_RCC_OscConfig+0x130>
- 80011d6:	687b      	ldr	r3, [r7, #4]
- 80011d8:	685b      	ldr	r3, [r3, #4]
- 80011da:	2b00      	cmp	r3, #0
- 80011dc:	d168      	bne.n	80012b0 <HAL_RCC_OscConfig+0x130>
+ 80011fe:	4b8d      	ldr	r3, [pc, #564]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001200:	681b      	ldr	r3, [r3, #0]
+ 8001202:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 8001206:	2b00      	cmp	r3, #0
+ 8001208:	d06c      	beq.n	80012e4 <HAL_RCC_OscConfig+0x130>
+ 800120a:	687b      	ldr	r3, [r7, #4]
+ 800120c:	685b      	ldr	r3, [r3, #4]
+ 800120e:	2b00      	cmp	r3, #0
+ 8001210:	d168      	bne.n	80012e4 <HAL_RCC_OscConfig+0x130>
       {
         return HAL_ERROR;
- 80011de:	2301      	movs	r3, #1
- 80011e0:	e238      	b.n	8001654 <HAL_RCC_OscConfig+0x4d4>
+ 8001212:	2301      	movs	r3, #1
+ 8001214:	e238      	b.n	8001688 <HAL_RCC_OscConfig+0x4d4>
       }
     }
     else
     {
       /* Set the new HSE configuration ---------------------------------------*/
       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
- 80011e2:	687b      	ldr	r3, [r7, #4]
- 80011e4:	685b      	ldr	r3, [r3, #4]
- 80011e6:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
- 80011ea:	d106      	bne.n	80011fa <HAL_RCC_OscConfig+0x7a>
- 80011ec:	4b84      	ldr	r3, [pc, #528]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 80011ee:	681b      	ldr	r3, [r3, #0]
- 80011f0:	4a83      	ldr	r2, [pc, #524]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 80011f2:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
- 80011f6:	6013      	str	r3, [r2, #0]
- 80011f8:	e02e      	b.n	8001258 <HAL_RCC_OscConfig+0xd8>
- 80011fa:	687b      	ldr	r3, [r7, #4]
- 80011fc:	685b      	ldr	r3, [r3, #4]
- 80011fe:	2b00      	cmp	r3, #0
- 8001200:	d10c      	bne.n	800121c <HAL_RCC_OscConfig+0x9c>
- 8001202:	4b7f      	ldr	r3, [pc, #508]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 8001204:	681b      	ldr	r3, [r3, #0]
- 8001206:	4a7e      	ldr	r2, [pc, #504]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 8001208:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
- 800120c:	6013      	str	r3, [r2, #0]
- 800120e:	4b7c      	ldr	r3, [pc, #496]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 8001210:	681b      	ldr	r3, [r3, #0]
- 8001212:	4a7b      	ldr	r2, [pc, #492]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 8001214:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
- 8001218:	6013      	str	r3, [r2, #0]
- 800121a:	e01d      	b.n	8001258 <HAL_RCC_OscConfig+0xd8>
- 800121c:	687b      	ldr	r3, [r7, #4]
- 800121e:	685b      	ldr	r3, [r3, #4]
- 8001220:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
- 8001224:	d10c      	bne.n	8001240 <HAL_RCC_OscConfig+0xc0>
- 8001226:	4b76      	ldr	r3, [pc, #472]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 8001228:	681b      	ldr	r3, [r3, #0]
- 800122a:	4a75      	ldr	r2, [pc, #468]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 800122c:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
- 8001230:	6013      	str	r3, [r2, #0]
- 8001232:	4b73      	ldr	r3, [pc, #460]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 8001234:	681b      	ldr	r3, [r3, #0]
- 8001236:	4a72      	ldr	r2, [pc, #456]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 8001238:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
- 800123c:	6013      	str	r3, [r2, #0]
- 800123e:	e00b      	b.n	8001258 <HAL_RCC_OscConfig+0xd8>
- 8001240:	4b6f      	ldr	r3, [pc, #444]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 8001242:	681b      	ldr	r3, [r3, #0]
- 8001244:	4a6e      	ldr	r2, [pc, #440]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 8001246:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
- 800124a:	6013      	str	r3, [r2, #0]
- 800124c:	4b6c      	ldr	r3, [pc, #432]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 800124e:	681b      	ldr	r3, [r3, #0]
- 8001250:	4a6b      	ldr	r2, [pc, #428]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 8001252:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
- 8001256:	6013      	str	r3, [r2, #0]
+ 8001216:	687b      	ldr	r3, [r7, #4]
+ 8001218:	685b      	ldr	r3, [r3, #4]
+ 800121a:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 800121e:	d106      	bne.n	800122e <HAL_RCC_OscConfig+0x7a>
+ 8001220:	4b84      	ldr	r3, [pc, #528]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001222:	681b      	ldr	r3, [r3, #0]
+ 8001224:	4a83      	ldr	r2, [pc, #524]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001226:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
+ 800122a:	6013      	str	r3, [r2, #0]
+ 800122c:	e02e      	b.n	800128c <HAL_RCC_OscConfig+0xd8>
+ 800122e:	687b      	ldr	r3, [r7, #4]
+ 8001230:	685b      	ldr	r3, [r3, #4]
+ 8001232:	2b00      	cmp	r3, #0
+ 8001234:	d10c      	bne.n	8001250 <HAL_RCC_OscConfig+0x9c>
+ 8001236:	4b7f      	ldr	r3, [pc, #508]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001238:	681b      	ldr	r3, [r3, #0]
+ 800123a:	4a7e      	ldr	r2, [pc, #504]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 800123c:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
+ 8001240:	6013      	str	r3, [r2, #0]
+ 8001242:	4b7c      	ldr	r3, [pc, #496]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001244:	681b      	ldr	r3, [r3, #0]
+ 8001246:	4a7b      	ldr	r2, [pc, #492]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001248:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
+ 800124c:	6013      	str	r3, [r2, #0]
+ 800124e:	e01d      	b.n	800128c <HAL_RCC_OscConfig+0xd8>
+ 8001250:	687b      	ldr	r3, [r7, #4]
+ 8001252:	685b      	ldr	r3, [r3, #4]
+ 8001254:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
+ 8001258:	d10c      	bne.n	8001274 <HAL_RCC_OscConfig+0xc0>
+ 800125a:	4b76      	ldr	r3, [pc, #472]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 800125c:	681b      	ldr	r3, [r3, #0]
+ 800125e:	4a75      	ldr	r2, [pc, #468]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001260:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
+ 8001264:	6013      	str	r3, [r2, #0]
+ 8001266:	4b73      	ldr	r3, [pc, #460]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001268:	681b      	ldr	r3, [r3, #0]
+ 800126a:	4a72      	ldr	r2, [pc, #456]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 800126c:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
+ 8001270:	6013      	str	r3, [r2, #0]
+ 8001272:	e00b      	b.n	800128c <HAL_RCC_OscConfig+0xd8>
+ 8001274:	4b6f      	ldr	r3, [pc, #444]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001276:	681b      	ldr	r3, [r3, #0]
+ 8001278:	4a6e      	ldr	r2, [pc, #440]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 800127a:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
+ 800127e:	6013      	str	r3, [r2, #0]
+ 8001280:	4b6c      	ldr	r3, [pc, #432]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001282:	681b      	ldr	r3, [r3, #0]
+ 8001284:	4a6b      	ldr	r2, [pc, #428]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001286:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
+ 800128a:	6013      	str	r3, [r2, #0]
 
       /* Check the HSE State */
       if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- 8001258:	687b      	ldr	r3, [r7, #4]
- 800125a:	685b      	ldr	r3, [r3, #4]
- 800125c:	2b00      	cmp	r3, #0
- 800125e:	d013      	beq.n	8001288 <HAL_RCC_OscConfig+0x108>
+ 800128c:	687b      	ldr	r3, [r7, #4]
+ 800128e:	685b      	ldr	r3, [r3, #4]
+ 8001290:	2b00      	cmp	r3, #0
+ 8001292:	d013      	beq.n	80012bc <HAL_RCC_OscConfig+0x108>
       {
         /* Get Start Tick*/
         tickstart = HAL_GetTick();
- 8001260:	f7ff f9bc 	bl	80005dc <HAL_GetTick>
- 8001264:	6138      	str	r0, [r7, #16]
+ 8001294:	f7ff f9a2 	bl	80005dc <HAL_GetTick>
+ 8001298:	6138      	str	r0, [r7, #16]
 
         /* Wait till HSE is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 8001266:	e008      	b.n	800127a <HAL_RCC_OscConfig+0xfa>
+ 800129a:	e008      	b.n	80012ae <HAL_RCC_OscConfig+0xfa>
         {
           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 8001268:	f7ff f9b8 	bl	80005dc <HAL_GetTick>
- 800126c:	4602      	mov	r2, r0
- 800126e:	693b      	ldr	r3, [r7, #16]
- 8001270:	1ad3      	subs	r3, r2, r3
- 8001272:	2b64      	cmp	r3, #100	; 0x64
- 8001274:	d901      	bls.n	800127a <HAL_RCC_OscConfig+0xfa>
+ 800129c:	f7ff f99e 	bl	80005dc <HAL_GetTick>
+ 80012a0:	4602      	mov	r2, r0
+ 80012a2:	693b      	ldr	r3, [r7, #16]
+ 80012a4:	1ad3      	subs	r3, r2, r3
+ 80012a6:	2b64      	cmp	r3, #100	; 0x64
+ 80012a8:	d901      	bls.n	80012ae <HAL_RCC_OscConfig+0xfa>
           {
             return HAL_TIMEOUT;
- 8001276:	2303      	movs	r3, #3
- 8001278:	e1ec      	b.n	8001654 <HAL_RCC_OscConfig+0x4d4>
+ 80012aa:	2303      	movs	r3, #3
+ 80012ac:	e1ec      	b.n	8001688 <HAL_RCC_OscConfig+0x4d4>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 800127a:	4b61      	ldr	r3, [pc, #388]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 800127c:	681b      	ldr	r3, [r3, #0]
- 800127e:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 8001282:	2b00      	cmp	r3, #0
- 8001284:	d0f0      	beq.n	8001268 <HAL_RCC_OscConfig+0xe8>
- 8001286:	e014      	b.n	80012b2 <HAL_RCC_OscConfig+0x132>
+ 80012ae:	4b61      	ldr	r3, [pc, #388]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 80012b0:	681b      	ldr	r3, [r3, #0]
+ 80012b2:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 80012b6:	2b00      	cmp	r3, #0
+ 80012b8:	d0f0      	beq.n	800129c <HAL_RCC_OscConfig+0xe8>
+ 80012ba:	e014      	b.n	80012e6 <HAL_RCC_OscConfig+0x132>
         }
       }
       else
       {
         /* Get Start Tick*/
         tickstart = HAL_GetTick();
- 8001288:	f7ff f9a8 	bl	80005dc <HAL_GetTick>
- 800128c:	6138      	str	r0, [r7, #16]
+ 80012bc:	f7ff f98e 	bl	80005dc <HAL_GetTick>
+ 80012c0:	6138      	str	r0, [r7, #16]
 
         /* Wait till HSE is bypassed or disabled */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 800128e:	e008      	b.n	80012a2 <HAL_RCC_OscConfig+0x122>
+ 80012c2:	e008      	b.n	80012d6 <HAL_RCC_OscConfig+0x122>
         {
            if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 8001290:	f7ff f9a4 	bl	80005dc <HAL_GetTick>
- 8001294:	4602      	mov	r2, r0
- 8001296:	693b      	ldr	r3, [r7, #16]
- 8001298:	1ad3      	subs	r3, r2, r3
- 800129a:	2b64      	cmp	r3, #100	; 0x64
- 800129c:	d901      	bls.n	80012a2 <HAL_RCC_OscConfig+0x122>
+ 80012c4:	f7ff f98a 	bl	80005dc <HAL_GetTick>
+ 80012c8:	4602      	mov	r2, r0
+ 80012ca:	693b      	ldr	r3, [r7, #16]
+ 80012cc:	1ad3      	subs	r3, r2, r3
+ 80012ce:	2b64      	cmp	r3, #100	; 0x64
+ 80012d0:	d901      	bls.n	80012d6 <HAL_RCC_OscConfig+0x122>
           {
             return HAL_TIMEOUT;
- 800129e:	2303      	movs	r3, #3
- 80012a0:	e1d8      	b.n	8001654 <HAL_RCC_OscConfig+0x4d4>
+ 80012d2:	2303      	movs	r3, #3
+ 80012d4:	e1d8      	b.n	8001688 <HAL_RCC_OscConfig+0x4d4>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 80012a2:	4b57      	ldr	r3, [pc, #348]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 80012a4:	681b      	ldr	r3, [r3, #0]
- 80012a6:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 80012aa:	2b00      	cmp	r3, #0
- 80012ac:	d1f0      	bne.n	8001290 <HAL_RCC_OscConfig+0x110>
- 80012ae:	e000      	b.n	80012b2 <HAL_RCC_OscConfig+0x132>
+ 80012d6:	4b57      	ldr	r3, [pc, #348]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 80012d8:	681b      	ldr	r3, [r3, #0]
+ 80012da:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 80012de:	2b00      	cmp	r3, #0
+ 80012e0:	d1f0      	bne.n	80012c4 <HAL_RCC_OscConfig+0x110>
+ 80012e2:	e000      	b.n	80012e6 <HAL_RCC_OscConfig+0x132>
       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 80012b0:	bf00      	nop
+ 80012e4:	bf00      	nop
         }
       }
     }
   }
   /*----------------------------- HSI Configuration --------------------------*/
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- 80012b2:	687b      	ldr	r3, [r7, #4]
- 80012b4:	681b      	ldr	r3, [r3, #0]
- 80012b6:	f003 0302 	and.w	r3, r3, #2
- 80012ba:	2b00      	cmp	r3, #0
- 80012bc:	d069      	beq.n	8001392 <HAL_RCC_OscConfig+0x212>
+ 80012e6:	687b      	ldr	r3, [r7, #4]
+ 80012e8:	681b      	ldr	r3, [r3, #0]
+ 80012ea:	f003 0302 	and.w	r3, r3, #2
+ 80012ee:	2b00      	cmp	r3, #0
+ 80012f0:	d069      	beq.n	80013c6 <HAL_RCC_OscConfig+0x212>
     /* Check the parameters */
     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
 
     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
- 80012be:	4b50      	ldr	r3, [pc, #320]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 80012c0:	689b      	ldr	r3, [r3, #8]
- 80012c2:	f003 030c 	and.w	r3, r3, #12
- 80012c6:	2b00      	cmp	r3, #0
- 80012c8:	d00b      	beq.n	80012e2 <HAL_RCC_OscConfig+0x162>
+ 80012f2:	4b50      	ldr	r3, [pc, #320]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 80012f4:	689b      	ldr	r3, [r3, #8]
+ 80012f6:	f003 030c 	and.w	r3, r3, #12
+ 80012fa:	2b00      	cmp	r3, #0
+ 80012fc:	d00b      	beq.n	8001316 <HAL_RCC_OscConfig+0x162>
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
- 80012ca:	4b4d      	ldr	r3, [pc, #308]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 80012cc:	689b      	ldr	r3, [r3, #8]
- 80012ce:	f003 030c 	and.w	r3, r3, #12
- 80012d2:	2b08      	cmp	r3, #8
- 80012d4:	d11c      	bne.n	8001310 <HAL_RCC_OscConfig+0x190>
- 80012d6:	4b4a      	ldr	r3, [pc, #296]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 80012d8:	685b      	ldr	r3, [r3, #4]
- 80012da:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
- 80012de:	2b00      	cmp	r3, #0
- 80012e0:	d116      	bne.n	8001310 <HAL_RCC_OscConfig+0x190>
+ 80012fe:	4b4d      	ldr	r3, [pc, #308]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001300:	689b      	ldr	r3, [r3, #8]
+ 8001302:	f003 030c 	and.w	r3, r3, #12
+ 8001306:	2b08      	cmp	r3, #8
+ 8001308:	d11c      	bne.n	8001344 <HAL_RCC_OscConfig+0x190>
+ 800130a:	4b4a      	ldr	r3, [pc, #296]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 800130c:	685b      	ldr	r3, [r3, #4]
+ 800130e:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
+ 8001312:	2b00      	cmp	r3, #0
+ 8001314:	d116      	bne.n	8001344 <HAL_RCC_OscConfig+0x190>
     {
       /* When HSI is used as system clock it will not disabled */
       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 80012e2:	4b47      	ldr	r3, [pc, #284]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 80012e4:	681b      	ldr	r3, [r3, #0]
- 80012e6:	f003 0302 	and.w	r3, r3, #2
- 80012ea:	2b00      	cmp	r3, #0
- 80012ec:	d005      	beq.n	80012fa <HAL_RCC_OscConfig+0x17a>
- 80012ee:	687b      	ldr	r3, [r7, #4]
- 80012f0:	68db      	ldr	r3, [r3, #12]
- 80012f2:	2b01      	cmp	r3, #1
- 80012f4:	d001      	beq.n	80012fa <HAL_RCC_OscConfig+0x17a>
+ 8001316:	4b47      	ldr	r3, [pc, #284]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001318:	681b      	ldr	r3, [r3, #0]
+ 800131a:	f003 0302 	and.w	r3, r3, #2
+ 800131e:	2b00      	cmp	r3, #0
+ 8001320:	d005      	beq.n	800132e <HAL_RCC_OscConfig+0x17a>
+ 8001322:	687b      	ldr	r3, [r7, #4]
+ 8001324:	68db      	ldr	r3, [r3, #12]
+ 8001326:	2b01      	cmp	r3, #1
+ 8001328:	d001      	beq.n	800132e <HAL_RCC_OscConfig+0x17a>
       {
         return HAL_ERROR;
- 80012f6:	2301      	movs	r3, #1
- 80012f8:	e1ac      	b.n	8001654 <HAL_RCC_OscConfig+0x4d4>
+ 800132a:	2301      	movs	r3, #1
+ 800132c:	e1ac      	b.n	8001688 <HAL_RCC_OscConfig+0x4d4>
       }
       /* Otherwise, just the calibration is allowed */
       else
       {
         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 80012fa:	4b41      	ldr	r3, [pc, #260]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 80012fc:	681b      	ldr	r3, [r3, #0]
- 80012fe:	f023 02f8 	bic.w	r2, r3, #248	; 0xf8
- 8001302:	687b      	ldr	r3, [r7, #4]
- 8001304:	691b      	ldr	r3, [r3, #16]
- 8001306:	00db      	lsls	r3, r3, #3
- 8001308:	493d      	ldr	r1, [pc, #244]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 800130a:	4313      	orrs	r3, r2
- 800130c:	600b      	str	r3, [r1, #0]
+ 800132e:	4b41      	ldr	r3, [pc, #260]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001330:	681b      	ldr	r3, [r3, #0]
+ 8001332:	f023 02f8 	bic.w	r2, r3, #248	; 0xf8
+ 8001336:	687b      	ldr	r3, [r7, #4]
+ 8001338:	691b      	ldr	r3, [r3, #16]
+ 800133a:	00db      	lsls	r3, r3, #3
+ 800133c:	493d      	ldr	r1, [pc, #244]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 800133e:	4313      	orrs	r3, r2
+ 8001340:	600b      	str	r3, [r1, #0]
       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 800130e:	e040      	b.n	8001392 <HAL_RCC_OscConfig+0x212>
+ 8001342:	e040      	b.n	80013c6 <HAL_RCC_OscConfig+0x212>
       }
     }
     else
     {
       /* Check the HSI State */
       if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
- 8001310:	687b      	ldr	r3, [r7, #4]
- 8001312:	68db      	ldr	r3, [r3, #12]
- 8001314:	2b00      	cmp	r3, #0
- 8001316:	d023      	beq.n	8001360 <HAL_RCC_OscConfig+0x1e0>
+ 8001344:	687b      	ldr	r3, [r7, #4]
+ 8001346:	68db      	ldr	r3, [r3, #12]
+ 8001348:	2b00      	cmp	r3, #0
+ 800134a:	d023      	beq.n	8001394 <HAL_RCC_OscConfig+0x1e0>
       {
         /* Enable the Internal High Speed oscillator (HSI). */
         __HAL_RCC_HSI_ENABLE();
- 8001318:	4b39      	ldr	r3, [pc, #228]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 800131a:	681b      	ldr	r3, [r3, #0]
- 800131c:	4a38      	ldr	r2, [pc, #224]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 800131e:	f043 0301 	orr.w	r3, r3, #1
- 8001322:	6013      	str	r3, [r2, #0]
+ 800134c:	4b39      	ldr	r3, [pc, #228]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 800134e:	681b      	ldr	r3, [r3, #0]
+ 8001350:	4a38      	ldr	r2, [pc, #224]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001352:	f043 0301 	orr.w	r3, r3, #1
+ 8001356:	6013      	str	r3, [r2, #0]
 
         /* Get Start Tick*/
         tickstart = HAL_GetTick();
- 8001324:	f7ff f95a 	bl	80005dc <HAL_GetTick>
- 8001328:	6138      	str	r0, [r7, #16]
+ 8001358:	f7ff f940 	bl	80005dc <HAL_GetTick>
+ 800135c:	6138      	str	r0, [r7, #16]
 
         /* Wait till HSI is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 800132a:	e008      	b.n	800133e <HAL_RCC_OscConfig+0x1be>
+ 800135e:	e008      	b.n	8001372 <HAL_RCC_OscConfig+0x1be>
         {
           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 800132c:	f7ff f956 	bl	80005dc <HAL_GetTick>
- 8001330:	4602      	mov	r2, r0
- 8001332:	693b      	ldr	r3, [r7, #16]
- 8001334:	1ad3      	subs	r3, r2, r3
- 8001336:	2b02      	cmp	r3, #2
- 8001338:	d901      	bls.n	800133e <HAL_RCC_OscConfig+0x1be>
+ 8001360:	f7ff f93c 	bl	80005dc <HAL_GetTick>
+ 8001364:	4602      	mov	r2, r0
+ 8001366:	693b      	ldr	r3, [r7, #16]
+ 8001368:	1ad3      	subs	r3, r2, r3
+ 800136a:	2b02      	cmp	r3, #2
+ 800136c:	d901      	bls.n	8001372 <HAL_RCC_OscConfig+0x1be>
           {
             return HAL_TIMEOUT;
- 800133a:	2303      	movs	r3, #3
- 800133c:	e18a      	b.n	8001654 <HAL_RCC_OscConfig+0x4d4>
+ 800136e:	2303      	movs	r3, #3
+ 8001370:	e18a      	b.n	8001688 <HAL_RCC_OscConfig+0x4d4>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 800133e:	4b30      	ldr	r3, [pc, #192]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 8001340:	681b      	ldr	r3, [r3, #0]
- 8001342:	f003 0302 	and.w	r3, r3, #2
- 8001346:	2b00      	cmp	r3, #0
- 8001348:	d0f0      	beq.n	800132c <HAL_RCC_OscConfig+0x1ac>
+ 8001372:	4b30      	ldr	r3, [pc, #192]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001374:	681b      	ldr	r3, [r3, #0]
+ 8001376:	f003 0302 	and.w	r3, r3, #2
+ 800137a:	2b00      	cmp	r3, #0
+ 800137c:	d0f0      	beq.n	8001360 <HAL_RCC_OscConfig+0x1ac>
           }
         }
 
         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 800134a:	4b2d      	ldr	r3, [pc, #180]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 800134c:	681b      	ldr	r3, [r3, #0]
- 800134e:	f023 02f8 	bic.w	r2, r3, #248	; 0xf8
- 8001352:	687b      	ldr	r3, [r7, #4]
- 8001354:	691b      	ldr	r3, [r3, #16]
- 8001356:	00db      	lsls	r3, r3, #3
- 8001358:	4929      	ldr	r1, [pc, #164]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 800135a:	4313      	orrs	r3, r2
- 800135c:	600b      	str	r3, [r1, #0]
- 800135e:	e018      	b.n	8001392 <HAL_RCC_OscConfig+0x212>
+ 800137e:	4b2d      	ldr	r3, [pc, #180]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001380:	681b      	ldr	r3, [r3, #0]
+ 8001382:	f023 02f8 	bic.w	r2, r3, #248	; 0xf8
+ 8001386:	687b      	ldr	r3, [r7, #4]
+ 8001388:	691b      	ldr	r3, [r3, #16]
+ 800138a:	00db      	lsls	r3, r3, #3
+ 800138c:	4929      	ldr	r1, [pc, #164]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 800138e:	4313      	orrs	r3, r2
+ 8001390:	600b      	str	r3, [r1, #0]
+ 8001392:	e018      	b.n	80013c6 <HAL_RCC_OscConfig+0x212>
       }
       else
       {
         /* Disable the Internal High Speed oscillator (HSI). */
         __HAL_RCC_HSI_DISABLE();
- 8001360:	4b27      	ldr	r3, [pc, #156]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 8001362:	681b      	ldr	r3, [r3, #0]
- 8001364:	4a26      	ldr	r2, [pc, #152]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 8001366:	f023 0301 	bic.w	r3, r3, #1
- 800136a:	6013      	str	r3, [r2, #0]
+ 8001394:	4b27      	ldr	r3, [pc, #156]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001396:	681b      	ldr	r3, [r3, #0]
+ 8001398:	4a26      	ldr	r2, [pc, #152]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 800139a:	f023 0301 	bic.w	r3, r3, #1
+ 800139e:	6013      	str	r3, [r2, #0]
 
         /* Get Start Tick*/
         tickstart = HAL_GetTick();
- 800136c:	f7ff f936 	bl	80005dc <HAL_GetTick>
- 8001370:	6138      	str	r0, [r7, #16]
+ 80013a0:	f7ff f91c 	bl	80005dc <HAL_GetTick>
+ 80013a4:	6138      	str	r0, [r7, #16]
 
         /* Wait till HSI is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 8001372:	e008      	b.n	8001386 <HAL_RCC_OscConfig+0x206>
+ 80013a6:	e008      	b.n	80013ba <HAL_RCC_OscConfig+0x206>
         {
           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 8001374:	f7ff f932 	bl	80005dc <HAL_GetTick>
- 8001378:	4602      	mov	r2, r0
- 800137a:	693b      	ldr	r3, [r7, #16]
- 800137c:	1ad3      	subs	r3, r2, r3
- 800137e:	2b02      	cmp	r3, #2
- 8001380:	d901      	bls.n	8001386 <HAL_RCC_OscConfig+0x206>
+ 80013a8:	f7ff f918 	bl	80005dc <HAL_GetTick>
+ 80013ac:	4602      	mov	r2, r0
+ 80013ae:	693b      	ldr	r3, [r7, #16]
+ 80013b0:	1ad3      	subs	r3, r2, r3
+ 80013b2:	2b02      	cmp	r3, #2
+ 80013b4:	d901      	bls.n	80013ba <HAL_RCC_OscConfig+0x206>
           {
             return HAL_TIMEOUT;
- 8001382:	2303      	movs	r3, #3
- 8001384:	e166      	b.n	8001654 <HAL_RCC_OscConfig+0x4d4>
+ 80013b6:	2303      	movs	r3, #3
+ 80013b8:	e166      	b.n	8001688 <HAL_RCC_OscConfig+0x4d4>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 8001386:	4b1e      	ldr	r3, [pc, #120]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 8001388:	681b      	ldr	r3, [r3, #0]
- 800138a:	f003 0302 	and.w	r3, r3, #2
- 800138e:	2b00      	cmp	r3, #0
- 8001390:	d1f0      	bne.n	8001374 <HAL_RCC_OscConfig+0x1f4>
+ 80013ba:	4b1e      	ldr	r3, [pc, #120]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 80013bc:	681b      	ldr	r3, [r3, #0]
+ 80013be:	f003 0302 	and.w	r3, r3, #2
+ 80013c2:	2b00      	cmp	r3, #0
+ 80013c4:	d1f0      	bne.n	80013a8 <HAL_RCC_OscConfig+0x1f4>
         }
       }
     }
   }
   /*------------------------------ LSI Configuration -------------------------*/
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- 8001392:	687b      	ldr	r3, [r7, #4]
- 8001394:	681b      	ldr	r3, [r3, #0]
- 8001396:	f003 0308 	and.w	r3, r3, #8
- 800139a:	2b00      	cmp	r3, #0
- 800139c:	d038      	beq.n	8001410 <HAL_RCC_OscConfig+0x290>
+ 80013c6:	687b      	ldr	r3, [r7, #4]
+ 80013c8:	681b      	ldr	r3, [r3, #0]
+ 80013ca:	f003 0308 	and.w	r3, r3, #8
+ 80013ce:	2b00      	cmp	r3, #0
+ 80013d0:	d038      	beq.n	8001444 <HAL_RCC_OscConfig+0x290>
   {
     /* Check the parameters */
     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
 
     /* Check the LSI State */
     if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
- 800139e:	687b      	ldr	r3, [r7, #4]
- 80013a0:	695b      	ldr	r3, [r3, #20]
- 80013a2:	2b00      	cmp	r3, #0
- 80013a4:	d019      	beq.n	80013da <HAL_RCC_OscConfig+0x25a>
+ 80013d2:	687b      	ldr	r3, [r7, #4]
+ 80013d4:	695b      	ldr	r3, [r3, #20]
+ 80013d6:	2b00      	cmp	r3, #0
+ 80013d8:	d019      	beq.n	800140e <HAL_RCC_OscConfig+0x25a>
     {
       /* Enable the Internal Low Speed oscillator (LSI). */
       __HAL_RCC_LSI_ENABLE();
- 80013a6:	4b16      	ldr	r3, [pc, #88]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 80013a8:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 80013aa:	4a15      	ldr	r2, [pc, #84]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 80013ac:	f043 0301 	orr.w	r3, r3, #1
- 80013b0:	6753      	str	r3, [r2, #116]	; 0x74
+ 80013da:	4b16      	ldr	r3, [pc, #88]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 80013dc:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 80013de:	4a15      	ldr	r2, [pc, #84]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 80013e0:	f043 0301 	orr.w	r3, r3, #1
+ 80013e4:	6753      	str	r3, [r2, #116]	; 0x74
 
       /* Get Start Tick*/
       tickstart = HAL_GetTick();
- 80013b2:	f7ff f913 	bl	80005dc <HAL_GetTick>
- 80013b6:	6138      	str	r0, [r7, #16]
+ 80013e6:	f7ff f8f9 	bl	80005dc <HAL_GetTick>
+ 80013ea:	6138      	str	r0, [r7, #16]
 
       /* Wait till LSI is ready */
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 80013b8:	e008      	b.n	80013cc <HAL_RCC_OscConfig+0x24c>
+ 80013ec:	e008      	b.n	8001400 <HAL_RCC_OscConfig+0x24c>
       {
         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 80013ba:	f7ff f90f 	bl	80005dc <HAL_GetTick>
- 80013be:	4602      	mov	r2, r0
- 80013c0:	693b      	ldr	r3, [r7, #16]
- 80013c2:	1ad3      	subs	r3, r2, r3
- 80013c4:	2b02      	cmp	r3, #2
- 80013c6:	d901      	bls.n	80013cc <HAL_RCC_OscConfig+0x24c>
+ 80013ee:	f7ff f8f5 	bl	80005dc <HAL_GetTick>
+ 80013f2:	4602      	mov	r2, r0
+ 80013f4:	693b      	ldr	r3, [r7, #16]
+ 80013f6:	1ad3      	subs	r3, r2, r3
+ 80013f8:	2b02      	cmp	r3, #2
+ 80013fa:	d901      	bls.n	8001400 <HAL_RCC_OscConfig+0x24c>
         {
           return HAL_TIMEOUT;
- 80013c8:	2303      	movs	r3, #3
- 80013ca:	e143      	b.n	8001654 <HAL_RCC_OscConfig+0x4d4>
+ 80013fc:	2303      	movs	r3, #3
+ 80013fe:	e143      	b.n	8001688 <HAL_RCC_OscConfig+0x4d4>
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 80013cc:	4b0c      	ldr	r3, [pc, #48]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 80013ce:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 80013d0:	f003 0302 	and.w	r3, r3, #2
- 80013d4:	2b00      	cmp	r3, #0
- 80013d6:	d0f0      	beq.n	80013ba <HAL_RCC_OscConfig+0x23a>
- 80013d8:	e01a      	b.n	8001410 <HAL_RCC_OscConfig+0x290>
+ 8001400:	4b0c      	ldr	r3, [pc, #48]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001402:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 8001404:	f003 0302 	and.w	r3, r3, #2
+ 8001408:	2b00      	cmp	r3, #0
+ 800140a:	d0f0      	beq.n	80013ee <HAL_RCC_OscConfig+0x23a>
+ 800140c:	e01a      	b.n	8001444 <HAL_RCC_OscConfig+0x290>
       }
     }
     else
     {
       /* Disable the Internal Low Speed oscillator (LSI). */
       __HAL_RCC_LSI_DISABLE();
- 80013da:	4b09      	ldr	r3, [pc, #36]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 80013dc:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 80013de:	4a08      	ldr	r2, [pc, #32]	; (8001400 <HAL_RCC_OscConfig+0x280>)
- 80013e0:	f023 0301 	bic.w	r3, r3, #1
- 80013e4:	6753      	str	r3, [r2, #116]	; 0x74
+ 800140e:	4b09      	ldr	r3, [pc, #36]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001410:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 8001412:	4a08      	ldr	r2, [pc, #32]	; (8001434 <HAL_RCC_OscConfig+0x280>)
+ 8001414:	f023 0301 	bic.w	r3, r3, #1
+ 8001418:	6753      	str	r3, [r2, #116]	; 0x74
 
       /* Get Start Tick*/
       tickstart = HAL_GetTick();
- 80013e6:	f7ff f8f9 	bl	80005dc <HAL_GetTick>
- 80013ea:	6138      	str	r0, [r7, #16]
+ 800141a:	f7ff f8df 	bl	80005dc <HAL_GetTick>
+ 800141e:	6138      	str	r0, [r7, #16]
 
       /* Wait till LSI is ready */
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 80013ec:	e00a      	b.n	8001404 <HAL_RCC_OscConfig+0x284>
+ 8001420:	e00a      	b.n	8001438 <HAL_RCC_OscConfig+0x284>
       {
         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 80013ee:	f7ff f8f5 	bl	80005dc <HAL_GetTick>
- 80013f2:	4602      	mov	r2, r0
- 80013f4:	693b      	ldr	r3, [r7, #16]
- 80013f6:	1ad3      	subs	r3, r2, r3
- 80013f8:	2b02      	cmp	r3, #2
- 80013fa:	d903      	bls.n	8001404 <HAL_RCC_OscConfig+0x284>
+ 8001422:	f7ff f8db 	bl	80005dc <HAL_GetTick>
+ 8001426:	4602      	mov	r2, r0
+ 8001428:	693b      	ldr	r3, [r7, #16]
+ 800142a:	1ad3      	subs	r3, r2, r3
+ 800142c:	2b02      	cmp	r3, #2
+ 800142e:	d903      	bls.n	8001438 <HAL_RCC_OscConfig+0x284>
         {
           return HAL_TIMEOUT;
- 80013fc:	2303      	movs	r3, #3
- 80013fe:	e129      	b.n	8001654 <HAL_RCC_OscConfig+0x4d4>
- 8001400:	40023800 	.word	0x40023800
+ 8001430:	2303      	movs	r3, #3
+ 8001432:	e129      	b.n	8001688 <HAL_RCC_OscConfig+0x4d4>
+ 8001434:	40023800 	.word	0x40023800
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 8001404:	4b95      	ldr	r3, [pc, #596]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 8001406:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 8001408:	f003 0302 	and.w	r3, r3, #2
- 800140c:	2b00      	cmp	r3, #0
- 800140e:	d1ee      	bne.n	80013ee <HAL_RCC_OscConfig+0x26e>
+ 8001438:	4b95      	ldr	r3, [pc, #596]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 800143a:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 800143c:	f003 0302 	and.w	r3, r3, #2
+ 8001440:	2b00      	cmp	r3, #0
+ 8001442:	d1ee      	bne.n	8001422 <HAL_RCC_OscConfig+0x26e>
         }
       }
     }
   }
   /*------------------------------ LSE Configuration -------------------------*/
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- 8001410:	687b      	ldr	r3, [r7, #4]
- 8001412:	681b      	ldr	r3, [r3, #0]
- 8001414:	f003 0304 	and.w	r3, r3, #4
- 8001418:	2b00      	cmp	r3, #0
- 800141a:	f000 80a4 	beq.w	8001566 <HAL_RCC_OscConfig+0x3e6>
+ 8001444:	687b      	ldr	r3, [r7, #4]
+ 8001446:	681b      	ldr	r3, [r3, #0]
+ 8001448:	f003 0304 	and.w	r3, r3, #4
+ 800144c:	2b00      	cmp	r3, #0
+ 800144e:	f000 80a4 	beq.w	800159a <HAL_RCC_OscConfig+0x3e6>
     /* Check the parameters */
     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
 
     /* Update LSE configuration in Backup Domain control register    */
     /* Requires to enable write access to Backup Domain of necessary */
     if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- 800141e:	4b8f      	ldr	r3, [pc, #572]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 8001420:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 8001422:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
- 8001426:	2b00      	cmp	r3, #0
- 8001428:	d10d      	bne.n	8001446 <HAL_RCC_OscConfig+0x2c6>
+ 8001452:	4b8f      	ldr	r3, [pc, #572]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 8001454:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8001456:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
+ 800145a:	2b00      	cmp	r3, #0
+ 800145c:	d10d      	bne.n	800147a <HAL_RCC_OscConfig+0x2c6>
     {
       /* Enable Power Clock*/
       __HAL_RCC_PWR_CLK_ENABLE();
- 800142a:	4b8c      	ldr	r3, [pc, #560]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 800142c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 800142e:	4a8b      	ldr	r2, [pc, #556]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 8001430:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
- 8001434:	6413      	str	r3, [r2, #64]	; 0x40
- 8001436:	4b89      	ldr	r3, [pc, #548]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 8001438:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 800143a:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
- 800143e:	60fb      	str	r3, [r7, #12]
- 8001440:	68fb      	ldr	r3, [r7, #12]
+ 800145e:	4b8c      	ldr	r3, [pc, #560]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 8001460:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8001462:	4a8b      	ldr	r2, [pc, #556]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 8001464:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
+ 8001468:	6413      	str	r3, [r2, #64]	; 0x40
+ 800146a:	4b89      	ldr	r3, [pc, #548]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 800146c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800146e:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
+ 8001472:	60fb      	str	r3, [r7, #12]
+ 8001474:	68fb      	ldr	r3, [r7, #12]
       pwrclkchanged = SET;
- 8001442:	2301      	movs	r3, #1
- 8001444:	75fb      	strb	r3, [r7, #23]
+ 8001476:	2301      	movs	r3, #1
+ 8001478:	75fb      	strb	r3, [r7, #23]
     }
 
     if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 8001446:	4b86      	ldr	r3, [pc, #536]	; (8001660 <HAL_RCC_OscConfig+0x4e0>)
- 8001448:	681b      	ldr	r3, [r3, #0]
- 800144a:	f403 7380 	and.w	r3, r3, #256	; 0x100
- 800144e:	2b00      	cmp	r3, #0
- 8001450:	d118      	bne.n	8001484 <HAL_RCC_OscConfig+0x304>
+ 800147a:	4b86      	ldr	r3, [pc, #536]	; (8001694 <HAL_RCC_OscConfig+0x4e0>)
+ 800147c:	681b      	ldr	r3, [r3, #0]
+ 800147e:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 8001482:	2b00      	cmp	r3, #0
+ 8001484:	d118      	bne.n	80014b8 <HAL_RCC_OscConfig+0x304>
     {
       /* Enable write access to Backup domain */
       PWR->CR1 |= PWR_CR1_DBP;
- 8001452:	4b83      	ldr	r3, [pc, #524]	; (8001660 <HAL_RCC_OscConfig+0x4e0>)
- 8001454:	681b      	ldr	r3, [r3, #0]
- 8001456:	4a82      	ldr	r2, [pc, #520]	; (8001660 <HAL_RCC_OscConfig+0x4e0>)
- 8001458:	f443 7380 	orr.w	r3, r3, #256	; 0x100
- 800145c:	6013      	str	r3, [r2, #0]
+ 8001486:	4b83      	ldr	r3, [pc, #524]	; (8001694 <HAL_RCC_OscConfig+0x4e0>)
+ 8001488:	681b      	ldr	r3, [r3, #0]
+ 800148a:	4a82      	ldr	r2, [pc, #520]	; (8001694 <HAL_RCC_OscConfig+0x4e0>)
+ 800148c:	f443 7380 	orr.w	r3, r3, #256	; 0x100
+ 8001490:	6013      	str	r3, [r2, #0]
 
       /* Wait for Backup domain Write protection disable */
       tickstart = HAL_GetTick();
- 800145e:	f7ff f8bd 	bl	80005dc <HAL_GetTick>
- 8001462:	6138      	str	r0, [r7, #16]
+ 8001492:	f7ff f8a3 	bl	80005dc <HAL_GetTick>
+ 8001496:	6138      	str	r0, [r7, #16]
 
       while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 8001464:	e008      	b.n	8001478 <HAL_RCC_OscConfig+0x2f8>
+ 8001498:	e008      	b.n	80014ac <HAL_RCC_OscConfig+0x2f8>
       {
         if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
- 8001466:	f7ff f8b9 	bl	80005dc <HAL_GetTick>
- 800146a:	4602      	mov	r2, r0
- 800146c:	693b      	ldr	r3, [r7, #16]
- 800146e:	1ad3      	subs	r3, r2, r3
- 8001470:	2b64      	cmp	r3, #100	; 0x64
- 8001472:	d901      	bls.n	8001478 <HAL_RCC_OscConfig+0x2f8>
+ 800149a:	f7ff f89f 	bl	80005dc <HAL_GetTick>
+ 800149e:	4602      	mov	r2, r0
+ 80014a0:	693b      	ldr	r3, [r7, #16]
+ 80014a2:	1ad3      	subs	r3, r2, r3
+ 80014a4:	2b64      	cmp	r3, #100	; 0x64
+ 80014a6:	d901      	bls.n	80014ac <HAL_RCC_OscConfig+0x2f8>
         {
           return HAL_TIMEOUT;
- 8001474:	2303      	movs	r3, #3
- 8001476:	e0ed      	b.n	8001654 <HAL_RCC_OscConfig+0x4d4>
+ 80014a8:	2303      	movs	r3, #3
+ 80014aa:	e0ed      	b.n	8001688 <HAL_RCC_OscConfig+0x4d4>
       while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 8001478:	4b79      	ldr	r3, [pc, #484]	; (8001660 <HAL_RCC_OscConfig+0x4e0>)
- 800147a:	681b      	ldr	r3, [r3, #0]
- 800147c:	f403 7380 	and.w	r3, r3, #256	; 0x100
- 8001480:	2b00      	cmp	r3, #0
- 8001482:	d0f0      	beq.n	8001466 <HAL_RCC_OscConfig+0x2e6>
+ 80014ac:	4b79      	ldr	r3, [pc, #484]	; (8001694 <HAL_RCC_OscConfig+0x4e0>)
+ 80014ae:	681b      	ldr	r3, [r3, #0]
+ 80014b0:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 80014b4:	2b00      	cmp	r3, #0
+ 80014b6:	d0f0      	beq.n	800149a <HAL_RCC_OscConfig+0x2e6>
         }
       }
     }
 
     /* Set the new LSE configuration -----------------------------------------*/
     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- 8001484:	687b      	ldr	r3, [r7, #4]
- 8001486:	689b      	ldr	r3, [r3, #8]
- 8001488:	2b01      	cmp	r3, #1
- 800148a:	d106      	bne.n	800149a <HAL_RCC_OscConfig+0x31a>
- 800148c:	4b73      	ldr	r3, [pc, #460]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 800148e:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8001490:	4a72      	ldr	r2, [pc, #456]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 8001492:	f043 0301 	orr.w	r3, r3, #1
- 8001496:	6713      	str	r3, [r2, #112]	; 0x70
- 8001498:	e02d      	b.n	80014f6 <HAL_RCC_OscConfig+0x376>
- 800149a:	687b      	ldr	r3, [r7, #4]
- 800149c:	689b      	ldr	r3, [r3, #8]
- 800149e:	2b00      	cmp	r3, #0
- 80014a0:	d10c      	bne.n	80014bc <HAL_RCC_OscConfig+0x33c>
- 80014a2:	4b6e      	ldr	r3, [pc, #440]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 80014a4:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 80014a6:	4a6d      	ldr	r2, [pc, #436]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 80014a8:	f023 0301 	bic.w	r3, r3, #1
- 80014ac:	6713      	str	r3, [r2, #112]	; 0x70
- 80014ae:	4b6b      	ldr	r3, [pc, #428]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 80014b0:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 80014b2:	4a6a      	ldr	r2, [pc, #424]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 80014b4:	f023 0304 	bic.w	r3, r3, #4
- 80014b8:	6713      	str	r3, [r2, #112]	; 0x70
- 80014ba:	e01c      	b.n	80014f6 <HAL_RCC_OscConfig+0x376>
- 80014bc:	687b      	ldr	r3, [r7, #4]
- 80014be:	689b      	ldr	r3, [r3, #8]
- 80014c0:	2b05      	cmp	r3, #5
- 80014c2:	d10c      	bne.n	80014de <HAL_RCC_OscConfig+0x35e>
- 80014c4:	4b65      	ldr	r3, [pc, #404]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 80014c6:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 80014c8:	4a64      	ldr	r2, [pc, #400]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 80014ca:	f043 0304 	orr.w	r3, r3, #4
- 80014ce:	6713      	str	r3, [r2, #112]	; 0x70
- 80014d0:	4b62      	ldr	r3, [pc, #392]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 80014d2:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 80014d4:	4a61      	ldr	r2, [pc, #388]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 80014d6:	f043 0301 	orr.w	r3, r3, #1
- 80014da:	6713      	str	r3, [r2, #112]	; 0x70
- 80014dc:	e00b      	b.n	80014f6 <HAL_RCC_OscConfig+0x376>
- 80014de:	4b5f      	ldr	r3, [pc, #380]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 80014e0:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 80014e2:	4a5e      	ldr	r2, [pc, #376]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 80014e4:	f023 0301 	bic.w	r3, r3, #1
- 80014e8:	6713      	str	r3, [r2, #112]	; 0x70
- 80014ea:	4b5c      	ldr	r3, [pc, #368]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 80014ec:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 80014ee:	4a5b      	ldr	r2, [pc, #364]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 80014f0:	f023 0304 	bic.w	r3, r3, #4
- 80014f4:	6713      	str	r3, [r2, #112]	; 0x70
+ 80014b8:	687b      	ldr	r3, [r7, #4]
+ 80014ba:	689b      	ldr	r3, [r3, #8]
+ 80014bc:	2b01      	cmp	r3, #1
+ 80014be:	d106      	bne.n	80014ce <HAL_RCC_OscConfig+0x31a>
+ 80014c0:	4b73      	ldr	r3, [pc, #460]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 80014c2:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 80014c4:	4a72      	ldr	r2, [pc, #456]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 80014c6:	f043 0301 	orr.w	r3, r3, #1
+ 80014ca:	6713      	str	r3, [r2, #112]	; 0x70
+ 80014cc:	e02d      	b.n	800152a <HAL_RCC_OscConfig+0x376>
+ 80014ce:	687b      	ldr	r3, [r7, #4]
+ 80014d0:	689b      	ldr	r3, [r3, #8]
+ 80014d2:	2b00      	cmp	r3, #0
+ 80014d4:	d10c      	bne.n	80014f0 <HAL_RCC_OscConfig+0x33c>
+ 80014d6:	4b6e      	ldr	r3, [pc, #440]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 80014d8:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 80014da:	4a6d      	ldr	r2, [pc, #436]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 80014dc:	f023 0301 	bic.w	r3, r3, #1
+ 80014e0:	6713      	str	r3, [r2, #112]	; 0x70
+ 80014e2:	4b6b      	ldr	r3, [pc, #428]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 80014e4:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 80014e6:	4a6a      	ldr	r2, [pc, #424]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 80014e8:	f023 0304 	bic.w	r3, r3, #4
+ 80014ec:	6713      	str	r3, [r2, #112]	; 0x70
+ 80014ee:	e01c      	b.n	800152a <HAL_RCC_OscConfig+0x376>
+ 80014f0:	687b      	ldr	r3, [r7, #4]
+ 80014f2:	689b      	ldr	r3, [r3, #8]
+ 80014f4:	2b05      	cmp	r3, #5
+ 80014f6:	d10c      	bne.n	8001512 <HAL_RCC_OscConfig+0x35e>
+ 80014f8:	4b65      	ldr	r3, [pc, #404]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 80014fa:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 80014fc:	4a64      	ldr	r2, [pc, #400]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 80014fe:	f043 0304 	orr.w	r3, r3, #4
+ 8001502:	6713      	str	r3, [r2, #112]	; 0x70
+ 8001504:	4b62      	ldr	r3, [pc, #392]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 8001506:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8001508:	4a61      	ldr	r2, [pc, #388]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 800150a:	f043 0301 	orr.w	r3, r3, #1
+ 800150e:	6713      	str	r3, [r2, #112]	; 0x70
+ 8001510:	e00b      	b.n	800152a <HAL_RCC_OscConfig+0x376>
+ 8001512:	4b5f      	ldr	r3, [pc, #380]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 8001514:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8001516:	4a5e      	ldr	r2, [pc, #376]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 8001518:	f023 0301 	bic.w	r3, r3, #1
+ 800151c:	6713      	str	r3, [r2, #112]	; 0x70
+ 800151e:	4b5c      	ldr	r3, [pc, #368]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 8001520:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8001522:	4a5b      	ldr	r2, [pc, #364]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 8001524:	f023 0304 	bic.w	r3, r3, #4
+ 8001528:	6713      	str	r3, [r2, #112]	; 0x70
     /* Check the LSE State */
     if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
- 80014f6:	687b      	ldr	r3, [r7, #4]
- 80014f8:	689b      	ldr	r3, [r3, #8]
- 80014fa:	2b00      	cmp	r3, #0
- 80014fc:	d015      	beq.n	800152a <HAL_RCC_OscConfig+0x3aa>
+ 800152a:	687b      	ldr	r3, [r7, #4]
+ 800152c:	689b      	ldr	r3, [r3, #8]
+ 800152e:	2b00      	cmp	r3, #0
+ 8001530:	d015      	beq.n	800155e <HAL_RCC_OscConfig+0x3aa>
     {
       /* Get Start Tick*/
       tickstart = HAL_GetTick();
- 80014fe:	f7ff f86d 	bl	80005dc <HAL_GetTick>
- 8001502:	6138      	str	r0, [r7, #16]
+ 8001532:	f7ff f853 	bl	80005dc <HAL_GetTick>
+ 8001536:	6138      	str	r0, [r7, #16]
 
       /* Wait till LSE is ready */
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8001504:	e00a      	b.n	800151c <HAL_RCC_OscConfig+0x39c>
+ 8001538:	e00a      	b.n	8001550 <HAL_RCC_OscConfig+0x39c>
       {
         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8001506:	f7ff f869 	bl	80005dc <HAL_GetTick>
- 800150a:	4602      	mov	r2, r0
- 800150c:	693b      	ldr	r3, [r7, #16]
- 800150e:	1ad3      	subs	r3, r2, r3
- 8001510:	f241 3288 	movw	r2, #5000	; 0x1388
- 8001514:	4293      	cmp	r3, r2
- 8001516:	d901      	bls.n	800151c <HAL_RCC_OscConfig+0x39c>
+ 800153a:	f7ff f84f 	bl	80005dc <HAL_GetTick>
+ 800153e:	4602      	mov	r2, r0
+ 8001540:	693b      	ldr	r3, [r7, #16]
+ 8001542:	1ad3      	subs	r3, r2, r3
+ 8001544:	f241 3288 	movw	r2, #5000	; 0x1388
+ 8001548:	4293      	cmp	r3, r2
+ 800154a:	d901      	bls.n	8001550 <HAL_RCC_OscConfig+0x39c>
         {
           return HAL_TIMEOUT;
- 8001518:	2303      	movs	r3, #3
- 800151a:	e09b      	b.n	8001654 <HAL_RCC_OscConfig+0x4d4>
+ 800154c:	2303      	movs	r3, #3
+ 800154e:	e09b      	b.n	8001688 <HAL_RCC_OscConfig+0x4d4>
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 800151c:	4b4f      	ldr	r3, [pc, #316]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 800151e:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8001520:	f003 0302 	and.w	r3, r3, #2
- 8001524:	2b00      	cmp	r3, #0
- 8001526:	d0ee      	beq.n	8001506 <HAL_RCC_OscConfig+0x386>
- 8001528:	e014      	b.n	8001554 <HAL_RCC_OscConfig+0x3d4>
+ 8001550:	4b4f      	ldr	r3, [pc, #316]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 8001552:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8001554:	f003 0302 	and.w	r3, r3, #2
+ 8001558:	2b00      	cmp	r3, #0
+ 800155a:	d0ee      	beq.n	800153a <HAL_RCC_OscConfig+0x386>
+ 800155c:	e014      	b.n	8001588 <HAL_RCC_OscConfig+0x3d4>
       }
     }
     else
     {
       /* Get Start Tick*/
       tickstart = HAL_GetTick();
- 800152a:	f7ff f857 	bl	80005dc <HAL_GetTick>
- 800152e:	6138      	str	r0, [r7, #16]
+ 800155e:	f7ff f83d 	bl	80005dc <HAL_GetTick>
+ 8001562:	6138      	str	r0, [r7, #16]
 
       /* Wait till LSE is ready */
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 8001530:	e00a      	b.n	8001548 <HAL_RCC_OscConfig+0x3c8>
+ 8001564:	e00a      	b.n	800157c <HAL_RCC_OscConfig+0x3c8>
       {
         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8001532:	f7ff f853 	bl	80005dc <HAL_GetTick>
- 8001536:	4602      	mov	r2, r0
- 8001538:	693b      	ldr	r3, [r7, #16]
- 800153a:	1ad3      	subs	r3, r2, r3
- 800153c:	f241 3288 	movw	r2, #5000	; 0x1388
- 8001540:	4293      	cmp	r3, r2
- 8001542:	d901      	bls.n	8001548 <HAL_RCC_OscConfig+0x3c8>
+ 8001566:	f7ff f839 	bl	80005dc <HAL_GetTick>
+ 800156a:	4602      	mov	r2, r0
+ 800156c:	693b      	ldr	r3, [r7, #16]
+ 800156e:	1ad3      	subs	r3, r2, r3
+ 8001570:	f241 3288 	movw	r2, #5000	; 0x1388
+ 8001574:	4293      	cmp	r3, r2
+ 8001576:	d901      	bls.n	800157c <HAL_RCC_OscConfig+0x3c8>
         {
           return HAL_TIMEOUT;
- 8001544:	2303      	movs	r3, #3
- 8001546:	e085      	b.n	8001654 <HAL_RCC_OscConfig+0x4d4>
+ 8001578:	2303      	movs	r3, #3
+ 800157a:	e085      	b.n	8001688 <HAL_RCC_OscConfig+0x4d4>
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 8001548:	4b44      	ldr	r3, [pc, #272]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 800154a:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 800154c:	f003 0302 	and.w	r3, r3, #2
- 8001550:	2b00      	cmp	r3, #0
- 8001552:	d1ee      	bne.n	8001532 <HAL_RCC_OscConfig+0x3b2>
+ 800157c:	4b44      	ldr	r3, [pc, #272]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 800157e:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8001580:	f003 0302 	and.w	r3, r3, #2
+ 8001584:	2b00      	cmp	r3, #0
+ 8001586:	d1ee      	bne.n	8001566 <HAL_RCC_OscConfig+0x3b2>
         }
       }
     }
 
     /* Restore clock configuration if changed */
     if(pwrclkchanged == SET)
- 8001554:	7dfb      	ldrb	r3, [r7, #23]
- 8001556:	2b01      	cmp	r3, #1
- 8001558:	d105      	bne.n	8001566 <HAL_RCC_OscConfig+0x3e6>
+ 8001588:	7dfb      	ldrb	r3, [r7, #23]
+ 800158a:	2b01      	cmp	r3, #1
+ 800158c:	d105      	bne.n	800159a <HAL_RCC_OscConfig+0x3e6>
     {
       __HAL_RCC_PWR_CLK_DISABLE();
- 800155a:	4b40      	ldr	r3, [pc, #256]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 800155c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 800155e:	4a3f      	ldr	r2, [pc, #252]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 8001560:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
- 8001564:	6413      	str	r3, [r2, #64]	; 0x40
+ 800158e:	4b40      	ldr	r3, [pc, #256]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 8001590:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8001592:	4a3f      	ldr	r2, [pc, #252]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 8001594:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
+ 8001598:	6413      	str	r3, [r2, #64]	; 0x40
     }
   }
   /*-------------------------------- PLL Configuration -----------------------*/
   /* Check the parameters */
   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- 8001566:	687b      	ldr	r3, [r7, #4]
- 8001568:	699b      	ldr	r3, [r3, #24]
- 800156a:	2b00      	cmp	r3, #0
- 800156c:	d071      	beq.n	8001652 <HAL_RCC_OscConfig+0x4d2>
+ 800159a:	687b      	ldr	r3, [r7, #4]
+ 800159c:	699b      	ldr	r3, [r3, #24]
+ 800159e:	2b00      	cmp	r3, #0
+ 80015a0:	d071      	beq.n	8001686 <HAL_RCC_OscConfig+0x4d2>
   {
     /* Check if the PLL is used as system clock or not */
     if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- 800156e:	4b3b      	ldr	r3, [pc, #236]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 8001570:	689b      	ldr	r3, [r3, #8]
- 8001572:	f003 030c 	and.w	r3, r3, #12
- 8001576:	2b08      	cmp	r3, #8
- 8001578:	d069      	beq.n	800164e <HAL_RCC_OscConfig+0x4ce>
+ 80015a2:	4b3b      	ldr	r3, [pc, #236]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 80015a4:	689b      	ldr	r3, [r3, #8]
+ 80015a6:	f003 030c 	and.w	r3, r3, #12
+ 80015aa:	2b08      	cmp	r3, #8
+ 80015ac:	d069      	beq.n	8001682 <HAL_RCC_OscConfig+0x4ce>
     {
       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- 800157a:	687b      	ldr	r3, [r7, #4]
- 800157c:	699b      	ldr	r3, [r3, #24]
- 800157e:	2b02      	cmp	r3, #2
- 8001580:	d14b      	bne.n	800161a <HAL_RCC_OscConfig+0x49a>
+ 80015ae:	687b      	ldr	r3, [r7, #4]
+ 80015b0:	699b      	ldr	r3, [r3, #24]
+ 80015b2:	2b02      	cmp	r3, #2
+ 80015b4:	d14b      	bne.n	800164e <HAL_RCC_OscConfig+0x49a>
 #if defined (RCC_PLLCFGR_PLLR)
         assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
 #endif
 
         /* Disable the main PLL. */
         __HAL_RCC_PLL_DISABLE();
- 8001582:	4b36      	ldr	r3, [pc, #216]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 8001584:	681b      	ldr	r3, [r3, #0]
- 8001586:	4a35      	ldr	r2, [pc, #212]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 8001588:	f023 7380 	bic.w	r3, r3, #16777216	; 0x1000000
- 800158c:	6013      	str	r3, [r2, #0]
+ 80015b6:	4b36      	ldr	r3, [pc, #216]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 80015b8:	681b      	ldr	r3, [r3, #0]
+ 80015ba:	4a35      	ldr	r2, [pc, #212]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 80015bc:	f023 7380 	bic.w	r3, r3, #16777216	; 0x1000000
+ 80015c0:	6013      	str	r3, [r2, #0]
 
         /* Get Start Tick*/
         tickstart = HAL_GetTick();
- 800158e:	f7ff f825 	bl	80005dc <HAL_GetTick>
- 8001592:	6138      	str	r0, [r7, #16]
+ 80015c2:	f7ff f80b 	bl	80005dc <HAL_GetTick>
+ 80015c6:	6138      	str	r0, [r7, #16]
 
         /* Wait till PLL is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8001594:	e008      	b.n	80015a8 <HAL_RCC_OscConfig+0x428>
+ 80015c8:	e008      	b.n	80015dc <HAL_RCC_OscConfig+0x428>
         {
           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8001596:	f7ff f821 	bl	80005dc <HAL_GetTick>
- 800159a:	4602      	mov	r2, r0
- 800159c:	693b      	ldr	r3, [r7, #16]
- 800159e:	1ad3      	subs	r3, r2, r3
- 80015a0:	2b02      	cmp	r3, #2
- 80015a2:	d901      	bls.n	80015a8 <HAL_RCC_OscConfig+0x428>
+ 80015ca:	f7ff f807 	bl	80005dc <HAL_GetTick>
+ 80015ce:	4602      	mov	r2, r0
+ 80015d0:	693b      	ldr	r3, [r7, #16]
+ 80015d2:	1ad3      	subs	r3, r2, r3
+ 80015d4:	2b02      	cmp	r3, #2
+ 80015d6:	d901      	bls.n	80015dc <HAL_RCC_OscConfig+0x428>
           {
             return HAL_TIMEOUT;
- 80015a4:	2303      	movs	r3, #3
- 80015a6:	e055      	b.n	8001654 <HAL_RCC_OscConfig+0x4d4>
+ 80015d8:	2303      	movs	r3, #3
+ 80015da:	e055      	b.n	8001688 <HAL_RCC_OscConfig+0x4d4>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 80015a8:	4b2c      	ldr	r3, [pc, #176]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 80015aa:	681b      	ldr	r3, [r3, #0]
- 80015ac:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
- 80015b0:	2b00      	cmp	r3, #0
- 80015b2:	d1f0      	bne.n	8001596 <HAL_RCC_OscConfig+0x416>
+ 80015dc:	4b2c      	ldr	r3, [pc, #176]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 80015de:	681b      	ldr	r3, [r3, #0]
+ 80015e0:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 80015e4:	2b00      	cmp	r3, #0
+ 80015e6:	d1f0      	bne.n	80015ca <HAL_RCC_OscConfig+0x416>
           }
         }
 
         /* Configure the main PLL clock source, multiplication and division factors. */
 #if defined (RCC_PLLCFGR_PLLR)
         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- 80015b4:	687b      	ldr	r3, [r7, #4]
- 80015b6:	69da      	ldr	r2, [r3, #28]
- 80015b8:	687b      	ldr	r3, [r7, #4]
- 80015ba:	6a1b      	ldr	r3, [r3, #32]
- 80015bc:	431a      	orrs	r2, r3
- 80015be:	687b      	ldr	r3, [r7, #4]
- 80015c0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 80015c2:	019b      	lsls	r3, r3, #6
- 80015c4:	431a      	orrs	r2, r3
- 80015c6:	687b      	ldr	r3, [r7, #4]
- 80015c8:	6a9b      	ldr	r3, [r3, #40]	; 0x28
- 80015ca:	085b      	lsrs	r3, r3, #1
- 80015cc:	3b01      	subs	r3, #1
- 80015ce:	041b      	lsls	r3, r3, #16
- 80015d0:	431a      	orrs	r2, r3
- 80015d2:	687b      	ldr	r3, [r7, #4]
- 80015d4:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 80015d6:	061b      	lsls	r3, r3, #24
- 80015d8:	431a      	orrs	r2, r3
- 80015da:	687b      	ldr	r3, [r7, #4]
- 80015dc:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 80015de:	071b      	lsls	r3, r3, #28
- 80015e0:	491e      	ldr	r1, [pc, #120]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 80015e2:	4313      	orrs	r3, r2
- 80015e4:	604b      	str	r3, [r1, #4]
+ 80015e8:	687b      	ldr	r3, [r7, #4]
+ 80015ea:	69da      	ldr	r2, [r3, #28]
+ 80015ec:	687b      	ldr	r3, [r7, #4]
+ 80015ee:	6a1b      	ldr	r3, [r3, #32]
+ 80015f0:	431a      	orrs	r2, r3
+ 80015f2:	687b      	ldr	r3, [r7, #4]
+ 80015f4:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80015f6:	019b      	lsls	r3, r3, #6
+ 80015f8:	431a      	orrs	r2, r3
+ 80015fa:	687b      	ldr	r3, [r7, #4]
+ 80015fc:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 80015fe:	085b      	lsrs	r3, r3, #1
+ 8001600:	3b01      	subs	r3, #1
+ 8001602:	041b      	lsls	r3, r3, #16
+ 8001604:	431a      	orrs	r2, r3
+ 8001606:	687b      	ldr	r3, [r7, #4]
+ 8001608:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800160a:	061b      	lsls	r3, r3, #24
+ 800160c:	431a      	orrs	r2, r3
+ 800160e:	687b      	ldr	r3, [r7, #4]
+ 8001610:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8001612:	071b      	lsls	r3, r3, #28
+ 8001614:	491e      	ldr	r1, [pc, #120]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 8001616:	4313      	orrs	r3, r2
+ 8001618:	604b      	str	r3, [r1, #4]
                              RCC_OscInitStruct->PLL.PLLP,
                              RCC_OscInitStruct->PLL.PLLQ);
 #endif
 
         /* Enable the main PLL. */
         __HAL_RCC_PLL_ENABLE();
- 80015e6:	4b1d      	ldr	r3, [pc, #116]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 80015e8:	681b      	ldr	r3, [r3, #0]
- 80015ea:	4a1c      	ldr	r2, [pc, #112]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 80015ec:	f043 7380 	orr.w	r3, r3, #16777216	; 0x1000000
- 80015f0:	6013      	str	r3, [r2, #0]
+ 800161a:	4b1d      	ldr	r3, [pc, #116]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 800161c:	681b      	ldr	r3, [r3, #0]
+ 800161e:	4a1c      	ldr	r2, [pc, #112]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 8001620:	f043 7380 	orr.w	r3, r3, #16777216	; 0x1000000
+ 8001624:	6013      	str	r3, [r2, #0]
 
         /* Get Start Tick*/
         tickstart = HAL_GetTick();
- 80015f2:	f7fe fff3 	bl	80005dc <HAL_GetTick>
- 80015f6:	6138      	str	r0, [r7, #16]
+ 8001626:	f7fe ffd9 	bl	80005dc <HAL_GetTick>
+ 800162a:	6138      	str	r0, [r7, #16]
 
         /* Wait till PLL is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 80015f8:	e008      	b.n	800160c <HAL_RCC_OscConfig+0x48c>
+ 800162c:	e008      	b.n	8001640 <HAL_RCC_OscConfig+0x48c>
         {
           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 80015fa:	f7fe ffef 	bl	80005dc <HAL_GetTick>
- 80015fe:	4602      	mov	r2, r0
- 8001600:	693b      	ldr	r3, [r7, #16]
- 8001602:	1ad3      	subs	r3, r2, r3
- 8001604:	2b02      	cmp	r3, #2
- 8001606:	d901      	bls.n	800160c <HAL_RCC_OscConfig+0x48c>
+ 800162e:	f7fe ffd5 	bl	80005dc <HAL_GetTick>
+ 8001632:	4602      	mov	r2, r0
+ 8001634:	693b      	ldr	r3, [r7, #16]
+ 8001636:	1ad3      	subs	r3, r2, r3
+ 8001638:	2b02      	cmp	r3, #2
+ 800163a:	d901      	bls.n	8001640 <HAL_RCC_OscConfig+0x48c>
           {
             return HAL_TIMEOUT;
- 8001608:	2303      	movs	r3, #3
- 800160a:	e023      	b.n	8001654 <HAL_RCC_OscConfig+0x4d4>
+ 800163c:	2303      	movs	r3, #3
+ 800163e:	e023      	b.n	8001688 <HAL_RCC_OscConfig+0x4d4>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 800160c:	4b13      	ldr	r3, [pc, #76]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 800160e:	681b      	ldr	r3, [r3, #0]
- 8001610:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
- 8001614:	2b00      	cmp	r3, #0
- 8001616:	d0f0      	beq.n	80015fa <HAL_RCC_OscConfig+0x47a>
- 8001618:	e01b      	b.n	8001652 <HAL_RCC_OscConfig+0x4d2>
+ 8001640:	4b13      	ldr	r3, [pc, #76]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 8001642:	681b      	ldr	r3, [r3, #0]
+ 8001644:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 8001648:	2b00      	cmp	r3, #0
+ 800164a:	d0f0      	beq.n	800162e <HAL_RCC_OscConfig+0x47a>
+ 800164c:	e01b      	b.n	8001686 <HAL_RCC_OscConfig+0x4d2>
         }
       }
       else
       {
         /* Disable the main PLL. */
         __HAL_RCC_PLL_DISABLE();
- 800161a:	4b10      	ldr	r3, [pc, #64]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 800161c:	681b      	ldr	r3, [r3, #0]
- 800161e:	4a0f      	ldr	r2, [pc, #60]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 8001620:	f023 7380 	bic.w	r3, r3, #16777216	; 0x1000000
- 8001624:	6013      	str	r3, [r2, #0]
+ 800164e:	4b10      	ldr	r3, [pc, #64]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 8001650:	681b      	ldr	r3, [r3, #0]
+ 8001652:	4a0f      	ldr	r2, [pc, #60]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 8001654:	f023 7380 	bic.w	r3, r3, #16777216	; 0x1000000
+ 8001658:	6013      	str	r3, [r2, #0]
 
         /* Get Start Tick*/
         tickstart = HAL_GetTick();
- 8001626:	f7fe ffd9 	bl	80005dc <HAL_GetTick>
- 800162a:	6138      	str	r0, [r7, #16]
+ 800165a:	f7fe ffbf 	bl	80005dc <HAL_GetTick>
+ 800165e:	6138      	str	r0, [r7, #16]
 
         /* Wait till PLL is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 800162c:	e008      	b.n	8001640 <HAL_RCC_OscConfig+0x4c0>
+ 8001660:	e008      	b.n	8001674 <HAL_RCC_OscConfig+0x4c0>
         {
           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 800162e:	f7fe ffd5 	bl	80005dc <HAL_GetTick>
- 8001632:	4602      	mov	r2, r0
- 8001634:	693b      	ldr	r3, [r7, #16]
- 8001636:	1ad3      	subs	r3, r2, r3
- 8001638:	2b02      	cmp	r3, #2
- 800163a:	d901      	bls.n	8001640 <HAL_RCC_OscConfig+0x4c0>
+ 8001662:	f7fe ffbb 	bl	80005dc <HAL_GetTick>
+ 8001666:	4602      	mov	r2, r0
+ 8001668:	693b      	ldr	r3, [r7, #16]
+ 800166a:	1ad3      	subs	r3, r2, r3
+ 800166c:	2b02      	cmp	r3, #2
+ 800166e:	d901      	bls.n	8001674 <HAL_RCC_OscConfig+0x4c0>
           {
             return HAL_TIMEOUT;
- 800163c:	2303      	movs	r3, #3
- 800163e:	e009      	b.n	8001654 <HAL_RCC_OscConfig+0x4d4>
+ 8001670:	2303      	movs	r3, #3
+ 8001672:	e009      	b.n	8001688 <HAL_RCC_OscConfig+0x4d4>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8001640:	4b06      	ldr	r3, [pc, #24]	; (800165c <HAL_RCC_OscConfig+0x4dc>)
- 8001642:	681b      	ldr	r3, [r3, #0]
- 8001644:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
- 8001648:	2b00      	cmp	r3, #0
- 800164a:	d1f0      	bne.n	800162e <HAL_RCC_OscConfig+0x4ae>
- 800164c:	e001      	b.n	8001652 <HAL_RCC_OscConfig+0x4d2>
+ 8001674:	4b06      	ldr	r3, [pc, #24]	; (8001690 <HAL_RCC_OscConfig+0x4dc>)
+ 8001676:	681b      	ldr	r3, [r3, #0]
+ 8001678:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 800167c:	2b00      	cmp	r3, #0
+ 800167e:	d1f0      	bne.n	8001662 <HAL_RCC_OscConfig+0x4ae>
+ 8001680:	e001      	b.n	8001686 <HAL_RCC_OscConfig+0x4d2>
         }
       }
     }
     else
     {
       return HAL_ERROR;
- 800164e:	2301      	movs	r3, #1
- 8001650:	e000      	b.n	8001654 <HAL_RCC_OscConfig+0x4d4>
+ 8001682:	2301      	movs	r3, #1
+ 8001684:	e000      	b.n	8001688 <HAL_RCC_OscConfig+0x4d4>
     }
   }
   return HAL_OK;
- 8001652:	2300      	movs	r3, #0
+ 8001686:	2300      	movs	r3, #0
 }
- 8001654:	4618      	mov	r0, r3
- 8001656:	3718      	adds	r7, #24
- 8001658:	46bd      	mov	sp, r7
- 800165a:	bd80      	pop	{r7, pc}
- 800165c:	40023800 	.word	0x40023800
- 8001660:	40007000 	.word	0x40007000
-
-08001664 <HAL_RCC_ClockConfig>:
+ 8001688:	4618      	mov	r0, r3
+ 800168a:	3718      	adds	r7, #24
+ 800168c:	46bd      	mov	sp, r7
+ 800168e:	bd80      	pop	{r7, pc}
+ 8001690:	40023800 	.word	0x40023800
+ 8001694:	40007000 	.word	0x40007000
+
+08001698 <HAL_RCC_ClockConfig>:
   *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
   *         (for more details refer to section above "Initialization/de-initialization functions")
   * @retval None
   */
 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
 {
- 8001664:	b580      	push	{r7, lr}
- 8001666:	b084      	sub	sp, #16
- 8001668:	af00      	add	r7, sp, #0
- 800166a:	6078      	str	r0, [r7, #4]
- 800166c:	6039      	str	r1, [r7, #0]
+ 8001698:	b580      	push	{r7, lr}
+ 800169a:	b084      	sub	sp, #16
+ 800169c:	af00      	add	r7, sp, #0
+ 800169e:	6078      	str	r0, [r7, #4]
+ 80016a0:	6039      	str	r1, [r7, #0]
   uint32_t tickstart = 0;
- 800166e:	2300      	movs	r3, #0
- 8001670:	60fb      	str	r3, [r7, #12]
+ 80016a2:	2300      	movs	r3, #0
+ 80016a4:	60fb      	str	r3, [r7, #12]
 
   /* Check Null pointer */
   if(RCC_ClkInitStruct == NULL)
- 8001672:	687b      	ldr	r3, [r7, #4]
- 8001674:	2b00      	cmp	r3, #0
- 8001676:	d101      	bne.n	800167c <HAL_RCC_ClockConfig+0x18>
+ 80016a6:	687b      	ldr	r3, [r7, #4]
+ 80016a8:	2b00      	cmp	r3, #0
+ 80016aa:	d101      	bne.n	80016b0 <HAL_RCC_ClockConfig+0x18>
   {
     return HAL_ERROR;
- 8001678:	2301      	movs	r3, #1
- 800167a:	e0ce      	b.n	800181a <HAL_RCC_ClockConfig+0x1b6>
+ 80016ac:	2301      	movs	r3, #1
+ 80016ae:	e0ce      	b.n	800184e <HAL_RCC_ClockConfig+0x1b6>
   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
      must be correctly programmed according to the frequency of the CPU clock
      (HCLK) and the supply voltage of the device. */
 
   /* Increasing the CPU frequency */
   if(FLatency > __HAL_FLASH_GET_LATENCY())
- 800167c:	4b69      	ldr	r3, [pc, #420]	; (8001824 <HAL_RCC_ClockConfig+0x1c0>)
- 800167e:	681b      	ldr	r3, [r3, #0]
- 8001680:	f003 030f 	and.w	r3, r3, #15
- 8001684:	683a      	ldr	r2, [r7, #0]
- 8001686:	429a      	cmp	r2, r3
- 8001688:	d910      	bls.n	80016ac <HAL_RCC_ClockConfig+0x48>
+ 80016b0:	4b69      	ldr	r3, [pc, #420]	; (8001858 <HAL_RCC_ClockConfig+0x1c0>)
+ 80016b2:	681b      	ldr	r3, [r3, #0]
+ 80016b4:	f003 030f 	and.w	r3, r3, #15
+ 80016b8:	683a      	ldr	r2, [r7, #0]
+ 80016ba:	429a      	cmp	r2, r3
+ 80016bc:	d910      	bls.n	80016e0 <HAL_RCC_ClockConfig+0x48>
   {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     __HAL_FLASH_SET_LATENCY(FLatency);
- 800168a:	4b66      	ldr	r3, [pc, #408]	; (8001824 <HAL_RCC_ClockConfig+0x1c0>)
- 800168c:	681b      	ldr	r3, [r3, #0]
- 800168e:	f023 020f 	bic.w	r2, r3, #15
- 8001692:	4964      	ldr	r1, [pc, #400]	; (8001824 <HAL_RCC_ClockConfig+0x1c0>)
- 8001694:	683b      	ldr	r3, [r7, #0]
- 8001696:	4313      	orrs	r3, r2
- 8001698:	600b      	str	r3, [r1, #0]
+ 80016be:	4b66      	ldr	r3, [pc, #408]	; (8001858 <HAL_RCC_ClockConfig+0x1c0>)
+ 80016c0:	681b      	ldr	r3, [r3, #0]
+ 80016c2:	f023 020f 	bic.w	r2, r3, #15
+ 80016c6:	4964      	ldr	r1, [pc, #400]	; (8001858 <HAL_RCC_ClockConfig+0x1c0>)
+ 80016c8:	683b      	ldr	r3, [r7, #0]
+ 80016ca:	4313      	orrs	r3, r2
+ 80016cc:	600b      	str	r3, [r1, #0]
 
     /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
     if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 800169a:	4b62      	ldr	r3, [pc, #392]	; (8001824 <HAL_RCC_ClockConfig+0x1c0>)
- 800169c:	681b      	ldr	r3, [r3, #0]
- 800169e:	f003 030f 	and.w	r3, r3, #15
- 80016a2:	683a      	ldr	r2, [r7, #0]
- 80016a4:	429a      	cmp	r2, r3
- 80016a6:	d001      	beq.n	80016ac <HAL_RCC_ClockConfig+0x48>
+ 80016ce:	4b62      	ldr	r3, [pc, #392]	; (8001858 <HAL_RCC_ClockConfig+0x1c0>)
+ 80016d0:	681b      	ldr	r3, [r3, #0]
+ 80016d2:	f003 030f 	and.w	r3, r3, #15
+ 80016d6:	683a      	ldr	r2, [r7, #0]
+ 80016d8:	429a      	cmp	r2, r3
+ 80016da:	d001      	beq.n	80016e0 <HAL_RCC_ClockConfig+0x48>
     {
       return HAL_ERROR;
- 80016a8:	2301      	movs	r3, #1
- 80016aa:	e0b6      	b.n	800181a <HAL_RCC_ClockConfig+0x1b6>
+ 80016dc:	2301      	movs	r3, #1
+ 80016de:	e0b6      	b.n	800184e <HAL_RCC_ClockConfig+0x1b6>
     }
   }
 
   /*-------------------------- HCLK Configuration --------------------------*/
   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- 80016ac:	687b      	ldr	r3, [r7, #4]
- 80016ae:	681b      	ldr	r3, [r3, #0]
- 80016b0:	f003 0302 	and.w	r3, r3, #2
- 80016b4:	2b00      	cmp	r3, #0
- 80016b6:	d020      	beq.n	80016fa <HAL_RCC_ClockConfig+0x96>
+ 80016e0:	687b      	ldr	r3, [r7, #4]
+ 80016e2:	681b      	ldr	r3, [r3, #0]
+ 80016e4:	f003 0302 	and.w	r3, r3, #2
+ 80016e8:	2b00      	cmp	r3, #0
+ 80016ea:	d020      	beq.n	800172e <HAL_RCC_ClockConfig+0x96>
   {
     /* Set the highest APBx dividers in order to ensure that we do not go through
        a non-spec phase whatever we decrease or increase HCLK. */
     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 80016b8:	687b      	ldr	r3, [r7, #4]
- 80016ba:	681b      	ldr	r3, [r3, #0]
- 80016bc:	f003 0304 	and.w	r3, r3, #4
- 80016c0:	2b00      	cmp	r3, #0
- 80016c2:	d005      	beq.n	80016d0 <HAL_RCC_ClockConfig+0x6c>
+ 80016ec:	687b      	ldr	r3, [r7, #4]
+ 80016ee:	681b      	ldr	r3, [r3, #0]
+ 80016f0:	f003 0304 	and.w	r3, r3, #4
+ 80016f4:	2b00      	cmp	r3, #0
+ 80016f6:	d005      	beq.n	8001704 <HAL_RCC_ClockConfig+0x6c>
     {
       MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
- 80016c4:	4b58      	ldr	r3, [pc, #352]	; (8001828 <HAL_RCC_ClockConfig+0x1c4>)
- 80016c6:	689b      	ldr	r3, [r3, #8]
- 80016c8:	4a57      	ldr	r2, [pc, #348]	; (8001828 <HAL_RCC_ClockConfig+0x1c4>)
- 80016ca:	f443 53e0 	orr.w	r3, r3, #7168	; 0x1c00
- 80016ce:	6093      	str	r3, [r2, #8]
+ 80016f8:	4b58      	ldr	r3, [pc, #352]	; (800185c <HAL_RCC_ClockConfig+0x1c4>)
+ 80016fa:	689b      	ldr	r3, [r3, #8]
+ 80016fc:	4a57      	ldr	r2, [pc, #348]	; (800185c <HAL_RCC_ClockConfig+0x1c4>)
+ 80016fe:	f443 53e0 	orr.w	r3, r3, #7168	; 0x1c00
+ 8001702:	6093      	str	r3, [r2, #8]
     }
 
     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 80016d0:	687b      	ldr	r3, [r7, #4]
- 80016d2:	681b      	ldr	r3, [r3, #0]
- 80016d4:	f003 0308 	and.w	r3, r3, #8
- 80016d8:	2b00      	cmp	r3, #0
- 80016da:	d005      	beq.n	80016e8 <HAL_RCC_ClockConfig+0x84>
+ 8001704:	687b      	ldr	r3, [r7, #4]
+ 8001706:	681b      	ldr	r3, [r3, #0]
+ 8001708:	f003 0308 	and.w	r3, r3, #8
+ 800170c:	2b00      	cmp	r3, #0
+ 800170e:	d005      	beq.n	800171c <HAL_RCC_ClockConfig+0x84>
     {
       MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
- 80016dc:	4b52      	ldr	r3, [pc, #328]	; (8001828 <HAL_RCC_ClockConfig+0x1c4>)
- 80016de:	689b      	ldr	r3, [r3, #8]
- 80016e0:	4a51      	ldr	r2, [pc, #324]	; (8001828 <HAL_RCC_ClockConfig+0x1c4>)
- 80016e2:	f443 4360 	orr.w	r3, r3, #57344	; 0xe000
- 80016e6:	6093      	str	r3, [r2, #8]
+ 8001710:	4b52      	ldr	r3, [pc, #328]	; (800185c <HAL_RCC_ClockConfig+0x1c4>)
+ 8001712:	689b      	ldr	r3, [r3, #8]
+ 8001714:	4a51      	ldr	r2, [pc, #324]	; (800185c <HAL_RCC_ClockConfig+0x1c4>)
+ 8001716:	f443 4360 	orr.w	r3, r3, #57344	; 0xe000
+ 800171a:	6093      	str	r3, [r2, #8]
     }
 
     /* Set the new HCLK clock divider */
     assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- 80016e8:	4b4f      	ldr	r3, [pc, #316]	; (8001828 <HAL_RCC_ClockConfig+0x1c4>)
- 80016ea:	689b      	ldr	r3, [r3, #8]
- 80016ec:	f023 02f0 	bic.w	r2, r3, #240	; 0xf0
- 80016f0:	687b      	ldr	r3, [r7, #4]
- 80016f2:	689b      	ldr	r3, [r3, #8]
- 80016f4:	494c      	ldr	r1, [pc, #304]	; (8001828 <HAL_RCC_ClockConfig+0x1c4>)
- 80016f6:	4313      	orrs	r3, r2
- 80016f8:	608b      	str	r3, [r1, #8]
+ 800171c:	4b4f      	ldr	r3, [pc, #316]	; (800185c <HAL_RCC_ClockConfig+0x1c4>)
+ 800171e:	689b      	ldr	r3, [r3, #8]
+ 8001720:	f023 02f0 	bic.w	r2, r3, #240	; 0xf0
+ 8001724:	687b      	ldr	r3, [r7, #4]
+ 8001726:	689b      	ldr	r3, [r3, #8]
+ 8001728:	494c      	ldr	r1, [pc, #304]	; (800185c <HAL_RCC_ClockConfig+0x1c4>)
+ 800172a:	4313      	orrs	r3, r2
+ 800172c:	608b      	str	r3, [r1, #8]
   }
 
   /*------------------------- SYSCLK Configuration ---------------------------*/
   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- 80016fa:	687b      	ldr	r3, [r7, #4]
- 80016fc:	681b      	ldr	r3, [r3, #0]
- 80016fe:	f003 0301 	and.w	r3, r3, #1
- 8001702:	2b00      	cmp	r3, #0
- 8001704:	d040      	beq.n	8001788 <HAL_RCC_ClockConfig+0x124>
+ 800172e:	687b      	ldr	r3, [r7, #4]
+ 8001730:	681b      	ldr	r3, [r3, #0]
+ 8001732:	f003 0301 	and.w	r3, r3, #1
+ 8001736:	2b00      	cmp	r3, #0
+ 8001738:	d040      	beq.n	80017bc <HAL_RCC_ClockConfig+0x124>
   {
     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
 
     /* HSE is selected as System Clock Source */
     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- 8001706:	687b      	ldr	r3, [r7, #4]
- 8001708:	685b      	ldr	r3, [r3, #4]
- 800170a:	2b01      	cmp	r3, #1
- 800170c:	d107      	bne.n	800171e <HAL_RCC_ClockConfig+0xba>
+ 800173a:	687b      	ldr	r3, [r7, #4]
+ 800173c:	685b      	ldr	r3, [r3, #4]
+ 800173e:	2b01      	cmp	r3, #1
+ 8001740:	d107      	bne.n	8001752 <HAL_RCC_ClockConfig+0xba>
     {
       /* Check the HSE ready flag */
       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 800170e:	4b46      	ldr	r3, [pc, #280]	; (8001828 <HAL_RCC_ClockConfig+0x1c4>)
- 8001710:	681b      	ldr	r3, [r3, #0]
- 8001712:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 8001716:	2b00      	cmp	r3, #0
- 8001718:	d115      	bne.n	8001746 <HAL_RCC_ClockConfig+0xe2>
+ 8001742:	4b46      	ldr	r3, [pc, #280]	; (800185c <HAL_RCC_ClockConfig+0x1c4>)
+ 8001744:	681b      	ldr	r3, [r3, #0]
+ 8001746:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 800174a:	2b00      	cmp	r3, #0
+ 800174c:	d115      	bne.n	800177a <HAL_RCC_ClockConfig+0xe2>
       {
         return HAL_ERROR;
- 800171a:	2301      	movs	r3, #1
- 800171c:	e07d      	b.n	800181a <HAL_RCC_ClockConfig+0x1b6>
+ 800174e:	2301      	movs	r3, #1
+ 8001750:	e07d      	b.n	800184e <HAL_RCC_ClockConfig+0x1b6>
       }
     }
     /* PLL is selected as System Clock Source */
     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- 800171e:	687b      	ldr	r3, [r7, #4]
- 8001720:	685b      	ldr	r3, [r3, #4]
- 8001722:	2b02      	cmp	r3, #2
- 8001724:	d107      	bne.n	8001736 <HAL_RCC_ClockConfig+0xd2>
+ 8001752:	687b      	ldr	r3, [r7, #4]
+ 8001754:	685b      	ldr	r3, [r3, #4]
+ 8001756:	2b02      	cmp	r3, #2
+ 8001758:	d107      	bne.n	800176a <HAL_RCC_ClockConfig+0xd2>
     {
       /* Check the PLL ready flag */
       if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 8001726:	4b40      	ldr	r3, [pc, #256]	; (8001828 <HAL_RCC_ClockConfig+0x1c4>)
- 8001728:	681b      	ldr	r3, [r3, #0]
- 800172a:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
- 800172e:	2b00      	cmp	r3, #0
- 8001730:	d109      	bne.n	8001746 <HAL_RCC_ClockConfig+0xe2>
+ 800175a:	4b40      	ldr	r3, [pc, #256]	; (800185c <HAL_RCC_ClockConfig+0x1c4>)
+ 800175c:	681b      	ldr	r3, [r3, #0]
+ 800175e:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 8001762:	2b00      	cmp	r3, #0
+ 8001764:	d109      	bne.n	800177a <HAL_RCC_ClockConfig+0xe2>
       {
         return HAL_ERROR;
- 8001732:	2301      	movs	r3, #1
- 8001734:	e071      	b.n	800181a <HAL_RCC_ClockConfig+0x1b6>
+ 8001766:	2301      	movs	r3, #1
+ 8001768:	e071      	b.n	800184e <HAL_RCC_ClockConfig+0x1b6>
     }
     /* HSI is selected as System Clock Source */
     else
     {
       /* Check the HSI ready flag */
       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 8001736:	4b3c      	ldr	r3, [pc, #240]	; (8001828 <HAL_RCC_ClockConfig+0x1c4>)
- 8001738:	681b      	ldr	r3, [r3, #0]
- 800173a:	f003 0302 	and.w	r3, r3, #2
- 800173e:	2b00      	cmp	r3, #0
- 8001740:	d101      	bne.n	8001746 <HAL_RCC_ClockConfig+0xe2>
+ 800176a:	4b3c      	ldr	r3, [pc, #240]	; (800185c <HAL_RCC_ClockConfig+0x1c4>)
+ 800176c:	681b      	ldr	r3, [r3, #0]
+ 800176e:	f003 0302 	and.w	r3, r3, #2
+ 8001772:	2b00      	cmp	r3, #0
+ 8001774:	d101      	bne.n	800177a <HAL_RCC_ClockConfig+0xe2>
       {
         return HAL_ERROR;
- 8001742:	2301      	movs	r3, #1
- 8001744:	e069      	b.n	800181a <HAL_RCC_ClockConfig+0x1b6>
+ 8001776:	2301      	movs	r3, #1
+ 8001778:	e069      	b.n	800184e <HAL_RCC_ClockConfig+0x1b6>
       }
     }
 
     __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
- 8001746:	4b38      	ldr	r3, [pc, #224]	; (8001828 <HAL_RCC_ClockConfig+0x1c4>)
- 8001748:	689b      	ldr	r3, [r3, #8]
- 800174a:	f023 0203 	bic.w	r2, r3, #3
- 800174e:	687b      	ldr	r3, [r7, #4]
- 8001750:	685b      	ldr	r3, [r3, #4]
- 8001752:	4935      	ldr	r1, [pc, #212]	; (8001828 <HAL_RCC_ClockConfig+0x1c4>)
- 8001754:	4313      	orrs	r3, r2
- 8001756:	608b      	str	r3, [r1, #8]
+ 800177a:	4b38      	ldr	r3, [pc, #224]	; (800185c <HAL_RCC_ClockConfig+0x1c4>)
+ 800177c:	689b      	ldr	r3, [r3, #8]
+ 800177e:	f023 0203 	bic.w	r2, r3, #3
+ 8001782:	687b      	ldr	r3, [r7, #4]
+ 8001784:	685b      	ldr	r3, [r3, #4]
+ 8001786:	4935      	ldr	r1, [pc, #212]	; (800185c <HAL_RCC_ClockConfig+0x1c4>)
+ 8001788:	4313      	orrs	r3, r2
+ 800178a:	608b      	str	r3, [r1, #8]
 
     /* Get Start Tick*/
     tickstart = HAL_GetTick();
- 8001758:	f7fe ff40 	bl	80005dc <HAL_GetTick>
- 800175c:	60f8      	str	r0, [r7, #12]
+ 800178c:	f7fe ff26 	bl	80005dc <HAL_GetTick>
+ 8001790:	60f8      	str	r0, [r7, #12]
 
     while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 800175e:	e00a      	b.n	8001776 <HAL_RCC_ClockConfig+0x112>
+ 8001792:	e00a      	b.n	80017aa <HAL_RCC_ClockConfig+0x112>
     {
       if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- 8001760:	f7fe ff3c 	bl	80005dc <HAL_GetTick>
- 8001764:	4602      	mov	r2, r0
- 8001766:	68fb      	ldr	r3, [r7, #12]
- 8001768:	1ad3      	subs	r3, r2, r3
- 800176a:	f241 3288 	movw	r2, #5000	; 0x1388
- 800176e:	4293      	cmp	r3, r2
- 8001770:	d901      	bls.n	8001776 <HAL_RCC_ClockConfig+0x112>
+ 8001794:	f7fe ff22 	bl	80005dc <HAL_GetTick>
+ 8001798:	4602      	mov	r2, r0
+ 800179a:	68fb      	ldr	r3, [r7, #12]
+ 800179c:	1ad3      	subs	r3, r2, r3
+ 800179e:	f241 3288 	movw	r2, #5000	; 0x1388
+ 80017a2:	4293      	cmp	r3, r2
+ 80017a4:	d901      	bls.n	80017aa <HAL_RCC_ClockConfig+0x112>
       {
         return HAL_TIMEOUT;
- 8001772:	2303      	movs	r3, #3
- 8001774:	e051      	b.n	800181a <HAL_RCC_ClockConfig+0x1b6>
+ 80017a6:	2303      	movs	r3, #3
+ 80017a8:	e051      	b.n	800184e <HAL_RCC_ClockConfig+0x1b6>
     while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 8001776:	4b2c      	ldr	r3, [pc, #176]	; (8001828 <HAL_RCC_ClockConfig+0x1c4>)
- 8001778:	689b      	ldr	r3, [r3, #8]
- 800177a:	f003 020c 	and.w	r2, r3, #12
- 800177e:	687b      	ldr	r3, [r7, #4]
- 8001780:	685b      	ldr	r3, [r3, #4]
- 8001782:	009b      	lsls	r3, r3, #2
- 8001784:	429a      	cmp	r2, r3
- 8001786:	d1eb      	bne.n	8001760 <HAL_RCC_ClockConfig+0xfc>
+ 80017aa:	4b2c      	ldr	r3, [pc, #176]	; (800185c <HAL_RCC_ClockConfig+0x1c4>)
+ 80017ac:	689b      	ldr	r3, [r3, #8]
+ 80017ae:	f003 020c 	and.w	r2, r3, #12
+ 80017b2:	687b      	ldr	r3, [r7, #4]
+ 80017b4:	685b      	ldr	r3, [r3, #4]
+ 80017b6:	009b      	lsls	r3, r3, #2
+ 80017b8:	429a      	cmp	r2, r3
+ 80017ba:	d1eb      	bne.n	8001794 <HAL_RCC_ClockConfig+0xfc>
       }
     }
   }
 
   /* Decreasing the number of wait states because of lower CPU frequency */
   if(FLatency < __HAL_FLASH_GET_LATENCY())
- 8001788:	4b26      	ldr	r3, [pc, #152]	; (8001824 <HAL_RCC_ClockConfig+0x1c0>)
- 800178a:	681b      	ldr	r3, [r3, #0]
- 800178c:	f003 030f 	and.w	r3, r3, #15
- 8001790:	683a      	ldr	r2, [r7, #0]
- 8001792:	429a      	cmp	r2, r3
- 8001794:	d210      	bcs.n	80017b8 <HAL_RCC_ClockConfig+0x154>
+ 80017bc:	4b26      	ldr	r3, [pc, #152]	; (8001858 <HAL_RCC_ClockConfig+0x1c0>)
+ 80017be:	681b      	ldr	r3, [r3, #0]
+ 80017c0:	f003 030f 	and.w	r3, r3, #15
+ 80017c4:	683a      	ldr	r2, [r7, #0]
+ 80017c6:	429a      	cmp	r2, r3
+ 80017c8:	d210      	bcs.n	80017ec <HAL_RCC_ClockConfig+0x154>
   {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     __HAL_FLASH_SET_LATENCY(FLatency);
- 8001796:	4b23      	ldr	r3, [pc, #140]	; (8001824 <HAL_RCC_ClockConfig+0x1c0>)
- 8001798:	681b      	ldr	r3, [r3, #0]
- 800179a:	f023 020f 	bic.w	r2, r3, #15
- 800179e:	4921      	ldr	r1, [pc, #132]	; (8001824 <HAL_RCC_ClockConfig+0x1c0>)
- 80017a0:	683b      	ldr	r3, [r7, #0]
- 80017a2:	4313      	orrs	r3, r2
- 80017a4:	600b      	str	r3, [r1, #0]
+ 80017ca:	4b23      	ldr	r3, [pc, #140]	; (8001858 <HAL_RCC_ClockConfig+0x1c0>)
+ 80017cc:	681b      	ldr	r3, [r3, #0]
+ 80017ce:	f023 020f 	bic.w	r2, r3, #15
+ 80017d2:	4921      	ldr	r1, [pc, #132]	; (8001858 <HAL_RCC_ClockConfig+0x1c0>)
+ 80017d4:	683b      	ldr	r3, [r7, #0]
+ 80017d6:	4313      	orrs	r3, r2
+ 80017d8:	600b      	str	r3, [r1, #0]
 
     /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
     if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 80017a6:	4b1f      	ldr	r3, [pc, #124]	; (8001824 <HAL_RCC_ClockConfig+0x1c0>)
- 80017a8:	681b      	ldr	r3, [r3, #0]
- 80017aa:	f003 030f 	and.w	r3, r3, #15
- 80017ae:	683a      	ldr	r2, [r7, #0]
- 80017b0:	429a      	cmp	r2, r3
- 80017b2:	d001      	beq.n	80017b8 <HAL_RCC_ClockConfig+0x154>
+ 80017da:	4b1f      	ldr	r3, [pc, #124]	; (8001858 <HAL_RCC_ClockConfig+0x1c0>)
+ 80017dc:	681b      	ldr	r3, [r3, #0]
+ 80017de:	f003 030f 	and.w	r3, r3, #15
+ 80017e2:	683a      	ldr	r2, [r7, #0]
+ 80017e4:	429a      	cmp	r2, r3
+ 80017e6:	d001      	beq.n	80017ec <HAL_RCC_ClockConfig+0x154>
     {
       return HAL_ERROR;
- 80017b4:	2301      	movs	r3, #1
- 80017b6:	e030      	b.n	800181a <HAL_RCC_ClockConfig+0x1b6>
+ 80017e8:	2301      	movs	r3, #1
+ 80017ea:	e030      	b.n	800184e <HAL_RCC_ClockConfig+0x1b6>
     }
   }
 
   /*-------------------------- PCLK1 Configuration ---------------------------*/
   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 80017b8:	687b      	ldr	r3, [r7, #4]
- 80017ba:	681b      	ldr	r3, [r3, #0]
- 80017bc:	f003 0304 	and.w	r3, r3, #4
- 80017c0:	2b00      	cmp	r3, #0
- 80017c2:	d008      	beq.n	80017d6 <HAL_RCC_ClockConfig+0x172>
+ 80017ec:	687b      	ldr	r3, [r7, #4]
+ 80017ee:	681b      	ldr	r3, [r3, #0]
+ 80017f0:	f003 0304 	and.w	r3, r3, #4
+ 80017f4:	2b00      	cmp	r3, #0
+ 80017f6:	d008      	beq.n	800180a <HAL_RCC_ClockConfig+0x172>
   {
     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
- 80017c4:	4b18      	ldr	r3, [pc, #96]	; (8001828 <HAL_RCC_ClockConfig+0x1c4>)
- 80017c6:	689b      	ldr	r3, [r3, #8]
- 80017c8:	f423 52e0 	bic.w	r2, r3, #7168	; 0x1c00
- 80017cc:	687b      	ldr	r3, [r7, #4]
- 80017ce:	68db      	ldr	r3, [r3, #12]
- 80017d0:	4915      	ldr	r1, [pc, #84]	; (8001828 <HAL_RCC_ClockConfig+0x1c4>)
- 80017d2:	4313      	orrs	r3, r2
- 80017d4:	608b      	str	r3, [r1, #8]
+ 80017f8:	4b18      	ldr	r3, [pc, #96]	; (800185c <HAL_RCC_ClockConfig+0x1c4>)
+ 80017fa:	689b      	ldr	r3, [r3, #8]
+ 80017fc:	f423 52e0 	bic.w	r2, r3, #7168	; 0x1c00
+ 8001800:	687b      	ldr	r3, [r7, #4]
+ 8001802:	68db      	ldr	r3, [r3, #12]
+ 8001804:	4915      	ldr	r1, [pc, #84]	; (800185c <HAL_RCC_ClockConfig+0x1c4>)
+ 8001806:	4313      	orrs	r3, r2
+ 8001808:	608b      	str	r3, [r1, #8]
   }
 
   /*-------------------------- PCLK2 Configuration ---------------------------*/
   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 80017d6:	687b      	ldr	r3, [r7, #4]
- 80017d8:	681b      	ldr	r3, [r3, #0]
- 80017da:	f003 0308 	and.w	r3, r3, #8
- 80017de:	2b00      	cmp	r3, #0
- 80017e0:	d009      	beq.n	80017f6 <HAL_RCC_ClockConfig+0x192>
+ 800180a:	687b      	ldr	r3, [r7, #4]
+ 800180c:	681b      	ldr	r3, [r3, #0]
+ 800180e:	f003 0308 	and.w	r3, r3, #8
+ 8001812:	2b00      	cmp	r3, #0
+ 8001814:	d009      	beq.n	800182a <HAL_RCC_ClockConfig+0x192>
   {
     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
- 80017e2:	4b11      	ldr	r3, [pc, #68]	; (8001828 <HAL_RCC_ClockConfig+0x1c4>)
- 80017e4:	689b      	ldr	r3, [r3, #8]
- 80017e6:	f423 4260 	bic.w	r2, r3, #57344	; 0xe000
- 80017ea:	687b      	ldr	r3, [r7, #4]
- 80017ec:	691b      	ldr	r3, [r3, #16]
- 80017ee:	00db      	lsls	r3, r3, #3
- 80017f0:	490d      	ldr	r1, [pc, #52]	; (8001828 <HAL_RCC_ClockConfig+0x1c4>)
- 80017f2:	4313      	orrs	r3, r2
- 80017f4:	608b      	str	r3, [r1, #8]
+ 8001816:	4b11      	ldr	r3, [pc, #68]	; (800185c <HAL_RCC_ClockConfig+0x1c4>)
+ 8001818:	689b      	ldr	r3, [r3, #8]
+ 800181a:	f423 4260 	bic.w	r2, r3, #57344	; 0xe000
+ 800181e:	687b      	ldr	r3, [r7, #4]
+ 8001820:	691b      	ldr	r3, [r3, #16]
+ 8001822:	00db      	lsls	r3, r3, #3
+ 8001824:	490d      	ldr	r1, [pc, #52]	; (800185c <HAL_RCC_ClockConfig+0x1c4>)
+ 8001826:	4313      	orrs	r3, r2
+ 8001828:	608b      	str	r3, [r1, #8]
   }
 
   /* Update the SystemCoreClock global variable */
   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
- 80017f6:	f000 f81d 	bl	8001834 <HAL_RCC_GetSysClockFreq>
- 80017fa:	4601      	mov	r1, r0
- 80017fc:	4b0a      	ldr	r3, [pc, #40]	; (8001828 <HAL_RCC_ClockConfig+0x1c4>)
- 80017fe:	689b      	ldr	r3, [r3, #8]
- 8001800:	091b      	lsrs	r3, r3, #4
- 8001802:	f003 030f 	and.w	r3, r3, #15
- 8001806:	4a09      	ldr	r2, [pc, #36]	; (800182c <HAL_RCC_ClockConfig+0x1c8>)
- 8001808:	5cd3      	ldrb	r3, [r2, r3]
- 800180a:	fa21 f303 	lsr.w	r3, r1, r3
- 800180e:	4a08      	ldr	r2, [pc, #32]	; (8001830 <HAL_RCC_ClockConfig+0x1cc>)
- 8001810:	6013      	str	r3, [r2, #0]
+ 800182a:	f000 f81d 	bl	8001868 <HAL_RCC_GetSysClockFreq>
+ 800182e:	4601      	mov	r1, r0
+ 8001830:	4b0a      	ldr	r3, [pc, #40]	; (800185c <HAL_RCC_ClockConfig+0x1c4>)
+ 8001832:	689b      	ldr	r3, [r3, #8]
+ 8001834:	091b      	lsrs	r3, r3, #4
+ 8001836:	f003 030f 	and.w	r3, r3, #15
+ 800183a:	4a09      	ldr	r2, [pc, #36]	; (8001860 <HAL_RCC_ClockConfig+0x1c8>)
+ 800183c:	5cd3      	ldrb	r3, [r2, r3]
+ 800183e:	fa21 f303 	lsr.w	r3, r1, r3
+ 8001842:	4a08      	ldr	r2, [pc, #32]	; (8001864 <HAL_RCC_ClockConfig+0x1cc>)
+ 8001844:	6013      	str	r3, [r2, #0]
 
   /* Configure the source of time base considering new system clocks settings*/
   HAL_InitTick (TICK_INT_PRIORITY);
- 8001812:	2000      	movs	r0, #0
- 8001814:	f7fe fe9e 	bl	8000554 <HAL_InitTick>
+ 8001846:	2000      	movs	r0, #0
+ 8001848:	f7fe fe84 	bl	8000554 <HAL_InitTick>
 
   return HAL_OK;
- 8001818:	2300      	movs	r3, #0
+ 800184c:	2300      	movs	r3, #0
 }
- 800181a:	4618      	mov	r0, r3
- 800181c:	3710      	adds	r7, #16
- 800181e:	46bd      	mov	sp, r7
- 8001820:	bd80      	pop	{r7, pc}
- 8001822:	bf00      	nop
- 8001824:	40023c00 	.word	0x40023c00
- 8001828:	40023800 	.word	0x40023800
- 800182c:	0800377c 	.word	0x0800377c
- 8001830:	20000008 	.word	0x20000008
-
-08001834 <HAL_RCC_GetSysClockFreq>:
+ 800184e:	4618      	mov	r0, r3
+ 8001850:	3710      	adds	r7, #16
+ 8001852:	46bd      	mov	sp, r7
+ 8001854:	bd80      	pop	{r7, pc}
+ 8001856:	bf00      	nop
+ 8001858:	40023c00 	.word	0x40023c00
+ 800185c:	40023800 	.word	0x40023800
+ 8001860:	08004440 	.word	0x08004440
+ 8001864:	20000008 	.word	0x20000008
+
+08001868 <HAL_RCC_GetSysClockFreq>:
   *
   *
   * @retval SYSCLK frequency
   */
 uint32_t HAL_RCC_GetSysClockFreq(void)
 {
- 8001834:	b5f0      	push	{r4, r5, r6, r7, lr}
- 8001836:	b085      	sub	sp, #20
- 8001838:	af00      	add	r7, sp, #0
+ 8001868:	b5f0      	push	{r4, r5, r6, r7, lr}
+ 800186a:	b085      	sub	sp, #20
+ 800186c:	af00      	add	r7, sp, #0
   uint32_t pllm = 0, pllvco = 0, pllp = 0;
- 800183a:	2300      	movs	r3, #0
- 800183c:	607b      	str	r3, [r7, #4]
- 800183e:	2300      	movs	r3, #0
- 8001840:	60fb      	str	r3, [r7, #12]
- 8001842:	2300      	movs	r3, #0
- 8001844:	603b      	str	r3, [r7, #0]
+ 800186e:	2300      	movs	r3, #0
+ 8001870:	607b      	str	r3, [r7, #4]
+ 8001872:	2300      	movs	r3, #0
+ 8001874:	60fb      	str	r3, [r7, #12]
+ 8001876:	2300      	movs	r3, #0
+ 8001878:	603b      	str	r3, [r7, #0]
   uint32_t sysclockfreq = 0;
- 8001846:	2300      	movs	r3, #0
- 8001848:	60bb      	str	r3, [r7, #8]
+ 800187a:	2300      	movs	r3, #0
+ 800187c:	60bb      	str	r3, [r7, #8]
 
   /* Get SYSCLK source -------------------------------------------------------*/
   switch (RCC->CFGR & RCC_CFGR_SWS)
- 800184a:	4b50      	ldr	r3, [pc, #320]	; (800198c <HAL_RCC_GetSysClockFreq+0x158>)
- 800184c:	689b      	ldr	r3, [r3, #8]
- 800184e:	f003 030c 	and.w	r3, r3, #12
- 8001852:	2b04      	cmp	r3, #4
- 8001854:	d007      	beq.n	8001866 <HAL_RCC_GetSysClockFreq+0x32>
- 8001856:	2b08      	cmp	r3, #8
- 8001858:	d008      	beq.n	800186c <HAL_RCC_GetSysClockFreq+0x38>
- 800185a:	2b00      	cmp	r3, #0
- 800185c:	f040 808d 	bne.w	800197a <HAL_RCC_GetSysClockFreq+0x146>
+ 800187e:	4b50      	ldr	r3, [pc, #320]	; (80019c0 <HAL_RCC_GetSysClockFreq+0x158>)
+ 8001880:	689b      	ldr	r3, [r3, #8]
+ 8001882:	f003 030c 	and.w	r3, r3, #12
+ 8001886:	2b04      	cmp	r3, #4
+ 8001888:	d007      	beq.n	800189a <HAL_RCC_GetSysClockFreq+0x32>
+ 800188a:	2b08      	cmp	r3, #8
+ 800188c:	d008      	beq.n	80018a0 <HAL_RCC_GetSysClockFreq+0x38>
+ 800188e:	2b00      	cmp	r3, #0
+ 8001890:	f040 808d 	bne.w	80019ae <HAL_RCC_GetSysClockFreq+0x146>
   {
     case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
     {
       sysclockfreq = HSI_VALUE;
- 8001860:	4b4b      	ldr	r3, [pc, #300]	; (8001990 <HAL_RCC_GetSysClockFreq+0x15c>)
- 8001862:	60bb      	str	r3, [r7, #8]
+ 8001894:	4b4b      	ldr	r3, [pc, #300]	; (80019c4 <HAL_RCC_GetSysClockFreq+0x15c>)
+ 8001896:	60bb      	str	r3, [r7, #8]
        break;
- 8001864:	e08c      	b.n	8001980 <HAL_RCC_GetSysClockFreq+0x14c>
+ 8001898:	e08c      	b.n	80019b4 <HAL_RCC_GetSysClockFreq+0x14c>
     }
     case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
     {
       sysclockfreq = HSE_VALUE;
- 8001866:	4b4b      	ldr	r3, [pc, #300]	; (8001994 <HAL_RCC_GetSysClockFreq+0x160>)
- 8001868:	60bb      	str	r3, [r7, #8]
+ 800189a:	4b4b      	ldr	r3, [pc, #300]	; (80019c8 <HAL_RCC_GetSysClockFreq+0x160>)
+ 800189c:	60bb      	str	r3, [r7, #8]
       break;
- 800186a:	e089      	b.n	8001980 <HAL_RCC_GetSysClockFreq+0x14c>
+ 800189e:	e089      	b.n	80019b4 <HAL_RCC_GetSysClockFreq+0x14c>
     }
     case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock  source */
     {
       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
       SYSCLK = PLL_VCO / PLLP */
       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
- 800186c:	4b47      	ldr	r3, [pc, #284]	; (800198c <HAL_RCC_GetSysClockFreq+0x158>)
- 800186e:	685b      	ldr	r3, [r3, #4]
- 8001870:	f003 033f 	and.w	r3, r3, #63	; 0x3f
- 8001874:	607b      	str	r3, [r7, #4]
+ 80018a0:	4b47      	ldr	r3, [pc, #284]	; (80019c0 <HAL_RCC_GetSysClockFreq+0x158>)
+ 80018a2:	685b      	ldr	r3, [r3, #4]
+ 80018a4:	f003 033f 	and.w	r3, r3, #63	; 0x3f
+ 80018a8:	607b      	str	r3, [r7, #4]
       if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
- 8001876:	4b45      	ldr	r3, [pc, #276]	; (800198c <HAL_RCC_GetSysClockFreq+0x158>)
- 8001878:	685b      	ldr	r3, [r3, #4]
- 800187a:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
- 800187e:	2b00      	cmp	r3, #0
- 8001880:	d023      	beq.n	80018ca <HAL_RCC_GetSysClockFreq+0x96>
+ 80018aa:	4b45      	ldr	r3, [pc, #276]	; (80019c0 <HAL_RCC_GetSysClockFreq+0x158>)
+ 80018ac:	685b      	ldr	r3, [r3, #4]
+ 80018ae:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
+ 80018b2:	2b00      	cmp	r3, #0
+ 80018b4:	d023      	beq.n	80018fe <HAL_RCC_GetSysClockFreq+0x96>
       {
         /* HSE used as PLL clock source */
         pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 8001882:	4b42      	ldr	r3, [pc, #264]	; (800198c <HAL_RCC_GetSysClockFreq+0x158>)
- 8001884:	685b      	ldr	r3, [r3, #4]
- 8001886:	099b      	lsrs	r3, r3, #6
- 8001888:	f04f 0400 	mov.w	r4, #0
- 800188c:	f240 11ff 	movw	r1, #511	; 0x1ff
- 8001890:	f04f 0200 	mov.w	r2, #0
- 8001894:	ea03 0501 	and.w	r5, r3, r1
- 8001898:	ea04 0602 	and.w	r6, r4, r2
- 800189c:	4a3d      	ldr	r2, [pc, #244]	; (8001994 <HAL_RCC_GetSysClockFreq+0x160>)
- 800189e:	fb02 f106 	mul.w	r1, r2, r6
- 80018a2:	2200      	movs	r2, #0
- 80018a4:	fb02 f205 	mul.w	r2, r2, r5
- 80018a8:	440a      	add	r2, r1
- 80018aa:	493a      	ldr	r1, [pc, #232]	; (8001994 <HAL_RCC_GetSysClockFreq+0x160>)
- 80018ac:	fba5 0101 	umull	r0, r1, r5, r1
- 80018b0:	1853      	adds	r3, r2, r1
- 80018b2:	4619      	mov	r1, r3
- 80018b4:	687b      	ldr	r3, [r7, #4]
- 80018b6:	f04f 0400 	mov.w	r4, #0
- 80018ba:	461a      	mov	r2, r3
- 80018bc:	4623      	mov	r3, r4
- 80018be:	f7fe fcbb 	bl	8000238 <__aeabi_uldivmod>
- 80018c2:	4603      	mov	r3, r0
- 80018c4:	460c      	mov	r4, r1
- 80018c6:	60fb      	str	r3, [r7, #12]
- 80018c8:	e049      	b.n	800195e <HAL_RCC_GetSysClockFreq+0x12a>
+ 80018b6:	4b42      	ldr	r3, [pc, #264]	; (80019c0 <HAL_RCC_GetSysClockFreq+0x158>)
+ 80018b8:	685b      	ldr	r3, [r3, #4]
+ 80018ba:	099b      	lsrs	r3, r3, #6
+ 80018bc:	f04f 0400 	mov.w	r4, #0
+ 80018c0:	f240 11ff 	movw	r1, #511	; 0x1ff
+ 80018c4:	f04f 0200 	mov.w	r2, #0
+ 80018c8:	ea03 0501 	and.w	r5, r3, r1
+ 80018cc:	ea04 0602 	and.w	r6, r4, r2
+ 80018d0:	4a3d      	ldr	r2, [pc, #244]	; (80019c8 <HAL_RCC_GetSysClockFreq+0x160>)
+ 80018d2:	fb02 f106 	mul.w	r1, r2, r6
+ 80018d6:	2200      	movs	r2, #0
+ 80018d8:	fb02 f205 	mul.w	r2, r2, r5
+ 80018dc:	440a      	add	r2, r1
+ 80018de:	493a      	ldr	r1, [pc, #232]	; (80019c8 <HAL_RCC_GetSysClockFreq+0x160>)
+ 80018e0:	fba5 0101 	umull	r0, r1, r5, r1
+ 80018e4:	1853      	adds	r3, r2, r1
+ 80018e6:	4619      	mov	r1, r3
+ 80018e8:	687b      	ldr	r3, [r7, #4]
+ 80018ea:	f04f 0400 	mov.w	r4, #0
+ 80018ee:	461a      	mov	r2, r3
+ 80018f0:	4623      	mov	r3, r4
+ 80018f2:	f7fe fca1 	bl	8000238 <__aeabi_uldivmod>
+ 80018f6:	4603      	mov	r3, r0
+ 80018f8:	460c      	mov	r4, r1
+ 80018fa:	60fb      	str	r3, [r7, #12]
+ 80018fc:	e049      	b.n	8001992 <HAL_RCC_GetSysClockFreq+0x12a>
       }
       else
       {
         /* HSI used as PLL clock source */
         pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 80018ca:	4b30      	ldr	r3, [pc, #192]	; (800198c <HAL_RCC_GetSysClockFreq+0x158>)
- 80018cc:	685b      	ldr	r3, [r3, #4]
- 80018ce:	099b      	lsrs	r3, r3, #6
- 80018d0:	f04f 0400 	mov.w	r4, #0
- 80018d4:	f240 11ff 	movw	r1, #511	; 0x1ff
- 80018d8:	f04f 0200 	mov.w	r2, #0
- 80018dc:	ea03 0501 	and.w	r5, r3, r1
- 80018e0:	ea04 0602 	and.w	r6, r4, r2
- 80018e4:	4629      	mov	r1, r5
- 80018e6:	4632      	mov	r2, r6
- 80018e8:	f04f 0300 	mov.w	r3, #0
- 80018ec:	f04f 0400 	mov.w	r4, #0
- 80018f0:	0154      	lsls	r4, r2, #5
- 80018f2:	ea44 64d1 	orr.w	r4, r4, r1, lsr #27
- 80018f6:	014b      	lsls	r3, r1, #5
- 80018f8:	4619      	mov	r1, r3
- 80018fa:	4622      	mov	r2, r4
- 80018fc:	1b49      	subs	r1, r1, r5
- 80018fe:	eb62 0206 	sbc.w	r2, r2, r6
- 8001902:	f04f 0300 	mov.w	r3, #0
- 8001906:	f04f 0400 	mov.w	r4, #0
- 800190a:	0194      	lsls	r4, r2, #6
- 800190c:	ea44 6491 	orr.w	r4, r4, r1, lsr #26
- 8001910:	018b      	lsls	r3, r1, #6
- 8001912:	1a5b      	subs	r3, r3, r1
- 8001914:	eb64 0402 	sbc.w	r4, r4, r2
- 8001918:	f04f 0100 	mov.w	r1, #0
- 800191c:	f04f 0200 	mov.w	r2, #0
- 8001920:	00e2      	lsls	r2, r4, #3
- 8001922:	ea42 7253 	orr.w	r2, r2, r3, lsr #29
- 8001926:	00d9      	lsls	r1, r3, #3
- 8001928:	460b      	mov	r3, r1
- 800192a:	4614      	mov	r4, r2
- 800192c:	195b      	adds	r3, r3, r5
- 800192e:	eb44 0406 	adc.w	r4, r4, r6
- 8001932:	f04f 0100 	mov.w	r1, #0
- 8001936:	f04f 0200 	mov.w	r2, #0
- 800193a:	02a2      	lsls	r2, r4, #10
- 800193c:	ea42 5293 	orr.w	r2, r2, r3, lsr #22
- 8001940:	0299      	lsls	r1, r3, #10
- 8001942:	460b      	mov	r3, r1
- 8001944:	4614      	mov	r4, r2
- 8001946:	4618      	mov	r0, r3
- 8001948:	4621      	mov	r1, r4
- 800194a:	687b      	ldr	r3, [r7, #4]
- 800194c:	f04f 0400 	mov.w	r4, #0
- 8001950:	461a      	mov	r2, r3
- 8001952:	4623      	mov	r3, r4
- 8001954:	f7fe fc70 	bl	8000238 <__aeabi_uldivmod>
- 8001958:	4603      	mov	r3, r0
- 800195a:	460c      	mov	r4, r1
- 800195c:	60fb      	str	r3, [r7, #12]
+ 80018fe:	4b30      	ldr	r3, [pc, #192]	; (80019c0 <HAL_RCC_GetSysClockFreq+0x158>)
+ 8001900:	685b      	ldr	r3, [r3, #4]
+ 8001902:	099b      	lsrs	r3, r3, #6
+ 8001904:	f04f 0400 	mov.w	r4, #0
+ 8001908:	f240 11ff 	movw	r1, #511	; 0x1ff
+ 800190c:	f04f 0200 	mov.w	r2, #0
+ 8001910:	ea03 0501 	and.w	r5, r3, r1
+ 8001914:	ea04 0602 	and.w	r6, r4, r2
+ 8001918:	4629      	mov	r1, r5
+ 800191a:	4632      	mov	r2, r6
+ 800191c:	f04f 0300 	mov.w	r3, #0
+ 8001920:	f04f 0400 	mov.w	r4, #0
+ 8001924:	0154      	lsls	r4, r2, #5
+ 8001926:	ea44 64d1 	orr.w	r4, r4, r1, lsr #27
+ 800192a:	014b      	lsls	r3, r1, #5
+ 800192c:	4619      	mov	r1, r3
+ 800192e:	4622      	mov	r2, r4
+ 8001930:	1b49      	subs	r1, r1, r5
+ 8001932:	eb62 0206 	sbc.w	r2, r2, r6
+ 8001936:	f04f 0300 	mov.w	r3, #0
+ 800193a:	f04f 0400 	mov.w	r4, #0
+ 800193e:	0194      	lsls	r4, r2, #6
+ 8001940:	ea44 6491 	orr.w	r4, r4, r1, lsr #26
+ 8001944:	018b      	lsls	r3, r1, #6
+ 8001946:	1a5b      	subs	r3, r3, r1
+ 8001948:	eb64 0402 	sbc.w	r4, r4, r2
+ 800194c:	f04f 0100 	mov.w	r1, #0
+ 8001950:	f04f 0200 	mov.w	r2, #0
+ 8001954:	00e2      	lsls	r2, r4, #3
+ 8001956:	ea42 7253 	orr.w	r2, r2, r3, lsr #29
+ 800195a:	00d9      	lsls	r1, r3, #3
+ 800195c:	460b      	mov	r3, r1
+ 800195e:	4614      	mov	r4, r2
+ 8001960:	195b      	adds	r3, r3, r5
+ 8001962:	eb44 0406 	adc.w	r4, r4, r6
+ 8001966:	f04f 0100 	mov.w	r1, #0
+ 800196a:	f04f 0200 	mov.w	r2, #0
+ 800196e:	02a2      	lsls	r2, r4, #10
+ 8001970:	ea42 5293 	orr.w	r2, r2, r3, lsr #22
+ 8001974:	0299      	lsls	r1, r3, #10
+ 8001976:	460b      	mov	r3, r1
+ 8001978:	4614      	mov	r4, r2
+ 800197a:	4618      	mov	r0, r3
+ 800197c:	4621      	mov	r1, r4
+ 800197e:	687b      	ldr	r3, [r7, #4]
+ 8001980:	f04f 0400 	mov.w	r4, #0
+ 8001984:	461a      	mov	r2, r3
+ 8001986:	4623      	mov	r3, r4
+ 8001988:	f7fe fc56 	bl	8000238 <__aeabi_uldivmod>
+ 800198c:	4603      	mov	r3, r0
+ 800198e:	460c      	mov	r4, r1
+ 8001990:	60fb      	str	r3, [r7, #12]
       }
       pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2);
- 800195e:	4b0b      	ldr	r3, [pc, #44]	; (800198c <HAL_RCC_GetSysClockFreq+0x158>)
- 8001960:	685b      	ldr	r3, [r3, #4]
- 8001962:	0c1b      	lsrs	r3, r3, #16
- 8001964:	f003 0303 	and.w	r3, r3, #3
- 8001968:	3301      	adds	r3, #1
- 800196a:	005b      	lsls	r3, r3, #1
- 800196c:	603b      	str	r3, [r7, #0]
+ 8001992:	4b0b      	ldr	r3, [pc, #44]	; (80019c0 <HAL_RCC_GetSysClockFreq+0x158>)
+ 8001994:	685b      	ldr	r3, [r3, #4]
+ 8001996:	0c1b      	lsrs	r3, r3, #16
+ 8001998:	f003 0303 	and.w	r3, r3, #3
+ 800199c:	3301      	adds	r3, #1
+ 800199e:	005b      	lsls	r3, r3, #1
+ 80019a0:	603b      	str	r3, [r7, #0]
 
       sysclockfreq = pllvco/pllp;
- 800196e:	68fa      	ldr	r2, [r7, #12]
- 8001970:	683b      	ldr	r3, [r7, #0]
- 8001972:	fbb2 f3f3 	udiv	r3, r2, r3
- 8001976:	60bb      	str	r3, [r7, #8]
+ 80019a2:	68fa      	ldr	r2, [r7, #12]
+ 80019a4:	683b      	ldr	r3, [r7, #0]
+ 80019a6:	fbb2 f3f3 	udiv	r3, r2, r3
+ 80019aa:	60bb      	str	r3, [r7, #8]
       break;
- 8001978:	e002      	b.n	8001980 <HAL_RCC_GetSysClockFreq+0x14c>
+ 80019ac:	e002      	b.n	80019b4 <HAL_RCC_GetSysClockFreq+0x14c>
     }
     default:
     {
       sysclockfreq = HSI_VALUE;
- 800197a:	4b05      	ldr	r3, [pc, #20]	; (8001990 <HAL_RCC_GetSysClockFreq+0x15c>)
- 800197c:	60bb      	str	r3, [r7, #8]
+ 80019ae:	4b05      	ldr	r3, [pc, #20]	; (80019c4 <HAL_RCC_GetSysClockFreq+0x15c>)
+ 80019b0:	60bb      	str	r3, [r7, #8]
       break;
- 800197e:	bf00      	nop
+ 80019b2:	bf00      	nop
     }
   }
   return sysclockfreq;
- 8001980:	68bb      	ldr	r3, [r7, #8]
+ 80019b4:	68bb      	ldr	r3, [r7, #8]
 }
- 8001982:	4618      	mov	r0, r3
- 8001984:	3714      	adds	r7, #20
- 8001986:	46bd      	mov	sp, r7
- 8001988:	bdf0      	pop	{r4, r5, r6, r7, pc}
- 800198a:	bf00      	nop
- 800198c:	40023800 	.word	0x40023800
- 8001990:	00f42400 	.word	0x00f42400
- 8001994:	017d7840 	.word	0x017d7840
-
-08001998 <HAL_RCC_GetHCLKFreq>:
+ 80019b6:	4618      	mov	r0, r3
+ 80019b8:	3714      	adds	r7, #20
+ 80019ba:	46bd      	mov	sp, r7
+ 80019bc:	bdf0      	pop	{r4, r5, r6, r7, pc}
+ 80019be:	bf00      	nop
+ 80019c0:	40023800 	.word	0x40023800
+ 80019c4:	00f42400 	.word	0x00f42400
+ 80019c8:	017d7840 	.word	0x017d7840
+
+080019cc <HAL_RCC_GetHCLKFreq>:
   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
   * @retval HCLK frequency
   */
 uint32_t HAL_RCC_GetHCLKFreq(void)
 {
- 8001998:	b480      	push	{r7}
- 800199a:	af00      	add	r7, sp, #0
+ 80019cc:	b480      	push	{r7}
+ 80019ce:	af00      	add	r7, sp, #0
   return SystemCoreClock;
- 800199c:	4b03      	ldr	r3, [pc, #12]	; (80019ac <HAL_RCC_GetHCLKFreq+0x14>)
- 800199e:	681b      	ldr	r3, [r3, #0]
+ 80019d0:	4b03      	ldr	r3, [pc, #12]	; (80019e0 <HAL_RCC_GetHCLKFreq+0x14>)
+ 80019d2:	681b      	ldr	r3, [r3, #0]
 }
- 80019a0:	4618      	mov	r0, r3
- 80019a2:	46bd      	mov	sp, r7
- 80019a4:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80019a8:	4770      	bx	lr
- 80019aa:	bf00      	nop
- 80019ac:	20000008 	.word	0x20000008
-
-080019b0 <HAL_RCC_GetPCLK1Freq>:
+ 80019d4:	4618      	mov	r0, r3
+ 80019d6:	46bd      	mov	sp, r7
+ 80019d8:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80019dc:	4770      	bx	lr
+ 80019de:	bf00      	nop
+ 80019e0:	20000008 	.word	0x20000008
+
+080019e4 <HAL_RCC_GetPCLK1Freq>:
   * @note   Each time PCLK1 changes, this function must be called to update the
   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
   * @retval PCLK1 frequency
   */
 uint32_t HAL_RCC_GetPCLK1Freq(void)
 {
- 80019b0:	b580      	push	{r7, lr}
- 80019b2:	af00      	add	r7, sp, #0
+ 80019e4:	b580      	push	{r7, lr}
+ 80019e6:	af00      	add	r7, sp, #0
   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
   return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
- 80019b4:	f7ff fff0 	bl	8001998 <HAL_RCC_GetHCLKFreq>
- 80019b8:	4601      	mov	r1, r0
- 80019ba:	4b05      	ldr	r3, [pc, #20]	; (80019d0 <HAL_RCC_GetPCLK1Freq+0x20>)
- 80019bc:	689b      	ldr	r3, [r3, #8]
- 80019be:	0a9b      	lsrs	r3, r3, #10
- 80019c0:	f003 0307 	and.w	r3, r3, #7
- 80019c4:	4a03      	ldr	r2, [pc, #12]	; (80019d4 <HAL_RCC_GetPCLK1Freq+0x24>)
- 80019c6:	5cd3      	ldrb	r3, [r2, r3]
- 80019c8:	fa21 f303 	lsr.w	r3, r1, r3
+ 80019e8:	f7ff fff0 	bl	80019cc <HAL_RCC_GetHCLKFreq>
+ 80019ec:	4601      	mov	r1, r0
+ 80019ee:	4b05      	ldr	r3, [pc, #20]	; (8001a04 <HAL_RCC_GetPCLK1Freq+0x20>)
+ 80019f0:	689b      	ldr	r3, [r3, #8]
+ 80019f2:	0a9b      	lsrs	r3, r3, #10
+ 80019f4:	f003 0307 	and.w	r3, r3, #7
+ 80019f8:	4a03      	ldr	r2, [pc, #12]	; (8001a08 <HAL_RCC_GetPCLK1Freq+0x24>)
+ 80019fa:	5cd3      	ldrb	r3, [r2, r3]
+ 80019fc:	fa21 f303 	lsr.w	r3, r1, r3
 }
- 80019cc:	4618      	mov	r0, r3
- 80019ce:	bd80      	pop	{r7, pc}
- 80019d0:	40023800 	.word	0x40023800
- 80019d4:	0800378c 	.word	0x0800378c
+ 8001a00:	4618      	mov	r0, r3
+ 8001a02:	bd80      	pop	{r7, pc}
+ 8001a04:	40023800 	.word	0x40023800
+ 8001a08:	08004450 	.word	0x08004450
 
-080019d8 <HAL_RCC_GetPCLK2Freq>:
+08001a0c <HAL_RCC_GetPCLK2Freq>:
   * @note   Each time PCLK2 changes, this function must be called to update the
   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
   * @retval PCLK2 frequency
   */
 uint32_t HAL_RCC_GetPCLK2Freq(void)
 {
- 80019d8:	b580      	push	{r7, lr}
- 80019da:	af00      	add	r7, sp, #0
+ 8001a0c:	b580      	push	{r7, lr}
+ 8001a0e:	af00      	add	r7, sp, #0
   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
   return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
- 80019dc:	f7ff ffdc 	bl	8001998 <HAL_RCC_GetHCLKFreq>
- 80019e0:	4601      	mov	r1, r0
- 80019e2:	4b05      	ldr	r3, [pc, #20]	; (80019f8 <HAL_RCC_GetPCLK2Freq+0x20>)
- 80019e4:	689b      	ldr	r3, [r3, #8]
- 80019e6:	0b5b      	lsrs	r3, r3, #13
- 80019e8:	f003 0307 	and.w	r3, r3, #7
- 80019ec:	4a03      	ldr	r2, [pc, #12]	; (80019fc <HAL_RCC_GetPCLK2Freq+0x24>)
- 80019ee:	5cd3      	ldrb	r3, [r2, r3]
- 80019f0:	fa21 f303 	lsr.w	r3, r1, r3
+ 8001a10:	f7ff ffdc 	bl	80019cc <HAL_RCC_GetHCLKFreq>
+ 8001a14:	4601      	mov	r1, r0
+ 8001a16:	4b05      	ldr	r3, [pc, #20]	; (8001a2c <HAL_RCC_GetPCLK2Freq+0x20>)
+ 8001a18:	689b      	ldr	r3, [r3, #8]
+ 8001a1a:	0b5b      	lsrs	r3, r3, #13
+ 8001a1c:	f003 0307 	and.w	r3, r3, #7
+ 8001a20:	4a03      	ldr	r2, [pc, #12]	; (8001a30 <HAL_RCC_GetPCLK2Freq+0x24>)
+ 8001a22:	5cd3      	ldrb	r3, [r2, r3]
+ 8001a24:	fa21 f303 	lsr.w	r3, r1, r3
 }
- 80019f4:	4618      	mov	r0, r3
- 80019f6:	bd80      	pop	{r7, pc}
- 80019f8:	40023800 	.word	0x40023800
- 80019fc:	0800378c 	.word	0x0800378c
+ 8001a28:	4618      	mov	r0, r3
+ 8001a2a:	bd80      	pop	{r7, pc}
+ 8001a2c:	40023800 	.word	0x40023800
+ 8001a30:	08004450 	.word	0x08004450
 
-08001a00 <HAL_RCCEx_PeriphCLKConfig>:
+08001a34 <HAL_RCCEx_PeriphCLKConfig>:
   *         the backup registers) are set to their reset values.
   *
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
 {
- 8001a00:	b580      	push	{r7, lr}
- 8001a02:	b088      	sub	sp, #32
- 8001a04:	af00      	add	r7, sp, #0
- 8001a06:	6078      	str	r0, [r7, #4]
+ 8001a34:	b580      	push	{r7, lr}
+ 8001a36:	b088      	sub	sp, #32
+ 8001a38:	af00      	add	r7, sp, #0
+ 8001a3a:	6078      	str	r0, [r7, #4]
   uint32_t tickstart = 0;
- 8001a08:	2300      	movs	r3, #0
- 8001a0a:	617b      	str	r3, [r7, #20]
+ 8001a3c:	2300      	movs	r3, #0
+ 8001a3e:	617b      	str	r3, [r7, #20]
   uint32_t tmpreg0 = 0;
- 8001a0c:	2300      	movs	r3, #0
- 8001a0e:	613b      	str	r3, [r7, #16]
+ 8001a40:	2300      	movs	r3, #0
+ 8001a42:	613b      	str	r3, [r7, #16]
   uint32_t tmpreg1 = 0;
- 8001a10:	2300      	movs	r3, #0
- 8001a12:	60fb      	str	r3, [r7, #12]
+ 8001a44:	2300      	movs	r3, #0
+ 8001a46:	60fb      	str	r3, [r7, #12]
   uint32_t plli2sused = 0;
- 8001a14:	2300      	movs	r3, #0
- 8001a16:	61fb      	str	r3, [r7, #28]
+ 8001a48:	2300      	movs	r3, #0
+ 8001a4a:	61fb      	str	r3, [r7, #28]
   uint32_t pllsaiused = 0;
- 8001a18:	2300      	movs	r3, #0
- 8001a1a:	61bb      	str	r3, [r7, #24]
+ 8001a4c:	2300      	movs	r3, #0
+ 8001a4e:	61bb      	str	r3, [r7, #24]
 
   /* Check the parameters */
   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
 
   /*----------------------------------- I2S configuration ----------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
- 8001a1c:	687b      	ldr	r3, [r7, #4]
- 8001a1e:	681b      	ldr	r3, [r3, #0]
- 8001a20:	f003 0301 	and.w	r3, r3, #1
- 8001a24:	2b00      	cmp	r3, #0
- 8001a26:	d012      	beq.n	8001a4e <HAL_RCCEx_PeriphCLKConfig+0x4e>
+ 8001a50:	687b      	ldr	r3, [r7, #4]
+ 8001a52:	681b      	ldr	r3, [r3, #0]
+ 8001a54:	f003 0301 	and.w	r3, r3, #1
+ 8001a58:	2b00      	cmp	r3, #0
+ 8001a5a:	d012      	beq.n	8001a82 <HAL_RCCEx_PeriphCLKConfig+0x4e>
   {
     /* Check the parameters */
     assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
 
     /* Configure I2S Clock source */
     __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
- 8001a28:	4b69      	ldr	r3, [pc, #420]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001a2a:	689b      	ldr	r3, [r3, #8]
- 8001a2c:	4a68      	ldr	r2, [pc, #416]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001a2e:	f423 0300 	bic.w	r3, r3, #8388608	; 0x800000
- 8001a32:	6093      	str	r3, [r2, #8]
- 8001a34:	4b66      	ldr	r3, [pc, #408]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001a36:	689a      	ldr	r2, [r3, #8]
- 8001a38:	687b      	ldr	r3, [r7, #4]
- 8001a3a:	6b5b      	ldr	r3, [r3, #52]	; 0x34
- 8001a3c:	4964      	ldr	r1, [pc, #400]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001a3e:	4313      	orrs	r3, r2
- 8001a40:	608b      	str	r3, [r1, #8]
+ 8001a5c:	4b69      	ldr	r3, [pc, #420]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001a5e:	689b      	ldr	r3, [r3, #8]
+ 8001a60:	4a68      	ldr	r2, [pc, #416]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001a62:	f423 0300 	bic.w	r3, r3, #8388608	; 0x800000
+ 8001a66:	6093      	str	r3, [r2, #8]
+ 8001a68:	4b66      	ldr	r3, [pc, #408]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001a6a:	689a      	ldr	r2, [r3, #8]
+ 8001a6c:	687b      	ldr	r3, [r7, #4]
+ 8001a6e:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 8001a70:	4964      	ldr	r1, [pc, #400]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001a72:	4313      	orrs	r3, r2
+ 8001a74:	608b      	str	r3, [r1, #8]
 
     /* Enable the PLLI2S when it's used as clock source for I2S */
     if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
- 8001a42:	687b      	ldr	r3, [r7, #4]
- 8001a44:	6b5b      	ldr	r3, [r3, #52]	; 0x34
- 8001a46:	2b00      	cmp	r3, #0
- 8001a48:	d101      	bne.n	8001a4e <HAL_RCCEx_PeriphCLKConfig+0x4e>
+ 8001a76:	687b      	ldr	r3, [r7, #4]
+ 8001a78:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 8001a7a:	2b00      	cmp	r3, #0
+ 8001a7c:	d101      	bne.n	8001a82 <HAL_RCCEx_PeriphCLKConfig+0x4e>
     {
       plli2sused = 1;
- 8001a4a:	2301      	movs	r3, #1
- 8001a4c:	61fb      	str	r3, [r7, #28]
+ 8001a7e:	2301      	movs	r3, #1
+ 8001a80:	61fb      	str	r3, [r7, #28]
     }
   }
 
   /*------------------------------------ SAI1 configuration --------------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
- 8001a4e:	687b      	ldr	r3, [r7, #4]
- 8001a50:	681b      	ldr	r3, [r3, #0]
- 8001a52:	f403 2300 	and.w	r3, r3, #524288	; 0x80000
- 8001a56:	2b00      	cmp	r3, #0
- 8001a58:	d017      	beq.n	8001a8a <HAL_RCCEx_PeriphCLKConfig+0x8a>
+ 8001a82:	687b      	ldr	r3, [r7, #4]
+ 8001a84:	681b      	ldr	r3, [r3, #0]
+ 8001a86:	f403 2300 	and.w	r3, r3, #524288	; 0x80000
+ 8001a8a:	2b00      	cmp	r3, #0
+ 8001a8c:	d017      	beq.n	8001abe <HAL_RCCEx_PeriphCLKConfig+0x8a>
   {
     /* Check the parameters */
     assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
 
     /* Configure SAI1 Clock source */
     __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
- 8001a5a:	4b5d      	ldr	r3, [pc, #372]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001a5c:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
- 8001a60:	f423 1240 	bic.w	r2, r3, #3145728	; 0x300000
- 8001a64:	687b      	ldr	r3, [r7, #4]
- 8001a66:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
- 8001a68:	4959      	ldr	r1, [pc, #356]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001a6a:	4313      	orrs	r3, r2
- 8001a6c:	f8c1 308c 	str.w	r3, [r1, #140]	; 0x8c
+ 8001a8e:	4b5d      	ldr	r3, [pc, #372]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001a90:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
+ 8001a94:	f423 1240 	bic.w	r2, r3, #3145728	; 0x300000
+ 8001a98:	687b      	ldr	r3, [r7, #4]
+ 8001a9a:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8001a9c:	4959      	ldr	r1, [pc, #356]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001a9e:	4313      	orrs	r3, r2
+ 8001aa0:	f8c1 308c 	str.w	r3, [r1, #140]	; 0x8c
     /* Enable the PLLI2S when it's used as clock source for SAI */
     if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
- 8001a70:	687b      	ldr	r3, [r7, #4]
- 8001a72:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
- 8001a74:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
- 8001a78:	d101      	bne.n	8001a7e <HAL_RCCEx_PeriphCLKConfig+0x7e>
+ 8001aa4:	687b      	ldr	r3, [r7, #4]
+ 8001aa6:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8001aa8:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
+ 8001aac:	d101      	bne.n	8001ab2 <HAL_RCCEx_PeriphCLKConfig+0x7e>
     {
       plli2sused = 1;
- 8001a7a:	2301      	movs	r3, #1
- 8001a7c:	61fb      	str	r3, [r7, #28]
+ 8001aae:	2301      	movs	r3, #1
+ 8001ab0:	61fb      	str	r3, [r7, #28]
     }
     /* Enable the PLLSAI when it's used as clock source for SAI */
     if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
- 8001a7e:	687b      	ldr	r3, [r7, #4]
- 8001a80:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
- 8001a82:	2b00      	cmp	r3, #0
- 8001a84:	d101      	bne.n	8001a8a <HAL_RCCEx_PeriphCLKConfig+0x8a>
+ 8001ab2:	687b      	ldr	r3, [r7, #4]
+ 8001ab4:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8001ab6:	2b00      	cmp	r3, #0
+ 8001ab8:	d101      	bne.n	8001abe <HAL_RCCEx_PeriphCLKConfig+0x8a>
     {
       pllsaiused = 1;
- 8001a86:	2301      	movs	r3, #1
- 8001a88:	61bb      	str	r3, [r7, #24]
+ 8001aba:	2301      	movs	r3, #1
+ 8001abc:	61bb      	str	r3, [r7, #24]
     }
   }
 
   /*------------------------------------ SAI2 configuration --------------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
- 8001a8a:	687b      	ldr	r3, [r7, #4]
- 8001a8c:	681b      	ldr	r3, [r3, #0]
- 8001a8e:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
- 8001a92:	2b00      	cmp	r3, #0
- 8001a94:	d017      	beq.n	8001ac6 <HAL_RCCEx_PeriphCLKConfig+0xc6>
+ 8001abe:	687b      	ldr	r3, [r7, #4]
+ 8001ac0:	681b      	ldr	r3, [r3, #0]
+ 8001ac2:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
+ 8001ac6:	2b00      	cmp	r3, #0
+ 8001ac8:	d017      	beq.n	8001afa <HAL_RCCEx_PeriphCLKConfig+0xc6>
   {
     /* Check the parameters */
     assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
 
     /* Configure SAI2 Clock source */
     __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
- 8001a96:	4b4e      	ldr	r3, [pc, #312]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001a98:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
- 8001a9c:	f423 0240 	bic.w	r2, r3, #12582912	; 0xc00000
- 8001aa0:	687b      	ldr	r3, [r7, #4]
- 8001aa2:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 8001aa4:	494a      	ldr	r1, [pc, #296]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001aa6:	4313      	orrs	r3, r2
- 8001aa8:	f8c1 308c 	str.w	r3, [r1, #140]	; 0x8c
+ 8001aca:	4b4e      	ldr	r3, [pc, #312]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001acc:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
+ 8001ad0:	f423 0240 	bic.w	r2, r3, #12582912	; 0xc00000
+ 8001ad4:	687b      	ldr	r3, [r7, #4]
+ 8001ad6:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8001ad8:	494a      	ldr	r1, [pc, #296]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001ada:	4313      	orrs	r3, r2
+ 8001adc:	f8c1 308c 	str.w	r3, [r1, #140]	; 0x8c
 
     /* Enable the PLLI2S when it's used as clock source for SAI */
     if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
- 8001aac:	687b      	ldr	r3, [r7, #4]
- 8001aae:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 8001ab0:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
- 8001ab4:	d101      	bne.n	8001aba <HAL_RCCEx_PeriphCLKConfig+0xba>
+ 8001ae0:	687b      	ldr	r3, [r7, #4]
+ 8001ae2:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8001ae4:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
+ 8001ae8:	d101      	bne.n	8001aee <HAL_RCCEx_PeriphCLKConfig+0xba>
     {
       plli2sused = 1;
- 8001ab6:	2301      	movs	r3, #1
- 8001ab8:	61fb      	str	r3, [r7, #28]
+ 8001aea:	2301      	movs	r3, #1
+ 8001aec:	61fb      	str	r3, [r7, #28]
     }
     /* Enable the PLLSAI when it's used as clock source for SAI */
     if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
- 8001aba:	687b      	ldr	r3, [r7, #4]
- 8001abc:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 8001abe:	2b00      	cmp	r3, #0
- 8001ac0:	d101      	bne.n	8001ac6 <HAL_RCCEx_PeriphCLKConfig+0xc6>
+ 8001aee:	687b      	ldr	r3, [r7, #4]
+ 8001af0:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8001af2:	2b00      	cmp	r3, #0
+ 8001af4:	d101      	bne.n	8001afa <HAL_RCCEx_PeriphCLKConfig+0xc6>
     {
       pllsaiused = 1;
- 8001ac2:	2301      	movs	r3, #1
- 8001ac4:	61bb      	str	r3, [r7, #24]
+ 8001af6:	2301      	movs	r3, #1
+ 8001af8:	61bb      	str	r3, [r7, #24]
     }
   }
 
   /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
- 8001ac6:	687b      	ldr	r3, [r7, #4]
- 8001ac8:	681b      	ldr	r3, [r3, #0]
- 8001aca:	f003 7380 	and.w	r3, r3, #16777216	; 0x1000000
- 8001ace:	2b00      	cmp	r3, #0
- 8001ad0:	d001      	beq.n	8001ad6 <HAL_RCCEx_PeriphCLKConfig+0xd6>
+ 8001afa:	687b      	ldr	r3, [r7, #4]
+ 8001afc:	681b      	ldr	r3, [r3, #0]
+ 8001afe:	f003 7380 	and.w	r3, r3, #16777216	; 0x1000000
+ 8001b02:	2b00      	cmp	r3, #0
+ 8001b04:	d001      	beq.n	8001b0a <HAL_RCCEx_PeriphCLKConfig+0xd6>
   {
       plli2sused = 1;
- 8001ad2:	2301      	movs	r3, #1
- 8001ad4:	61fb      	str	r3, [r7, #28]
+ 8001b06:	2301      	movs	r3, #1
+ 8001b08:	61fb      	str	r3, [r7, #28]
   }
 
   /*------------------------------------ RTC configuration --------------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
- 8001ad6:	687b      	ldr	r3, [r7, #4]
- 8001ad8:	681b      	ldr	r3, [r3, #0]
- 8001ada:	f003 0320 	and.w	r3, r3, #32
- 8001ade:	2b00      	cmp	r3, #0
- 8001ae0:	f000 808b 	beq.w	8001bfa <HAL_RCCEx_PeriphCLKConfig+0x1fa>
+ 8001b0a:	687b      	ldr	r3, [r7, #4]
+ 8001b0c:	681b      	ldr	r3, [r3, #0]
+ 8001b0e:	f003 0320 	and.w	r3, r3, #32
+ 8001b12:	2b00      	cmp	r3, #0
+ 8001b14:	f000 808b 	beq.w	8001c2e <HAL_RCCEx_PeriphCLKConfig+0x1fa>
   {
     /* Check for RTC Parameters used to output RTCCLK */
     assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
 
     /* Enable Power Clock*/
     __HAL_RCC_PWR_CLK_ENABLE();
- 8001ae4:	4b3a      	ldr	r3, [pc, #232]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001ae6:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 8001ae8:	4a39      	ldr	r2, [pc, #228]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001aea:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
- 8001aee:	6413      	str	r3, [r2, #64]	; 0x40
- 8001af0:	4b37      	ldr	r3, [pc, #220]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001af2:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 8001af4:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
- 8001af8:	60bb      	str	r3, [r7, #8]
- 8001afa:	68bb      	ldr	r3, [r7, #8]
+ 8001b18:	4b3a      	ldr	r3, [pc, #232]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b1a:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8001b1c:	4a39      	ldr	r2, [pc, #228]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b1e:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
+ 8001b22:	6413      	str	r3, [r2, #64]	; 0x40
+ 8001b24:	4b37      	ldr	r3, [pc, #220]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b26:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8001b28:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
+ 8001b2c:	60bb      	str	r3, [r7, #8]
+ 8001b2e:	68bb      	ldr	r3, [r7, #8]
 
     /* Enable write access to Backup domain */
     PWR->CR1 |= PWR_CR1_DBP;
- 8001afc:	4b35      	ldr	r3, [pc, #212]	; (8001bd4 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8001afe:	681b      	ldr	r3, [r3, #0]
- 8001b00:	4a34      	ldr	r2, [pc, #208]	; (8001bd4 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8001b02:	f443 7380 	orr.w	r3, r3, #256	; 0x100
- 8001b06:	6013      	str	r3, [r2, #0]
+ 8001b30:	4b35      	ldr	r3, [pc, #212]	; (8001c08 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
+ 8001b32:	681b      	ldr	r3, [r3, #0]
+ 8001b34:	4a34      	ldr	r2, [pc, #208]	; (8001c08 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
+ 8001b36:	f443 7380 	orr.w	r3, r3, #256	; 0x100
+ 8001b3a:	6013      	str	r3, [r2, #0]
 
     /* Get Start Tick*/
     tickstart = HAL_GetTick();
- 8001b08:	f7fe fd68 	bl	80005dc <HAL_GetTick>
- 8001b0c:	6178      	str	r0, [r7, #20]
+ 8001b3c:	f7fe fd4e 	bl	80005dc <HAL_GetTick>
+ 8001b40:	6178      	str	r0, [r7, #20]
 
     /* Wait for Backup domain Write protection disable */
     while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- 8001b0e:	e008      	b.n	8001b22 <HAL_RCCEx_PeriphCLKConfig+0x122>
+ 8001b42:	e008      	b.n	8001b56 <HAL_RCCEx_PeriphCLKConfig+0x122>
     {
       if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- 8001b10:	f7fe fd64 	bl	80005dc <HAL_GetTick>
- 8001b14:	4602      	mov	r2, r0
- 8001b16:	697b      	ldr	r3, [r7, #20]
- 8001b18:	1ad3      	subs	r3, r2, r3
- 8001b1a:	2b64      	cmp	r3, #100	; 0x64
- 8001b1c:	d901      	bls.n	8001b22 <HAL_RCCEx_PeriphCLKConfig+0x122>
+ 8001b44:	f7fe fd4a 	bl	80005dc <HAL_GetTick>
+ 8001b48:	4602      	mov	r2, r0
+ 8001b4a:	697b      	ldr	r3, [r7, #20]
+ 8001b4c:	1ad3      	subs	r3, r2, r3
+ 8001b4e:	2b64      	cmp	r3, #100	; 0x64
+ 8001b50:	d901      	bls.n	8001b56 <HAL_RCCEx_PeriphCLKConfig+0x122>
       {
         return HAL_TIMEOUT;
- 8001b1e:	2303      	movs	r3, #3
- 8001b20:	e38d      	b.n	800223e <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 8001b52:	2303      	movs	r3, #3
+ 8001b54:	e38d      	b.n	8002272 <HAL_RCCEx_PeriphCLKConfig+0x83e>
     while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- 8001b22:	4b2c      	ldr	r3, [pc, #176]	; (8001bd4 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8001b24:	681b      	ldr	r3, [r3, #0]
- 8001b26:	f403 7380 	and.w	r3, r3, #256	; 0x100
- 8001b2a:	2b00      	cmp	r3, #0
- 8001b2c:	d0f0      	beq.n	8001b10 <HAL_RCCEx_PeriphCLKConfig+0x110>
+ 8001b56:	4b2c      	ldr	r3, [pc, #176]	; (8001c08 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
+ 8001b58:	681b      	ldr	r3, [r3, #0]
+ 8001b5a:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 8001b5e:	2b00      	cmp	r3, #0
+ 8001b60:	d0f0      	beq.n	8001b44 <HAL_RCCEx_PeriphCLKConfig+0x110>
       }
     }
 
     /* Reset the Backup domain only if the RTC Clock source selection is modified */
     tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
- 8001b2e:	4b28      	ldr	r3, [pc, #160]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001b30:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8001b32:	f403 7340 	and.w	r3, r3, #768	; 0x300
- 8001b36:	613b      	str	r3, [r7, #16]
+ 8001b62:	4b28      	ldr	r3, [pc, #160]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b64:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8001b66:	f403 7340 	and.w	r3, r3, #768	; 0x300
+ 8001b6a:	613b      	str	r3, [r7, #16]
 
     if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
- 8001b38:	693b      	ldr	r3, [r7, #16]
- 8001b3a:	2b00      	cmp	r3, #0
- 8001b3c:	d035      	beq.n	8001baa <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- 8001b3e:	687b      	ldr	r3, [r7, #4]
- 8001b40:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8001b42:	f403 7340 	and.w	r3, r3, #768	; 0x300
- 8001b46:	693a      	ldr	r2, [r7, #16]
- 8001b48:	429a      	cmp	r2, r3
- 8001b4a:	d02e      	beq.n	8001baa <HAL_RCCEx_PeriphCLKConfig+0x1aa>
+ 8001b6c:	693b      	ldr	r3, [r7, #16]
+ 8001b6e:	2b00      	cmp	r3, #0
+ 8001b70:	d035      	beq.n	8001bde <HAL_RCCEx_PeriphCLKConfig+0x1aa>
+ 8001b72:	687b      	ldr	r3, [r7, #4]
+ 8001b74:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8001b76:	f403 7340 	and.w	r3, r3, #768	; 0x300
+ 8001b7a:	693a      	ldr	r2, [r7, #16]
+ 8001b7c:	429a      	cmp	r2, r3
+ 8001b7e:	d02e      	beq.n	8001bde <HAL_RCCEx_PeriphCLKConfig+0x1aa>
     {
       /* Store the content of BDCR register before the reset of Backup Domain */
       tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
- 8001b4c:	4b20      	ldr	r3, [pc, #128]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001b4e:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8001b50:	f423 7340 	bic.w	r3, r3, #768	; 0x300
- 8001b54:	613b      	str	r3, [r7, #16]
+ 8001b80:	4b20      	ldr	r3, [pc, #128]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b82:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8001b84:	f423 7340 	bic.w	r3, r3, #768	; 0x300
+ 8001b88:	613b      	str	r3, [r7, #16]
 
       /* RTC Clock selection can be changed only if the Backup Domain is reset */
       __HAL_RCC_BACKUPRESET_FORCE();
- 8001b56:	4b1e      	ldr	r3, [pc, #120]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001b58:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8001b5a:	4a1d      	ldr	r2, [pc, #116]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001b5c:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
- 8001b60:	6713      	str	r3, [r2, #112]	; 0x70
+ 8001b8a:	4b1e      	ldr	r3, [pc, #120]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b8c:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8001b8e:	4a1d      	ldr	r2, [pc, #116]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b90:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
+ 8001b94:	6713      	str	r3, [r2, #112]	; 0x70
       __HAL_RCC_BACKUPRESET_RELEASE();
- 8001b62:	4b1b      	ldr	r3, [pc, #108]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001b64:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8001b66:	4a1a      	ldr	r2, [pc, #104]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001b68:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
- 8001b6c:	6713      	str	r3, [r2, #112]	; 0x70
+ 8001b96:	4b1b      	ldr	r3, [pc, #108]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b98:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8001b9a:	4a1a      	ldr	r2, [pc, #104]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b9c:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
+ 8001ba0:	6713      	str	r3, [r2, #112]	; 0x70
 
       /* Restore the Content of BDCR register */
       RCC->BDCR = tmpreg0;
- 8001b6e:	4a18      	ldr	r2, [pc, #96]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001b70:	693b      	ldr	r3, [r7, #16]
- 8001b72:	6713      	str	r3, [r2, #112]	; 0x70
+ 8001ba2:	4a18      	ldr	r2, [pc, #96]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001ba4:	693b      	ldr	r3, [r7, #16]
+ 8001ba6:	6713      	str	r3, [r2, #112]	; 0x70
 
       /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
       if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
- 8001b74:	4b16      	ldr	r3, [pc, #88]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001b76:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8001b78:	f003 0301 	and.w	r3, r3, #1
- 8001b7c:	2b01      	cmp	r3, #1
- 8001b7e:	d114      	bne.n	8001baa <HAL_RCCEx_PeriphCLKConfig+0x1aa>
+ 8001ba8:	4b16      	ldr	r3, [pc, #88]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001baa:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8001bac:	f003 0301 	and.w	r3, r3, #1
+ 8001bb0:	2b01      	cmp	r3, #1
+ 8001bb2:	d114      	bne.n	8001bde <HAL_RCCEx_PeriphCLKConfig+0x1aa>
       {
         /* Get Start Tick*/
         tickstart = HAL_GetTick();
- 8001b80:	f7fe fd2c 	bl	80005dc <HAL_GetTick>
- 8001b84:	6178      	str	r0, [r7, #20]
+ 8001bb4:	f7fe fd12 	bl	80005dc <HAL_GetTick>
+ 8001bb8:	6178      	str	r0, [r7, #20]
 
         /* Wait till LSE is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8001b86:	e00a      	b.n	8001b9e <HAL_RCCEx_PeriphCLKConfig+0x19e>
+ 8001bba:	e00a      	b.n	8001bd2 <HAL_RCCEx_PeriphCLKConfig+0x19e>
         {
           if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8001b88:	f7fe fd28 	bl	80005dc <HAL_GetTick>
- 8001b8c:	4602      	mov	r2, r0
- 8001b8e:	697b      	ldr	r3, [r7, #20]
- 8001b90:	1ad3      	subs	r3, r2, r3
- 8001b92:	f241 3288 	movw	r2, #5000	; 0x1388
- 8001b96:	4293      	cmp	r3, r2
- 8001b98:	d901      	bls.n	8001b9e <HAL_RCCEx_PeriphCLKConfig+0x19e>
+ 8001bbc:	f7fe fd0e 	bl	80005dc <HAL_GetTick>
+ 8001bc0:	4602      	mov	r2, r0
+ 8001bc2:	697b      	ldr	r3, [r7, #20]
+ 8001bc4:	1ad3      	subs	r3, r2, r3
+ 8001bc6:	f241 3288 	movw	r2, #5000	; 0x1388
+ 8001bca:	4293      	cmp	r3, r2
+ 8001bcc:	d901      	bls.n	8001bd2 <HAL_RCCEx_PeriphCLKConfig+0x19e>
           {
             return HAL_TIMEOUT;
- 8001b9a:	2303      	movs	r3, #3
- 8001b9c:	e34f      	b.n	800223e <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 8001bce:	2303      	movs	r3, #3
+ 8001bd0:	e34f      	b.n	8002272 <HAL_RCCEx_PeriphCLKConfig+0x83e>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8001b9e:	4b0c      	ldr	r3, [pc, #48]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001ba0:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8001ba2:	f003 0302 	and.w	r3, r3, #2
- 8001ba6:	2b00      	cmp	r3, #0
- 8001ba8:	d0ee      	beq.n	8001b88 <HAL_RCCEx_PeriphCLKConfig+0x188>
+ 8001bd2:	4b0c      	ldr	r3, [pc, #48]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001bd4:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8001bd6:	f003 0302 	and.w	r3, r3, #2
+ 8001bda:	2b00      	cmp	r3, #0
+ 8001bdc:	d0ee      	beq.n	8001bbc <HAL_RCCEx_PeriphCLKConfig+0x188>
           }
         }
       }
     }
     __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
- 8001baa:	687b      	ldr	r3, [r7, #4]
- 8001bac:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8001bae:	f403 7340 	and.w	r3, r3, #768	; 0x300
- 8001bb2:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
- 8001bb6:	d111      	bne.n	8001bdc <HAL_RCCEx_PeriphCLKConfig+0x1dc>
- 8001bb8:	4b05      	ldr	r3, [pc, #20]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001bba:	689b      	ldr	r3, [r3, #8]
- 8001bbc:	f423 12f8 	bic.w	r2, r3, #2031616	; 0x1f0000
- 8001bc0:	687b      	ldr	r3, [r7, #4]
- 8001bc2:	6b19      	ldr	r1, [r3, #48]	; 0x30
- 8001bc4:	4b04      	ldr	r3, [pc, #16]	; (8001bd8 <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
- 8001bc6:	400b      	ands	r3, r1
- 8001bc8:	4901      	ldr	r1, [pc, #4]	; (8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001bca:	4313      	orrs	r3, r2
- 8001bcc:	608b      	str	r3, [r1, #8]
- 8001bce:	e00b      	b.n	8001be8 <HAL_RCCEx_PeriphCLKConfig+0x1e8>
- 8001bd0:	40023800 	.word	0x40023800
- 8001bd4:	40007000 	.word	0x40007000
- 8001bd8:	0ffffcff 	.word	0x0ffffcff
- 8001bdc:	4bb3      	ldr	r3, [pc, #716]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001bde:	689b      	ldr	r3, [r3, #8]
- 8001be0:	4ab2      	ldr	r2, [pc, #712]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001be2:	f423 13f8 	bic.w	r3, r3, #2031616	; 0x1f0000
- 8001be6:	6093      	str	r3, [r2, #8]
- 8001be8:	4bb0      	ldr	r3, [pc, #704]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001bea:	6f1a      	ldr	r2, [r3, #112]	; 0x70
- 8001bec:	687b      	ldr	r3, [r7, #4]
- 8001bee:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8001bf0:	f3c3 030b 	ubfx	r3, r3, #0, #12
- 8001bf4:	49ad      	ldr	r1, [pc, #692]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001bf6:	4313      	orrs	r3, r2
- 8001bf8:	670b      	str	r3, [r1, #112]	; 0x70
+ 8001bde:	687b      	ldr	r3, [r7, #4]
+ 8001be0:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8001be2:	f403 7340 	and.w	r3, r3, #768	; 0x300
+ 8001be6:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
+ 8001bea:	d111      	bne.n	8001c10 <HAL_RCCEx_PeriphCLKConfig+0x1dc>
+ 8001bec:	4b05      	ldr	r3, [pc, #20]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001bee:	689b      	ldr	r3, [r3, #8]
+ 8001bf0:	f423 12f8 	bic.w	r2, r3, #2031616	; 0x1f0000
+ 8001bf4:	687b      	ldr	r3, [r7, #4]
+ 8001bf6:	6b19      	ldr	r1, [r3, #48]	; 0x30
+ 8001bf8:	4b04      	ldr	r3, [pc, #16]	; (8001c0c <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
+ 8001bfa:	400b      	ands	r3, r1
+ 8001bfc:	4901      	ldr	r1, [pc, #4]	; (8001c04 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001bfe:	4313      	orrs	r3, r2
+ 8001c00:	608b      	str	r3, [r1, #8]
+ 8001c02:	e00b      	b.n	8001c1c <HAL_RCCEx_PeriphCLKConfig+0x1e8>
+ 8001c04:	40023800 	.word	0x40023800
+ 8001c08:	40007000 	.word	0x40007000
+ 8001c0c:	0ffffcff 	.word	0x0ffffcff
+ 8001c10:	4bb3      	ldr	r3, [pc, #716]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c12:	689b      	ldr	r3, [r3, #8]
+ 8001c14:	4ab2      	ldr	r2, [pc, #712]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c16:	f423 13f8 	bic.w	r3, r3, #2031616	; 0x1f0000
+ 8001c1a:	6093      	str	r3, [r2, #8]
+ 8001c1c:	4bb0      	ldr	r3, [pc, #704]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c1e:	6f1a      	ldr	r2, [r3, #112]	; 0x70
+ 8001c20:	687b      	ldr	r3, [r7, #4]
+ 8001c22:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8001c24:	f3c3 030b 	ubfx	r3, r3, #0, #12
+ 8001c28:	49ad      	ldr	r1, [pc, #692]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c2a:	4313      	orrs	r3, r2
+ 8001c2c:	670b      	str	r3, [r1, #112]	; 0x70
   }
 
   /*------------------------------------ TIM configuration --------------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
- 8001bfa:	687b      	ldr	r3, [r7, #4]
- 8001bfc:	681b      	ldr	r3, [r3, #0]
- 8001bfe:	f003 0310 	and.w	r3, r3, #16
- 8001c02:	2b00      	cmp	r3, #0
- 8001c04:	d010      	beq.n	8001c28 <HAL_RCCEx_PeriphCLKConfig+0x228>
+ 8001c2e:	687b      	ldr	r3, [r7, #4]
+ 8001c30:	681b      	ldr	r3, [r3, #0]
+ 8001c32:	f003 0310 	and.w	r3, r3, #16
+ 8001c36:	2b00      	cmp	r3, #0
+ 8001c38:	d010      	beq.n	8001c5c <HAL_RCCEx_PeriphCLKConfig+0x228>
   {
     /* Check the parameters */
     assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
 
     /* Configure Timer Prescaler */
     __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
- 8001c06:	4ba9      	ldr	r3, [pc, #676]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c08:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
- 8001c0c:	4aa7      	ldr	r2, [pc, #668]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c0e:	f023 7380 	bic.w	r3, r3, #16777216	; 0x1000000
- 8001c12:	f8c2 308c 	str.w	r3, [r2, #140]	; 0x8c
- 8001c16:	4ba5      	ldr	r3, [pc, #660]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c18:	f8d3 208c 	ldr.w	r2, [r3, #140]	; 0x8c
- 8001c1c:	687b      	ldr	r3, [r7, #4]
- 8001c1e:	6b9b      	ldr	r3, [r3, #56]	; 0x38
- 8001c20:	49a2      	ldr	r1, [pc, #648]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c22:	4313      	orrs	r3, r2
- 8001c24:	f8c1 308c 	str.w	r3, [r1, #140]	; 0x8c
+ 8001c3a:	4ba9      	ldr	r3, [pc, #676]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c3c:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
+ 8001c40:	4aa7      	ldr	r2, [pc, #668]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c42:	f023 7380 	bic.w	r3, r3, #16777216	; 0x1000000
+ 8001c46:	f8c2 308c 	str.w	r3, [r2, #140]	; 0x8c
+ 8001c4a:	4ba5      	ldr	r3, [pc, #660]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c4c:	f8d3 208c 	ldr.w	r2, [r3, #140]	; 0x8c
+ 8001c50:	687b      	ldr	r3, [r7, #4]
+ 8001c52:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 8001c54:	49a2      	ldr	r1, [pc, #648]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c56:	4313      	orrs	r3, r2
+ 8001c58:	f8c1 308c 	str.w	r3, [r1, #140]	; 0x8c
   }
 
   /*-------------------------------------- I2C1 Configuration -----------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
- 8001c28:	687b      	ldr	r3, [r7, #4]
- 8001c2a:	681b      	ldr	r3, [r3, #0]
- 8001c2c:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
- 8001c30:	2b00      	cmp	r3, #0
- 8001c32:	d00a      	beq.n	8001c4a <HAL_RCCEx_PeriphCLKConfig+0x24a>
+ 8001c5c:	687b      	ldr	r3, [r7, #4]
+ 8001c5e:	681b      	ldr	r3, [r3, #0]
+ 8001c60:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
+ 8001c64:	2b00      	cmp	r3, #0
+ 8001c66:	d00a      	beq.n	8001c7e <HAL_RCCEx_PeriphCLKConfig+0x24a>
   {
     /* Check the parameters */
     assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
 
     /* Configure the I2C1 clock source */
     __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
- 8001c34:	4b9d      	ldr	r3, [pc, #628]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c36:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8001c3a:	f423 3240 	bic.w	r2, r3, #196608	; 0x30000
- 8001c3e:	687b      	ldr	r3, [r7, #4]
- 8001c40:	6e5b      	ldr	r3, [r3, #100]	; 0x64
- 8001c42:	499a      	ldr	r1, [pc, #616]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c44:	4313      	orrs	r3, r2
- 8001c46:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
+ 8001c68:	4b9d      	ldr	r3, [pc, #628]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c6a:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8001c6e:	f423 3240 	bic.w	r2, r3, #196608	; 0x30000
+ 8001c72:	687b      	ldr	r3, [r7, #4]
+ 8001c74:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 8001c76:	499a      	ldr	r1, [pc, #616]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c78:	4313      	orrs	r3, r2
+ 8001c7a:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
   }
 
   /*-------------------------------------- I2C2 Configuration -----------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
- 8001c4a:	687b      	ldr	r3, [r7, #4]
- 8001c4c:	681b      	ldr	r3, [r3, #0]
- 8001c4e:	f403 4300 	and.w	r3, r3, #32768	; 0x8000
- 8001c52:	2b00      	cmp	r3, #0
- 8001c54:	d00a      	beq.n	8001c6c <HAL_RCCEx_PeriphCLKConfig+0x26c>
+ 8001c7e:	687b      	ldr	r3, [r7, #4]
+ 8001c80:	681b      	ldr	r3, [r3, #0]
+ 8001c82:	f403 4300 	and.w	r3, r3, #32768	; 0x8000
+ 8001c86:	2b00      	cmp	r3, #0
+ 8001c88:	d00a      	beq.n	8001ca0 <HAL_RCCEx_PeriphCLKConfig+0x26c>
   {
     /* Check the parameters */
     assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
 
     /* Configure the I2C2 clock source */
     __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
- 8001c56:	4b95      	ldr	r3, [pc, #596]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c58:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8001c5c:	f423 2240 	bic.w	r2, r3, #786432	; 0xc0000
- 8001c60:	687b      	ldr	r3, [r7, #4]
- 8001c62:	6e9b      	ldr	r3, [r3, #104]	; 0x68
- 8001c64:	4991      	ldr	r1, [pc, #580]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c66:	4313      	orrs	r3, r2
- 8001c68:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
+ 8001c8a:	4b95      	ldr	r3, [pc, #596]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c8c:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8001c90:	f423 2240 	bic.w	r2, r3, #786432	; 0xc0000
+ 8001c94:	687b      	ldr	r3, [r7, #4]
+ 8001c96:	6e9b      	ldr	r3, [r3, #104]	; 0x68
+ 8001c98:	4991      	ldr	r1, [pc, #580]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c9a:	4313      	orrs	r3, r2
+ 8001c9c:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
   }
 
   /*-------------------------------------- I2C3 Configuration -----------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
- 8001c6c:	687b      	ldr	r3, [r7, #4]
- 8001c6e:	681b      	ldr	r3, [r3, #0]
- 8001c70:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
- 8001c74:	2b00      	cmp	r3, #0
- 8001c76:	d00a      	beq.n	8001c8e <HAL_RCCEx_PeriphCLKConfig+0x28e>
+ 8001ca0:	687b      	ldr	r3, [r7, #4]
+ 8001ca2:	681b      	ldr	r3, [r3, #0]
+ 8001ca4:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
+ 8001ca8:	2b00      	cmp	r3, #0
+ 8001caa:	d00a      	beq.n	8001cc2 <HAL_RCCEx_PeriphCLKConfig+0x28e>
   {
     /* Check the parameters */
     assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
 
     /* Configure the I2C3 clock source */
     __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
- 8001c78:	4b8c      	ldr	r3, [pc, #560]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c7a:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8001c7e:	f423 1240 	bic.w	r2, r3, #3145728	; 0x300000
- 8001c82:	687b      	ldr	r3, [r7, #4]
- 8001c84:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 8001c86:	4989      	ldr	r1, [pc, #548]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c88:	4313      	orrs	r3, r2
- 8001c8a:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
+ 8001cac:	4b8c      	ldr	r3, [pc, #560]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001cae:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8001cb2:	f423 1240 	bic.w	r2, r3, #3145728	; 0x300000
+ 8001cb6:	687b      	ldr	r3, [r7, #4]
+ 8001cb8:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 8001cba:	4989      	ldr	r1, [pc, #548]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001cbc:	4313      	orrs	r3, r2
+ 8001cbe:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
   }
 
   /*-------------------------------------- I2C4 Configuration -----------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
- 8001c8e:	687b      	ldr	r3, [r7, #4]
- 8001c90:	681b      	ldr	r3, [r3, #0]
- 8001c92:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 8001c96:	2b00      	cmp	r3, #0
- 8001c98:	d00a      	beq.n	8001cb0 <HAL_RCCEx_PeriphCLKConfig+0x2b0>
+ 8001cc2:	687b      	ldr	r3, [r7, #4]
+ 8001cc4:	681b      	ldr	r3, [r3, #0]
+ 8001cc6:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
+ 8001cca:	2b00      	cmp	r3, #0
+ 8001ccc:	d00a      	beq.n	8001ce4 <HAL_RCCEx_PeriphCLKConfig+0x2b0>
   {
     /* Check the parameters */
     assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
 
     /* Configure the I2C4 clock source */
     __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
- 8001c9a:	4b84      	ldr	r3, [pc, #528]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c9c:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8001ca0:	f423 0240 	bic.w	r2, r3, #12582912	; 0xc00000
- 8001ca4:	687b      	ldr	r3, [r7, #4]
- 8001ca6:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8001ca8:	4980      	ldr	r1, [pc, #512]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001caa:	4313      	orrs	r3, r2
- 8001cac:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
+ 8001cce:	4b84      	ldr	r3, [pc, #528]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001cd0:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8001cd4:	f423 0240 	bic.w	r2, r3, #12582912	; 0xc00000
+ 8001cd8:	687b      	ldr	r3, [r7, #4]
+ 8001cda:	6f1b      	ldr	r3, [r3, #112]	; 0x70
+ 8001cdc:	4980      	ldr	r1, [pc, #512]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001cde:	4313      	orrs	r3, r2
+ 8001ce0:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
   }
 
   /*-------------------------------------- USART1 Configuration -----------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
- 8001cb0:	687b      	ldr	r3, [r7, #4]
- 8001cb2:	681b      	ldr	r3, [r3, #0]
- 8001cb4:	f003 0340 	and.w	r3, r3, #64	; 0x40
- 8001cb8:	2b00      	cmp	r3, #0
- 8001cba:	d00a      	beq.n	8001cd2 <HAL_RCCEx_PeriphCLKConfig+0x2d2>
+ 8001ce4:	687b      	ldr	r3, [r7, #4]
+ 8001ce6:	681b      	ldr	r3, [r3, #0]
+ 8001ce8:	f003 0340 	and.w	r3, r3, #64	; 0x40
+ 8001cec:	2b00      	cmp	r3, #0
+ 8001cee:	d00a      	beq.n	8001d06 <HAL_RCCEx_PeriphCLKConfig+0x2d2>
   {
     /* Check the parameters */
     assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
 
     /* Configure the USART1 clock source */
     __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
- 8001cbc:	4b7b      	ldr	r3, [pc, #492]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001cbe:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8001cc2:	f023 0203 	bic.w	r2, r3, #3
- 8001cc6:	687b      	ldr	r3, [r7, #4]
- 8001cc8:	6c5b      	ldr	r3, [r3, #68]	; 0x44
- 8001cca:	4978      	ldr	r1, [pc, #480]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001ccc:	4313      	orrs	r3, r2
- 8001cce:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
+ 8001cf0:	4b7b      	ldr	r3, [pc, #492]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001cf2:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8001cf6:	f023 0203 	bic.w	r2, r3, #3
+ 8001cfa:	687b      	ldr	r3, [r7, #4]
+ 8001cfc:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 8001cfe:	4978      	ldr	r1, [pc, #480]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d00:	4313      	orrs	r3, r2
+ 8001d02:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
   }
 
   /*-------------------------------------- USART2 Configuration -----------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
- 8001cd2:	687b      	ldr	r3, [r7, #4]
- 8001cd4:	681b      	ldr	r3, [r3, #0]
- 8001cd6:	f003 0380 	and.w	r3, r3, #128	; 0x80
- 8001cda:	2b00      	cmp	r3, #0
- 8001cdc:	d00a      	beq.n	8001cf4 <HAL_RCCEx_PeriphCLKConfig+0x2f4>
+ 8001d06:	687b      	ldr	r3, [r7, #4]
+ 8001d08:	681b      	ldr	r3, [r3, #0]
+ 8001d0a:	f003 0380 	and.w	r3, r3, #128	; 0x80
+ 8001d0e:	2b00      	cmp	r3, #0
+ 8001d10:	d00a      	beq.n	8001d28 <HAL_RCCEx_PeriphCLKConfig+0x2f4>
   {
     /* Check the parameters */
     assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
 
     /* Configure the USART2 clock source */
     __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
- 8001cde:	4b73      	ldr	r3, [pc, #460]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001ce0:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8001ce4:	f023 020c 	bic.w	r2, r3, #12
- 8001ce8:	687b      	ldr	r3, [r7, #4]
- 8001cea:	6c9b      	ldr	r3, [r3, #72]	; 0x48
- 8001cec:	496f      	ldr	r1, [pc, #444]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001cee:	4313      	orrs	r3, r2
- 8001cf0:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
+ 8001d12:	4b73      	ldr	r3, [pc, #460]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d14:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8001d18:	f023 020c 	bic.w	r2, r3, #12
+ 8001d1c:	687b      	ldr	r3, [r7, #4]
+ 8001d1e:	6c9b      	ldr	r3, [r3, #72]	; 0x48
+ 8001d20:	496f      	ldr	r1, [pc, #444]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d22:	4313      	orrs	r3, r2
+ 8001d24:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
   }
 
   /*-------------------------------------- USART3 Configuration -----------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
- 8001cf4:	687b      	ldr	r3, [r7, #4]
- 8001cf6:	681b      	ldr	r3, [r3, #0]
- 8001cf8:	f403 7380 	and.w	r3, r3, #256	; 0x100
- 8001cfc:	2b00      	cmp	r3, #0
- 8001cfe:	d00a      	beq.n	8001d16 <HAL_RCCEx_PeriphCLKConfig+0x316>
+ 8001d28:	687b      	ldr	r3, [r7, #4]
+ 8001d2a:	681b      	ldr	r3, [r3, #0]
+ 8001d2c:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 8001d30:	2b00      	cmp	r3, #0
+ 8001d32:	d00a      	beq.n	8001d4a <HAL_RCCEx_PeriphCLKConfig+0x316>
   {
     /* Check the parameters */
     assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
 
     /* Configure the USART3 clock source */
     __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
- 8001d00:	4b6a      	ldr	r3, [pc, #424]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d02:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8001d06:	f023 0230 	bic.w	r2, r3, #48	; 0x30
- 8001d0a:	687b      	ldr	r3, [r7, #4]
- 8001d0c:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
- 8001d0e:	4967      	ldr	r1, [pc, #412]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d10:	4313      	orrs	r3, r2
- 8001d12:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
+ 8001d34:	4b6a      	ldr	r3, [pc, #424]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d36:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8001d3a:	f023 0230 	bic.w	r2, r3, #48	; 0x30
+ 8001d3e:	687b      	ldr	r3, [r7, #4]
+ 8001d40:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
+ 8001d42:	4967      	ldr	r1, [pc, #412]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d44:	4313      	orrs	r3, r2
+ 8001d46:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
   }
 
   /*-------------------------------------- UART4 Configuration -----------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
- 8001d16:	687b      	ldr	r3, [r7, #4]
- 8001d18:	681b      	ldr	r3, [r3, #0]
- 8001d1a:	f403 7300 	and.w	r3, r3, #512	; 0x200
- 8001d1e:	2b00      	cmp	r3, #0
- 8001d20:	d00a      	beq.n	8001d38 <HAL_RCCEx_PeriphCLKConfig+0x338>
+ 8001d4a:	687b      	ldr	r3, [r7, #4]
+ 8001d4c:	681b      	ldr	r3, [r3, #0]
+ 8001d4e:	f403 7300 	and.w	r3, r3, #512	; 0x200
+ 8001d52:	2b00      	cmp	r3, #0
+ 8001d54:	d00a      	beq.n	8001d6c <HAL_RCCEx_PeriphCLKConfig+0x338>
   {
     /* Check the parameters */
     assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
 
     /* Configure the UART4 clock source */
     __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
- 8001d22:	4b62      	ldr	r3, [pc, #392]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d24:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8001d28:	f023 02c0 	bic.w	r2, r3, #192	; 0xc0
- 8001d2c:	687b      	ldr	r3, [r7, #4]
- 8001d2e:	6d1b      	ldr	r3, [r3, #80]	; 0x50
- 8001d30:	495e      	ldr	r1, [pc, #376]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d32:	4313      	orrs	r3, r2
- 8001d34:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
+ 8001d56:	4b62      	ldr	r3, [pc, #392]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d58:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8001d5c:	f023 02c0 	bic.w	r2, r3, #192	; 0xc0
+ 8001d60:	687b      	ldr	r3, [r7, #4]
+ 8001d62:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8001d64:	495e      	ldr	r1, [pc, #376]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d66:	4313      	orrs	r3, r2
+ 8001d68:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
   }
 
   /*-------------------------------------- UART5 Configuration -----------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
- 8001d38:	687b      	ldr	r3, [r7, #4]
- 8001d3a:	681b      	ldr	r3, [r3, #0]
- 8001d3c:	f403 6380 	and.w	r3, r3, #1024	; 0x400
- 8001d40:	2b00      	cmp	r3, #0
- 8001d42:	d00a      	beq.n	8001d5a <HAL_RCCEx_PeriphCLKConfig+0x35a>
+ 8001d6c:	687b      	ldr	r3, [r7, #4]
+ 8001d6e:	681b      	ldr	r3, [r3, #0]
+ 8001d70:	f403 6380 	and.w	r3, r3, #1024	; 0x400
+ 8001d74:	2b00      	cmp	r3, #0
+ 8001d76:	d00a      	beq.n	8001d8e <HAL_RCCEx_PeriphCLKConfig+0x35a>
   {
     /* Check the parameters */
     assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
 
     /* Configure the UART5 clock source */
     __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
- 8001d44:	4b59      	ldr	r3, [pc, #356]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d46:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8001d4a:	f423 7240 	bic.w	r2, r3, #768	; 0x300
- 8001d4e:	687b      	ldr	r3, [r7, #4]
- 8001d50:	6d5b      	ldr	r3, [r3, #84]	; 0x54
- 8001d52:	4956      	ldr	r1, [pc, #344]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d54:	4313      	orrs	r3, r2
- 8001d56:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
+ 8001d78:	4b59      	ldr	r3, [pc, #356]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d7a:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8001d7e:	f423 7240 	bic.w	r2, r3, #768	; 0x300
+ 8001d82:	687b      	ldr	r3, [r7, #4]
+ 8001d84:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8001d86:	4956      	ldr	r1, [pc, #344]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d88:	4313      	orrs	r3, r2
+ 8001d8a:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
   }
 
   /*-------------------------------------- USART6 Configuration -----------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
- 8001d5a:	687b      	ldr	r3, [r7, #4]
- 8001d5c:	681b      	ldr	r3, [r3, #0]
- 8001d5e:	f403 6300 	and.w	r3, r3, #2048	; 0x800
- 8001d62:	2b00      	cmp	r3, #0
- 8001d64:	d00a      	beq.n	8001d7c <HAL_RCCEx_PeriphCLKConfig+0x37c>
+ 8001d8e:	687b      	ldr	r3, [r7, #4]
+ 8001d90:	681b      	ldr	r3, [r3, #0]
+ 8001d92:	f403 6300 	and.w	r3, r3, #2048	; 0x800
+ 8001d96:	2b00      	cmp	r3, #0
+ 8001d98:	d00a      	beq.n	8001db0 <HAL_RCCEx_PeriphCLKConfig+0x37c>
   {
     /* Check the parameters */
     assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
 
     /* Configure the USART6 clock source */
     __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
- 8001d66:	4b51      	ldr	r3, [pc, #324]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d68:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8001d6c:	f423 6240 	bic.w	r2, r3, #3072	; 0xc00
- 8001d70:	687b      	ldr	r3, [r7, #4]
- 8001d72:	6d9b      	ldr	r3, [r3, #88]	; 0x58
- 8001d74:	494d      	ldr	r1, [pc, #308]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d76:	4313      	orrs	r3, r2
- 8001d78:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
+ 8001d9a:	4b51      	ldr	r3, [pc, #324]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d9c:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8001da0:	f423 6240 	bic.w	r2, r3, #3072	; 0xc00
+ 8001da4:	687b      	ldr	r3, [r7, #4]
+ 8001da6:	6d9b      	ldr	r3, [r3, #88]	; 0x58
+ 8001da8:	494d      	ldr	r1, [pc, #308]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001daa:	4313      	orrs	r3, r2
+ 8001dac:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
   }
 
   /*-------------------------------------- UART7 Configuration -----------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
- 8001d7c:	687b      	ldr	r3, [r7, #4]
- 8001d7e:	681b      	ldr	r3, [r3, #0]
- 8001d80:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
- 8001d84:	2b00      	cmp	r3, #0
- 8001d86:	d00a      	beq.n	8001d9e <HAL_RCCEx_PeriphCLKConfig+0x39e>
+ 8001db0:	687b      	ldr	r3, [r7, #4]
+ 8001db2:	681b      	ldr	r3, [r3, #0]
+ 8001db4:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
+ 8001db8:	2b00      	cmp	r3, #0
+ 8001dba:	d00a      	beq.n	8001dd2 <HAL_RCCEx_PeriphCLKConfig+0x39e>
   {
     /* Check the parameters */
     assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
 
     /* Configure the UART7 clock source */
     __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
- 8001d88:	4b48      	ldr	r3, [pc, #288]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d8a:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8001d8e:	f423 5240 	bic.w	r2, r3, #12288	; 0x3000
- 8001d92:	687b      	ldr	r3, [r7, #4]
- 8001d94:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
- 8001d96:	4945      	ldr	r1, [pc, #276]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d98:	4313      	orrs	r3, r2
- 8001d9a:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
+ 8001dbc:	4b48      	ldr	r3, [pc, #288]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001dbe:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8001dc2:	f423 5240 	bic.w	r2, r3, #12288	; 0x3000
+ 8001dc6:	687b      	ldr	r3, [r7, #4]
+ 8001dc8:	6ddb      	ldr	r3, [r3, #92]	; 0x5c
+ 8001dca:	4945      	ldr	r1, [pc, #276]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001dcc:	4313      	orrs	r3, r2
+ 8001dce:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
   }
 
   /*-------------------------------------- UART8 Configuration -----------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
- 8001d9e:	687b      	ldr	r3, [r7, #4]
- 8001da0:	681b      	ldr	r3, [r3, #0]
- 8001da2:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
- 8001da6:	2b00      	cmp	r3, #0
- 8001da8:	d00a      	beq.n	8001dc0 <HAL_RCCEx_PeriphCLKConfig+0x3c0>
+ 8001dd2:	687b      	ldr	r3, [r7, #4]
+ 8001dd4:	681b      	ldr	r3, [r3, #0]
+ 8001dd6:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
+ 8001dda:	2b00      	cmp	r3, #0
+ 8001ddc:	d00a      	beq.n	8001df4 <HAL_RCCEx_PeriphCLKConfig+0x3c0>
   {
     /* Check the parameters */
     assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
 
     /* Configure the UART8 clock source */
     __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
- 8001daa:	4b40      	ldr	r3, [pc, #256]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001dac:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8001db0:	f423 4240 	bic.w	r2, r3, #49152	; 0xc000
- 8001db4:	687b      	ldr	r3, [r7, #4]
- 8001db6:	6e1b      	ldr	r3, [r3, #96]	; 0x60
- 8001db8:	493c      	ldr	r1, [pc, #240]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001dba:	4313      	orrs	r3, r2
- 8001dbc:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
+ 8001dde:	4b40      	ldr	r3, [pc, #256]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001de0:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8001de4:	f423 4240 	bic.w	r2, r3, #49152	; 0xc000
+ 8001de8:	687b      	ldr	r3, [r7, #4]
+ 8001dea:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 8001dec:	493c      	ldr	r1, [pc, #240]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001dee:	4313      	orrs	r3, r2
+ 8001df0:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
   }
 
   /*--------------------------------------- CEC Configuration -----------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
- 8001dc0:	687b      	ldr	r3, [r7, #4]
- 8001dc2:	681b      	ldr	r3, [r3, #0]
- 8001dc4:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
- 8001dc8:	2b00      	cmp	r3, #0
- 8001dca:	d00a      	beq.n	8001de2 <HAL_RCCEx_PeriphCLKConfig+0x3e2>
+ 8001df4:	687b      	ldr	r3, [r7, #4]
+ 8001df6:	681b      	ldr	r3, [r3, #0]
+ 8001df8:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
+ 8001dfc:	2b00      	cmp	r3, #0
+ 8001dfe:	d00a      	beq.n	8001e16 <HAL_RCCEx_PeriphCLKConfig+0x3e2>
   {
     /* Check the parameters */
     assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
 
     /* Configure the CEC clock source */
     __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
- 8001dcc:	4b37      	ldr	r3, [pc, #220]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001dce:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8001dd2:	f023 6280 	bic.w	r2, r3, #67108864	; 0x4000000
- 8001dd6:	687b      	ldr	r3, [r7, #4]
- 8001dd8:	6f9b      	ldr	r3, [r3, #120]	; 0x78
- 8001dda:	4934      	ldr	r1, [pc, #208]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001ddc:	4313      	orrs	r3, r2
- 8001dde:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
+ 8001e00:	4b37      	ldr	r3, [pc, #220]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001e02:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8001e06:	f023 6280 	bic.w	r2, r3, #67108864	; 0x4000000
+ 8001e0a:	687b      	ldr	r3, [r7, #4]
+ 8001e0c:	6f9b      	ldr	r3, [r3, #120]	; 0x78
+ 8001e0e:	4934      	ldr	r1, [pc, #208]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001e10:	4313      	orrs	r3, r2
+ 8001e12:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
   }
 
   /*-------------------------------------- CK48 Configuration -----------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
- 8001de2:	687b      	ldr	r3, [r7, #4]
- 8001de4:	681b      	ldr	r3, [r3, #0]
- 8001de6:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
- 8001dea:	2b00      	cmp	r3, #0
- 8001dec:	d011      	beq.n	8001e12 <HAL_RCCEx_PeriphCLKConfig+0x412>
+ 8001e16:	687b      	ldr	r3, [r7, #4]
+ 8001e18:	681b      	ldr	r3, [r3, #0]
+ 8001e1a:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
+ 8001e1e:	2b00      	cmp	r3, #0
+ 8001e20:	d011      	beq.n	8001e46 <HAL_RCCEx_PeriphCLKConfig+0x412>
   {
     /* Check the parameters */
     assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
 
     /* Configure the CLK48 source */
     __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
- 8001dee:	4b2f      	ldr	r3, [pc, #188]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001df0:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8001df4:	f023 6200 	bic.w	r2, r3, #134217728	; 0x8000000
- 8001df8:	687b      	ldr	r3, [r7, #4]
- 8001dfa:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
- 8001dfc:	492b      	ldr	r1, [pc, #172]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001dfe:	4313      	orrs	r3, r2
- 8001e00:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
+ 8001e22:	4b2f      	ldr	r3, [pc, #188]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001e24:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8001e28:	f023 6200 	bic.w	r2, r3, #134217728	; 0x8000000
+ 8001e2c:	687b      	ldr	r3, [r7, #4]
+ 8001e2e:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
+ 8001e30:	492b      	ldr	r1, [pc, #172]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001e32:	4313      	orrs	r3, r2
+ 8001e34:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
 
     /* Enable the PLLSAI when it's used as clock source for CK48 */
     if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
- 8001e04:	687b      	ldr	r3, [r7, #4]
- 8001e06:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
- 8001e08:	f1b3 6f00 	cmp.w	r3, #134217728	; 0x8000000
- 8001e0c:	d101      	bne.n	8001e12 <HAL_RCCEx_PeriphCLKConfig+0x412>
+ 8001e38:	687b      	ldr	r3, [r7, #4]
+ 8001e3a:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
+ 8001e3c:	f1b3 6f00 	cmp.w	r3, #134217728	; 0x8000000
+ 8001e40:	d101      	bne.n	8001e46 <HAL_RCCEx_PeriphCLKConfig+0x412>
     {
       pllsaiused = 1;
- 8001e0e:	2301      	movs	r3, #1
- 8001e10:	61bb      	str	r3, [r7, #24]
+ 8001e42:	2301      	movs	r3, #1
+ 8001e44:	61bb      	str	r3, [r7, #24]
     }
   }
 
   /*-------------------------------------- LTDC Configuration -----------------------------------*/
 #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
- 8001e12:	687b      	ldr	r3, [r7, #4]
- 8001e14:	681b      	ldr	r3, [r3, #0]
- 8001e16:	f003 0308 	and.w	r3, r3, #8
- 8001e1a:	2b00      	cmp	r3, #0
- 8001e1c:	d001      	beq.n	8001e22 <HAL_RCCEx_PeriphCLKConfig+0x422>
+ 8001e46:	687b      	ldr	r3, [r7, #4]
+ 8001e48:	681b      	ldr	r3, [r3, #0]
+ 8001e4a:	f003 0308 	and.w	r3, r3, #8
+ 8001e4e:	2b00      	cmp	r3, #0
+ 8001e50:	d001      	beq.n	8001e56 <HAL_RCCEx_PeriphCLKConfig+0x422>
   {
     pllsaiused = 1;
- 8001e1e:	2301      	movs	r3, #1
- 8001e20:	61bb      	str	r3, [r7, #24]
+ 8001e52:	2301      	movs	r3, #1
+ 8001e54:	61bb      	str	r3, [r7, #24]
   }
 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
 
   /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
- 8001e22:	687b      	ldr	r3, [r7, #4]
- 8001e24:	681b      	ldr	r3, [r3, #0]
- 8001e26:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
- 8001e2a:	2b00      	cmp	r3, #0
- 8001e2c:	d00a      	beq.n	8001e44 <HAL_RCCEx_PeriphCLKConfig+0x444>
+ 8001e56:	687b      	ldr	r3, [r7, #4]
+ 8001e58:	681b      	ldr	r3, [r3, #0]
+ 8001e5a:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
+ 8001e5e:	2b00      	cmp	r3, #0
+ 8001e60:	d00a      	beq.n	8001e78 <HAL_RCCEx_PeriphCLKConfig+0x444>
   {
     /* Check the parameters */
     assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
 
     /* Configure the LTPIM1 clock source */
     __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
- 8001e2e:	4b1f      	ldr	r3, [pc, #124]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001e30:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8001e34:	f023 7240 	bic.w	r2, r3, #50331648	; 0x3000000
- 8001e38:	687b      	ldr	r3, [r7, #4]
- 8001e3a:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 8001e3c:	491b      	ldr	r1, [pc, #108]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001e3e:	4313      	orrs	r3, r2
- 8001e40:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
+ 8001e62:	4b1f      	ldr	r3, [pc, #124]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001e64:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8001e68:	f023 7240 	bic.w	r2, r3, #50331648	; 0x3000000
+ 8001e6c:	687b      	ldr	r3, [r7, #4]
+ 8001e6e:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 8001e70:	491b      	ldr	r1, [pc, #108]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001e72:	4313      	orrs	r3, r2
+ 8001e74:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
    }
 
   /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
- 8001e44:	687b      	ldr	r3, [r7, #4]
- 8001e46:	681b      	ldr	r3, [r3, #0]
- 8001e48:	f403 0300 	and.w	r3, r3, #8388608	; 0x800000
- 8001e4c:	2b00      	cmp	r3, #0
- 8001e4e:	d00b      	beq.n	8001e68 <HAL_RCCEx_PeriphCLKConfig+0x468>
+ 8001e78:	687b      	ldr	r3, [r7, #4]
+ 8001e7a:	681b      	ldr	r3, [r3, #0]
+ 8001e7c:	f403 0300 	and.w	r3, r3, #8388608	; 0x800000
+ 8001e80:	2b00      	cmp	r3, #0
+ 8001e82:	d00b      	beq.n	8001e9c <HAL_RCCEx_PeriphCLKConfig+0x468>
   {
     /* Check the parameters */
     assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
 
     /* Configure the SDMMC1 clock source */
     __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
- 8001e50:	4b16      	ldr	r3, [pc, #88]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001e52:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8001e56:	f023 5280 	bic.w	r2, r3, #268435456	; 0x10000000
- 8001e5a:	687b      	ldr	r3, [r7, #4]
- 8001e5c:	f8d3 3080 	ldr.w	r3, [r3, #128]	; 0x80
- 8001e60:	4912      	ldr	r1, [pc, #72]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001e62:	4313      	orrs	r3, r2
- 8001e64:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
+ 8001e84:	4b16      	ldr	r3, [pc, #88]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001e86:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8001e8a:	f023 5280 	bic.w	r2, r3, #268435456	; 0x10000000
+ 8001e8e:	687b      	ldr	r3, [r7, #4]
+ 8001e90:	f8d3 3080 	ldr.w	r3, [r3, #128]	; 0x80
+ 8001e94:	4912      	ldr	r1, [pc, #72]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001e96:	4313      	orrs	r3, r2
+ 8001e98:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
   }
 
 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
   /*------------------------------------- SDMMC2 Configuration ------------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
- 8001e68:	687b      	ldr	r3, [r7, #4]
- 8001e6a:	681b      	ldr	r3, [r3, #0]
- 8001e6c:	f003 6380 	and.w	r3, r3, #67108864	; 0x4000000
- 8001e70:	2b00      	cmp	r3, #0
- 8001e72:	d00b      	beq.n	8001e8c <HAL_RCCEx_PeriphCLKConfig+0x48c>
+ 8001e9c:	687b      	ldr	r3, [r7, #4]
+ 8001e9e:	681b      	ldr	r3, [r3, #0]
+ 8001ea0:	f003 6380 	and.w	r3, r3, #67108864	; 0x4000000
+ 8001ea4:	2b00      	cmp	r3, #0
+ 8001ea6:	d00b      	beq.n	8001ec0 <HAL_RCCEx_PeriphCLKConfig+0x48c>
   {
     /* Check the parameters */
     assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
 
     /* Configure the SDMMC2 clock source */
     __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
- 8001e74:	4b0d      	ldr	r3, [pc, #52]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001e76:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8001e7a:	f023 5200 	bic.w	r2, r3, #536870912	; 0x20000000
- 8001e7e:	687b      	ldr	r3, [r7, #4]
- 8001e80:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
- 8001e84:	4909      	ldr	r1, [pc, #36]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001e86:	4313      	orrs	r3, r2
- 8001e88:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
+ 8001ea8:	4b0d      	ldr	r3, [pc, #52]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001eaa:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8001eae:	f023 5200 	bic.w	r2, r3, #536870912	; 0x20000000
+ 8001eb2:	687b      	ldr	r3, [r7, #4]
+ 8001eb4:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 8001eb8:	4909      	ldr	r1, [pc, #36]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001eba:	4313      	orrs	r3, r2
+ 8001ebc:	f8c1 3090 	str.w	r3, [r1, #144]	; 0x90
   }
 
   /*------------------------------------- DFSDM1 Configuration -------------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
- 8001e8c:	687b      	ldr	r3, [r7, #4]
- 8001e8e:	681b      	ldr	r3, [r3, #0]
- 8001e90:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
- 8001e94:	2b00      	cmp	r3, #0
- 8001e96:	d00f      	beq.n	8001eb8 <HAL_RCCEx_PeriphCLKConfig+0x4b8>
+ 8001ec0:	687b      	ldr	r3, [r7, #4]
+ 8001ec2:	681b      	ldr	r3, [r3, #0]
+ 8001ec4:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
+ 8001ec8:	2b00      	cmp	r3, #0
+ 8001eca:	d00f      	beq.n	8001eec <HAL_RCCEx_PeriphCLKConfig+0x4b8>
   {
     /* Check the parameters */
     assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
 
     /* Configure the DFSDM1 interface clock source */
     __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
- 8001e98:	4b04      	ldr	r3, [pc, #16]	; (8001eac <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001e9a:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
- 8001e9e:	f023 7200 	bic.w	r2, r3, #33554432	; 0x2000000
- 8001ea2:	687b      	ldr	r3, [r7, #4]
- 8001ea4:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 8001ea8:	e002      	b.n	8001eb0 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
- 8001eaa:	bf00      	nop
- 8001eac:	40023800 	.word	0x40023800
- 8001eb0:	4985      	ldr	r1, [pc, #532]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001eb2:	4313      	orrs	r3, r2
- 8001eb4:	f8c1 308c 	str.w	r3, [r1, #140]	; 0x8c
+ 8001ecc:	4b04      	ldr	r3, [pc, #16]	; (8001ee0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001ece:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
+ 8001ed2:	f023 7200 	bic.w	r2, r3, #33554432	; 0x2000000
+ 8001ed6:	687b      	ldr	r3, [r7, #4]
+ 8001ed8:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 8001edc:	e002      	b.n	8001ee4 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
+ 8001ede:	bf00      	nop
+ 8001ee0:	40023800 	.word	0x40023800
+ 8001ee4:	4985      	ldr	r1, [pc, #532]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001ee6:	4313      	orrs	r3, r2
+ 8001ee8:	f8c1 308c 	str.w	r3, [r1, #140]	; 0x8c
   }
 
   /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
- 8001eb8:	687b      	ldr	r3, [r7, #4]
- 8001eba:	681b      	ldr	r3, [r3, #0]
- 8001ebc:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
- 8001ec0:	2b00      	cmp	r3, #0
- 8001ec2:	d00b      	beq.n	8001edc <HAL_RCCEx_PeriphCLKConfig+0x4dc>
+ 8001eec:	687b      	ldr	r3, [r7, #4]
+ 8001eee:	681b      	ldr	r3, [r3, #0]
+ 8001ef0:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
+ 8001ef4:	2b00      	cmp	r3, #0
+ 8001ef6:	d00b      	beq.n	8001f10 <HAL_RCCEx_PeriphCLKConfig+0x4dc>
   {
     /* Check the parameters */
     assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
 
     /* Configure the DFSDM interface clock source */
     __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
- 8001ec4:	4b80      	ldr	r3, [pc, #512]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001ec6:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
- 8001eca:	f023 6280 	bic.w	r2, r3, #67108864	; 0x4000000
- 8001ece:	687b      	ldr	r3, [r7, #4]
- 8001ed0:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
- 8001ed4:	497c      	ldr	r1, [pc, #496]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001ed6:	4313      	orrs	r3, r2
- 8001ed8:	f8c1 308c 	str.w	r3, [r1, #140]	; 0x8c
+ 8001ef8:	4b80      	ldr	r3, [pc, #512]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001efa:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
+ 8001efe:	f023 6280 	bic.w	r2, r3, #67108864	; 0x4000000
+ 8001f02:	687b      	ldr	r3, [r7, #4]
+ 8001f04:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
+ 8001f08:	497c      	ldr	r1, [pc, #496]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001f0a:	4313      	orrs	r3, r2
+ 8001f0c:	f8c1 308c 	str.w	r3, [r1, #140]	; 0x8c
   }
 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
 
   /*-------------------------------------- PLLI2S Configuration ---------------------------------*/
   /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
   if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
- 8001edc:	69fb      	ldr	r3, [r7, #28]
- 8001ede:	2b01      	cmp	r3, #1
- 8001ee0:	d005      	beq.n	8001eee <HAL_RCCEx_PeriphCLKConfig+0x4ee>
- 8001ee2:	687b      	ldr	r3, [r7, #4]
- 8001ee4:	681b      	ldr	r3, [r3, #0]
- 8001ee6:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
- 8001eea:	f040 80d6 	bne.w	800209a <HAL_RCCEx_PeriphCLKConfig+0x69a>
+ 8001f10:	69fb      	ldr	r3, [r7, #28]
+ 8001f12:	2b01      	cmp	r3, #1
+ 8001f14:	d005      	beq.n	8001f22 <HAL_RCCEx_PeriphCLKConfig+0x4ee>
+ 8001f16:	687b      	ldr	r3, [r7, #4]
+ 8001f18:	681b      	ldr	r3, [r3, #0]
+ 8001f1a:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
+ 8001f1e:	f040 80d6 	bne.w	80020ce <HAL_RCCEx_PeriphCLKConfig+0x69a>
   {
     /* Disable the PLLI2S */
     __HAL_RCC_PLLI2S_DISABLE();
- 8001eee:	4b76      	ldr	r3, [pc, #472]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001ef0:	681b      	ldr	r3, [r3, #0]
- 8001ef2:	4a75      	ldr	r2, [pc, #468]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001ef4:	f023 6380 	bic.w	r3, r3, #67108864	; 0x4000000
- 8001ef8:	6013      	str	r3, [r2, #0]
+ 8001f22:	4b76      	ldr	r3, [pc, #472]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001f24:	681b      	ldr	r3, [r3, #0]
+ 8001f26:	4a75      	ldr	r2, [pc, #468]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001f28:	f023 6380 	bic.w	r3, r3, #67108864	; 0x4000000
+ 8001f2c:	6013      	str	r3, [r2, #0]
 
     /* Get Start Tick*/
     tickstart = HAL_GetTick();
- 8001efa:	f7fe fb6f 	bl	80005dc <HAL_GetTick>
- 8001efe:	6178      	str	r0, [r7, #20]
+ 8001f2e:	f7fe fb55 	bl	80005dc <HAL_GetTick>
+ 8001f32:	6178      	str	r0, [r7, #20]
 
     /* Wait till PLLI2S is disabled */
     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
- 8001f00:	e008      	b.n	8001f14 <HAL_RCCEx_PeriphCLKConfig+0x514>
+ 8001f34:	e008      	b.n	8001f48 <HAL_RCCEx_PeriphCLKConfig+0x514>
     {
       if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- 8001f02:	f7fe fb6b 	bl	80005dc <HAL_GetTick>
- 8001f06:	4602      	mov	r2, r0
- 8001f08:	697b      	ldr	r3, [r7, #20]
- 8001f0a:	1ad3      	subs	r3, r2, r3
- 8001f0c:	2b64      	cmp	r3, #100	; 0x64
- 8001f0e:	d901      	bls.n	8001f14 <HAL_RCCEx_PeriphCLKConfig+0x514>
+ 8001f36:	f7fe fb51 	bl	80005dc <HAL_GetTick>
+ 8001f3a:	4602      	mov	r2, r0
+ 8001f3c:	697b      	ldr	r3, [r7, #20]
+ 8001f3e:	1ad3      	subs	r3, r2, r3
+ 8001f40:	2b64      	cmp	r3, #100	; 0x64
+ 8001f42:	d901      	bls.n	8001f48 <HAL_RCCEx_PeriphCLKConfig+0x514>
       {
         /* return in case of Timeout detected */
         return HAL_TIMEOUT;
- 8001f10:	2303      	movs	r3, #3
- 8001f12:	e194      	b.n	800223e <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 8001f44:	2303      	movs	r3, #3
+ 8001f46:	e194      	b.n	8002272 <HAL_RCCEx_PeriphCLKConfig+0x83e>
     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
- 8001f14:	4b6c      	ldr	r3, [pc, #432]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001f16:	681b      	ldr	r3, [r3, #0]
- 8001f18:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
- 8001f1c:	2b00      	cmp	r3, #0
- 8001f1e:	d1f0      	bne.n	8001f02 <HAL_RCCEx_PeriphCLKConfig+0x502>
+ 8001f48:	4b6c      	ldr	r3, [pc, #432]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001f4a:	681b      	ldr	r3, [r3, #0]
+ 8001f4c:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
+ 8001f50:	2b00      	cmp	r3, #0
+ 8001f52:	d1f0      	bne.n	8001f36 <HAL_RCCEx_PeriphCLKConfig+0x502>
 
     /* check for common PLLI2S Parameters */
     assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
 
     /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
     if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
- 8001f20:	687b      	ldr	r3, [r7, #4]
- 8001f22:	681b      	ldr	r3, [r3, #0]
- 8001f24:	f003 0301 	and.w	r3, r3, #1
- 8001f28:	2b00      	cmp	r3, #0
- 8001f2a:	d021      	beq.n	8001f70 <HAL_RCCEx_PeriphCLKConfig+0x570>
- 8001f2c:	687b      	ldr	r3, [r7, #4]
- 8001f2e:	6b5b      	ldr	r3, [r3, #52]	; 0x34
- 8001f30:	2b00      	cmp	r3, #0
- 8001f32:	d11d      	bne.n	8001f70 <HAL_RCCEx_PeriphCLKConfig+0x570>
+ 8001f54:	687b      	ldr	r3, [r7, #4]
+ 8001f56:	681b      	ldr	r3, [r3, #0]
+ 8001f58:	f003 0301 	and.w	r3, r3, #1
+ 8001f5c:	2b00      	cmp	r3, #0
+ 8001f5e:	d021      	beq.n	8001fa4 <HAL_RCCEx_PeriphCLKConfig+0x570>
+ 8001f60:	687b      	ldr	r3, [r7, #4]
+ 8001f62:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 8001f64:	2b00      	cmp	r3, #0
+ 8001f66:	d11d      	bne.n	8001fa4 <HAL_RCCEx_PeriphCLKConfig+0x570>
     {
       /* check for Parameters */
       assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
 
       /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
       tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
- 8001f34:	4b64      	ldr	r3, [pc, #400]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001f36:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
- 8001f3a:	0c1b      	lsrs	r3, r3, #16
- 8001f3c:	f003 0303 	and.w	r3, r3, #3
- 8001f40:	613b      	str	r3, [r7, #16]
+ 8001f68:	4b64      	ldr	r3, [pc, #400]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001f6a:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 8001f6e:	0c1b      	lsrs	r3, r3, #16
+ 8001f70:	f003 0303 	and.w	r3, r3, #3
+ 8001f74:	613b      	str	r3, [r7, #16]
       tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
- 8001f42:	4b61      	ldr	r3, [pc, #388]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001f44:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
- 8001f48:	0e1b      	lsrs	r3, r3, #24
- 8001f4a:	f003 030f 	and.w	r3, r3, #15
- 8001f4e:	60fb      	str	r3, [r7, #12]
+ 8001f76:	4b61      	ldr	r3, [pc, #388]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001f78:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 8001f7c:	0e1b      	lsrs	r3, r3, #24
+ 8001f7e:	f003 030f 	and.w	r3, r3, #15
+ 8001f82:	60fb      	str	r3, [r7, #12]
       /* Configure the PLLI2S division factors */
       /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
       /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
- 8001f50:	687b      	ldr	r3, [r7, #4]
- 8001f52:	685b      	ldr	r3, [r3, #4]
- 8001f54:	019a      	lsls	r2, r3, #6
- 8001f56:	693b      	ldr	r3, [r7, #16]
- 8001f58:	041b      	lsls	r3, r3, #16
- 8001f5a:	431a      	orrs	r2, r3
- 8001f5c:	68fb      	ldr	r3, [r7, #12]
- 8001f5e:	061b      	lsls	r3, r3, #24
- 8001f60:	431a      	orrs	r2, r3
- 8001f62:	687b      	ldr	r3, [r7, #4]
- 8001f64:	689b      	ldr	r3, [r3, #8]
- 8001f66:	071b      	lsls	r3, r3, #28
- 8001f68:	4957      	ldr	r1, [pc, #348]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001f6a:	4313      	orrs	r3, r2
- 8001f6c:	f8c1 3084 	str.w	r3, [r1, #132]	; 0x84
+ 8001f84:	687b      	ldr	r3, [r7, #4]
+ 8001f86:	685b      	ldr	r3, [r3, #4]
+ 8001f88:	019a      	lsls	r2, r3, #6
+ 8001f8a:	693b      	ldr	r3, [r7, #16]
+ 8001f8c:	041b      	lsls	r3, r3, #16
+ 8001f8e:	431a      	orrs	r2, r3
+ 8001f90:	68fb      	ldr	r3, [r7, #12]
+ 8001f92:	061b      	lsls	r3, r3, #24
+ 8001f94:	431a      	orrs	r2, r3
+ 8001f96:	687b      	ldr	r3, [r7, #4]
+ 8001f98:	689b      	ldr	r3, [r3, #8]
+ 8001f9a:	071b      	lsls	r3, r3, #28
+ 8001f9c:	4957      	ldr	r1, [pc, #348]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001f9e:	4313      	orrs	r3, r2
+ 8001fa0:	f8c1 3084 	str.w	r3, [r1, #132]	; 0x84
     }
 
     /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
     if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
- 8001f70:	687b      	ldr	r3, [r7, #4]
- 8001f72:	681b      	ldr	r3, [r3, #0]
- 8001f74:	f403 2300 	and.w	r3, r3, #524288	; 0x80000
- 8001f78:	2b00      	cmp	r3, #0
- 8001f7a:	d004      	beq.n	8001f86 <HAL_RCCEx_PeriphCLKConfig+0x586>
- 8001f7c:	687b      	ldr	r3, [r7, #4]
- 8001f7e:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
- 8001f80:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
- 8001f84:	d00a      	beq.n	8001f9c <HAL_RCCEx_PeriphCLKConfig+0x59c>
+ 8001fa4:	687b      	ldr	r3, [r7, #4]
+ 8001fa6:	681b      	ldr	r3, [r3, #0]
+ 8001fa8:	f403 2300 	and.w	r3, r3, #524288	; 0x80000
+ 8001fac:	2b00      	cmp	r3, #0
+ 8001fae:	d004      	beq.n	8001fba <HAL_RCCEx_PeriphCLKConfig+0x586>
+ 8001fb0:	687b      	ldr	r3, [r7, #4]
+ 8001fb2:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 8001fb4:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
+ 8001fb8:	d00a      	beq.n	8001fd0 <HAL_RCCEx_PeriphCLKConfig+0x59c>
        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
- 8001f86:	687b      	ldr	r3, [r7, #4]
- 8001f88:	681b      	ldr	r3, [r3, #0]
- 8001f8a:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
+ 8001fba:	687b      	ldr	r3, [r7, #4]
+ 8001fbc:	681b      	ldr	r3, [r3, #0]
+ 8001fbe:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
     if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
- 8001f8e:	2b00      	cmp	r3, #0
- 8001f90:	d02e      	beq.n	8001ff0 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
+ 8001fc2:	2b00      	cmp	r3, #0
+ 8001fc4:	d02e      	beq.n	8002024 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
- 8001f92:	687b      	ldr	r3, [r7, #4]
- 8001f94:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 8001f96:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
- 8001f9a:	d129      	bne.n	8001ff0 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
+ 8001fc6:	687b      	ldr	r3, [r7, #4]
+ 8001fc8:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8001fca:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
+ 8001fce:	d129      	bne.n	8002024 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
       assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
       /* Check for PLLI2S/DIVQ parameters */
       assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
 
       /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
       tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
- 8001f9c:	4b4a      	ldr	r3, [pc, #296]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001f9e:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
- 8001fa2:	0c1b      	lsrs	r3, r3, #16
- 8001fa4:	f003 0303 	and.w	r3, r3, #3
- 8001fa8:	613b      	str	r3, [r7, #16]
+ 8001fd0:	4b4a      	ldr	r3, [pc, #296]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001fd2:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 8001fd6:	0c1b      	lsrs	r3, r3, #16
+ 8001fd8:	f003 0303 	and.w	r3, r3, #3
+ 8001fdc:	613b      	str	r3, [r7, #16]
       tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
- 8001faa:	4b47      	ldr	r3, [pc, #284]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001fac:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
- 8001fb0:	0f1b      	lsrs	r3, r3, #28
- 8001fb2:	f003 0307 	and.w	r3, r3, #7
- 8001fb6:	60fb      	str	r3, [r7, #12]
+ 8001fde:	4b47      	ldr	r3, [pc, #284]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001fe0:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 8001fe4:	0f1b      	lsrs	r3, r3, #28
+ 8001fe6:	f003 0307 	and.w	r3, r3, #7
+ 8001fea:	60fb      	str	r3, [r7, #12]
       /* Configure the PLLI2S division factors */
       /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
       /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
       /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
- 8001fb8:	687b      	ldr	r3, [r7, #4]
- 8001fba:	685b      	ldr	r3, [r3, #4]
- 8001fbc:	019a      	lsls	r2, r3, #6
- 8001fbe:	693b      	ldr	r3, [r7, #16]
- 8001fc0:	041b      	lsls	r3, r3, #16
- 8001fc2:	431a      	orrs	r2, r3
- 8001fc4:	687b      	ldr	r3, [r7, #4]
- 8001fc6:	68db      	ldr	r3, [r3, #12]
- 8001fc8:	061b      	lsls	r3, r3, #24
- 8001fca:	431a      	orrs	r2, r3
- 8001fcc:	68fb      	ldr	r3, [r7, #12]
- 8001fce:	071b      	lsls	r3, r3, #28
- 8001fd0:	493d      	ldr	r1, [pc, #244]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001fd2:	4313      	orrs	r3, r2
- 8001fd4:	f8c1 3084 	str.w	r3, [r1, #132]	; 0x84
+ 8001fec:	687b      	ldr	r3, [r7, #4]
+ 8001fee:	685b      	ldr	r3, [r3, #4]
+ 8001ff0:	019a      	lsls	r2, r3, #6
+ 8001ff2:	693b      	ldr	r3, [r7, #16]
+ 8001ff4:	041b      	lsls	r3, r3, #16
+ 8001ff6:	431a      	orrs	r2, r3
+ 8001ff8:	687b      	ldr	r3, [r7, #4]
+ 8001ffa:	68db      	ldr	r3, [r3, #12]
+ 8001ffc:	061b      	lsls	r3, r3, #24
+ 8001ffe:	431a      	orrs	r2, r3
+ 8002000:	68fb      	ldr	r3, [r7, #12]
+ 8002002:	071b      	lsls	r3, r3, #28
+ 8002004:	493d      	ldr	r1, [pc, #244]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002006:	4313      	orrs	r3, r2
+ 8002008:	f8c1 3084 	str.w	r3, [r1, #132]	; 0x84
 
       /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
       __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
- 8001fd8:	4b3b      	ldr	r3, [pc, #236]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001fda:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
- 8001fde:	f023 021f 	bic.w	r2, r3, #31
- 8001fe2:	687b      	ldr	r3, [r7, #4]
- 8001fe4:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8001fe6:	3b01      	subs	r3, #1
- 8001fe8:	4937      	ldr	r1, [pc, #220]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001fea:	4313      	orrs	r3, r2
- 8001fec:	f8c1 308c 	str.w	r3, [r1, #140]	; 0x8c
+ 800200c:	4b3b      	ldr	r3, [pc, #236]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 800200e:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
+ 8002012:	f023 021f 	bic.w	r2, r3, #31
+ 8002016:	687b      	ldr	r3, [r7, #4]
+ 8002018:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 800201a:	3b01      	subs	r3, #1
+ 800201c:	4937      	ldr	r1, [pc, #220]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 800201e:	4313      	orrs	r3, r2
+ 8002020:	f8c1 308c 	str.w	r3, [r1, #140]	; 0x8c
     }
 
     /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
     if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
- 8001ff0:	687b      	ldr	r3, [r7, #4]
- 8001ff2:	681b      	ldr	r3, [r3, #0]
- 8001ff4:	f003 7380 	and.w	r3, r3, #16777216	; 0x1000000
- 8001ff8:	2b00      	cmp	r3, #0
- 8001ffa:	d01d      	beq.n	8002038 <HAL_RCCEx_PeriphCLKConfig+0x638>
+ 8002024:	687b      	ldr	r3, [r7, #4]
+ 8002026:	681b      	ldr	r3, [r3, #0]
+ 8002028:	f003 7380 	and.w	r3, r3, #16777216	; 0x1000000
+ 800202c:	2b00      	cmp	r3, #0
+ 800202e:	d01d      	beq.n	800206c <HAL_RCCEx_PeriphCLKConfig+0x638>
     {
       /* check for Parameters */
       assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
 
      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
       tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
- 8001ffc:	4b32      	ldr	r3, [pc, #200]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001ffe:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
- 8002002:	0e1b      	lsrs	r3, r3, #24
- 8002004:	f003 030f 	and.w	r3, r3, #15
- 8002008:	613b      	str	r3, [r7, #16]
+ 8002030:	4b32      	ldr	r3, [pc, #200]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002032:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 8002036:	0e1b      	lsrs	r3, r3, #24
+ 8002038:	f003 030f 	and.w	r3, r3, #15
+ 800203c:	613b      	str	r3, [r7, #16]
       tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
- 800200a:	4b2f      	ldr	r3, [pc, #188]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800200c:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
- 8002010:	0f1b      	lsrs	r3, r3, #28
- 8002012:	f003 0307 	and.w	r3, r3, #7
- 8002016:	60fb      	str	r3, [r7, #12]
+ 800203e:	4b2f      	ldr	r3, [pc, #188]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002040:	f8d3 3084 	ldr.w	r3, [r3, #132]	; 0x84
+ 8002044:	0f1b      	lsrs	r3, r3, #28
+ 8002046:	f003 0307 	and.w	r3, r3, #7
+ 800204a:	60fb      	str	r3, [r7, #12]
       /* Configure the PLLI2S division factors */
       /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
       /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
- 8002018:	687b      	ldr	r3, [r7, #4]
- 800201a:	685b      	ldr	r3, [r3, #4]
- 800201c:	019a      	lsls	r2, r3, #6
- 800201e:	687b      	ldr	r3, [r7, #4]
- 8002020:	691b      	ldr	r3, [r3, #16]
- 8002022:	041b      	lsls	r3, r3, #16
- 8002024:	431a      	orrs	r2, r3
- 8002026:	693b      	ldr	r3, [r7, #16]
- 8002028:	061b      	lsls	r3, r3, #24
- 800202a:	431a      	orrs	r2, r3
- 800202c:	68fb      	ldr	r3, [r7, #12]
- 800202e:	071b      	lsls	r3, r3, #28
- 8002030:	4925      	ldr	r1, [pc, #148]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002032:	4313      	orrs	r3, r2
- 8002034:	f8c1 3084 	str.w	r3, [r1, #132]	; 0x84
+ 800204c:	687b      	ldr	r3, [r7, #4]
+ 800204e:	685b      	ldr	r3, [r3, #4]
+ 8002050:	019a      	lsls	r2, r3, #6
+ 8002052:	687b      	ldr	r3, [r7, #4]
+ 8002054:	691b      	ldr	r3, [r3, #16]
+ 8002056:	041b      	lsls	r3, r3, #16
+ 8002058:	431a      	orrs	r2, r3
+ 800205a:	693b      	ldr	r3, [r7, #16]
+ 800205c:	061b      	lsls	r3, r3, #24
+ 800205e:	431a      	orrs	r2, r3
+ 8002060:	68fb      	ldr	r3, [r7, #12]
+ 8002062:	071b      	lsls	r3, r3, #28
+ 8002064:	4925      	ldr	r1, [pc, #148]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002066:	4313      	orrs	r3, r2
+ 8002068:	f8c1 3084 	str.w	r3, [r1, #132]	; 0x84
     }
 
     /*----------------- In Case of PLLI2S is just selected  -----------------*/
     if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
- 8002038:	687b      	ldr	r3, [r7, #4]
- 800203a:	681b      	ldr	r3, [r3, #0]
- 800203c:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
- 8002040:	2b00      	cmp	r3, #0
- 8002042:	d011      	beq.n	8002068 <HAL_RCCEx_PeriphCLKConfig+0x668>
+ 800206c:	687b      	ldr	r3, [r7, #4]
+ 800206e:	681b      	ldr	r3, [r3, #0]
+ 8002070:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
+ 8002074:	2b00      	cmp	r3, #0
+ 8002076:	d011      	beq.n	800209c <HAL_RCCEx_PeriphCLKConfig+0x668>
       assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
 
       /* Configure the PLLI2S division factors */
       /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
       /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
- 8002044:	687b      	ldr	r3, [r7, #4]
- 8002046:	685b      	ldr	r3, [r3, #4]
- 8002048:	019a      	lsls	r2, r3, #6
- 800204a:	687b      	ldr	r3, [r7, #4]
- 800204c:	691b      	ldr	r3, [r3, #16]
- 800204e:	041b      	lsls	r3, r3, #16
- 8002050:	431a      	orrs	r2, r3
- 8002052:	687b      	ldr	r3, [r7, #4]
- 8002054:	68db      	ldr	r3, [r3, #12]
- 8002056:	061b      	lsls	r3, r3, #24
- 8002058:	431a      	orrs	r2, r3
- 800205a:	687b      	ldr	r3, [r7, #4]
- 800205c:	689b      	ldr	r3, [r3, #8]
- 800205e:	071b      	lsls	r3, r3, #28
- 8002060:	4919      	ldr	r1, [pc, #100]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002062:	4313      	orrs	r3, r2
- 8002064:	f8c1 3084 	str.w	r3, [r1, #132]	; 0x84
+ 8002078:	687b      	ldr	r3, [r7, #4]
+ 800207a:	685b      	ldr	r3, [r3, #4]
+ 800207c:	019a      	lsls	r2, r3, #6
+ 800207e:	687b      	ldr	r3, [r7, #4]
+ 8002080:	691b      	ldr	r3, [r3, #16]
+ 8002082:	041b      	lsls	r3, r3, #16
+ 8002084:	431a      	orrs	r2, r3
+ 8002086:	687b      	ldr	r3, [r7, #4]
+ 8002088:	68db      	ldr	r3, [r3, #12]
+ 800208a:	061b      	lsls	r3, r3, #24
+ 800208c:	431a      	orrs	r2, r3
+ 800208e:	687b      	ldr	r3, [r7, #4]
+ 8002090:	689b      	ldr	r3, [r3, #8]
+ 8002092:	071b      	lsls	r3, r3, #28
+ 8002094:	4919      	ldr	r1, [pc, #100]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002096:	4313      	orrs	r3, r2
+ 8002098:	f8c1 3084 	str.w	r3, [r1, #132]	; 0x84
     }
 
     /* Enable the PLLI2S */
     __HAL_RCC_PLLI2S_ENABLE();
- 8002068:	4b17      	ldr	r3, [pc, #92]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800206a:	681b      	ldr	r3, [r3, #0]
- 800206c:	4a16      	ldr	r2, [pc, #88]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800206e:	f043 6380 	orr.w	r3, r3, #67108864	; 0x4000000
- 8002072:	6013      	str	r3, [r2, #0]
+ 800209c:	4b17      	ldr	r3, [pc, #92]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 800209e:	681b      	ldr	r3, [r3, #0]
+ 80020a0:	4a16      	ldr	r2, [pc, #88]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 80020a2:	f043 6380 	orr.w	r3, r3, #67108864	; 0x4000000
+ 80020a6:	6013      	str	r3, [r2, #0]
 
     /* Get Start Tick*/
     tickstart = HAL_GetTick();
- 8002074:	f7fe fab2 	bl	80005dc <HAL_GetTick>
- 8002078:	6178      	str	r0, [r7, #20]
+ 80020a8:	f7fe fa98 	bl	80005dc <HAL_GetTick>
+ 80020ac:	6178      	str	r0, [r7, #20]
 
     /* Wait till PLLI2S is ready */
     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
- 800207a:	e008      	b.n	800208e <HAL_RCCEx_PeriphCLKConfig+0x68e>
+ 80020ae:	e008      	b.n	80020c2 <HAL_RCCEx_PeriphCLKConfig+0x68e>
     {
       if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- 800207c:	f7fe faae 	bl	80005dc <HAL_GetTick>
- 8002080:	4602      	mov	r2, r0
- 8002082:	697b      	ldr	r3, [r7, #20]
- 8002084:	1ad3      	subs	r3, r2, r3
- 8002086:	2b64      	cmp	r3, #100	; 0x64
- 8002088:	d901      	bls.n	800208e <HAL_RCCEx_PeriphCLKConfig+0x68e>
+ 80020b0:	f7fe fa94 	bl	80005dc <HAL_GetTick>
+ 80020b4:	4602      	mov	r2, r0
+ 80020b6:	697b      	ldr	r3, [r7, #20]
+ 80020b8:	1ad3      	subs	r3, r2, r3
+ 80020ba:	2b64      	cmp	r3, #100	; 0x64
+ 80020bc:	d901      	bls.n	80020c2 <HAL_RCCEx_PeriphCLKConfig+0x68e>
       {
         /* return in case of Timeout detected */
         return HAL_TIMEOUT;
- 800208a:	2303      	movs	r3, #3
- 800208c:	e0d7      	b.n	800223e <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 80020be:	2303      	movs	r3, #3
+ 80020c0:	e0d7      	b.n	8002272 <HAL_RCCEx_PeriphCLKConfig+0x83e>
     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
- 800208e:	4b0e      	ldr	r3, [pc, #56]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002090:	681b      	ldr	r3, [r3, #0]
- 8002092:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
- 8002096:	2b00      	cmp	r3, #0
- 8002098:	d0f0      	beq.n	800207c <HAL_RCCEx_PeriphCLKConfig+0x67c>
+ 80020c2:	4b0e      	ldr	r3, [pc, #56]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 80020c4:	681b      	ldr	r3, [r3, #0]
+ 80020c6:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
+ 80020ca:	2b00      	cmp	r3, #0
+ 80020cc:	d0f0      	beq.n	80020b0 <HAL_RCCEx_PeriphCLKConfig+0x67c>
     }
   }
 
   /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
   /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
   if(pllsaiused == 1)
- 800209a:	69bb      	ldr	r3, [r7, #24]
- 800209c:	2b01      	cmp	r3, #1
- 800209e:	f040 80cd 	bne.w	800223c <HAL_RCCEx_PeriphCLKConfig+0x83c>
+ 80020ce:	69bb      	ldr	r3, [r7, #24]
+ 80020d0:	2b01      	cmp	r3, #1
+ 80020d2:	f040 80cd 	bne.w	8002270 <HAL_RCCEx_PeriphCLKConfig+0x83c>
   {
     /* Disable PLLSAI Clock */
     __HAL_RCC_PLLSAI_DISABLE();
- 80020a2:	4b09      	ldr	r3, [pc, #36]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80020a4:	681b      	ldr	r3, [r3, #0]
- 80020a6:	4a08      	ldr	r2, [pc, #32]	; (80020c8 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80020a8:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
- 80020ac:	6013      	str	r3, [r2, #0]
+ 80020d6:	4b09      	ldr	r3, [pc, #36]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 80020d8:	681b      	ldr	r3, [r3, #0]
+ 80020da:	4a08      	ldr	r2, [pc, #32]	; (80020fc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 80020dc:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
+ 80020e0:	6013      	str	r3, [r2, #0]
 
     /* Get Start Tick*/
     tickstart = HAL_GetTick();
- 80020ae:	f7fe fa95 	bl	80005dc <HAL_GetTick>
- 80020b2:	6178      	str	r0, [r7, #20]
+ 80020e2:	f7fe fa7b 	bl	80005dc <HAL_GetTick>
+ 80020e6:	6178      	str	r0, [r7, #20]
 
     /* Wait till PLLSAI is disabled */
     while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
- 80020b4:	e00a      	b.n	80020cc <HAL_RCCEx_PeriphCLKConfig+0x6cc>
+ 80020e8:	e00a      	b.n	8002100 <HAL_RCCEx_PeriphCLKConfig+0x6cc>
     {
       if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
- 80020b6:	f7fe fa91 	bl	80005dc <HAL_GetTick>
- 80020ba:	4602      	mov	r2, r0
- 80020bc:	697b      	ldr	r3, [r7, #20]
- 80020be:	1ad3      	subs	r3, r2, r3
- 80020c0:	2b64      	cmp	r3, #100	; 0x64
- 80020c2:	d903      	bls.n	80020cc <HAL_RCCEx_PeriphCLKConfig+0x6cc>
+ 80020ea:	f7fe fa77 	bl	80005dc <HAL_GetTick>
+ 80020ee:	4602      	mov	r2, r0
+ 80020f0:	697b      	ldr	r3, [r7, #20]
+ 80020f2:	1ad3      	subs	r3, r2, r3
+ 80020f4:	2b64      	cmp	r3, #100	; 0x64
+ 80020f6:	d903      	bls.n	8002100 <HAL_RCCEx_PeriphCLKConfig+0x6cc>
       {
         /* return in case of Timeout detected */
         return HAL_TIMEOUT;
- 80020c4:	2303      	movs	r3, #3
- 80020c6:	e0ba      	b.n	800223e <HAL_RCCEx_PeriphCLKConfig+0x83e>
- 80020c8:	40023800 	.word	0x40023800
+ 80020f8:	2303      	movs	r3, #3
+ 80020fa:	e0ba      	b.n	8002272 <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 80020fc:	40023800 	.word	0x40023800
     while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
- 80020cc:	4b5e      	ldr	r3, [pc, #376]	; (8002248 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80020ce:	681b      	ldr	r3, [r3, #0]
- 80020d0:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
- 80020d4:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
- 80020d8:	d0ed      	beq.n	80020b6 <HAL_RCCEx_PeriphCLKConfig+0x6b6>
+ 8002100:	4b5e      	ldr	r3, [pc, #376]	; (800227c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002102:	681b      	ldr	r3, [r3, #0]
+ 8002104:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
+ 8002108:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 800210c:	d0ed      	beq.n	80020ea <HAL_RCCEx_PeriphCLKConfig+0x6b6>
 
     /* Check the PLLSAI division factors */
     assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
 
     /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
     if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
- 80020da:	687b      	ldr	r3, [r7, #4]
- 80020dc:	681b      	ldr	r3, [r3, #0]
- 80020de:	f403 2300 	and.w	r3, r3, #524288	; 0x80000
- 80020e2:	2b00      	cmp	r3, #0
- 80020e4:	d003      	beq.n	80020ee <HAL_RCCEx_PeriphCLKConfig+0x6ee>
- 80020e6:	687b      	ldr	r3, [r7, #4]
- 80020e8:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
- 80020ea:	2b00      	cmp	r3, #0
- 80020ec:	d009      	beq.n	8002102 <HAL_RCCEx_PeriphCLKConfig+0x702>
+ 800210e:	687b      	ldr	r3, [r7, #4]
+ 8002110:	681b      	ldr	r3, [r3, #0]
+ 8002112:	f403 2300 	and.w	r3, r3, #524288	; 0x80000
+ 8002116:	2b00      	cmp	r3, #0
+ 8002118:	d003      	beq.n	8002122 <HAL_RCCEx_PeriphCLKConfig+0x6ee>
+ 800211a:	687b      	ldr	r3, [r7, #4]
+ 800211c:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
+ 800211e:	2b00      	cmp	r3, #0
+ 8002120:	d009      	beq.n	8002136 <HAL_RCCEx_PeriphCLKConfig+0x702>
        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
- 80020ee:	687b      	ldr	r3, [r7, #4]
- 80020f0:	681b      	ldr	r3, [r3, #0]
- 80020f2:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
+ 8002122:	687b      	ldr	r3, [r7, #4]
+ 8002124:	681b      	ldr	r3, [r3, #0]
+ 8002126:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
     if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
- 80020f6:	2b00      	cmp	r3, #0
- 80020f8:	d02e      	beq.n	8002158 <HAL_RCCEx_PeriphCLKConfig+0x758>
+ 800212a:	2b00      	cmp	r3, #0
+ 800212c:	d02e      	beq.n	800218c <HAL_RCCEx_PeriphCLKConfig+0x758>
        ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
- 80020fa:	687b      	ldr	r3, [r7, #4]
- 80020fc:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 80020fe:	2b00      	cmp	r3, #0
- 8002100:	d12a      	bne.n	8002158 <HAL_RCCEx_PeriphCLKConfig+0x758>
+ 800212e:	687b      	ldr	r3, [r7, #4]
+ 8002130:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8002132:	2b00      	cmp	r3, #0
+ 8002134:	d12a      	bne.n	800218c <HAL_RCCEx_PeriphCLKConfig+0x758>
       assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
       /* check for PLLSAI/DIVQ Parameter */
       assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
 
       /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
       tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
- 8002102:	4b51      	ldr	r3, [pc, #324]	; (8002248 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8002104:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 8002108:	0c1b      	lsrs	r3, r3, #16
- 800210a:	f003 0303 	and.w	r3, r3, #3
- 800210e:	613b      	str	r3, [r7, #16]
+ 8002136:	4b51      	ldr	r3, [pc, #324]	; (800227c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002138:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 800213c:	0c1b      	lsrs	r3, r3, #16
+ 800213e:	f003 0303 	and.w	r3, r3, #3
+ 8002142:	613b      	str	r3, [r7, #16]
       tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
- 8002110:	4b4d      	ldr	r3, [pc, #308]	; (8002248 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8002112:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 8002116:	0f1b      	lsrs	r3, r3, #28
- 8002118:	f003 0307 	and.w	r3, r3, #7
- 800211c:	60fb      	str	r3, [r7, #12]
+ 8002144:	4b4d      	ldr	r3, [pc, #308]	; (800227c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002146:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 800214a:	0f1b      	lsrs	r3, r3, #28
+ 800214c:	f003 0307 	and.w	r3, r3, #7
+ 8002150:	60fb      	str	r3, [r7, #12]
       /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
       /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
       /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
- 800211e:	687b      	ldr	r3, [r7, #4]
- 8002120:	695b      	ldr	r3, [r3, #20]
- 8002122:	019a      	lsls	r2, r3, #6
- 8002124:	693b      	ldr	r3, [r7, #16]
- 8002126:	041b      	lsls	r3, r3, #16
- 8002128:	431a      	orrs	r2, r3
- 800212a:	687b      	ldr	r3, [r7, #4]
- 800212c:	699b      	ldr	r3, [r3, #24]
- 800212e:	061b      	lsls	r3, r3, #24
- 8002130:	431a      	orrs	r2, r3
- 8002132:	68fb      	ldr	r3, [r7, #12]
- 8002134:	071b      	lsls	r3, r3, #28
- 8002136:	4944      	ldr	r1, [pc, #272]	; (8002248 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8002138:	4313      	orrs	r3, r2
- 800213a:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
+ 8002152:	687b      	ldr	r3, [r7, #4]
+ 8002154:	695b      	ldr	r3, [r3, #20]
+ 8002156:	019a      	lsls	r2, r3, #6
+ 8002158:	693b      	ldr	r3, [r7, #16]
+ 800215a:	041b      	lsls	r3, r3, #16
+ 800215c:	431a      	orrs	r2, r3
+ 800215e:	687b      	ldr	r3, [r7, #4]
+ 8002160:	699b      	ldr	r3, [r3, #24]
+ 8002162:	061b      	lsls	r3, r3, #24
+ 8002164:	431a      	orrs	r2, r3
+ 8002166:	68fb      	ldr	r3, [r7, #12]
+ 8002168:	071b      	lsls	r3, r3, #28
+ 800216a:	4944      	ldr	r1, [pc, #272]	; (800227c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 800216c:	4313      	orrs	r3, r2
+ 800216e:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
 
       /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
       __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
- 800213e:	4b42      	ldr	r3, [pc, #264]	; (8002248 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8002140:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
- 8002144:	f423 52f8 	bic.w	r2, r3, #7936	; 0x1f00
- 8002148:	687b      	ldr	r3, [r7, #4]
- 800214a:	6a9b      	ldr	r3, [r3, #40]	; 0x28
- 800214c:	3b01      	subs	r3, #1
- 800214e:	021b      	lsls	r3, r3, #8
- 8002150:	493d      	ldr	r1, [pc, #244]	; (8002248 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8002152:	4313      	orrs	r3, r2
- 8002154:	f8c1 308c 	str.w	r3, [r1, #140]	; 0x8c
+ 8002172:	4b42      	ldr	r3, [pc, #264]	; (800227c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002174:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
+ 8002178:	f423 52f8 	bic.w	r2, r3, #7936	; 0x1f00
+ 800217c:	687b      	ldr	r3, [r7, #4]
+ 800217e:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 8002180:	3b01      	subs	r3, #1
+ 8002182:	021b      	lsls	r3, r3, #8
+ 8002184:	493d      	ldr	r1, [pc, #244]	; (800227c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002186:	4313      	orrs	r3, r2
+ 8002188:	f8c1 308c 	str.w	r3, [r1, #140]	; 0x8c
     }
 
     /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
     /* In Case of PLLI2S is selected as source clock for CK48 */
     if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
- 8002158:	687b      	ldr	r3, [r7, #4]
- 800215a:	681b      	ldr	r3, [r3, #0]
- 800215c:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
- 8002160:	2b00      	cmp	r3, #0
- 8002162:	d022      	beq.n	80021aa <HAL_RCCEx_PeriphCLKConfig+0x7aa>
- 8002164:	687b      	ldr	r3, [r7, #4]
- 8002166:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
- 8002168:	f1b3 6f00 	cmp.w	r3, #134217728	; 0x8000000
- 800216c:	d11d      	bne.n	80021aa <HAL_RCCEx_PeriphCLKConfig+0x7aa>
+ 800218c:	687b      	ldr	r3, [r7, #4]
+ 800218e:	681b      	ldr	r3, [r3, #0]
+ 8002190:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
+ 8002194:	2b00      	cmp	r3, #0
+ 8002196:	d022      	beq.n	80021de <HAL_RCCEx_PeriphCLKConfig+0x7aa>
+ 8002198:	687b      	ldr	r3, [r7, #4]
+ 800219a:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
+ 800219c:	f1b3 6f00 	cmp.w	r3, #134217728	; 0x8000000
+ 80021a0:	d11d      	bne.n	80021de <HAL_RCCEx_PeriphCLKConfig+0x7aa>
     {
       /* check for Parameters */
       assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
       /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
       tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
- 800216e:	4b36      	ldr	r3, [pc, #216]	; (8002248 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8002170:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 8002174:	0e1b      	lsrs	r3, r3, #24
- 8002176:	f003 030f 	and.w	r3, r3, #15
- 800217a:	613b      	str	r3, [r7, #16]
+ 80021a2:	4b36      	ldr	r3, [pc, #216]	; (800227c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80021a4:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 80021a8:	0e1b      	lsrs	r3, r3, #24
+ 80021aa:	f003 030f 	and.w	r3, r3, #15
+ 80021ae:	613b      	str	r3, [r7, #16]
       tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
- 800217c:	4b32      	ldr	r3, [pc, #200]	; (8002248 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800217e:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 8002182:	0f1b      	lsrs	r3, r3, #28
- 8002184:	f003 0307 	and.w	r3, r3, #7
- 8002188:	60fb      	str	r3, [r7, #12]
+ 80021b0:	4b32      	ldr	r3, [pc, #200]	; (800227c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80021b2:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 80021b6:	0f1b      	lsrs	r3, r3, #28
+ 80021b8:	f003 0307 	and.w	r3, r3, #7
+ 80021bc:	60fb      	str	r3, [r7, #12]
 
       /* Configure the PLLSAI division factors */
       /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
       /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
- 800218a:	687b      	ldr	r3, [r7, #4]
- 800218c:	695b      	ldr	r3, [r3, #20]
- 800218e:	019a      	lsls	r2, r3, #6
- 8002190:	687b      	ldr	r3, [r7, #4]
- 8002192:	6a1b      	ldr	r3, [r3, #32]
- 8002194:	041b      	lsls	r3, r3, #16
- 8002196:	431a      	orrs	r2, r3
- 8002198:	693b      	ldr	r3, [r7, #16]
- 800219a:	061b      	lsls	r3, r3, #24
- 800219c:	431a      	orrs	r2, r3
- 800219e:	68fb      	ldr	r3, [r7, #12]
- 80021a0:	071b      	lsls	r3, r3, #28
- 80021a2:	4929      	ldr	r1, [pc, #164]	; (8002248 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80021a4:	4313      	orrs	r3, r2
- 80021a6:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
+ 80021be:	687b      	ldr	r3, [r7, #4]
+ 80021c0:	695b      	ldr	r3, [r3, #20]
+ 80021c2:	019a      	lsls	r2, r3, #6
+ 80021c4:	687b      	ldr	r3, [r7, #4]
+ 80021c6:	6a1b      	ldr	r3, [r3, #32]
+ 80021c8:	041b      	lsls	r3, r3, #16
+ 80021ca:	431a      	orrs	r2, r3
+ 80021cc:	693b      	ldr	r3, [r7, #16]
+ 80021ce:	061b      	lsls	r3, r3, #24
+ 80021d0:	431a      	orrs	r2, r3
+ 80021d2:	68fb      	ldr	r3, [r7, #12]
+ 80021d4:	071b      	lsls	r3, r3, #28
+ 80021d6:	4929      	ldr	r1, [pc, #164]	; (800227c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80021d8:	4313      	orrs	r3, r2
+ 80021da:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
     }
 
 #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
     /*---------------------------- LTDC configuration -------------------------------*/
     if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
- 80021aa:	687b      	ldr	r3, [r7, #4]
- 80021ac:	681b      	ldr	r3, [r3, #0]
- 80021ae:	f003 0308 	and.w	r3, r3, #8
- 80021b2:	2b00      	cmp	r3, #0
- 80021b4:	d028      	beq.n	8002208 <HAL_RCCEx_PeriphCLKConfig+0x808>
+ 80021de:	687b      	ldr	r3, [r7, #4]
+ 80021e0:	681b      	ldr	r3, [r3, #0]
+ 80021e2:	f003 0308 	and.w	r3, r3, #8
+ 80021e6:	2b00      	cmp	r3, #0
+ 80021e8:	d028      	beq.n	800223c <HAL_RCCEx_PeriphCLKConfig+0x808>
     {
       assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
       assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
 
       /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
       tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
- 80021b6:	4b24      	ldr	r3, [pc, #144]	; (8002248 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80021b8:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 80021bc:	0e1b      	lsrs	r3, r3, #24
- 80021be:	f003 030f 	and.w	r3, r3, #15
- 80021c2:	613b      	str	r3, [r7, #16]
+ 80021ea:	4b24      	ldr	r3, [pc, #144]	; (800227c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80021ec:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 80021f0:	0e1b      	lsrs	r3, r3, #24
+ 80021f2:	f003 030f 	and.w	r3, r3, #15
+ 80021f6:	613b      	str	r3, [r7, #16]
       tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
- 80021c4:	4b20      	ldr	r3, [pc, #128]	; (8002248 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80021c6:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 80021ca:	0c1b      	lsrs	r3, r3, #16
- 80021cc:	f003 0303 	and.w	r3, r3, #3
- 80021d0:	60fb      	str	r3, [r7, #12]
+ 80021f8:	4b20      	ldr	r3, [pc, #128]	; (800227c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80021fa:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 80021fe:	0c1b      	lsrs	r3, r3, #16
+ 8002200:	f003 0303 	and.w	r3, r3, #3
+ 8002204:	60fb      	str	r3, [r7, #12]
 
       /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
       /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
       /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
- 80021d2:	687b      	ldr	r3, [r7, #4]
- 80021d4:	695b      	ldr	r3, [r3, #20]
- 80021d6:	019a      	lsls	r2, r3, #6
- 80021d8:	68fb      	ldr	r3, [r7, #12]
- 80021da:	041b      	lsls	r3, r3, #16
- 80021dc:	431a      	orrs	r2, r3
- 80021de:	693b      	ldr	r3, [r7, #16]
- 80021e0:	061b      	lsls	r3, r3, #24
- 80021e2:	431a      	orrs	r2, r3
- 80021e4:	687b      	ldr	r3, [r7, #4]
- 80021e6:	69db      	ldr	r3, [r3, #28]
- 80021e8:	071b      	lsls	r3, r3, #28
- 80021ea:	4917      	ldr	r1, [pc, #92]	; (8002248 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80021ec:	4313      	orrs	r3, r2
- 80021ee:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
+ 8002206:	687b      	ldr	r3, [r7, #4]
+ 8002208:	695b      	ldr	r3, [r3, #20]
+ 800220a:	019a      	lsls	r2, r3, #6
+ 800220c:	68fb      	ldr	r3, [r7, #12]
+ 800220e:	041b      	lsls	r3, r3, #16
+ 8002210:	431a      	orrs	r2, r3
+ 8002212:	693b      	ldr	r3, [r7, #16]
+ 8002214:	061b      	lsls	r3, r3, #24
+ 8002216:	431a      	orrs	r2, r3
+ 8002218:	687b      	ldr	r3, [r7, #4]
+ 800221a:	69db      	ldr	r3, [r3, #28]
+ 800221c:	071b      	lsls	r3, r3, #28
+ 800221e:	4917      	ldr	r1, [pc, #92]	; (800227c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002220:	4313      	orrs	r3, r2
+ 8002222:	f8c1 3088 	str.w	r3, [r1, #136]	; 0x88
 
       /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
       __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
- 80021f2:	4b15      	ldr	r3, [pc, #84]	; (8002248 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80021f4:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
- 80021f8:	f423 3240 	bic.w	r2, r3, #196608	; 0x30000
- 80021fc:	687b      	ldr	r3, [r7, #4]
- 80021fe:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8002200:	4911      	ldr	r1, [pc, #68]	; (8002248 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8002202:	4313      	orrs	r3, r2
- 8002204:	f8c1 308c 	str.w	r3, [r1, #140]	; 0x8c
+ 8002226:	4b15      	ldr	r3, [pc, #84]	; (800227c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002228:	f8d3 308c 	ldr.w	r3, [r3, #140]	; 0x8c
+ 800222c:	f423 3240 	bic.w	r2, r3, #196608	; 0x30000
+ 8002230:	687b      	ldr	r3, [r7, #4]
+ 8002232:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8002234:	4911      	ldr	r1, [pc, #68]	; (800227c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002236:	4313      	orrs	r3, r2
+ 8002238:	f8c1 308c 	str.w	r3, [r1, #140]	; 0x8c
     }
 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx  */
 
     /* Enable PLLSAI Clock */
     __HAL_RCC_PLLSAI_ENABLE();
- 8002208:	4b0f      	ldr	r3, [pc, #60]	; (8002248 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800220a:	681b      	ldr	r3, [r3, #0]
- 800220c:	4a0e      	ldr	r2, [pc, #56]	; (8002248 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800220e:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
- 8002212:	6013      	str	r3, [r2, #0]
+ 800223c:	4b0f      	ldr	r3, [pc, #60]	; (800227c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 800223e:	681b      	ldr	r3, [r3, #0]
+ 8002240:	4a0e      	ldr	r2, [pc, #56]	; (800227c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002242:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
+ 8002246:	6013      	str	r3, [r2, #0]
 
     /* Get Start Tick*/
     tickstart = HAL_GetTick();
- 8002214:	f7fe f9e2 	bl	80005dc <HAL_GetTick>
- 8002218:	6178      	str	r0, [r7, #20]
+ 8002248:	f7fe f9c8 	bl	80005dc <HAL_GetTick>
+ 800224c:	6178      	str	r0, [r7, #20]
 
     /* Wait till PLLSAI is ready */
     while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
- 800221a:	e008      	b.n	800222e <HAL_RCCEx_PeriphCLKConfig+0x82e>
+ 800224e:	e008      	b.n	8002262 <HAL_RCCEx_PeriphCLKConfig+0x82e>
     {
       if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
- 800221c:	f7fe f9de 	bl	80005dc <HAL_GetTick>
- 8002220:	4602      	mov	r2, r0
- 8002222:	697b      	ldr	r3, [r7, #20]
- 8002224:	1ad3      	subs	r3, r2, r3
- 8002226:	2b64      	cmp	r3, #100	; 0x64
- 8002228:	d901      	bls.n	800222e <HAL_RCCEx_PeriphCLKConfig+0x82e>
+ 8002250:	f7fe f9c4 	bl	80005dc <HAL_GetTick>
+ 8002254:	4602      	mov	r2, r0
+ 8002256:	697b      	ldr	r3, [r7, #20]
+ 8002258:	1ad3      	subs	r3, r2, r3
+ 800225a:	2b64      	cmp	r3, #100	; 0x64
+ 800225c:	d901      	bls.n	8002262 <HAL_RCCEx_PeriphCLKConfig+0x82e>
       {
         /* return in case of Timeout detected */
         return HAL_TIMEOUT;
- 800222a:	2303      	movs	r3, #3
- 800222c:	e007      	b.n	800223e <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 800225e:	2303      	movs	r3, #3
+ 8002260:	e007      	b.n	8002272 <HAL_RCCEx_PeriphCLKConfig+0x83e>
     while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
- 800222e:	4b06      	ldr	r3, [pc, #24]	; (8002248 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8002230:	681b      	ldr	r3, [r3, #0]
- 8002232:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
- 8002236:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
- 800223a:	d1ef      	bne.n	800221c <HAL_RCCEx_PeriphCLKConfig+0x81c>
+ 8002262:	4b06      	ldr	r3, [pc, #24]	; (800227c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002264:	681b      	ldr	r3, [r3, #0]
+ 8002266:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
+ 800226a:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
+ 800226e:	d1ef      	bne.n	8002250 <HAL_RCCEx_PeriphCLKConfig+0x81c>
       }
     }
   }
   return HAL_OK;
- 800223c:	2300      	movs	r3, #0
+ 8002270:	2300      	movs	r3, #0
 }
- 800223e:	4618      	mov	r0, r3
- 8002240:	3720      	adds	r7, #32
- 8002242:	46bd      	mov	sp, r7
- 8002244:	bd80      	pop	{r7, pc}
- 8002246:	bf00      	nop
- 8002248:	40023800 	.word	0x40023800
-
-0800224c <HAL_TIM_Encoder_Init>:
+ 8002272:	4618      	mov	r0, r3
+ 8002274:	3720      	adds	r7, #32
+ 8002276:	46bd      	mov	sp, r7
+ 8002278:	bd80      	pop	{r7, pc}
+ 800227a:	bf00      	nop
+ 800227c:	40023800 	.word	0x40023800
+
+08002280 <HAL_TIM_PWM_Init>:
+  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+ 8002280:	b580      	push	{r7, lr}
+ 8002282:	b082      	sub	sp, #8
+ 8002284:	af00      	add	r7, sp, #0
+ 8002286:	6078      	str	r0, [r7, #4]
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+ 8002288:	687b      	ldr	r3, [r7, #4]
+ 800228a:	2b00      	cmp	r3, #0
+ 800228c:	d101      	bne.n	8002292 <HAL_TIM_PWM_Init+0x12>
+  {
+    return HAL_ERROR;
+ 800228e:	2301      	movs	r3, #1
+ 8002290:	e01d      	b.n	80022ce <HAL_TIM_PWM_Init+0x4e>
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+ 8002292:	687b      	ldr	r3, [r7, #4]
+ 8002294:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
+ 8002298:	b2db      	uxtb	r3, r3
+ 800229a:	2b00      	cmp	r3, #0
+ 800229c:	d106      	bne.n	80022ac <HAL_TIM_PWM_Init+0x2c>
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+ 800229e:	687b      	ldr	r3, [r7, #4]
+ 80022a0:	2200      	movs	r2, #0
+ 80022a2:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->PWM_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_PWM_MspInit(htim);
+ 80022a6:	6878      	ldr	r0, [r7, #4]
+ 80022a8:	f001 fed6 	bl	8004058 <HAL_TIM_PWM_MspInit>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+ 80022ac:	687b      	ldr	r3, [r7, #4]
+ 80022ae:	2202      	movs	r2, #2
+ 80022b0:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+
+  /* Init the base time for the PWM */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ 80022b4:	687b      	ldr	r3, [r7, #4]
+ 80022b6:	681a      	ldr	r2, [r3, #0]
+ 80022b8:	687b      	ldr	r3, [r7, #4]
+ 80022ba:	3304      	adds	r3, #4
+ 80022bc:	4619      	mov	r1, r3
+ 80022be:	4610      	mov	r0, r2
+ 80022c0:	f000 f9ec 	bl	800269c <TIM_Base_SetConfig>
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+ 80022c4:	687b      	ldr	r3, [r7, #4]
+ 80022c6:	2201      	movs	r2, #1
+ 80022c8:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+
+  return HAL_OK;
+ 80022cc:	2300      	movs	r3, #0
+}
+ 80022ce:	4618      	mov	r0, r3
+ 80022d0:	3708      	adds	r7, #8
+ 80022d2:	46bd      	mov	sp, r7
+ 80022d4:	bd80      	pop	{r7, pc}
+	...
+
+080022d8 <HAL_TIM_Encoder_Init>:
   * @param  htim TIM Encoder Interface handle
   * @param  sConfig TIM Encoder Interface configuration structure
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
 {
- 800224c:	b580      	push	{r7, lr}
- 800224e:	b086      	sub	sp, #24
- 8002250:	af00      	add	r7, sp, #0
- 8002252:	6078      	str	r0, [r7, #4]
- 8002254:	6039      	str	r1, [r7, #0]
+ 80022d8:	b580      	push	{r7, lr}
+ 80022da:	b086      	sub	sp, #24
+ 80022dc:	af00      	add	r7, sp, #0
+ 80022de:	6078      	str	r0, [r7, #4]
+ 80022e0:	6039      	str	r1, [r7, #0]
   uint32_t tmpsmcr;
   uint32_t tmpccmr1;
   uint32_t tmpccer;
 
   /* Check the TIM handle allocation */
   if (htim == NULL)
- 8002256:	687b      	ldr	r3, [r7, #4]
- 8002258:	2b00      	cmp	r3, #0
- 800225a:	d101      	bne.n	8002260 <HAL_TIM_Encoder_Init+0x14>
+ 80022e2:	687b      	ldr	r3, [r7, #4]
+ 80022e4:	2b00      	cmp	r3, #0
+ 80022e6:	d101      	bne.n	80022ec <HAL_TIM_Encoder_Init+0x14>
   {
     return HAL_ERROR;
- 800225c:	2301      	movs	r3, #1
- 800225e:	e07b      	b.n	8002358 <HAL_TIM_Encoder_Init+0x10c>
+ 80022e8:	2301      	movs	r3, #1
+ 80022ea:	e07b      	b.n	80023e4 <HAL_TIM_Encoder_Init+0x10c>
   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
 
   if (htim->State == HAL_TIM_STATE_RESET)
- 8002260:	687b      	ldr	r3, [r7, #4]
- 8002262:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
- 8002266:	b2db      	uxtb	r3, r3
- 8002268:	2b00      	cmp	r3, #0
- 800226a:	d106      	bne.n	800227a <HAL_TIM_Encoder_Init+0x2e>
+ 80022ec:	687b      	ldr	r3, [r7, #4]
+ 80022ee:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
+ 80022f2:	b2db      	uxtb	r3, r3
+ 80022f4:	2b00      	cmp	r3, #0
+ 80022f6:	d106      	bne.n	8002306 <HAL_TIM_Encoder_Init+0x2e>
   {
     /* Allocate lock resource and initialize it */
     htim->Lock = HAL_UNLOCKED;
- 800226c:	687b      	ldr	r3, [r7, #4]
- 800226e:	2200      	movs	r2, #0
- 8002270:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
+ 80022f8:	687b      	ldr	r3, [r7, #4]
+ 80022fa:	2200      	movs	r2, #0
+ 80022fc:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
     }
     /* Init the low level hardware : GPIO, CLOCK, NVIC */
     htim->Encoder_MspInitCallback(htim);
 #else
     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
     HAL_TIM_Encoder_MspInit(htim);
- 8002274:	6878      	ldr	r0, [r7, #4]
- 8002276:	f001 f8a3 	bl	80033c0 <HAL_TIM_Encoder_MspInit>
+ 8002300:	6878      	ldr	r0, [r7, #4]
+ 8002302:	f001 fe19 	bl	8003f38 <HAL_TIM_Encoder_MspInit>
 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
   }
 
   /* Set the TIM state */
   htim->State = HAL_TIM_STATE_BUSY;
- 800227a:	687b      	ldr	r3, [r7, #4]
- 800227c:	2202      	movs	r2, #2
- 800227e:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+ 8002306:	687b      	ldr	r3, [r7, #4]
+ 8002308:	2202      	movs	r2, #2
+ 800230a:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
 
   /* Reset the SMS and ECE bits */
   htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
- 8002282:	687b      	ldr	r3, [r7, #4]
- 8002284:	681b      	ldr	r3, [r3, #0]
- 8002286:	6899      	ldr	r1, [r3, #8]
- 8002288:	687b      	ldr	r3, [r7, #4]
- 800228a:	681a      	ldr	r2, [r3, #0]
- 800228c:	4b34      	ldr	r3, [pc, #208]	; (8002360 <HAL_TIM_Encoder_Init+0x114>)
- 800228e:	400b      	ands	r3, r1
- 8002290:	6093      	str	r3, [r2, #8]
+ 800230e:	687b      	ldr	r3, [r7, #4]
+ 8002310:	681b      	ldr	r3, [r3, #0]
+ 8002312:	6899      	ldr	r1, [r3, #8]
+ 8002314:	687b      	ldr	r3, [r7, #4]
+ 8002316:	681a      	ldr	r2, [r3, #0]
+ 8002318:	4b34      	ldr	r3, [pc, #208]	; (80023ec <HAL_TIM_Encoder_Init+0x114>)
+ 800231a:	400b      	ands	r3, r1
+ 800231c:	6093      	str	r3, [r2, #8]
 
   /* Configure the Time base in the Encoder Mode */
   TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 8002292:	687b      	ldr	r3, [r7, #4]
- 8002294:	681a      	ldr	r2, [r3, #0]
- 8002296:	687b      	ldr	r3, [r7, #4]
- 8002298:	3304      	adds	r3, #4
- 800229a:	4619      	mov	r1, r3
- 800229c:	4610      	mov	r0, r2
- 800229e:	f000 f867 	bl	8002370 <TIM_Base_SetConfig>
+ 800231e:	687b      	ldr	r3, [r7, #4]
+ 8002320:	681a      	ldr	r2, [r3, #0]
+ 8002322:	687b      	ldr	r3, [r7, #4]
+ 8002324:	3304      	adds	r3, #4
+ 8002326:	4619      	mov	r1, r3
+ 8002328:	4610      	mov	r0, r2
+ 800232a:	f000 f9b7 	bl	800269c <TIM_Base_SetConfig>
 
   /* Get the TIMx SMCR register value */
   tmpsmcr = htim->Instance->SMCR;
- 80022a2:	687b      	ldr	r3, [r7, #4]
- 80022a4:	681b      	ldr	r3, [r3, #0]
- 80022a6:	689b      	ldr	r3, [r3, #8]
- 80022a8:	617b      	str	r3, [r7, #20]
+ 800232e:	687b      	ldr	r3, [r7, #4]
+ 8002330:	681b      	ldr	r3, [r3, #0]
+ 8002332:	689b      	ldr	r3, [r3, #8]
+ 8002334:	617b      	str	r3, [r7, #20]
 
   /* Get the TIMx CCMR1 register value */
   tmpccmr1 = htim->Instance->CCMR1;
- 80022aa:	687b      	ldr	r3, [r7, #4]
- 80022ac:	681b      	ldr	r3, [r3, #0]
- 80022ae:	699b      	ldr	r3, [r3, #24]
- 80022b0:	613b      	str	r3, [r7, #16]
+ 8002336:	687b      	ldr	r3, [r7, #4]
+ 8002338:	681b      	ldr	r3, [r3, #0]
+ 800233a:	699b      	ldr	r3, [r3, #24]
+ 800233c:	613b      	str	r3, [r7, #16]
 
   /* Get the TIMx CCER register value */
   tmpccer = htim->Instance->CCER;
- 80022b2:	687b      	ldr	r3, [r7, #4]
- 80022b4:	681b      	ldr	r3, [r3, #0]
- 80022b6:	6a1b      	ldr	r3, [r3, #32]
- 80022b8:	60fb      	str	r3, [r7, #12]
+ 800233e:	687b      	ldr	r3, [r7, #4]
+ 8002340:	681b      	ldr	r3, [r3, #0]
+ 8002342:	6a1b      	ldr	r3, [r3, #32]
+ 8002344:	60fb      	str	r3, [r7, #12]
 
   /* Set the encoder Mode */
   tmpsmcr |= sConfig->EncoderMode;
- 80022ba:	683b      	ldr	r3, [r7, #0]
- 80022bc:	681b      	ldr	r3, [r3, #0]
- 80022be:	697a      	ldr	r2, [r7, #20]
- 80022c0:	4313      	orrs	r3, r2
- 80022c2:	617b      	str	r3, [r7, #20]
+ 8002346:	683b      	ldr	r3, [r7, #0]
+ 8002348:	681b      	ldr	r3, [r3, #0]
+ 800234a:	697a      	ldr	r2, [r7, #20]
+ 800234c:	4313      	orrs	r3, r2
+ 800234e:	617b      	str	r3, [r7, #20]
 
   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
- 80022c4:	693a      	ldr	r2, [r7, #16]
- 80022c6:	4b27      	ldr	r3, [pc, #156]	; (8002364 <HAL_TIM_Encoder_Init+0x118>)
- 80022c8:	4013      	ands	r3, r2
- 80022ca:	613b      	str	r3, [r7, #16]
+ 8002350:	693a      	ldr	r2, [r7, #16]
+ 8002352:	4b27      	ldr	r3, [pc, #156]	; (80023f0 <HAL_TIM_Encoder_Init+0x118>)
+ 8002354:	4013      	ands	r3, r2
+ 8002356:	613b      	str	r3, [r7, #16]
   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
- 80022cc:	683b      	ldr	r3, [r7, #0]
- 80022ce:	689a      	ldr	r2, [r3, #8]
- 80022d0:	683b      	ldr	r3, [r7, #0]
- 80022d2:	699b      	ldr	r3, [r3, #24]
- 80022d4:	021b      	lsls	r3, r3, #8
- 80022d6:	4313      	orrs	r3, r2
- 80022d8:	693a      	ldr	r2, [r7, #16]
- 80022da:	4313      	orrs	r3, r2
- 80022dc:	613b      	str	r3, [r7, #16]
+ 8002358:	683b      	ldr	r3, [r7, #0]
+ 800235a:	689a      	ldr	r2, [r3, #8]
+ 800235c:	683b      	ldr	r3, [r7, #0]
+ 800235e:	699b      	ldr	r3, [r3, #24]
+ 8002360:	021b      	lsls	r3, r3, #8
+ 8002362:	4313      	orrs	r3, r2
+ 8002364:	693a      	ldr	r2, [r7, #16]
+ 8002366:	4313      	orrs	r3, r2
+ 8002368:	613b      	str	r3, [r7, #16]
 
   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
- 80022de:	693a      	ldr	r2, [r7, #16]
- 80022e0:	4b21      	ldr	r3, [pc, #132]	; (8002368 <HAL_TIM_Encoder_Init+0x11c>)
- 80022e2:	4013      	ands	r3, r2
- 80022e4:	613b      	str	r3, [r7, #16]
+ 800236a:	693a      	ldr	r2, [r7, #16]
+ 800236c:	4b21      	ldr	r3, [pc, #132]	; (80023f4 <HAL_TIM_Encoder_Init+0x11c>)
+ 800236e:	4013      	ands	r3, r2
+ 8002370:	613b      	str	r3, [r7, #16]
   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
- 80022e6:	693a      	ldr	r2, [r7, #16]
- 80022e8:	4b20      	ldr	r3, [pc, #128]	; (800236c <HAL_TIM_Encoder_Init+0x120>)
- 80022ea:	4013      	ands	r3, r2
- 80022ec:	613b      	str	r3, [r7, #16]
+ 8002372:	693a      	ldr	r2, [r7, #16]
+ 8002374:	4b20      	ldr	r3, [pc, #128]	; (80023f8 <HAL_TIM_Encoder_Init+0x120>)
+ 8002376:	4013      	ands	r3, r2
+ 8002378:	613b      	str	r3, [r7, #16]
   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
- 80022ee:	683b      	ldr	r3, [r7, #0]
- 80022f0:	68da      	ldr	r2, [r3, #12]
- 80022f2:	683b      	ldr	r3, [r7, #0]
- 80022f4:	69db      	ldr	r3, [r3, #28]
- 80022f6:	021b      	lsls	r3, r3, #8
- 80022f8:	4313      	orrs	r3, r2
- 80022fa:	693a      	ldr	r2, [r7, #16]
- 80022fc:	4313      	orrs	r3, r2
- 80022fe:	613b      	str	r3, [r7, #16]
+ 800237a:	683b      	ldr	r3, [r7, #0]
+ 800237c:	68da      	ldr	r2, [r3, #12]
+ 800237e:	683b      	ldr	r3, [r7, #0]
+ 8002380:	69db      	ldr	r3, [r3, #28]
+ 8002382:	021b      	lsls	r3, r3, #8
+ 8002384:	4313      	orrs	r3, r2
+ 8002386:	693a      	ldr	r2, [r7, #16]
+ 8002388:	4313      	orrs	r3, r2
+ 800238a:	613b      	str	r3, [r7, #16]
   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
- 8002300:	683b      	ldr	r3, [r7, #0]
- 8002302:	691b      	ldr	r3, [r3, #16]
- 8002304:	011a      	lsls	r2, r3, #4
- 8002306:	683b      	ldr	r3, [r7, #0]
- 8002308:	6a1b      	ldr	r3, [r3, #32]
- 800230a:	031b      	lsls	r3, r3, #12
- 800230c:	4313      	orrs	r3, r2
- 800230e:	693a      	ldr	r2, [r7, #16]
- 8002310:	4313      	orrs	r3, r2
- 8002312:	613b      	str	r3, [r7, #16]
+ 800238c:	683b      	ldr	r3, [r7, #0]
+ 800238e:	691b      	ldr	r3, [r3, #16]
+ 8002390:	011a      	lsls	r2, r3, #4
+ 8002392:	683b      	ldr	r3, [r7, #0]
+ 8002394:	6a1b      	ldr	r3, [r3, #32]
+ 8002396:	031b      	lsls	r3, r3, #12
+ 8002398:	4313      	orrs	r3, r2
+ 800239a:	693a      	ldr	r2, [r7, #16]
+ 800239c:	4313      	orrs	r3, r2
+ 800239e:	613b      	str	r3, [r7, #16]
 
   /* Set the TI1 and the TI2 Polarities */
   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
- 8002314:	68fb      	ldr	r3, [r7, #12]
- 8002316:	f023 0322 	bic.w	r3, r3, #34	; 0x22
- 800231a:	60fb      	str	r3, [r7, #12]
+ 80023a0:	68fb      	ldr	r3, [r7, #12]
+ 80023a2:	f023 0322 	bic.w	r3, r3, #34	; 0x22
+ 80023a6:	60fb      	str	r3, [r7, #12]
   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
- 800231c:	68fb      	ldr	r3, [r7, #12]
- 800231e:	f023 0388 	bic.w	r3, r3, #136	; 0x88
- 8002322:	60fb      	str	r3, [r7, #12]
+ 80023a8:	68fb      	ldr	r3, [r7, #12]
+ 80023aa:	f023 0388 	bic.w	r3, r3, #136	; 0x88
+ 80023ae:	60fb      	str	r3, [r7, #12]
   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
- 8002324:	683b      	ldr	r3, [r7, #0]
- 8002326:	685a      	ldr	r2, [r3, #4]
- 8002328:	683b      	ldr	r3, [r7, #0]
- 800232a:	695b      	ldr	r3, [r3, #20]
- 800232c:	011b      	lsls	r3, r3, #4
- 800232e:	4313      	orrs	r3, r2
- 8002330:	68fa      	ldr	r2, [r7, #12]
- 8002332:	4313      	orrs	r3, r2
- 8002334:	60fb      	str	r3, [r7, #12]
+ 80023b0:	683b      	ldr	r3, [r7, #0]
+ 80023b2:	685a      	ldr	r2, [r3, #4]
+ 80023b4:	683b      	ldr	r3, [r7, #0]
+ 80023b6:	695b      	ldr	r3, [r3, #20]
+ 80023b8:	011b      	lsls	r3, r3, #4
+ 80023ba:	4313      	orrs	r3, r2
+ 80023bc:	68fa      	ldr	r2, [r7, #12]
+ 80023be:	4313      	orrs	r3, r2
+ 80023c0:	60fb      	str	r3, [r7, #12]
 
   /* Write to TIMx SMCR */
   htim->Instance->SMCR = tmpsmcr;
- 8002336:	687b      	ldr	r3, [r7, #4]
- 8002338:	681b      	ldr	r3, [r3, #0]
- 800233a:	697a      	ldr	r2, [r7, #20]
- 800233c:	609a      	str	r2, [r3, #8]
+ 80023c2:	687b      	ldr	r3, [r7, #4]
+ 80023c4:	681b      	ldr	r3, [r3, #0]
+ 80023c6:	697a      	ldr	r2, [r7, #20]
+ 80023c8:	609a      	str	r2, [r3, #8]
 
   /* Write to TIMx CCMR1 */
   htim->Instance->CCMR1 = tmpccmr1;
- 800233e:	687b      	ldr	r3, [r7, #4]
- 8002340:	681b      	ldr	r3, [r3, #0]
- 8002342:	693a      	ldr	r2, [r7, #16]
- 8002344:	619a      	str	r2, [r3, #24]
+ 80023ca:	687b      	ldr	r3, [r7, #4]
+ 80023cc:	681b      	ldr	r3, [r3, #0]
+ 80023ce:	693a      	ldr	r2, [r7, #16]
+ 80023d0:	619a      	str	r2, [r3, #24]
 
   /* Write to TIMx CCER */
   htim->Instance->CCER = tmpccer;
- 8002346:	687b      	ldr	r3, [r7, #4]
- 8002348:	681b      	ldr	r3, [r3, #0]
- 800234a:	68fa      	ldr	r2, [r7, #12]
- 800234c:	621a      	str	r2, [r3, #32]
+ 80023d2:	687b      	ldr	r3, [r7, #4]
+ 80023d4:	681b      	ldr	r3, [r3, #0]
+ 80023d6:	68fa      	ldr	r2, [r7, #12]
+ 80023d8:	621a      	str	r2, [r3, #32]
 
   /* Initialize the TIM state*/
   htim->State = HAL_TIM_STATE_READY;
- 800234e:	687b      	ldr	r3, [r7, #4]
- 8002350:	2201      	movs	r2, #1
- 8002352:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+ 80023da:	687b      	ldr	r3, [r7, #4]
+ 80023dc:	2201      	movs	r2, #1
+ 80023de:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+
+  return HAL_OK;
+ 80023e2:	2300      	movs	r3, #0
+}
+ 80023e4:	4618      	mov	r0, r3
+ 80023e6:	3718      	adds	r7, #24
+ 80023e8:	46bd      	mov	sp, r7
+ 80023ea:	bd80      	pop	{r7, pc}
+ 80023ec:	fffebff8 	.word	0xfffebff8
+ 80023f0:	fffffcfc 	.word	0xfffffcfc
+ 80023f4:	fffff3f3 	.word	0xfffff3f3
+ 80023f8:	ffff0f0f 	.word	0xffff0f0f
+
+080023fc <HAL_TIM_Encoder_Start>:
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ 80023fc:	b580      	push	{r7, lr}
+ 80023fe:	b082      	sub	sp, #8
+ 8002400:	af00      	add	r7, sp, #0
+ 8002402:	6078      	str	r0, [r7, #4]
+ 8002404:	6039      	str	r1, [r7, #0]
+  /* Check the parameters */
+  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+  /* Enable the encoder interface channels */
+  switch (Channel)
+ 8002406:	683b      	ldr	r3, [r7, #0]
+ 8002408:	2b00      	cmp	r3, #0
+ 800240a:	d002      	beq.n	8002412 <HAL_TIM_Encoder_Start+0x16>
+ 800240c:	2b04      	cmp	r3, #4
+ 800240e:	d008      	beq.n	8002422 <HAL_TIM_Encoder_Start+0x26>
+ 8002410:	e00f      	b.n	8002432 <HAL_TIM_Encoder_Start+0x36>
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ 8002412:	687b      	ldr	r3, [r7, #4]
+ 8002414:	681b      	ldr	r3, [r3, #0]
+ 8002416:	2201      	movs	r2, #1
+ 8002418:	2100      	movs	r1, #0
+ 800241a:	4618      	mov	r0, r3
+ 800241c:	f000 fc3c 	bl	8002c98 <TIM_CCxChannelCmd>
+      break;
+ 8002420:	e016      	b.n	8002450 <HAL_TIM_Encoder_Start+0x54>
+    }
 
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 8002422:	687b      	ldr	r3, [r7, #4]
+ 8002424:	681b      	ldr	r3, [r3, #0]
+ 8002426:	2201      	movs	r2, #1
+ 8002428:	2104      	movs	r1, #4
+ 800242a:	4618      	mov	r0, r3
+ 800242c:	f000 fc34 	bl	8002c98 <TIM_CCxChannelCmd>
+      break;
+ 8002430:	e00e      	b.n	8002450 <HAL_TIM_Encoder_Start+0x54>
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ 8002432:	687b      	ldr	r3, [r7, #4]
+ 8002434:	681b      	ldr	r3, [r3, #0]
+ 8002436:	2201      	movs	r2, #1
+ 8002438:	2100      	movs	r1, #0
+ 800243a:	4618      	mov	r0, r3
+ 800243c:	f000 fc2c 	bl	8002c98 <TIM_CCxChannelCmd>
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 8002440:	687b      	ldr	r3, [r7, #4]
+ 8002442:	681b      	ldr	r3, [r3, #0]
+ 8002444:	2201      	movs	r2, #1
+ 8002446:	2104      	movs	r1, #4
+ 8002448:	4618      	mov	r0, r3
+ 800244a:	f000 fc25 	bl	8002c98 <TIM_CCxChannelCmd>
+      break;
+ 800244e:	bf00      	nop
+    }
+  }
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+ 8002450:	687b      	ldr	r3, [r7, #4]
+ 8002452:	681b      	ldr	r3, [r3, #0]
+ 8002454:	681a      	ldr	r2, [r3, #0]
+ 8002456:	687b      	ldr	r3, [r7, #4]
+ 8002458:	681b      	ldr	r3, [r3, #0]
+ 800245a:	f042 0201 	orr.w	r2, r2, #1
+ 800245e:	601a      	str	r2, [r3, #0]
+
+  /* Return function status */
   return HAL_OK;
- 8002356:	2300      	movs	r3, #0
+ 8002460:	2300      	movs	r3, #0
 }
- 8002358:	4618      	mov	r0, r3
- 800235a:	3718      	adds	r7, #24
- 800235c:	46bd      	mov	sp, r7
- 800235e:	bd80      	pop	{r7, pc}
- 8002360:	fffebff8 	.word	0xfffebff8
- 8002364:	fffffcfc 	.word	0xfffffcfc
- 8002368:	fffff3f3 	.word	0xfffff3f3
- 800236c:	ffff0f0f 	.word	0xffff0f0f
-
-08002370 <TIM_Base_SetConfig>:
+ 8002462:	4618      	mov	r0, r3
+ 8002464:	3708      	adds	r7, #8
+ 8002466:	46bd      	mov	sp, r7
+ 8002468:	bd80      	pop	{r7, pc}
+	...
+
+0800246c <HAL_TIM_PWM_ConfigChannel>:
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+                                            TIM_OC_InitTypeDef *sConfig,
+                                            uint32_t Channel)
+{
+ 800246c:	b580      	push	{r7, lr}
+ 800246e:	b084      	sub	sp, #16
+ 8002470:	af00      	add	r7, sp, #0
+ 8002472:	60f8      	str	r0, [r7, #12]
+ 8002474:	60b9      	str	r1, [r7, #8]
+ 8002476:	607a      	str	r2, [r7, #4]
+  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+ 8002478:	68fb      	ldr	r3, [r7, #12]
+ 800247a:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
+ 800247e:	2b01      	cmp	r3, #1
+ 8002480:	d101      	bne.n	8002486 <HAL_TIM_PWM_ConfigChannel+0x1a>
+ 8002482:	2302      	movs	r3, #2
+ 8002484:	e105      	b.n	8002692 <HAL_TIM_PWM_ConfigChannel+0x226>
+ 8002486:	68fb      	ldr	r3, [r7, #12]
+ 8002488:	2201      	movs	r2, #1
+ 800248a:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
+
+  htim->State = HAL_TIM_STATE_BUSY;
+ 800248e:	68fb      	ldr	r3, [r7, #12]
+ 8002490:	2202      	movs	r2, #2
+ 8002492:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+
+  switch (Channel)
+ 8002496:	687b      	ldr	r3, [r7, #4]
+ 8002498:	2b14      	cmp	r3, #20
+ 800249a:	f200 80f0 	bhi.w	800267e <HAL_TIM_PWM_ConfigChannel+0x212>
+ 800249e:	a201      	add	r2, pc, #4	; (adr r2, 80024a4 <HAL_TIM_PWM_ConfigChannel+0x38>)
+ 80024a0:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 80024a4:	080024f9 	.word	0x080024f9
+ 80024a8:	0800267f 	.word	0x0800267f
+ 80024ac:	0800267f 	.word	0x0800267f
+ 80024b0:	0800267f 	.word	0x0800267f
+ 80024b4:	08002539 	.word	0x08002539
+ 80024b8:	0800267f 	.word	0x0800267f
+ 80024bc:	0800267f 	.word	0x0800267f
+ 80024c0:	0800267f 	.word	0x0800267f
+ 80024c4:	0800257b 	.word	0x0800257b
+ 80024c8:	0800267f 	.word	0x0800267f
+ 80024cc:	0800267f 	.word	0x0800267f
+ 80024d0:	0800267f 	.word	0x0800267f
+ 80024d4:	080025bb 	.word	0x080025bb
+ 80024d8:	0800267f 	.word	0x0800267f
+ 80024dc:	0800267f 	.word	0x0800267f
+ 80024e0:	0800267f 	.word	0x0800267f
+ 80024e4:	080025fd 	.word	0x080025fd
+ 80024e8:	0800267f 	.word	0x0800267f
+ 80024ec:	0800267f 	.word	0x0800267f
+ 80024f0:	0800267f 	.word	0x0800267f
+ 80024f4:	0800263d 	.word	0x0800263d
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 1 in PWM mode */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+ 80024f8:	68fb      	ldr	r3, [r7, #12]
+ 80024fa:	681b      	ldr	r3, [r3, #0]
+ 80024fc:	68b9      	ldr	r1, [r7, #8]
+ 80024fe:	4618      	mov	r0, r3
+ 8002500:	f000 f96c 	bl	80027dc <TIM_OC1_SetConfig>
+
+      /* Set the Preload enable bit for channel1 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+ 8002504:	68fb      	ldr	r3, [r7, #12]
+ 8002506:	681b      	ldr	r3, [r3, #0]
+ 8002508:	699a      	ldr	r2, [r3, #24]
+ 800250a:	68fb      	ldr	r3, [r7, #12]
+ 800250c:	681b      	ldr	r3, [r3, #0]
+ 800250e:	f042 0208 	orr.w	r2, r2, #8
+ 8002512:	619a      	str	r2, [r3, #24]
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+ 8002514:	68fb      	ldr	r3, [r7, #12]
+ 8002516:	681b      	ldr	r3, [r3, #0]
+ 8002518:	699a      	ldr	r2, [r3, #24]
+ 800251a:	68fb      	ldr	r3, [r7, #12]
+ 800251c:	681b      	ldr	r3, [r3, #0]
+ 800251e:	f022 0204 	bic.w	r2, r2, #4
+ 8002522:	619a      	str	r2, [r3, #24]
+      htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ 8002524:	68fb      	ldr	r3, [r7, #12]
+ 8002526:	681b      	ldr	r3, [r3, #0]
+ 8002528:	6999      	ldr	r1, [r3, #24]
+ 800252a:	68bb      	ldr	r3, [r7, #8]
+ 800252c:	691a      	ldr	r2, [r3, #16]
+ 800252e:	68fb      	ldr	r3, [r7, #12]
+ 8002530:	681b      	ldr	r3, [r3, #0]
+ 8002532:	430a      	orrs	r2, r1
+ 8002534:	619a      	str	r2, [r3, #24]
+      break;
+ 8002536:	e0a3      	b.n	8002680 <HAL_TIM_PWM_ConfigChannel+0x214>
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 2 in PWM mode */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+ 8002538:	68fb      	ldr	r3, [r7, #12]
+ 800253a:	681b      	ldr	r3, [r3, #0]
+ 800253c:	68b9      	ldr	r1, [r7, #8]
+ 800253e:	4618      	mov	r0, r3
+ 8002540:	f000 f9be 	bl	80028c0 <TIM_OC2_SetConfig>
+
+      /* Set the Preload enable bit for channel2 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+ 8002544:	68fb      	ldr	r3, [r7, #12]
+ 8002546:	681b      	ldr	r3, [r3, #0]
+ 8002548:	699a      	ldr	r2, [r3, #24]
+ 800254a:	68fb      	ldr	r3, [r7, #12]
+ 800254c:	681b      	ldr	r3, [r3, #0]
+ 800254e:	f442 6200 	orr.w	r2, r2, #2048	; 0x800
+ 8002552:	619a      	str	r2, [r3, #24]
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+ 8002554:	68fb      	ldr	r3, [r7, #12]
+ 8002556:	681b      	ldr	r3, [r3, #0]
+ 8002558:	699a      	ldr	r2, [r3, #24]
+ 800255a:	68fb      	ldr	r3, [r7, #12]
+ 800255c:	681b      	ldr	r3, [r3, #0]
+ 800255e:	f422 6280 	bic.w	r2, r2, #1024	; 0x400
+ 8002562:	619a      	str	r2, [r3, #24]
+      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ 8002564:	68fb      	ldr	r3, [r7, #12]
+ 8002566:	681b      	ldr	r3, [r3, #0]
+ 8002568:	6999      	ldr	r1, [r3, #24]
+ 800256a:	68bb      	ldr	r3, [r7, #8]
+ 800256c:	691b      	ldr	r3, [r3, #16]
+ 800256e:	021a      	lsls	r2, r3, #8
+ 8002570:	68fb      	ldr	r3, [r7, #12]
+ 8002572:	681b      	ldr	r3, [r3, #0]
+ 8002574:	430a      	orrs	r2, r1
+ 8002576:	619a      	str	r2, [r3, #24]
+      break;
+ 8002578:	e082      	b.n	8002680 <HAL_TIM_PWM_ConfigChannel+0x214>
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 3 in PWM mode */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+ 800257a:	68fb      	ldr	r3, [r7, #12]
+ 800257c:	681b      	ldr	r3, [r3, #0]
+ 800257e:	68b9      	ldr	r1, [r7, #8]
+ 8002580:	4618      	mov	r0, r3
+ 8002582:	f000 fa15 	bl	80029b0 <TIM_OC3_SetConfig>
+
+      /* Set the Preload enable bit for channel3 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+ 8002586:	68fb      	ldr	r3, [r7, #12]
+ 8002588:	681b      	ldr	r3, [r3, #0]
+ 800258a:	69da      	ldr	r2, [r3, #28]
+ 800258c:	68fb      	ldr	r3, [r7, #12]
+ 800258e:	681b      	ldr	r3, [r3, #0]
+ 8002590:	f042 0208 	orr.w	r2, r2, #8
+ 8002594:	61da      	str	r2, [r3, #28]
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+ 8002596:	68fb      	ldr	r3, [r7, #12]
+ 8002598:	681b      	ldr	r3, [r3, #0]
+ 800259a:	69da      	ldr	r2, [r3, #28]
+ 800259c:	68fb      	ldr	r3, [r7, #12]
+ 800259e:	681b      	ldr	r3, [r3, #0]
+ 80025a0:	f022 0204 	bic.w	r2, r2, #4
+ 80025a4:	61da      	str	r2, [r3, #28]
+      htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ 80025a6:	68fb      	ldr	r3, [r7, #12]
+ 80025a8:	681b      	ldr	r3, [r3, #0]
+ 80025aa:	69d9      	ldr	r1, [r3, #28]
+ 80025ac:	68bb      	ldr	r3, [r7, #8]
+ 80025ae:	691a      	ldr	r2, [r3, #16]
+ 80025b0:	68fb      	ldr	r3, [r7, #12]
+ 80025b2:	681b      	ldr	r3, [r3, #0]
+ 80025b4:	430a      	orrs	r2, r1
+ 80025b6:	61da      	str	r2, [r3, #28]
+      break;
+ 80025b8:	e062      	b.n	8002680 <HAL_TIM_PWM_ConfigChannel+0x214>
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 4 in PWM mode */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+ 80025ba:	68fb      	ldr	r3, [r7, #12]
+ 80025bc:	681b      	ldr	r3, [r3, #0]
+ 80025be:	68b9      	ldr	r1, [r7, #8]
+ 80025c0:	4618      	mov	r0, r3
+ 80025c2:	f000 fa6b 	bl	8002a9c <TIM_OC4_SetConfig>
+
+      /* Set the Preload enable bit for channel4 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+ 80025c6:	68fb      	ldr	r3, [r7, #12]
+ 80025c8:	681b      	ldr	r3, [r3, #0]
+ 80025ca:	69da      	ldr	r2, [r3, #28]
+ 80025cc:	68fb      	ldr	r3, [r7, #12]
+ 80025ce:	681b      	ldr	r3, [r3, #0]
+ 80025d0:	f442 6200 	orr.w	r2, r2, #2048	; 0x800
+ 80025d4:	61da      	str	r2, [r3, #28]
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+ 80025d6:	68fb      	ldr	r3, [r7, #12]
+ 80025d8:	681b      	ldr	r3, [r3, #0]
+ 80025da:	69da      	ldr	r2, [r3, #28]
+ 80025dc:	68fb      	ldr	r3, [r7, #12]
+ 80025de:	681b      	ldr	r3, [r3, #0]
+ 80025e0:	f422 6280 	bic.w	r2, r2, #1024	; 0x400
+ 80025e4:	61da      	str	r2, [r3, #28]
+      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ 80025e6:	68fb      	ldr	r3, [r7, #12]
+ 80025e8:	681b      	ldr	r3, [r3, #0]
+ 80025ea:	69d9      	ldr	r1, [r3, #28]
+ 80025ec:	68bb      	ldr	r3, [r7, #8]
+ 80025ee:	691b      	ldr	r3, [r3, #16]
+ 80025f0:	021a      	lsls	r2, r3, #8
+ 80025f2:	68fb      	ldr	r3, [r7, #12]
+ 80025f4:	681b      	ldr	r3, [r3, #0]
+ 80025f6:	430a      	orrs	r2, r1
+ 80025f8:	61da      	str	r2, [r3, #28]
+      break;
+ 80025fa:	e041      	b.n	8002680 <HAL_TIM_PWM_ConfigChannel+0x214>
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 5 in PWM mode */
+      TIM_OC5_SetConfig(htim->Instance, sConfig);
+ 80025fc:	68fb      	ldr	r3, [r7, #12]
+ 80025fe:	681b      	ldr	r3, [r3, #0]
+ 8002600:	68b9      	ldr	r1, [r7, #8]
+ 8002602:	4618      	mov	r0, r3
+ 8002604:	f000 faa2 	bl	8002b4c <TIM_OC5_SetConfig>
+
+      /* Set the Preload enable bit for channel5*/
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+ 8002608:	68fb      	ldr	r3, [r7, #12]
+ 800260a:	681b      	ldr	r3, [r3, #0]
+ 800260c:	6d5a      	ldr	r2, [r3, #84]	; 0x54
+ 800260e:	68fb      	ldr	r3, [r7, #12]
+ 8002610:	681b      	ldr	r3, [r3, #0]
+ 8002612:	f042 0208 	orr.w	r2, r2, #8
+ 8002616:	655a      	str	r2, [r3, #84]	; 0x54
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+ 8002618:	68fb      	ldr	r3, [r7, #12]
+ 800261a:	681b      	ldr	r3, [r3, #0]
+ 800261c:	6d5a      	ldr	r2, [r3, #84]	; 0x54
+ 800261e:	68fb      	ldr	r3, [r7, #12]
+ 8002620:	681b      	ldr	r3, [r3, #0]
+ 8002622:	f022 0204 	bic.w	r2, r2, #4
+ 8002626:	655a      	str	r2, [r3, #84]	; 0x54
+      htim->Instance->CCMR3 |= sConfig->OCFastMode;
+ 8002628:	68fb      	ldr	r3, [r7, #12]
+ 800262a:	681b      	ldr	r3, [r3, #0]
+ 800262c:	6d59      	ldr	r1, [r3, #84]	; 0x54
+ 800262e:	68bb      	ldr	r3, [r7, #8]
+ 8002630:	691a      	ldr	r2, [r3, #16]
+ 8002632:	68fb      	ldr	r3, [r7, #12]
+ 8002634:	681b      	ldr	r3, [r3, #0]
+ 8002636:	430a      	orrs	r2, r1
+ 8002638:	655a      	str	r2, [r3, #84]	; 0x54
+      break;
+ 800263a:	e021      	b.n	8002680 <HAL_TIM_PWM_ConfigChannel+0x214>
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 6 in PWM mode */
+      TIM_OC6_SetConfig(htim->Instance, sConfig);
+ 800263c:	68fb      	ldr	r3, [r7, #12]
+ 800263e:	681b      	ldr	r3, [r3, #0]
+ 8002640:	68b9      	ldr	r1, [r7, #8]
+ 8002642:	4618      	mov	r0, r3
+ 8002644:	f000 fad4 	bl	8002bf0 <TIM_OC6_SetConfig>
+
+      /* Set the Preload enable bit for channel6 */
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+ 8002648:	68fb      	ldr	r3, [r7, #12]
+ 800264a:	681b      	ldr	r3, [r3, #0]
+ 800264c:	6d5a      	ldr	r2, [r3, #84]	; 0x54
+ 800264e:	68fb      	ldr	r3, [r7, #12]
+ 8002650:	681b      	ldr	r3, [r3, #0]
+ 8002652:	f442 6200 	orr.w	r2, r2, #2048	; 0x800
+ 8002656:	655a      	str	r2, [r3, #84]	; 0x54
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+ 8002658:	68fb      	ldr	r3, [r7, #12]
+ 800265a:	681b      	ldr	r3, [r3, #0]
+ 800265c:	6d5a      	ldr	r2, [r3, #84]	; 0x54
+ 800265e:	68fb      	ldr	r3, [r7, #12]
+ 8002660:	681b      	ldr	r3, [r3, #0]
+ 8002662:	f422 6280 	bic.w	r2, r2, #1024	; 0x400
+ 8002666:	655a      	str	r2, [r3, #84]	; 0x54
+      htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+ 8002668:	68fb      	ldr	r3, [r7, #12]
+ 800266a:	681b      	ldr	r3, [r3, #0]
+ 800266c:	6d59      	ldr	r1, [r3, #84]	; 0x54
+ 800266e:	68bb      	ldr	r3, [r7, #8]
+ 8002670:	691b      	ldr	r3, [r3, #16]
+ 8002672:	021a      	lsls	r2, r3, #8
+ 8002674:	68fb      	ldr	r3, [r7, #12]
+ 8002676:	681b      	ldr	r3, [r3, #0]
+ 8002678:	430a      	orrs	r2, r1
+ 800267a:	655a      	str	r2, [r3, #84]	; 0x54
+      break;
+ 800267c:	e000      	b.n	8002680 <HAL_TIM_PWM_ConfigChannel+0x214>
+    }
+
+    default:
+      break;
+ 800267e:	bf00      	nop
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+ 8002680:	68fb      	ldr	r3, [r7, #12]
+ 8002682:	2201      	movs	r2, #1
+ 8002684:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+
+  __HAL_UNLOCK(htim);
+ 8002688:	68fb      	ldr	r3, [r7, #12]
+ 800268a:	2200      	movs	r2, #0
+ 800268c:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
+
+  return HAL_OK;
+ 8002690:	2300      	movs	r3, #0
+}
+ 8002692:	4618      	mov	r0, r3
+ 8002694:	3710      	adds	r7, #16
+ 8002696:	46bd      	mov	sp, r7
+ 8002698:	bd80      	pop	{r7, pc}
+ 800269a:	bf00      	nop
+
+0800269c <TIM_Base_SetConfig>:
   * @param  TIMx TIM peripheral
   * @param  Structure TIM Base configuration structure
   * @retval None
   */
 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
 {
- 8002370:	b480      	push	{r7}
- 8002372:	b085      	sub	sp, #20
- 8002374:	af00      	add	r7, sp, #0
- 8002376:	6078      	str	r0, [r7, #4]
- 8002378:	6039      	str	r1, [r7, #0]
+ 800269c:	b480      	push	{r7}
+ 800269e:	b085      	sub	sp, #20
+ 80026a0:	af00      	add	r7, sp, #0
+ 80026a2:	6078      	str	r0, [r7, #4]
+ 80026a4:	6039      	str	r1, [r7, #0]
   uint32_t tmpcr1;
   tmpcr1 = TIMx->CR1;
- 800237a:	687b      	ldr	r3, [r7, #4]
- 800237c:	681b      	ldr	r3, [r3, #0]
- 800237e:	60fb      	str	r3, [r7, #12]
+ 80026a6:	687b      	ldr	r3, [r7, #4]
+ 80026a8:	681b      	ldr	r3, [r3, #0]
+ 80026aa:	60fb      	str	r3, [r7, #12]
 
   /* Set TIM Time Base Unit parameters ---------------------------------------*/
   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- 8002380:	687b      	ldr	r3, [r7, #4]
- 8002382:	4a40      	ldr	r2, [pc, #256]	; (8002484 <TIM_Base_SetConfig+0x114>)
- 8002384:	4293      	cmp	r3, r2
- 8002386:	d013      	beq.n	80023b0 <TIM_Base_SetConfig+0x40>
- 8002388:	687b      	ldr	r3, [r7, #4]
- 800238a:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
- 800238e:	d00f      	beq.n	80023b0 <TIM_Base_SetConfig+0x40>
- 8002390:	687b      	ldr	r3, [r7, #4]
- 8002392:	4a3d      	ldr	r2, [pc, #244]	; (8002488 <TIM_Base_SetConfig+0x118>)
- 8002394:	4293      	cmp	r3, r2
- 8002396:	d00b      	beq.n	80023b0 <TIM_Base_SetConfig+0x40>
- 8002398:	687b      	ldr	r3, [r7, #4]
- 800239a:	4a3c      	ldr	r2, [pc, #240]	; (800248c <TIM_Base_SetConfig+0x11c>)
- 800239c:	4293      	cmp	r3, r2
- 800239e:	d007      	beq.n	80023b0 <TIM_Base_SetConfig+0x40>
- 80023a0:	687b      	ldr	r3, [r7, #4]
- 80023a2:	4a3b      	ldr	r2, [pc, #236]	; (8002490 <TIM_Base_SetConfig+0x120>)
- 80023a4:	4293      	cmp	r3, r2
- 80023a6:	d003      	beq.n	80023b0 <TIM_Base_SetConfig+0x40>
- 80023a8:	687b      	ldr	r3, [r7, #4]
- 80023aa:	4a3a      	ldr	r2, [pc, #232]	; (8002494 <TIM_Base_SetConfig+0x124>)
- 80023ac:	4293      	cmp	r3, r2
- 80023ae:	d108      	bne.n	80023c2 <TIM_Base_SetConfig+0x52>
+ 80026ac:	687b      	ldr	r3, [r7, #4]
+ 80026ae:	4a40      	ldr	r2, [pc, #256]	; (80027b0 <TIM_Base_SetConfig+0x114>)
+ 80026b0:	4293      	cmp	r3, r2
+ 80026b2:	d013      	beq.n	80026dc <TIM_Base_SetConfig+0x40>
+ 80026b4:	687b      	ldr	r3, [r7, #4]
+ 80026b6:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
+ 80026ba:	d00f      	beq.n	80026dc <TIM_Base_SetConfig+0x40>
+ 80026bc:	687b      	ldr	r3, [r7, #4]
+ 80026be:	4a3d      	ldr	r2, [pc, #244]	; (80027b4 <TIM_Base_SetConfig+0x118>)
+ 80026c0:	4293      	cmp	r3, r2
+ 80026c2:	d00b      	beq.n	80026dc <TIM_Base_SetConfig+0x40>
+ 80026c4:	687b      	ldr	r3, [r7, #4]
+ 80026c6:	4a3c      	ldr	r2, [pc, #240]	; (80027b8 <TIM_Base_SetConfig+0x11c>)
+ 80026c8:	4293      	cmp	r3, r2
+ 80026ca:	d007      	beq.n	80026dc <TIM_Base_SetConfig+0x40>
+ 80026cc:	687b      	ldr	r3, [r7, #4]
+ 80026ce:	4a3b      	ldr	r2, [pc, #236]	; (80027bc <TIM_Base_SetConfig+0x120>)
+ 80026d0:	4293      	cmp	r3, r2
+ 80026d2:	d003      	beq.n	80026dc <TIM_Base_SetConfig+0x40>
+ 80026d4:	687b      	ldr	r3, [r7, #4]
+ 80026d6:	4a3a      	ldr	r2, [pc, #232]	; (80027c0 <TIM_Base_SetConfig+0x124>)
+ 80026d8:	4293      	cmp	r3, r2
+ 80026da:	d108      	bne.n	80026ee <TIM_Base_SetConfig+0x52>
   {
     /* Select the Counter Mode */
     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
- 80023b0:	68fb      	ldr	r3, [r7, #12]
- 80023b2:	f023 0370 	bic.w	r3, r3, #112	; 0x70
- 80023b6:	60fb      	str	r3, [r7, #12]
+ 80026dc:	68fb      	ldr	r3, [r7, #12]
+ 80026de:	f023 0370 	bic.w	r3, r3, #112	; 0x70
+ 80026e2:	60fb      	str	r3, [r7, #12]
     tmpcr1 |= Structure->CounterMode;
- 80023b8:	683b      	ldr	r3, [r7, #0]
- 80023ba:	685b      	ldr	r3, [r3, #4]
- 80023bc:	68fa      	ldr	r2, [r7, #12]
- 80023be:	4313      	orrs	r3, r2
- 80023c0:	60fb      	str	r3, [r7, #12]
+ 80026e4:	683b      	ldr	r3, [r7, #0]
+ 80026e6:	685b      	ldr	r3, [r3, #4]
+ 80026e8:	68fa      	ldr	r2, [r7, #12]
+ 80026ea:	4313      	orrs	r3, r2
+ 80026ec:	60fb      	str	r3, [r7, #12]
   }
 
   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- 80023c2:	687b      	ldr	r3, [r7, #4]
- 80023c4:	4a2f      	ldr	r2, [pc, #188]	; (8002484 <TIM_Base_SetConfig+0x114>)
- 80023c6:	4293      	cmp	r3, r2
- 80023c8:	d02b      	beq.n	8002422 <TIM_Base_SetConfig+0xb2>
- 80023ca:	687b      	ldr	r3, [r7, #4]
- 80023cc:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
- 80023d0:	d027      	beq.n	8002422 <TIM_Base_SetConfig+0xb2>
- 80023d2:	687b      	ldr	r3, [r7, #4]
- 80023d4:	4a2c      	ldr	r2, [pc, #176]	; (8002488 <TIM_Base_SetConfig+0x118>)
- 80023d6:	4293      	cmp	r3, r2
- 80023d8:	d023      	beq.n	8002422 <TIM_Base_SetConfig+0xb2>
- 80023da:	687b      	ldr	r3, [r7, #4]
- 80023dc:	4a2b      	ldr	r2, [pc, #172]	; (800248c <TIM_Base_SetConfig+0x11c>)
- 80023de:	4293      	cmp	r3, r2
- 80023e0:	d01f      	beq.n	8002422 <TIM_Base_SetConfig+0xb2>
- 80023e2:	687b      	ldr	r3, [r7, #4]
- 80023e4:	4a2a      	ldr	r2, [pc, #168]	; (8002490 <TIM_Base_SetConfig+0x120>)
- 80023e6:	4293      	cmp	r3, r2
- 80023e8:	d01b      	beq.n	8002422 <TIM_Base_SetConfig+0xb2>
- 80023ea:	687b      	ldr	r3, [r7, #4]
- 80023ec:	4a29      	ldr	r2, [pc, #164]	; (8002494 <TIM_Base_SetConfig+0x124>)
- 80023ee:	4293      	cmp	r3, r2
- 80023f0:	d017      	beq.n	8002422 <TIM_Base_SetConfig+0xb2>
- 80023f2:	687b      	ldr	r3, [r7, #4]
- 80023f4:	4a28      	ldr	r2, [pc, #160]	; (8002498 <TIM_Base_SetConfig+0x128>)
- 80023f6:	4293      	cmp	r3, r2
- 80023f8:	d013      	beq.n	8002422 <TIM_Base_SetConfig+0xb2>
- 80023fa:	687b      	ldr	r3, [r7, #4]
- 80023fc:	4a27      	ldr	r2, [pc, #156]	; (800249c <TIM_Base_SetConfig+0x12c>)
- 80023fe:	4293      	cmp	r3, r2
- 8002400:	d00f      	beq.n	8002422 <TIM_Base_SetConfig+0xb2>
- 8002402:	687b      	ldr	r3, [r7, #4]
- 8002404:	4a26      	ldr	r2, [pc, #152]	; (80024a0 <TIM_Base_SetConfig+0x130>)
- 8002406:	4293      	cmp	r3, r2
- 8002408:	d00b      	beq.n	8002422 <TIM_Base_SetConfig+0xb2>
- 800240a:	687b      	ldr	r3, [r7, #4]
- 800240c:	4a25      	ldr	r2, [pc, #148]	; (80024a4 <TIM_Base_SetConfig+0x134>)
- 800240e:	4293      	cmp	r3, r2
- 8002410:	d007      	beq.n	8002422 <TIM_Base_SetConfig+0xb2>
- 8002412:	687b      	ldr	r3, [r7, #4]
- 8002414:	4a24      	ldr	r2, [pc, #144]	; (80024a8 <TIM_Base_SetConfig+0x138>)
- 8002416:	4293      	cmp	r3, r2
- 8002418:	d003      	beq.n	8002422 <TIM_Base_SetConfig+0xb2>
- 800241a:	687b      	ldr	r3, [r7, #4]
- 800241c:	4a23      	ldr	r2, [pc, #140]	; (80024ac <TIM_Base_SetConfig+0x13c>)
- 800241e:	4293      	cmp	r3, r2
- 8002420:	d108      	bne.n	8002434 <TIM_Base_SetConfig+0xc4>
+ 80026ee:	687b      	ldr	r3, [r7, #4]
+ 80026f0:	4a2f      	ldr	r2, [pc, #188]	; (80027b0 <TIM_Base_SetConfig+0x114>)
+ 80026f2:	4293      	cmp	r3, r2
+ 80026f4:	d02b      	beq.n	800274e <TIM_Base_SetConfig+0xb2>
+ 80026f6:	687b      	ldr	r3, [r7, #4]
+ 80026f8:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
+ 80026fc:	d027      	beq.n	800274e <TIM_Base_SetConfig+0xb2>
+ 80026fe:	687b      	ldr	r3, [r7, #4]
+ 8002700:	4a2c      	ldr	r2, [pc, #176]	; (80027b4 <TIM_Base_SetConfig+0x118>)
+ 8002702:	4293      	cmp	r3, r2
+ 8002704:	d023      	beq.n	800274e <TIM_Base_SetConfig+0xb2>
+ 8002706:	687b      	ldr	r3, [r7, #4]
+ 8002708:	4a2b      	ldr	r2, [pc, #172]	; (80027b8 <TIM_Base_SetConfig+0x11c>)
+ 800270a:	4293      	cmp	r3, r2
+ 800270c:	d01f      	beq.n	800274e <TIM_Base_SetConfig+0xb2>
+ 800270e:	687b      	ldr	r3, [r7, #4]
+ 8002710:	4a2a      	ldr	r2, [pc, #168]	; (80027bc <TIM_Base_SetConfig+0x120>)
+ 8002712:	4293      	cmp	r3, r2
+ 8002714:	d01b      	beq.n	800274e <TIM_Base_SetConfig+0xb2>
+ 8002716:	687b      	ldr	r3, [r7, #4]
+ 8002718:	4a29      	ldr	r2, [pc, #164]	; (80027c0 <TIM_Base_SetConfig+0x124>)
+ 800271a:	4293      	cmp	r3, r2
+ 800271c:	d017      	beq.n	800274e <TIM_Base_SetConfig+0xb2>
+ 800271e:	687b      	ldr	r3, [r7, #4]
+ 8002720:	4a28      	ldr	r2, [pc, #160]	; (80027c4 <TIM_Base_SetConfig+0x128>)
+ 8002722:	4293      	cmp	r3, r2
+ 8002724:	d013      	beq.n	800274e <TIM_Base_SetConfig+0xb2>
+ 8002726:	687b      	ldr	r3, [r7, #4]
+ 8002728:	4a27      	ldr	r2, [pc, #156]	; (80027c8 <TIM_Base_SetConfig+0x12c>)
+ 800272a:	4293      	cmp	r3, r2
+ 800272c:	d00f      	beq.n	800274e <TIM_Base_SetConfig+0xb2>
+ 800272e:	687b      	ldr	r3, [r7, #4]
+ 8002730:	4a26      	ldr	r2, [pc, #152]	; (80027cc <TIM_Base_SetConfig+0x130>)
+ 8002732:	4293      	cmp	r3, r2
+ 8002734:	d00b      	beq.n	800274e <TIM_Base_SetConfig+0xb2>
+ 8002736:	687b      	ldr	r3, [r7, #4]
+ 8002738:	4a25      	ldr	r2, [pc, #148]	; (80027d0 <TIM_Base_SetConfig+0x134>)
+ 800273a:	4293      	cmp	r3, r2
+ 800273c:	d007      	beq.n	800274e <TIM_Base_SetConfig+0xb2>
+ 800273e:	687b      	ldr	r3, [r7, #4]
+ 8002740:	4a24      	ldr	r2, [pc, #144]	; (80027d4 <TIM_Base_SetConfig+0x138>)
+ 8002742:	4293      	cmp	r3, r2
+ 8002744:	d003      	beq.n	800274e <TIM_Base_SetConfig+0xb2>
+ 8002746:	687b      	ldr	r3, [r7, #4]
+ 8002748:	4a23      	ldr	r2, [pc, #140]	; (80027d8 <TIM_Base_SetConfig+0x13c>)
+ 800274a:	4293      	cmp	r3, r2
+ 800274c:	d108      	bne.n	8002760 <TIM_Base_SetConfig+0xc4>
   {
     /* Set the clock division */
     tmpcr1 &= ~TIM_CR1_CKD;
- 8002422:	68fb      	ldr	r3, [r7, #12]
- 8002424:	f423 7340 	bic.w	r3, r3, #768	; 0x300
- 8002428:	60fb      	str	r3, [r7, #12]
+ 800274e:	68fb      	ldr	r3, [r7, #12]
+ 8002750:	f423 7340 	bic.w	r3, r3, #768	; 0x300
+ 8002754:	60fb      	str	r3, [r7, #12]
     tmpcr1 |= (uint32_t)Structure->ClockDivision;
- 800242a:	683b      	ldr	r3, [r7, #0]
- 800242c:	68db      	ldr	r3, [r3, #12]
- 800242e:	68fa      	ldr	r2, [r7, #12]
- 8002430:	4313      	orrs	r3, r2
- 8002432:	60fb      	str	r3, [r7, #12]
+ 8002756:	683b      	ldr	r3, [r7, #0]
+ 8002758:	68db      	ldr	r3, [r3, #12]
+ 800275a:	68fa      	ldr	r2, [r7, #12]
+ 800275c:	4313      	orrs	r3, r2
+ 800275e:	60fb      	str	r3, [r7, #12]
   }
 
   /* Set the auto-reload preload */
   MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
- 8002434:	68fb      	ldr	r3, [r7, #12]
- 8002436:	f023 0280 	bic.w	r2, r3, #128	; 0x80
- 800243a:	683b      	ldr	r3, [r7, #0]
- 800243c:	695b      	ldr	r3, [r3, #20]
- 800243e:	4313      	orrs	r3, r2
- 8002440:	60fb      	str	r3, [r7, #12]
+ 8002760:	68fb      	ldr	r3, [r7, #12]
+ 8002762:	f023 0280 	bic.w	r2, r3, #128	; 0x80
+ 8002766:	683b      	ldr	r3, [r7, #0]
+ 8002768:	695b      	ldr	r3, [r3, #20]
+ 800276a:	4313      	orrs	r3, r2
+ 800276c:	60fb      	str	r3, [r7, #12]
 
   TIMx->CR1 = tmpcr1;
- 8002442:	687b      	ldr	r3, [r7, #4]
- 8002444:	68fa      	ldr	r2, [r7, #12]
- 8002446:	601a      	str	r2, [r3, #0]
+ 800276e:	687b      	ldr	r3, [r7, #4]
+ 8002770:	68fa      	ldr	r2, [r7, #12]
+ 8002772:	601a      	str	r2, [r3, #0]
 
   /* Set the Autoreload value */
   TIMx->ARR = (uint32_t)Structure->Period ;
- 8002448:	683b      	ldr	r3, [r7, #0]
- 800244a:	689a      	ldr	r2, [r3, #8]
- 800244c:	687b      	ldr	r3, [r7, #4]
- 800244e:	62da      	str	r2, [r3, #44]	; 0x2c
+ 8002774:	683b      	ldr	r3, [r7, #0]
+ 8002776:	689a      	ldr	r2, [r3, #8]
+ 8002778:	687b      	ldr	r3, [r7, #4]
+ 800277a:	62da      	str	r2, [r3, #44]	; 0x2c
 
   /* Set the Prescaler value */
   TIMx->PSC = Structure->Prescaler;
- 8002450:	683b      	ldr	r3, [r7, #0]
- 8002452:	681a      	ldr	r2, [r3, #0]
- 8002454:	687b      	ldr	r3, [r7, #4]
- 8002456:	629a      	str	r2, [r3, #40]	; 0x28
+ 800277c:	683b      	ldr	r3, [r7, #0]
+ 800277e:	681a      	ldr	r2, [r3, #0]
+ 8002780:	687b      	ldr	r3, [r7, #4]
+ 8002782:	629a      	str	r2, [r3, #40]	; 0x28
 
   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
- 8002458:	687b      	ldr	r3, [r7, #4]
- 800245a:	4a0a      	ldr	r2, [pc, #40]	; (8002484 <TIM_Base_SetConfig+0x114>)
- 800245c:	4293      	cmp	r3, r2
- 800245e:	d003      	beq.n	8002468 <TIM_Base_SetConfig+0xf8>
- 8002460:	687b      	ldr	r3, [r7, #4]
- 8002462:	4a0c      	ldr	r2, [pc, #48]	; (8002494 <TIM_Base_SetConfig+0x124>)
- 8002464:	4293      	cmp	r3, r2
- 8002466:	d103      	bne.n	8002470 <TIM_Base_SetConfig+0x100>
+ 8002784:	687b      	ldr	r3, [r7, #4]
+ 8002786:	4a0a      	ldr	r2, [pc, #40]	; (80027b0 <TIM_Base_SetConfig+0x114>)
+ 8002788:	4293      	cmp	r3, r2
+ 800278a:	d003      	beq.n	8002794 <TIM_Base_SetConfig+0xf8>
+ 800278c:	687b      	ldr	r3, [r7, #4]
+ 800278e:	4a0c      	ldr	r2, [pc, #48]	; (80027c0 <TIM_Base_SetConfig+0x124>)
+ 8002790:	4293      	cmp	r3, r2
+ 8002792:	d103      	bne.n	800279c <TIM_Base_SetConfig+0x100>
   {
     /* Set the Repetition Counter value */
     TIMx->RCR = Structure->RepetitionCounter;
- 8002468:	683b      	ldr	r3, [r7, #0]
- 800246a:	691a      	ldr	r2, [r3, #16]
- 800246c:	687b      	ldr	r3, [r7, #4]
- 800246e:	631a      	str	r2, [r3, #48]	; 0x30
+ 8002794:	683b      	ldr	r3, [r7, #0]
+ 8002796:	691a      	ldr	r2, [r3, #16]
+ 8002798:	687b      	ldr	r3, [r7, #4]
+ 800279a:	631a      	str	r2, [r3, #48]	; 0x30
   }
 
   /* Generate an update event to reload the Prescaler
      and the repetition counter (only for advanced timer) value immediately */
   TIMx->EGR = TIM_EGR_UG;
- 8002470:	687b      	ldr	r3, [r7, #4]
- 8002472:	2201      	movs	r2, #1
- 8002474:	615a      	str	r2, [r3, #20]
+ 800279c:	687b      	ldr	r3, [r7, #4]
+ 800279e:	2201      	movs	r2, #1
+ 80027a0:	615a      	str	r2, [r3, #20]
+}
+ 80027a2:	bf00      	nop
+ 80027a4:	3714      	adds	r7, #20
+ 80027a6:	46bd      	mov	sp, r7
+ 80027a8:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80027ac:	4770      	bx	lr
+ 80027ae:	bf00      	nop
+ 80027b0:	40010000 	.word	0x40010000
+ 80027b4:	40000400 	.word	0x40000400
+ 80027b8:	40000800 	.word	0x40000800
+ 80027bc:	40000c00 	.word	0x40000c00
+ 80027c0:	40010400 	.word	0x40010400
+ 80027c4:	40014000 	.word	0x40014000
+ 80027c8:	40014400 	.word	0x40014400
+ 80027cc:	40014800 	.word	0x40014800
+ 80027d0:	40001800 	.word	0x40001800
+ 80027d4:	40001c00 	.word	0x40001c00
+ 80027d8:	40002000 	.word	0x40002000
+
+080027dc <TIM_OC1_SetConfig>:
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ 80027dc:	b480      	push	{r7}
+ 80027de:	b087      	sub	sp, #28
+ 80027e0:	af00      	add	r7, sp, #0
+ 80027e2:	6078      	str	r0, [r7, #4]
+ 80027e4:	6039      	str	r1, [r7, #0]
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+ 80027e6:	687b      	ldr	r3, [r7, #4]
+ 80027e8:	6a1b      	ldr	r3, [r3, #32]
+ 80027ea:	f023 0201 	bic.w	r2, r3, #1
+ 80027ee:	687b      	ldr	r3, [r7, #4]
+ 80027f0:	621a      	str	r2, [r3, #32]
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+ 80027f2:	687b      	ldr	r3, [r7, #4]
+ 80027f4:	6a1b      	ldr	r3, [r3, #32]
+ 80027f6:	617b      	str	r3, [r7, #20]
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+ 80027f8:	687b      	ldr	r3, [r7, #4]
+ 80027fa:	685b      	ldr	r3, [r3, #4]
+ 80027fc:	613b      	str	r3, [r7, #16]
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+ 80027fe:	687b      	ldr	r3, [r7, #4]
+ 8002800:	699b      	ldr	r3, [r3, #24]
+ 8002802:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC1M;
+ 8002804:	68fa      	ldr	r2, [r7, #12]
+ 8002806:	4b2b      	ldr	r3, [pc, #172]	; (80028b4 <TIM_OC1_SetConfig+0xd8>)
+ 8002808:	4013      	ands	r3, r2
+ 800280a:	60fb      	str	r3, [r7, #12]
+  tmpccmrx &= ~TIM_CCMR1_CC1S;
+ 800280c:	68fb      	ldr	r3, [r7, #12]
+ 800280e:	f023 0303 	bic.w	r3, r3, #3
+ 8002812:	60fb      	str	r3, [r7, #12]
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+ 8002814:	683b      	ldr	r3, [r7, #0]
+ 8002816:	681b      	ldr	r3, [r3, #0]
+ 8002818:	68fa      	ldr	r2, [r7, #12]
+ 800281a:	4313      	orrs	r3, r2
+ 800281c:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC1P;
+ 800281e:	697b      	ldr	r3, [r7, #20]
+ 8002820:	f023 0302 	bic.w	r3, r3, #2
+ 8002824:	617b      	str	r3, [r7, #20]
+  /* Set the Output Compare Polarity */
+  tmpccer |= OC_Config->OCPolarity;
+ 8002826:	683b      	ldr	r3, [r7, #0]
+ 8002828:	689b      	ldr	r3, [r3, #8]
+ 800282a:	697a      	ldr	r2, [r7, #20]
+ 800282c:	4313      	orrs	r3, r2
+ 800282e:	617b      	str	r3, [r7, #20]
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+ 8002830:	687b      	ldr	r3, [r7, #4]
+ 8002832:	4a21      	ldr	r2, [pc, #132]	; (80028b8 <TIM_OC1_SetConfig+0xdc>)
+ 8002834:	4293      	cmp	r3, r2
+ 8002836:	d003      	beq.n	8002840 <TIM_OC1_SetConfig+0x64>
+ 8002838:	687b      	ldr	r3, [r7, #4]
+ 800283a:	4a20      	ldr	r2, [pc, #128]	; (80028bc <TIM_OC1_SetConfig+0xe0>)
+ 800283c:	4293      	cmp	r3, r2
+ 800283e:	d10c      	bne.n	800285a <TIM_OC1_SetConfig+0x7e>
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC1NP;
+ 8002840:	697b      	ldr	r3, [r7, #20]
+ 8002842:	f023 0308 	bic.w	r3, r3, #8
+ 8002846:	617b      	str	r3, [r7, #20]
+    /* Set the Output N Polarity */
+    tmpccer |= OC_Config->OCNPolarity;
+ 8002848:	683b      	ldr	r3, [r7, #0]
+ 800284a:	68db      	ldr	r3, [r3, #12]
+ 800284c:	697a      	ldr	r2, [r7, #20]
+ 800284e:	4313      	orrs	r3, r2
+ 8002850:	617b      	str	r3, [r7, #20]
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC1NE;
+ 8002852:	697b      	ldr	r3, [r7, #20]
+ 8002854:	f023 0304 	bic.w	r3, r3, #4
+ 8002858:	617b      	str	r3, [r7, #20]
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 800285a:	687b      	ldr	r3, [r7, #4]
+ 800285c:	4a16      	ldr	r2, [pc, #88]	; (80028b8 <TIM_OC1_SetConfig+0xdc>)
+ 800285e:	4293      	cmp	r3, r2
+ 8002860:	d003      	beq.n	800286a <TIM_OC1_SetConfig+0x8e>
+ 8002862:	687b      	ldr	r3, [r7, #4]
+ 8002864:	4a15      	ldr	r2, [pc, #84]	; (80028bc <TIM_OC1_SetConfig+0xe0>)
+ 8002866:	4293      	cmp	r3, r2
+ 8002868:	d111      	bne.n	800288e <TIM_OC1_SetConfig+0xb2>
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS1;
+ 800286a:	693b      	ldr	r3, [r7, #16]
+ 800286c:	f423 7380 	bic.w	r3, r3, #256	; 0x100
+ 8002870:	613b      	str	r3, [r7, #16]
+    tmpcr2 &= ~TIM_CR2_OIS1N;
+ 8002872:	693b      	ldr	r3, [r7, #16]
+ 8002874:	f423 7300 	bic.w	r3, r3, #512	; 0x200
+ 8002878:	613b      	str	r3, [r7, #16]
+    /* Set the Output Idle state */
+    tmpcr2 |= OC_Config->OCIdleState;
+ 800287a:	683b      	ldr	r3, [r7, #0]
+ 800287c:	695b      	ldr	r3, [r3, #20]
+ 800287e:	693a      	ldr	r2, [r7, #16]
+ 8002880:	4313      	orrs	r3, r2
+ 8002882:	613b      	str	r3, [r7, #16]
+    /* Set the Output N Idle state */
+    tmpcr2 |= OC_Config->OCNIdleState;
+ 8002884:	683b      	ldr	r3, [r7, #0]
+ 8002886:	699b      	ldr	r3, [r3, #24]
+ 8002888:	693a      	ldr	r2, [r7, #16]
+ 800288a:	4313      	orrs	r3, r2
+ 800288c:	613b      	str	r3, [r7, #16]
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+ 800288e:	687b      	ldr	r3, [r7, #4]
+ 8002890:	693a      	ldr	r2, [r7, #16]
+ 8002892:	605a      	str	r2, [r3, #4]
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+ 8002894:	687b      	ldr	r3, [r7, #4]
+ 8002896:	68fa      	ldr	r2, [r7, #12]
+ 8002898:	619a      	str	r2, [r3, #24]
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = OC_Config->Pulse;
+ 800289a:	683b      	ldr	r3, [r7, #0]
+ 800289c:	685a      	ldr	r2, [r3, #4]
+ 800289e:	687b      	ldr	r3, [r7, #4]
+ 80028a0:	635a      	str	r2, [r3, #52]	; 0x34
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+ 80028a2:	687b      	ldr	r3, [r7, #4]
+ 80028a4:	697a      	ldr	r2, [r7, #20]
+ 80028a6:	621a      	str	r2, [r3, #32]
+}
+ 80028a8:	bf00      	nop
+ 80028aa:	371c      	adds	r7, #28
+ 80028ac:	46bd      	mov	sp, r7
+ 80028ae:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80028b2:	4770      	bx	lr
+ 80028b4:	fffeff8f 	.word	0xfffeff8f
+ 80028b8:	40010000 	.word	0x40010000
+ 80028bc:	40010400 	.word	0x40010400
+
+080028c0 <TIM_OC2_SetConfig>:
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ 80028c0:	b480      	push	{r7}
+ 80028c2:	b087      	sub	sp, #28
+ 80028c4:	af00      	add	r7, sp, #0
+ 80028c6:	6078      	str	r0, [r7, #4]
+ 80028c8:	6039      	str	r1, [r7, #0]
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+ 80028ca:	687b      	ldr	r3, [r7, #4]
+ 80028cc:	6a1b      	ldr	r3, [r3, #32]
+ 80028ce:	f023 0210 	bic.w	r2, r3, #16
+ 80028d2:	687b      	ldr	r3, [r7, #4]
+ 80028d4:	621a      	str	r2, [r3, #32]
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+ 80028d6:	687b      	ldr	r3, [r7, #4]
+ 80028d8:	6a1b      	ldr	r3, [r3, #32]
+ 80028da:	617b      	str	r3, [r7, #20]
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+ 80028dc:	687b      	ldr	r3, [r7, #4]
+ 80028de:	685b      	ldr	r3, [r3, #4]
+ 80028e0:	613b      	str	r3, [r7, #16]
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+ 80028e2:	687b      	ldr	r3, [r7, #4]
+ 80028e4:	699b      	ldr	r3, [r3, #24]
+ 80028e6:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC2M;
+ 80028e8:	68fa      	ldr	r2, [r7, #12]
+ 80028ea:	4b2e      	ldr	r3, [pc, #184]	; (80029a4 <TIM_OC2_SetConfig+0xe4>)
+ 80028ec:	4013      	ands	r3, r2
+ 80028ee:	60fb      	str	r3, [r7, #12]
+  tmpccmrx &= ~TIM_CCMR1_CC2S;
+ 80028f0:	68fb      	ldr	r3, [r7, #12]
+ 80028f2:	f423 7340 	bic.w	r3, r3, #768	; 0x300
+ 80028f6:	60fb      	str	r3, [r7, #12]
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+ 80028f8:	683b      	ldr	r3, [r7, #0]
+ 80028fa:	681b      	ldr	r3, [r3, #0]
+ 80028fc:	021b      	lsls	r3, r3, #8
+ 80028fe:	68fa      	ldr	r2, [r7, #12]
+ 8002900:	4313      	orrs	r3, r2
+ 8002902:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC2P;
+ 8002904:	697b      	ldr	r3, [r7, #20]
+ 8002906:	f023 0320 	bic.w	r3, r3, #32
+ 800290a:	617b      	str	r3, [r7, #20]
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 4U);
+ 800290c:	683b      	ldr	r3, [r7, #0]
+ 800290e:	689b      	ldr	r3, [r3, #8]
+ 8002910:	011b      	lsls	r3, r3, #4
+ 8002912:	697a      	ldr	r2, [r7, #20]
+ 8002914:	4313      	orrs	r3, r2
+ 8002916:	617b      	str	r3, [r7, #20]
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+ 8002918:	687b      	ldr	r3, [r7, #4]
+ 800291a:	4a23      	ldr	r2, [pc, #140]	; (80029a8 <TIM_OC2_SetConfig+0xe8>)
+ 800291c:	4293      	cmp	r3, r2
+ 800291e:	d003      	beq.n	8002928 <TIM_OC2_SetConfig+0x68>
+ 8002920:	687b      	ldr	r3, [r7, #4]
+ 8002922:	4a22      	ldr	r2, [pc, #136]	; (80029ac <TIM_OC2_SetConfig+0xec>)
+ 8002924:	4293      	cmp	r3, r2
+ 8002926:	d10d      	bne.n	8002944 <TIM_OC2_SetConfig+0x84>
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC2NP;
+ 8002928:	697b      	ldr	r3, [r7, #20]
+ 800292a:	f023 0380 	bic.w	r3, r3, #128	; 0x80
+ 800292e:	617b      	str	r3, [r7, #20]
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 4U);
+ 8002930:	683b      	ldr	r3, [r7, #0]
+ 8002932:	68db      	ldr	r3, [r3, #12]
+ 8002934:	011b      	lsls	r3, r3, #4
+ 8002936:	697a      	ldr	r2, [r7, #20]
+ 8002938:	4313      	orrs	r3, r2
+ 800293a:	617b      	str	r3, [r7, #20]
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC2NE;
+ 800293c:	697b      	ldr	r3, [r7, #20]
+ 800293e:	f023 0340 	bic.w	r3, r3, #64	; 0x40
+ 8002942:	617b      	str	r3, [r7, #20]
+
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 8002944:	687b      	ldr	r3, [r7, #4]
+ 8002946:	4a18      	ldr	r2, [pc, #96]	; (80029a8 <TIM_OC2_SetConfig+0xe8>)
+ 8002948:	4293      	cmp	r3, r2
+ 800294a:	d003      	beq.n	8002954 <TIM_OC2_SetConfig+0x94>
+ 800294c:	687b      	ldr	r3, [r7, #4]
+ 800294e:	4a17      	ldr	r2, [pc, #92]	; (80029ac <TIM_OC2_SetConfig+0xec>)
+ 8002950:	4293      	cmp	r3, r2
+ 8002952:	d113      	bne.n	800297c <TIM_OC2_SetConfig+0xbc>
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS2;
+ 8002954:	693b      	ldr	r3, [r7, #16]
+ 8002956:	f423 6380 	bic.w	r3, r3, #1024	; 0x400
+ 800295a:	613b      	str	r3, [r7, #16]
+    tmpcr2 &= ~TIM_CR2_OIS2N;
+ 800295c:	693b      	ldr	r3, [r7, #16]
+ 800295e:	f423 6300 	bic.w	r3, r3, #2048	; 0x800
+ 8002962:	613b      	str	r3, [r7, #16]
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 2U);
+ 8002964:	683b      	ldr	r3, [r7, #0]
+ 8002966:	695b      	ldr	r3, [r3, #20]
+ 8002968:	009b      	lsls	r3, r3, #2
+ 800296a:	693a      	ldr	r2, [r7, #16]
+ 800296c:	4313      	orrs	r3, r2
+ 800296e:	613b      	str	r3, [r7, #16]
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+ 8002970:	683b      	ldr	r3, [r7, #0]
+ 8002972:	699b      	ldr	r3, [r3, #24]
+ 8002974:	009b      	lsls	r3, r3, #2
+ 8002976:	693a      	ldr	r2, [r7, #16]
+ 8002978:	4313      	orrs	r3, r2
+ 800297a:	613b      	str	r3, [r7, #16]
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+ 800297c:	687b      	ldr	r3, [r7, #4]
+ 800297e:	693a      	ldr	r2, [r7, #16]
+ 8002980:	605a      	str	r2, [r3, #4]
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+ 8002982:	687b      	ldr	r3, [r7, #4]
+ 8002984:	68fa      	ldr	r2, [r7, #12]
+ 8002986:	619a      	str	r2, [r3, #24]
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = OC_Config->Pulse;
+ 8002988:	683b      	ldr	r3, [r7, #0]
+ 800298a:	685a      	ldr	r2, [r3, #4]
+ 800298c:	687b      	ldr	r3, [r7, #4]
+ 800298e:	639a      	str	r2, [r3, #56]	; 0x38
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+ 8002990:	687b      	ldr	r3, [r7, #4]
+ 8002992:	697a      	ldr	r2, [r7, #20]
+ 8002994:	621a      	str	r2, [r3, #32]
+}
+ 8002996:	bf00      	nop
+ 8002998:	371c      	adds	r7, #28
+ 800299a:	46bd      	mov	sp, r7
+ 800299c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80029a0:	4770      	bx	lr
+ 80029a2:	bf00      	nop
+ 80029a4:	feff8fff 	.word	0xfeff8fff
+ 80029a8:	40010000 	.word	0x40010000
+ 80029ac:	40010400 	.word	0x40010400
+
+080029b0 <TIM_OC3_SetConfig>:
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ 80029b0:	b480      	push	{r7}
+ 80029b2:	b087      	sub	sp, #28
+ 80029b4:	af00      	add	r7, sp, #0
+ 80029b6:	6078      	str	r0, [r7, #4]
+ 80029b8:	6039      	str	r1, [r7, #0]
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 3: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+ 80029ba:	687b      	ldr	r3, [r7, #4]
+ 80029bc:	6a1b      	ldr	r3, [r3, #32]
+ 80029be:	f423 7280 	bic.w	r2, r3, #256	; 0x100
+ 80029c2:	687b      	ldr	r3, [r7, #4]
+ 80029c4:	621a      	str	r2, [r3, #32]
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+ 80029c6:	687b      	ldr	r3, [r7, #4]
+ 80029c8:	6a1b      	ldr	r3, [r3, #32]
+ 80029ca:	617b      	str	r3, [r7, #20]
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+ 80029cc:	687b      	ldr	r3, [r7, #4]
+ 80029ce:	685b      	ldr	r3, [r3, #4]
+ 80029d0:	613b      	str	r3, [r7, #16]
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+ 80029d2:	687b      	ldr	r3, [r7, #4]
+ 80029d4:	69db      	ldr	r3, [r3, #28]
+ 80029d6:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC3M;
+ 80029d8:	68fa      	ldr	r2, [r7, #12]
+ 80029da:	4b2d      	ldr	r3, [pc, #180]	; (8002a90 <TIM_OC3_SetConfig+0xe0>)
+ 80029dc:	4013      	ands	r3, r2
+ 80029de:	60fb      	str	r3, [r7, #12]
+  tmpccmrx &= ~TIM_CCMR2_CC3S;
+ 80029e0:	68fb      	ldr	r3, [r7, #12]
+ 80029e2:	f023 0303 	bic.w	r3, r3, #3
+ 80029e6:	60fb      	str	r3, [r7, #12]
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+ 80029e8:	683b      	ldr	r3, [r7, #0]
+ 80029ea:	681b      	ldr	r3, [r3, #0]
+ 80029ec:	68fa      	ldr	r2, [r7, #12]
+ 80029ee:	4313      	orrs	r3, r2
+ 80029f0:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC3P;
+ 80029f2:	697b      	ldr	r3, [r7, #20]
+ 80029f4:	f423 7300 	bic.w	r3, r3, #512	; 0x200
+ 80029f8:	617b      	str	r3, [r7, #20]
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 8U);
+ 80029fa:	683b      	ldr	r3, [r7, #0]
+ 80029fc:	689b      	ldr	r3, [r3, #8]
+ 80029fe:	021b      	lsls	r3, r3, #8
+ 8002a00:	697a      	ldr	r2, [r7, #20]
+ 8002a02:	4313      	orrs	r3, r2
+ 8002a04:	617b      	str	r3, [r7, #20]
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+ 8002a06:	687b      	ldr	r3, [r7, #4]
+ 8002a08:	4a22      	ldr	r2, [pc, #136]	; (8002a94 <TIM_OC3_SetConfig+0xe4>)
+ 8002a0a:	4293      	cmp	r3, r2
+ 8002a0c:	d003      	beq.n	8002a16 <TIM_OC3_SetConfig+0x66>
+ 8002a0e:	687b      	ldr	r3, [r7, #4]
+ 8002a10:	4a21      	ldr	r2, [pc, #132]	; (8002a98 <TIM_OC3_SetConfig+0xe8>)
+ 8002a12:	4293      	cmp	r3, r2
+ 8002a14:	d10d      	bne.n	8002a32 <TIM_OC3_SetConfig+0x82>
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC3NP;
+ 8002a16:	697b      	ldr	r3, [r7, #20]
+ 8002a18:	f423 6300 	bic.w	r3, r3, #2048	; 0x800
+ 8002a1c:	617b      	str	r3, [r7, #20]
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 8U);
+ 8002a1e:	683b      	ldr	r3, [r7, #0]
+ 8002a20:	68db      	ldr	r3, [r3, #12]
+ 8002a22:	021b      	lsls	r3, r3, #8
+ 8002a24:	697a      	ldr	r2, [r7, #20]
+ 8002a26:	4313      	orrs	r3, r2
+ 8002a28:	617b      	str	r3, [r7, #20]
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC3NE;
+ 8002a2a:	697b      	ldr	r3, [r7, #20]
+ 8002a2c:	f423 6380 	bic.w	r3, r3, #1024	; 0x400
+ 8002a30:	617b      	str	r3, [r7, #20]
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 8002a32:	687b      	ldr	r3, [r7, #4]
+ 8002a34:	4a17      	ldr	r2, [pc, #92]	; (8002a94 <TIM_OC3_SetConfig+0xe4>)
+ 8002a36:	4293      	cmp	r3, r2
+ 8002a38:	d003      	beq.n	8002a42 <TIM_OC3_SetConfig+0x92>
+ 8002a3a:	687b      	ldr	r3, [r7, #4]
+ 8002a3c:	4a16      	ldr	r2, [pc, #88]	; (8002a98 <TIM_OC3_SetConfig+0xe8>)
+ 8002a3e:	4293      	cmp	r3, r2
+ 8002a40:	d113      	bne.n	8002a6a <TIM_OC3_SetConfig+0xba>
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS3;
+ 8002a42:	693b      	ldr	r3, [r7, #16]
+ 8002a44:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
+ 8002a48:	613b      	str	r3, [r7, #16]
+    tmpcr2 &= ~TIM_CR2_OIS3N;
+ 8002a4a:	693b      	ldr	r3, [r7, #16]
+ 8002a4c:	f423 5300 	bic.w	r3, r3, #8192	; 0x2000
+ 8002a50:	613b      	str	r3, [r7, #16]
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 4U);
+ 8002a52:	683b      	ldr	r3, [r7, #0]
+ 8002a54:	695b      	ldr	r3, [r3, #20]
+ 8002a56:	011b      	lsls	r3, r3, #4
+ 8002a58:	693a      	ldr	r2, [r7, #16]
+ 8002a5a:	4313      	orrs	r3, r2
+ 8002a5c:	613b      	str	r3, [r7, #16]
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+ 8002a5e:	683b      	ldr	r3, [r7, #0]
+ 8002a60:	699b      	ldr	r3, [r3, #24]
+ 8002a62:	011b      	lsls	r3, r3, #4
+ 8002a64:	693a      	ldr	r2, [r7, #16]
+ 8002a66:	4313      	orrs	r3, r2
+ 8002a68:	613b      	str	r3, [r7, #16]
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+ 8002a6a:	687b      	ldr	r3, [r7, #4]
+ 8002a6c:	693a      	ldr	r2, [r7, #16]
+ 8002a6e:	605a      	str	r2, [r3, #4]
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+ 8002a70:	687b      	ldr	r3, [r7, #4]
+ 8002a72:	68fa      	ldr	r2, [r7, #12]
+ 8002a74:	61da      	str	r2, [r3, #28]
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = OC_Config->Pulse;
+ 8002a76:	683b      	ldr	r3, [r7, #0]
+ 8002a78:	685a      	ldr	r2, [r3, #4]
+ 8002a7a:	687b      	ldr	r3, [r7, #4]
+ 8002a7c:	63da      	str	r2, [r3, #60]	; 0x3c
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+ 8002a7e:	687b      	ldr	r3, [r7, #4]
+ 8002a80:	697a      	ldr	r2, [r7, #20]
+ 8002a82:	621a      	str	r2, [r3, #32]
 }
- 8002476:	bf00      	nop
- 8002478:	3714      	adds	r7, #20
- 800247a:	46bd      	mov	sp, r7
- 800247c:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8002480:	4770      	bx	lr
- 8002482:	bf00      	nop
- 8002484:	40010000 	.word	0x40010000
- 8002488:	40000400 	.word	0x40000400
- 800248c:	40000800 	.word	0x40000800
- 8002490:	40000c00 	.word	0x40000c00
- 8002494:	40010400 	.word	0x40010400
- 8002498:	40014000 	.word	0x40014000
- 800249c:	40014400 	.word	0x40014400
- 80024a0:	40014800 	.word	0x40014800
- 80024a4:	40001800 	.word	0x40001800
- 80024a8:	40001c00 	.word	0x40001c00
- 80024ac:	40002000 	.word	0x40002000
-
-080024b0 <HAL_TIMEx_MasterConfigSynchronization>:
+ 8002a84:	bf00      	nop
+ 8002a86:	371c      	adds	r7, #28
+ 8002a88:	46bd      	mov	sp, r7
+ 8002a8a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8002a8e:	4770      	bx	lr
+ 8002a90:	fffeff8f 	.word	0xfffeff8f
+ 8002a94:	40010000 	.word	0x40010000
+ 8002a98:	40010400 	.word	0x40010400
+
+08002a9c <TIM_OC4_SetConfig>:
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ 8002a9c:	b480      	push	{r7}
+ 8002a9e:	b087      	sub	sp, #28
+ 8002aa0:	af00      	add	r7, sp, #0
+ 8002aa2:	6078      	str	r0, [r7, #4]
+ 8002aa4:	6039      	str	r1, [r7, #0]
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+ 8002aa6:	687b      	ldr	r3, [r7, #4]
+ 8002aa8:	6a1b      	ldr	r3, [r3, #32]
+ 8002aaa:	f423 5280 	bic.w	r2, r3, #4096	; 0x1000
+ 8002aae:	687b      	ldr	r3, [r7, #4]
+ 8002ab0:	621a      	str	r2, [r3, #32]
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+ 8002ab2:	687b      	ldr	r3, [r7, #4]
+ 8002ab4:	6a1b      	ldr	r3, [r3, #32]
+ 8002ab6:	613b      	str	r3, [r7, #16]
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+ 8002ab8:	687b      	ldr	r3, [r7, #4]
+ 8002aba:	685b      	ldr	r3, [r3, #4]
+ 8002abc:	617b      	str	r3, [r7, #20]
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+ 8002abe:	687b      	ldr	r3, [r7, #4]
+ 8002ac0:	69db      	ldr	r3, [r3, #28]
+ 8002ac2:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC4M;
+ 8002ac4:	68fa      	ldr	r2, [r7, #12]
+ 8002ac6:	4b1e      	ldr	r3, [pc, #120]	; (8002b40 <TIM_OC4_SetConfig+0xa4>)
+ 8002ac8:	4013      	ands	r3, r2
+ 8002aca:	60fb      	str	r3, [r7, #12]
+  tmpccmrx &= ~TIM_CCMR2_CC4S;
+ 8002acc:	68fb      	ldr	r3, [r7, #12]
+ 8002ace:	f423 7340 	bic.w	r3, r3, #768	; 0x300
+ 8002ad2:	60fb      	str	r3, [r7, #12]
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+ 8002ad4:	683b      	ldr	r3, [r7, #0]
+ 8002ad6:	681b      	ldr	r3, [r3, #0]
+ 8002ad8:	021b      	lsls	r3, r3, #8
+ 8002ada:	68fa      	ldr	r2, [r7, #12]
+ 8002adc:	4313      	orrs	r3, r2
+ 8002ade:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC4P;
+ 8002ae0:	693b      	ldr	r3, [r7, #16]
+ 8002ae2:	f423 5300 	bic.w	r3, r3, #8192	; 0x2000
+ 8002ae6:	613b      	str	r3, [r7, #16]
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 12U);
+ 8002ae8:	683b      	ldr	r3, [r7, #0]
+ 8002aea:	689b      	ldr	r3, [r3, #8]
+ 8002aec:	031b      	lsls	r3, r3, #12
+ 8002aee:	693a      	ldr	r2, [r7, #16]
+ 8002af0:	4313      	orrs	r3, r2
+ 8002af2:	613b      	str	r3, [r7, #16]
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 8002af4:	687b      	ldr	r3, [r7, #4]
+ 8002af6:	4a13      	ldr	r2, [pc, #76]	; (8002b44 <TIM_OC4_SetConfig+0xa8>)
+ 8002af8:	4293      	cmp	r3, r2
+ 8002afa:	d003      	beq.n	8002b04 <TIM_OC4_SetConfig+0x68>
+ 8002afc:	687b      	ldr	r3, [r7, #4]
+ 8002afe:	4a12      	ldr	r2, [pc, #72]	; (8002b48 <TIM_OC4_SetConfig+0xac>)
+ 8002b00:	4293      	cmp	r3, r2
+ 8002b02:	d109      	bne.n	8002b18 <TIM_OC4_SetConfig+0x7c>
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS4;
+ 8002b04:	697b      	ldr	r3, [r7, #20]
+ 8002b06:	f423 4380 	bic.w	r3, r3, #16384	; 0x4000
+ 8002b0a:	617b      	str	r3, [r7, #20]
+
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 6U);
+ 8002b0c:	683b      	ldr	r3, [r7, #0]
+ 8002b0e:	695b      	ldr	r3, [r3, #20]
+ 8002b10:	019b      	lsls	r3, r3, #6
+ 8002b12:	697a      	ldr	r2, [r7, #20]
+ 8002b14:	4313      	orrs	r3, r2
+ 8002b16:	617b      	str	r3, [r7, #20]
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+ 8002b18:	687b      	ldr	r3, [r7, #4]
+ 8002b1a:	697a      	ldr	r2, [r7, #20]
+ 8002b1c:	605a      	str	r2, [r3, #4]
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+ 8002b1e:	687b      	ldr	r3, [r7, #4]
+ 8002b20:	68fa      	ldr	r2, [r7, #12]
+ 8002b22:	61da      	str	r2, [r3, #28]
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = OC_Config->Pulse;
+ 8002b24:	683b      	ldr	r3, [r7, #0]
+ 8002b26:	685a      	ldr	r2, [r3, #4]
+ 8002b28:	687b      	ldr	r3, [r7, #4]
+ 8002b2a:	641a      	str	r2, [r3, #64]	; 0x40
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+ 8002b2c:	687b      	ldr	r3, [r7, #4]
+ 8002b2e:	693a      	ldr	r2, [r7, #16]
+ 8002b30:	621a      	str	r2, [r3, #32]
+}
+ 8002b32:	bf00      	nop
+ 8002b34:	371c      	adds	r7, #28
+ 8002b36:	46bd      	mov	sp, r7
+ 8002b38:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8002b3c:	4770      	bx	lr
+ 8002b3e:	bf00      	nop
+ 8002b40:	feff8fff 	.word	0xfeff8fff
+ 8002b44:	40010000 	.word	0x40010000
+ 8002b48:	40010400 	.word	0x40010400
+
+08002b4c <TIM_OC5_SetConfig>:
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+                              TIM_OC_InitTypeDef *OC_Config)
+{
+ 8002b4c:	b480      	push	{r7}
+ 8002b4e:	b087      	sub	sp, #28
+ 8002b50:	af00      	add	r7, sp, #0
+ 8002b52:	6078      	str	r0, [r7, #4]
+ 8002b54:	6039      	str	r1, [r7, #0]
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the output: Reset the CCxE Bit */
+  TIMx->CCER &= ~TIM_CCER_CC5E;
+ 8002b56:	687b      	ldr	r3, [r7, #4]
+ 8002b58:	6a1b      	ldr	r3, [r3, #32]
+ 8002b5a:	f423 3280 	bic.w	r2, r3, #65536	; 0x10000
+ 8002b5e:	687b      	ldr	r3, [r7, #4]
+ 8002b60:	621a      	str	r2, [r3, #32]
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+ 8002b62:	687b      	ldr	r3, [r7, #4]
+ 8002b64:	6a1b      	ldr	r3, [r3, #32]
+ 8002b66:	613b      	str	r3, [r7, #16]
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+ 8002b68:	687b      	ldr	r3, [r7, #4]
+ 8002b6a:	685b      	ldr	r3, [r3, #4]
+ 8002b6c:	617b      	str	r3, [r7, #20]
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR3;
+ 8002b6e:	687b      	ldr	r3, [r7, #4]
+ 8002b70:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8002b72:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~(TIM_CCMR3_OC5M);
+ 8002b74:	68fa      	ldr	r2, [r7, #12]
+ 8002b76:	4b1b      	ldr	r3, [pc, #108]	; (8002be4 <TIM_OC5_SetConfig+0x98>)
+ 8002b78:	4013      	ands	r3, r2
+ 8002b7a:	60fb      	str	r3, [r7, #12]
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+ 8002b7c:	683b      	ldr	r3, [r7, #0]
+ 8002b7e:	681b      	ldr	r3, [r3, #0]
+ 8002b80:	68fa      	ldr	r2, [r7, #12]
+ 8002b82:	4313      	orrs	r3, r2
+ 8002b84:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC5P;
+ 8002b86:	693b      	ldr	r3, [r7, #16]
+ 8002b88:	f423 3300 	bic.w	r3, r3, #131072	; 0x20000
+ 8002b8c:	613b      	str	r3, [r7, #16]
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 16U);
+ 8002b8e:	683b      	ldr	r3, [r7, #0]
+ 8002b90:	689b      	ldr	r3, [r3, #8]
+ 8002b92:	041b      	lsls	r3, r3, #16
+ 8002b94:	693a      	ldr	r2, [r7, #16]
+ 8002b96:	4313      	orrs	r3, r2
+ 8002b98:	613b      	str	r3, [r7, #16]
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 8002b9a:	687b      	ldr	r3, [r7, #4]
+ 8002b9c:	4a12      	ldr	r2, [pc, #72]	; (8002be8 <TIM_OC5_SetConfig+0x9c>)
+ 8002b9e:	4293      	cmp	r3, r2
+ 8002ba0:	d003      	beq.n	8002baa <TIM_OC5_SetConfig+0x5e>
+ 8002ba2:	687b      	ldr	r3, [r7, #4]
+ 8002ba4:	4a11      	ldr	r2, [pc, #68]	; (8002bec <TIM_OC5_SetConfig+0xa0>)
+ 8002ba6:	4293      	cmp	r3, r2
+ 8002ba8:	d109      	bne.n	8002bbe <TIM_OC5_SetConfig+0x72>
+  {
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS5;
+ 8002baa:	697b      	ldr	r3, [r7, #20]
+ 8002bac:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
+ 8002bb0:	617b      	str	r3, [r7, #20]
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 8U);
+ 8002bb2:	683b      	ldr	r3, [r7, #0]
+ 8002bb4:	695b      	ldr	r3, [r3, #20]
+ 8002bb6:	021b      	lsls	r3, r3, #8
+ 8002bb8:	697a      	ldr	r2, [r7, #20]
+ 8002bba:	4313      	orrs	r3, r2
+ 8002bbc:	617b      	str	r3, [r7, #20]
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+ 8002bbe:	687b      	ldr	r3, [r7, #4]
+ 8002bc0:	697a      	ldr	r2, [r7, #20]
+ 8002bc2:	605a      	str	r2, [r3, #4]
+
+  /* Write to TIMx CCMR3 */
+  TIMx->CCMR3 = tmpccmrx;
+ 8002bc4:	687b      	ldr	r3, [r7, #4]
+ 8002bc6:	68fa      	ldr	r2, [r7, #12]
+ 8002bc8:	655a      	str	r2, [r3, #84]	; 0x54
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR5 = OC_Config->Pulse;
+ 8002bca:	683b      	ldr	r3, [r7, #0]
+ 8002bcc:	685a      	ldr	r2, [r3, #4]
+ 8002bce:	687b      	ldr	r3, [r7, #4]
+ 8002bd0:	659a      	str	r2, [r3, #88]	; 0x58
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+ 8002bd2:	687b      	ldr	r3, [r7, #4]
+ 8002bd4:	693a      	ldr	r2, [r7, #16]
+ 8002bd6:	621a      	str	r2, [r3, #32]
+}
+ 8002bd8:	bf00      	nop
+ 8002bda:	371c      	adds	r7, #28
+ 8002bdc:	46bd      	mov	sp, r7
+ 8002bde:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8002be2:	4770      	bx	lr
+ 8002be4:	fffeff8f 	.word	0xfffeff8f
+ 8002be8:	40010000 	.word	0x40010000
+ 8002bec:	40010400 	.word	0x40010400
+
+08002bf0 <TIM_OC6_SetConfig>:
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+                              TIM_OC_InitTypeDef *OC_Config)
+{
+ 8002bf0:	b480      	push	{r7}
+ 8002bf2:	b087      	sub	sp, #28
+ 8002bf4:	af00      	add	r7, sp, #0
+ 8002bf6:	6078      	str	r0, [r7, #4]
+ 8002bf8:	6039      	str	r1, [r7, #0]
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the output: Reset the CCxE Bit */
+  TIMx->CCER &= ~TIM_CCER_CC6E;
+ 8002bfa:	687b      	ldr	r3, [r7, #4]
+ 8002bfc:	6a1b      	ldr	r3, [r3, #32]
+ 8002bfe:	f423 1280 	bic.w	r2, r3, #1048576	; 0x100000
+ 8002c02:	687b      	ldr	r3, [r7, #4]
+ 8002c04:	621a      	str	r2, [r3, #32]
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+ 8002c06:	687b      	ldr	r3, [r7, #4]
+ 8002c08:	6a1b      	ldr	r3, [r3, #32]
+ 8002c0a:	613b      	str	r3, [r7, #16]
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+ 8002c0c:	687b      	ldr	r3, [r7, #4]
+ 8002c0e:	685b      	ldr	r3, [r3, #4]
+ 8002c10:	617b      	str	r3, [r7, #20]
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR3;
+ 8002c12:	687b      	ldr	r3, [r7, #4]
+ 8002c14:	6d5b      	ldr	r3, [r3, #84]	; 0x54
+ 8002c16:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~(TIM_CCMR3_OC6M);
+ 8002c18:	68fa      	ldr	r2, [r7, #12]
+ 8002c1a:	4b1c      	ldr	r3, [pc, #112]	; (8002c8c <TIM_OC6_SetConfig+0x9c>)
+ 8002c1c:	4013      	ands	r3, r2
+ 8002c1e:	60fb      	str	r3, [r7, #12]
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+ 8002c20:	683b      	ldr	r3, [r7, #0]
+ 8002c22:	681b      	ldr	r3, [r3, #0]
+ 8002c24:	021b      	lsls	r3, r3, #8
+ 8002c26:	68fa      	ldr	r2, [r7, #12]
+ 8002c28:	4313      	orrs	r3, r2
+ 8002c2a:	60fb      	str	r3, [r7, #12]
+
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+ 8002c2c:	693b      	ldr	r3, [r7, #16]
+ 8002c2e:	f423 1300 	bic.w	r3, r3, #2097152	; 0x200000
+ 8002c32:	613b      	str	r3, [r7, #16]
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 20U);
+ 8002c34:	683b      	ldr	r3, [r7, #0]
+ 8002c36:	689b      	ldr	r3, [r3, #8]
+ 8002c38:	051b      	lsls	r3, r3, #20
+ 8002c3a:	693a      	ldr	r2, [r7, #16]
+ 8002c3c:	4313      	orrs	r3, r2
+ 8002c3e:	613b      	str	r3, [r7, #16]
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 8002c40:	687b      	ldr	r3, [r7, #4]
+ 8002c42:	4a13      	ldr	r2, [pc, #76]	; (8002c90 <TIM_OC6_SetConfig+0xa0>)
+ 8002c44:	4293      	cmp	r3, r2
+ 8002c46:	d003      	beq.n	8002c50 <TIM_OC6_SetConfig+0x60>
+ 8002c48:	687b      	ldr	r3, [r7, #4]
+ 8002c4a:	4a12      	ldr	r2, [pc, #72]	; (8002c94 <TIM_OC6_SetConfig+0xa4>)
+ 8002c4c:	4293      	cmp	r3, r2
+ 8002c4e:	d109      	bne.n	8002c64 <TIM_OC6_SetConfig+0x74>
+  {
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS6;
+ 8002c50:	697b      	ldr	r3, [r7, #20]
+ 8002c52:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
+ 8002c56:	617b      	str	r3, [r7, #20]
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 10U);
+ 8002c58:	683b      	ldr	r3, [r7, #0]
+ 8002c5a:	695b      	ldr	r3, [r3, #20]
+ 8002c5c:	029b      	lsls	r3, r3, #10
+ 8002c5e:	697a      	ldr	r2, [r7, #20]
+ 8002c60:	4313      	orrs	r3, r2
+ 8002c62:	617b      	str	r3, [r7, #20]
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+ 8002c64:	687b      	ldr	r3, [r7, #4]
+ 8002c66:	697a      	ldr	r2, [r7, #20]
+ 8002c68:	605a      	str	r2, [r3, #4]
+
+  /* Write to TIMx CCMR3 */
+  TIMx->CCMR3 = tmpccmrx;
+ 8002c6a:	687b      	ldr	r3, [r7, #4]
+ 8002c6c:	68fa      	ldr	r2, [r7, #12]
+ 8002c6e:	655a      	str	r2, [r3, #84]	; 0x54
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR6 = OC_Config->Pulse;
+ 8002c70:	683b      	ldr	r3, [r7, #0]
+ 8002c72:	685a      	ldr	r2, [r3, #4]
+ 8002c74:	687b      	ldr	r3, [r7, #4]
+ 8002c76:	65da      	str	r2, [r3, #92]	; 0x5c
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+ 8002c78:	687b      	ldr	r3, [r7, #4]
+ 8002c7a:	693a      	ldr	r2, [r7, #16]
+ 8002c7c:	621a      	str	r2, [r3, #32]
+}
+ 8002c7e:	bf00      	nop
+ 8002c80:	371c      	adds	r7, #28
+ 8002c82:	46bd      	mov	sp, r7
+ 8002c84:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8002c88:	4770      	bx	lr
+ 8002c8a:	bf00      	nop
+ 8002c8c:	feff8fff 	.word	0xfeff8fff
+ 8002c90:	40010000 	.word	0x40010000
+ 8002c94:	40010400 	.word	0x40010400
+
+08002c98 <TIM_CCxChannelCmd>:
+  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
+  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+  * @retval None
+  */
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+ 8002c98:	b480      	push	{r7}
+ 8002c9a:	b087      	sub	sp, #28
+ 8002c9c:	af00      	add	r7, sp, #0
+ 8002c9e:	60f8      	str	r0, [r7, #12]
+ 8002ca0:	60b9      	str	r1, [r7, #8]
+ 8002ca2:	607a      	str	r2, [r7, #4]
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_TIM_CHANNELS(Channel));
+
+  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+ 8002ca4:	68bb      	ldr	r3, [r7, #8]
+ 8002ca6:	f003 031f 	and.w	r3, r3, #31
+ 8002caa:	2201      	movs	r2, #1
+ 8002cac:	fa02 f303 	lsl.w	r3, r2, r3
+ 8002cb0:	617b      	str	r3, [r7, #20]
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= ~tmp;
+ 8002cb2:	68fb      	ldr	r3, [r7, #12]
+ 8002cb4:	6a1a      	ldr	r2, [r3, #32]
+ 8002cb6:	697b      	ldr	r3, [r7, #20]
+ 8002cb8:	43db      	mvns	r3, r3
+ 8002cba:	401a      	ands	r2, r3
+ 8002cbc:	68fb      	ldr	r3, [r7, #12]
+ 8002cbe:	621a      	str	r2, [r3, #32]
+
+  /* Set or reset the CCxE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+ 8002cc0:	68fb      	ldr	r3, [r7, #12]
+ 8002cc2:	6a1a      	ldr	r2, [r3, #32]
+ 8002cc4:	68bb      	ldr	r3, [r7, #8]
+ 8002cc6:	f003 031f 	and.w	r3, r3, #31
+ 8002cca:	6879      	ldr	r1, [r7, #4]
+ 8002ccc:	fa01 f303 	lsl.w	r3, r1, r3
+ 8002cd0:	431a      	orrs	r2, r3
+ 8002cd2:	68fb      	ldr	r3, [r7, #12]
+ 8002cd4:	621a      	str	r2, [r3, #32]
+}
+ 8002cd6:	bf00      	nop
+ 8002cd8:	371c      	adds	r7, #28
+ 8002cda:	46bd      	mov	sp, r7
+ 8002cdc:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8002ce0:	4770      	bx	lr
+	...
+
+08002ce4 <HAL_TIMEx_MasterConfigSynchronization>:
   *         mode.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
                                                         TIM_MasterConfigTypeDef *sMasterConfig)
 {
- 80024b0:	b480      	push	{r7}
- 80024b2:	b085      	sub	sp, #20
- 80024b4:	af00      	add	r7, sp, #0
- 80024b6:	6078      	str	r0, [r7, #4]
- 80024b8:	6039      	str	r1, [r7, #0]
+ 8002ce4:	b480      	push	{r7}
+ 8002ce6:	b085      	sub	sp, #20
+ 8002ce8:	af00      	add	r7, sp, #0
+ 8002cea:	6078      	str	r0, [r7, #4]
+ 8002cec:	6039      	str	r1, [r7, #0]
   assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
 
   /* Check input state */
   __HAL_LOCK(htim);
- 80024ba:	687b      	ldr	r3, [r7, #4]
- 80024bc:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
- 80024c0:	2b01      	cmp	r3, #1
- 80024c2:	d101      	bne.n	80024c8 <HAL_TIMEx_MasterConfigSynchronization+0x18>
- 80024c4:	2302      	movs	r3, #2
- 80024c6:	e045      	b.n	8002554 <HAL_TIMEx_MasterConfigSynchronization+0xa4>
- 80024c8:	687b      	ldr	r3, [r7, #4]
- 80024ca:	2201      	movs	r2, #1
- 80024cc:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
+ 8002cee:	687b      	ldr	r3, [r7, #4]
+ 8002cf0:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
+ 8002cf4:	2b01      	cmp	r3, #1
+ 8002cf6:	d101      	bne.n	8002cfc <HAL_TIMEx_MasterConfigSynchronization+0x18>
+ 8002cf8:	2302      	movs	r3, #2
+ 8002cfa:	e045      	b.n	8002d88 <HAL_TIMEx_MasterConfigSynchronization+0xa4>
+ 8002cfc:	687b      	ldr	r3, [r7, #4]
+ 8002cfe:	2201      	movs	r2, #1
+ 8002d00:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
 
   /* Change the handler state */
   htim->State = HAL_TIM_STATE_BUSY;
- 80024d0:	687b      	ldr	r3, [r7, #4]
- 80024d2:	2202      	movs	r2, #2
- 80024d4:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+ 8002d04:	687b      	ldr	r3, [r7, #4]
+ 8002d06:	2202      	movs	r2, #2
+ 8002d08:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
 
   /* Get the TIMx CR2 register value */
   tmpcr2 = htim->Instance->CR2;
- 80024d8:	687b      	ldr	r3, [r7, #4]
- 80024da:	681b      	ldr	r3, [r3, #0]
- 80024dc:	685b      	ldr	r3, [r3, #4]
- 80024de:	60fb      	str	r3, [r7, #12]
+ 8002d0c:	687b      	ldr	r3, [r7, #4]
+ 8002d0e:	681b      	ldr	r3, [r3, #0]
+ 8002d10:	685b      	ldr	r3, [r3, #4]
+ 8002d12:	60fb      	str	r3, [r7, #12]
 
   /* Get the TIMx SMCR register value */
   tmpsmcr = htim->Instance->SMCR;
- 80024e0:	687b      	ldr	r3, [r7, #4]
- 80024e2:	681b      	ldr	r3, [r3, #0]
- 80024e4:	689b      	ldr	r3, [r3, #8]
- 80024e6:	60bb      	str	r3, [r7, #8]
+ 8002d14:	687b      	ldr	r3, [r7, #4]
+ 8002d16:	681b      	ldr	r3, [r3, #0]
+ 8002d18:	689b      	ldr	r3, [r3, #8]
+ 8002d1a:	60bb      	str	r3, [r7, #8]
 
   /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
   if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
- 80024e8:	687b      	ldr	r3, [r7, #4]
- 80024ea:	681b      	ldr	r3, [r3, #0]
- 80024ec:	4a1c      	ldr	r2, [pc, #112]	; (8002560 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
- 80024ee:	4293      	cmp	r3, r2
- 80024f0:	d004      	beq.n	80024fc <HAL_TIMEx_MasterConfigSynchronization+0x4c>
- 80024f2:	687b      	ldr	r3, [r7, #4]
- 80024f4:	681b      	ldr	r3, [r3, #0]
- 80024f6:	4a1b      	ldr	r2, [pc, #108]	; (8002564 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
- 80024f8:	4293      	cmp	r3, r2
- 80024fa:	d108      	bne.n	800250e <HAL_TIMEx_MasterConfigSynchronization+0x5e>
+ 8002d1c:	687b      	ldr	r3, [r7, #4]
+ 8002d1e:	681b      	ldr	r3, [r3, #0]
+ 8002d20:	4a1c      	ldr	r2, [pc, #112]	; (8002d94 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
+ 8002d22:	4293      	cmp	r3, r2
+ 8002d24:	d004      	beq.n	8002d30 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
+ 8002d26:	687b      	ldr	r3, [r7, #4]
+ 8002d28:	681b      	ldr	r3, [r3, #0]
+ 8002d2a:	4a1b      	ldr	r2, [pc, #108]	; (8002d98 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
+ 8002d2c:	4293      	cmp	r3, r2
+ 8002d2e:	d108      	bne.n	8002d42 <HAL_TIMEx_MasterConfigSynchronization+0x5e>
   {
     /* Check the parameters */
     assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
 
     /* Clear the MMS2 bits */
     tmpcr2 &= ~TIM_CR2_MMS2;
- 80024fc:	68fb      	ldr	r3, [r7, #12]
- 80024fe:	f423 0370 	bic.w	r3, r3, #15728640	; 0xf00000
- 8002502:	60fb      	str	r3, [r7, #12]
+ 8002d30:	68fb      	ldr	r3, [r7, #12]
+ 8002d32:	f423 0370 	bic.w	r3, r3, #15728640	; 0xf00000
+ 8002d36:	60fb      	str	r3, [r7, #12]
     /* Select the TRGO2 source*/
     tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
- 8002504:	683b      	ldr	r3, [r7, #0]
- 8002506:	685b      	ldr	r3, [r3, #4]
- 8002508:	68fa      	ldr	r2, [r7, #12]
- 800250a:	4313      	orrs	r3, r2
- 800250c:	60fb      	str	r3, [r7, #12]
+ 8002d38:	683b      	ldr	r3, [r7, #0]
+ 8002d3a:	685b      	ldr	r3, [r3, #4]
+ 8002d3c:	68fa      	ldr	r2, [r7, #12]
+ 8002d3e:	4313      	orrs	r3, r2
+ 8002d40:	60fb      	str	r3, [r7, #12]
   }
 
   /* Reset the MMS Bits */
   tmpcr2 &= ~TIM_CR2_MMS;
- 800250e:	68fb      	ldr	r3, [r7, #12]
- 8002510:	f023 0370 	bic.w	r3, r3, #112	; 0x70
- 8002514:	60fb      	str	r3, [r7, #12]
+ 8002d42:	68fb      	ldr	r3, [r7, #12]
+ 8002d44:	f023 0370 	bic.w	r3, r3, #112	; 0x70
+ 8002d48:	60fb      	str	r3, [r7, #12]
   /* Select the TRGO source */
   tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
- 8002516:	683b      	ldr	r3, [r7, #0]
- 8002518:	681b      	ldr	r3, [r3, #0]
- 800251a:	68fa      	ldr	r2, [r7, #12]
- 800251c:	4313      	orrs	r3, r2
- 800251e:	60fb      	str	r3, [r7, #12]
+ 8002d4a:	683b      	ldr	r3, [r7, #0]
+ 8002d4c:	681b      	ldr	r3, [r3, #0]
+ 8002d4e:	68fa      	ldr	r2, [r7, #12]
+ 8002d50:	4313      	orrs	r3, r2
+ 8002d52:	60fb      	str	r3, [r7, #12]
 
   /* Reset the MSM Bit */
   tmpsmcr &= ~TIM_SMCR_MSM;
- 8002520:	68bb      	ldr	r3, [r7, #8]
- 8002522:	f023 0380 	bic.w	r3, r3, #128	; 0x80
- 8002526:	60bb      	str	r3, [r7, #8]
+ 8002d54:	68bb      	ldr	r3, [r7, #8]
+ 8002d56:	f023 0380 	bic.w	r3, r3, #128	; 0x80
+ 8002d5a:	60bb      	str	r3, [r7, #8]
   /* Set master mode */
   tmpsmcr |= sMasterConfig->MasterSlaveMode;
- 8002528:	683b      	ldr	r3, [r7, #0]
- 800252a:	689b      	ldr	r3, [r3, #8]
- 800252c:	68ba      	ldr	r2, [r7, #8]
- 800252e:	4313      	orrs	r3, r2
- 8002530:	60bb      	str	r3, [r7, #8]
+ 8002d5c:	683b      	ldr	r3, [r7, #0]
+ 8002d5e:	689b      	ldr	r3, [r3, #8]
+ 8002d60:	68ba      	ldr	r2, [r7, #8]
+ 8002d62:	4313      	orrs	r3, r2
+ 8002d64:	60bb      	str	r3, [r7, #8]
 
   /* Update TIMx CR2 */
   htim->Instance->CR2 = tmpcr2;
- 8002532:	687b      	ldr	r3, [r7, #4]
- 8002534:	681b      	ldr	r3, [r3, #0]
- 8002536:	68fa      	ldr	r2, [r7, #12]
- 8002538:	605a      	str	r2, [r3, #4]
+ 8002d66:	687b      	ldr	r3, [r7, #4]
+ 8002d68:	681b      	ldr	r3, [r3, #0]
+ 8002d6a:	68fa      	ldr	r2, [r7, #12]
+ 8002d6c:	605a      	str	r2, [r3, #4]
 
   /* Update TIMx SMCR */
   htim->Instance->SMCR = tmpsmcr;
- 800253a:	687b      	ldr	r3, [r7, #4]
- 800253c:	681b      	ldr	r3, [r3, #0]
- 800253e:	68ba      	ldr	r2, [r7, #8]
- 8002540:	609a      	str	r2, [r3, #8]
+ 8002d6e:	687b      	ldr	r3, [r7, #4]
+ 8002d70:	681b      	ldr	r3, [r3, #0]
+ 8002d72:	68ba      	ldr	r2, [r7, #8]
+ 8002d74:	609a      	str	r2, [r3, #8]
 
   /* Change the htim state */
   htim->State = HAL_TIM_STATE_READY;
- 8002542:	687b      	ldr	r3, [r7, #4]
- 8002544:	2201      	movs	r2, #1
- 8002546:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
+ 8002d76:	687b      	ldr	r3, [r7, #4]
+ 8002d78:	2201      	movs	r2, #1
+ 8002d7a:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
 
   __HAL_UNLOCK(htim);
- 800254a:	687b      	ldr	r3, [r7, #4]
- 800254c:	2200      	movs	r2, #0
- 800254e:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
+ 8002d7e:	687b      	ldr	r3, [r7, #4]
+ 8002d80:	2200      	movs	r2, #0
+ 8002d82:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
 
   return HAL_OK;
- 8002552:	2300      	movs	r3, #0
+ 8002d86:	2300      	movs	r3, #0
 }
- 8002554:	4618      	mov	r0, r3
- 8002556:	3714      	adds	r7, #20
- 8002558:	46bd      	mov	sp, r7
- 800255a:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800255e:	4770      	bx	lr
- 8002560:	40010000 	.word	0x40010000
- 8002564:	40010400 	.word	0x40010400
-
-08002568 <HAL_UART_Init>:
+ 8002d88:	4618      	mov	r0, r3
+ 8002d8a:	3714      	adds	r7, #20
+ 8002d8c:	46bd      	mov	sp, r7
+ 8002d8e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8002d92:	4770      	bx	lr
+ 8002d94:	40010000 	.word	0x40010000
+ 8002d98:	40010400 	.word	0x40010400
+
+08002d9c <HAL_UART_Init>:
   *        parameters in the UART_InitTypeDef and initialize the associated handle.
   * @param huart UART handle.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
 {
- 8002568:	b580      	push	{r7, lr}
- 800256a:	b082      	sub	sp, #8
- 800256c:	af00      	add	r7, sp, #0
- 800256e:	6078      	str	r0, [r7, #4]
+ 8002d9c:	b580      	push	{r7, lr}
+ 8002d9e:	b082      	sub	sp, #8
+ 8002da0:	af00      	add	r7, sp, #0
+ 8002da2:	6078      	str	r0, [r7, #4]
   /* Check the UART handle allocation */
   if (huart == NULL)
- 8002570:	687b      	ldr	r3, [r7, #4]
- 8002572:	2b00      	cmp	r3, #0
- 8002574:	d101      	bne.n	800257a <HAL_UART_Init+0x12>
+ 8002da4:	687b      	ldr	r3, [r7, #4]
+ 8002da6:	2b00      	cmp	r3, #0
+ 8002da8:	d101      	bne.n	8002dae <HAL_UART_Init+0x12>
   {
     return HAL_ERROR;
- 8002576:	2301      	movs	r3, #1
- 8002578:	e040      	b.n	80025fc <HAL_UART_Init+0x94>
+ 8002daa:	2301      	movs	r3, #1
+ 8002dac:	e040      	b.n	8002e30 <HAL_UART_Init+0x94>
   {
     /* Check the parameters */
     assert_param(IS_UART_INSTANCE(huart->Instance));
   }
 
   if (huart->gState == HAL_UART_STATE_RESET)
- 800257a:	687b      	ldr	r3, [r7, #4]
- 800257c:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 800257e:	2b00      	cmp	r3, #0
- 8002580:	d106      	bne.n	8002590 <HAL_UART_Init+0x28>
+ 8002dae:	687b      	ldr	r3, [r7, #4]
+ 8002db0:	6f5b      	ldr	r3, [r3, #116]	; 0x74
+ 8002db2:	2b00      	cmp	r3, #0
+ 8002db4:	d106      	bne.n	8002dc4 <HAL_UART_Init+0x28>
   {
     /* Allocate lock resource and initialize it */
     huart->Lock = HAL_UNLOCKED;
- 8002582:	687b      	ldr	r3, [r7, #4]
- 8002584:	2200      	movs	r2, #0
- 8002586:	f883 2070 	strb.w	r2, [r3, #112]	; 0x70
+ 8002db6:	687b      	ldr	r3, [r7, #4]
+ 8002db8:	2200      	movs	r2, #0
+ 8002dba:	f883 2070 	strb.w	r2, [r3, #112]	; 0x70
 
     /* Init the low level hardware */
     huart->MspInitCallback(huart);
 #else
     /* Init the low level hardware : GPIO, CLOCK */
     HAL_UART_MspInit(huart);
- 800258a:	6878      	ldr	r0, [r7, #4]
- 800258c:	f000 ff5a 	bl	8003444 <HAL_UART_MspInit>
+ 8002dbe:	6878      	ldr	r0, [r7, #4]
+ 8002dc0:	f001 f9a2 	bl	8004108 <HAL_UART_MspInit>
 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
   }
 
   huart->gState = HAL_UART_STATE_BUSY;
- 8002590:	687b      	ldr	r3, [r7, #4]
- 8002592:	2224      	movs	r2, #36	; 0x24
- 8002594:	675a      	str	r2, [r3, #116]	; 0x74
+ 8002dc4:	687b      	ldr	r3, [r7, #4]
+ 8002dc6:	2224      	movs	r2, #36	; 0x24
+ 8002dc8:	675a      	str	r2, [r3, #116]	; 0x74
 
   /* Disable the Peripheral */
   __HAL_UART_DISABLE(huart);
- 8002596:	687b      	ldr	r3, [r7, #4]
- 8002598:	681b      	ldr	r3, [r3, #0]
- 800259a:	681a      	ldr	r2, [r3, #0]
- 800259c:	687b      	ldr	r3, [r7, #4]
- 800259e:	681b      	ldr	r3, [r3, #0]
- 80025a0:	f022 0201 	bic.w	r2, r2, #1
- 80025a4:	601a      	str	r2, [r3, #0]
+ 8002dca:	687b      	ldr	r3, [r7, #4]
+ 8002dcc:	681b      	ldr	r3, [r3, #0]
+ 8002dce:	681a      	ldr	r2, [r3, #0]
+ 8002dd0:	687b      	ldr	r3, [r7, #4]
+ 8002dd2:	681b      	ldr	r3, [r3, #0]
+ 8002dd4:	f022 0201 	bic.w	r2, r2, #1
+ 8002dd8:	601a      	str	r2, [r3, #0]
 
   /* Set the UART Communication parameters */
   if (UART_SetConfig(huart) == HAL_ERROR)
- 80025a6:	6878      	ldr	r0, [r7, #4]
- 80025a8:	f000 f95c 	bl	8002864 <UART_SetConfig>
- 80025ac:	4603      	mov	r3, r0
- 80025ae:	2b01      	cmp	r3, #1
- 80025b0:	d101      	bne.n	80025b6 <HAL_UART_Init+0x4e>
+ 8002dda:	6878      	ldr	r0, [r7, #4]
+ 8002ddc:	f000 f95c 	bl	8003098 <UART_SetConfig>
+ 8002de0:	4603      	mov	r3, r0
+ 8002de2:	2b01      	cmp	r3, #1
+ 8002de4:	d101      	bne.n	8002dea <HAL_UART_Init+0x4e>
   {
     return HAL_ERROR;
- 80025b2:	2301      	movs	r3, #1
- 80025b4:	e022      	b.n	80025fc <HAL_UART_Init+0x94>
+ 8002de6:	2301      	movs	r3, #1
+ 8002de8:	e022      	b.n	8002e30 <HAL_UART_Init+0x94>
   }
 
   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- 80025b6:	687b      	ldr	r3, [r7, #4]
- 80025b8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 80025ba:	2b00      	cmp	r3, #0
- 80025bc:	d002      	beq.n	80025c4 <HAL_UART_Init+0x5c>
+ 8002dea:	687b      	ldr	r3, [r7, #4]
+ 8002dec:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8002dee:	2b00      	cmp	r3, #0
+ 8002df0:	d002      	beq.n	8002df8 <HAL_UART_Init+0x5c>
   {
     UART_AdvFeatureConfig(huart);
- 80025be:	6878      	ldr	r0, [r7, #4]
- 80025c0:	f000 fbf4 	bl	8002dac <UART_AdvFeatureConfig>
+ 8002df2:	6878      	ldr	r0, [r7, #4]
+ 8002df4:	f000 fbf4 	bl	80035e0 <UART_AdvFeatureConfig>
   }
 
   /* In asynchronous mode, the following bits must be kept cleared:
   - LINEN and CLKEN bits in the USART_CR2 register,
   - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- 80025c4:	687b      	ldr	r3, [r7, #4]
- 80025c6:	681b      	ldr	r3, [r3, #0]
- 80025c8:	685a      	ldr	r2, [r3, #4]
- 80025ca:	687b      	ldr	r3, [r7, #4]
- 80025cc:	681b      	ldr	r3, [r3, #0]
- 80025ce:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
- 80025d2:	605a      	str	r2, [r3, #4]
+ 8002df8:	687b      	ldr	r3, [r7, #4]
+ 8002dfa:	681b      	ldr	r3, [r3, #0]
+ 8002dfc:	685a      	ldr	r2, [r3, #4]
+ 8002dfe:	687b      	ldr	r3, [r7, #4]
+ 8002e00:	681b      	ldr	r3, [r3, #0]
+ 8002e02:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
+ 8002e06:	605a      	str	r2, [r3, #4]
   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
- 80025d4:	687b      	ldr	r3, [r7, #4]
- 80025d6:	681b      	ldr	r3, [r3, #0]
- 80025d8:	689a      	ldr	r2, [r3, #8]
- 80025da:	687b      	ldr	r3, [r7, #4]
- 80025dc:	681b      	ldr	r3, [r3, #0]
- 80025de:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
- 80025e2:	609a      	str	r2, [r3, #8]
+ 8002e08:	687b      	ldr	r3, [r7, #4]
+ 8002e0a:	681b      	ldr	r3, [r3, #0]
+ 8002e0c:	689a      	ldr	r2, [r3, #8]
+ 8002e0e:	687b      	ldr	r3, [r7, #4]
+ 8002e10:	681b      	ldr	r3, [r3, #0]
+ 8002e12:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
+ 8002e16:	609a      	str	r2, [r3, #8]
 
   /* Enable the Peripheral */
   __HAL_UART_ENABLE(huart);
- 80025e4:	687b      	ldr	r3, [r7, #4]
- 80025e6:	681b      	ldr	r3, [r3, #0]
- 80025e8:	681a      	ldr	r2, [r3, #0]
- 80025ea:	687b      	ldr	r3, [r7, #4]
- 80025ec:	681b      	ldr	r3, [r3, #0]
- 80025ee:	f042 0201 	orr.w	r2, r2, #1
- 80025f2:	601a      	str	r2, [r3, #0]
+ 8002e18:	687b      	ldr	r3, [r7, #4]
+ 8002e1a:	681b      	ldr	r3, [r3, #0]
+ 8002e1c:	681a      	ldr	r2, [r3, #0]
+ 8002e1e:	687b      	ldr	r3, [r7, #4]
+ 8002e20:	681b      	ldr	r3, [r3, #0]
+ 8002e22:	f042 0201 	orr.w	r2, r2, #1
+ 8002e26:	601a      	str	r2, [r3, #0]
 
   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
   return (UART_CheckIdleState(huart));
- 80025f4:	6878      	ldr	r0, [r7, #4]
- 80025f6:	f000 fc7b 	bl	8002ef0 <UART_CheckIdleState>
- 80025fa:	4603      	mov	r3, r0
+ 8002e28:	6878      	ldr	r0, [r7, #4]
+ 8002e2a:	f000 fc7b 	bl	8003724 <UART_CheckIdleState>
+ 8002e2e:	4603      	mov	r3, r0
 }
- 80025fc:	4618      	mov	r0, r3
- 80025fe:	3708      	adds	r7, #8
- 8002600:	46bd      	mov	sp, r7
- 8002602:	bd80      	pop	{r7, pc}
+ 8002e30:	4618      	mov	r0, r3
+ 8002e32:	3708      	adds	r7, #8
+ 8002e34:	46bd      	mov	sp, r7
+ 8002e36:	bd80      	pop	{r7, pc}
 
-08002604 <HAL_UART_IRQHandler>:
+08002e38 <HAL_UART_IRQHandler>:
   * @brief Handle UART interrupt request.
   * @param huart UART handle.
   * @retval None
   */
 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
 {
- 8002604:	b580      	push	{r7, lr}
- 8002606:	b088      	sub	sp, #32
- 8002608:	af00      	add	r7, sp, #0
- 800260a:	6078      	str	r0, [r7, #4]
+ 8002e38:	b580      	push	{r7, lr}
+ 8002e3a:	b088      	sub	sp, #32
+ 8002e3c:	af00      	add	r7, sp, #0
+ 8002e3e:	6078      	str	r0, [r7, #4]
   uint32_t isrflags   = READ_REG(huart->Instance->ISR);
- 800260c:	687b      	ldr	r3, [r7, #4]
- 800260e:	681b      	ldr	r3, [r3, #0]
- 8002610:	69db      	ldr	r3, [r3, #28]
- 8002612:	61fb      	str	r3, [r7, #28]
+ 8002e40:	687b      	ldr	r3, [r7, #4]
+ 8002e42:	681b      	ldr	r3, [r3, #0]
+ 8002e44:	69db      	ldr	r3, [r3, #28]
+ 8002e46:	61fb      	str	r3, [r7, #28]
   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
- 8002614:	687b      	ldr	r3, [r7, #4]
- 8002616:	681b      	ldr	r3, [r3, #0]
- 8002618:	681b      	ldr	r3, [r3, #0]
- 800261a:	61bb      	str	r3, [r7, #24]
+ 8002e48:	687b      	ldr	r3, [r7, #4]
+ 8002e4a:	681b      	ldr	r3, [r3, #0]
+ 8002e4c:	681b      	ldr	r3, [r3, #0]
+ 8002e4e:	61bb      	str	r3, [r7, #24]
   uint32_t cr3its     = READ_REG(huart->Instance->CR3);
- 800261c:	687b      	ldr	r3, [r7, #4]
- 800261e:	681b      	ldr	r3, [r3, #0]
- 8002620:	689b      	ldr	r3, [r3, #8]
- 8002622:	617b      	str	r3, [r7, #20]
+ 8002e50:	687b      	ldr	r3, [r7, #4]
+ 8002e52:	681b      	ldr	r3, [r3, #0]
+ 8002e54:	689b      	ldr	r3, [r3, #8]
+ 8002e56:	617b      	str	r3, [r7, #20]
 
   uint32_t errorflags;
   uint32_t errorcode;
 
   /* If no error occurs */
   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- 8002624:	69fb      	ldr	r3, [r7, #28]
- 8002626:	f003 030f 	and.w	r3, r3, #15
- 800262a:	613b      	str	r3, [r7, #16]
+ 8002e58:	69fb      	ldr	r3, [r7, #28]
+ 8002e5a:	f003 030f 	and.w	r3, r3, #15
+ 8002e5e:	613b      	str	r3, [r7, #16]
   if (errorflags == 0U)
- 800262c:	693b      	ldr	r3, [r7, #16]
- 800262e:	2b00      	cmp	r3, #0
- 8002630:	d113      	bne.n	800265a <HAL_UART_IRQHandler+0x56>
+ 8002e60:	693b      	ldr	r3, [r7, #16]
+ 8002e62:	2b00      	cmp	r3, #0
+ 8002e64:	d113      	bne.n	8002e8e <HAL_UART_IRQHandler+0x56>
   {
     /* UART in mode Receiver ---------------------------------------------------*/
     if (((isrflags & USART_ISR_RXNE) != 0U)
- 8002632:	69fb      	ldr	r3, [r7, #28]
- 8002634:	f003 0320 	and.w	r3, r3, #32
- 8002638:	2b00      	cmp	r3, #0
- 800263a:	d00e      	beq.n	800265a <HAL_UART_IRQHandler+0x56>
+ 8002e66:	69fb      	ldr	r3, [r7, #28]
+ 8002e68:	f003 0320 	and.w	r3, r3, #32
+ 8002e6c:	2b00      	cmp	r3, #0
+ 8002e6e:	d00e      	beq.n	8002e8e <HAL_UART_IRQHandler+0x56>
         && ((cr1its & USART_CR1_RXNEIE) != 0U))
- 800263c:	69bb      	ldr	r3, [r7, #24]
- 800263e:	f003 0320 	and.w	r3, r3, #32
- 8002642:	2b00      	cmp	r3, #0
- 8002644:	d009      	beq.n	800265a <HAL_UART_IRQHandler+0x56>
+ 8002e70:	69bb      	ldr	r3, [r7, #24]
+ 8002e72:	f003 0320 	and.w	r3, r3, #32
+ 8002e76:	2b00      	cmp	r3, #0
+ 8002e78:	d009      	beq.n	8002e8e <HAL_UART_IRQHandler+0x56>
     {
       if (huart->RxISR != NULL)
- 8002646:	687b      	ldr	r3, [r7, #4]
- 8002648:	6e1b      	ldr	r3, [r3, #96]	; 0x60
- 800264a:	2b00      	cmp	r3, #0
- 800264c:	f000 80eb 	beq.w	8002826 <HAL_UART_IRQHandler+0x222>
+ 8002e7a:	687b      	ldr	r3, [r7, #4]
+ 8002e7c:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 8002e7e:	2b00      	cmp	r3, #0
+ 8002e80:	f000 80eb 	beq.w	800305a <HAL_UART_IRQHandler+0x222>
       {
         huart->RxISR(huart);
- 8002650:	687b      	ldr	r3, [r7, #4]
- 8002652:	6e1b      	ldr	r3, [r3, #96]	; 0x60
- 8002654:	6878      	ldr	r0, [r7, #4]
- 8002656:	4798      	blx	r3
+ 8002e84:	687b      	ldr	r3, [r7, #4]
+ 8002e86:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 8002e88:	6878      	ldr	r0, [r7, #4]
+ 8002e8a:	4798      	blx	r3
       }
       return;
- 8002658:	e0e5      	b.n	8002826 <HAL_UART_IRQHandler+0x222>
+ 8002e8c:	e0e5      	b.n	800305a <HAL_UART_IRQHandler+0x222>
     }
   }
 
   /* If some errors occur */
   if ((errorflags != 0U)
- 800265a:	693b      	ldr	r3, [r7, #16]
- 800265c:	2b00      	cmp	r3, #0
- 800265e:	f000 80c0 	beq.w	80027e2 <HAL_UART_IRQHandler+0x1de>
+ 8002e8e:	693b      	ldr	r3, [r7, #16]
+ 8002e90:	2b00      	cmp	r3, #0
+ 8002e92:	f000 80c0 	beq.w	8003016 <HAL_UART_IRQHandler+0x1de>
       && (((cr3its & USART_CR3_EIE) != 0U)
- 8002662:	697b      	ldr	r3, [r7, #20]
- 8002664:	f003 0301 	and.w	r3, r3, #1
- 8002668:	2b00      	cmp	r3, #0
- 800266a:	d105      	bne.n	8002678 <HAL_UART_IRQHandler+0x74>
+ 8002e96:	697b      	ldr	r3, [r7, #20]
+ 8002e98:	f003 0301 	and.w	r3, r3, #1
+ 8002e9c:	2b00      	cmp	r3, #0
+ 8002e9e:	d105      	bne.n	8002eac <HAL_UART_IRQHandler+0x74>
           || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
- 800266c:	69bb      	ldr	r3, [r7, #24]
- 800266e:	f403 7390 	and.w	r3, r3, #288	; 0x120
- 8002672:	2b00      	cmp	r3, #0
- 8002674:	f000 80b5 	beq.w	80027e2 <HAL_UART_IRQHandler+0x1de>
+ 8002ea0:	69bb      	ldr	r3, [r7, #24]
+ 8002ea2:	f403 7390 	and.w	r3, r3, #288	; 0x120
+ 8002ea6:	2b00      	cmp	r3, #0
+ 8002ea8:	f000 80b5 	beq.w	8003016 <HAL_UART_IRQHandler+0x1de>
   {
     /* UART parity error interrupt occurred -------------------------------------*/
     if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
- 8002678:	69fb      	ldr	r3, [r7, #28]
- 800267a:	f003 0301 	and.w	r3, r3, #1
- 800267e:	2b00      	cmp	r3, #0
- 8002680:	d00e      	beq.n	80026a0 <HAL_UART_IRQHandler+0x9c>
- 8002682:	69bb      	ldr	r3, [r7, #24]
- 8002684:	f403 7380 	and.w	r3, r3, #256	; 0x100
- 8002688:	2b00      	cmp	r3, #0
- 800268a:	d009      	beq.n	80026a0 <HAL_UART_IRQHandler+0x9c>
+ 8002eac:	69fb      	ldr	r3, [r7, #28]
+ 8002eae:	f003 0301 	and.w	r3, r3, #1
+ 8002eb2:	2b00      	cmp	r3, #0
+ 8002eb4:	d00e      	beq.n	8002ed4 <HAL_UART_IRQHandler+0x9c>
+ 8002eb6:	69bb      	ldr	r3, [r7, #24]
+ 8002eb8:	f403 7380 	and.w	r3, r3, #256	; 0x100
+ 8002ebc:	2b00      	cmp	r3, #0
+ 8002ebe:	d009      	beq.n	8002ed4 <HAL_UART_IRQHandler+0x9c>
     {
       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
- 800268c:	687b      	ldr	r3, [r7, #4]
- 800268e:	681b      	ldr	r3, [r3, #0]
- 8002690:	2201      	movs	r2, #1
- 8002692:	621a      	str	r2, [r3, #32]
+ 8002ec0:	687b      	ldr	r3, [r7, #4]
+ 8002ec2:	681b      	ldr	r3, [r3, #0]
+ 8002ec4:	2201      	movs	r2, #1
+ 8002ec6:	621a      	str	r2, [r3, #32]
 
       huart->ErrorCode |= HAL_UART_ERROR_PE;
- 8002694:	687b      	ldr	r3, [r7, #4]
- 8002696:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
- 8002698:	f043 0201 	orr.w	r2, r3, #1
- 800269c:	687b      	ldr	r3, [r7, #4]
- 800269e:	67da      	str	r2, [r3, #124]	; 0x7c
+ 8002ec8:	687b      	ldr	r3, [r7, #4]
+ 8002eca:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
+ 8002ecc:	f043 0201 	orr.w	r2, r3, #1
+ 8002ed0:	687b      	ldr	r3, [r7, #4]
+ 8002ed2:	67da      	str	r2, [r3, #124]	; 0x7c
     }
 
     /* UART frame error interrupt occurred --------------------------------------*/
     if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
- 80026a0:	69fb      	ldr	r3, [r7, #28]
- 80026a2:	f003 0302 	and.w	r3, r3, #2
- 80026a6:	2b00      	cmp	r3, #0
- 80026a8:	d00e      	beq.n	80026c8 <HAL_UART_IRQHandler+0xc4>
- 80026aa:	697b      	ldr	r3, [r7, #20]
- 80026ac:	f003 0301 	and.w	r3, r3, #1
- 80026b0:	2b00      	cmp	r3, #0
- 80026b2:	d009      	beq.n	80026c8 <HAL_UART_IRQHandler+0xc4>
+ 8002ed4:	69fb      	ldr	r3, [r7, #28]
+ 8002ed6:	f003 0302 	and.w	r3, r3, #2
+ 8002eda:	2b00      	cmp	r3, #0
+ 8002edc:	d00e      	beq.n	8002efc <HAL_UART_IRQHandler+0xc4>
+ 8002ede:	697b      	ldr	r3, [r7, #20]
+ 8002ee0:	f003 0301 	and.w	r3, r3, #1
+ 8002ee4:	2b00      	cmp	r3, #0
+ 8002ee6:	d009      	beq.n	8002efc <HAL_UART_IRQHandler+0xc4>
     {
       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
- 80026b4:	687b      	ldr	r3, [r7, #4]
- 80026b6:	681b      	ldr	r3, [r3, #0]
- 80026b8:	2202      	movs	r2, #2
- 80026ba:	621a      	str	r2, [r3, #32]
+ 8002ee8:	687b      	ldr	r3, [r7, #4]
+ 8002eea:	681b      	ldr	r3, [r3, #0]
+ 8002eec:	2202      	movs	r2, #2
+ 8002eee:	621a      	str	r2, [r3, #32]
 
       huart->ErrorCode |= HAL_UART_ERROR_FE;
- 80026bc:	687b      	ldr	r3, [r7, #4]
- 80026be:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
- 80026c0:	f043 0204 	orr.w	r2, r3, #4
- 80026c4:	687b      	ldr	r3, [r7, #4]
- 80026c6:	67da      	str	r2, [r3, #124]	; 0x7c
+ 8002ef0:	687b      	ldr	r3, [r7, #4]
+ 8002ef2:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
+ 8002ef4:	f043 0204 	orr.w	r2, r3, #4
+ 8002ef8:	687b      	ldr	r3, [r7, #4]
+ 8002efa:	67da      	str	r2, [r3, #124]	; 0x7c
     }
 
     /* UART noise error interrupt occurred --------------------------------------*/
     if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
- 80026c8:	69fb      	ldr	r3, [r7, #28]
- 80026ca:	f003 0304 	and.w	r3, r3, #4
- 80026ce:	2b00      	cmp	r3, #0
- 80026d0:	d00e      	beq.n	80026f0 <HAL_UART_IRQHandler+0xec>
- 80026d2:	697b      	ldr	r3, [r7, #20]
- 80026d4:	f003 0301 	and.w	r3, r3, #1
- 80026d8:	2b00      	cmp	r3, #0
- 80026da:	d009      	beq.n	80026f0 <HAL_UART_IRQHandler+0xec>
+ 8002efc:	69fb      	ldr	r3, [r7, #28]
+ 8002efe:	f003 0304 	and.w	r3, r3, #4
+ 8002f02:	2b00      	cmp	r3, #0
+ 8002f04:	d00e      	beq.n	8002f24 <HAL_UART_IRQHandler+0xec>
+ 8002f06:	697b      	ldr	r3, [r7, #20]
+ 8002f08:	f003 0301 	and.w	r3, r3, #1
+ 8002f0c:	2b00      	cmp	r3, #0
+ 8002f0e:	d009      	beq.n	8002f24 <HAL_UART_IRQHandler+0xec>
     {
       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
- 80026dc:	687b      	ldr	r3, [r7, #4]
- 80026de:	681b      	ldr	r3, [r3, #0]
- 80026e0:	2204      	movs	r2, #4
- 80026e2:	621a      	str	r2, [r3, #32]
+ 8002f10:	687b      	ldr	r3, [r7, #4]
+ 8002f12:	681b      	ldr	r3, [r3, #0]
+ 8002f14:	2204      	movs	r2, #4
+ 8002f16:	621a      	str	r2, [r3, #32]
 
       huart->ErrorCode |= HAL_UART_ERROR_NE;
- 80026e4:	687b      	ldr	r3, [r7, #4]
- 80026e6:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
- 80026e8:	f043 0202 	orr.w	r2, r3, #2
- 80026ec:	687b      	ldr	r3, [r7, #4]
- 80026ee:	67da      	str	r2, [r3, #124]	; 0x7c
+ 8002f18:	687b      	ldr	r3, [r7, #4]
+ 8002f1a:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
+ 8002f1c:	f043 0202 	orr.w	r2, r3, #2
+ 8002f20:	687b      	ldr	r3, [r7, #4]
+ 8002f22:	67da      	str	r2, [r3, #124]	; 0x7c
     }
 
     /* UART Over-Run interrupt occurred -----------------------------------------*/
     if (((isrflags & USART_ISR_ORE) != 0U)
- 80026f0:	69fb      	ldr	r3, [r7, #28]
- 80026f2:	f003 0308 	and.w	r3, r3, #8
- 80026f6:	2b00      	cmp	r3, #0
- 80026f8:	d013      	beq.n	8002722 <HAL_UART_IRQHandler+0x11e>
+ 8002f24:	69fb      	ldr	r3, [r7, #28]
+ 8002f26:	f003 0308 	and.w	r3, r3, #8
+ 8002f2a:	2b00      	cmp	r3, #0
+ 8002f2c:	d013      	beq.n	8002f56 <HAL_UART_IRQHandler+0x11e>
         && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
- 80026fa:	69bb      	ldr	r3, [r7, #24]
- 80026fc:	f003 0320 	and.w	r3, r3, #32
- 8002700:	2b00      	cmp	r3, #0
- 8002702:	d104      	bne.n	800270e <HAL_UART_IRQHandler+0x10a>
+ 8002f2e:	69bb      	ldr	r3, [r7, #24]
+ 8002f30:	f003 0320 	and.w	r3, r3, #32
+ 8002f34:	2b00      	cmp	r3, #0
+ 8002f36:	d104      	bne.n	8002f42 <HAL_UART_IRQHandler+0x10a>
             ((cr3its & USART_CR3_EIE) != 0U)))
- 8002704:	697b      	ldr	r3, [r7, #20]
- 8002706:	f003 0301 	and.w	r3, r3, #1
+ 8002f38:	697b      	ldr	r3, [r7, #20]
+ 8002f3a:	f003 0301 	and.w	r3, r3, #1
         && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
- 800270a:	2b00      	cmp	r3, #0
- 800270c:	d009      	beq.n	8002722 <HAL_UART_IRQHandler+0x11e>
+ 8002f3e:	2b00      	cmp	r3, #0
+ 8002f40:	d009      	beq.n	8002f56 <HAL_UART_IRQHandler+0x11e>
     {
       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
- 800270e:	687b      	ldr	r3, [r7, #4]
- 8002710:	681b      	ldr	r3, [r3, #0]
- 8002712:	2208      	movs	r2, #8
- 8002714:	621a      	str	r2, [r3, #32]
+ 8002f42:	687b      	ldr	r3, [r7, #4]
+ 8002f44:	681b      	ldr	r3, [r3, #0]
+ 8002f46:	2208      	movs	r2, #8
+ 8002f48:	621a      	str	r2, [r3, #32]
 
       huart->ErrorCode |= HAL_UART_ERROR_ORE;
- 8002716:	687b      	ldr	r3, [r7, #4]
- 8002718:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
- 800271a:	f043 0208 	orr.w	r2, r3, #8
- 800271e:	687b      	ldr	r3, [r7, #4]
- 8002720:	67da      	str	r2, [r3, #124]	; 0x7c
+ 8002f4a:	687b      	ldr	r3, [r7, #4]
+ 8002f4c:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
+ 8002f4e:	f043 0208 	orr.w	r2, r3, #8
+ 8002f52:	687b      	ldr	r3, [r7, #4]
+ 8002f54:	67da      	str	r2, [r3, #124]	; 0x7c
     }
 
     /* Call UART Error Call back function if need be --------------------------*/
     if (huart->ErrorCode != HAL_UART_ERROR_NONE)
- 8002722:	687b      	ldr	r3, [r7, #4]
- 8002724:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
- 8002726:	2b00      	cmp	r3, #0
- 8002728:	d07f      	beq.n	800282a <HAL_UART_IRQHandler+0x226>
+ 8002f56:	687b      	ldr	r3, [r7, #4]
+ 8002f58:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
+ 8002f5a:	2b00      	cmp	r3, #0
+ 8002f5c:	d07f      	beq.n	800305e <HAL_UART_IRQHandler+0x226>
     {
       /* UART in mode Receiver ---------------------------------------------------*/
       if (((isrflags & USART_ISR_RXNE) != 0U)
- 800272a:	69fb      	ldr	r3, [r7, #28]
- 800272c:	f003 0320 	and.w	r3, r3, #32
- 8002730:	2b00      	cmp	r3, #0
- 8002732:	d00c      	beq.n	800274e <HAL_UART_IRQHandler+0x14a>
+ 8002f5e:	69fb      	ldr	r3, [r7, #28]
+ 8002f60:	f003 0320 	and.w	r3, r3, #32
+ 8002f64:	2b00      	cmp	r3, #0
+ 8002f66:	d00c      	beq.n	8002f82 <HAL_UART_IRQHandler+0x14a>
           && ((cr1its & USART_CR1_RXNEIE) != 0U))
- 8002734:	69bb      	ldr	r3, [r7, #24]
- 8002736:	f003 0320 	and.w	r3, r3, #32
- 800273a:	2b00      	cmp	r3, #0
- 800273c:	d007      	beq.n	800274e <HAL_UART_IRQHandler+0x14a>
+ 8002f68:	69bb      	ldr	r3, [r7, #24]
+ 8002f6a:	f003 0320 	and.w	r3, r3, #32
+ 8002f6e:	2b00      	cmp	r3, #0
+ 8002f70:	d007      	beq.n	8002f82 <HAL_UART_IRQHandler+0x14a>
       {
         if (huart->RxISR != NULL)
- 800273e:	687b      	ldr	r3, [r7, #4]
- 8002740:	6e1b      	ldr	r3, [r3, #96]	; 0x60
- 8002742:	2b00      	cmp	r3, #0
- 8002744:	d003      	beq.n	800274e <HAL_UART_IRQHandler+0x14a>
+ 8002f72:	687b      	ldr	r3, [r7, #4]
+ 8002f74:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 8002f76:	2b00      	cmp	r3, #0
+ 8002f78:	d003      	beq.n	8002f82 <HAL_UART_IRQHandler+0x14a>
         {
           huart->RxISR(huart);
- 8002746:	687b      	ldr	r3, [r7, #4]
- 8002748:	6e1b      	ldr	r3, [r3, #96]	; 0x60
- 800274a:	6878      	ldr	r0, [r7, #4]
- 800274c:	4798      	blx	r3
+ 8002f7a:	687b      	ldr	r3, [r7, #4]
+ 8002f7c:	6e1b      	ldr	r3, [r3, #96]	; 0x60
+ 8002f7e:	6878      	ldr	r0, [r7, #4]
+ 8002f80:	4798      	blx	r3
         }
       }
 
       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
          consider error as blocking */
       errorcode = huart->ErrorCode;
- 800274e:	687b      	ldr	r3, [r7, #4]
- 8002750:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
- 8002752:	60fb      	str	r3, [r7, #12]
+ 8002f82:	687b      	ldr	r3, [r7, #4]
+ 8002f84:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
+ 8002f86:	60fb      	str	r3, [r7, #12]
       if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
- 8002754:	687b      	ldr	r3, [r7, #4]
- 8002756:	681b      	ldr	r3, [r3, #0]
- 8002758:	689b      	ldr	r3, [r3, #8]
- 800275a:	f003 0340 	and.w	r3, r3, #64	; 0x40
- 800275e:	2b40      	cmp	r3, #64	; 0x40
- 8002760:	d004      	beq.n	800276c <HAL_UART_IRQHandler+0x168>
+ 8002f88:	687b      	ldr	r3, [r7, #4]
+ 8002f8a:	681b      	ldr	r3, [r3, #0]
+ 8002f8c:	689b      	ldr	r3, [r3, #8]
+ 8002f8e:	f003 0340 	and.w	r3, r3, #64	; 0x40
+ 8002f92:	2b40      	cmp	r3, #64	; 0x40
+ 8002f94:	d004      	beq.n	8002fa0 <HAL_UART_IRQHandler+0x168>
           ((errorcode & HAL_UART_ERROR_ORE) != 0U))
- 8002762:	68fb      	ldr	r3, [r7, #12]
- 8002764:	f003 0308 	and.w	r3, r3, #8
+ 8002f96:	68fb      	ldr	r3, [r7, #12]
+ 8002f98:	f003 0308 	and.w	r3, r3, #8
       if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
- 8002768:	2b00      	cmp	r3, #0
- 800276a:	d031      	beq.n	80027d0 <HAL_UART_IRQHandler+0x1cc>
+ 8002f9c:	2b00      	cmp	r3, #0
+ 8002f9e:	d031      	beq.n	8003004 <HAL_UART_IRQHandler+0x1cc>
       {
         /* Blocking error : transfer is aborted
            Set the UART state ready to be able to start again the process,
            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
         UART_EndRxTransfer(huart);
- 800276c:	6878      	ldr	r0, [r7, #4]
- 800276e:	f000 fc36 	bl	8002fde <UART_EndRxTransfer>
+ 8002fa0:	6878      	ldr	r0, [r7, #4]
+ 8002fa2:	f000 fc36 	bl	8003812 <UART_EndRxTransfer>
 
         /* Disable the UART DMA Rx request if enabled */
         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8002772:	687b      	ldr	r3, [r7, #4]
- 8002774:	681b      	ldr	r3, [r3, #0]
- 8002776:	689b      	ldr	r3, [r3, #8]
- 8002778:	f003 0340 	and.w	r3, r3, #64	; 0x40
- 800277c:	2b40      	cmp	r3, #64	; 0x40
- 800277e:	d123      	bne.n	80027c8 <HAL_UART_IRQHandler+0x1c4>
+ 8002fa6:	687b      	ldr	r3, [r7, #4]
+ 8002fa8:	681b      	ldr	r3, [r3, #0]
+ 8002faa:	689b      	ldr	r3, [r3, #8]
+ 8002fac:	f003 0340 	and.w	r3, r3, #64	; 0x40
+ 8002fb0:	2b40      	cmp	r3, #64	; 0x40
+ 8002fb2:	d123      	bne.n	8002ffc <HAL_UART_IRQHandler+0x1c4>
         {
           CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- 8002780:	687b      	ldr	r3, [r7, #4]
- 8002782:	681b      	ldr	r3, [r3, #0]
- 8002784:	689a      	ldr	r2, [r3, #8]
- 8002786:	687b      	ldr	r3, [r7, #4]
- 8002788:	681b      	ldr	r3, [r3, #0]
- 800278a:	f022 0240 	bic.w	r2, r2, #64	; 0x40
- 800278e:	609a      	str	r2, [r3, #8]
+ 8002fb4:	687b      	ldr	r3, [r7, #4]
+ 8002fb6:	681b      	ldr	r3, [r3, #0]
+ 8002fb8:	689a      	ldr	r2, [r3, #8]
+ 8002fba:	687b      	ldr	r3, [r7, #4]
+ 8002fbc:	681b      	ldr	r3, [r3, #0]
+ 8002fbe:	f022 0240 	bic.w	r2, r2, #64	; 0x40
+ 8002fc2:	609a      	str	r2, [r3, #8]
 
           /* Abort the UART DMA Rx channel */
           if (huart->hdmarx != NULL)
- 8002790:	687b      	ldr	r3, [r7, #4]
- 8002792:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 8002794:	2b00      	cmp	r3, #0
- 8002796:	d013      	beq.n	80027c0 <HAL_UART_IRQHandler+0x1bc>
+ 8002fc4:	687b      	ldr	r3, [r7, #4]
+ 8002fc6:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 8002fc8:	2b00      	cmp	r3, #0
+ 8002fca:	d013      	beq.n	8002ff4 <HAL_UART_IRQHandler+0x1bc>
           {
             /* Set the UART DMA Abort callback :
                will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
             huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
- 8002798:	687b      	ldr	r3, [r7, #4]
- 800279a:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 800279c:	4a26      	ldr	r2, [pc, #152]	; (8002838 <HAL_UART_IRQHandler+0x234>)
- 800279e:	651a      	str	r2, [r3, #80]	; 0x50
+ 8002fcc:	687b      	ldr	r3, [r7, #4]
+ 8002fce:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 8002fd0:	4a26      	ldr	r2, [pc, #152]	; (800306c <HAL_UART_IRQHandler+0x234>)
+ 8002fd2:	651a      	str	r2, [r3, #80]	; 0x50
 
             /* Abort DMA RX */
             if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
- 80027a0:	687b      	ldr	r3, [r7, #4]
- 80027a2:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 80027a4:	4618      	mov	r0, r3
- 80027a6:	f7fe f8e5 	bl	8000974 <HAL_DMA_Abort_IT>
- 80027aa:	4603      	mov	r3, r0
- 80027ac:	2b00      	cmp	r3, #0
- 80027ae:	d016      	beq.n	80027de <HAL_UART_IRQHandler+0x1da>
+ 8002fd4:	687b      	ldr	r3, [r7, #4]
+ 8002fd6:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 8002fd8:	4618      	mov	r0, r3
+ 8002fda:	f7fd fccb 	bl	8000974 <HAL_DMA_Abort_IT>
+ 8002fde:	4603      	mov	r3, r0
+ 8002fe0:	2b00      	cmp	r3, #0
+ 8002fe2:	d016      	beq.n	8003012 <HAL_UART_IRQHandler+0x1da>
             {
               /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
               huart->hdmarx->XferAbortCallback(huart->hdmarx);
- 80027b0:	687b      	ldr	r3, [r7, #4]
- 80027b2:	6edb      	ldr	r3, [r3, #108]	; 0x6c
- 80027b4:	6d1b      	ldr	r3, [r3, #80]	; 0x50
- 80027b6:	687a      	ldr	r2, [r7, #4]
- 80027b8:	6ed2      	ldr	r2, [r2, #108]	; 0x6c
- 80027ba:	4610      	mov	r0, r2
- 80027bc:	4798      	blx	r3
+ 8002fe4:	687b      	ldr	r3, [r7, #4]
+ 8002fe6:	6edb      	ldr	r3, [r3, #108]	; 0x6c
+ 8002fe8:	6d1b      	ldr	r3, [r3, #80]	; 0x50
+ 8002fea:	687a      	ldr	r2, [r7, #4]
+ 8002fec:	6ed2      	ldr	r2, [r2, #108]	; 0x6c
+ 8002fee:	4610      	mov	r0, r2
+ 8002ff0:	4798      	blx	r3
         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 80027be:	e00e      	b.n	80027de <HAL_UART_IRQHandler+0x1da>
+ 8002ff2:	e00e      	b.n	8003012 <HAL_UART_IRQHandler+0x1da>
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
             /*Call registered error callback*/
             huart->ErrorCallback(huart);
 #else
             /*Call legacy weak error callback*/
             HAL_UART_ErrorCallback(huart);
- 80027c0:	6878      	ldr	r0, [r7, #4]
- 80027c2:	f000 f845 	bl	8002850 <HAL_UART_ErrorCallback>
+ 8002ff4:	6878      	ldr	r0, [r7, #4]
+ 8002ff6:	f000 f845 	bl	8003084 <HAL_UART_ErrorCallback>
         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 80027c6:	e00a      	b.n	80027de <HAL_UART_IRQHandler+0x1da>
+ 8002ffa:	e00a      	b.n	8003012 <HAL_UART_IRQHandler+0x1da>
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
           /*Call registered error callback*/
           huart->ErrorCallback(huart);
 #else
           /*Call legacy weak error callback*/
           HAL_UART_ErrorCallback(huart);
- 80027c8:	6878      	ldr	r0, [r7, #4]
- 80027ca:	f000 f841 	bl	8002850 <HAL_UART_ErrorCallback>
+ 8002ffc:	6878      	ldr	r0, [r7, #4]
+ 8002ffe:	f000 f841 	bl	8003084 <HAL_UART_ErrorCallback>
         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 80027ce:	e006      	b.n	80027de <HAL_UART_IRQHandler+0x1da>
+ 8003002:	e006      	b.n	8003012 <HAL_UART_IRQHandler+0x1da>
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
         /*Call registered error callback*/
         huart->ErrorCallback(huart);
 #else
         /*Call legacy weak error callback*/
         HAL_UART_ErrorCallback(huart);
- 80027d0:	6878      	ldr	r0, [r7, #4]
- 80027d2:	f000 f83d 	bl	8002850 <HAL_UART_ErrorCallback>
+ 8003004:	6878      	ldr	r0, [r7, #4]
+ 8003006:	f000 f83d 	bl	8003084 <HAL_UART_ErrorCallback>
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
         huart->ErrorCode = HAL_UART_ERROR_NONE;
- 80027d6:	687b      	ldr	r3, [r7, #4]
- 80027d8:	2200      	movs	r2, #0
- 80027da:	67da      	str	r2, [r3, #124]	; 0x7c
+ 800300a:	687b      	ldr	r3, [r7, #4]
+ 800300c:	2200      	movs	r2, #0
+ 800300e:	67da      	str	r2, [r3, #124]	; 0x7c
       }
     }
     return;
- 80027dc:	e025      	b.n	800282a <HAL_UART_IRQHandler+0x226>
+ 8003010:	e025      	b.n	800305e <HAL_UART_IRQHandler+0x226>
         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 80027de:	bf00      	nop
+ 8003012:	bf00      	nop
     return;
- 80027e0:	e023      	b.n	800282a <HAL_UART_IRQHandler+0x226>
+ 8003014:	e023      	b.n	800305e <HAL_UART_IRQHandler+0x226>
 
   } /* End if some error occurs */
 
   /* UART in mode Transmitter ------------------------------------------------*/
   if (((isrflags & USART_ISR_TXE) != 0U)
- 80027e2:	69fb      	ldr	r3, [r7, #28]
- 80027e4:	f003 0380 	and.w	r3, r3, #128	; 0x80
- 80027e8:	2b00      	cmp	r3, #0
- 80027ea:	d00d      	beq.n	8002808 <HAL_UART_IRQHandler+0x204>
+ 8003016:	69fb      	ldr	r3, [r7, #28]
+ 8003018:	f003 0380 	and.w	r3, r3, #128	; 0x80
+ 800301c:	2b00      	cmp	r3, #0
+ 800301e:	d00d      	beq.n	800303c <HAL_UART_IRQHandler+0x204>
       && ((cr1its & USART_CR1_TXEIE) != 0U))
- 80027ec:	69bb      	ldr	r3, [r7, #24]
- 80027ee:	f003 0380 	and.w	r3, r3, #128	; 0x80
- 80027f2:	2b00      	cmp	r3, #0
- 80027f4:	d008      	beq.n	8002808 <HAL_UART_IRQHandler+0x204>
+ 8003020:	69bb      	ldr	r3, [r7, #24]
+ 8003022:	f003 0380 	and.w	r3, r3, #128	; 0x80
+ 8003026:	2b00      	cmp	r3, #0
+ 8003028:	d008      	beq.n	800303c <HAL_UART_IRQHandler+0x204>
   {
     if (huart->TxISR != NULL)
- 80027f6:	687b      	ldr	r3, [r7, #4]
- 80027f8:	6e5b      	ldr	r3, [r3, #100]	; 0x64
- 80027fa:	2b00      	cmp	r3, #0
- 80027fc:	d017      	beq.n	800282e <HAL_UART_IRQHandler+0x22a>
+ 800302a:	687b      	ldr	r3, [r7, #4]
+ 800302c:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 800302e:	2b00      	cmp	r3, #0
+ 8003030:	d017      	beq.n	8003062 <HAL_UART_IRQHandler+0x22a>
     {
       huart->TxISR(huart);
- 80027fe:	687b      	ldr	r3, [r7, #4]
- 8002800:	6e5b      	ldr	r3, [r3, #100]	; 0x64
- 8002802:	6878      	ldr	r0, [r7, #4]
- 8002804:	4798      	blx	r3
+ 8003032:	687b      	ldr	r3, [r7, #4]
+ 8003034:	6e5b      	ldr	r3, [r3, #100]	; 0x64
+ 8003036:	6878      	ldr	r0, [r7, #4]
+ 8003038:	4798      	blx	r3
     }
     return;
- 8002806:	e012      	b.n	800282e <HAL_UART_IRQHandler+0x22a>
+ 800303a:	e012      	b.n	8003062 <HAL_UART_IRQHandler+0x22a>
   }
 
   /* UART in mode Transmitter (transmission end) -----------------------------*/
   if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
- 8002808:	69fb      	ldr	r3, [r7, #28]
- 800280a:	f003 0340 	and.w	r3, r3, #64	; 0x40
- 800280e:	2b00      	cmp	r3, #0
- 8002810:	d00e      	beq.n	8002830 <HAL_UART_IRQHandler+0x22c>
- 8002812:	69bb      	ldr	r3, [r7, #24]
- 8002814:	f003 0340 	and.w	r3, r3, #64	; 0x40
- 8002818:	2b00      	cmp	r3, #0
- 800281a:	d009      	beq.n	8002830 <HAL_UART_IRQHandler+0x22c>
+ 800303c:	69fb      	ldr	r3, [r7, #28]
+ 800303e:	f003 0340 	and.w	r3, r3, #64	; 0x40
+ 8003042:	2b00      	cmp	r3, #0
+ 8003044:	d00e      	beq.n	8003064 <HAL_UART_IRQHandler+0x22c>
+ 8003046:	69bb      	ldr	r3, [r7, #24]
+ 8003048:	f003 0340 	and.w	r3, r3, #64	; 0x40
+ 800304c:	2b00      	cmp	r3, #0
+ 800304e:	d009      	beq.n	8003064 <HAL_UART_IRQHandler+0x22c>
   {
     UART_EndTransmit_IT(huart);
- 800281c:	6878      	ldr	r0, [r7, #4]
- 800281e:	f000 fc14 	bl	800304a <UART_EndTransmit_IT>
+ 8003050:	6878      	ldr	r0, [r7, #4]
+ 8003052:	f000 fc14 	bl	800387e <UART_EndTransmit_IT>
     return;
- 8002822:	bf00      	nop
- 8002824:	e004      	b.n	8002830 <HAL_UART_IRQHandler+0x22c>
+ 8003056:	bf00      	nop
+ 8003058:	e004      	b.n	8003064 <HAL_UART_IRQHandler+0x22c>
       return;
- 8002826:	bf00      	nop
- 8002828:	e002      	b.n	8002830 <HAL_UART_IRQHandler+0x22c>
+ 800305a:	bf00      	nop
+ 800305c:	e002      	b.n	8003064 <HAL_UART_IRQHandler+0x22c>
     return;
- 800282a:	bf00      	nop
- 800282c:	e000      	b.n	8002830 <HAL_UART_IRQHandler+0x22c>
+ 800305e:	bf00      	nop
+ 8003060:	e000      	b.n	8003064 <HAL_UART_IRQHandler+0x22c>
     return;
- 800282e:	bf00      	nop
+ 8003062:	bf00      	nop
   }
 
 }
- 8002830:	3720      	adds	r7, #32
- 8002832:	46bd      	mov	sp, r7
- 8002834:	bd80      	pop	{r7, pc}
- 8002836:	bf00      	nop
- 8002838:	0800301f 	.word	0x0800301f
+ 8003064:	3720      	adds	r7, #32
+ 8003066:	46bd      	mov	sp, r7
+ 8003068:	bd80      	pop	{r7, pc}
+ 800306a:	bf00      	nop
+ 800306c:	08003853 	.word	0x08003853
 
-0800283c <HAL_UART_TxCpltCallback>:
+08003070 <HAL_UART_TxCpltCallback>:
   * @brief Tx Transfer completed callback.
   * @param huart UART handle.
   * @retval None
   */
 __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
 {
- 800283c:	b480      	push	{r7}
- 800283e:	b083      	sub	sp, #12
- 8002840:	af00      	add	r7, sp, #0
- 8002842:	6078      	str	r0, [r7, #4]
+ 8003070:	b480      	push	{r7}
+ 8003072:	b083      	sub	sp, #12
+ 8003074:	af00      	add	r7, sp, #0
+ 8003076:	6078      	str	r0, [r7, #4]
   UNUSED(huart);
 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_UART_TxCpltCallback can be implemented in the user file.
    */
 }
- 8002844:	bf00      	nop
- 8002846:	370c      	adds	r7, #12
- 8002848:	46bd      	mov	sp, r7
- 800284a:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800284e:	4770      	bx	lr
+ 8003078:	bf00      	nop
+ 800307a:	370c      	adds	r7, #12
+ 800307c:	46bd      	mov	sp, r7
+ 800307e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8003082:	4770      	bx	lr
 
-08002850 <HAL_UART_ErrorCallback>:
+08003084 <HAL_UART_ErrorCallback>:
   * @brief  UART error callback.
   * @param  huart UART handle.
   * @retval None
   */
 __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
 {
- 8002850:	b480      	push	{r7}
- 8002852:	b083      	sub	sp, #12
- 8002854:	af00      	add	r7, sp, #0
- 8002856:	6078      	str	r0, [r7, #4]
+ 8003084:	b480      	push	{r7}
+ 8003086:	b083      	sub	sp, #12
+ 8003088:	af00      	add	r7, sp, #0
+ 800308a:	6078      	str	r0, [r7, #4]
   UNUSED(huart);
 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_UART_ErrorCallback can be implemented in the user file.
    */
 }
- 8002858:	bf00      	nop
- 800285a:	370c      	adds	r7, #12
- 800285c:	46bd      	mov	sp, r7
- 800285e:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8002862:	4770      	bx	lr
+ 800308c:	bf00      	nop
+ 800308e:	370c      	adds	r7, #12
+ 8003090:	46bd      	mov	sp, r7
+ 8003092:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8003096:	4770      	bx	lr
 
-08002864 <UART_SetConfig>:
+08003098 <UART_SetConfig>:
   * @brief Configure the UART peripheral.
   * @param huart UART handle.
   * @retval HAL status
   */
 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
 {
- 8002864:	b580      	push	{r7, lr}
- 8002866:	b088      	sub	sp, #32
- 8002868:	af00      	add	r7, sp, #0
- 800286a:	6078      	str	r0, [r7, #4]
+ 8003098:	b580      	push	{r7, lr}
+ 800309a:	b088      	sub	sp, #32
+ 800309c:	af00      	add	r7, sp, #0
+ 800309e:	6078      	str	r0, [r7, #4]
   uint32_t tmpreg;
   uint16_t brrtemp;
   UART_ClockSourceTypeDef clocksource;
   uint32_t usartdiv                   = 0x00000000U;
- 800286c:	2300      	movs	r3, #0
- 800286e:	61bb      	str	r3, [r7, #24]
+ 80030a0:	2300      	movs	r3, #0
+ 80030a2:	61bb      	str	r3, [r7, #24]
   HAL_StatusTypeDef ret               = HAL_OK;
- 8002870:	2300      	movs	r3, #0
- 8002872:	75fb      	strb	r3, [r7, #23]
+ 80030a4:	2300      	movs	r3, #0
+ 80030a6:	75fb      	strb	r3, [r7, #23]
   *  the UART Word Length, Parity, Mode and oversampling:
   *  set the M bits according to huart->Init.WordLength value
   *  set PCE and PS bits according to huart->Init.Parity value
   *  set TE and RE bits according to huart->Init.Mode value
   *  set OVER8 bit according to huart->Init.OverSampling value */
   tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
- 8002874:	687b      	ldr	r3, [r7, #4]
- 8002876:	689a      	ldr	r2, [r3, #8]
- 8002878:	687b      	ldr	r3, [r7, #4]
- 800287a:	691b      	ldr	r3, [r3, #16]
- 800287c:	431a      	orrs	r2, r3
- 800287e:	687b      	ldr	r3, [r7, #4]
- 8002880:	695b      	ldr	r3, [r3, #20]
- 8002882:	431a      	orrs	r2, r3
- 8002884:	687b      	ldr	r3, [r7, #4]
- 8002886:	69db      	ldr	r3, [r3, #28]
- 8002888:	4313      	orrs	r3, r2
- 800288a:	613b      	str	r3, [r7, #16]
+ 80030a8:	687b      	ldr	r3, [r7, #4]
+ 80030aa:	689a      	ldr	r2, [r3, #8]
+ 80030ac:	687b      	ldr	r3, [r7, #4]
+ 80030ae:	691b      	ldr	r3, [r3, #16]
+ 80030b0:	431a      	orrs	r2, r3
+ 80030b2:	687b      	ldr	r3, [r7, #4]
+ 80030b4:	695b      	ldr	r3, [r3, #20]
+ 80030b6:	431a      	orrs	r2, r3
+ 80030b8:	687b      	ldr	r3, [r7, #4]
+ 80030ba:	69db      	ldr	r3, [r3, #28]
+ 80030bc:	4313      	orrs	r3, r2
+ 80030be:	613b      	str	r3, [r7, #16]
   MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
- 800288c:	687b      	ldr	r3, [r7, #4]
- 800288e:	681b      	ldr	r3, [r3, #0]
- 8002890:	681a      	ldr	r2, [r3, #0]
- 8002892:	4bb1      	ldr	r3, [pc, #708]	; (8002b58 <UART_SetConfig+0x2f4>)
- 8002894:	4013      	ands	r3, r2
- 8002896:	687a      	ldr	r2, [r7, #4]
- 8002898:	6812      	ldr	r2, [r2, #0]
- 800289a:	6939      	ldr	r1, [r7, #16]
- 800289c:	430b      	orrs	r3, r1
- 800289e:	6013      	str	r3, [r2, #0]
+ 80030c0:	687b      	ldr	r3, [r7, #4]
+ 80030c2:	681b      	ldr	r3, [r3, #0]
+ 80030c4:	681a      	ldr	r2, [r3, #0]
+ 80030c6:	4bb1      	ldr	r3, [pc, #708]	; (800338c <UART_SetConfig+0x2f4>)
+ 80030c8:	4013      	ands	r3, r2
+ 80030ca:	687a      	ldr	r2, [r7, #4]
+ 80030cc:	6812      	ldr	r2, [r2, #0]
+ 80030ce:	6939      	ldr	r1, [r7, #16]
+ 80030d0:	430b      	orrs	r3, r1
+ 80030d2:	6013      	str	r3, [r2, #0]
 
   /*-------------------------- USART CR2 Configuration -----------------------*/
   /* Configure the UART Stop Bits: Set STOP[13:12] bits according
   * to huart->Init.StopBits value */
   MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
- 80028a0:	687b      	ldr	r3, [r7, #4]
- 80028a2:	681b      	ldr	r3, [r3, #0]
- 80028a4:	685b      	ldr	r3, [r3, #4]
- 80028a6:	f423 5140 	bic.w	r1, r3, #12288	; 0x3000
- 80028aa:	687b      	ldr	r3, [r7, #4]
- 80028ac:	68da      	ldr	r2, [r3, #12]
- 80028ae:	687b      	ldr	r3, [r7, #4]
- 80028b0:	681b      	ldr	r3, [r3, #0]
- 80028b2:	430a      	orrs	r2, r1
- 80028b4:	605a      	str	r2, [r3, #4]
+ 80030d4:	687b      	ldr	r3, [r7, #4]
+ 80030d6:	681b      	ldr	r3, [r3, #0]
+ 80030d8:	685b      	ldr	r3, [r3, #4]
+ 80030da:	f423 5140 	bic.w	r1, r3, #12288	; 0x3000
+ 80030de:	687b      	ldr	r3, [r7, #4]
+ 80030e0:	68da      	ldr	r2, [r3, #12]
+ 80030e2:	687b      	ldr	r3, [r7, #4]
+ 80030e4:	681b      	ldr	r3, [r3, #0]
+ 80030e6:	430a      	orrs	r2, r1
+ 80030e8:	605a      	str	r2, [r3, #4]
   /* Configure
   * - UART HardWare Flow Control: set CTSE and RTSE bits according
   *   to huart->Init.HwFlowCtl value
   * - one-bit sampling method versus three samples' majority rule according
   *   to huart->Init.OneBitSampling (not applicable to LPUART) */
   tmpreg = (uint32_t)huart->Init.HwFlowCtl;
- 80028b6:	687b      	ldr	r3, [r7, #4]
- 80028b8:	699b      	ldr	r3, [r3, #24]
- 80028ba:	613b      	str	r3, [r7, #16]
+ 80030ea:	687b      	ldr	r3, [r7, #4]
+ 80030ec:	699b      	ldr	r3, [r3, #24]
+ 80030ee:	613b      	str	r3, [r7, #16]
 
   tmpreg |= huart->Init.OneBitSampling;
- 80028bc:	687b      	ldr	r3, [r7, #4]
- 80028be:	6a1b      	ldr	r3, [r3, #32]
- 80028c0:	693a      	ldr	r2, [r7, #16]
- 80028c2:	4313      	orrs	r3, r2
- 80028c4:	613b      	str	r3, [r7, #16]
+ 80030f0:	687b      	ldr	r3, [r7, #4]
+ 80030f2:	6a1b      	ldr	r3, [r3, #32]
+ 80030f4:	693a      	ldr	r2, [r7, #16]
+ 80030f6:	4313      	orrs	r3, r2
+ 80030f8:	613b      	str	r3, [r7, #16]
   MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
- 80028c6:	687b      	ldr	r3, [r7, #4]
- 80028c8:	681b      	ldr	r3, [r3, #0]
- 80028ca:	689b      	ldr	r3, [r3, #8]
- 80028cc:	f423 6130 	bic.w	r1, r3, #2816	; 0xb00
- 80028d0:	687b      	ldr	r3, [r7, #4]
- 80028d2:	681b      	ldr	r3, [r3, #0]
- 80028d4:	693a      	ldr	r2, [r7, #16]
- 80028d6:	430a      	orrs	r2, r1
- 80028d8:	609a      	str	r2, [r3, #8]
+ 80030fa:	687b      	ldr	r3, [r7, #4]
+ 80030fc:	681b      	ldr	r3, [r3, #0]
+ 80030fe:	689b      	ldr	r3, [r3, #8]
+ 8003100:	f423 6130 	bic.w	r1, r3, #2816	; 0xb00
+ 8003104:	687b      	ldr	r3, [r7, #4]
+ 8003106:	681b      	ldr	r3, [r3, #0]
+ 8003108:	693a      	ldr	r2, [r7, #16]
+ 800310a:	430a      	orrs	r2, r1
+ 800310c:	609a      	str	r2, [r3, #8]
 
 
   /*-------------------------- USART BRR Configuration -----------------------*/
   UART_GETCLOCKSOURCE(huart, clocksource);
- 80028da:	687b      	ldr	r3, [r7, #4]
- 80028dc:	681b      	ldr	r3, [r3, #0]
- 80028de:	4a9f      	ldr	r2, [pc, #636]	; (8002b5c <UART_SetConfig+0x2f8>)
- 80028e0:	4293      	cmp	r3, r2
- 80028e2:	d121      	bne.n	8002928 <UART_SetConfig+0xc4>
- 80028e4:	4b9e      	ldr	r3, [pc, #632]	; (8002b60 <UART_SetConfig+0x2fc>)
- 80028e6:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 80028ea:	f003 0303 	and.w	r3, r3, #3
- 80028ee:	2b03      	cmp	r3, #3
- 80028f0:	d816      	bhi.n	8002920 <UART_SetConfig+0xbc>
- 80028f2:	a201      	add	r2, pc, #4	; (adr r2, 80028f8 <UART_SetConfig+0x94>)
- 80028f4:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
- 80028f8:	08002909 	.word	0x08002909
- 80028fc:	08002915 	.word	0x08002915
- 8002900:	0800290f 	.word	0x0800290f
- 8002904:	0800291b 	.word	0x0800291b
- 8002908:	2301      	movs	r3, #1
- 800290a:	77fb      	strb	r3, [r7, #31]
- 800290c:	e151      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 800290e:	2302      	movs	r3, #2
- 8002910:	77fb      	strb	r3, [r7, #31]
- 8002912:	e14e      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002914:	2304      	movs	r3, #4
- 8002916:	77fb      	strb	r3, [r7, #31]
- 8002918:	e14b      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 800291a:	2308      	movs	r3, #8
- 800291c:	77fb      	strb	r3, [r7, #31]
- 800291e:	e148      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002920:	2310      	movs	r3, #16
- 8002922:	77fb      	strb	r3, [r7, #31]
- 8002924:	bf00      	nop
- 8002926:	e144      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002928:	687b      	ldr	r3, [r7, #4]
- 800292a:	681b      	ldr	r3, [r3, #0]
- 800292c:	4a8d      	ldr	r2, [pc, #564]	; (8002b64 <UART_SetConfig+0x300>)
- 800292e:	4293      	cmp	r3, r2
- 8002930:	d134      	bne.n	800299c <UART_SetConfig+0x138>
- 8002932:	4b8b      	ldr	r3, [pc, #556]	; (8002b60 <UART_SetConfig+0x2fc>)
- 8002934:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8002938:	f003 030c 	and.w	r3, r3, #12
- 800293c:	2b0c      	cmp	r3, #12
- 800293e:	d829      	bhi.n	8002994 <UART_SetConfig+0x130>
- 8002940:	a201      	add	r2, pc, #4	; (adr r2, 8002948 <UART_SetConfig+0xe4>)
- 8002942:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
- 8002946:	bf00      	nop
- 8002948:	0800297d 	.word	0x0800297d
- 800294c:	08002995 	.word	0x08002995
- 8002950:	08002995 	.word	0x08002995
- 8002954:	08002995 	.word	0x08002995
- 8002958:	08002989 	.word	0x08002989
- 800295c:	08002995 	.word	0x08002995
- 8002960:	08002995 	.word	0x08002995
- 8002964:	08002995 	.word	0x08002995
- 8002968:	08002983 	.word	0x08002983
- 800296c:	08002995 	.word	0x08002995
- 8002970:	08002995 	.word	0x08002995
- 8002974:	08002995 	.word	0x08002995
- 8002978:	0800298f 	.word	0x0800298f
- 800297c:	2300      	movs	r3, #0
- 800297e:	77fb      	strb	r3, [r7, #31]
- 8002980:	e117      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002982:	2302      	movs	r3, #2
- 8002984:	77fb      	strb	r3, [r7, #31]
- 8002986:	e114      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002988:	2304      	movs	r3, #4
- 800298a:	77fb      	strb	r3, [r7, #31]
- 800298c:	e111      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 800298e:	2308      	movs	r3, #8
- 8002990:	77fb      	strb	r3, [r7, #31]
- 8002992:	e10e      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002994:	2310      	movs	r3, #16
- 8002996:	77fb      	strb	r3, [r7, #31]
- 8002998:	bf00      	nop
- 800299a:	e10a      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 800299c:	687b      	ldr	r3, [r7, #4]
- 800299e:	681b      	ldr	r3, [r3, #0]
- 80029a0:	4a71      	ldr	r2, [pc, #452]	; (8002b68 <UART_SetConfig+0x304>)
- 80029a2:	4293      	cmp	r3, r2
- 80029a4:	d120      	bne.n	80029e8 <UART_SetConfig+0x184>
- 80029a6:	4b6e      	ldr	r3, [pc, #440]	; (8002b60 <UART_SetConfig+0x2fc>)
- 80029a8:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 80029ac:	f003 0330 	and.w	r3, r3, #48	; 0x30
- 80029b0:	2b10      	cmp	r3, #16
- 80029b2:	d00f      	beq.n	80029d4 <UART_SetConfig+0x170>
- 80029b4:	2b10      	cmp	r3, #16
- 80029b6:	d802      	bhi.n	80029be <UART_SetConfig+0x15a>
- 80029b8:	2b00      	cmp	r3, #0
- 80029ba:	d005      	beq.n	80029c8 <UART_SetConfig+0x164>
- 80029bc:	e010      	b.n	80029e0 <UART_SetConfig+0x17c>
- 80029be:	2b20      	cmp	r3, #32
- 80029c0:	d005      	beq.n	80029ce <UART_SetConfig+0x16a>
- 80029c2:	2b30      	cmp	r3, #48	; 0x30
- 80029c4:	d009      	beq.n	80029da <UART_SetConfig+0x176>
- 80029c6:	e00b      	b.n	80029e0 <UART_SetConfig+0x17c>
- 80029c8:	2300      	movs	r3, #0
- 80029ca:	77fb      	strb	r3, [r7, #31]
- 80029cc:	e0f1      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 80029ce:	2302      	movs	r3, #2
- 80029d0:	77fb      	strb	r3, [r7, #31]
- 80029d2:	e0ee      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 80029d4:	2304      	movs	r3, #4
- 80029d6:	77fb      	strb	r3, [r7, #31]
- 80029d8:	e0eb      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 80029da:	2308      	movs	r3, #8
- 80029dc:	77fb      	strb	r3, [r7, #31]
- 80029de:	e0e8      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 80029e0:	2310      	movs	r3, #16
- 80029e2:	77fb      	strb	r3, [r7, #31]
- 80029e4:	bf00      	nop
- 80029e6:	e0e4      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 80029e8:	687b      	ldr	r3, [r7, #4]
- 80029ea:	681b      	ldr	r3, [r3, #0]
- 80029ec:	4a5f      	ldr	r2, [pc, #380]	; (8002b6c <UART_SetConfig+0x308>)
- 80029ee:	4293      	cmp	r3, r2
- 80029f0:	d120      	bne.n	8002a34 <UART_SetConfig+0x1d0>
- 80029f2:	4b5b      	ldr	r3, [pc, #364]	; (8002b60 <UART_SetConfig+0x2fc>)
- 80029f4:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 80029f8:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
- 80029fc:	2b40      	cmp	r3, #64	; 0x40
- 80029fe:	d00f      	beq.n	8002a20 <UART_SetConfig+0x1bc>
- 8002a00:	2b40      	cmp	r3, #64	; 0x40
- 8002a02:	d802      	bhi.n	8002a0a <UART_SetConfig+0x1a6>
- 8002a04:	2b00      	cmp	r3, #0
- 8002a06:	d005      	beq.n	8002a14 <UART_SetConfig+0x1b0>
- 8002a08:	e010      	b.n	8002a2c <UART_SetConfig+0x1c8>
- 8002a0a:	2b80      	cmp	r3, #128	; 0x80
- 8002a0c:	d005      	beq.n	8002a1a <UART_SetConfig+0x1b6>
- 8002a0e:	2bc0      	cmp	r3, #192	; 0xc0
- 8002a10:	d009      	beq.n	8002a26 <UART_SetConfig+0x1c2>
- 8002a12:	e00b      	b.n	8002a2c <UART_SetConfig+0x1c8>
- 8002a14:	2300      	movs	r3, #0
- 8002a16:	77fb      	strb	r3, [r7, #31]
- 8002a18:	e0cb      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002a1a:	2302      	movs	r3, #2
- 8002a1c:	77fb      	strb	r3, [r7, #31]
- 8002a1e:	e0c8      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002a20:	2304      	movs	r3, #4
- 8002a22:	77fb      	strb	r3, [r7, #31]
- 8002a24:	e0c5      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002a26:	2308      	movs	r3, #8
- 8002a28:	77fb      	strb	r3, [r7, #31]
- 8002a2a:	e0c2      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002a2c:	2310      	movs	r3, #16
- 8002a2e:	77fb      	strb	r3, [r7, #31]
- 8002a30:	bf00      	nop
- 8002a32:	e0be      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002a34:	687b      	ldr	r3, [r7, #4]
- 8002a36:	681b      	ldr	r3, [r3, #0]
- 8002a38:	4a4d      	ldr	r2, [pc, #308]	; (8002b70 <UART_SetConfig+0x30c>)
- 8002a3a:	4293      	cmp	r3, r2
- 8002a3c:	d124      	bne.n	8002a88 <UART_SetConfig+0x224>
- 8002a3e:	4b48      	ldr	r3, [pc, #288]	; (8002b60 <UART_SetConfig+0x2fc>)
- 8002a40:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8002a44:	f403 7340 	and.w	r3, r3, #768	; 0x300
- 8002a48:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
- 8002a4c:	d012      	beq.n	8002a74 <UART_SetConfig+0x210>
- 8002a4e:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
- 8002a52:	d802      	bhi.n	8002a5a <UART_SetConfig+0x1f6>
- 8002a54:	2b00      	cmp	r3, #0
- 8002a56:	d007      	beq.n	8002a68 <UART_SetConfig+0x204>
- 8002a58:	e012      	b.n	8002a80 <UART_SetConfig+0x21c>
- 8002a5a:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
- 8002a5e:	d006      	beq.n	8002a6e <UART_SetConfig+0x20a>
- 8002a60:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
- 8002a64:	d009      	beq.n	8002a7a <UART_SetConfig+0x216>
- 8002a66:	e00b      	b.n	8002a80 <UART_SetConfig+0x21c>
- 8002a68:	2300      	movs	r3, #0
- 8002a6a:	77fb      	strb	r3, [r7, #31]
- 8002a6c:	e0a1      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002a6e:	2302      	movs	r3, #2
- 8002a70:	77fb      	strb	r3, [r7, #31]
- 8002a72:	e09e      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002a74:	2304      	movs	r3, #4
- 8002a76:	77fb      	strb	r3, [r7, #31]
- 8002a78:	e09b      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002a7a:	2308      	movs	r3, #8
- 8002a7c:	77fb      	strb	r3, [r7, #31]
- 8002a7e:	e098      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002a80:	2310      	movs	r3, #16
- 8002a82:	77fb      	strb	r3, [r7, #31]
- 8002a84:	bf00      	nop
- 8002a86:	e094      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002a88:	687b      	ldr	r3, [r7, #4]
- 8002a8a:	681b      	ldr	r3, [r3, #0]
- 8002a8c:	4a39      	ldr	r2, [pc, #228]	; (8002b74 <UART_SetConfig+0x310>)
- 8002a8e:	4293      	cmp	r3, r2
- 8002a90:	d124      	bne.n	8002adc <UART_SetConfig+0x278>
- 8002a92:	4b33      	ldr	r3, [pc, #204]	; (8002b60 <UART_SetConfig+0x2fc>)
- 8002a94:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8002a98:	f403 6340 	and.w	r3, r3, #3072	; 0xc00
- 8002a9c:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
- 8002aa0:	d012      	beq.n	8002ac8 <UART_SetConfig+0x264>
- 8002aa2:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
- 8002aa6:	d802      	bhi.n	8002aae <UART_SetConfig+0x24a>
- 8002aa8:	2b00      	cmp	r3, #0
- 8002aaa:	d007      	beq.n	8002abc <UART_SetConfig+0x258>
- 8002aac:	e012      	b.n	8002ad4 <UART_SetConfig+0x270>
- 8002aae:	f5b3 6f00 	cmp.w	r3, #2048	; 0x800
- 8002ab2:	d006      	beq.n	8002ac2 <UART_SetConfig+0x25e>
- 8002ab4:	f5b3 6f40 	cmp.w	r3, #3072	; 0xc00
- 8002ab8:	d009      	beq.n	8002ace <UART_SetConfig+0x26a>
- 8002aba:	e00b      	b.n	8002ad4 <UART_SetConfig+0x270>
- 8002abc:	2301      	movs	r3, #1
- 8002abe:	77fb      	strb	r3, [r7, #31]
- 8002ac0:	e077      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002ac2:	2302      	movs	r3, #2
- 8002ac4:	77fb      	strb	r3, [r7, #31]
- 8002ac6:	e074      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002ac8:	2304      	movs	r3, #4
- 8002aca:	77fb      	strb	r3, [r7, #31]
- 8002acc:	e071      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002ace:	2308      	movs	r3, #8
- 8002ad0:	77fb      	strb	r3, [r7, #31]
- 8002ad2:	e06e      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002ad4:	2310      	movs	r3, #16
- 8002ad6:	77fb      	strb	r3, [r7, #31]
- 8002ad8:	bf00      	nop
- 8002ada:	e06a      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002adc:	687b      	ldr	r3, [r7, #4]
- 8002ade:	681b      	ldr	r3, [r3, #0]
- 8002ae0:	4a25      	ldr	r2, [pc, #148]	; (8002b78 <UART_SetConfig+0x314>)
- 8002ae2:	4293      	cmp	r3, r2
- 8002ae4:	d124      	bne.n	8002b30 <UART_SetConfig+0x2cc>
- 8002ae6:	4b1e      	ldr	r3, [pc, #120]	; (8002b60 <UART_SetConfig+0x2fc>)
- 8002ae8:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8002aec:	f403 5340 	and.w	r3, r3, #12288	; 0x3000
- 8002af0:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
- 8002af4:	d012      	beq.n	8002b1c <UART_SetConfig+0x2b8>
- 8002af6:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
- 8002afa:	d802      	bhi.n	8002b02 <UART_SetConfig+0x29e>
- 8002afc:	2b00      	cmp	r3, #0
- 8002afe:	d007      	beq.n	8002b10 <UART_SetConfig+0x2ac>
- 8002b00:	e012      	b.n	8002b28 <UART_SetConfig+0x2c4>
- 8002b02:	f5b3 5f00 	cmp.w	r3, #8192	; 0x2000
- 8002b06:	d006      	beq.n	8002b16 <UART_SetConfig+0x2b2>
- 8002b08:	f5b3 5f40 	cmp.w	r3, #12288	; 0x3000
- 8002b0c:	d009      	beq.n	8002b22 <UART_SetConfig+0x2be>
- 8002b0e:	e00b      	b.n	8002b28 <UART_SetConfig+0x2c4>
- 8002b10:	2300      	movs	r3, #0
- 8002b12:	77fb      	strb	r3, [r7, #31]
- 8002b14:	e04d      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002b16:	2302      	movs	r3, #2
- 8002b18:	77fb      	strb	r3, [r7, #31]
- 8002b1a:	e04a      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002b1c:	2304      	movs	r3, #4
- 8002b1e:	77fb      	strb	r3, [r7, #31]
- 8002b20:	e047      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002b22:	2308      	movs	r3, #8
- 8002b24:	77fb      	strb	r3, [r7, #31]
- 8002b26:	e044      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002b28:	2310      	movs	r3, #16
- 8002b2a:	77fb      	strb	r3, [r7, #31]
- 8002b2c:	bf00      	nop
- 8002b2e:	e040      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002b30:	687b      	ldr	r3, [r7, #4]
- 8002b32:	681b      	ldr	r3, [r3, #0]
- 8002b34:	4a11      	ldr	r2, [pc, #68]	; (8002b7c <UART_SetConfig+0x318>)
- 8002b36:	4293      	cmp	r3, r2
- 8002b38:	d139      	bne.n	8002bae <UART_SetConfig+0x34a>
- 8002b3a:	4b09      	ldr	r3, [pc, #36]	; (8002b60 <UART_SetConfig+0x2fc>)
- 8002b3c:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
- 8002b40:	f403 4340 	and.w	r3, r3, #49152	; 0xc000
- 8002b44:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
- 8002b48:	d027      	beq.n	8002b9a <UART_SetConfig+0x336>
- 8002b4a:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
- 8002b4e:	d817      	bhi.n	8002b80 <UART_SetConfig+0x31c>
- 8002b50:	2b00      	cmp	r3, #0
- 8002b52:	d01c      	beq.n	8002b8e <UART_SetConfig+0x32a>
- 8002b54:	e027      	b.n	8002ba6 <UART_SetConfig+0x342>
- 8002b56:	bf00      	nop
- 8002b58:	efff69f3 	.word	0xefff69f3
- 8002b5c:	40011000 	.word	0x40011000
- 8002b60:	40023800 	.word	0x40023800
- 8002b64:	40004400 	.word	0x40004400
- 8002b68:	40004800 	.word	0x40004800
- 8002b6c:	40004c00 	.word	0x40004c00
- 8002b70:	40005000 	.word	0x40005000
- 8002b74:	40011400 	.word	0x40011400
- 8002b78:	40007800 	.word	0x40007800
- 8002b7c:	40007c00 	.word	0x40007c00
- 8002b80:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
- 8002b84:	d006      	beq.n	8002b94 <UART_SetConfig+0x330>
- 8002b86:	f5b3 4f40 	cmp.w	r3, #49152	; 0xc000
- 8002b8a:	d009      	beq.n	8002ba0 <UART_SetConfig+0x33c>
- 8002b8c:	e00b      	b.n	8002ba6 <UART_SetConfig+0x342>
- 8002b8e:	2300      	movs	r3, #0
- 8002b90:	77fb      	strb	r3, [r7, #31]
- 8002b92:	e00e      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002b94:	2302      	movs	r3, #2
- 8002b96:	77fb      	strb	r3, [r7, #31]
- 8002b98:	e00b      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002b9a:	2304      	movs	r3, #4
- 8002b9c:	77fb      	strb	r3, [r7, #31]
- 8002b9e:	e008      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002ba0:	2308      	movs	r3, #8
- 8002ba2:	77fb      	strb	r3, [r7, #31]
- 8002ba4:	e005      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002ba6:	2310      	movs	r3, #16
- 8002ba8:	77fb      	strb	r3, [r7, #31]
- 8002baa:	bf00      	nop
- 8002bac:	e001      	b.n	8002bb2 <UART_SetConfig+0x34e>
- 8002bae:	2310      	movs	r3, #16
- 8002bb0:	77fb      	strb	r3, [r7, #31]
+ 800310e:	687b      	ldr	r3, [r7, #4]
+ 8003110:	681b      	ldr	r3, [r3, #0]
+ 8003112:	4a9f      	ldr	r2, [pc, #636]	; (8003390 <UART_SetConfig+0x2f8>)
+ 8003114:	4293      	cmp	r3, r2
+ 8003116:	d121      	bne.n	800315c <UART_SetConfig+0xc4>
+ 8003118:	4b9e      	ldr	r3, [pc, #632]	; (8003394 <UART_SetConfig+0x2fc>)
+ 800311a:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 800311e:	f003 0303 	and.w	r3, r3, #3
+ 8003122:	2b03      	cmp	r3, #3
+ 8003124:	d816      	bhi.n	8003154 <UART_SetConfig+0xbc>
+ 8003126:	a201      	add	r2, pc, #4	; (adr r2, 800312c <UART_SetConfig+0x94>)
+ 8003128:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800312c:	0800313d 	.word	0x0800313d
+ 8003130:	08003149 	.word	0x08003149
+ 8003134:	08003143 	.word	0x08003143
+ 8003138:	0800314f 	.word	0x0800314f
+ 800313c:	2301      	movs	r3, #1
+ 800313e:	77fb      	strb	r3, [r7, #31]
+ 8003140:	e151      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 8003142:	2302      	movs	r3, #2
+ 8003144:	77fb      	strb	r3, [r7, #31]
+ 8003146:	e14e      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 8003148:	2304      	movs	r3, #4
+ 800314a:	77fb      	strb	r3, [r7, #31]
+ 800314c:	e14b      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 800314e:	2308      	movs	r3, #8
+ 8003150:	77fb      	strb	r3, [r7, #31]
+ 8003152:	e148      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 8003154:	2310      	movs	r3, #16
+ 8003156:	77fb      	strb	r3, [r7, #31]
+ 8003158:	bf00      	nop
+ 800315a:	e144      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 800315c:	687b      	ldr	r3, [r7, #4]
+ 800315e:	681b      	ldr	r3, [r3, #0]
+ 8003160:	4a8d      	ldr	r2, [pc, #564]	; (8003398 <UART_SetConfig+0x300>)
+ 8003162:	4293      	cmp	r3, r2
+ 8003164:	d134      	bne.n	80031d0 <UART_SetConfig+0x138>
+ 8003166:	4b8b      	ldr	r3, [pc, #556]	; (8003394 <UART_SetConfig+0x2fc>)
+ 8003168:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 800316c:	f003 030c 	and.w	r3, r3, #12
+ 8003170:	2b0c      	cmp	r3, #12
+ 8003172:	d829      	bhi.n	80031c8 <UART_SetConfig+0x130>
+ 8003174:	a201      	add	r2, pc, #4	; (adr r2, 800317c <UART_SetConfig+0xe4>)
+ 8003176:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800317a:	bf00      	nop
+ 800317c:	080031b1 	.word	0x080031b1
+ 8003180:	080031c9 	.word	0x080031c9
+ 8003184:	080031c9 	.word	0x080031c9
+ 8003188:	080031c9 	.word	0x080031c9
+ 800318c:	080031bd 	.word	0x080031bd
+ 8003190:	080031c9 	.word	0x080031c9
+ 8003194:	080031c9 	.word	0x080031c9
+ 8003198:	080031c9 	.word	0x080031c9
+ 800319c:	080031b7 	.word	0x080031b7
+ 80031a0:	080031c9 	.word	0x080031c9
+ 80031a4:	080031c9 	.word	0x080031c9
+ 80031a8:	080031c9 	.word	0x080031c9
+ 80031ac:	080031c3 	.word	0x080031c3
+ 80031b0:	2300      	movs	r3, #0
+ 80031b2:	77fb      	strb	r3, [r7, #31]
+ 80031b4:	e117      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 80031b6:	2302      	movs	r3, #2
+ 80031b8:	77fb      	strb	r3, [r7, #31]
+ 80031ba:	e114      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 80031bc:	2304      	movs	r3, #4
+ 80031be:	77fb      	strb	r3, [r7, #31]
+ 80031c0:	e111      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 80031c2:	2308      	movs	r3, #8
+ 80031c4:	77fb      	strb	r3, [r7, #31]
+ 80031c6:	e10e      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 80031c8:	2310      	movs	r3, #16
+ 80031ca:	77fb      	strb	r3, [r7, #31]
+ 80031cc:	bf00      	nop
+ 80031ce:	e10a      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 80031d0:	687b      	ldr	r3, [r7, #4]
+ 80031d2:	681b      	ldr	r3, [r3, #0]
+ 80031d4:	4a71      	ldr	r2, [pc, #452]	; (800339c <UART_SetConfig+0x304>)
+ 80031d6:	4293      	cmp	r3, r2
+ 80031d8:	d120      	bne.n	800321c <UART_SetConfig+0x184>
+ 80031da:	4b6e      	ldr	r3, [pc, #440]	; (8003394 <UART_SetConfig+0x2fc>)
+ 80031dc:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 80031e0:	f003 0330 	and.w	r3, r3, #48	; 0x30
+ 80031e4:	2b10      	cmp	r3, #16
+ 80031e6:	d00f      	beq.n	8003208 <UART_SetConfig+0x170>
+ 80031e8:	2b10      	cmp	r3, #16
+ 80031ea:	d802      	bhi.n	80031f2 <UART_SetConfig+0x15a>
+ 80031ec:	2b00      	cmp	r3, #0
+ 80031ee:	d005      	beq.n	80031fc <UART_SetConfig+0x164>
+ 80031f0:	e010      	b.n	8003214 <UART_SetConfig+0x17c>
+ 80031f2:	2b20      	cmp	r3, #32
+ 80031f4:	d005      	beq.n	8003202 <UART_SetConfig+0x16a>
+ 80031f6:	2b30      	cmp	r3, #48	; 0x30
+ 80031f8:	d009      	beq.n	800320e <UART_SetConfig+0x176>
+ 80031fa:	e00b      	b.n	8003214 <UART_SetConfig+0x17c>
+ 80031fc:	2300      	movs	r3, #0
+ 80031fe:	77fb      	strb	r3, [r7, #31]
+ 8003200:	e0f1      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 8003202:	2302      	movs	r3, #2
+ 8003204:	77fb      	strb	r3, [r7, #31]
+ 8003206:	e0ee      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 8003208:	2304      	movs	r3, #4
+ 800320a:	77fb      	strb	r3, [r7, #31]
+ 800320c:	e0eb      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 800320e:	2308      	movs	r3, #8
+ 8003210:	77fb      	strb	r3, [r7, #31]
+ 8003212:	e0e8      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 8003214:	2310      	movs	r3, #16
+ 8003216:	77fb      	strb	r3, [r7, #31]
+ 8003218:	bf00      	nop
+ 800321a:	e0e4      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 800321c:	687b      	ldr	r3, [r7, #4]
+ 800321e:	681b      	ldr	r3, [r3, #0]
+ 8003220:	4a5f      	ldr	r2, [pc, #380]	; (80033a0 <UART_SetConfig+0x308>)
+ 8003222:	4293      	cmp	r3, r2
+ 8003224:	d120      	bne.n	8003268 <UART_SetConfig+0x1d0>
+ 8003226:	4b5b      	ldr	r3, [pc, #364]	; (8003394 <UART_SetConfig+0x2fc>)
+ 8003228:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 800322c:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
+ 8003230:	2b40      	cmp	r3, #64	; 0x40
+ 8003232:	d00f      	beq.n	8003254 <UART_SetConfig+0x1bc>
+ 8003234:	2b40      	cmp	r3, #64	; 0x40
+ 8003236:	d802      	bhi.n	800323e <UART_SetConfig+0x1a6>
+ 8003238:	2b00      	cmp	r3, #0
+ 800323a:	d005      	beq.n	8003248 <UART_SetConfig+0x1b0>
+ 800323c:	e010      	b.n	8003260 <UART_SetConfig+0x1c8>
+ 800323e:	2b80      	cmp	r3, #128	; 0x80
+ 8003240:	d005      	beq.n	800324e <UART_SetConfig+0x1b6>
+ 8003242:	2bc0      	cmp	r3, #192	; 0xc0
+ 8003244:	d009      	beq.n	800325a <UART_SetConfig+0x1c2>
+ 8003246:	e00b      	b.n	8003260 <UART_SetConfig+0x1c8>
+ 8003248:	2300      	movs	r3, #0
+ 800324a:	77fb      	strb	r3, [r7, #31]
+ 800324c:	e0cb      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 800324e:	2302      	movs	r3, #2
+ 8003250:	77fb      	strb	r3, [r7, #31]
+ 8003252:	e0c8      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 8003254:	2304      	movs	r3, #4
+ 8003256:	77fb      	strb	r3, [r7, #31]
+ 8003258:	e0c5      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 800325a:	2308      	movs	r3, #8
+ 800325c:	77fb      	strb	r3, [r7, #31]
+ 800325e:	e0c2      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 8003260:	2310      	movs	r3, #16
+ 8003262:	77fb      	strb	r3, [r7, #31]
+ 8003264:	bf00      	nop
+ 8003266:	e0be      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 8003268:	687b      	ldr	r3, [r7, #4]
+ 800326a:	681b      	ldr	r3, [r3, #0]
+ 800326c:	4a4d      	ldr	r2, [pc, #308]	; (80033a4 <UART_SetConfig+0x30c>)
+ 800326e:	4293      	cmp	r3, r2
+ 8003270:	d124      	bne.n	80032bc <UART_SetConfig+0x224>
+ 8003272:	4b48      	ldr	r3, [pc, #288]	; (8003394 <UART_SetConfig+0x2fc>)
+ 8003274:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8003278:	f403 7340 	and.w	r3, r3, #768	; 0x300
+ 800327c:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
+ 8003280:	d012      	beq.n	80032a8 <UART_SetConfig+0x210>
+ 8003282:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
+ 8003286:	d802      	bhi.n	800328e <UART_SetConfig+0x1f6>
+ 8003288:	2b00      	cmp	r3, #0
+ 800328a:	d007      	beq.n	800329c <UART_SetConfig+0x204>
+ 800328c:	e012      	b.n	80032b4 <UART_SetConfig+0x21c>
+ 800328e:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
+ 8003292:	d006      	beq.n	80032a2 <UART_SetConfig+0x20a>
+ 8003294:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
+ 8003298:	d009      	beq.n	80032ae <UART_SetConfig+0x216>
+ 800329a:	e00b      	b.n	80032b4 <UART_SetConfig+0x21c>
+ 800329c:	2300      	movs	r3, #0
+ 800329e:	77fb      	strb	r3, [r7, #31]
+ 80032a0:	e0a1      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 80032a2:	2302      	movs	r3, #2
+ 80032a4:	77fb      	strb	r3, [r7, #31]
+ 80032a6:	e09e      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 80032a8:	2304      	movs	r3, #4
+ 80032aa:	77fb      	strb	r3, [r7, #31]
+ 80032ac:	e09b      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 80032ae:	2308      	movs	r3, #8
+ 80032b0:	77fb      	strb	r3, [r7, #31]
+ 80032b2:	e098      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 80032b4:	2310      	movs	r3, #16
+ 80032b6:	77fb      	strb	r3, [r7, #31]
+ 80032b8:	bf00      	nop
+ 80032ba:	e094      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 80032bc:	687b      	ldr	r3, [r7, #4]
+ 80032be:	681b      	ldr	r3, [r3, #0]
+ 80032c0:	4a39      	ldr	r2, [pc, #228]	; (80033a8 <UART_SetConfig+0x310>)
+ 80032c2:	4293      	cmp	r3, r2
+ 80032c4:	d124      	bne.n	8003310 <UART_SetConfig+0x278>
+ 80032c6:	4b33      	ldr	r3, [pc, #204]	; (8003394 <UART_SetConfig+0x2fc>)
+ 80032c8:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 80032cc:	f403 6340 	and.w	r3, r3, #3072	; 0xc00
+ 80032d0:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
+ 80032d4:	d012      	beq.n	80032fc <UART_SetConfig+0x264>
+ 80032d6:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
+ 80032da:	d802      	bhi.n	80032e2 <UART_SetConfig+0x24a>
+ 80032dc:	2b00      	cmp	r3, #0
+ 80032de:	d007      	beq.n	80032f0 <UART_SetConfig+0x258>
+ 80032e0:	e012      	b.n	8003308 <UART_SetConfig+0x270>
+ 80032e2:	f5b3 6f00 	cmp.w	r3, #2048	; 0x800
+ 80032e6:	d006      	beq.n	80032f6 <UART_SetConfig+0x25e>
+ 80032e8:	f5b3 6f40 	cmp.w	r3, #3072	; 0xc00
+ 80032ec:	d009      	beq.n	8003302 <UART_SetConfig+0x26a>
+ 80032ee:	e00b      	b.n	8003308 <UART_SetConfig+0x270>
+ 80032f0:	2301      	movs	r3, #1
+ 80032f2:	77fb      	strb	r3, [r7, #31]
+ 80032f4:	e077      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 80032f6:	2302      	movs	r3, #2
+ 80032f8:	77fb      	strb	r3, [r7, #31]
+ 80032fa:	e074      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 80032fc:	2304      	movs	r3, #4
+ 80032fe:	77fb      	strb	r3, [r7, #31]
+ 8003300:	e071      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 8003302:	2308      	movs	r3, #8
+ 8003304:	77fb      	strb	r3, [r7, #31]
+ 8003306:	e06e      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 8003308:	2310      	movs	r3, #16
+ 800330a:	77fb      	strb	r3, [r7, #31]
+ 800330c:	bf00      	nop
+ 800330e:	e06a      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 8003310:	687b      	ldr	r3, [r7, #4]
+ 8003312:	681b      	ldr	r3, [r3, #0]
+ 8003314:	4a25      	ldr	r2, [pc, #148]	; (80033ac <UART_SetConfig+0x314>)
+ 8003316:	4293      	cmp	r3, r2
+ 8003318:	d124      	bne.n	8003364 <UART_SetConfig+0x2cc>
+ 800331a:	4b1e      	ldr	r3, [pc, #120]	; (8003394 <UART_SetConfig+0x2fc>)
+ 800331c:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8003320:	f403 5340 	and.w	r3, r3, #12288	; 0x3000
+ 8003324:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
+ 8003328:	d012      	beq.n	8003350 <UART_SetConfig+0x2b8>
+ 800332a:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
+ 800332e:	d802      	bhi.n	8003336 <UART_SetConfig+0x29e>
+ 8003330:	2b00      	cmp	r3, #0
+ 8003332:	d007      	beq.n	8003344 <UART_SetConfig+0x2ac>
+ 8003334:	e012      	b.n	800335c <UART_SetConfig+0x2c4>
+ 8003336:	f5b3 5f00 	cmp.w	r3, #8192	; 0x2000
+ 800333a:	d006      	beq.n	800334a <UART_SetConfig+0x2b2>
+ 800333c:	f5b3 5f40 	cmp.w	r3, #12288	; 0x3000
+ 8003340:	d009      	beq.n	8003356 <UART_SetConfig+0x2be>
+ 8003342:	e00b      	b.n	800335c <UART_SetConfig+0x2c4>
+ 8003344:	2300      	movs	r3, #0
+ 8003346:	77fb      	strb	r3, [r7, #31]
+ 8003348:	e04d      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 800334a:	2302      	movs	r3, #2
+ 800334c:	77fb      	strb	r3, [r7, #31]
+ 800334e:	e04a      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 8003350:	2304      	movs	r3, #4
+ 8003352:	77fb      	strb	r3, [r7, #31]
+ 8003354:	e047      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 8003356:	2308      	movs	r3, #8
+ 8003358:	77fb      	strb	r3, [r7, #31]
+ 800335a:	e044      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 800335c:	2310      	movs	r3, #16
+ 800335e:	77fb      	strb	r3, [r7, #31]
+ 8003360:	bf00      	nop
+ 8003362:	e040      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 8003364:	687b      	ldr	r3, [r7, #4]
+ 8003366:	681b      	ldr	r3, [r3, #0]
+ 8003368:	4a11      	ldr	r2, [pc, #68]	; (80033b0 <UART_SetConfig+0x318>)
+ 800336a:	4293      	cmp	r3, r2
+ 800336c:	d139      	bne.n	80033e2 <UART_SetConfig+0x34a>
+ 800336e:	4b09      	ldr	r3, [pc, #36]	; (8003394 <UART_SetConfig+0x2fc>)
+ 8003370:	f8d3 3090 	ldr.w	r3, [r3, #144]	; 0x90
+ 8003374:	f403 4340 	and.w	r3, r3, #49152	; 0xc000
+ 8003378:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
+ 800337c:	d027      	beq.n	80033ce <UART_SetConfig+0x336>
+ 800337e:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
+ 8003382:	d817      	bhi.n	80033b4 <UART_SetConfig+0x31c>
+ 8003384:	2b00      	cmp	r3, #0
+ 8003386:	d01c      	beq.n	80033c2 <UART_SetConfig+0x32a>
+ 8003388:	e027      	b.n	80033da <UART_SetConfig+0x342>
+ 800338a:	bf00      	nop
+ 800338c:	efff69f3 	.word	0xefff69f3
+ 8003390:	40011000 	.word	0x40011000
+ 8003394:	40023800 	.word	0x40023800
+ 8003398:	40004400 	.word	0x40004400
+ 800339c:	40004800 	.word	0x40004800
+ 80033a0:	40004c00 	.word	0x40004c00
+ 80033a4:	40005000 	.word	0x40005000
+ 80033a8:	40011400 	.word	0x40011400
+ 80033ac:	40007800 	.word	0x40007800
+ 80033b0:	40007c00 	.word	0x40007c00
+ 80033b4:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
+ 80033b8:	d006      	beq.n	80033c8 <UART_SetConfig+0x330>
+ 80033ba:	f5b3 4f40 	cmp.w	r3, #49152	; 0xc000
+ 80033be:	d009      	beq.n	80033d4 <UART_SetConfig+0x33c>
+ 80033c0:	e00b      	b.n	80033da <UART_SetConfig+0x342>
+ 80033c2:	2300      	movs	r3, #0
+ 80033c4:	77fb      	strb	r3, [r7, #31]
+ 80033c6:	e00e      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 80033c8:	2302      	movs	r3, #2
+ 80033ca:	77fb      	strb	r3, [r7, #31]
+ 80033cc:	e00b      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 80033ce:	2304      	movs	r3, #4
+ 80033d0:	77fb      	strb	r3, [r7, #31]
+ 80033d2:	e008      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 80033d4:	2308      	movs	r3, #8
+ 80033d6:	77fb      	strb	r3, [r7, #31]
+ 80033d8:	e005      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 80033da:	2310      	movs	r3, #16
+ 80033dc:	77fb      	strb	r3, [r7, #31]
+ 80033de:	bf00      	nop
+ 80033e0:	e001      	b.n	80033e6 <UART_SetConfig+0x34e>
+ 80033e2:	2310      	movs	r3, #16
+ 80033e4:	77fb      	strb	r3, [r7, #31]
 
   if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
- 8002bb2:	687b      	ldr	r3, [r7, #4]
- 8002bb4:	69db      	ldr	r3, [r3, #28]
- 8002bb6:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
- 8002bba:	d17c      	bne.n	8002cb6 <UART_SetConfig+0x452>
+ 80033e6:	687b      	ldr	r3, [r7, #4]
+ 80033e8:	69db      	ldr	r3, [r3, #28]
+ 80033ea:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
+ 80033ee:	d17c      	bne.n	80034ea <UART_SetConfig+0x452>
   {
     switch (clocksource)
- 8002bbc:	7ffb      	ldrb	r3, [r7, #31]
- 8002bbe:	2b08      	cmp	r3, #8
- 8002bc0:	d859      	bhi.n	8002c76 <UART_SetConfig+0x412>
- 8002bc2:	a201      	add	r2, pc, #4	; (adr r2, 8002bc8 <UART_SetConfig+0x364>)
- 8002bc4:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
- 8002bc8:	08002bed 	.word	0x08002bed
- 8002bcc:	08002c0b 	.word	0x08002c0b
- 8002bd0:	08002c29 	.word	0x08002c29
- 8002bd4:	08002c77 	.word	0x08002c77
- 8002bd8:	08002c41 	.word	0x08002c41
- 8002bdc:	08002c77 	.word	0x08002c77
- 8002be0:	08002c77 	.word	0x08002c77
- 8002be4:	08002c77 	.word	0x08002c77
- 8002be8:	08002c5f 	.word	0x08002c5f
+ 80033f0:	7ffb      	ldrb	r3, [r7, #31]
+ 80033f2:	2b08      	cmp	r3, #8
+ 80033f4:	d859      	bhi.n	80034aa <UART_SetConfig+0x412>
+ 80033f6:	a201      	add	r2, pc, #4	; (adr r2, 80033fc <UART_SetConfig+0x364>)
+ 80033f8:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 80033fc:	08003421 	.word	0x08003421
+ 8003400:	0800343f 	.word	0x0800343f
+ 8003404:	0800345d 	.word	0x0800345d
+ 8003408:	080034ab 	.word	0x080034ab
+ 800340c:	08003475 	.word	0x08003475
+ 8003410:	080034ab 	.word	0x080034ab
+ 8003414:	080034ab 	.word	0x080034ab
+ 8003418:	080034ab 	.word	0x080034ab
+ 800341c:	08003493 	.word	0x08003493
     {
       case UART_CLOCKSOURCE_PCLK1:
         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- 8002bec:	f7fe fee0 	bl	80019b0 <HAL_RCC_GetPCLK1Freq>
- 8002bf0:	4603      	mov	r3, r0
- 8002bf2:	005a      	lsls	r2, r3, #1
- 8002bf4:	687b      	ldr	r3, [r7, #4]
- 8002bf6:	685b      	ldr	r3, [r3, #4]
- 8002bf8:	085b      	lsrs	r3, r3, #1
- 8002bfa:	441a      	add	r2, r3
- 8002bfc:	687b      	ldr	r3, [r7, #4]
- 8002bfe:	685b      	ldr	r3, [r3, #4]
- 8002c00:	fbb2 f3f3 	udiv	r3, r2, r3
- 8002c04:	b29b      	uxth	r3, r3
- 8002c06:	61bb      	str	r3, [r7, #24]
+ 8003420:	f7fe fae0 	bl	80019e4 <HAL_RCC_GetPCLK1Freq>
+ 8003424:	4603      	mov	r3, r0
+ 8003426:	005a      	lsls	r2, r3, #1
+ 8003428:	687b      	ldr	r3, [r7, #4]
+ 800342a:	685b      	ldr	r3, [r3, #4]
+ 800342c:	085b      	lsrs	r3, r3, #1
+ 800342e:	441a      	add	r2, r3
+ 8003430:	687b      	ldr	r3, [r7, #4]
+ 8003432:	685b      	ldr	r3, [r3, #4]
+ 8003434:	fbb2 f3f3 	udiv	r3, r2, r3
+ 8003438:	b29b      	uxth	r3, r3
+ 800343a:	61bb      	str	r3, [r7, #24]
         break;
- 8002c08:	e038      	b.n	8002c7c <UART_SetConfig+0x418>
+ 800343c:	e038      	b.n	80034b0 <UART_SetConfig+0x418>
       case UART_CLOCKSOURCE_PCLK2:
         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- 8002c0a:	f7fe fee5 	bl	80019d8 <HAL_RCC_GetPCLK2Freq>
- 8002c0e:	4603      	mov	r3, r0
- 8002c10:	005a      	lsls	r2, r3, #1
- 8002c12:	687b      	ldr	r3, [r7, #4]
- 8002c14:	685b      	ldr	r3, [r3, #4]
- 8002c16:	085b      	lsrs	r3, r3, #1
- 8002c18:	441a      	add	r2, r3
- 8002c1a:	687b      	ldr	r3, [r7, #4]
- 8002c1c:	685b      	ldr	r3, [r3, #4]
- 8002c1e:	fbb2 f3f3 	udiv	r3, r2, r3
- 8002c22:	b29b      	uxth	r3, r3
- 8002c24:	61bb      	str	r3, [r7, #24]
+ 800343e:	f7fe fae5 	bl	8001a0c <HAL_RCC_GetPCLK2Freq>
+ 8003442:	4603      	mov	r3, r0
+ 8003444:	005a      	lsls	r2, r3, #1
+ 8003446:	687b      	ldr	r3, [r7, #4]
+ 8003448:	685b      	ldr	r3, [r3, #4]
+ 800344a:	085b      	lsrs	r3, r3, #1
+ 800344c:	441a      	add	r2, r3
+ 800344e:	687b      	ldr	r3, [r7, #4]
+ 8003450:	685b      	ldr	r3, [r3, #4]
+ 8003452:	fbb2 f3f3 	udiv	r3, r2, r3
+ 8003456:	b29b      	uxth	r3, r3
+ 8003458:	61bb      	str	r3, [r7, #24]
         break;
- 8002c26:	e029      	b.n	8002c7c <UART_SetConfig+0x418>
+ 800345a:	e029      	b.n	80034b0 <UART_SetConfig+0x418>
       case UART_CLOCKSOURCE_HSI:
         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
- 8002c28:	687b      	ldr	r3, [r7, #4]
- 8002c2a:	685b      	ldr	r3, [r3, #4]
- 8002c2c:	085a      	lsrs	r2, r3, #1
- 8002c2e:	4b5d      	ldr	r3, [pc, #372]	; (8002da4 <UART_SetConfig+0x540>)
- 8002c30:	4413      	add	r3, r2
- 8002c32:	687a      	ldr	r2, [r7, #4]
- 8002c34:	6852      	ldr	r2, [r2, #4]
- 8002c36:	fbb3 f3f2 	udiv	r3, r3, r2
- 8002c3a:	b29b      	uxth	r3, r3
- 8002c3c:	61bb      	str	r3, [r7, #24]
+ 800345c:	687b      	ldr	r3, [r7, #4]
+ 800345e:	685b      	ldr	r3, [r3, #4]
+ 8003460:	085a      	lsrs	r2, r3, #1
+ 8003462:	4b5d      	ldr	r3, [pc, #372]	; (80035d8 <UART_SetConfig+0x540>)
+ 8003464:	4413      	add	r3, r2
+ 8003466:	687a      	ldr	r2, [r7, #4]
+ 8003468:	6852      	ldr	r2, [r2, #4]
+ 800346a:	fbb3 f3f2 	udiv	r3, r3, r2
+ 800346e:	b29b      	uxth	r3, r3
+ 8003470:	61bb      	str	r3, [r7, #24]
         break;
- 8002c3e:	e01d      	b.n	8002c7c <UART_SetConfig+0x418>
+ 8003472:	e01d      	b.n	80034b0 <UART_SetConfig+0x418>
       case UART_CLOCKSOURCE_SYSCLK:
         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- 8002c40:	f7fe fdf8 	bl	8001834 <HAL_RCC_GetSysClockFreq>
- 8002c44:	4603      	mov	r3, r0
- 8002c46:	005a      	lsls	r2, r3, #1
- 8002c48:	687b      	ldr	r3, [r7, #4]
- 8002c4a:	685b      	ldr	r3, [r3, #4]
- 8002c4c:	085b      	lsrs	r3, r3, #1
- 8002c4e:	441a      	add	r2, r3
- 8002c50:	687b      	ldr	r3, [r7, #4]
- 8002c52:	685b      	ldr	r3, [r3, #4]
- 8002c54:	fbb2 f3f3 	udiv	r3, r2, r3
- 8002c58:	b29b      	uxth	r3, r3
- 8002c5a:	61bb      	str	r3, [r7, #24]
+ 8003474:	f7fe f9f8 	bl	8001868 <HAL_RCC_GetSysClockFreq>
+ 8003478:	4603      	mov	r3, r0
+ 800347a:	005a      	lsls	r2, r3, #1
+ 800347c:	687b      	ldr	r3, [r7, #4]
+ 800347e:	685b      	ldr	r3, [r3, #4]
+ 8003480:	085b      	lsrs	r3, r3, #1
+ 8003482:	441a      	add	r2, r3
+ 8003484:	687b      	ldr	r3, [r7, #4]
+ 8003486:	685b      	ldr	r3, [r3, #4]
+ 8003488:	fbb2 f3f3 	udiv	r3, r2, r3
+ 800348c:	b29b      	uxth	r3, r3
+ 800348e:	61bb      	str	r3, [r7, #24]
         break;
- 8002c5c:	e00e      	b.n	8002c7c <UART_SetConfig+0x418>
+ 8003490:	e00e      	b.n	80034b0 <UART_SetConfig+0x418>
       case UART_CLOCKSOURCE_LSE:
         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
- 8002c5e:	687b      	ldr	r3, [r7, #4]
- 8002c60:	685b      	ldr	r3, [r3, #4]
- 8002c62:	085b      	lsrs	r3, r3, #1
- 8002c64:	f503 3280 	add.w	r2, r3, #65536	; 0x10000
- 8002c68:	687b      	ldr	r3, [r7, #4]
- 8002c6a:	685b      	ldr	r3, [r3, #4]
- 8002c6c:	fbb2 f3f3 	udiv	r3, r2, r3
- 8002c70:	b29b      	uxth	r3, r3
- 8002c72:	61bb      	str	r3, [r7, #24]
+ 8003492:	687b      	ldr	r3, [r7, #4]
+ 8003494:	685b      	ldr	r3, [r3, #4]
+ 8003496:	085b      	lsrs	r3, r3, #1
+ 8003498:	f503 3280 	add.w	r2, r3, #65536	; 0x10000
+ 800349c:	687b      	ldr	r3, [r7, #4]
+ 800349e:	685b      	ldr	r3, [r3, #4]
+ 80034a0:	fbb2 f3f3 	udiv	r3, r2, r3
+ 80034a4:	b29b      	uxth	r3, r3
+ 80034a6:	61bb      	str	r3, [r7, #24]
         break;
- 8002c74:	e002      	b.n	8002c7c <UART_SetConfig+0x418>
+ 80034a8:	e002      	b.n	80034b0 <UART_SetConfig+0x418>
       case UART_CLOCKSOURCE_UNDEFINED:
       default:
         ret = HAL_ERROR;
- 8002c76:	2301      	movs	r3, #1
- 8002c78:	75fb      	strb	r3, [r7, #23]
+ 80034aa:	2301      	movs	r3, #1
+ 80034ac:	75fb      	strb	r3, [r7, #23]
         break;
- 8002c7a:	bf00      	nop
+ 80034ae:	bf00      	nop
     }
 
     /* USARTDIV must be greater than or equal to 0d16 */
     if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 8002c7c:	69bb      	ldr	r3, [r7, #24]
- 8002c7e:	2b0f      	cmp	r3, #15
- 8002c80:	d916      	bls.n	8002cb0 <UART_SetConfig+0x44c>
- 8002c82:	69bb      	ldr	r3, [r7, #24]
- 8002c84:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
- 8002c88:	d212      	bcs.n	8002cb0 <UART_SetConfig+0x44c>
+ 80034b0:	69bb      	ldr	r3, [r7, #24]
+ 80034b2:	2b0f      	cmp	r3, #15
+ 80034b4:	d916      	bls.n	80034e4 <UART_SetConfig+0x44c>
+ 80034b6:	69bb      	ldr	r3, [r7, #24]
+ 80034b8:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 80034bc:	d212      	bcs.n	80034e4 <UART_SetConfig+0x44c>
     {
       brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
- 8002c8a:	69bb      	ldr	r3, [r7, #24]
- 8002c8c:	b29b      	uxth	r3, r3
- 8002c8e:	f023 030f 	bic.w	r3, r3, #15
- 8002c92:	81fb      	strh	r3, [r7, #14]
+ 80034be:	69bb      	ldr	r3, [r7, #24]
+ 80034c0:	b29b      	uxth	r3, r3
+ 80034c2:	f023 030f 	bic.w	r3, r3, #15
+ 80034c6:	81fb      	strh	r3, [r7, #14]
       brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- 8002c94:	69bb      	ldr	r3, [r7, #24]
- 8002c96:	085b      	lsrs	r3, r3, #1
- 8002c98:	b29b      	uxth	r3, r3
- 8002c9a:	f003 0307 	and.w	r3, r3, #7
- 8002c9e:	b29a      	uxth	r2, r3
- 8002ca0:	89fb      	ldrh	r3, [r7, #14]
- 8002ca2:	4313      	orrs	r3, r2
- 8002ca4:	81fb      	strh	r3, [r7, #14]
+ 80034c8:	69bb      	ldr	r3, [r7, #24]
+ 80034ca:	085b      	lsrs	r3, r3, #1
+ 80034cc:	b29b      	uxth	r3, r3
+ 80034ce:	f003 0307 	and.w	r3, r3, #7
+ 80034d2:	b29a      	uxth	r2, r3
+ 80034d4:	89fb      	ldrh	r3, [r7, #14]
+ 80034d6:	4313      	orrs	r3, r2
+ 80034d8:	81fb      	strh	r3, [r7, #14]
       huart->Instance->BRR = brrtemp;
- 8002ca6:	687b      	ldr	r3, [r7, #4]
- 8002ca8:	681b      	ldr	r3, [r3, #0]
- 8002caa:	89fa      	ldrh	r2, [r7, #14]
- 8002cac:	60da      	str	r2, [r3, #12]
- 8002cae:	e06e      	b.n	8002d8e <UART_SetConfig+0x52a>
+ 80034da:	687b      	ldr	r3, [r7, #4]
+ 80034dc:	681b      	ldr	r3, [r3, #0]
+ 80034de:	89fa      	ldrh	r2, [r7, #14]
+ 80034e0:	60da      	str	r2, [r3, #12]
+ 80034e2:	e06e      	b.n	80035c2 <UART_SetConfig+0x52a>
     }
     else
     {
       ret = HAL_ERROR;
- 8002cb0:	2301      	movs	r3, #1
- 8002cb2:	75fb      	strb	r3, [r7, #23]
- 8002cb4:	e06b      	b.n	8002d8e <UART_SetConfig+0x52a>
+ 80034e4:	2301      	movs	r3, #1
+ 80034e6:	75fb      	strb	r3, [r7, #23]
+ 80034e8:	e06b      	b.n	80035c2 <UART_SetConfig+0x52a>
     }
   }
   else
   {
     switch (clocksource)
- 8002cb6:	7ffb      	ldrb	r3, [r7, #31]
- 8002cb8:	2b08      	cmp	r3, #8
- 8002cba:	d857      	bhi.n	8002d6c <UART_SetConfig+0x508>
- 8002cbc:	a201      	add	r2, pc, #4	; (adr r2, 8002cc4 <UART_SetConfig+0x460>)
- 8002cbe:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
- 8002cc2:	bf00      	nop
- 8002cc4:	08002ce9 	.word	0x08002ce9
- 8002cc8:	08002d05 	.word	0x08002d05
- 8002ccc:	08002d21 	.word	0x08002d21
- 8002cd0:	08002d6d 	.word	0x08002d6d
- 8002cd4:	08002d39 	.word	0x08002d39
- 8002cd8:	08002d6d 	.word	0x08002d6d
- 8002cdc:	08002d6d 	.word	0x08002d6d
- 8002ce0:	08002d6d 	.word	0x08002d6d
- 8002ce4:	08002d55 	.word	0x08002d55
+ 80034ea:	7ffb      	ldrb	r3, [r7, #31]
+ 80034ec:	2b08      	cmp	r3, #8
+ 80034ee:	d857      	bhi.n	80035a0 <UART_SetConfig+0x508>
+ 80034f0:	a201      	add	r2, pc, #4	; (adr r2, 80034f8 <UART_SetConfig+0x460>)
+ 80034f2:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 80034f6:	bf00      	nop
+ 80034f8:	0800351d 	.word	0x0800351d
+ 80034fc:	08003539 	.word	0x08003539
+ 8003500:	08003555 	.word	0x08003555
+ 8003504:	080035a1 	.word	0x080035a1
+ 8003508:	0800356d 	.word	0x0800356d
+ 800350c:	080035a1 	.word	0x080035a1
+ 8003510:	080035a1 	.word	0x080035a1
+ 8003514:	080035a1 	.word	0x080035a1
+ 8003518:	08003589 	.word	0x08003589
     {
       case UART_CLOCKSOURCE_PCLK1:
         usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- 8002ce8:	f7fe fe62 	bl	80019b0 <HAL_RCC_GetPCLK1Freq>
- 8002cec:	4602      	mov	r2, r0
- 8002cee:	687b      	ldr	r3, [r7, #4]
- 8002cf0:	685b      	ldr	r3, [r3, #4]
- 8002cf2:	085b      	lsrs	r3, r3, #1
- 8002cf4:	441a      	add	r2, r3
- 8002cf6:	687b      	ldr	r3, [r7, #4]
- 8002cf8:	685b      	ldr	r3, [r3, #4]
- 8002cfa:	fbb2 f3f3 	udiv	r3, r2, r3
- 8002cfe:	b29b      	uxth	r3, r3
- 8002d00:	61bb      	str	r3, [r7, #24]
+ 800351c:	f7fe fa62 	bl	80019e4 <HAL_RCC_GetPCLK1Freq>
+ 8003520:	4602      	mov	r2, r0
+ 8003522:	687b      	ldr	r3, [r7, #4]
+ 8003524:	685b      	ldr	r3, [r3, #4]
+ 8003526:	085b      	lsrs	r3, r3, #1
+ 8003528:	441a      	add	r2, r3
+ 800352a:	687b      	ldr	r3, [r7, #4]
+ 800352c:	685b      	ldr	r3, [r3, #4]
+ 800352e:	fbb2 f3f3 	udiv	r3, r2, r3
+ 8003532:	b29b      	uxth	r3, r3
+ 8003534:	61bb      	str	r3, [r7, #24]
         break;
- 8002d02:	e036      	b.n	8002d72 <UART_SetConfig+0x50e>
+ 8003536:	e036      	b.n	80035a6 <UART_SetConfig+0x50e>
       case UART_CLOCKSOURCE_PCLK2:
         usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- 8002d04:	f7fe fe68 	bl	80019d8 <HAL_RCC_GetPCLK2Freq>
- 8002d08:	4602      	mov	r2, r0
- 8002d0a:	687b      	ldr	r3, [r7, #4]
- 8002d0c:	685b      	ldr	r3, [r3, #4]
- 8002d0e:	085b      	lsrs	r3, r3, #1
- 8002d10:	441a      	add	r2, r3
- 8002d12:	687b      	ldr	r3, [r7, #4]
- 8002d14:	685b      	ldr	r3, [r3, #4]
- 8002d16:	fbb2 f3f3 	udiv	r3, r2, r3
- 8002d1a:	b29b      	uxth	r3, r3
- 8002d1c:	61bb      	str	r3, [r7, #24]
+ 8003538:	f7fe fa68 	bl	8001a0c <HAL_RCC_GetPCLK2Freq>
+ 800353c:	4602      	mov	r2, r0
+ 800353e:	687b      	ldr	r3, [r7, #4]
+ 8003540:	685b      	ldr	r3, [r3, #4]
+ 8003542:	085b      	lsrs	r3, r3, #1
+ 8003544:	441a      	add	r2, r3
+ 8003546:	687b      	ldr	r3, [r7, #4]
+ 8003548:	685b      	ldr	r3, [r3, #4]
+ 800354a:	fbb2 f3f3 	udiv	r3, r2, r3
+ 800354e:	b29b      	uxth	r3, r3
+ 8003550:	61bb      	str	r3, [r7, #24]
         break;
- 8002d1e:	e028      	b.n	8002d72 <UART_SetConfig+0x50e>
+ 8003552:	e028      	b.n	80035a6 <UART_SetConfig+0x50e>
       case UART_CLOCKSOURCE_HSI:
         usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
- 8002d20:	687b      	ldr	r3, [r7, #4]
- 8002d22:	685b      	ldr	r3, [r3, #4]
- 8002d24:	085a      	lsrs	r2, r3, #1
- 8002d26:	4b20      	ldr	r3, [pc, #128]	; (8002da8 <UART_SetConfig+0x544>)
- 8002d28:	4413      	add	r3, r2
- 8002d2a:	687a      	ldr	r2, [r7, #4]
- 8002d2c:	6852      	ldr	r2, [r2, #4]
- 8002d2e:	fbb3 f3f2 	udiv	r3, r3, r2
- 8002d32:	b29b      	uxth	r3, r3
- 8002d34:	61bb      	str	r3, [r7, #24]
+ 8003554:	687b      	ldr	r3, [r7, #4]
+ 8003556:	685b      	ldr	r3, [r3, #4]
+ 8003558:	085a      	lsrs	r2, r3, #1
+ 800355a:	4b20      	ldr	r3, [pc, #128]	; (80035dc <UART_SetConfig+0x544>)
+ 800355c:	4413      	add	r3, r2
+ 800355e:	687a      	ldr	r2, [r7, #4]
+ 8003560:	6852      	ldr	r2, [r2, #4]
+ 8003562:	fbb3 f3f2 	udiv	r3, r3, r2
+ 8003566:	b29b      	uxth	r3, r3
+ 8003568:	61bb      	str	r3, [r7, #24]
         break;
- 8002d36:	e01c      	b.n	8002d72 <UART_SetConfig+0x50e>
+ 800356a:	e01c      	b.n	80035a6 <UART_SetConfig+0x50e>
       case UART_CLOCKSOURCE_SYSCLK:
         usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- 8002d38:	f7fe fd7c 	bl	8001834 <HAL_RCC_GetSysClockFreq>
- 8002d3c:	4602      	mov	r2, r0
- 8002d3e:	687b      	ldr	r3, [r7, #4]
- 8002d40:	685b      	ldr	r3, [r3, #4]
- 8002d42:	085b      	lsrs	r3, r3, #1
- 8002d44:	441a      	add	r2, r3
- 8002d46:	687b      	ldr	r3, [r7, #4]
- 8002d48:	685b      	ldr	r3, [r3, #4]
- 8002d4a:	fbb2 f3f3 	udiv	r3, r2, r3
- 8002d4e:	b29b      	uxth	r3, r3
- 8002d50:	61bb      	str	r3, [r7, #24]
+ 800356c:	f7fe f97c 	bl	8001868 <HAL_RCC_GetSysClockFreq>
+ 8003570:	4602      	mov	r2, r0
+ 8003572:	687b      	ldr	r3, [r7, #4]
+ 8003574:	685b      	ldr	r3, [r3, #4]
+ 8003576:	085b      	lsrs	r3, r3, #1
+ 8003578:	441a      	add	r2, r3
+ 800357a:	687b      	ldr	r3, [r7, #4]
+ 800357c:	685b      	ldr	r3, [r3, #4]
+ 800357e:	fbb2 f3f3 	udiv	r3, r2, r3
+ 8003582:	b29b      	uxth	r3, r3
+ 8003584:	61bb      	str	r3, [r7, #24]
         break;
- 8002d52:	e00e      	b.n	8002d72 <UART_SetConfig+0x50e>
+ 8003586:	e00e      	b.n	80035a6 <UART_SetConfig+0x50e>
       case UART_CLOCKSOURCE_LSE:
         usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
- 8002d54:	687b      	ldr	r3, [r7, #4]
- 8002d56:	685b      	ldr	r3, [r3, #4]
- 8002d58:	085b      	lsrs	r3, r3, #1
- 8002d5a:	f503 4200 	add.w	r2, r3, #32768	; 0x8000
- 8002d5e:	687b      	ldr	r3, [r7, #4]
- 8002d60:	685b      	ldr	r3, [r3, #4]
- 8002d62:	fbb2 f3f3 	udiv	r3, r2, r3
- 8002d66:	b29b      	uxth	r3, r3
- 8002d68:	61bb      	str	r3, [r7, #24]
+ 8003588:	687b      	ldr	r3, [r7, #4]
+ 800358a:	685b      	ldr	r3, [r3, #4]
+ 800358c:	085b      	lsrs	r3, r3, #1
+ 800358e:	f503 4200 	add.w	r2, r3, #32768	; 0x8000
+ 8003592:	687b      	ldr	r3, [r7, #4]
+ 8003594:	685b      	ldr	r3, [r3, #4]
+ 8003596:	fbb2 f3f3 	udiv	r3, r2, r3
+ 800359a:	b29b      	uxth	r3, r3
+ 800359c:	61bb      	str	r3, [r7, #24]
         break;
- 8002d6a:	e002      	b.n	8002d72 <UART_SetConfig+0x50e>
+ 800359e:	e002      	b.n	80035a6 <UART_SetConfig+0x50e>
       case UART_CLOCKSOURCE_UNDEFINED:
       default:
         ret = HAL_ERROR;
- 8002d6c:	2301      	movs	r3, #1
- 8002d6e:	75fb      	strb	r3, [r7, #23]
+ 80035a0:	2301      	movs	r3, #1
+ 80035a2:	75fb      	strb	r3, [r7, #23]
         break;
- 8002d70:	bf00      	nop
+ 80035a4:	bf00      	nop
     }
 
     /* USARTDIV must be greater than or equal to 0d16 */
     if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 8002d72:	69bb      	ldr	r3, [r7, #24]
- 8002d74:	2b0f      	cmp	r3, #15
- 8002d76:	d908      	bls.n	8002d8a <UART_SetConfig+0x526>
- 8002d78:	69bb      	ldr	r3, [r7, #24]
- 8002d7a:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
- 8002d7e:	d204      	bcs.n	8002d8a <UART_SetConfig+0x526>
+ 80035a6:	69bb      	ldr	r3, [r7, #24]
+ 80035a8:	2b0f      	cmp	r3, #15
+ 80035aa:	d908      	bls.n	80035be <UART_SetConfig+0x526>
+ 80035ac:	69bb      	ldr	r3, [r7, #24]
+ 80035ae:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 80035b2:	d204      	bcs.n	80035be <UART_SetConfig+0x526>
     {
       huart->Instance->BRR = usartdiv;
- 8002d80:	687b      	ldr	r3, [r7, #4]
- 8002d82:	681b      	ldr	r3, [r3, #0]
- 8002d84:	69ba      	ldr	r2, [r7, #24]
- 8002d86:	60da      	str	r2, [r3, #12]
- 8002d88:	e001      	b.n	8002d8e <UART_SetConfig+0x52a>
+ 80035b4:	687b      	ldr	r3, [r7, #4]
+ 80035b6:	681b      	ldr	r3, [r3, #0]
+ 80035b8:	69ba      	ldr	r2, [r7, #24]
+ 80035ba:	60da      	str	r2, [r3, #12]
+ 80035bc:	e001      	b.n	80035c2 <UART_SetConfig+0x52a>
     }
     else
     {
       ret = HAL_ERROR;
- 8002d8a:	2301      	movs	r3, #1
- 8002d8c:	75fb      	strb	r3, [r7, #23]
+ 80035be:	2301      	movs	r3, #1
+ 80035c0:	75fb      	strb	r3, [r7, #23]
     }
   }
 
 
   /* Clear ISR function pointers */
   huart->RxISR = NULL;
- 8002d8e:	687b      	ldr	r3, [r7, #4]
- 8002d90:	2200      	movs	r2, #0
- 8002d92:	661a      	str	r2, [r3, #96]	; 0x60
+ 80035c2:	687b      	ldr	r3, [r7, #4]
+ 80035c4:	2200      	movs	r2, #0
+ 80035c6:	661a      	str	r2, [r3, #96]	; 0x60
   huart->TxISR = NULL;
- 8002d94:	687b      	ldr	r3, [r7, #4]
- 8002d96:	2200      	movs	r2, #0
- 8002d98:	665a      	str	r2, [r3, #100]	; 0x64
+ 80035c8:	687b      	ldr	r3, [r7, #4]
+ 80035ca:	2200      	movs	r2, #0
+ 80035cc:	665a      	str	r2, [r3, #100]	; 0x64
 
   return ret;
- 8002d9a:	7dfb      	ldrb	r3, [r7, #23]
+ 80035ce:	7dfb      	ldrb	r3, [r7, #23]
 }
- 8002d9c:	4618      	mov	r0, r3
- 8002d9e:	3720      	adds	r7, #32
- 8002da0:	46bd      	mov	sp, r7
- 8002da2:	bd80      	pop	{r7, pc}
- 8002da4:	01e84800 	.word	0x01e84800
- 8002da8:	00f42400 	.word	0x00f42400
-
-08002dac <UART_AdvFeatureConfig>:
+ 80035d0:	4618      	mov	r0, r3
+ 80035d2:	3720      	adds	r7, #32
+ 80035d4:	46bd      	mov	sp, r7
+ 80035d6:	bd80      	pop	{r7, pc}
+ 80035d8:	01e84800 	.word	0x01e84800
+ 80035dc:	00f42400 	.word	0x00f42400
+
+080035e0 <UART_AdvFeatureConfig>:
   * @brief Configure the UART peripheral advanced features.
   * @param huart UART handle.
   * @retval None
   */
 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
 {
- 8002dac:	b480      	push	{r7}
- 8002dae:	b083      	sub	sp, #12
- 8002db0:	af00      	add	r7, sp, #0
- 8002db2:	6078      	str	r0, [r7, #4]
+ 80035e0:	b480      	push	{r7}
+ 80035e2:	b083      	sub	sp, #12
+ 80035e4:	af00      	add	r7, sp, #0
+ 80035e6:	6078      	str	r0, [r7, #4]
   /* Check whether the set of advanced features to configure is properly set */
   assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
 
   /* if required, configure TX pin active level inversion */
   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
- 8002db4:	687b      	ldr	r3, [r7, #4]
- 8002db6:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8002db8:	f003 0301 	and.w	r3, r3, #1
- 8002dbc:	2b00      	cmp	r3, #0
- 8002dbe:	d00a      	beq.n	8002dd6 <UART_AdvFeatureConfig+0x2a>
+ 80035e8:	687b      	ldr	r3, [r7, #4]
+ 80035ea:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80035ec:	f003 0301 	and.w	r3, r3, #1
+ 80035f0:	2b00      	cmp	r3, #0
+ 80035f2:	d00a      	beq.n	800360a <UART_AdvFeatureConfig+0x2a>
   {
     assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
     MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
- 8002dc0:	687b      	ldr	r3, [r7, #4]
- 8002dc2:	681b      	ldr	r3, [r3, #0]
- 8002dc4:	685b      	ldr	r3, [r3, #4]
- 8002dc6:	f423 3100 	bic.w	r1, r3, #131072	; 0x20000
- 8002dca:	687b      	ldr	r3, [r7, #4]
- 8002dcc:	6a9a      	ldr	r2, [r3, #40]	; 0x28
- 8002dce:	687b      	ldr	r3, [r7, #4]
- 8002dd0:	681b      	ldr	r3, [r3, #0]
- 8002dd2:	430a      	orrs	r2, r1
- 8002dd4:	605a      	str	r2, [r3, #4]
+ 80035f4:	687b      	ldr	r3, [r7, #4]
+ 80035f6:	681b      	ldr	r3, [r3, #0]
+ 80035f8:	685b      	ldr	r3, [r3, #4]
+ 80035fa:	f423 3100 	bic.w	r1, r3, #131072	; 0x20000
+ 80035fe:	687b      	ldr	r3, [r7, #4]
+ 8003600:	6a9a      	ldr	r2, [r3, #40]	; 0x28
+ 8003602:	687b      	ldr	r3, [r7, #4]
+ 8003604:	681b      	ldr	r3, [r3, #0]
+ 8003606:	430a      	orrs	r2, r1
+ 8003608:	605a      	str	r2, [r3, #4]
   }
 
   /* if required, configure RX pin active level inversion */
   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
- 8002dd6:	687b      	ldr	r3, [r7, #4]
- 8002dd8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8002dda:	f003 0302 	and.w	r3, r3, #2
- 8002dde:	2b00      	cmp	r3, #0
- 8002de0:	d00a      	beq.n	8002df8 <UART_AdvFeatureConfig+0x4c>
+ 800360a:	687b      	ldr	r3, [r7, #4]
+ 800360c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 800360e:	f003 0302 	and.w	r3, r3, #2
+ 8003612:	2b00      	cmp	r3, #0
+ 8003614:	d00a      	beq.n	800362c <UART_AdvFeatureConfig+0x4c>
   {
     assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
     MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
- 8002de2:	687b      	ldr	r3, [r7, #4]
- 8002de4:	681b      	ldr	r3, [r3, #0]
- 8002de6:	685b      	ldr	r3, [r3, #4]
- 8002de8:	f423 3180 	bic.w	r1, r3, #65536	; 0x10000
- 8002dec:	687b      	ldr	r3, [r7, #4]
- 8002dee:	6ada      	ldr	r2, [r3, #44]	; 0x2c
- 8002df0:	687b      	ldr	r3, [r7, #4]
- 8002df2:	681b      	ldr	r3, [r3, #0]
- 8002df4:	430a      	orrs	r2, r1
- 8002df6:	605a      	str	r2, [r3, #4]
+ 8003616:	687b      	ldr	r3, [r7, #4]
+ 8003618:	681b      	ldr	r3, [r3, #0]
+ 800361a:	685b      	ldr	r3, [r3, #4]
+ 800361c:	f423 3180 	bic.w	r1, r3, #65536	; 0x10000
+ 8003620:	687b      	ldr	r3, [r7, #4]
+ 8003622:	6ada      	ldr	r2, [r3, #44]	; 0x2c
+ 8003624:	687b      	ldr	r3, [r7, #4]
+ 8003626:	681b      	ldr	r3, [r3, #0]
+ 8003628:	430a      	orrs	r2, r1
+ 800362a:	605a      	str	r2, [r3, #4]
   }
 
   /* if required, configure data inversion */
   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
- 8002df8:	687b      	ldr	r3, [r7, #4]
- 8002dfa:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8002dfc:	f003 0304 	and.w	r3, r3, #4
- 8002e00:	2b00      	cmp	r3, #0
- 8002e02:	d00a      	beq.n	8002e1a <UART_AdvFeatureConfig+0x6e>
+ 800362c:	687b      	ldr	r3, [r7, #4]
+ 800362e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8003630:	f003 0304 	and.w	r3, r3, #4
+ 8003634:	2b00      	cmp	r3, #0
+ 8003636:	d00a      	beq.n	800364e <UART_AdvFeatureConfig+0x6e>
   {
     assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
     MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
- 8002e04:	687b      	ldr	r3, [r7, #4]
- 8002e06:	681b      	ldr	r3, [r3, #0]
- 8002e08:	685b      	ldr	r3, [r3, #4]
- 8002e0a:	f423 2180 	bic.w	r1, r3, #262144	; 0x40000
- 8002e0e:	687b      	ldr	r3, [r7, #4]
- 8002e10:	6b1a      	ldr	r2, [r3, #48]	; 0x30
- 8002e12:	687b      	ldr	r3, [r7, #4]
- 8002e14:	681b      	ldr	r3, [r3, #0]
- 8002e16:	430a      	orrs	r2, r1
- 8002e18:	605a      	str	r2, [r3, #4]
+ 8003638:	687b      	ldr	r3, [r7, #4]
+ 800363a:	681b      	ldr	r3, [r3, #0]
+ 800363c:	685b      	ldr	r3, [r3, #4]
+ 800363e:	f423 2180 	bic.w	r1, r3, #262144	; 0x40000
+ 8003642:	687b      	ldr	r3, [r7, #4]
+ 8003644:	6b1a      	ldr	r2, [r3, #48]	; 0x30
+ 8003646:	687b      	ldr	r3, [r7, #4]
+ 8003648:	681b      	ldr	r3, [r3, #0]
+ 800364a:	430a      	orrs	r2, r1
+ 800364c:	605a      	str	r2, [r3, #4]
   }
 
   /* if required, configure RX/TX pins swap */
   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
- 8002e1a:	687b      	ldr	r3, [r7, #4]
- 8002e1c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8002e1e:	f003 0308 	and.w	r3, r3, #8
- 8002e22:	2b00      	cmp	r3, #0
- 8002e24:	d00a      	beq.n	8002e3c <UART_AdvFeatureConfig+0x90>
+ 800364e:	687b      	ldr	r3, [r7, #4]
+ 8003650:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8003652:	f003 0308 	and.w	r3, r3, #8
+ 8003656:	2b00      	cmp	r3, #0
+ 8003658:	d00a      	beq.n	8003670 <UART_AdvFeatureConfig+0x90>
   {
     assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
     MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
- 8002e26:	687b      	ldr	r3, [r7, #4]
- 8002e28:	681b      	ldr	r3, [r3, #0]
- 8002e2a:	685b      	ldr	r3, [r3, #4]
- 8002e2c:	f423 4100 	bic.w	r1, r3, #32768	; 0x8000
- 8002e30:	687b      	ldr	r3, [r7, #4]
- 8002e32:	6b5a      	ldr	r2, [r3, #52]	; 0x34
- 8002e34:	687b      	ldr	r3, [r7, #4]
- 8002e36:	681b      	ldr	r3, [r3, #0]
- 8002e38:	430a      	orrs	r2, r1
- 8002e3a:	605a      	str	r2, [r3, #4]
+ 800365a:	687b      	ldr	r3, [r7, #4]
+ 800365c:	681b      	ldr	r3, [r3, #0]
+ 800365e:	685b      	ldr	r3, [r3, #4]
+ 8003660:	f423 4100 	bic.w	r1, r3, #32768	; 0x8000
+ 8003664:	687b      	ldr	r3, [r7, #4]
+ 8003666:	6b5a      	ldr	r2, [r3, #52]	; 0x34
+ 8003668:	687b      	ldr	r3, [r7, #4]
+ 800366a:	681b      	ldr	r3, [r3, #0]
+ 800366c:	430a      	orrs	r2, r1
+ 800366e:	605a      	str	r2, [r3, #4]
   }
 
   /* if required, configure RX overrun detection disabling */
   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
- 8002e3c:	687b      	ldr	r3, [r7, #4]
- 8002e3e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8002e40:	f003 0310 	and.w	r3, r3, #16
- 8002e44:	2b00      	cmp	r3, #0
- 8002e46:	d00a      	beq.n	8002e5e <UART_AdvFeatureConfig+0xb2>
+ 8003670:	687b      	ldr	r3, [r7, #4]
+ 8003672:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8003674:	f003 0310 	and.w	r3, r3, #16
+ 8003678:	2b00      	cmp	r3, #0
+ 800367a:	d00a      	beq.n	8003692 <UART_AdvFeatureConfig+0xb2>
   {
     assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
     MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
- 8002e48:	687b      	ldr	r3, [r7, #4]
- 8002e4a:	681b      	ldr	r3, [r3, #0]
- 8002e4c:	689b      	ldr	r3, [r3, #8]
- 8002e4e:	f423 5180 	bic.w	r1, r3, #4096	; 0x1000
- 8002e52:	687b      	ldr	r3, [r7, #4]
- 8002e54:	6b9a      	ldr	r2, [r3, #56]	; 0x38
- 8002e56:	687b      	ldr	r3, [r7, #4]
- 8002e58:	681b      	ldr	r3, [r3, #0]
- 8002e5a:	430a      	orrs	r2, r1
- 8002e5c:	609a      	str	r2, [r3, #8]
+ 800367c:	687b      	ldr	r3, [r7, #4]
+ 800367e:	681b      	ldr	r3, [r3, #0]
+ 8003680:	689b      	ldr	r3, [r3, #8]
+ 8003682:	f423 5180 	bic.w	r1, r3, #4096	; 0x1000
+ 8003686:	687b      	ldr	r3, [r7, #4]
+ 8003688:	6b9a      	ldr	r2, [r3, #56]	; 0x38
+ 800368a:	687b      	ldr	r3, [r7, #4]
+ 800368c:	681b      	ldr	r3, [r3, #0]
+ 800368e:	430a      	orrs	r2, r1
+ 8003690:	609a      	str	r2, [r3, #8]
   }
 
   /* if required, configure DMA disabling on reception error */
   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
- 8002e5e:	687b      	ldr	r3, [r7, #4]
- 8002e60:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8002e62:	f003 0320 	and.w	r3, r3, #32
- 8002e66:	2b00      	cmp	r3, #0
- 8002e68:	d00a      	beq.n	8002e80 <UART_AdvFeatureConfig+0xd4>
+ 8003692:	687b      	ldr	r3, [r7, #4]
+ 8003694:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 8003696:	f003 0320 	and.w	r3, r3, #32
+ 800369a:	2b00      	cmp	r3, #0
+ 800369c:	d00a      	beq.n	80036b4 <UART_AdvFeatureConfig+0xd4>
   {
     assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
     MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
- 8002e6a:	687b      	ldr	r3, [r7, #4]
- 8002e6c:	681b      	ldr	r3, [r3, #0]
- 8002e6e:	689b      	ldr	r3, [r3, #8]
- 8002e70:	f423 5100 	bic.w	r1, r3, #8192	; 0x2000
- 8002e74:	687b      	ldr	r3, [r7, #4]
- 8002e76:	6bda      	ldr	r2, [r3, #60]	; 0x3c
- 8002e78:	687b      	ldr	r3, [r7, #4]
- 8002e7a:	681b      	ldr	r3, [r3, #0]
- 8002e7c:	430a      	orrs	r2, r1
- 8002e7e:	609a      	str	r2, [r3, #8]
+ 800369e:	687b      	ldr	r3, [r7, #4]
+ 80036a0:	681b      	ldr	r3, [r3, #0]
+ 80036a2:	689b      	ldr	r3, [r3, #8]
+ 80036a4:	f423 5100 	bic.w	r1, r3, #8192	; 0x2000
+ 80036a8:	687b      	ldr	r3, [r7, #4]
+ 80036aa:	6bda      	ldr	r2, [r3, #60]	; 0x3c
+ 80036ac:	687b      	ldr	r3, [r7, #4]
+ 80036ae:	681b      	ldr	r3, [r3, #0]
+ 80036b0:	430a      	orrs	r2, r1
+ 80036b2:	609a      	str	r2, [r3, #8]
   }
 
   /* if required, configure auto Baud rate detection scheme */
   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
- 8002e80:	687b      	ldr	r3, [r7, #4]
- 8002e82:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8002e84:	f003 0340 	and.w	r3, r3, #64	; 0x40
- 8002e88:	2b00      	cmp	r3, #0
- 8002e8a:	d01a      	beq.n	8002ec2 <UART_AdvFeatureConfig+0x116>
+ 80036b4:	687b      	ldr	r3, [r7, #4]
+ 80036b6:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80036b8:	f003 0340 	and.w	r3, r3, #64	; 0x40
+ 80036bc:	2b00      	cmp	r3, #0
+ 80036be:	d01a      	beq.n	80036f6 <UART_AdvFeatureConfig+0x116>
   {
     assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
     assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
     MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
- 8002e8c:	687b      	ldr	r3, [r7, #4]
- 8002e8e:	681b      	ldr	r3, [r3, #0]
- 8002e90:	685b      	ldr	r3, [r3, #4]
- 8002e92:	f423 1180 	bic.w	r1, r3, #1048576	; 0x100000
- 8002e96:	687b      	ldr	r3, [r7, #4]
- 8002e98:	6c1a      	ldr	r2, [r3, #64]	; 0x40
- 8002e9a:	687b      	ldr	r3, [r7, #4]
- 8002e9c:	681b      	ldr	r3, [r3, #0]
- 8002e9e:	430a      	orrs	r2, r1
- 8002ea0:	605a      	str	r2, [r3, #4]
+ 80036c0:	687b      	ldr	r3, [r7, #4]
+ 80036c2:	681b      	ldr	r3, [r3, #0]
+ 80036c4:	685b      	ldr	r3, [r3, #4]
+ 80036c6:	f423 1180 	bic.w	r1, r3, #1048576	; 0x100000
+ 80036ca:	687b      	ldr	r3, [r7, #4]
+ 80036cc:	6c1a      	ldr	r2, [r3, #64]	; 0x40
+ 80036ce:	687b      	ldr	r3, [r7, #4]
+ 80036d0:	681b      	ldr	r3, [r3, #0]
+ 80036d2:	430a      	orrs	r2, r1
+ 80036d4:	605a      	str	r2, [r3, #4]
     /* set auto Baudrate detection parameters if detection is enabled */
     if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
- 8002ea2:	687b      	ldr	r3, [r7, #4]
- 8002ea4:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 8002ea6:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
- 8002eaa:	d10a      	bne.n	8002ec2 <UART_AdvFeatureConfig+0x116>
+ 80036d6:	687b      	ldr	r3, [r7, #4]
+ 80036d8:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 80036da:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
+ 80036de:	d10a      	bne.n	80036f6 <UART_AdvFeatureConfig+0x116>
     {
       assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
       MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
- 8002eac:	687b      	ldr	r3, [r7, #4]
- 8002eae:	681b      	ldr	r3, [r3, #0]
- 8002eb0:	685b      	ldr	r3, [r3, #4]
- 8002eb2:	f423 01c0 	bic.w	r1, r3, #6291456	; 0x600000
- 8002eb6:	687b      	ldr	r3, [r7, #4]
- 8002eb8:	6c5a      	ldr	r2, [r3, #68]	; 0x44
- 8002eba:	687b      	ldr	r3, [r7, #4]
- 8002ebc:	681b      	ldr	r3, [r3, #0]
- 8002ebe:	430a      	orrs	r2, r1
- 8002ec0:	605a      	str	r2, [r3, #4]
+ 80036e0:	687b      	ldr	r3, [r7, #4]
+ 80036e2:	681b      	ldr	r3, [r3, #0]
+ 80036e4:	685b      	ldr	r3, [r3, #4]
+ 80036e6:	f423 01c0 	bic.w	r1, r3, #6291456	; 0x600000
+ 80036ea:	687b      	ldr	r3, [r7, #4]
+ 80036ec:	6c5a      	ldr	r2, [r3, #68]	; 0x44
+ 80036ee:	687b      	ldr	r3, [r7, #4]
+ 80036f0:	681b      	ldr	r3, [r3, #0]
+ 80036f2:	430a      	orrs	r2, r1
+ 80036f4:	605a      	str	r2, [r3, #4]
     }
   }
 
   /* if required, configure MSB first on communication line */
   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
- 8002ec2:	687b      	ldr	r3, [r7, #4]
- 8002ec4:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8002ec6:	f003 0380 	and.w	r3, r3, #128	; 0x80
- 8002eca:	2b00      	cmp	r3, #0
- 8002ecc:	d00a      	beq.n	8002ee4 <UART_AdvFeatureConfig+0x138>
+ 80036f6:	687b      	ldr	r3, [r7, #4]
+ 80036f8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+ 80036fa:	f003 0380 	and.w	r3, r3, #128	; 0x80
+ 80036fe:	2b00      	cmp	r3, #0
+ 8003700:	d00a      	beq.n	8003718 <UART_AdvFeatureConfig+0x138>
   {
     assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
     MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
- 8002ece:	687b      	ldr	r3, [r7, #4]
- 8002ed0:	681b      	ldr	r3, [r3, #0]
- 8002ed2:	685b      	ldr	r3, [r3, #4]
- 8002ed4:	f423 2100 	bic.w	r1, r3, #524288	; 0x80000
- 8002ed8:	687b      	ldr	r3, [r7, #4]
- 8002eda:	6c9a      	ldr	r2, [r3, #72]	; 0x48
- 8002edc:	687b      	ldr	r3, [r7, #4]
- 8002ede:	681b      	ldr	r3, [r3, #0]
- 8002ee0:	430a      	orrs	r2, r1
- 8002ee2:	605a      	str	r2, [r3, #4]
+ 8003702:	687b      	ldr	r3, [r7, #4]
+ 8003704:	681b      	ldr	r3, [r3, #0]
+ 8003706:	685b      	ldr	r3, [r3, #4]
+ 8003708:	f423 2100 	bic.w	r1, r3, #524288	; 0x80000
+ 800370c:	687b      	ldr	r3, [r7, #4]
+ 800370e:	6c9a      	ldr	r2, [r3, #72]	; 0x48
+ 8003710:	687b      	ldr	r3, [r7, #4]
+ 8003712:	681b      	ldr	r3, [r3, #0]
+ 8003714:	430a      	orrs	r2, r1
+ 8003716:	605a      	str	r2, [r3, #4]
   }
 }
- 8002ee4:	bf00      	nop
- 8002ee6:	370c      	adds	r7, #12
- 8002ee8:	46bd      	mov	sp, r7
- 8002eea:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8002eee:	4770      	bx	lr
+ 8003718:	bf00      	nop
+ 800371a:	370c      	adds	r7, #12
+ 800371c:	46bd      	mov	sp, r7
+ 800371e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8003722:	4770      	bx	lr
 
-08002ef0 <UART_CheckIdleState>:
+08003724 <UART_CheckIdleState>:
   * @brief Check the UART Idle State.
   * @param huart UART handle.
   * @retval HAL status
   */
 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
 {
- 8002ef0:	b580      	push	{r7, lr}
- 8002ef2:	b086      	sub	sp, #24
- 8002ef4:	af02      	add	r7, sp, #8
- 8002ef6:	6078      	str	r0, [r7, #4]
+ 8003724:	b580      	push	{r7, lr}
+ 8003726:	b086      	sub	sp, #24
+ 8003728:	af02      	add	r7, sp, #8
+ 800372a:	6078      	str	r0, [r7, #4]
   uint32_t tickstart;
 
   /* Initialize the UART ErrorCode */
   huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8002ef8:	687b      	ldr	r3, [r7, #4]
- 8002efa:	2200      	movs	r2, #0
- 8002efc:	67da      	str	r2, [r3, #124]	; 0x7c
+ 800372c:	687b      	ldr	r3, [r7, #4]
+ 800372e:	2200      	movs	r2, #0
+ 8003730:	67da      	str	r2, [r3, #124]	; 0x7c
 
   /* Init tickstart for timeout managment*/
   tickstart = HAL_GetTick();
- 8002efe:	f7fd fb6d 	bl	80005dc <HAL_GetTick>
- 8002f02:	60f8      	str	r0, [r7, #12]
+ 8003732:	f7fc ff53 	bl	80005dc <HAL_GetTick>
+ 8003736:	60f8      	str	r0, [r7, #12]
 
   /* Check if the Transmitter is enabled */
   if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- 8002f04:	687b      	ldr	r3, [r7, #4]
- 8002f06:	681b      	ldr	r3, [r3, #0]
- 8002f08:	681b      	ldr	r3, [r3, #0]
- 8002f0a:	f003 0308 	and.w	r3, r3, #8
- 8002f0e:	2b08      	cmp	r3, #8
- 8002f10:	d10e      	bne.n	8002f30 <UART_CheckIdleState+0x40>
+ 8003738:	687b      	ldr	r3, [r7, #4]
+ 800373a:	681b      	ldr	r3, [r3, #0]
+ 800373c:	681b      	ldr	r3, [r3, #0]
+ 800373e:	f003 0308 	and.w	r3, r3, #8
+ 8003742:	2b08      	cmp	r3, #8
+ 8003744:	d10e      	bne.n	8003764 <UART_CheckIdleState+0x40>
   {
     /* Wait until TEACK flag is set */
     if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- 8002f12:	f06f 437e 	mvn.w	r3, #4261412864	; 0xfe000000
- 8002f16:	9300      	str	r3, [sp, #0]
- 8002f18:	68fb      	ldr	r3, [r7, #12]
- 8002f1a:	2200      	movs	r2, #0
- 8002f1c:	f44f 1100 	mov.w	r1, #2097152	; 0x200000
- 8002f20:	6878      	ldr	r0, [r7, #4]
- 8002f22:	f000 f814 	bl	8002f4e <UART_WaitOnFlagUntilTimeout>
- 8002f26:	4603      	mov	r3, r0
- 8002f28:	2b00      	cmp	r3, #0
- 8002f2a:	d001      	beq.n	8002f30 <UART_CheckIdleState+0x40>
+ 8003746:	f06f 437e 	mvn.w	r3, #4261412864	; 0xfe000000
+ 800374a:	9300      	str	r3, [sp, #0]
+ 800374c:	68fb      	ldr	r3, [r7, #12]
+ 800374e:	2200      	movs	r2, #0
+ 8003750:	f44f 1100 	mov.w	r1, #2097152	; 0x200000
+ 8003754:	6878      	ldr	r0, [r7, #4]
+ 8003756:	f000 f814 	bl	8003782 <UART_WaitOnFlagUntilTimeout>
+ 800375a:	4603      	mov	r3, r0
+ 800375c:	2b00      	cmp	r3, #0
+ 800375e:	d001      	beq.n	8003764 <UART_CheckIdleState+0x40>
     {
       /* Timeout occurred */
       return HAL_TIMEOUT;
- 8002f2c:	2303      	movs	r3, #3
- 8002f2e:	e00a      	b.n	8002f46 <UART_CheckIdleState+0x56>
+ 8003760:	2303      	movs	r3, #3
+ 8003762:	e00a      	b.n	800377a <UART_CheckIdleState+0x56>
     }
   }
 
   /* Initialize the UART State */
   huart->gState = HAL_UART_STATE_READY;
- 8002f30:	687b      	ldr	r3, [r7, #4]
- 8002f32:	2220      	movs	r2, #32
- 8002f34:	675a      	str	r2, [r3, #116]	; 0x74
+ 8003764:	687b      	ldr	r3, [r7, #4]
+ 8003766:	2220      	movs	r2, #32
+ 8003768:	675a      	str	r2, [r3, #116]	; 0x74
   huart->RxState = HAL_UART_STATE_READY;
- 8002f36:	687b      	ldr	r3, [r7, #4]
- 8002f38:	2220      	movs	r2, #32
- 8002f3a:	679a      	str	r2, [r3, #120]	; 0x78
+ 800376a:	687b      	ldr	r3, [r7, #4]
+ 800376c:	2220      	movs	r2, #32
+ 800376e:	679a      	str	r2, [r3, #120]	; 0x78
 
   /* Process Unlocked */
   __HAL_UNLOCK(huart);
- 8002f3c:	687b      	ldr	r3, [r7, #4]
- 8002f3e:	2200      	movs	r2, #0
- 8002f40:	f883 2070 	strb.w	r2, [r3, #112]	; 0x70
+ 8003770:	687b      	ldr	r3, [r7, #4]
+ 8003772:	2200      	movs	r2, #0
+ 8003774:	f883 2070 	strb.w	r2, [r3, #112]	; 0x70
 
   return HAL_OK;
- 8002f44:	2300      	movs	r3, #0
+ 8003778:	2300      	movs	r3, #0
 }
- 8002f46:	4618      	mov	r0, r3
- 8002f48:	3710      	adds	r7, #16
- 8002f4a:	46bd      	mov	sp, r7
- 8002f4c:	bd80      	pop	{r7, pc}
+ 800377a:	4618      	mov	r0, r3
+ 800377c:	3710      	adds	r7, #16
+ 800377e:	46bd      	mov	sp, r7
+ 8003780:	bd80      	pop	{r7, pc}
 
-08002f4e <UART_WaitOnFlagUntilTimeout>:
+08003782 <UART_WaitOnFlagUntilTimeout>:
   * @param Tickstart Tick start value
   * @param Timeout   Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
 {
- 8002f4e:	b580      	push	{r7, lr}
- 8002f50:	b084      	sub	sp, #16
- 8002f52:	af00      	add	r7, sp, #0
- 8002f54:	60f8      	str	r0, [r7, #12]
- 8002f56:	60b9      	str	r1, [r7, #8]
- 8002f58:	603b      	str	r3, [r7, #0]
- 8002f5a:	4613      	mov	r3, r2
- 8002f5c:	71fb      	strb	r3, [r7, #7]
+ 8003782:	b580      	push	{r7, lr}
+ 8003784:	b084      	sub	sp, #16
+ 8003786:	af00      	add	r7, sp, #0
+ 8003788:	60f8      	str	r0, [r7, #12]
+ 800378a:	60b9      	str	r1, [r7, #8]
+ 800378c:	603b      	str	r3, [r7, #0]
+ 800378e:	4613      	mov	r3, r2
+ 8003790:	71fb      	strb	r3, [r7, #7]
   /* Wait until flag is set */
   while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 8002f5e:	e02a      	b.n	8002fb6 <UART_WaitOnFlagUntilTimeout+0x68>
+ 8003792:	e02a      	b.n	80037ea <UART_WaitOnFlagUntilTimeout+0x68>
   {
     /* Check for the Timeout */
     if (Timeout != HAL_MAX_DELAY)
- 8002f60:	69bb      	ldr	r3, [r7, #24]
- 8002f62:	f1b3 3fff 	cmp.w	r3, #4294967295	; 0xffffffff
- 8002f66:	d026      	beq.n	8002fb6 <UART_WaitOnFlagUntilTimeout+0x68>
+ 8003794:	69bb      	ldr	r3, [r7, #24]
+ 8003796:	f1b3 3fff 	cmp.w	r3, #4294967295	; 0xffffffff
+ 800379a:	d026      	beq.n	80037ea <UART_WaitOnFlagUntilTimeout+0x68>
     {
       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 8002f68:	f7fd fb38 	bl	80005dc <HAL_GetTick>
- 8002f6c:	4602      	mov	r2, r0
- 8002f6e:	683b      	ldr	r3, [r7, #0]
- 8002f70:	1ad3      	subs	r3, r2, r3
- 8002f72:	69ba      	ldr	r2, [r7, #24]
- 8002f74:	429a      	cmp	r2, r3
- 8002f76:	d302      	bcc.n	8002f7e <UART_WaitOnFlagUntilTimeout+0x30>
- 8002f78:	69bb      	ldr	r3, [r7, #24]
- 8002f7a:	2b00      	cmp	r3, #0
- 8002f7c:	d11b      	bne.n	8002fb6 <UART_WaitOnFlagUntilTimeout+0x68>
+ 800379c:	f7fc ff1e 	bl	80005dc <HAL_GetTick>
+ 80037a0:	4602      	mov	r2, r0
+ 80037a2:	683b      	ldr	r3, [r7, #0]
+ 80037a4:	1ad3      	subs	r3, r2, r3
+ 80037a6:	69ba      	ldr	r2, [r7, #24]
+ 80037a8:	429a      	cmp	r2, r3
+ 80037aa:	d302      	bcc.n	80037b2 <UART_WaitOnFlagUntilTimeout+0x30>
+ 80037ac:	69bb      	ldr	r3, [r7, #24]
+ 80037ae:	2b00      	cmp	r3, #0
+ 80037b0:	d11b      	bne.n	80037ea <UART_WaitOnFlagUntilTimeout+0x68>
       {
         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
         CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- 8002f7e:	68fb      	ldr	r3, [r7, #12]
- 8002f80:	681b      	ldr	r3, [r3, #0]
- 8002f82:	681a      	ldr	r2, [r3, #0]
- 8002f84:	68fb      	ldr	r3, [r7, #12]
- 8002f86:	681b      	ldr	r3, [r3, #0]
- 8002f88:	f422 72d0 	bic.w	r2, r2, #416	; 0x1a0
- 8002f8c:	601a      	str	r2, [r3, #0]
+ 80037b2:	68fb      	ldr	r3, [r7, #12]
+ 80037b4:	681b      	ldr	r3, [r3, #0]
+ 80037b6:	681a      	ldr	r2, [r3, #0]
+ 80037b8:	68fb      	ldr	r3, [r7, #12]
+ 80037ba:	681b      	ldr	r3, [r3, #0]
+ 80037bc:	f422 72d0 	bic.w	r2, r2, #416	; 0x1a0
+ 80037c0:	601a      	str	r2, [r3, #0]
         CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 8002f8e:	68fb      	ldr	r3, [r7, #12]
- 8002f90:	681b      	ldr	r3, [r3, #0]
- 8002f92:	689a      	ldr	r2, [r3, #8]
- 8002f94:	68fb      	ldr	r3, [r7, #12]
- 8002f96:	681b      	ldr	r3, [r3, #0]
- 8002f98:	f022 0201 	bic.w	r2, r2, #1
- 8002f9c:	609a      	str	r2, [r3, #8]
+ 80037c2:	68fb      	ldr	r3, [r7, #12]
+ 80037c4:	681b      	ldr	r3, [r3, #0]
+ 80037c6:	689a      	ldr	r2, [r3, #8]
+ 80037c8:	68fb      	ldr	r3, [r7, #12]
+ 80037ca:	681b      	ldr	r3, [r3, #0]
+ 80037cc:	f022 0201 	bic.w	r2, r2, #1
+ 80037d0:	609a      	str	r2, [r3, #8]
 
         huart->gState = HAL_UART_STATE_READY;
- 8002f9e:	68fb      	ldr	r3, [r7, #12]
- 8002fa0:	2220      	movs	r2, #32
- 8002fa2:	675a      	str	r2, [r3, #116]	; 0x74
+ 80037d2:	68fb      	ldr	r3, [r7, #12]
+ 80037d4:	2220      	movs	r2, #32
+ 80037d6:	675a      	str	r2, [r3, #116]	; 0x74
         huart->RxState = HAL_UART_STATE_READY;
- 8002fa4:	68fb      	ldr	r3, [r7, #12]
- 8002fa6:	2220      	movs	r2, #32
- 8002fa8:	679a      	str	r2, [r3, #120]	; 0x78
+ 80037d8:	68fb      	ldr	r3, [r7, #12]
+ 80037da:	2220      	movs	r2, #32
+ 80037dc:	679a      	str	r2, [r3, #120]	; 0x78
 
         /* Process Unlocked */
         __HAL_UNLOCK(huart);
- 8002faa:	68fb      	ldr	r3, [r7, #12]
- 8002fac:	2200      	movs	r2, #0
- 8002fae:	f883 2070 	strb.w	r2, [r3, #112]	; 0x70
+ 80037de:	68fb      	ldr	r3, [r7, #12]
+ 80037e0:	2200      	movs	r2, #0
+ 80037e2:	f883 2070 	strb.w	r2, [r3, #112]	; 0x70
 
         return HAL_TIMEOUT;
- 8002fb2:	2303      	movs	r3, #3
- 8002fb4:	e00f      	b.n	8002fd6 <UART_WaitOnFlagUntilTimeout+0x88>
+ 80037e6:	2303      	movs	r3, #3
+ 80037e8:	e00f      	b.n	800380a <UART_WaitOnFlagUntilTimeout+0x88>
   while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 8002fb6:	68fb      	ldr	r3, [r7, #12]
- 8002fb8:	681b      	ldr	r3, [r3, #0]
- 8002fba:	69da      	ldr	r2, [r3, #28]
- 8002fbc:	68bb      	ldr	r3, [r7, #8]
- 8002fbe:	4013      	ands	r3, r2
- 8002fc0:	68ba      	ldr	r2, [r7, #8]
- 8002fc2:	429a      	cmp	r2, r3
- 8002fc4:	bf0c      	ite	eq
- 8002fc6:	2301      	moveq	r3, #1
- 8002fc8:	2300      	movne	r3, #0
- 8002fca:	b2db      	uxtb	r3, r3
- 8002fcc:	461a      	mov	r2, r3
- 8002fce:	79fb      	ldrb	r3, [r7, #7]
- 8002fd0:	429a      	cmp	r2, r3
- 8002fd2:	d0c5      	beq.n	8002f60 <UART_WaitOnFlagUntilTimeout+0x12>
+ 80037ea:	68fb      	ldr	r3, [r7, #12]
+ 80037ec:	681b      	ldr	r3, [r3, #0]
+ 80037ee:	69da      	ldr	r2, [r3, #28]
+ 80037f0:	68bb      	ldr	r3, [r7, #8]
+ 80037f2:	4013      	ands	r3, r2
+ 80037f4:	68ba      	ldr	r2, [r7, #8]
+ 80037f6:	429a      	cmp	r2, r3
+ 80037f8:	bf0c      	ite	eq
+ 80037fa:	2301      	moveq	r3, #1
+ 80037fc:	2300      	movne	r3, #0
+ 80037fe:	b2db      	uxtb	r3, r3
+ 8003800:	461a      	mov	r2, r3
+ 8003802:	79fb      	ldrb	r3, [r7, #7]
+ 8003804:	429a      	cmp	r2, r3
+ 8003806:	d0c5      	beq.n	8003794 <UART_WaitOnFlagUntilTimeout+0x12>
       }
     }
   }
   return HAL_OK;
- 8002fd4:	2300      	movs	r3, #0
+ 8003808:	2300      	movs	r3, #0
 }
- 8002fd6:	4618      	mov	r0, r3
- 8002fd8:	3710      	adds	r7, #16
- 8002fda:	46bd      	mov	sp, r7
- 8002fdc:	bd80      	pop	{r7, pc}
+ 800380a:	4618      	mov	r0, r3
+ 800380c:	3710      	adds	r7, #16
+ 800380e:	46bd      	mov	sp, r7
+ 8003810:	bd80      	pop	{r7, pc}
 
-08002fde <UART_EndRxTransfer>:
+08003812 <UART_EndRxTransfer>:
   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
   * @param  huart UART handle.
   * @retval None
   */
 static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
 {
- 8002fde:	b480      	push	{r7}
- 8002fe0:	b083      	sub	sp, #12
- 8002fe2:	af00      	add	r7, sp, #0
- 8002fe4:	6078      	str	r0, [r7, #4]
+ 8003812:	b480      	push	{r7}
+ 8003814:	b083      	sub	sp, #12
+ 8003816:	af00      	add	r7, sp, #0
+ 8003818:	6078      	str	r0, [r7, #4]
   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 8002fe6:	687b      	ldr	r3, [r7, #4]
- 8002fe8:	681b      	ldr	r3, [r3, #0]
- 8002fea:	681a      	ldr	r2, [r3, #0]
- 8002fec:	687b      	ldr	r3, [r7, #4]
- 8002fee:	681b      	ldr	r3, [r3, #0]
- 8002ff0:	f422 7290 	bic.w	r2, r2, #288	; 0x120
- 8002ff4:	601a      	str	r2, [r3, #0]
+ 800381a:	687b      	ldr	r3, [r7, #4]
+ 800381c:	681b      	ldr	r3, [r3, #0]
+ 800381e:	681a      	ldr	r2, [r3, #0]
+ 8003820:	687b      	ldr	r3, [r7, #4]
+ 8003822:	681b      	ldr	r3, [r3, #0]
+ 8003824:	f422 7290 	bic.w	r2, r2, #288	; 0x120
+ 8003828:	601a      	str	r2, [r3, #0]
   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 8002ff6:	687b      	ldr	r3, [r7, #4]
- 8002ff8:	681b      	ldr	r3, [r3, #0]
- 8002ffa:	689a      	ldr	r2, [r3, #8]
- 8002ffc:	687b      	ldr	r3, [r7, #4]
- 8002ffe:	681b      	ldr	r3, [r3, #0]
- 8003000:	f022 0201 	bic.w	r2, r2, #1
- 8003004:	609a      	str	r2, [r3, #8]
+ 800382a:	687b      	ldr	r3, [r7, #4]
+ 800382c:	681b      	ldr	r3, [r3, #0]
+ 800382e:	689a      	ldr	r2, [r3, #8]
+ 8003830:	687b      	ldr	r3, [r7, #4]
+ 8003832:	681b      	ldr	r3, [r3, #0]
+ 8003834:	f022 0201 	bic.w	r2, r2, #1
+ 8003838:	609a      	str	r2, [r3, #8]
 
   /* At end of Rx process, restore huart->RxState to Ready */
   huart->RxState = HAL_UART_STATE_READY;
- 8003006:	687b      	ldr	r3, [r7, #4]
- 8003008:	2220      	movs	r2, #32
- 800300a:	679a      	str	r2, [r3, #120]	; 0x78
+ 800383a:	687b      	ldr	r3, [r7, #4]
+ 800383c:	2220      	movs	r2, #32
+ 800383e:	679a      	str	r2, [r3, #120]	; 0x78
 
   /* Reset RxIsr function pointer */
   huart->RxISR = NULL;
- 800300c:	687b      	ldr	r3, [r7, #4]
- 800300e:	2200      	movs	r2, #0
- 8003010:	661a      	str	r2, [r3, #96]	; 0x60
+ 8003840:	687b      	ldr	r3, [r7, #4]
+ 8003842:	2200      	movs	r2, #0
+ 8003844:	661a      	str	r2, [r3, #96]	; 0x60
 }
- 8003012:	bf00      	nop
- 8003014:	370c      	adds	r7, #12
- 8003016:	46bd      	mov	sp, r7
- 8003018:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800301c:	4770      	bx	lr
+ 8003846:	bf00      	nop
+ 8003848:	370c      	adds	r7, #12
+ 800384a:	46bd      	mov	sp, r7
+ 800384c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8003850:	4770      	bx	lr
 
-0800301e <UART_DMAAbortOnError>:
+08003852 <UART_DMAAbortOnError>:
   *         (To be called at end of DMA Abort procedure following error occurrence).
   * @param  hdma DMA handle.
   * @retval None
   */
 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
 {
- 800301e:	b580      	push	{r7, lr}
- 8003020:	b084      	sub	sp, #16
- 8003022:	af00      	add	r7, sp, #0
- 8003024:	6078      	str	r0, [r7, #4]
+ 8003852:	b580      	push	{r7, lr}
+ 8003854:	b084      	sub	sp, #16
+ 8003856:	af00      	add	r7, sp, #0
+ 8003858:	6078      	str	r0, [r7, #4]
   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
- 8003026:	687b      	ldr	r3, [r7, #4]
- 8003028:	6b9b      	ldr	r3, [r3, #56]	; 0x38
- 800302a:	60fb      	str	r3, [r7, #12]
+ 800385a:	687b      	ldr	r3, [r7, #4]
+ 800385c:	6b9b      	ldr	r3, [r3, #56]	; 0x38
+ 800385e:	60fb      	str	r3, [r7, #12]
   huart->RxXferCount = 0U;
- 800302c:	68fb      	ldr	r3, [r7, #12]
- 800302e:	2200      	movs	r2, #0
- 8003030:	f8a3 205a 	strh.w	r2, [r3, #90]	; 0x5a
+ 8003860:	68fb      	ldr	r3, [r7, #12]
+ 8003862:	2200      	movs	r2, #0
+ 8003864:	f8a3 205a 	strh.w	r2, [r3, #90]	; 0x5a
   huart->TxXferCount = 0U;
- 8003034:	68fb      	ldr	r3, [r7, #12]
- 8003036:	2200      	movs	r2, #0
- 8003038:	f8a3 2052 	strh.w	r2, [r3, #82]	; 0x52
+ 8003868:	68fb      	ldr	r3, [r7, #12]
+ 800386a:	2200      	movs	r2, #0
+ 800386c:	f8a3 2052 	strh.w	r2, [r3, #82]	; 0x52
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
   /*Call registered error callback*/
   huart->ErrorCallback(huart);
 #else
   /*Call legacy weak error callback*/
   HAL_UART_ErrorCallback(huart);
- 800303c:	68f8      	ldr	r0, [r7, #12]
- 800303e:	f7ff fc07 	bl	8002850 <HAL_UART_ErrorCallback>
+ 8003870:	68f8      	ldr	r0, [r7, #12]
+ 8003872:	f7ff fc07 	bl	8003084 <HAL_UART_ErrorCallback>
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 }
- 8003042:	bf00      	nop
- 8003044:	3710      	adds	r7, #16
- 8003046:	46bd      	mov	sp, r7
- 8003048:	bd80      	pop	{r7, pc}
+ 8003876:	bf00      	nop
+ 8003878:	3710      	adds	r7, #16
+ 800387a:	46bd      	mov	sp, r7
+ 800387c:	bd80      	pop	{r7, pc}
 
-0800304a <UART_EndTransmit_IT>:
+0800387e <UART_EndTransmit_IT>:
   * @param  huart pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval None
   */
 static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
 {
- 800304a:	b580      	push	{r7, lr}
- 800304c:	b082      	sub	sp, #8
- 800304e:	af00      	add	r7, sp, #0
- 8003050:	6078      	str	r0, [r7, #4]
+ 800387e:	b580      	push	{r7, lr}
+ 8003880:	b082      	sub	sp, #8
+ 8003882:	af00      	add	r7, sp, #0
+ 8003884:	6078      	str	r0, [r7, #4]
   /* Disable the UART Transmit Complete Interrupt */
   CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
- 8003052:	687b      	ldr	r3, [r7, #4]
- 8003054:	681b      	ldr	r3, [r3, #0]
- 8003056:	681a      	ldr	r2, [r3, #0]
- 8003058:	687b      	ldr	r3, [r7, #4]
- 800305a:	681b      	ldr	r3, [r3, #0]
- 800305c:	f022 0240 	bic.w	r2, r2, #64	; 0x40
- 8003060:	601a      	str	r2, [r3, #0]
+ 8003886:	687b      	ldr	r3, [r7, #4]
+ 8003888:	681b      	ldr	r3, [r3, #0]
+ 800388a:	681a      	ldr	r2, [r3, #0]
+ 800388c:	687b      	ldr	r3, [r7, #4]
+ 800388e:	681b      	ldr	r3, [r3, #0]
+ 8003890:	f022 0240 	bic.w	r2, r2, #64	; 0x40
+ 8003894:	601a      	str	r2, [r3, #0]
 
   /* Tx process is ended, restore huart->gState to Ready */
   huart->gState = HAL_UART_STATE_READY;
- 8003062:	687b      	ldr	r3, [r7, #4]
- 8003064:	2220      	movs	r2, #32
- 8003066:	675a      	str	r2, [r3, #116]	; 0x74
+ 8003896:	687b      	ldr	r3, [r7, #4]
+ 8003898:	2220      	movs	r2, #32
+ 800389a:	675a      	str	r2, [r3, #116]	; 0x74
 
   /* Cleat TxISR function pointer */
   huart->TxISR = NULL;
- 8003068:	687b      	ldr	r3, [r7, #4]
- 800306a:	2200      	movs	r2, #0
- 800306c:	665a      	str	r2, [r3, #100]	; 0x64
+ 800389c:	687b      	ldr	r3, [r7, #4]
+ 800389e:	2200      	movs	r2, #0
+ 80038a0:	665a      	str	r2, [r3, #100]	; 0x64
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
   /*Call registered Tx complete callback*/
   huart->TxCpltCallback(huart);
 #else
   /*Call legacy weak Tx complete callback*/
   HAL_UART_TxCpltCallback(huart);
- 800306e:	6878      	ldr	r0, [r7, #4]
- 8003070:	f7ff fbe4 	bl	800283c <HAL_UART_TxCpltCallback>
+ 80038a2:	6878      	ldr	r0, [r7, #4]
+ 80038a4:	f7ff fbe4 	bl	8003070 <HAL_UART_TxCpltCallback>
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 }
- 8003074:	bf00      	nop
- 8003076:	3708      	adds	r7, #8
- 8003078:	46bd      	mov	sp, r7
- 800307a:	bd80      	pop	{r7, pc}
+ 80038a8:	bf00      	nop
+ 80038aa:	3708      	adds	r7, #8
+ 80038ac:	46bd      	mov	sp, r7
+ 80038ae:	bd80      	pop	{r7, pc}
+
+080038b0 <_ZN7EncoderC1EP17TIM_HandleTypeDef>:
+#include "encoder.h"
+
+Encoder::Encoder(TIM_HandleTypeDef* timer) {
+ 80038b0:	b580      	push	{r7, lr}
+ 80038b2:	b082      	sub	sp, #8
+ 80038b4:	af00      	add	r7, sp, #0
+ 80038b6:	6078      	str	r0, [r7, #4]
+ 80038b8:	6039      	str	r1, [r7, #0]
+  timer_ = timer;
+ 80038ba:	687b      	ldr	r3, [r7, #4]
+ 80038bc:	683a      	ldr	r2, [r7, #0]
+ 80038be:	601a      	str	r2, [r3, #0]
+  HAL_TIM_Encoder_Start(timer_, TIM_CHANNEL_ALL);
+ 80038c0:	687b      	ldr	r3, [r7, #4]
+ 80038c2:	681b      	ldr	r3, [r3, #0]
+ 80038c4:	213c      	movs	r1, #60	; 0x3c
+ 80038c6:	4618      	mov	r0, r3
+ 80038c8:	f7fe fd98 	bl	80023fc <HAL_TIM_Encoder_Start>
+}
+ 80038cc:	687b      	ldr	r3, [r7, #4]
+ 80038ce:	4618      	mov	r0, r3
+ 80038d0:	3708      	adds	r7, #8
+ 80038d2:	46bd      	mov	sp, r7
+ 80038d4:	bd80      	pop	{r7, pc}
+
+080038d6 <_ZN7Encoder8GetCountEv>:
+ public:
+  TIM_HandleTypeDef* timer_;
+
+  Encoder(TIM_HandleTypeDef* timer);
+
+  int GetCount() {
+ 80038d6:	b480      	push	{r7}
+ 80038d8:	b083      	sub	sp, #12
+ 80038da:	af00      	add	r7, sp, #0
+ 80038dc:	6078      	str	r0, [r7, #4]
+    return __HAL_TIM_GET_COUNTER(timer_);
+ 80038de:	687b      	ldr	r3, [r7, #4]
+ 80038e0:	681b      	ldr	r3, [r3, #0]
+ 80038e2:	681b      	ldr	r3, [r3, #0]
+ 80038e4:	6a5b      	ldr	r3, [r3, #36]	; 0x24
+  }
+ 80038e6:	4618      	mov	r0, r3
+ 80038e8:	370c      	adds	r7, #12
+ 80038ea:	46bd      	mov	sp, r7
+ 80038ec:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80038f0:	4770      	bx	lr
+
+080038f2 <_ZN7Encoder10ResetCountEv>:
+
+  void ResetCount() {
+ 80038f2:	b480      	push	{r7}
+ 80038f4:	b083      	sub	sp, #12
+ 80038f6:	af00      	add	r7, sp, #0
+ 80038f8:	6078      	str	r0, [r7, #4]
+    __HAL_TIM_SET_COUNTER(timer_, 0);
+ 80038fa:	687b      	ldr	r3, [r7, #4]
+ 80038fc:	681b      	ldr	r3, [r3, #0]
+ 80038fe:	681b      	ldr	r3, [r3, #0]
+ 8003900:	2200      	movs	r2, #0
+ 8003902:	625a      	str	r2, [r3, #36]	; 0x24
+  }
+ 8003904:	bf00      	nop
+ 8003906:	370c      	adds	r7, #12
+ 8003908:	46bd      	mov	sp, r7
+ 800390a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800390e:	4770      	bx	lr
 
-0800307c <main>:
+08003910 <main>:
 /**
   * @brief  The application entry point.
   * @retval int
   */
 int main(void)
 {
- 800307c:	b580      	push	{r7, lr}
- 800307e:	af00      	add	r7, sp, #0
+ 8003910:	b580      	push	{r7, lr}
+ 8003912:	b082      	sub	sp, #8
+ 8003914:	af00      	add	r7, sp, #0
   
 
   /* MCU Configuration--------------------------------------------------------*/
 
   /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
   HAL_Init();
- 8003080:	f7fd fa5a 	bl	8000538 <HAL_Init>
+ 8003916:	f7fc fe0f 	bl	8000538 <HAL_Init>
   /* USER CODE BEGIN Init */
 
   /* USER CODE END Init */
 
   /* Configure the system clock */
   SystemClock_Config();
- 8003084:	f000 f80a 	bl	800309c <_Z18SystemClock_Configv>
+ 800391a:	f000 f821 	bl	8003960 <_Z18SystemClock_Configv>
   /* USER CODE BEGIN SysInit */
 
   /* USER CODE END SysInit */
 
   /* Initialize all configured peripherals */
   MX_GPIO_Init();
- 8003088:	f000 f94a 	bl	8003320 <_ZL12MX_GPIO_Initv>
+ 800391e:	f000 fa37 	bl	8003d90 <_ZL12MX_GPIO_Initv>
   MX_DMA_Init();
- 800308c:	f000 f922 	bl	80032d4 <_ZL11MX_DMA_Initv>
+ 8003922:	f000 fa0f 	bl	8003d44 <_ZL11MX_DMA_Initv>
   MX_TIM2_Init();
- 8003090:	f000 f88e 	bl	80031b0 <_ZL12MX_TIM2_Initv>
+ 8003926:	f000 f8a5 	bl	8003a74 <_ZL12MX_TIM2_Initv>
+  MX_TIM4_Init();
+ 800392a:	f000 f901 	bl	8003b30 <_ZL12MX_TIM4_Initv>
+  MX_TIM5_Init();
+ 800392e:	f000 f977 	bl	8003c20 <_ZL12MX_TIM5_Initv>
   MX_USART3_UART_Init();
- 8003094:	f000 f8ea 	bl	800326c <_ZL19MX_USART3_UART_Initv>
-
+ 8003932:	f000 f9d3 	bl	8003cdc <_ZL19MX_USART3_UART_Initv>
+  /* USER CODE BEGIN 2 */
+  Encoder encoder_left = Encoder(&htim2);
+ 8003936:	463b      	mov	r3, r7
+ 8003938:	4908      	ldr	r1, [pc, #32]	; (800395c <main+0x4c>)
+ 800393a:	4618      	mov	r0, r3
+ 800393c:	f7ff ffb8 	bl	80038b0 <_ZN7EncoderC1EP17TIM_HandleTypeDef>
+  uint32_t count_left = 0;
+ 8003940:	2300      	movs	r3, #0
+ 8003942:	607b      	str	r3, [r7, #4]
   /* USER CODE END 2 */
 
   /* Infinite loop */
   /* USER CODE BEGIN WHILE */
   while (1) {
- 8003098:	e7fe      	b.n	8003098 <main+0x1c>
-	...
-
-0800309c <_Z18SystemClock_Configv>:
+    count_left = encoder_left.GetCount();
+ 8003944:	463b      	mov	r3, r7
+ 8003946:	4618      	mov	r0, r3
+ 8003948:	f7ff ffc5 	bl	80038d6 <_ZN7Encoder8GetCountEv>
+ 800394c:	4603      	mov	r3, r0
+ 800394e:	607b      	str	r3, [r7, #4]
+    encoder_left.ResetCount();
+ 8003950:	463b      	mov	r3, r7
+ 8003952:	4618      	mov	r0, r3
+ 8003954:	f7ff ffcd 	bl	80038f2 <_ZN7Encoder10ResetCountEv>
+    count_left = encoder_left.GetCount();
+ 8003958:	e7f4      	b.n	8003944 <main+0x34>
+ 800395a:	bf00      	nop
+ 800395c:	20000028 	.word	0x20000028
+
+08003960 <_Z18SystemClock_Configv>:
 /**
   * @brief System Clock Configuration
   * @retval None
   */
 void SystemClock_Config(void)
 {
- 800309c:	b580      	push	{r7, lr}
- 800309e:	b0b8      	sub	sp, #224	; 0xe0
- 80030a0:	af00      	add	r7, sp, #0
+ 8003960:	b580      	push	{r7, lr}
+ 8003962:	b0b8      	sub	sp, #224	; 0xe0
+ 8003964:	af00      	add	r7, sp, #0
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- 80030a2:	f107 03ac 	add.w	r3, r7, #172	; 0xac
- 80030a6:	2234      	movs	r2, #52	; 0x34
- 80030a8:	2100      	movs	r1, #0
- 80030aa:	4618      	mov	r0, r3
- 80030ac:	f000 fb4e 	bl	800374c <memset>
+ 8003966:	f107 03ac 	add.w	r3, r7, #172	; 0xac
+ 800396a:	2234      	movs	r2, #52	; 0x34
+ 800396c:	2100      	movs	r1, #0
+ 800396e:	4618      	mov	r0, r3
+ 8003970:	f000 fd4e 	bl	8004410 <memset>
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
- 80030b0:	f107 0398 	add.w	r3, r7, #152	; 0x98
- 80030b4:	2200      	movs	r2, #0
- 80030b6:	601a      	str	r2, [r3, #0]
- 80030b8:	605a      	str	r2, [r3, #4]
- 80030ba:	609a      	str	r2, [r3, #8]
- 80030bc:	60da      	str	r2, [r3, #12]
- 80030be:	611a      	str	r2, [r3, #16]
+ 8003974:	f107 0398 	add.w	r3, r7, #152	; 0x98
+ 8003978:	2200      	movs	r2, #0
+ 800397a:	601a      	str	r2, [r3, #0]
+ 800397c:	605a      	str	r2, [r3, #4]
+ 800397e:	609a      	str	r2, [r3, #8]
+ 8003980:	60da      	str	r2, [r3, #12]
+ 8003982:	611a      	str	r2, [r3, #16]
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
- 80030c0:	f107 0308 	add.w	r3, r7, #8
- 80030c4:	2290      	movs	r2, #144	; 0x90
- 80030c6:	2100      	movs	r1, #0
- 80030c8:	4618      	mov	r0, r3
- 80030ca:	f000 fb3f 	bl	800374c <memset>
+ 8003984:	f107 0308 	add.w	r3, r7, #8
+ 8003988:	2290      	movs	r2, #144	; 0x90
+ 800398a:	2100      	movs	r1, #0
+ 800398c:	4618      	mov	r0, r3
+ 800398e:	f000 fd3f 	bl	8004410 <memset>
 
   /** Configure the main internal regulator output voltage 
   */
   __HAL_RCC_PWR_CLK_ENABLE();
- 80030ce:	4b36      	ldr	r3, [pc, #216]	; (80031a8 <_Z18SystemClock_Configv+0x10c>)
- 80030d0:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 80030d2:	4a35      	ldr	r2, [pc, #212]	; (80031a8 <_Z18SystemClock_Configv+0x10c>)
- 80030d4:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
- 80030d8:	6413      	str	r3, [r2, #64]	; 0x40
- 80030da:	4b33      	ldr	r3, [pc, #204]	; (80031a8 <_Z18SystemClock_Configv+0x10c>)
- 80030dc:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 80030de:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
- 80030e2:	607b      	str	r3, [r7, #4]
- 80030e4:	687b      	ldr	r3, [r7, #4]
+ 8003992:	4b36      	ldr	r3, [pc, #216]	; (8003a6c <_Z18SystemClock_Configv+0x10c>)
+ 8003994:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8003996:	4a35      	ldr	r2, [pc, #212]	; (8003a6c <_Z18SystemClock_Configv+0x10c>)
+ 8003998:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
+ 800399c:	6413      	str	r3, [r2, #64]	; 0x40
+ 800399e:	4b33      	ldr	r3, [pc, #204]	; (8003a6c <_Z18SystemClock_Configv+0x10c>)
+ 80039a0:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 80039a2:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
+ 80039a6:	607b      	str	r3, [r7, #4]
+ 80039a8:	687b      	ldr	r3, [r7, #4]
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
- 80030e6:	4b31      	ldr	r3, [pc, #196]	; (80031ac <_Z18SystemClock_Configv+0x110>)
- 80030e8:	681b      	ldr	r3, [r3, #0]
- 80030ea:	f423 4340 	bic.w	r3, r3, #49152	; 0xc000
- 80030ee:	4a2f      	ldr	r2, [pc, #188]	; (80031ac <_Z18SystemClock_Configv+0x110>)
- 80030f0:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
- 80030f4:	6013      	str	r3, [r2, #0]
- 80030f6:	4b2d      	ldr	r3, [pc, #180]	; (80031ac <_Z18SystemClock_Configv+0x110>)
- 80030f8:	681b      	ldr	r3, [r3, #0]
- 80030fa:	f403 4340 	and.w	r3, r3, #49152	; 0xc000
- 80030fe:	603b      	str	r3, [r7, #0]
- 8003100:	683b      	ldr	r3, [r7, #0]
+ 80039aa:	4b31      	ldr	r3, [pc, #196]	; (8003a70 <_Z18SystemClock_Configv+0x110>)
+ 80039ac:	681b      	ldr	r3, [r3, #0]
+ 80039ae:	f423 4340 	bic.w	r3, r3, #49152	; 0xc000
+ 80039b2:	4a2f      	ldr	r2, [pc, #188]	; (8003a70 <_Z18SystemClock_Configv+0x110>)
+ 80039b4:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
+ 80039b8:	6013      	str	r3, [r2, #0]
+ 80039ba:	4b2d      	ldr	r3, [pc, #180]	; (8003a70 <_Z18SystemClock_Configv+0x110>)
+ 80039bc:	681b      	ldr	r3, [r3, #0]
+ 80039be:	f403 4340 	and.w	r3, r3, #49152	; 0xc000
+ 80039c2:	603b      	str	r3, [r7, #0]
+ 80039c4:	683b      	ldr	r3, [r7, #0]
   /** Initializes the CPU, AHB and APB busses clocks 
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
- 8003102:	2302      	movs	r3, #2
- 8003104:	f8c7 30ac 	str.w	r3, [r7, #172]	; 0xac
+ 80039c6:	2302      	movs	r3, #2
+ 80039c8:	f8c7 30ac 	str.w	r3, [r7, #172]	; 0xac
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- 8003108:	2301      	movs	r3, #1
- 800310a:	f8c7 30b8 	str.w	r3, [r7, #184]	; 0xb8
+ 80039cc:	2301      	movs	r3, #1
+ 80039ce:	f8c7 30b8 	str.w	r3, [r7, #184]	; 0xb8
   RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- 800310e:	2310      	movs	r3, #16
- 8003110:	f8c7 30bc 	str.w	r3, [r7, #188]	; 0xbc
+ 80039d2:	2310      	movs	r3, #16
+ 80039d4:	f8c7 30bc 	str.w	r3, [r7, #188]	; 0xbc
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- 8003114:	2300      	movs	r3, #0
- 8003116:	f8c7 30c4 	str.w	r3, [r7, #196]	; 0xc4
+ 80039d8:	2300      	movs	r3, #0
+ 80039da:	f8c7 30c4 	str.w	r3, [r7, #196]	; 0xc4
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- 800311a:	f107 03ac 	add.w	r3, r7, #172	; 0xac
- 800311e:	4618      	mov	r0, r3
- 8003120:	f7fe f82e 	bl	8001180 <HAL_RCC_OscConfig>
- 8003124:	4603      	mov	r3, r0
- 8003126:	2b00      	cmp	r3, #0
- 8003128:	bf14      	ite	ne
- 800312a:	2301      	movne	r3, #1
- 800312c:	2300      	moveq	r3, #0
- 800312e:	b2db      	uxtb	r3, r3
- 8003130:	2b00      	cmp	r3, #0
- 8003132:	d001      	beq.n	8003138 <_Z18SystemClock_Configv+0x9c>
+ 80039de:	f107 03ac 	add.w	r3, r7, #172	; 0xac
+ 80039e2:	4618      	mov	r0, r3
+ 80039e4:	f7fd fbe6 	bl	80011b4 <HAL_RCC_OscConfig>
+ 80039e8:	4603      	mov	r3, r0
+ 80039ea:	2b00      	cmp	r3, #0
+ 80039ec:	bf14      	ite	ne
+ 80039ee:	2301      	movne	r3, #1
+ 80039f0:	2300      	moveq	r3, #0
+ 80039f2:	b2db      	uxtb	r3, r3
+ 80039f4:	2b00      	cmp	r3, #0
+ 80039f6:	d001      	beq.n	80039fc <_Z18SystemClock_Configv+0x9c>
   {
     Error_Handler();
- 8003134:	f000 f918 	bl	8003368 <Error_Handler>
+ 80039f8:	f000 fa72 	bl	8003ee0 <Error_Handler>
   }
   /** Initializes the CPU, AHB and APB busses clocks 
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- 8003138:	230f      	movs	r3, #15
- 800313a:	f8c7 3098 	str.w	r3, [r7, #152]	; 0x98
+ 80039fc:	230f      	movs	r3, #15
+ 80039fe:	f8c7 3098 	str.w	r3, [r7, #152]	; 0x98
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
- 800313e:	2300      	movs	r3, #0
- 8003140:	f8c7 309c 	str.w	r3, [r7, #156]	; 0x9c
+ 8003a02:	2300      	movs	r3, #0
+ 8003a04:	f8c7 309c 	str.w	r3, [r7, #156]	; 0x9c
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- 8003144:	2300      	movs	r3, #0
- 8003146:	f8c7 30a0 	str.w	r3, [r7, #160]	; 0xa0
+ 8003a08:	2300      	movs	r3, #0
+ 8003a0a:	f8c7 30a0 	str.w	r3, [r7, #160]	; 0xa0
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- 800314a:	2300      	movs	r3, #0
- 800314c:	f8c7 30a4 	str.w	r3, [r7, #164]	; 0xa4
+ 8003a0e:	2300      	movs	r3, #0
+ 8003a10:	f8c7 30a4 	str.w	r3, [r7, #164]	; 0xa4
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
- 8003150:	2300      	movs	r3, #0
- 8003152:	f8c7 30a8 	str.w	r3, [r7, #168]	; 0xa8
+ 8003a14:	2300      	movs	r3, #0
+ 8003a16:	f8c7 30a8 	str.w	r3, [r7, #168]	; 0xa8
 
   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
- 8003156:	f107 0398 	add.w	r3, r7, #152	; 0x98
- 800315a:	2100      	movs	r1, #0
- 800315c:	4618      	mov	r0, r3
- 800315e:	f7fe fa81 	bl	8001664 <HAL_RCC_ClockConfig>
- 8003162:	4603      	mov	r3, r0
- 8003164:	2b00      	cmp	r3, #0
- 8003166:	bf14      	ite	ne
- 8003168:	2301      	movne	r3, #1
- 800316a:	2300      	moveq	r3, #0
- 800316c:	b2db      	uxtb	r3, r3
- 800316e:	2b00      	cmp	r3, #0
- 8003170:	d001      	beq.n	8003176 <_Z18SystemClock_Configv+0xda>
+ 8003a1a:	f107 0398 	add.w	r3, r7, #152	; 0x98
+ 8003a1e:	2100      	movs	r1, #0
+ 8003a20:	4618      	mov	r0, r3
+ 8003a22:	f7fd fe39 	bl	8001698 <HAL_RCC_ClockConfig>
+ 8003a26:	4603      	mov	r3, r0
+ 8003a28:	2b00      	cmp	r3, #0
+ 8003a2a:	bf14      	ite	ne
+ 8003a2c:	2301      	movne	r3, #1
+ 8003a2e:	2300      	moveq	r3, #0
+ 8003a30:	b2db      	uxtb	r3, r3
+ 8003a32:	2b00      	cmp	r3, #0
+ 8003a34:	d001      	beq.n	8003a3a <_Z18SystemClock_Configv+0xda>
   {
     Error_Handler();
- 8003172:	f000 f8f9 	bl	8003368 <Error_Handler>
+ 8003a36:	f000 fa53 	bl	8003ee0 <Error_Handler>
   }
   PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3;
- 8003176:	f44f 7380 	mov.w	r3, #256	; 0x100
- 800317a:	60bb      	str	r3, [r7, #8]
+ 8003a3a:	f44f 7380 	mov.w	r3, #256	; 0x100
+ 8003a3e:	60bb      	str	r3, [r7, #8]
   PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
- 800317c:	2300      	movs	r3, #0
- 800317e:	657b      	str	r3, [r7, #84]	; 0x54
+ 8003a40:	2300      	movs	r3, #0
+ 8003a42:	657b      	str	r3, [r7, #84]	; 0x54
   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
- 8003180:	f107 0308 	add.w	r3, r7, #8
- 8003184:	4618      	mov	r0, r3
- 8003186:	f7fe fc3b 	bl	8001a00 <HAL_RCCEx_PeriphCLKConfig>
- 800318a:	4603      	mov	r3, r0
- 800318c:	2b00      	cmp	r3, #0
- 800318e:	bf14      	ite	ne
- 8003190:	2301      	movne	r3, #1
- 8003192:	2300      	moveq	r3, #0
- 8003194:	b2db      	uxtb	r3, r3
- 8003196:	2b00      	cmp	r3, #0
- 8003198:	d001      	beq.n	800319e <_Z18SystemClock_Configv+0x102>
+ 8003a44:	f107 0308 	add.w	r3, r7, #8
+ 8003a48:	4618      	mov	r0, r3
+ 8003a4a:	f7fd fff3 	bl	8001a34 <HAL_RCCEx_PeriphCLKConfig>
+ 8003a4e:	4603      	mov	r3, r0
+ 8003a50:	2b00      	cmp	r3, #0
+ 8003a52:	bf14      	ite	ne
+ 8003a54:	2301      	movne	r3, #1
+ 8003a56:	2300      	moveq	r3, #0
+ 8003a58:	b2db      	uxtb	r3, r3
+ 8003a5a:	2b00      	cmp	r3, #0
+ 8003a5c:	d001      	beq.n	8003a62 <_Z18SystemClock_Configv+0x102>
   {
     Error_Handler();
- 800319a:	f000 f8e5 	bl	8003368 <Error_Handler>
+ 8003a5e:	f000 fa3f 	bl	8003ee0 <Error_Handler>
   }
 }
- 800319e:	bf00      	nop
- 80031a0:	37e0      	adds	r7, #224	; 0xe0
- 80031a2:	46bd      	mov	sp, r7
- 80031a4:	bd80      	pop	{r7, pc}
- 80031a6:	bf00      	nop
- 80031a8:	40023800 	.word	0x40023800
- 80031ac:	40007000 	.word	0x40007000
-
-080031b0 <_ZL12MX_TIM2_Initv>:
+ 8003a62:	bf00      	nop
+ 8003a64:	37e0      	adds	r7, #224	; 0xe0
+ 8003a66:	46bd      	mov	sp, r7
+ 8003a68:	bd80      	pop	{r7, pc}
+ 8003a6a:	bf00      	nop
+ 8003a6c:	40023800 	.word	0x40023800
+ 8003a70:	40007000 	.word	0x40007000
+
+08003a74 <_ZL12MX_TIM2_Initv>:
   * @brief TIM2 Initialization Function
   * @param None
   * @retval None
   */
 static void MX_TIM2_Init(void)
 {
- 80031b0:	b580      	push	{r7, lr}
- 80031b2:	b08c      	sub	sp, #48	; 0x30
- 80031b4:	af00      	add	r7, sp, #0
+ 8003a74:	b580      	push	{r7, lr}
+ 8003a76:	b08c      	sub	sp, #48	; 0x30
+ 8003a78:	af00      	add	r7, sp, #0
 
   /* USER CODE BEGIN TIM2_Init 0 */
 
   /* USER CODE END TIM2_Init 0 */
 
   TIM_Encoder_InitTypeDef sConfig = {0};
- 80031b6:	f107 030c 	add.w	r3, r7, #12
- 80031ba:	2224      	movs	r2, #36	; 0x24
- 80031bc:	2100      	movs	r1, #0
- 80031be:	4618      	mov	r0, r3
- 80031c0:	f000 fac4 	bl	800374c <memset>
+ 8003a7a:	f107 030c 	add.w	r3, r7, #12
+ 8003a7e:	2224      	movs	r2, #36	; 0x24
+ 8003a80:	2100      	movs	r1, #0
+ 8003a82:	4618      	mov	r0, r3
+ 8003a84:	f000 fcc4 	bl	8004410 <memset>
   TIM_MasterConfigTypeDef sMasterConfig = {0};
- 80031c4:	463b      	mov	r3, r7
- 80031c6:	2200      	movs	r2, #0
- 80031c8:	601a      	str	r2, [r3, #0]
- 80031ca:	605a      	str	r2, [r3, #4]
- 80031cc:	609a      	str	r2, [r3, #8]
+ 8003a88:	463b      	mov	r3, r7
+ 8003a8a:	2200      	movs	r2, #0
+ 8003a8c:	601a      	str	r2, [r3, #0]
+ 8003a8e:	605a      	str	r2, [r3, #4]
+ 8003a90:	609a      	str	r2, [r3, #8]
 
   /* USER CODE BEGIN TIM2_Init 1 */
 
   /* USER CODE END TIM2_Init 1 */
   htim2.Instance = TIM2;
- 80031ce:	4b26      	ldr	r3, [pc, #152]	; (8003268 <_ZL12MX_TIM2_Initv+0xb8>)
- 80031d0:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
- 80031d4:	601a      	str	r2, [r3, #0]
+ 8003a92:	4b26      	ldr	r3, [pc, #152]	; (8003b2c <_ZL12MX_TIM2_Initv+0xb8>)
+ 8003a94:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
+ 8003a98:	601a      	str	r2, [r3, #0]
   htim2.Init.Prescaler = 0;
- 80031d6:	4b24      	ldr	r3, [pc, #144]	; (8003268 <_ZL12MX_TIM2_Initv+0xb8>)
- 80031d8:	2200      	movs	r2, #0
- 80031da:	605a      	str	r2, [r3, #4]
+ 8003a9a:	4b24      	ldr	r3, [pc, #144]	; (8003b2c <_ZL12MX_TIM2_Initv+0xb8>)
+ 8003a9c:	2200      	movs	r2, #0
+ 8003a9e:	605a      	str	r2, [r3, #4]
   htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
- 80031dc:	4b22      	ldr	r3, [pc, #136]	; (8003268 <_ZL12MX_TIM2_Initv+0xb8>)
- 80031de:	2200      	movs	r2, #0
- 80031e0:	609a      	str	r2, [r3, #8]
-  htim2.Init.Period = 0;
- 80031e2:	4b21      	ldr	r3, [pc, #132]	; (8003268 <_ZL12MX_TIM2_Initv+0xb8>)
- 80031e4:	2200      	movs	r2, #0
- 80031e6:	60da      	str	r2, [r3, #12]
+ 8003aa0:	4b22      	ldr	r3, [pc, #136]	; (8003b2c <_ZL12MX_TIM2_Initv+0xb8>)
+ 8003aa2:	2200      	movs	r2, #0
+ 8003aa4:	609a      	str	r2, [r3, #8]
+  htim2.Init.Period = 4294967295;
+ 8003aa6:	4b21      	ldr	r3, [pc, #132]	; (8003b2c <_ZL12MX_TIM2_Initv+0xb8>)
+ 8003aa8:	f04f 32ff 	mov.w	r2, #4294967295	; 0xffffffff
+ 8003aac:	60da      	str	r2, [r3, #12]
   htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 80031e8:	4b1f      	ldr	r3, [pc, #124]	; (8003268 <_ZL12MX_TIM2_Initv+0xb8>)
- 80031ea:	2200      	movs	r2, #0
- 80031ec:	611a      	str	r2, [r3, #16]
+ 8003aae:	4b1f      	ldr	r3, [pc, #124]	; (8003b2c <_ZL12MX_TIM2_Initv+0xb8>)
+ 8003ab0:	2200      	movs	r2, #0
+ 8003ab2:	611a      	str	r2, [r3, #16]
   htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 80031ee:	4b1e      	ldr	r3, [pc, #120]	; (8003268 <_ZL12MX_TIM2_Initv+0xb8>)
- 80031f0:	2200      	movs	r2, #0
- 80031f2:	619a      	str	r2, [r3, #24]
+ 8003ab4:	4b1d      	ldr	r3, [pc, #116]	; (8003b2c <_ZL12MX_TIM2_Initv+0xb8>)
+ 8003ab6:	2200      	movs	r2, #0
+ 8003ab8:	619a      	str	r2, [r3, #24]
   sConfig.EncoderMode = TIM_ENCODERMODE_TI1;
- 80031f4:	2301      	movs	r3, #1
- 80031f6:	60fb      	str	r3, [r7, #12]
+ 8003aba:	2301      	movs	r3, #1
+ 8003abc:	60fb      	str	r3, [r7, #12]
   sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
- 80031f8:	2300      	movs	r3, #0
- 80031fa:	613b      	str	r3, [r7, #16]
+ 8003abe:	2300      	movs	r3, #0
+ 8003ac0:	613b      	str	r3, [r7, #16]
   sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
- 80031fc:	2301      	movs	r3, #1
- 80031fe:	617b      	str	r3, [r7, #20]
+ 8003ac2:	2301      	movs	r3, #1
+ 8003ac4:	617b      	str	r3, [r7, #20]
   sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
- 8003200:	2300      	movs	r3, #0
- 8003202:	61bb      	str	r3, [r7, #24]
+ 8003ac6:	2300      	movs	r3, #0
+ 8003ac8:	61bb      	str	r3, [r7, #24]
   sConfig.IC1Filter = 0;
- 8003204:	2300      	movs	r3, #0
- 8003206:	61fb      	str	r3, [r7, #28]
+ 8003aca:	2300      	movs	r3, #0
+ 8003acc:	61fb      	str	r3, [r7, #28]
   sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
- 8003208:	2300      	movs	r3, #0
- 800320a:	623b      	str	r3, [r7, #32]
+ 8003ace:	2300      	movs	r3, #0
+ 8003ad0:	623b      	str	r3, [r7, #32]
   sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
- 800320c:	2301      	movs	r3, #1
- 800320e:	627b      	str	r3, [r7, #36]	; 0x24
+ 8003ad2:	2301      	movs	r3, #1
+ 8003ad4:	627b      	str	r3, [r7, #36]	; 0x24
   sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
- 8003210:	2300      	movs	r3, #0
- 8003212:	62bb      	str	r3, [r7, #40]	; 0x28
+ 8003ad6:	2300      	movs	r3, #0
+ 8003ad8:	62bb      	str	r3, [r7, #40]	; 0x28
   sConfig.IC2Filter = 0;
- 8003214:	2300      	movs	r3, #0
- 8003216:	62fb      	str	r3, [r7, #44]	; 0x2c
+ 8003ada:	2300      	movs	r3, #0
+ 8003adc:	62fb      	str	r3, [r7, #44]	; 0x2c
   if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK)
- 8003218:	f107 030c 	add.w	r3, r7, #12
- 800321c:	4619      	mov	r1, r3
- 800321e:	4812      	ldr	r0, [pc, #72]	; (8003268 <_ZL12MX_TIM2_Initv+0xb8>)
- 8003220:	f7ff f814 	bl	800224c <HAL_TIM_Encoder_Init>
- 8003224:	4603      	mov	r3, r0
- 8003226:	2b00      	cmp	r3, #0
- 8003228:	bf14      	ite	ne
- 800322a:	2301      	movne	r3, #1
- 800322c:	2300      	moveq	r3, #0
- 800322e:	b2db      	uxtb	r3, r3
- 8003230:	2b00      	cmp	r3, #0
- 8003232:	d001      	beq.n	8003238 <_ZL12MX_TIM2_Initv+0x88>
+ 8003ade:	f107 030c 	add.w	r3, r7, #12
+ 8003ae2:	4619      	mov	r1, r3
+ 8003ae4:	4811      	ldr	r0, [pc, #68]	; (8003b2c <_ZL12MX_TIM2_Initv+0xb8>)
+ 8003ae6:	f7fe fbf7 	bl	80022d8 <HAL_TIM_Encoder_Init>
+ 8003aea:	4603      	mov	r3, r0
+ 8003aec:	2b00      	cmp	r3, #0
+ 8003aee:	bf14      	ite	ne
+ 8003af0:	2301      	movne	r3, #1
+ 8003af2:	2300      	moveq	r3, #0
+ 8003af4:	b2db      	uxtb	r3, r3
+ 8003af6:	2b00      	cmp	r3, #0
+ 8003af8:	d001      	beq.n	8003afe <_ZL12MX_TIM2_Initv+0x8a>
   {
     Error_Handler();
- 8003234:	f000 f898 	bl	8003368 <Error_Handler>
+ 8003afa:	f000 f9f1 	bl	8003ee0 <Error_Handler>
   }
   sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8003238:	2300      	movs	r3, #0
- 800323a:	603b      	str	r3, [r7, #0]
+ 8003afe:	2300      	movs	r3, #0
+ 8003b00:	603b      	str	r3, [r7, #0]
   sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 800323c:	2300      	movs	r3, #0
- 800323e:	60bb      	str	r3, [r7, #8]
+ 8003b02:	2300      	movs	r3, #0
+ 8003b04:	60bb      	str	r3, [r7, #8]
   if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
- 8003240:	463b      	mov	r3, r7
- 8003242:	4619      	mov	r1, r3
- 8003244:	4808      	ldr	r0, [pc, #32]	; (8003268 <_ZL12MX_TIM2_Initv+0xb8>)
- 8003246:	f7ff f933 	bl	80024b0 <HAL_TIMEx_MasterConfigSynchronization>
- 800324a:	4603      	mov	r3, r0
- 800324c:	2b00      	cmp	r3, #0
- 800324e:	bf14      	ite	ne
- 8003250:	2301      	movne	r3, #1
- 8003252:	2300      	moveq	r3, #0
- 8003254:	b2db      	uxtb	r3, r3
- 8003256:	2b00      	cmp	r3, #0
- 8003258:	d001      	beq.n	800325e <_ZL12MX_TIM2_Initv+0xae>
+ 8003b06:	463b      	mov	r3, r7
+ 8003b08:	4619      	mov	r1, r3
+ 8003b0a:	4808      	ldr	r0, [pc, #32]	; (8003b2c <_ZL12MX_TIM2_Initv+0xb8>)
+ 8003b0c:	f7ff f8ea 	bl	8002ce4 <HAL_TIMEx_MasterConfigSynchronization>
+ 8003b10:	4603      	mov	r3, r0
+ 8003b12:	2b00      	cmp	r3, #0
+ 8003b14:	bf14      	ite	ne
+ 8003b16:	2301      	movne	r3, #1
+ 8003b18:	2300      	moveq	r3, #0
+ 8003b1a:	b2db      	uxtb	r3, r3
+ 8003b1c:	2b00      	cmp	r3, #0
+ 8003b1e:	d001      	beq.n	8003b24 <_ZL12MX_TIM2_Initv+0xb0>
   {
     Error_Handler();
- 800325a:	f000 f885 	bl	8003368 <Error_Handler>
+ 8003b20:	f000 f9de 	bl	8003ee0 <Error_Handler>
   }
   /* USER CODE BEGIN TIM2_Init 2 */
 
   /* USER CODE END TIM2_Init 2 */
 
 }
- 800325e:	bf00      	nop
- 8003260:	3730      	adds	r7, #48	; 0x30
- 8003262:	46bd      	mov	sp, r7
- 8003264:	bd80      	pop	{r7, pc}
- 8003266:	bf00      	nop
- 8003268:	20000028 	.word	0x20000028
-
-0800326c <_ZL19MX_USART3_UART_Initv>:
+ 8003b24:	bf00      	nop
+ 8003b26:	3730      	adds	r7, #48	; 0x30
+ 8003b28:	46bd      	mov	sp, r7
+ 8003b2a:	bd80      	pop	{r7, pc}
+ 8003b2c:	20000028 	.word	0x20000028
+
+08003b30 <_ZL12MX_TIM4_Initv>:
+  * @brief TIM4 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM4_Init(void)
+{
+ 8003b30:	b580      	push	{r7, lr}
+ 8003b32:	b08a      	sub	sp, #40	; 0x28
+ 8003b34:	af00      	add	r7, sp, #0
+
+  /* USER CODE BEGIN TIM4_Init 0 */
+
+  /* USER CODE END TIM4_Init 0 */
+
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 8003b36:	f107 031c 	add.w	r3, r7, #28
+ 8003b3a:	2200      	movs	r2, #0
+ 8003b3c:	601a      	str	r2, [r3, #0]
+ 8003b3e:	605a      	str	r2, [r3, #4]
+ 8003b40:	609a      	str	r2, [r3, #8]
+  TIM_OC_InitTypeDef sConfigOC = {0};
+ 8003b42:	463b      	mov	r3, r7
+ 8003b44:	2200      	movs	r2, #0
+ 8003b46:	601a      	str	r2, [r3, #0]
+ 8003b48:	605a      	str	r2, [r3, #4]
+ 8003b4a:	609a      	str	r2, [r3, #8]
+ 8003b4c:	60da      	str	r2, [r3, #12]
+ 8003b4e:	611a      	str	r2, [r3, #16]
+ 8003b50:	615a      	str	r2, [r3, #20]
+ 8003b52:	619a      	str	r2, [r3, #24]
+
+  /* USER CODE BEGIN TIM4_Init 1 */
+
+  /* USER CODE END TIM4_Init 1 */
+  htim4.Instance = TIM4;
+ 8003b54:	4b30      	ldr	r3, [pc, #192]	; (8003c18 <_ZL12MX_TIM4_Initv+0xe8>)
+ 8003b56:	4a31      	ldr	r2, [pc, #196]	; (8003c1c <_ZL12MX_TIM4_Initv+0xec>)
+ 8003b58:	601a      	str	r2, [r3, #0]
+  htim4.Init.Prescaler = 0;
+ 8003b5a:	4b2f      	ldr	r3, [pc, #188]	; (8003c18 <_ZL12MX_TIM4_Initv+0xe8>)
+ 8003b5c:	2200      	movs	r2, #0
+ 8003b5e:	605a      	str	r2, [r3, #4]
+  htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 8003b60:	4b2d      	ldr	r3, [pc, #180]	; (8003c18 <_ZL12MX_TIM4_Initv+0xe8>)
+ 8003b62:	2200      	movs	r2, #0
+ 8003b64:	609a      	str	r2, [r3, #8]
+  htim4.Init.Period = 0;
+ 8003b66:	4b2c      	ldr	r3, [pc, #176]	; (8003c18 <_ZL12MX_TIM4_Initv+0xe8>)
+ 8003b68:	2200      	movs	r2, #0
+ 8003b6a:	60da      	str	r2, [r3, #12]
+  htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 8003b6c:	4b2a      	ldr	r3, [pc, #168]	; (8003c18 <_ZL12MX_TIM4_Initv+0xe8>)
+ 8003b6e:	2200      	movs	r2, #0
+ 8003b70:	611a      	str	r2, [r3, #16]
+  htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 8003b72:	4b29      	ldr	r3, [pc, #164]	; (8003c18 <_ZL12MX_TIM4_Initv+0xe8>)
+ 8003b74:	2200      	movs	r2, #0
+ 8003b76:	619a      	str	r2, [r3, #24]
+  if (HAL_TIM_PWM_Init(&htim4) != HAL_OK)
+ 8003b78:	4827      	ldr	r0, [pc, #156]	; (8003c18 <_ZL12MX_TIM4_Initv+0xe8>)
+ 8003b7a:	f7fe fb81 	bl	8002280 <HAL_TIM_PWM_Init>
+ 8003b7e:	4603      	mov	r3, r0
+ 8003b80:	2b00      	cmp	r3, #0
+ 8003b82:	bf14      	ite	ne
+ 8003b84:	2301      	movne	r3, #1
+ 8003b86:	2300      	moveq	r3, #0
+ 8003b88:	b2db      	uxtb	r3, r3
+ 8003b8a:	2b00      	cmp	r3, #0
+ 8003b8c:	d001      	beq.n	8003b92 <_ZL12MX_TIM4_Initv+0x62>
+  {
+    Error_Handler();
+ 8003b8e:	f000 f9a7 	bl	8003ee0 <Error_Handler>
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ 8003b92:	2300      	movs	r3, #0
+ 8003b94:	61fb      	str	r3, [r7, #28]
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 8003b96:	2300      	movs	r3, #0
+ 8003b98:	627b      	str	r3, [r7, #36]	; 0x24
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
+ 8003b9a:	f107 031c 	add.w	r3, r7, #28
+ 8003b9e:	4619      	mov	r1, r3
+ 8003ba0:	481d      	ldr	r0, [pc, #116]	; (8003c18 <_ZL12MX_TIM4_Initv+0xe8>)
+ 8003ba2:	f7ff f89f 	bl	8002ce4 <HAL_TIMEx_MasterConfigSynchronization>
+ 8003ba6:	4603      	mov	r3, r0
+ 8003ba8:	2b00      	cmp	r3, #0
+ 8003baa:	bf14      	ite	ne
+ 8003bac:	2301      	movne	r3, #1
+ 8003bae:	2300      	moveq	r3, #0
+ 8003bb0:	b2db      	uxtb	r3, r3
+ 8003bb2:	2b00      	cmp	r3, #0
+ 8003bb4:	d001      	beq.n	8003bba <_ZL12MX_TIM4_Initv+0x8a>
+  {
+    Error_Handler();
+ 8003bb6:	f000 f993 	bl	8003ee0 <Error_Handler>
+  }
+  sConfigOC.OCMode = TIM_OCMODE_PWM1;
+ 8003bba:	2360      	movs	r3, #96	; 0x60
+ 8003bbc:	603b      	str	r3, [r7, #0]
+  sConfigOC.Pulse = 0;
+ 8003bbe:	2300      	movs	r3, #0
+ 8003bc0:	607b      	str	r3, [r7, #4]
+  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+ 8003bc2:	2300      	movs	r3, #0
+ 8003bc4:	60bb      	str	r3, [r7, #8]
+  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
+ 8003bc6:	2300      	movs	r3, #0
+ 8003bc8:	613b      	str	r3, [r7, #16]
+  if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
+ 8003bca:	463b      	mov	r3, r7
+ 8003bcc:	2208      	movs	r2, #8
+ 8003bce:	4619      	mov	r1, r3
+ 8003bd0:	4811      	ldr	r0, [pc, #68]	; (8003c18 <_ZL12MX_TIM4_Initv+0xe8>)
+ 8003bd2:	f7fe fc4b 	bl	800246c <HAL_TIM_PWM_ConfigChannel>
+ 8003bd6:	4603      	mov	r3, r0
+ 8003bd8:	2b00      	cmp	r3, #0
+ 8003bda:	bf14      	ite	ne
+ 8003bdc:	2301      	movne	r3, #1
+ 8003bde:	2300      	moveq	r3, #0
+ 8003be0:	b2db      	uxtb	r3, r3
+ 8003be2:	2b00      	cmp	r3, #0
+ 8003be4:	d001      	beq.n	8003bea <_ZL12MX_TIM4_Initv+0xba>
+  {
+    Error_Handler();
+ 8003be6:	f000 f97b 	bl	8003ee0 <Error_Handler>
+  }
+  if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
+ 8003bea:	463b      	mov	r3, r7
+ 8003bec:	220c      	movs	r2, #12
+ 8003bee:	4619      	mov	r1, r3
+ 8003bf0:	4809      	ldr	r0, [pc, #36]	; (8003c18 <_ZL12MX_TIM4_Initv+0xe8>)
+ 8003bf2:	f7fe fc3b 	bl	800246c <HAL_TIM_PWM_ConfigChannel>
+ 8003bf6:	4603      	mov	r3, r0
+ 8003bf8:	2b00      	cmp	r3, #0
+ 8003bfa:	bf14      	ite	ne
+ 8003bfc:	2301      	movne	r3, #1
+ 8003bfe:	2300      	moveq	r3, #0
+ 8003c00:	b2db      	uxtb	r3, r3
+ 8003c02:	2b00      	cmp	r3, #0
+ 8003c04:	d001      	beq.n	8003c0a <_ZL12MX_TIM4_Initv+0xda>
+  {
+    Error_Handler();
+ 8003c06:	f000 f96b 	bl	8003ee0 <Error_Handler>
+  }
+  /* USER CODE BEGIN TIM4_Init 2 */
+
+  /* USER CODE END TIM4_Init 2 */
+  HAL_TIM_MspPostInit(&htim4);
+ 8003c0a:	4803      	ldr	r0, [pc, #12]	; (8003c18 <_ZL12MX_TIM4_Initv+0xe8>)
+ 8003c0c:	f000 fa44 	bl	8004098 <HAL_TIM_MspPostInit>
+
+}
+ 8003c10:	bf00      	nop
+ 8003c12:	3728      	adds	r7, #40	; 0x28
+ 8003c14:	46bd      	mov	sp, r7
+ 8003c16:	bd80      	pop	{r7, pc}
+ 8003c18:	20000068 	.word	0x20000068
+ 8003c1c:	40000800 	.word	0x40000800
+
+08003c20 <_ZL12MX_TIM5_Initv>:
+  * @brief TIM5 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM5_Init(void)
+{
+ 8003c20:	b580      	push	{r7, lr}
+ 8003c22:	b08c      	sub	sp, #48	; 0x30
+ 8003c24:	af00      	add	r7, sp, #0
+
+  /* USER CODE BEGIN TIM5_Init 0 */
+
+  /* USER CODE END TIM5_Init 0 */
+
+  TIM_Encoder_InitTypeDef sConfig = {0};
+ 8003c26:	f107 030c 	add.w	r3, r7, #12
+ 8003c2a:	2224      	movs	r2, #36	; 0x24
+ 8003c2c:	2100      	movs	r1, #0
+ 8003c2e:	4618      	mov	r0, r3
+ 8003c30:	f000 fbee 	bl	8004410 <memset>
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 8003c34:	463b      	mov	r3, r7
+ 8003c36:	2200      	movs	r2, #0
+ 8003c38:	601a      	str	r2, [r3, #0]
+ 8003c3a:	605a      	str	r2, [r3, #4]
+ 8003c3c:	609a      	str	r2, [r3, #8]
+
+  /* USER CODE BEGIN TIM5_Init 1 */
+
+  /* USER CODE END TIM5_Init 1 */
+  htim5.Instance = TIM5;
+ 8003c3e:	4b25      	ldr	r3, [pc, #148]	; (8003cd4 <_ZL12MX_TIM5_Initv+0xb4>)
+ 8003c40:	4a25      	ldr	r2, [pc, #148]	; (8003cd8 <_ZL12MX_TIM5_Initv+0xb8>)
+ 8003c42:	601a      	str	r2, [r3, #0]
+  htim5.Init.Prescaler = 0;
+ 8003c44:	4b23      	ldr	r3, [pc, #140]	; (8003cd4 <_ZL12MX_TIM5_Initv+0xb4>)
+ 8003c46:	2200      	movs	r2, #0
+ 8003c48:	605a      	str	r2, [r3, #4]
+  htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 8003c4a:	4b22      	ldr	r3, [pc, #136]	; (8003cd4 <_ZL12MX_TIM5_Initv+0xb4>)
+ 8003c4c:	2200      	movs	r2, #0
+ 8003c4e:	609a      	str	r2, [r3, #8]
+  htim5.Init.Period = 0;
+ 8003c50:	4b20      	ldr	r3, [pc, #128]	; (8003cd4 <_ZL12MX_TIM5_Initv+0xb4>)
+ 8003c52:	2200      	movs	r2, #0
+ 8003c54:	60da      	str	r2, [r3, #12]
+  htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 8003c56:	4b1f      	ldr	r3, [pc, #124]	; (8003cd4 <_ZL12MX_TIM5_Initv+0xb4>)
+ 8003c58:	2200      	movs	r2, #0
+ 8003c5a:	611a      	str	r2, [r3, #16]
+  htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 8003c5c:	4b1d      	ldr	r3, [pc, #116]	; (8003cd4 <_ZL12MX_TIM5_Initv+0xb4>)
+ 8003c5e:	2200      	movs	r2, #0
+ 8003c60:	619a      	str	r2, [r3, #24]
+  sConfig.EncoderMode = TIM_ENCODERMODE_TI1;
+ 8003c62:	2301      	movs	r3, #1
+ 8003c64:	60fb      	str	r3, [r7, #12]
+  sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
+ 8003c66:	2300      	movs	r3, #0
+ 8003c68:	613b      	str	r3, [r7, #16]
+  sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
+ 8003c6a:	2301      	movs	r3, #1
+ 8003c6c:	617b      	str	r3, [r7, #20]
+  sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
+ 8003c6e:	2300      	movs	r3, #0
+ 8003c70:	61bb      	str	r3, [r7, #24]
+  sConfig.IC1Filter = 0;
+ 8003c72:	2300      	movs	r3, #0
+ 8003c74:	61fb      	str	r3, [r7, #28]
+  sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
+ 8003c76:	2300      	movs	r3, #0
+ 8003c78:	623b      	str	r3, [r7, #32]
+  sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
+ 8003c7a:	2301      	movs	r3, #1
+ 8003c7c:	627b      	str	r3, [r7, #36]	; 0x24
+  sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
+ 8003c7e:	2300      	movs	r3, #0
+ 8003c80:	62bb      	str	r3, [r7, #40]	; 0x28
+  sConfig.IC2Filter = 0;
+ 8003c82:	2300      	movs	r3, #0
+ 8003c84:	62fb      	str	r3, [r7, #44]	; 0x2c
+  if (HAL_TIM_Encoder_Init(&htim5, &sConfig) != HAL_OK)
+ 8003c86:	f107 030c 	add.w	r3, r7, #12
+ 8003c8a:	4619      	mov	r1, r3
+ 8003c8c:	4811      	ldr	r0, [pc, #68]	; (8003cd4 <_ZL12MX_TIM5_Initv+0xb4>)
+ 8003c8e:	f7fe fb23 	bl	80022d8 <HAL_TIM_Encoder_Init>
+ 8003c92:	4603      	mov	r3, r0
+ 8003c94:	2b00      	cmp	r3, #0
+ 8003c96:	bf14      	ite	ne
+ 8003c98:	2301      	movne	r3, #1
+ 8003c9a:	2300      	moveq	r3, #0
+ 8003c9c:	b2db      	uxtb	r3, r3
+ 8003c9e:	2b00      	cmp	r3, #0
+ 8003ca0:	d001      	beq.n	8003ca6 <_ZL12MX_TIM5_Initv+0x86>
+  {
+    Error_Handler();
+ 8003ca2:	f000 f91d 	bl	8003ee0 <Error_Handler>
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ 8003ca6:	2300      	movs	r3, #0
+ 8003ca8:	603b      	str	r3, [r7, #0]
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 8003caa:	2300      	movs	r3, #0
+ 8003cac:	60bb      	str	r3, [r7, #8]
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK)
+ 8003cae:	463b      	mov	r3, r7
+ 8003cb0:	4619      	mov	r1, r3
+ 8003cb2:	4808      	ldr	r0, [pc, #32]	; (8003cd4 <_ZL12MX_TIM5_Initv+0xb4>)
+ 8003cb4:	f7ff f816 	bl	8002ce4 <HAL_TIMEx_MasterConfigSynchronization>
+ 8003cb8:	4603      	mov	r3, r0
+ 8003cba:	2b00      	cmp	r3, #0
+ 8003cbc:	bf14      	ite	ne
+ 8003cbe:	2301      	movne	r3, #1
+ 8003cc0:	2300      	moveq	r3, #0
+ 8003cc2:	b2db      	uxtb	r3, r3
+ 8003cc4:	2b00      	cmp	r3, #0
+ 8003cc6:	d001      	beq.n	8003ccc <_ZL12MX_TIM5_Initv+0xac>
+  {
+    Error_Handler();
+ 8003cc8:	f000 f90a 	bl	8003ee0 <Error_Handler>
+  }
+  /* USER CODE BEGIN TIM5_Init 2 */
+
+  /* USER CODE END TIM5_Init 2 */
+
+}
+ 8003ccc:	bf00      	nop
+ 8003cce:	3730      	adds	r7, #48	; 0x30
+ 8003cd0:	46bd      	mov	sp, r7
+ 8003cd2:	bd80      	pop	{r7, pc}
+ 8003cd4:	200000a8 	.word	0x200000a8
+ 8003cd8:	40000c00 	.word	0x40000c00
+
+08003cdc <_ZL19MX_USART3_UART_Initv>:
   * @brief USART3 Initialization Function
   * @param None
   * @retval None
   */
 static void MX_USART3_UART_Init(void)
 {
- 800326c:	b580      	push	{r7, lr}
- 800326e:	af00      	add	r7, sp, #0
+ 8003cdc:	b580      	push	{r7, lr}
+ 8003cde:	af00      	add	r7, sp, #0
   /* USER CODE END USART3_Init 0 */
 
   /* USER CODE BEGIN USART3_Init 1 */
 
   /* USER CODE END USART3_Init 1 */
   huart3.Instance = USART3;
- 8003270:	4b16      	ldr	r3, [pc, #88]	; (80032cc <_ZL19MX_USART3_UART_Initv+0x60>)
- 8003272:	4a17      	ldr	r2, [pc, #92]	; (80032d0 <_ZL19MX_USART3_UART_Initv+0x64>)
- 8003274:	601a      	str	r2, [r3, #0]
+ 8003ce0:	4b16      	ldr	r3, [pc, #88]	; (8003d3c <_ZL19MX_USART3_UART_Initv+0x60>)
+ 8003ce2:	4a17      	ldr	r2, [pc, #92]	; (8003d40 <_ZL19MX_USART3_UART_Initv+0x64>)
+ 8003ce4:	601a      	str	r2, [r3, #0]
   huart3.Init.BaudRate = 115200;
- 8003276:	4b15      	ldr	r3, [pc, #84]	; (80032cc <_ZL19MX_USART3_UART_Initv+0x60>)
- 8003278:	f44f 32e1 	mov.w	r2, #115200	; 0x1c200
- 800327c:	605a      	str	r2, [r3, #4]
+ 8003ce6:	4b15      	ldr	r3, [pc, #84]	; (8003d3c <_ZL19MX_USART3_UART_Initv+0x60>)
+ 8003ce8:	f44f 32e1 	mov.w	r2, #115200	; 0x1c200
+ 8003cec:	605a      	str	r2, [r3, #4]
   huart3.Init.WordLength = UART_WORDLENGTH_8B;
- 800327e:	4b13      	ldr	r3, [pc, #76]	; (80032cc <_ZL19MX_USART3_UART_Initv+0x60>)
- 8003280:	2200      	movs	r2, #0
- 8003282:	609a      	str	r2, [r3, #8]
+ 8003cee:	4b13      	ldr	r3, [pc, #76]	; (8003d3c <_ZL19MX_USART3_UART_Initv+0x60>)
+ 8003cf0:	2200      	movs	r2, #0
+ 8003cf2:	609a      	str	r2, [r3, #8]
   huart3.Init.StopBits = UART_STOPBITS_1;
- 8003284:	4b11      	ldr	r3, [pc, #68]	; (80032cc <_ZL19MX_USART3_UART_Initv+0x60>)
- 8003286:	2200      	movs	r2, #0
- 8003288:	60da      	str	r2, [r3, #12]
+ 8003cf4:	4b11      	ldr	r3, [pc, #68]	; (8003d3c <_ZL19MX_USART3_UART_Initv+0x60>)
+ 8003cf6:	2200      	movs	r2, #0
+ 8003cf8:	60da      	str	r2, [r3, #12]
   huart3.Init.Parity = UART_PARITY_NONE;
- 800328a:	4b10      	ldr	r3, [pc, #64]	; (80032cc <_ZL19MX_USART3_UART_Initv+0x60>)
- 800328c:	2200      	movs	r2, #0
- 800328e:	611a      	str	r2, [r3, #16]
+ 8003cfa:	4b10      	ldr	r3, [pc, #64]	; (8003d3c <_ZL19MX_USART3_UART_Initv+0x60>)
+ 8003cfc:	2200      	movs	r2, #0
+ 8003cfe:	611a      	str	r2, [r3, #16]
   huart3.Init.Mode = UART_MODE_TX_RX;
- 8003290:	4b0e      	ldr	r3, [pc, #56]	; (80032cc <_ZL19MX_USART3_UART_Initv+0x60>)
- 8003292:	220c      	movs	r2, #12
- 8003294:	615a      	str	r2, [r3, #20]
+ 8003d00:	4b0e      	ldr	r3, [pc, #56]	; (8003d3c <_ZL19MX_USART3_UART_Initv+0x60>)
+ 8003d02:	220c      	movs	r2, #12
+ 8003d04:	615a      	str	r2, [r3, #20]
   huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
- 8003296:	4b0d      	ldr	r3, [pc, #52]	; (80032cc <_ZL19MX_USART3_UART_Initv+0x60>)
- 8003298:	2200      	movs	r2, #0
- 800329a:	619a      	str	r2, [r3, #24]
+ 8003d06:	4b0d      	ldr	r3, [pc, #52]	; (8003d3c <_ZL19MX_USART3_UART_Initv+0x60>)
+ 8003d08:	2200      	movs	r2, #0
+ 8003d0a:	619a      	str	r2, [r3, #24]
   huart3.Init.OverSampling = UART_OVERSAMPLING_16;
- 800329c:	4b0b      	ldr	r3, [pc, #44]	; (80032cc <_ZL19MX_USART3_UART_Initv+0x60>)
- 800329e:	2200      	movs	r2, #0
- 80032a0:	61da      	str	r2, [r3, #28]
+ 8003d0c:	4b0b      	ldr	r3, [pc, #44]	; (8003d3c <_ZL19MX_USART3_UART_Initv+0x60>)
+ 8003d0e:	2200      	movs	r2, #0
+ 8003d10:	61da      	str	r2, [r3, #28]
   huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
- 80032a2:	4b0a      	ldr	r3, [pc, #40]	; (80032cc <_ZL19MX_USART3_UART_Initv+0x60>)
- 80032a4:	2200      	movs	r2, #0
- 80032a6:	621a      	str	r2, [r3, #32]
+ 8003d12:	4b0a      	ldr	r3, [pc, #40]	; (8003d3c <_ZL19MX_USART3_UART_Initv+0x60>)
+ 8003d14:	2200      	movs	r2, #0
+ 8003d16:	621a      	str	r2, [r3, #32]
   huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
- 80032a8:	4b08      	ldr	r3, [pc, #32]	; (80032cc <_ZL19MX_USART3_UART_Initv+0x60>)
- 80032aa:	2200      	movs	r2, #0
- 80032ac:	625a      	str	r2, [r3, #36]	; 0x24
+ 8003d18:	4b08      	ldr	r3, [pc, #32]	; (8003d3c <_ZL19MX_USART3_UART_Initv+0x60>)
+ 8003d1a:	2200      	movs	r2, #0
+ 8003d1c:	625a      	str	r2, [r3, #36]	; 0x24
   if (HAL_UART_Init(&huart3) != HAL_OK)
- 80032ae:	4807      	ldr	r0, [pc, #28]	; (80032cc <_ZL19MX_USART3_UART_Initv+0x60>)
- 80032b0:	f7ff f95a 	bl	8002568 <HAL_UART_Init>
- 80032b4:	4603      	mov	r3, r0
- 80032b6:	2b00      	cmp	r3, #0
- 80032b8:	bf14      	ite	ne
- 80032ba:	2301      	movne	r3, #1
- 80032bc:	2300      	moveq	r3, #0
- 80032be:	b2db      	uxtb	r3, r3
- 80032c0:	2b00      	cmp	r3, #0
- 80032c2:	d001      	beq.n	80032c8 <_ZL19MX_USART3_UART_Initv+0x5c>
+ 8003d1e:	4807      	ldr	r0, [pc, #28]	; (8003d3c <_ZL19MX_USART3_UART_Initv+0x60>)
+ 8003d20:	f7ff f83c 	bl	8002d9c <HAL_UART_Init>
+ 8003d24:	4603      	mov	r3, r0
+ 8003d26:	2b00      	cmp	r3, #0
+ 8003d28:	bf14      	ite	ne
+ 8003d2a:	2301      	movne	r3, #1
+ 8003d2c:	2300      	moveq	r3, #0
+ 8003d2e:	b2db      	uxtb	r3, r3
+ 8003d30:	2b00      	cmp	r3, #0
+ 8003d32:	d001      	beq.n	8003d38 <_ZL19MX_USART3_UART_Initv+0x5c>
   {
     Error_Handler();
- 80032c4:	f000 f850 	bl	8003368 <Error_Handler>
+ 8003d34:	f000 f8d4 	bl	8003ee0 <Error_Handler>
   }
   /* USER CODE BEGIN USART3_Init 2 */
 
   /* USER CODE END USART3_Init 2 */
 
 }
- 80032c8:	bf00      	nop
- 80032ca:	bd80      	pop	{r7, pc}
- 80032cc:	20000068 	.word	0x20000068
- 80032d0:	40004800 	.word	0x40004800
+ 8003d38:	bf00      	nop
+ 8003d3a:	bd80      	pop	{r7, pc}
+ 8003d3c:	200000e8 	.word	0x200000e8
+ 8003d40:	40004800 	.word	0x40004800
 
-080032d4 <_ZL11MX_DMA_Initv>:
+08003d44 <_ZL11MX_DMA_Initv>:
 
 /** 
   * Enable DMA controller clock
   */
 static void MX_DMA_Init(void) 
 {
- 80032d4:	b580      	push	{r7, lr}
- 80032d6:	b082      	sub	sp, #8
- 80032d8:	af00      	add	r7, sp, #0
+ 8003d44:	b580      	push	{r7, lr}
+ 8003d46:	b082      	sub	sp, #8
+ 8003d48:	af00      	add	r7, sp, #0
 
   /* DMA controller clock enable */
   __HAL_RCC_DMA1_CLK_ENABLE();
- 80032da:	4b10      	ldr	r3, [pc, #64]	; (800331c <_ZL11MX_DMA_Initv+0x48>)
- 80032dc:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 80032de:	4a0f      	ldr	r2, [pc, #60]	; (800331c <_ZL11MX_DMA_Initv+0x48>)
- 80032e0:	f443 1300 	orr.w	r3, r3, #2097152	; 0x200000
- 80032e4:	6313      	str	r3, [r2, #48]	; 0x30
- 80032e6:	4b0d      	ldr	r3, [pc, #52]	; (800331c <_ZL11MX_DMA_Initv+0x48>)
- 80032e8:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 80032ea:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
- 80032ee:	607b      	str	r3, [r7, #4]
- 80032f0:	687b      	ldr	r3, [r7, #4]
+ 8003d4a:	4b10      	ldr	r3, [pc, #64]	; (8003d8c <_ZL11MX_DMA_Initv+0x48>)
+ 8003d4c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8003d4e:	4a0f      	ldr	r2, [pc, #60]	; (8003d8c <_ZL11MX_DMA_Initv+0x48>)
+ 8003d50:	f443 1300 	orr.w	r3, r3, #2097152	; 0x200000
+ 8003d54:	6313      	str	r3, [r2, #48]	; 0x30
+ 8003d56:	4b0d      	ldr	r3, [pc, #52]	; (8003d8c <_ZL11MX_DMA_Initv+0x48>)
+ 8003d58:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8003d5a:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
+ 8003d5e:	607b      	str	r3, [r7, #4]
+ 8003d60:	687b      	ldr	r3, [r7, #4]
 
   /* DMA interrupt init */
   /* DMA1_Stream1_IRQn interrupt configuration */
   HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 0, 0);
- 80032f2:	2200      	movs	r2, #0
- 80032f4:	2100      	movs	r1, #0
- 80032f6:	200c      	movs	r0, #12
- 80032f8:	f7fd fa57 	bl	80007aa <HAL_NVIC_SetPriority>
+ 8003d62:	2200      	movs	r2, #0
+ 8003d64:	2100      	movs	r1, #0
+ 8003d66:	200c      	movs	r0, #12
+ 8003d68:	f7fc fd1f 	bl	80007aa <HAL_NVIC_SetPriority>
   HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
- 80032fc:	200c      	movs	r0, #12
- 80032fe:	f7fd fa70 	bl	80007e2 <HAL_NVIC_EnableIRQ>
+ 8003d6c:	200c      	movs	r0, #12
+ 8003d6e:	f7fc fd38 	bl	80007e2 <HAL_NVIC_EnableIRQ>
   /* DMA1_Stream3_IRQn interrupt configuration */
   HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 0, 0);
- 8003302:	2200      	movs	r2, #0
- 8003304:	2100      	movs	r1, #0
- 8003306:	200e      	movs	r0, #14
- 8003308:	f7fd fa4f 	bl	80007aa <HAL_NVIC_SetPriority>
+ 8003d72:	2200      	movs	r2, #0
+ 8003d74:	2100      	movs	r1, #0
+ 8003d76:	200e      	movs	r0, #14
+ 8003d78:	f7fc fd17 	bl	80007aa <HAL_NVIC_SetPriority>
   HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn);
- 800330c:	200e      	movs	r0, #14
- 800330e:	f7fd fa68 	bl	80007e2 <HAL_NVIC_EnableIRQ>
+ 8003d7c:	200e      	movs	r0, #14
+ 8003d7e:	f7fc fd30 	bl	80007e2 <HAL_NVIC_EnableIRQ>
 
 }
- 8003312:	bf00      	nop
- 8003314:	3708      	adds	r7, #8
- 8003316:	46bd      	mov	sp, r7
- 8003318:	bd80      	pop	{r7, pc}
- 800331a:	bf00      	nop
- 800331c:	40023800 	.word	0x40023800
-
-08003320 <_ZL12MX_GPIO_Initv>:
+ 8003d82:	bf00      	nop
+ 8003d84:	3708      	adds	r7, #8
+ 8003d86:	46bd      	mov	sp, r7
+ 8003d88:	bd80      	pop	{r7, pc}
+ 8003d8a:	bf00      	nop
+ 8003d8c:	40023800 	.word	0x40023800
+
+08003d90 <_ZL12MX_GPIO_Initv>:
   * @brief GPIO Initialization Function
   * @param None
   * @retval None
   */
 static void MX_GPIO_Init(void)
 {
- 8003320:	b480      	push	{r7}
- 8003322:	b083      	sub	sp, #12
- 8003324:	af00      	add	r7, sp, #0
+ 8003d90:	b580      	push	{r7, lr}
+ 8003d92:	b08c      	sub	sp, #48	; 0x30
+ 8003d94:	af00      	add	r7, sp, #0
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8003d96:	f107 031c 	add.w	r3, r7, #28
+ 8003d9a:	2200      	movs	r2, #0
+ 8003d9c:	601a      	str	r2, [r3, #0]
+ 8003d9e:	605a      	str	r2, [r3, #4]
+ 8003da0:	609a      	str	r2, [r3, #8]
+ 8003da2:	60da      	str	r2, [r3, #12]
+ 8003da4:	611a      	str	r2, [r3, #16]
 
   /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+ 8003da6:	4b49      	ldr	r3, [pc, #292]	; (8003ecc <_ZL12MX_GPIO_Initv+0x13c>)
+ 8003da8:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8003daa:	4a48      	ldr	r2, [pc, #288]	; (8003ecc <_ZL12MX_GPIO_Initv+0x13c>)
+ 8003dac:	f043 0304 	orr.w	r3, r3, #4
+ 8003db0:	6313      	str	r3, [r2, #48]	; 0x30
+ 8003db2:	4b46      	ldr	r3, [pc, #280]	; (8003ecc <_ZL12MX_GPIO_Initv+0x13c>)
+ 8003db4:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8003db6:	f003 0304 	and.w	r3, r3, #4
+ 8003dba:	61bb      	str	r3, [r7, #24]
+ 8003dbc:	69bb      	ldr	r3, [r7, #24]
   __HAL_RCC_GPIOA_CLK_ENABLE();
- 8003326:	4b0f      	ldr	r3, [pc, #60]	; (8003364 <_ZL12MX_GPIO_Initv+0x44>)
- 8003328:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 800332a:	4a0e      	ldr	r2, [pc, #56]	; (8003364 <_ZL12MX_GPIO_Initv+0x44>)
- 800332c:	f043 0301 	orr.w	r3, r3, #1
- 8003330:	6313      	str	r3, [r2, #48]	; 0x30
- 8003332:	4b0c      	ldr	r3, [pc, #48]	; (8003364 <_ZL12MX_GPIO_Initv+0x44>)
- 8003334:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8003336:	f003 0301 	and.w	r3, r3, #1
- 800333a:	607b      	str	r3, [r7, #4]
- 800333c:	687b      	ldr	r3, [r7, #4]
+ 8003dbe:	4b43      	ldr	r3, [pc, #268]	; (8003ecc <_ZL12MX_GPIO_Initv+0x13c>)
+ 8003dc0:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8003dc2:	4a42      	ldr	r2, [pc, #264]	; (8003ecc <_ZL12MX_GPIO_Initv+0x13c>)
+ 8003dc4:	f043 0301 	orr.w	r3, r3, #1
+ 8003dc8:	6313      	str	r3, [r2, #48]	; 0x30
+ 8003dca:	4b40      	ldr	r3, [pc, #256]	; (8003ecc <_ZL12MX_GPIO_Initv+0x13c>)
+ 8003dcc:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8003dce:	f003 0301 	and.w	r3, r3, #1
+ 8003dd2:	617b      	str	r3, [r7, #20]
+ 8003dd4:	697b      	ldr	r3, [r7, #20]
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+ 8003dd6:	4b3d      	ldr	r3, [pc, #244]	; (8003ecc <_ZL12MX_GPIO_Initv+0x13c>)
+ 8003dd8:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8003dda:	4a3c      	ldr	r2, [pc, #240]	; (8003ecc <_ZL12MX_GPIO_Initv+0x13c>)
+ 8003ddc:	f043 0320 	orr.w	r3, r3, #32
+ 8003de0:	6313      	str	r3, [r2, #48]	; 0x30
+ 8003de2:	4b3a      	ldr	r3, [pc, #232]	; (8003ecc <_ZL12MX_GPIO_Initv+0x13c>)
+ 8003de4:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8003de6:	f003 0320 	and.w	r3, r3, #32
+ 8003dea:	613b      	str	r3, [r7, #16]
+ 8003dec:	693b      	ldr	r3, [r7, #16]
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+ 8003dee:	4b37      	ldr	r3, [pc, #220]	; (8003ecc <_ZL12MX_GPIO_Initv+0x13c>)
+ 8003df0:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8003df2:	4a36      	ldr	r2, [pc, #216]	; (8003ecc <_ZL12MX_GPIO_Initv+0x13c>)
+ 8003df4:	f043 0310 	orr.w	r3, r3, #16
+ 8003df8:	6313      	str	r3, [r2, #48]	; 0x30
+ 8003dfa:	4b34      	ldr	r3, [pc, #208]	; (8003ecc <_ZL12MX_GPIO_Initv+0x13c>)
+ 8003dfc:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8003dfe:	f003 0310 	and.w	r3, r3, #16
+ 8003e02:	60fb      	str	r3, [r7, #12]
+ 8003e04:	68fb      	ldr	r3, [r7, #12]
   __HAL_RCC_GPIOD_CLK_ENABLE();
- 800333e:	4b09      	ldr	r3, [pc, #36]	; (8003364 <_ZL12MX_GPIO_Initv+0x44>)
- 8003340:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8003342:	4a08      	ldr	r2, [pc, #32]	; (8003364 <_ZL12MX_GPIO_Initv+0x44>)
- 8003344:	f043 0308 	orr.w	r3, r3, #8
- 8003348:	6313      	str	r3, [r2, #48]	; 0x30
- 800334a:	4b06      	ldr	r3, [pc, #24]	; (8003364 <_ZL12MX_GPIO_Initv+0x44>)
- 800334c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 800334e:	f003 0308 	and.w	r3, r3, #8
- 8003352:	603b      	str	r3, [r7, #0]
- 8003354:	683b      	ldr	r3, [r7, #0]
+ 8003e06:	4b31      	ldr	r3, [pc, #196]	; (8003ecc <_ZL12MX_GPIO_Initv+0x13c>)
+ 8003e08:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8003e0a:	4a30      	ldr	r2, [pc, #192]	; (8003ecc <_ZL12MX_GPIO_Initv+0x13c>)
+ 8003e0c:	f043 0308 	orr.w	r3, r3, #8
+ 8003e10:	6313      	str	r3, [r2, #48]	; 0x30
+ 8003e12:	4b2e      	ldr	r3, [pc, #184]	; (8003ecc <_ZL12MX_GPIO_Initv+0x13c>)
+ 8003e14:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8003e16:	f003 0308 	and.w	r3, r3, #8
+ 8003e1a:	60bb      	str	r3, [r7, #8]
+ 8003e1c:	68bb      	ldr	r3, [r7, #8]
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+ 8003e1e:	4b2b      	ldr	r3, [pc, #172]	; (8003ecc <_ZL12MX_GPIO_Initv+0x13c>)
+ 8003e20:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8003e22:	4a2a      	ldr	r2, [pc, #168]	; (8003ecc <_ZL12MX_GPIO_Initv+0x13c>)
+ 8003e24:	f043 0302 	orr.w	r3, r3, #2
+ 8003e28:	6313      	str	r3, [r2, #48]	; 0x30
+ 8003e2a:	4b28      	ldr	r3, [pc, #160]	; (8003ecc <_ZL12MX_GPIO_Initv+0x13c>)
+ 8003e2c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8003e2e:	f003 0302 	and.w	r3, r3, #2
+ 8003e32:	607b      	str	r3, [r7, #4]
+ 8003e34:	687b      	ldr	r3, [r7, #4]
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOF, GPIO_PIN_12|dir_1_Pin|sleep_2_Pin|sleep_1_Pin, GPIO_PIN_RESET);
+ 8003e36:	2200      	movs	r2, #0
+ 8003e38:	f44f 4170 	mov.w	r1, #61440	; 0xf000
+ 8003e3c:	4824      	ldr	r0, [pc, #144]	; (8003ed0 <_ZL12MX_GPIO_Initv+0x140>)
+ 8003e3e:	f7fd f99f 	bl	8001180 <HAL_GPIO_WritePin>
+
+  /*Configure GPIO pin : PC0 */
+  GPIO_InitStruct.Pin = GPIO_PIN_0;
+ 8003e42:	2301      	movs	r3, #1
+ 8003e44:	61fb      	str	r3, [r7, #28]
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 8003e46:	2303      	movs	r3, #3
+ 8003e48:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8003e4a:	2300      	movs	r3, #0
+ 8003e4c:	627b      	str	r3, [r7, #36]	; 0x24
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 8003e4e:	f107 031c 	add.w	r3, r7, #28
+ 8003e52:	4619      	mov	r1, r3
+ 8003e54:	481f      	ldr	r0, [pc, #124]	; (8003ed4 <_ZL12MX_GPIO_Initv+0x144>)
+ 8003e56:	f7fc ffe9 	bl	8000e2c <HAL_GPIO_Init>
+
+  /*Configure GPIO pin : current_1_Pin */
+  GPIO_InitStruct.Pin = current_1_Pin;
+ 8003e5a:	2308      	movs	r3, #8
+ 8003e5c:	61fb      	str	r3, [r7, #28]
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 8003e5e:	2303      	movs	r3, #3
+ 8003e60:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8003e62:	2300      	movs	r3, #0
+ 8003e64:	627b      	str	r3, [r7, #36]	; 0x24
+  HAL_GPIO_Init(current_1_GPIO_Port, &GPIO_InitStruct);
+ 8003e66:	f107 031c 	add.w	r3, r7, #28
+ 8003e6a:	4619      	mov	r1, r3
+ 8003e6c:	481a      	ldr	r0, [pc, #104]	; (8003ed8 <_ZL12MX_GPIO_Initv+0x148>)
+ 8003e6e:	f7fc ffdd 	bl	8000e2c <HAL_GPIO_Init>
+
+  /*Configure GPIO pin : fault_2_Pin */
+  GPIO_InitStruct.Pin = fault_2_Pin;
+ 8003e72:	2340      	movs	r3, #64	; 0x40
+ 8003e74:	61fb      	str	r3, [r7, #28]
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 8003e76:	2300      	movs	r3, #0
+ 8003e78:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8003e7a:	2300      	movs	r3, #0
+ 8003e7c:	627b      	str	r3, [r7, #36]	; 0x24
+  HAL_GPIO_Init(fault_2_GPIO_Port, &GPIO_InitStruct);
+ 8003e7e:	f107 031c 	add.w	r3, r7, #28
+ 8003e82:	4619      	mov	r1, r3
+ 8003e84:	4814      	ldr	r0, [pc, #80]	; (8003ed8 <_ZL12MX_GPIO_Initv+0x148>)
+ 8003e86:	f7fc ffd1 	bl	8000e2c <HAL_GPIO_Init>
+
+  /*Configure GPIO pins : PF12 dir_1_Pin sleep_2_Pin sleep_1_Pin */
+  GPIO_InitStruct.Pin = GPIO_PIN_12|dir_1_Pin|sleep_2_Pin|sleep_1_Pin;
+ 8003e8a:	f44f 4370 	mov.w	r3, #61440	; 0xf000
+ 8003e8e:	61fb      	str	r3, [r7, #28]
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 8003e90:	2301      	movs	r3, #1
+ 8003e92:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8003e94:	2300      	movs	r3, #0
+ 8003e96:	627b      	str	r3, [r7, #36]	; 0x24
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8003e98:	2300      	movs	r3, #0
+ 8003e9a:	62bb      	str	r3, [r7, #40]	; 0x28
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+ 8003e9c:	f107 031c 	add.w	r3, r7, #28
+ 8003ea0:	4619      	mov	r1, r3
+ 8003ea2:	480b      	ldr	r0, [pc, #44]	; (8003ed0 <_ZL12MX_GPIO_Initv+0x140>)
+ 8003ea4:	f7fc ffc2 	bl	8000e2c <HAL_GPIO_Init>
+
+  /*Configure GPIO pin : fault_1_Pin */
+  GPIO_InitStruct.Pin = fault_1_Pin;
+ 8003ea8:	f44f 7300 	mov.w	r3, #512	; 0x200
+ 8003eac:	61fb      	str	r3, [r7, #28]
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 8003eae:	2300      	movs	r3, #0
+ 8003eb0:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8003eb2:	2300      	movs	r3, #0
+ 8003eb4:	627b      	str	r3, [r7, #36]	; 0x24
+  HAL_GPIO_Init(fault_1_GPIO_Port, &GPIO_InitStruct);
+ 8003eb6:	f107 031c 	add.w	r3, r7, #28
+ 8003eba:	4619      	mov	r1, r3
+ 8003ebc:	4807      	ldr	r0, [pc, #28]	; (8003edc <_ZL12MX_GPIO_Initv+0x14c>)
+ 8003ebe:	f7fc ffb5 	bl	8000e2c <HAL_GPIO_Init>
 
 }
- 8003356:	bf00      	nop
- 8003358:	370c      	adds	r7, #12
- 800335a:	46bd      	mov	sp, r7
- 800335c:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8003360:	4770      	bx	lr
- 8003362:	bf00      	nop
- 8003364:	40023800 	.word	0x40023800
-
-08003368 <Error_Handler>:
+ 8003ec2:	bf00      	nop
+ 8003ec4:	3730      	adds	r7, #48	; 0x30
+ 8003ec6:	46bd      	mov	sp, r7
+ 8003ec8:	bd80      	pop	{r7, pc}
+ 8003eca:	bf00      	nop
+ 8003ecc:	40023800 	.word	0x40023800
+ 8003ed0:	40021400 	.word	0x40021400
+ 8003ed4:	40020800 	.word	0x40020800
+ 8003ed8:	40020000 	.word	0x40020000
+ 8003edc:	40021000 	.word	0x40021000
+
+08003ee0 <Error_Handler>:
 /**
   * @brief  This function is executed in case of error occurrence.
   * @retval None
   */
 void Error_Handler(void)
 {
- 8003368:	b480      	push	{r7}
- 800336a:	af00      	add	r7, sp, #0
+ 8003ee0:	b480      	push	{r7}
+ 8003ee2:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN Error_Handler_Debug */
   /* User can add his own implementation to report the HAL error return state */
 
   /* USER CODE END Error_Handler_Debug */
 }
- 800336c:	bf00      	nop
- 800336e:	46bd      	mov	sp, r7
- 8003370:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8003374:	4770      	bx	lr
+ 8003ee4:	bf00      	nop
+ 8003ee6:	46bd      	mov	sp, r7
+ 8003ee8:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8003eec:	4770      	bx	lr
 	...
 
-08003378 <HAL_MspInit>:
-/* USER CODE END 0 */
-/**
+08003ef0 <HAL_MspInit>:
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+                    /**
   * Initializes the Global MSP.
   */
 void HAL_MspInit(void)
 {
- 8003378:	b480      	push	{r7}
- 800337a:	b083      	sub	sp, #12
- 800337c:	af00      	add	r7, sp, #0
+ 8003ef0:	b480      	push	{r7}
+ 8003ef2:	b083      	sub	sp, #12
+ 8003ef4:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN MspInit 0 */
 
   /* USER CODE END MspInit 0 */
 
   __HAL_RCC_PWR_CLK_ENABLE();
- 800337e:	4b0f      	ldr	r3, [pc, #60]	; (80033bc <HAL_MspInit+0x44>)
- 8003380:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 8003382:	4a0e      	ldr	r2, [pc, #56]	; (80033bc <HAL_MspInit+0x44>)
- 8003384:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
- 8003388:	6413      	str	r3, [r2, #64]	; 0x40
- 800338a:	4b0c      	ldr	r3, [pc, #48]	; (80033bc <HAL_MspInit+0x44>)
- 800338c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 800338e:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
- 8003392:	607b      	str	r3, [r7, #4]
- 8003394:	687b      	ldr	r3, [r7, #4]
+ 8003ef6:	4b0f      	ldr	r3, [pc, #60]	; (8003f34 <HAL_MspInit+0x44>)
+ 8003ef8:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8003efa:	4a0e      	ldr	r2, [pc, #56]	; (8003f34 <HAL_MspInit+0x44>)
+ 8003efc:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
+ 8003f00:	6413      	str	r3, [r2, #64]	; 0x40
+ 8003f02:	4b0c      	ldr	r3, [pc, #48]	; (8003f34 <HAL_MspInit+0x44>)
+ 8003f04:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8003f06:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
+ 8003f0a:	607b      	str	r3, [r7, #4]
+ 8003f0c:	687b      	ldr	r3, [r7, #4]
   __HAL_RCC_SYSCFG_CLK_ENABLE();
- 8003396:	4b09      	ldr	r3, [pc, #36]	; (80033bc <HAL_MspInit+0x44>)
- 8003398:	6c5b      	ldr	r3, [r3, #68]	; 0x44
- 800339a:	4a08      	ldr	r2, [pc, #32]	; (80033bc <HAL_MspInit+0x44>)
- 800339c:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
- 80033a0:	6453      	str	r3, [r2, #68]	; 0x44
- 80033a2:	4b06      	ldr	r3, [pc, #24]	; (80033bc <HAL_MspInit+0x44>)
- 80033a4:	6c5b      	ldr	r3, [r3, #68]	; 0x44
- 80033a6:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
- 80033aa:	603b      	str	r3, [r7, #0]
- 80033ac:	683b      	ldr	r3, [r7, #0]
+ 8003f0e:	4b09      	ldr	r3, [pc, #36]	; (8003f34 <HAL_MspInit+0x44>)
+ 8003f10:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 8003f12:	4a08      	ldr	r2, [pc, #32]	; (8003f34 <HAL_MspInit+0x44>)
+ 8003f14:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
+ 8003f18:	6453      	str	r3, [r2, #68]	; 0x44
+ 8003f1a:	4b06      	ldr	r3, [pc, #24]	; (8003f34 <HAL_MspInit+0x44>)
+ 8003f1c:	6c5b      	ldr	r3, [r3, #68]	; 0x44
+ 8003f1e:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
+ 8003f22:	603b      	str	r3, [r7, #0]
+ 8003f24:	683b      	ldr	r3, [r7, #0]
   /* System interrupt init*/
 
   /* USER CODE BEGIN MspInit 1 */
 
   /* USER CODE END MspInit 1 */
 }
- 80033ae:	bf00      	nop
- 80033b0:	370c      	adds	r7, #12
- 80033b2:	46bd      	mov	sp, r7
- 80033b4:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80033b8:	4770      	bx	lr
- 80033ba:	bf00      	nop
- 80033bc:	40023800 	.word	0x40023800
-
-080033c0 <HAL_TIM_Encoder_MspInit>:
+ 8003f26:	bf00      	nop
+ 8003f28:	370c      	adds	r7, #12
+ 8003f2a:	46bd      	mov	sp, r7
+ 8003f2c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8003f30:	4770      	bx	lr
+ 8003f32:	bf00      	nop
+ 8003f34:	40023800 	.word	0x40023800
+
+08003f38 <HAL_TIM_Encoder_MspInit>:
 * This function configures the hardware resources used in this example
 * @param htim_encoder: TIM_Encoder handle pointer
 * @retval None
 */
 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
 {
- 80033c0:	b580      	push	{r7, lr}
- 80033c2:	b08a      	sub	sp, #40	; 0x28
- 80033c4:	af00      	add	r7, sp, #0
- 80033c6:	6078      	str	r0, [r7, #4]
+ 8003f38:	b580      	push	{r7, lr}
+ 8003f3a:	b08c      	sub	sp, #48	; 0x30
+ 8003f3c:	af00      	add	r7, sp, #0
+ 8003f3e:	6078      	str	r0, [r7, #4]
   GPIO_InitTypeDef GPIO_InitStruct = {0};
- 80033c8:	f107 0314 	add.w	r3, r7, #20
- 80033cc:	2200      	movs	r2, #0
- 80033ce:	601a      	str	r2, [r3, #0]
- 80033d0:	605a      	str	r2, [r3, #4]
- 80033d2:	609a      	str	r2, [r3, #8]
- 80033d4:	60da      	str	r2, [r3, #12]
- 80033d6:	611a      	str	r2, [r3, #16]
+ 8003f40:	f107 031c 	add.w	r3, r7, #28
+ 8003f44:	2200      	movs	r2, #0
+ 8003f46:	601a      	str	r2, [r3, #0]
+ 8003f48:	605a      	str	r2, [r3, #4]
+ 8003f4a:	609a      	str	r2, [r3, #8]
+ 8003f4c:	60da      	str	r2, [r3, #12]
+ 8003f4e:	611a      	str	r2, [r3, #16]
   if(htim_encoder->Instance==TIM2)
- 80033d8:	687b      	ldr	r3, [r7, #4]
- 80033da:	681b      	ldr	r3, [r3, #0]
- 80033dc:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
- 80033e0:	d127      	bne.n	8003432 <HAL_TIM_Encoder_MspInit+0x72>
+ 8003f50:	687b      	ldr	r3, [r7, #4]
+ 8003f52:	681b      	ldr	r3, [r3, #0]
+ 8003f54:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
+ 8003f58:	d144      	bne.n	8003fe4 <HAL_TIM_Encoder_MspInit+0xac>
   {
   /* USER CODE BEGIN TIM2_MspInit 0 */
 
   /* USER CODE END TIM2_MspInit 0 */
     /* Peripheral clock enable */
     __HAL_RCC_TIM2_CLK_ENABLE();
- 80033e2:	4b16      	ldr	r3, [pc, #88]	; (800343c <HAL_TIM_Encoder_MspInit+0x7c>)
- 80033e4:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 80033e6:	4a15      	ldr	r2, [pc, #84]	; (800343c <HAL_TIM_Encoder_MspInit+0x7c>)
- 80033e8:	f043 0301 	orr.w	r3, r3, #1
- 80033ec:	6413      	str	r3, [r2, #64]	; 0x40
- 80033ee:	4b13      	ldr	r3, [pc, #76]	; (800343c <HAL_TIM_Encoder_MspInit+0x7c>)
- 80033f0:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 80033f2:	f003 0301 	and.w	r3, r3, #1
- 80033f6:	613b      	str	r3, [r7, #16]
- 80033f8:	693b      	ldr	r3, [r7, #16]
+ 8003f5a:	4b3b      	ldr	r3, [pc, #236]	; (8004048 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8003f5c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8003f5e:	4a3a      	ldr	r2, [pc, #232]	; (8004048 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8003f60:	f043 0301 	orr.w	r3, r3, #1
+ 8003f64:	6413      	str	r3, [r2, #64]	; 0x40
+ 8003f66:	4b38      	ldr	r3, [pc, #224]	; (8004048 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8003f68:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8003f6a:	f003 0301 	and.w	r3, r3, #1
+ 8003f6e:	61bb      	str	r3, [r7, #24]
+ 8003f70:	69bb      	ldr	r3, [r7, #24]
   
     __HAL_RCC_GPIOA_CLK_ENABLE();
- 80033fa:	4b10      	ldr	r3, [pc, #64]	; (800343c <HAL_TIM_Encoder_MspInit+0x7c>)
- 80033fc:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 80033fe:	4a0f      	ldr	r2, [pc, #60]	; (800343c <HAL_TIM_Encoder_MspInit+0x7c>)
- 8003400:	f043 0301 	orr.w	r3, r3, #1
- 8003404:	6313      	str	r3, [r2, #48]	; 0x30
- 8003406:	4b0d      	ldr	r3, [pc, #52]	; (800343c <HAL_TIM_Encoder_MspInit+0x7c>)
- 8003408:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 800340a:	f003 0301 	and.w	r3, r3, #1
- 800340e:	60fb      	str	r3, [r7, #12]
- 8003410:	68fb      	ldr	r3, [r7, #12]
+ 8003f72:	4b35      	ldr	r3, [pc, #212]	; (8004048 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8003f74:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8003f76:	4a34      	ldr	r2, [pc, #208]	; (8004048 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8003f78:	f043 0301 	orr.w	r3, r3, #1
+ 8003f7c:	6313      	str	r3, [r2, #48]	; 0x30
+ 8003f7e:	4b32      	ldr	r3, [pc, #200]	; (8004048 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8003f80:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8003f82:	f003 0301 	and.w	r3, r3, #1
+ 8003f86:	617b      	str	r3, [r7, #20]
+ 8003f88:	697b      	ldr	r3, [r7, #20]
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+ 8003f8a:	4b2f      	ldr	r3, [pc, #188]	; (8004048 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8003f8c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8003f8e:	4a2e      	ldr	r2, [pc, #184]	; (8004048 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8003f90:	f043 0302 	orr.w	r3, r3, #2
+ 8003f94:	6313      	str	r3, [r2, #48]	; 0x30
+ 8003f96:	4b2c      	ldr	r3, [pc, #176]	; (8004048 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8003f98:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8003f9a:	f003 0302 	and.w	r3, r3, #2
+ 8003f9e:	613b      	str	r3, [r7, #16]
+ 8003fa0:	693b      	ldr	r3, [r7, #16]
     /**TIM2 GPIO Configuration    
-    PA0/WKUP     ------> TIM2_CH1
-    PA1     ------> TIM2_CH2 
+    PA5     ------> TIM2_CH1
+    PB3     ------> TIM2_CH2 
     */
-    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
- 8003412:	2303      	movs	r3, #3
- 8003414:	617b      	str	r3, [r7, #20]
+    GPIO_InitStruct.Pin = GPIO_PIN_5;
+ 8003fa2:	2320      	movs	r3, #32
+ 8003fa4:	61fb      	str	r3, [r7, #28]
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8003416:	2302      	movs	r3, #2
- 8003418:	61bb      	str	r3, [r7, #24]
+ 8003fa6:	2302      	movs	r3, #2
+ 8003fa8:	623b      	str	r3, [r7, #32]
     GPIO_InitStruct.Pull = GPIO_NOPULL;
- 800341a:	2300      	movs	r3, #0
- 800341c:	61fb      	str	r3, [r7, #28]
+ 8003faa:	2300      	movs	r3, #0
+ 8003fac:	627b      	str	r3, [r7, #36]	; 0x24
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 800341e:	2300      	movs	r3, #0
- 8003420:	623b      	str	r3, [r7, #32]
+ 8003fae:	2300      	movs	r3, #0
+ 8003fb0:	62bb      	str	r3, [r7, #40]	; 0x28
     GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
- 8003422:	2301      	movs	r3, #1
- 8003424:	627b      	str	r3, [r7, #36]	; 0x24
+ 8003fb2:	2301      	movs	r3, #1
+ 8003fb4:	62fb      	str	r3, [r7, #44]	; 0x2c
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 8003426:	f107 0314 	add.w	r3, r7, #20
- 800342a:	4619      	mov	r1, r3
- 800342c:	4804      	ldr	r0, [pc, #16]	; (8003440 <HAL_TIM_Encoder_MspInit+0x80>)
- 800342e:	f7fd fcfd 	bl	8000e2c <HAL_GPIO_Init>
-  /* USER CODE BEGIN TIM2_MspInit 1 */
+ 8003fb6:	f107 031c 	add.w	r3, r7, #28
+ 8003fba:	4619      	mov	r1, r3
+ 8003fbc:	4823      	ldr	r0, [pc, #140]	; (800404c <HAL_TIM_Encoder_MspInit+0x114>)
+ 8003fbe:	f7fc ff35 	bl	8000e2c <HAL_GPIO_Init>
+
+    GPIO_InitStruct.Pin = GPIO_PIN_3;
+ 8003fc2:	2308      	movs	r3, #8
+ 8003fc4:	61fb      	str	r3, [r7, #28]
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8003fc6:	2302      	movs	r3, #2
+ 8003fc8:	623b      	str	r3, [r7, #32]
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8003fca:	2300      	movs	r3, #0
+ 8003fcc:	627b      	str	r3, [r7, #36]	; 0x24
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8003fce:	2300      	movs	r3, #0
+ 8003fd0:	62bb      	str	r3, [r7, #40]	; 0x28
+    GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
+ 8003fd2:	2301      	movs	r3, #1
+ 8003fd4:	62fb      	str	r3, [r7, #44]	; 0x2c
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8003fd6:	f107 031c 	add.w	r3, r7, #28
+ 8003fda:	4619      	mov	r1, r3
+ 8003fdc:	481c      	ldr	r0, [pc, #112]	; (8004050 <HAL_TIM_Encoder_MspInit+0x118>)
+ 8003fde:	f7fc ff25 	bl	8000e2c <HAL_GPIO_Init>
+  /* USER CODE BEGIN TIM5_MspInit 1 */
+
+  /* USER CODE END TIM5_MspInit 1 */
+  }
 
-  /* USER CODE END TIM2_MspInit 1 */
+}
+ 8003fe2:	e02c      	b.n	800403e <HAL_TIM_Encoder_MspInit+0x106>
+  else if(htim_encoder->Instance==TIM5)
+ 8003fe4:	687b      	ldr	r3, [r7, #4]
+ 8003fe6:	681b      	ldr	r3, [r3, #0]
+ 8003fe8:	4a1a      	ldr	r2, [pc, #104]	; (8004054 <HAL_TIM_Encoder_MspInit+0x11c>)
+ 8003fea:	4293      	cmp	r3, r2
+ 8003fec:	d127      	bne.n	800403e <HAL_TIM_Encoder_MspInit+0x106>
+    __HAL_RCC_TIM5_CLK_ENABLE();
+ 8003fee:	4b16      	ldr	r3, [pc, #88]	; (8004048 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8003ff0:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8003ff2:	4a15      	ldr	r2, [pc, #84]	; (8004048 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8003ff4:	f043 0308 	orr.w	r3, r3, #8
+ 8003ff8:	6413      	str	r3, [r2, #64]	; 0x40
+ 8003ffa:	4b13      	ldr	r3, [pc, #76]	; (8004048 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8003ffc:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8003ffe:	f003 0308 	and.w	r3, r3, #8
+ 8004002:	60fb      	str	r3, [r7, #12]
+ 8004004:	68fb      	ldr	r3, [r7, #12]
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 8004006:	4b10      	ldr	r3, [pc, #64]	; (8004048 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8004008:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 800400a:	4a0f      	ldr	r2, [pc, #60]	; (8004048 <HAL_TIM_Encoder_MspInit+0x110>)
+ 800400c:	f043 0301 	orr.w	r3, r3, #1
+ 8004010:	6313      	str	r3, [r2, #48]	; 0x30
+ 8004012:	4b0d      	ldr	r3, [pc, #52]	; (8004048 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8004014:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8004016:	f003 0301 	and.w	r3, r3, #1
+ 800401a:	60bb      	str	r3, [r7, #8]
+ 800401c:	68bb      	ldr	r3, [r7, #8]
+    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
+ 800401e:	2303      	movs	r3, #3
+ 8004020:	61fb      	str	r3, [r7, #28]
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8004022:	2302      	movs	r3, #2
+ 8004024:	623b      	str	r3, [r7, #32]
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8004026:	2300      	movs	r3, #0
+ 8004028:	627b      	str	r3, [r7, #36]	; 0x24
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 800402a:	2300      	movs	r3, #0
+ 800402c:	62bb      	str	r3, [r7, #40]	; 0x28
+    GPIO_InitStruct.Alternate = GPIO_AF2_TIM5;
+ 800402e:	2302      	movs	r3, #2
+ 8004030:	62fb      	str	r3, [r7, #44]	; 0x2c
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8004032:	f107 031c 	add.w	r3, r7, #28
+ 8004036:	4619      	mov	r1, r3
+ 8004038:	4804      	ldr	r0, [pc, #16]	; (800404c <HAL_TIM_Encoder_MspInit+0x114>)
+ 800403a:	f7fc fef7 	bl	8000e2c <HAL_GPIO_Init>
+}
+ 800403e:	bf00      	nop
+ 8004040:	3730      	adds	r7, #48	; 0x30
+ 8004042:	46bd      	mov	sp, r7
+ 8004044:	bd80      	pop	{r7, pc}
+ 8004046:	bf00      	nop
+ 8004048:	40023800 	.word	0x40023800
+ 800404c:	40020000 	.word	0x40020000
+ 8004050:	40020400 	.word	0x40020400
+ 8004054:	40000c00 	.word	0x40000c00
+
+08004058 <HAL_TIM_PWM_MspInit>:
+* This function configures the hardware resources used in this example
+* @param htim_pwm: TIM_PWM handle pointer
+* @retval None
+*/
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
+{
+ 8004058:	b480      	push	{r7}
+ 800405a:	b085      	sub	sp, #20
+ 800405c:	af00      	add	r7, sp, #0
+ 800405e:	6078      	str	r0, [r7, #4]
+  if(htim_pwm->Instance==TIM4)
+ 8004060:	687b      	ldr	r3, [r7, #4]
+ 8004062:	681b      	ldr	r3, [r3, #0]
+ 8004064:	4a0a      	ldr	r2, [pc, #40]	; (8004090 <HAL_TIM_PWM_MspInit+0x38>)
+ 8004066:	4293      	cmp	r3, r2
+ 8004068:	d10b      	bne.n	8004082 <HAL_TIM_PWM_MspInit+0x2a>
+  {
+  /* USER CODE BEGIN TIM4_MspInit 0 */
+
+  /* USER CODE END TIM4_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM4_CLK_ENABLE();
+ 800406a:	4b0a      	ldr	r3, [pc, #40]	; (8004094 <HAL_TIM_PWM_MspInit+0x3c>)
+ 800406c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800406e:	4a09      	ldr	r2, [pc, #36]	; (8004094 <HAL_TIM_PWM_MspInit+0x3c>)
+ 8004070:	f043 0304 	orr.w	r3, r3, #4
+ 8004074:	6413      	str	r3, [r2, #64]	; 0x40
+ 8004076:	4b07      	ldr	r3, [pc, #28]	; (8004094 <HAL_TIM_PWM_MspInit+0x3c>)
+ 8004078:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800407a:	f003 0304 	and.w	r3, r3, #4
+ 800407e:	60fb      	str	r3, [r7, #12]
+ 8004080:	68fb      	ldr	r3, [r7, #12]
+  /* USER CODE BEGIN TIM4_MspInit 1 */
+
+  /* USER CODE END TIM4_MspInit 1 */
+  }
+
+}
+ 8004082:	bf00      	nop
+ 8004084:	3714      	adds	r7, #20
+ 8004086:	46bd      	mov	sp, r7
+ 8004088:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800408c:	4770      	bx	lr
+ 800408e:	bf00      	nop
+ 8004090:	40000800 	.word	0x40000800
+ 8004094:	40023800 	.word	0x40023800
+
+08004098 <HAL_TIM_MspPostInit>:
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
+{
+ 8004098:	b580      	push	{r7, lr}
+ 800409a:	b088      	sub	sp, #32
+ 800409c:	af00      	add	r7, sp, #0
+ 800409e:	6078      	str	r0, [r7, #4]
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 80040a0:	f107 030c 	add.w	r3, r7, #12
+ 80040a4:	2200      	movs	r2, #0
+ 80040a6:	601a      	str	r2, [r3, #0]
+ 80040a8:	605a      	str	r2, [r3, #4]
+ 80040aa:	609a      	str	r2, [r3, #8]
+ 80040ac:	60da      	str	r2, [r3, #12]
+ 80040ae:	611a      	str	r2, [r3, #16]
+  if(htim->Instance==TIM4)
+ 80040b0:	687b      	ldr	r3, [r7, #4]
+ 80040b2:	681b      	ldr	r3, [r3, #0]
+ 80040b4:	4a11      	ldr	r2, [pc, #68]	; (80040fc <HAL_TIM_MspPostInit+0x64>)
+ 80040b6:	4293      	cmp	r3, r2
+ 80040b8:	d11c      	bne.n	80040f4 <HAL_TIM_MspPostInit+0x5c>
+  {
+  /* USER CODE BEGIN TIM4_MspPostInit 0 */
+
+  /* USER CODE END TIM4_MspPostInit 0 */
+  
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+ 80040ba:	4b11      	ldr	r3, [pc, #68]	; (8004100 <HAL_TIM_MspPostInit+0x68>)
+ 80040bc:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 80040be:	4a10      	ldr	r2, [pc, #64]	; (8004100 <HAL_TIM_MspPostInit+0x68>)
+ 80040c0:	f043 0308 	orr.w	r3, r3, #8
+ 80040c4:	6313      	str	r3, [r2, #48]	; 0x30
+ 80040c6:	4b0e      	ldr	r3, [pc, #56]	; (8004100 <HAL_TIM_MspPostInit+0x68>)
+ 80040c8:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 80040ca:	f003 0308 	and.w	r3, r3, #8
+ 80040ce:	60bb      	str	r3, [r7, #8]
+ 80040d0:	68bb      	ldr	r3, [r7, #8]
+    /**TIM4 GPIO Configuration    
+    PD14     ------> TIM4_CH3
+    PD15     ------> TIM4_CH4 
+    */
+    GPIO_InitStruct.Pin = pwm_2_Pin|pwm_1_Pin;
+ 80040d2:	f44f 4340 	mov.w	r3, #49152	; 0xc000
+ 80040d6:	60fb      	str	r3, [r7, #12]
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 80040d8:	2302      	movs	r3, #2
+ 80040da:	613b      	str	r3, [r7, #16]
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 80040dc:	2300      	movs	r3, #0
+ 80040de:	617b      	str	r3, [r7, #20]
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 80040e0:	2300      	movs	r3, #0
+ 80040e2:	61bb      	str	r3, [r7, #24]
+    GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
+ 80040e4:	2302      	movs	r3, #2
+ 80040e6:	61fb      	str	r3, [r7, #28]
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+ 80040e8:	f107 030c 	add.w	r3, r7, #12
+ 80040ec:	4619      	mov	r1, r3
+ 80040ee:	4805      	ldr	r0, [pc, #20]	; (8004104 <HAL_TIM_MspPostInit+0x6c>)
+ 80040f0:	f7fc fe9c 	bl	8000e2c <HAL_GPIO_Init>
+  /* USER CODE BEGIN TIM4_MspPostInit 1 */
+
+  /* USER CODE END TIM4_MspPostInit 1 */
   }
 
 }
- 8003432:	bf00      	nop
- 8003434:	3728      	adds	r7, #40	; 0x28
- 8003436:	46bd      	mov	sp, r7
- 8003438:	bd80      	pop	{r7, pc}
- 800343a:	bf00      	nop
- 800343c:	40023800 	.word	0x40023800
- 8003440:	40020000 	.word	0x40020000
-
-08003444 <HAL_UART_MspInit>:
+ 80040f4:	bf00      	nop
+ 80040f6:	3720      	adds	r7, #32
+ 80040f8:	46bd      	mov	sp, r7
+ 80040fa:	bd80      	pop	{r7, pc}
+ 80040fc:	40000800 	.word	0x40000800
+ 8004100:	40023800 	.word	0x40023800
+ 8004104:	40020c00 	.word	0x40020c00
+
+08004108 <HAL_UART_MspInit>:
 * This function configures the hardware resources used in this example
 * @param huart: UART handle pointer
 * @retval None
 */
 void HAL_UART_MspInit(UART_HandleTypeDef* huart)
 {
- 8003444:	b580      	push	{r7, lr}
- 8003446:	b08a      	sub	sp, #40	; 0x28
- 8003448:	af00      	add	r7, sp, #0
- 800344a:	6078      	str	r0, [r7, #4]
+ 8004108:	b580      	push	{r7, lr}
+ 800410a:	b08a      	sub	sp, #40	; 0x28
+ 800410c:	af00      	add	r7, sp, #0
+ 800410e:	6078      	str	r0, [r7, #4]
   GPIO_InitTypeDef GPIO_InitStruct = {0};
- 800344c:	f107 0314 	add.w	r3, r7, #20
- 8003450:	2200      	movs	r2, #0
- 8003452:	601a      	str	r2, [r3, #0]
- 8003454:	605a      	str	r2, [r3, #4]
- 8003456:	609a      	str	r2, [r3, #8]
- 8003458:	60da      	str	r2, [r3, #12]
- 800345a:	611a      	str	r2, [r3, #16]
+ 8004110:	f107 0314 	add.w	r3, r7, #20
+ 8004114:	2200      	movs	r2, #0
+ 8004116:	601a      	str	r2, [r3, #0]
+ 8004118:	605a      	str	r2, [r3, #4]
+ 800411a:	609a      	str	r2, [r3, #8]
+ 800411c:	60da      	str	r2, [r3, #12]
+ 800411e:	611a      	str	r2, [r3, #16]
   if(huart->Instance==USART3)
- 800345c:	687b      	ldr	r3, [r7, #4]
- 800345e:	681b      	ldr	r3, [r3, #0]
- 8003460:	4a4b      	ldr	r2, [pc, #300]	; (8003590 <HAL_UART_MspInit+0x14c>)
- 8003462:	4293      	cmp	r3, r2
- 8003464:	f040 808f 	bne.w	8003586 <HAL_UART_MspInit+0x142>
+ 8004120:	687b      	ldr	r3, [r7, #4]
+ 8004122:	681b      	ldr	r3, [r3, #0]
+ 8004124:	4a4b      	ldr	r2, [pc, #300]	; (8004254 <HAL_UART_MspInit+0x14c>)
+ 8004126:	4293      	cmp	r3, r2
+ 8004128:	f040 808f 	bne.w	800424a <HAL_UART_MspInit+0x142>
   {
   /* USER CODE BEGIN USART3_MspInit 0 */
 
   /* USER CODE END USART3_MspInit 0 */
     /* Peripheral clock enable */
     __HAL_RCC_USART3_CLK_ENABLE();
- 8003468:	4b4a      	ldr	r3, [pc, #296]	; (8003594 <HAL_UART_MspInit+0x150>)
- 800346a:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 800346c:	4a49      	ldr	r2, [pc, #292]	; (8003594 <HAL_UART_MspInit+0x150>)
- 800346e:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
- 8003472:	6413      	str	r3, [r2, #64]	; 0x40
- 8003474:	4b47      	ldr	r3, [pc, #284]	; (8003594 <HAL_UART_MspInit+0x150>)
- 8003476:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 8003478:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
- 800347c:	613b      	str	r3, [r7, #16]
- 800347e:	693b      	ldr	r3, [r7, #16]
+ 800412c:	4b4a      	ldr	r3, [pc, #296]	; (8004258 <HAL_UART_MspInit+0x150>)
+ 800412e:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 8004130:	4a49      	ldr	r2, [pc, #292]	; (8004258 <HAL_UART_MspInit+0x150>)
+ 8004132:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
+ 8004136:	6413      	str	r3, [r2, #64]	; 0x40
+ 8004138:	4b47      	ldr	r3, [pc, #284]	; (8004258 <HAL_UART_MspInit+0x150>)
+ 800413a:	6c1b      	ldr	r3, [r3, #64]	; 0x40
+ 800413c:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
+ 8004140:	613b      	str	r3, [r7, #16]
+ 8004142:	693b      	ldr	r3, [r7, #16]
   
     __HAL_RCC_GPIOD_CLK_ENABLE();
- 8003480:	4b44      	ldr	r3, [pc, #272]	; (8003594 <HAL_UART_MspInit+0x150>)
- 8003482:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8003484:	4a43      	ldr	r2, [pc, #268]	; (8003594 <HAL_UART_MspInit+0x150>)
- 8003486:	f043 0308 	orr.w	r3, r3, #8
- 800348a:	6313      	str	r3, [r2, #48]	; 0x30
- 800348c:	4b41      	ldr	r3, [pc, #260]	; (8003594 <HAL_UART_MspInit+0x150>)
- 800348e:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8003490:	f003 0308 	and.w	r3, r3, #8
- 8003494:	60fb      	str	r3, [r7, #12]
- 8003496:	68fb      	ldr	r3, [r7, #12]
+ 8004144:	4b44      	ldr	r3, [pc, #272]	; (8004258 <HAL_UART_MspInit+0x150>)
+ 8004146:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8004148:	4a43      	ldr	r2, [pc, #268]	; (8004258 <HAL_UART_MspInit+0x150>)
+ 800414a:	f043 0308 	orr.w	r3, r3, #8
+ 800414e:	6313      	str	r3, [r2, #48]	; 0x30
+ 8004150:	4b41      	ldr	r3, [pc, #260]	; (8004258 <HAL_UART_MspInit+0x150>)
+ 8004152:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 8004154:	f003 0308 	and.w	r3, r3, #8
+ 8004158:	60fb      	str	r3, [r7, #12]
+ 800415a:	68fb      	ldr	r3, [r7, #12]
     /**USART3 GPIO Configuration    
     PD8     ------> USART3_TX
     PD9     ------> USART3_RX 
     */
     GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
- 8003498:	f44f 7340 	mov.w	r3, #768	; 0x300
- 800349c:	617b      	str	r3, [r7, #20]
+ 800415c:	f44f 7340 	mov.w	r3, #768	; 0x300
+ 8004160:	617b      	str	r3, [r7, #20]
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 800349e:	2302      	movs	r3, #2
- 80034a0:	61bb      	str	r3, [r7, #24]
+ 8004162:	2302      	movs	r3, #2
+ 8004164:	61bb      	str	r3, [r7, #24]
     GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80034a2:	2300      	movs	r3, #0
- 80034a4:	61fb      	str	r3, [r7, #28]
+ 8004166:	2300      	movs	r3, #0
+ 8004168:	61fb      	str	r3, [r7, #28]
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- 80034a6:	2303      	movs	r3, #3
- 80034a8:	623b      	str	r3, [r7, #32]
+ 800416a:	2303      	movs	r3, #3
+ 800416c:	623b      	str	r3, [r7, #32]
     GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
- 80034aa:	2307      	movs	r3, #7
- 80034ac:	627b      	str	r3, [r7, #36]	; 0x24
+ 800416e:	2307      	movs	r3, #7
+ 8004170:	627b      	str	r3, [r7, #36]	; 0x24
     HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
- 80034ae:	f107 0314 	add.w	r3, r7, #20
- 80034b2:	4619      	mov	r1, r3
- 80034b4:	4838      	ldr	r0, [pc, #224]	; (8003598 <HAL_UART_MspInit+0x154>)
- 80034b6:	f7fd fcb9 	bl	8000e2c <HAL_GPIO_Init>
+ 8004172:	f107 0314 	add.w	r3, r7, #20
+ 8004176:	4619      	mov	r1, r3
+ 8004178:	4838      	ldr	r0, [pc, #224]	; (800425c <HAL_UART_MspInit+0x154>)
+ 800417a:	f7fc fe57 	bl	8000e2c <HAL_GPIO_Init>
 
     /* USART3 DMA Init */
     /* USART3_RX Init */
     hdma_usart3_rx.Instance = DMA1_Stream1;
- 80034ba:	4b38      	ldr	r3, [pc, #224]	; (800359c <HAL_UART_MspInit+0x158>)
- 80034bc:	4a38      	ldr	r2, [pc, #224]	; (80035a0 <HAL_UART_MspInit+0x15c>)
- 80034be:	601a      	str	r2, [r3, #0]
+ 800417e:	4b38      	ldr	r3, [pc, #224]	; (8004260 <HAL_UART_MspInit+0x158>)
+ 8004180:	4a38      	ldr	r2, [pc, #224]	; (8004264 <HAL_UART_MspInit+0x15c>)
+ 8004182:	601a      	str	r2, [r3, #0]
     hdma_usart3_rx.Init.Channel = DMA_CHANNEL_4;
- 80034c0:	4b36      	ldr	r3, [pc, #216]	; (800359c <HAL_UART_MspInit+0x158>)
- 80034c2:	f04f 6200 	mov.w	r2, #134217728	; 0x8000000
- 80034c6:	605a      	str	r2, [r3, #4]
+ 8004184:	4b36      	ldr	r3, [pc, #216]	; (8004260 <HAL_UART_MspInit+0x158>)
+ 8004186:	f04f 6200 	mov.w	r2, #134217728	; 0x8000000
+ 800418a:	605a      	str	r2, [r3, #4]
     hdma_usart3_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
- 80034c8:	4b34      	ldr	r3, [pc, #208]	; (800359c <HAL_UART_MspInit+0x158>)
- 80034ca:	2200      	movs	r2, #0
- 80034cc:	609a      	str	r2, [r3, #8]
+ 800418c:	4b34      	ldr	r3, [pc, #208]	; (8004260 <HAL_UART_MspInit+0x158>)
+ 800418e:	2200      	movs	r2, #0
+ 8004190:	609a      	str	r2, [r3, #8]
     hdma_usart3_rx.Init.PeriphInc = DMA_PINC_DISABLE;
- 80034ce:	4b33      	ldr	r3, [pc, #204]	; (800359c <HAL_UART_MspInit+0x158>)
- 80034d0:	2200      	movs	r2, #0
- 80034d2:	60da      	str	r2, [r3, #12]
+ 8004192:	4b33      	ldr	r3, [pc, #204]	; (8004260 <HAL_UART_MspInit+0x158>)
+ 8004194:	2200      	movs	r2, #0
+ 8004196:	60da      	str	r2, [r3, #12]
     hdma_usart3_rx.Init.MemInc = DMA_MINC_ENABLE;
- 80034d4:	4b31      	ldr	r3, [pc, #196]	; (800359c <HAL_UART_MspInit+0x158>)
- 80034d6:	f44f 6280 	mov.w	r2, #1024	; 0x400
- 80034da:	611a      	str	r2, [r3, #16]
+ 8004198:	4b31      	ldr	r3, [pc, #196]	; (8004260 <HAL_UART_MspInit+0x158>)
+ 800419a:	f44f 6280 	mov.w	r2, #1024	; 0x400
+ 800419e:	611a      	str	r2, [r3, #16]
     hdma_usart3_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
- 80034dc:	4b2f      	ldr	r3, [pc, #188]	; (800359c <HAL_UART_MspInit+0x158>)
- 80034de:	2200      	movs	r2, #0
- 80034e0:	615a      	str	r2, [r3, #20]
+ 80041a0:	4b2f      	ldr	r3, [pc, #188]	; (8004260 <HAL_UART_MspInit+0x158>)
+ 80041a2:	2200      	movs	r2, #0
+ 80041a4:	615a      	str	r2, [r3, #20]
     hdma_usart3_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
- 80034e2:	4b2e      	ldr	r3, [pc, #184]	; (800359c <HAL_UART_MspInit+0x158>)
- 80034e4:	2200      	movs	r2, #0
- 80034e6:	619a      	str	r2, [r3, #24]
+ 80041a6:	4b2e      	ldr	r3, [pc, #184]	; (8004260 <HAL_UART_MspInit+0x158>)
+ 80041a8:	2200      	movs	r2, #0
+ 80041aa:	619a      	str	r2, [r3, #24]
     hdma_usart3_rx.Init.Mode = DMA_NORMAL;
- 80034e8:	4b2c      	ldr	r3, [pc, #176]	; (800359c <HAL_UART_MspInit+0x158>)
- 80034ea:	2200      	movs	r2, #0
- 80034ec:	61da      	str	r2, [r3, #28]
+ 80041ac:	4b2c      	ldr	r3, [pc, #176]	; (8004260 <HAL_UART_MspInit+0x158>)
+ 80041ae:	2200      	movs	r2, #0
+ 80041b0:	61da      	str	r2, [r3, #28]
     hdma_usart3_rx.Init.Priority = DMA_PRIORITY_HIGH;
- 80034ee:	4b2b      	ldr	r3, [pc, #172]	; (800359c <HAL_UART_MspInit+0x158>)
- 80034f0:	f44f 3200 	mov.w	r2, #131072	; 0x20000
- 80034f4:	621a      	str	r2, [r3, #32]
+ 80041b2:	4b2b      	ldr	r3, [pc, #172]	; (8004260 <HAL_UART_MspInit+0x158>)
+ 80041b4:	f44f 3200 	mov.w	r2, #131072	; 0x20000
+ 80041b8:	621a      	str	r2, [r3, #32]
     hdma_usart3_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
- 80034f6:	4b29      	ldr	r3, [pc, #164]	; (800359c <HAL_UART_MspInit+0x158>)
- 80034f8:	2200      	movs	r2, #0
- 80034fa:	625a      	str	r2, [r3, #36]	; 0x24
+ 80041ba:	4b29      	ldr	r3, [pc, #164]	; (8004260 <HAL_UART_MspInit+0x158>)
+ 80041bc:	2200      	movs	r2, #0
+ 80041be:	625a      	str	r2, [r3, #36]	; 0x24
     if (HAL_DMA_Init(&hdma_usart3_rx) != HAL_OK)
- 80034fc:	4827      	ldr	r0, [pc, #156]	; (800359c <HAL_UART_MspInit+0x158>)
- 80034fe:	f7fd f98b 	bl	8000818 <HAL_DMA_Init>
- 8003502:	4603      	mov	r3, r0
- 8003504:	2b00      	cmp	r3, #0
- 8003506:	d001      	beq.n	800350c <HAL_UART_MspInit+0xc8>
+ 80041c0:	4827      	ldr	r0, [pc, #156]	; (8004260 <HAL_UART_MspInit+0x158>)
+ 80041c2:	f7fc fb29 	bl	8000818 <HAL_DMA_Init>
+ 80041c6:	4603      	mov	r3, r0
+ 80041c8:	2b00      	cmp	r3, #0
+ 80041ca:	d001      	beq.n	80041d0 <HAL_UART_MspInit+0xc8>
     {
       Error_Handler();
- 8003508:	f7ff ff2e 	bl	8003368 <Error_Handler>
+ 80041cc:	f7ff fe88 	bl	8003ee0 <Error_Handler>
     }
 
     __HAL_LINKDMA(huart,hdmarx,hdma_usart3_rx);
- 800350c:	687b      	ldr	r3, [r7, #4]
- 800350e:	4a23      	ldr	r2, [pc, #140]	; (800359c <HAL_UART_MspInit+0x158>)
- 8003510:	66da      	str	r2, [r3, #108]	; 0x6c
- 8003512:	4a22      	ldr	r2, [pc, #136]	; (800359c <HAL_UART_MspInit+0x158>)
- 8003514:	687b      	ldr	r3, [r7, #4]
- 8003516:	6393      	str	r3, [r2, #56]	; 0x38
+ 80041d0:	687b      	ldr	r3, [r7, #4]
+ 80041d2:	4a23      	ldr	r2, [pc, #140]	; (8004260 <HAL_UART_MspInit+0x158>)
+ 80041d4:	66da      	str	r2, [r3, #108]	; 0x6c
+ 80041d6:	4a22      	ldr	r2, [pc, #136]	; (8004260 <HAL_UART_MspInit+0x158>)
+ 80041d8:	687b      	ldr	r3, [r7, #4]
+ 80041da:	6393      	str	r3, [r2, #56]	; 0x38
 
     /* USART3_TX Init */
     hdma_usart3_tx.Instance = DMA1_Stream3;
- 8003518:	4b22      	ldr	r3, [pc, #136]	; (80035a4 <HAL_UART_MspInit+0x160>)
- 800351a:	4a23      	ldr	r2, [pc, #140]	; (80035a8 <HAL_UART_MspInit+0x164>)
- 800351c:	601a      	str	r2, [r3, #0]
+ 80041dc:	4b22      	ldr	r3, [pc, #136]	; (8004268 <HAL_UART_MspInit+0x160>)
+ 80041de:	4a23      	ldr	r2, [pc, #140]	; (800426c <HAL_UART_MspInit+0x164>)
+ 80041e0:	601a      	str	r2, [r3, #0]
     hdma_usart3_tx.Init.Channel = DMA_CHANNEL_4;
- 800351e:	4b21      	ldr	r3, [pc, #132]	; (80035a4 <HAL_UART_MspInit+0x160>)
- 8003520:	f04f 6200 	mov.w	r2, #134217728	; 0x8000000
- 8003524:	605a      	str	r2, [r3, #4]
+ 80041e2:	4b21      	ldr	r3, [pc, #132]	; (8004268 <HAL_UART_MspInit+0x160>)
+ 80041e4:	f04f 6200 	mov.w	r2, #134217728	; 0x8000000
+ 80041e8:	605a      	str	r2, [r3, #4]
     hdma_usart3_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
- 8003526:	4b1f      	ldr	r3, [pc, #124]	; (80035a4 <HAL_UART_MspInit+0x160>)
- 8003528:	2240      	movs	r2, #64	; 0x40
- 800352a:	609a      	str	r2, [r3, #8]
+ 80041ea:	4b1f      	ldr	r3, [pc, #124]	; (8004268 <HAL_UART_MspInit+0x160>)
+ 80041ec:	2240      	movs	r2, #64	; 0x40
+ 80041ee:	609a      	str	r2, [r3, #8]
     hdma_usart3_tx.Init.PeriphInc = DMA_PINC_DISABLE;
- 800352c:	4b1d      	ldr	r3, [pc, #116]	; (80035a4 <HAL_UART_MspInit+0x160>)
- 800352e:	2200      	movs	r2, #0
- 8003530:	60da      	str	r2, [r3, #12]
+ 80041f0:	4b1d      	ldr	r3, [pc, #116]	; (8004268 <HAL_UART_MspInit+0x160>)
+ 80041f2:	2200      	movs	r2, #0
+ 80041f4:	60da      	str	r2, [r3, #12]
     hdma_usart3_tx.Init.MemInc = DMA_MINC_ENABLE;
- 8003532:	4b1c      	ldr	r3, [pc, #112]	; (80035a4 <HAL_UART_MspInit+0x160>)
- 8003534:	f44f 6280 	mov.w	r2, #1024	; 0x400
- 8003538:	611a      	str	r2, [r3, #16]
+ 80041f6:	4b1c      	ldr	r3, [pc, #112]	; (8004268 <HAL_UART_MspInit+0x160>)
+ 80041f8:	f44f 6280 	mov.w	r2, #1024	; 0x400
+ 80041fc:	611a      	str	r2, [r3, #16]
     hdma_usart3_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
- 800353a:	4b1a      	ldr	r3, [pc, #104]	; (80035a4 <HAL_UART_MspInit+0x160>)
- 800353c:	2200      	movs	r2, #0
- 800353e:	615a      	str	r2, [r3, #20]
+ 80041fe:	4b1a      	ldr	r3, [pc, #104]	; (8004268 <HAL_UART_MspInit+0x160>)
+ 8004200:	2200      	movs	r2, #0
+ 8004202:	615a      	str	r2, [r3, #20]
     hdma_usart3_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
- 8003540:	4b18      	ldr	r3, [pc, #96]	; (80035a4 <HAL_UART_MspInit+0x160>)
- 8003542:	2200      	movs	r2, #0
- 8003544:	619a      	str	r2, [r3, #24]
+ 8004204:	4b18      	ldr	r3, [pc, #96]	; (8004268 <HAL_UART_MspInit+0x160>)
+ 8004206:	2200      	movs	r2, #0
+ 8004208:	619a      	str	r2, [r3, #24]
     hdma_usart3_tx.Init.Mode = DMA_NORMAL;
- 8003546:	4b17      	ldr	r3, [pc, #92]	; (80035a4 <HAL_UART_MspInit+0x160>)
- 8003548:	2200      	movs	r2, #0
- 800354a:	61da      	str	r2, [r3, #28]
+ 800420a:	4b17      	ldr	r3, [pc, #92]	; (8004268 <HAL_UART_MspInit+0x160>)
+ 800420c:	2200      	movs	r2, #0
+ 800420e:	61da      	str	r2, [r3, #28]
     hdma_usart3_tx.Init.Priority = DMA_PRIORITY_HIGH;
- 800354c:	4b15      	ldr	r3, [pc, #84]	; (80035a4 <HAL_UART_MspInit+0x160>)
- 800354e:	f44f 3200 	mov.w	r2, #131072	; 0x20000
- 8003552:	621a      	str	r2, [r3, #32]
+ 8004210:	4b15      	ldr	r3, [pc, #84]	; (8004268 <HAL_UART_MspInit+0x160>)
+ 8004212:	f44f 3200 	mov.w	r2, #131072	; 0x20000
+ 8004216:	621a      	str	r2, [r3, #32]
     hdma_usart3_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
- 8003554:	4b13      	ldr	r3, [pc, #76]	; (80035a4 <HAL_UART_MspInit+0x160>)
- 8003556:	2200      	movs	r2, #0
- 8003558:	625a      	str	r2, [r3, #36]	; 0x24
+ 8004218:	4b13      	ldr	r3, [pc, #76]	; (8004268 <HAL_UART_MspInit+0x160>)
+ 800421a:	2200      	movs	r2, #0
+ 800421c:	625a      	str	r2, [r3, #36]	; 0x24
     if (HAL_DMA_Init(&hdma_usart3_tx) != HAL_OK)
- 800355a:	4812      	ldr	r0, [pc, #72]	; (80035a4 <HAL_UART_MspInit+0x160>)
- 800355c:	f7fd f95c 	bl	8000818 <HAL_DMA_Init>
- 8003560:	4603      	mov	r3, r0
- 8003562:	2b00      	cmp	r3, #0
- 8003564:	d001      	beq.n	800356a <HAL_UART_MspInit+0x126>
+ 800421e:	4812      	ldr	r0, [pc, #72]	; (8004268 <HAL_UART_MspInit+0x160>)
+ 8004220:	f7fc fafa 	bl	8000818 <HAL_DMA_Init>
+ 8004224:	4603      	mov	r3, r0
+ 8004226:	2b00      	cmp	r3, #0
+ 8004228:	d001      	beq.n	800422e <HAL_UART_MspInit+0x126>
     {
       Error_Handler();
- 8003566:	f7ff feff 	bl	8003368 <Error_Handler>
+ 800422a:	f7ff fe59 	bl	8003ee0 <Error_Handler>
     }
 
     __HAL_LINKDMA(huart,hdmatx,hdma_usart3_tx);
- 800356a:	687b      	ldr	r3, [r7, #4]
- 800356c:	4a0d      	ldr	r2, [pc, #52]	; (80035a4 <HAL_UART_MspInit+0x160>)
- 800356e:	669a      	str	r2, [r3, #104]	; 0x68
- 8003570:	4a0c      	ldr	r2, [pc, #48]	; (80035a4 <HAL_UART_MspInit+0x160>)
- 8003572:	687b      	ldr	r3, [r7, #4]
- 8003574:	6393      	str	r3, [r2, #56]	; 0x38
+ 800422e:	687b      	ldr	r3, [r7, #4]
+ 8004230:	4a0d      	ldr	r2, [pc, #52]	; (8004268 <HAL_UART_MspInit+0x160>)
+ 8004232:	669a      	str	r2, [r3, #104]	; 0x68
+ 8004234:	4a0c      	ldr	r2, [pc, #48]	; (8004268 <HAL_UART_MspInit+0x160>)
+ 8004236:	687b      	ldr	r3, [r7, #4]
+ 8004238:	6393      	str	r3, [r2, #56]	; 0x38
 
     /* USART3 interrupt Init */
     HAL_NVIC_SetPriority(USART3_IRQn, 0, 0);
- 8003576:	2200      	movs	r2, #0
- 8003578:	2100      	movs	r1, #0
- 800357a:	2027      	movs	r0, #39	; 0x27
- 800357c:	f7fd f915 	bl	80007aa <HAL_NVIC_SetPriority>
+ 800423a:	2200      	movs	r2, #0
+ 800423c:	2100      	movs	r1, #0
+ 800423e:	2027      	movs	r0, #39	; 0x27
+ 8004240:	f7fc fab3 	bl	80007aa <HAL_NVIC_SetPriority>
     HAL_NVIC_EnableIRQ(USART3_IRQn);
- 8003580:	2027      	movs	r0, #39	; 0x27
- 8003582:	f7fd f92e 	bl	80007e2 <HAL_NVIC_EnableIRQ>
+ 8004244:	2027      	movs	r0, #39	; 0x27
+ 8004246:	f7fc facc 	bl	80007e2 <HAL_NVIC_EnableIRQ>
   /* USER CODE BEGIN USART3_MspInit 1 */
 
   /* USER CODE END USART3_MspInit 1 */
   }
 
 }
- 8003586:	bf00      	nop
- 8003588:	3728      	adds	r7, #40	; 0x28
- 800358a:	46bd      	mov	sp, r7
- 800358c:	bd80      	pop	{r7, pc}
- 800358e:	bf00      	nop
- 8003590:	40004800 	.word	0x40004800
- 8003594:	40023800 	.word	0x40023800
- 8003598:	40020c00 	.word	0x40020c00
- 800359c:	200000e8 	.word	0x200000e8
- 80035a0:	40026028 	.word	0x40026028
- 80035a4:	20000148 	.word	0x20000148
- 80035a8:	40026058 	.word	0x40026058
-
-080035ac <NMI_Handler>:
+ 800424a:	bf00      	nop
+ 800424c:	3728      	adds	r7, #40	; 0x28
+ 800424e:	46bd      	mov	sp, r7
+ 8004250:	bd80      	pop	{r7, pc}
+ 8004252:	bf00      	nop
+ 8004254:	40004800 	.word	0x40004800
+ 8004258:	40023800 	.word	0x40023800
+ 800425c:	40020c00 	.word	0x40020c00
+ 8004260:	20000168 	.word	0x20000168
+ 8004264:	40026028 	.word	0x40026028
+ 8004268:	200001c8 	.word	0x200001c8
+ 800426c:	40026058 	.word	0x40026058
+
+08004270 <NMI_Handler>:
 /******************************************************************************/
 /**
   * @brief This function handles Non maskable interrupt.
   */
 void NMI_Handler(void)
 {
- 80035ac:	b480      	push	{r7}
- 80035ae:	af00      	add	r7, sp, #0
+ 8004270:	b480      	push	{r7}
+ 8004272:	af00      	add	r7, sp, #0
 
   /* USER CODE END NonMaskableInt_IRQn 0 */
   /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
 
   /* USER CODE END NonMaskableInt_IRQn 1 */
 }
- 80035b0:	bf00      	nop
- 80035b2:	46bd      	mov	sp, r7
- 80035b4:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80035b8:	4770      	bx	lr
+ 8004274:	bf00      	nop
+ 8004276:	46bd      	mov	sp, r7
+ 8004278:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 800427c:	4770      	bx	lr
 
-080035ba <HardFault_Handler>:
+0800427e <HardFault_Handler>:
 
 /**
   * @brief This function handles Hard fault interrupt.
   */
 void HardFault_Handler(void)
 {
- 80035ba:	b480      	push	{r7}
- 80035bc:	af00      	add	r7, sp, #0
+ 800427e:	b480      	push	{r7}
+ 8004280:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN HardFault_IRQn 0 */
 
   /* USER CODE END HardFault_IRQn 0 */
   while (1)
- 80035be:	e7fe      	b.n	80035be <HardFault_Handler+0x4>
+ 8004282:	e7fe      	b.n	8004282 <HardFault_Handler+0x4>
 
-080035c0 <MemManage_Handler>:
+08004284 <MemManage_Handler>:
 
 /**
   * @brief This function handles Memory management fault.
   */
 void MemManage_Handler(void)
 {
- 80035c0:	b480      	push	{r7}
- 80035c2:	af00      	add	r7, sp, #0
+ 8004284:	b480      	push	{r7}
+ 8004286:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN MemoryManagement_IRQn 0 */
 
   /* USER CODE END MemoryManagement_IRQn 0 */
   while (1)
- 80035c4:	e7fe      	b.n	80035c4 <MemManage_Handler+0x4>
+ 8004288:	e7fe      	b.n	8004288 <MemManage_Handler+0x4>
 
-080035c6 <BusFault_Handler>:
+0800428a <BusFault_Handler>:
 
 /**
   * @brief This function handles Pre-fetch fault, memory access fault.
   */
 void BusFault_Handler(void)
 {
- 80035c6:	b480      	push	{r7}
- 80035c8:	af00      	add	r7, sp, #0
+ 800428a:	b480      	push	{r7}
+ 800428c:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN BusFault_IRQn 0 */
 
   /* USER CODE END BusFault_IRQn 0 */
   while (1)
- 80035ca:	e7fe      	b.n	80035ca <BusFault_Handler+0x4>
+ 800428e:	e7fe      	b.n	800428e <BusFault_Handler+0x4>
 
-080035cc <UsageFault_Handler>:
+08004290 <UsageFault_Handler>:
 
 /**
   * @brief This function handles Undefined instruction or illegal state.
   */
 void UsageFault_Handler(void)
 {
- 80035cc:	b480      	push	{r7}
- 80035ce:	af00      	add	r7, sp, #0
+ 8004290:	b480      	push	{r7}
+ 8004292:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN UsageFault_IRQn 0 */
 
   /* USER CODE END UsageFault_IRQn 0 */
   while (1)
- 80035d0:	e7fe      	b.n	80035d0 <UsageFault_Handler+0x4>
+ 8004294:	e7fe      	b.n	8004294 <UsageFault_Handler+0x4>
 
-080035d2 <SVC_Handler>:
+08004296 <SVC_Handler>:
 
 /**
   * @brief This function handles System service call via SWI instruction.
   */
 void SVC_Handler(void)
 {
- 80035d2:	b480      	push	{r7}
- 80035d4:	af00      	add	r7, sp, #0
+ 8004296:	b480      	push	{r7}
+ 8004298:	af00      	add	r7, sp, #0
 
   /* USER CODE END SVCall_IRQn 0 */
   /* USER CODE BEGIN SVCall_IRQn 1 */
 
   /* USER CODE END SVCall_IRQn 1 */
 }
- 80035d6:	bf00      	nop
- 80035d8:	46bd      	mov	sp, r7
- 80035da:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80035de:	4770      	bx	lr
+ 800429a:	bf00      	nop
+ 800429c:	46bd      	mov	sp, r7
+ 800429e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80042a2:	4770      	bx	lr
 
-080035e0 <DebugMon_Handler>:
+080042a4 <DebugMon_Handler>:
 
 /**
   * @brief This function handles Debug monitor.
   */
 void DebugMon_Handler(void)
 {
- 80035e0:	b480      	push	{r7}
- 80035e2:	af00      	add	r7, sp, #0
+ 80042a4:	b480      	push	{r7}
+ 80042a6:	af00      	add	r7, sp, #0
 
   /* USER CODE END DebugMonitor_IRQn 0 */
   /* USER CODE BEGIN DebugMonitor_IRQn 1 */
 
   /* USER CODE END DebugMonitor_IRQn 1 */
 }
- 80035e4:	bf00      	nop
- 80035e6:	46bd      	mov	sp, r7
- 80035e8:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80035ec:	4770      	bx	lr
+ 80042a8:	bf00      	nop
+ 80042aa:	46bd      	mov	sp, r7
+ 80042ac:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80042b0:	4770      	bx	lr
 
-080035ee <PendSV_Handler>:
+080042b2 <PendSV_Handler>:
 
 /**
   * @brief This function handles Pendable request for system service.
   */
 void PendSV_Handler(void)
 {
- 80035ee:	b480      	push	{r7}
- 80035f0:	af00      	add	r7, sp, #0
+ 80042b2:	b480      	push	{r7}
+ 80042b4:	af00      	add	r7, sp, #0
 
   /* USER CODE END PendSV_IRQn 0 */
   /* USER CODE BEGIN PendSV_IRQn 1 */
 
   /* USER CODE END PendSV_IRQn 1 */
 }
- 80035f2:	bf00      	nop
- 80035f4:	46bd      	mov	sp, r7
- 80035f6:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80035fa:	4770      	bx	lr
+ 80042b6:	bf00      	nop
+ 80042b8:	46bd      	mov	sp, r7
+ 80042ba:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80042be:	4770      	bx	lr
 
-080035fc <SysTick_Handler>:
+080042c0 <SysTick_Handler>:
 
 /**
   * @brief This function handles System tick timer.
   */
 void SysTick_Handler(void)
 {
- 80035fc:	b580      	push	{r7, lr}
- 80035fe:	af00      	add	r7, sp, #0
+ 80042c0:	b580      	push	{r7, lr}
+ 80042c2:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN SysTick_IRQn 0 */
 
   /* USER CODE END SysTick_IRQn 0 */
   HAL_IncTick();
- 8003600:	f7fc ffd8 	bl	80005b4 <HAL_IncTick>
+ 80042c4:	f7fc f976 	bl	80005b4 <HAL_IncTick>
   /* USER CODE BEGIN SysTick_IRQn 1 */
 
   /* USER CODE END SysTick_IRQn 1 */
 }
- 8003604:	bf00      	nop
- 8003606:	bd80      	pop	{r7, pc}
+ 80042c8:	bf00      	nop
+ 80042ca:	bd80      	pop	{r7, pc}
 
-08003608 <DMA1_Stream1_IRQHandler>:
+080042cc <DMA1_Stream1_IRQHandler>:
 
 /**
   * @brief This function handles DMA1 stream1 global interrupt.
   */
 void DMA1_Stream1_IRQHandler(void)
 {
- 8003608:	b580      	push	{r7, lr}
- 800360a:	af00      	add	r7, sp, #0
+ 80042cc:	b580      	push	{r7, lr}
+ 80042ce:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */
 
   /* USER CODE END DMA1_Stream1_IRQn 0 */
   HAL_DMA_IRQHandler(&hdma_usart3_rx);
- 800360c:	4802      	ldr	r0, [pc, #8]	; (8003618 <DMA1_Stream1_IRQHandler+0x10>)
- 800360e:	f7fd f9d3 	bl	80009b8 <HAL_DMA_IRQHandler>
+ 80042d0:	4802      	ldr	r0, [pc, #8]	; (80042dc <DMA1_Stream1_IRQHandler+0x10>)
+ 80042d2:	f7fc fb71 	bl	80009b8 <HAL_DMA_IRQHandler>
   /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */
 
   /* USER CODE END DMA1_Stream1_IRQn 1 */
 }
- 8003612:	bf00      	nop
- 8003614:	bd80      	pop	{r7, pc}
- 8003616:	bf00      	nop
- 8003618:	200000e8 	.word	0x200000e8
+ 80042d6:	bf00      	nop
+ 80042d8:	bd80      	pop	{r7, pc}
+ 80042da:	bf00      	nop
+ 80042dc:	20000168 	.word	0x20000168
 
-0800361c <DMA1_Stream3_IRQHandler>:
+080042e0 <DMA1_Stream3_IRQHandler>:
 
 /**
   * @brief This function handles DMA1 stream3 global interrupt.
   */
 void DMA1_Stream3_IRQHandler(void)
 {
- 800361c:	b580      	push	{r7, lr}
- 800361e:	af00      	add	r7, sp, #0
+ 80042e0:	b580      	push	{r7, lr}
+ 80042e2:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN DMA1_Stream3_IRQn 0 */
 
   /* USER CODE END DMA1_Stream3_IRQn 0 */
   HAL_DMA_IRQHandler(&hdma_usart3_tx);
- 8003620:	4802      	ldr	r0, [pc, #8]	; (800362c <DMA1_Stream3_IRQHandler+0x10>)
- 8003622:	f7fd f9c9 	bl	80009b8 <HAL_DMA_IRQHandler>
+ 80042e4:	4802      	ldr	r0, [pc, #8]	; (80042f0 <DMA1_Stream3_IRQHandler+0x10>)
+ 80042e6:	f7fc fb67 	bl	80009b8 <HAL_DMA_IRQHandler>
   /* USER CODE BEGIN DMA1_Stream3_IRQn 1 */
 
   /* USER CODE END DMA1_Stream3_IRQn 1 */
 }
- 8003626:	bf00      	nop
- 8003628:	bd80      	pop	{r7, pc}
- 800362a:	bf00      	nop
- 800362c:	20000148 	.word	0x20000148
+ 80042ea:	bf00      	nop
+ 80042ec:	bd80      	pop	{r7, pc}
+ 80042ee:	bf00      	nop
+ 80042f0:	200001c8 	.word	0x200001c8
 
-08003630 <USART3_IRQHandler>:
+080042f4 <USART3_IRQHandler>:
 
 /**
   * @brief This function handles USART3 global interrupt.
   */
 void USART3_IRQHandler(void)
 {
- 8003630:	b580      	push	{r7, lr}
- 8003632:	af00      	add	r7, sp, #0
+ 80042f4:	b580      	push	{r7, lr}
+ 80042f6:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN USART3_IRQn 0 */
 
   /* USER CODE END USART3_IRQn 0 */
   HAL_UART_IRQHandler(&huart3);
- 8003634:	4802      	ldr	r0, [pc, #8]	; (8003640 <USART3_IRQHandler+0x10>)
- 8003636:	f7fe ffe5 	bl	8002604 <HAL_UART_IRQHandler>
+ 80042f8:	4802      	ldr	r0, [pc, #8]	; (8004304 <USART3_IRQHandler+0x10>)
+ 80042fa:	f7fe fd9d 	bl	8002e38 <HAL_UART_IRQHandler>
   /* USER CODE BEGIN USART3_IRQn 1 */
 
   /* USER CODE END USART3_IRQn 1 */
 }
- 800363a:	bf00      	nop
- 800363c:	bd80      	pop	{r7, pc}
- 800363e:	bf00      	nop
- 8003640:	20000068 	.word	0x20000068
+ 80042fe:	bf00      	nop
+ 8004300:	bd80      	pop	{r7, pc}
+ 8004302:	bf00      	nop
+ 8004304:	200000e8 	.word	0x200000e8
 
-08003644 <SystemInit>:
+08004308 <SystemInit>:
   *         SystemFrequency variable.
   * @param  None
   * @retval None
   */
 void SystemInit(void)
 {
- 8003644:	b480      	push	{r7}
- 8003646:	af00      	add	r7, sp, #0
+ 8004308:	b480      	push	{r7}
+ 800430a:	af00      	add	r7, sp, #0
   /* FPU settings ------------------------------------------------------------*/
   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
     SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
- 8003648:	4b15      	ldr	r3, [pc, #84]	; (80036a0 <SystemInit+0x5c>)
- 800364a:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 800364e:	4a14      	ldr	r2, [pc, #80]	; (80036a0 <SystemInit+0x5c>)
- 8003650:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
- 8003654:	f8c2 3088 	str.w	r3, [r2, #136]	; 0x88
+ 800430c:	4b15      	ldr	r3, [pc, #84]	; (8004364 <SystemInit+0x5c>)
+ 800430e:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
+ 8004312:	4a14      	ldr	r2, [pc, #80]	; (8004364 <SystemInit+0x5c>)
+ 8004314:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
+ 8004318:	f8c2 3088 	str.w	r3, [r2, #136]	; 0x88
   #endif
   /* Reset the RCC clock configuration to the default reset state ------------*/
   /* Set HSION bit */
   RCC->CR |= (uint32_t)0x00000001;
- 8003658:	4b12      	ldr	r3, [pc, #72]	; (80036a4 <SystemInit+0x60>)
- 800365a:	681b      	ldr	r3, [r3, #0]
- 800365c:	4a11      	ldr	r2, [pc, #68]	; (80036a4 <SystemInit+0x60>)
- 800365e:	f043 0301 	orr.w	r3, r3, #1
- 8003662:	6013      	str	r3, [r2, #0]
+ 800431c:	4b12      	ldr	r3, [pc, #72]	; (8004368 <SystemInit+0x60>)
+ 800431e:	681b      	ldr	r3, [r3, #0]
+ 8004320:	4a11      	ldr	r2, [pc, #68]	; (8004368 <SystemInit+0x60>)
+ 8004322:	f043 0301 	orr.w	r3, r3, #1
+ 8004326:	6013      	str	r3, [r2, #0]
 
   /* Reset CFGR register */
   RCC->CFGR = 0x00000000;
- 8003664:	4b0f      	ldr	r3, [pc, #60]	; (80036a4 <SystemInit+0x60>)
- 8003666:	2200      	movs	r2, #0
- 8003668:	609a      	str	r2, [r3, #8]
+ 8004328:	4b0f      	ldr	r3, [pc, #60]	; (8004368 <SystemInit+0x60>)
+ 800432a:	2200      	movs	r2, #0
+ 800432c:	609a      	str	r2, [r3, #8]
 
   /* Reset HSEON, CSSON and PLLON bits */
   RCC->CR &= (uint32_t)0xFEF6FFFF;
- 800366a:	4b0e      	ldr	r3, [pc, #56]	; (80036a4 <SystemInit+0x60>)
- 800366c:	681a      	ldr	r2, [r3, #0]
- 800366e:	490d      	ldr	r1, [pc, #52]	; (80036a4 <SystemInit+0x60>)
- 8003670:	4b0d      	ldr	r3, [pc, #52]	; (80036a8 <SystemInit+0x64>)
- 8003672:	4013      	ands	r3, r2
- 8003674:	600b      	str	r3, [r1, #0]
+ 800432e:	4b0e      	ldr	r3, [pc, #56]	; (8004368 <SystemInit+0x60>)
+ 8004330:	681a      	ldr	r2, [r3, #0]
+ 8004332:	490d      	ldr	r1, [pc, #52]	; (8004368 <SystemInit+0x60>)
+ 8004334:	4b0d      	ldr	r3, [pc, #52]	; (800436c <SystemInit+0x64>)
+ 8004336:	4013      	ands	r3, r2
+ 8004338:	600b      	str	r3, [r1, #0]
 
   /* Reset PLLCFGR register */
   RCC->PLLCFGR = 0x24003010;
- 8003676:	4b0b      	ldr	r3, [pc, #44]	; (80036a4 <SystemInit+0x60>)
- 8003678:	4a0c      	ldr	r2, [pc, #48]	; (80036ac <SystemInit+0x68>)
- 800367a:	605a      	str	r2, [r3, #4]
+ 800433a:	4b0b      	ldr	r3, [pc, #44]	; (8004368 <SystemInit+0x60>)
+ 800433c:	4a0c      	ldr	r2, [pc, #48]	; (8004370 <SystemInit+0x68>)
+ 800433e:	605a      	str	r2, [r3, #4]
 
   /* Reset HSEBYP bit */
   RCC->CR &= (uint32_t)0xFFFBFFFF;
- 800367c:	4b09      	ldr	r3, [pc, #36]	; (80036a4 <SystemInit+0x60>)
- 800367e:	681b      	ldr	r3, [r3, #0]
- 8003680:	4a08      	ldr	r2, [pc, #32]	; (80036a4 <SystemInit+0x60>)
- 8003682:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
- 8003686:	6013      	str	r3, [r2, #0]
+ 8004340:	4b09      	ldr	r3, [pc, #36]	; (8004368 <SystemInit+0x60>)
+ 8004342:	681b      	ldr	r3, [r3, #0]
+ 8004344:	4a08      	ldr	r2, [pc, #32]	; (8004368 <SystemInit+0x60>)
+ 8004346:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
+ 800434a:	6013      	str	r3, [r2, #0]
 
   /* Disable all interrupts */
   RCC->CIR = 0x00000000;
- 8003688:	4b06      	ldr	r3, [pc, #24]	; (80036a4 <SystemInit+0x60>)
- 800368a:	2200      	movs	r2, #0
- 800368c:	60da      	str	r2, [r3, #12]
+ 800434c:	4b06      	ldr	r3, [pc, #24]	; (8004368 <SystemInit+0x60>)
+ 800434e:	2200      	movs	r2, #0
+ 8004350:	60da      	str	r2, [r3, #12]
 
   /* Configure the Vector Table location add offset address ------------------*/
 #ifdef VECT_TAB_SRAM
   SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
 #else
   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
- 800368e:	4b04      	ldr	r3, [pc, #16]	; (80036a0 <SystemInit+0x5c>)
- 8003690:	f04f 6200 	mov.w	r2, #134217728	; 0x8000000
- 8003694:	609a      	str	r2, [r3, #8]
+ 8004352:	4b04      	ldr	r3, [pc, #16]	; (8004364 <SystemInit+0x5c>)
+ 8004354:	f04f 6200 	mov.w	r2, #134217728	; 0x8000000
+ 8004358:	609a      	str	r2, [r3, #8]
 #endif
 }
- 8003696:	bf00      	nop
- 8003698:	46bd      	mov	sp, r7
- 800369a:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800369e:	4770      	bx	lr
- 80036a0:	e000ed00 	.word	0xe000ed00
- 80036a4:	40023800 	.word	0x40023800
- 80036a8:	fef6ffff 	.word	0xfef6ffff
- 80036ac:	24003010 	.word	0x24003010
+ 800435a:	bf00      	nop
+ 800435c:	46bd      	mov	sp, r7
+ 800435e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8004362:	4770      	bx	lr
+ 8004364:	e000ed00 	.word	0xe000ed00
+ 8004368:	40023800 	.word	0x40023800
+ 800436c:	fef6ffff 	.word	0xfef6ffff
+ 8004370:	24003010 	.word	0x24003010
 
-080036b0 <Reset_Handler>:
+08004374 <Reset_Handler>:
 
     .section  .text.Reset_Handler
   .weak  Reset_Handler
   .type  Reset_Handler, %function
 Reset_Handler:  
   ldr   sp, =_estack      /* set stack pointer */
- 80036b0:	f8df d034 	ldr.w	sp, [pc, #52]	; 80036e8 <LoopFillZerobss+0x14>
+ 8004374:	f8df d034 	ldr.w	sp, [pc, #52]	; 80043ac <LoopFillZerobss+0x14>
 
 /* Copy the data segment initializers from flash to SRAM */  
   movs  r1, #0
- 80036b4:	2100      	movs	r1, #0
+ 8004378:	2100      	movs	r1, #0
   b  LoopCopyDataInit
- 80036b6:	e003      	b.n	80036c0 <LoopCopyDataInit>
+ 800437a:	e003      	b.n	8004384 <LoopCopyDataInit>
 
-080036b8 <CopyDataInit>:
+0800437c <CopyDataInit>:
 
 CopyDataInit:
   ldr  r3, =_sidata
- 80036b8:	4b0c      	ldr	r3, [pc, #48]	; (80036ec <LoopFillZerobss+0x18>)
+ 800437c:	4b0c      	ldr	r3, [pc, #48]	; (80043b0 <LoopFillZerobss+0x18>)
   ldr  r3, [r3, r1]
- 80036ba:	585b      	ldr	r3, [r3, r1]
+ 800437e:	585b      	ldr	r3, [r3, r1]
   str  r3, [r0, r1]
- 80036bc:	5043      	str	r3, [r0, r1]
+ 8004380:	5043      	str	r3, [r0, r1]
   adds  r1, r1, #4
- 80036be:	3104      	adds	r1, #4
+ 8004382:	3104      	adds	r1, #4
 
-080036c0 <LoopCopyDataInit>:
+08004384 <LoopCopyDataInit>:
     
 LoopCopyDataInit:
   ldr  r0, =_sdata
- 80036c0:	480b      	ldr	r0, [pc, #44]	; (80036f0 <LoopFillZerobss+0x1c>)
+ 8004384:	480b      	ldr	r0, [pc, #44]	; (80043b4 <LoopFillZerobss+0x1c>)
   ldr  r3, =_edata
- 80036c2:	4b0c      	ldr	r3, [pc, #48]	; (80036f4 <LoopFillZerobss+0x20>)
+ 8004386:	4b0c      	ldr	r3, [pc, #48]	; (80043b8 <LoopFillZerobss+0x20>)
   adds  r2, r0, r1
- 80036c4:	1842      	adds	r2, r0, r1
+ 8004388:	1842      	adds	r2, r0, r1
   cmp  r2, r3
- 80036c6:	429a      	cmp	r2, r3
+ 800438a:	429a      	cmp	r2, r3
   bcc  CopyDataInit
- 80036c8:	d3f6      	bcc.n	80036b8 <CopyDataInit>
+ 800438c:	d3f6      	bcc.n	800437c <CopyDataInit>
   ldr  r2, =_sbss
- 80036ca:	4a0b      	ldr	r2, [pc, #44]	; (80036f8 <LoopFillZerobss+0x24>)
+ 800438e:	4a0b      	ldr	r2, [pc, #44]	; (80043bc <LoopFillZerobss+0x24>)
   b  LoopFillZerobss
- 80036cc:	e002      	b.n	80036d4 <LoopFillZerobss>
+ 8004390:	e002      	b.n	8004398 <LoopFillZerobss>
 
-080036ce <FillZerobss>:
+08004392 <FillZerobss>:
 /* Zero fill the bss segment. */  
 FillZerobss:
   movs  r3, #0
- 80036ce:	2300      	movs	r3, #0
+ 8004392:	2300      	movs	r3, #0
   str  r3, [r2], #4
- 80036d0:	f842 3b04 	str.w	r3, [r2], #4
+ 8004394:	f842 3b04 	str.w	r3, [r2], #4
 
-080036d4 <LoopFillZerobss>:
+08004398 <LoopFillZerobss>:
     
 LoopFillZerobss:
   ldr  r3, = _ebss
- 80036d4:	4b09      	ldr	r3, [pc, #36]	; (80036fc <LoopFillZerobss+0x28>)
+ 8004398:	4b09      	ldr	r3, [pc, #36]	; (80043c0 <LoopFillZerobss+0x28>)
   cmp  r2, r3
- 80036d6:	429a      	cmp	r2, r3
+ 800439a:	429a      	cmp	r2, r3
   bcc  FillZerobss
- 80036d8:	d3f9      	bcc.n	80036ce <FillZerobss>
+ 800439c:	d3f9      	bcc.n	8004392 <FillZerobss>
 
 /* Call the clock system initialization function.*/
   bl  SystemInit   
- 80036da:	f7ff ffb3 	bl	8003644 <SystemInit>
+ 800439e:	f7ff ffb3 	bl	8004308 <SystemInit>
 /* Call static constructors */
     bl __libc_init_array
- 80036de:	f000 f811 	bl	8003704 <__libc_init_array>
+ 80043a2:	f000 f811 	bl	80043c8 <__libc_init_array>
 /* Call the application's entry point.*/
   bl  main
- 80036e2:	f7ff fccb 	bl	800307c <main>
+ 80043a6:	f7ff fab3 	bl	8003910 <main>
   bx  lr    
- 80036e6:	4770      	bx	lr
+ 80043aa:	4770      	bx	lr
   ldr   sp, =_estack      /* set stack pointer */
- 80036e8:	20080000 	.word	0x20080000
+ 80043ac:	20080000 	.word	0x20080000
   ldr  r3, =_sidata
- 80036ec:	080037a4 	.word	0x080037a4
+ 80043b0:	08004468 	.word	0x08004468
   ldr  r0, =_sdata
- 80036f0:	20000000 	.word	0x20000000
+ 80043b4:	20000000 	.word	0x20000000
   ldr  r3, =_edata
- 80036f4:	2000000c 	.word	0x2000000c
+ 80043b8:	2000000c 	.word	0x2000000c
   ldr  r2, =_sbss
- 80036f8:	2000000c 	.word	0x2000000c
+ 80043bc:	2000000c 	.word	0x2000000c
   ldr  r3, = _ebss
- 80036fc:	200001ac 	.word	0x200001ac
+ 80043c0:	2000022c 	.word	0x2000022c
 
-08003700 <ADC_IRQHandler>:
+080043c4 <ADC_IRQHandler>:
  * @retval None       
 */
     .section  .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b  Infinite_Loop
- 8003700:	e7fe      	b.n	8003700 <ADC_IRQHandler>
+ 80043c4:	e7fe      	b.n	80043c4 <ADC_IRQHandler>
 	...
 
-08003704 <__libc_init_array>:
- 8003704:	b570      	push	{r4, r5, r6, lr}
- 8003706:	4e0d      	ldr	r6, [pc, #52]	; (800373c <__libc_init_array+0x38>)
- 8003708:	4c0d      	ldr	r4, [pc, #52]	; (8003740 <__libc_init_array+0x3c>)
- 800370a:	1ba4      	subs	r4, r4, r6
- 800370c:	10a4      	asrs	r4, r4, #2
- 800370e:	2500      	movs	r5, #0
- 8003710:	42a5      	cmp	r5, r4
- 8003712:	d109      	bne.n	8003728 <__libc_init_array+0x24>
- 8003714:	4e0b      	ldr	r6, [pc, #44]	; (8003744 <__libc_init_array+0x40>)
- 8003716:	4c0c      	ldr	r4, [pc, #48]	; (8003748 <__libc_init_array+0x44>)
- 8003718:	f000 f820 	bl	800375c <_init>
- 800371c:	1ba4      	subs	r4, r4, r6
- 800371e:	10a4      	asrs	r4, r4, #2
- 8003720:	2500      	movs	r5, #0
- 8003722:	42a5      	cmp	r5, r4
- 8003724:	d105      	bne.n	8003732 <__libc_init_array+0x2e>
- 8003726:	bd70      	pop	{r4, r5, r6, pc}
- 8003728:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
- 800372c:	4798      	blx	r3
- 800372e:	3501      	adds	r5, #1
- 8003730:	e7ee      	b.n	8003710 <__libc_init_array+0xc>
- 8003732:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
- 8003736:	4798      	blx	r3
- 8003738:	3501      	adds	r5, #1
- 800373a:	e7f2      	b.n	8003722 <__libc_init_array+0x1e>
- 800373c:	0800379c 	.word	0x0800379c
- 8003740:	0800379c 	.word	0x0800379c
- 8003744:	0800379c 	.word	0x0800379c
- 8003748:	080037a0 	.word	0x080037a0
-
-0800374c <memset>:
- 800374c:	4402      	add	r2, r0
- 800374e:	4603      	mov	r3, r0
- 8003750:	4293      	cmp	r3, r2
- 8003752:	d100      	bne.n	8003756 <memset+0xa>
- 8003754:	4770      	bx	lr
- 8003756:	f803 1b01 	strb.w	r1, [r3], #1
- 800375a:	e7f9      	b.n	8003750 <memset+0x4>
-
-0800375c <_init>:
- 800375c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
- 800375e:	bf00      	nop
- 8003760:	bcf8      	pop	{r3, r4, r5, r6, r7}
- 8003762:	bc08      	pop	{r3}
- 8003764:	469e      	mov	lr, r3
- 8003766:	4770      	bx	lr
-
-08003768 <_fini>:
- 8003768:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
- 800376a:	bf00      	nop
- 800376c:	bcf8      	pop	{r3, r4, r5, r6, r7}
- 800376e:	bc08      	pop	{r3}
- 8003770:	469e      	mov	lr, r3
- 8003772:	4770      	bx	lr
+080043c8 <__libc_init_array>:
+ 80043c8:	b570      	push	{r4, r5, r6, lr}
+ 80043ca:	4e0d      	ldr	r6, [pc, #52]	; (8004400 <__libc_init_array+0x38>)
+ 80043cc:	4c0d      	ldr	r4, [pc, #52]	; (8004404 <__libc_init_array+0x3c>)
+ 80043ce:	1ba4      	subs	r4, r4, r6
+ 80043d0:	10a4      	asrs	r4, r4, #2
+ 80043d2:	2500      	movs	r5, #0
+ 80043d4:	42a5      	cmp	r5, r4
+ 80043d6:	d109      	bne.n	80043ec <__libc_init_array+0x24>
+ 80043d8:	4e0b      	ldr	r6, [pc, #44]	; (8004408 <__libc_init_array+0x40>)
+ 80043da:	4c0c      	ldr	r4, [pc, #48]	; (800440c <__libc_init_array+0x44>)
+ 80043dc:	f000 f820 	bl	8004420 <_init>
+ 80043e0:	1ba4      	subs	r4, r4, r6
+ 80043e2:	10a4      	asrs	r4, r4, #2
+ 80043e4:	2500      	movs	r5, #0
+ 80043e6:	42a5      	cmp	r5, r4
+ 80043e8:	d105      	bne.n	80043f6 <__libc_init_array+0x2e>
+ 80043ea:	bd70      	pop	{r4, r5, r6, pc}
+ 80043ec:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
+ 80043f0:	4798      	blx	r3
+ 80043f2:	3501      	adds	r5, #1
+ 80043f4:	e7ee      	b.n	80043d4 <__libc_init_array+0xc>
+ 80043f6:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
+ 80043fa:	4798      	blx	r3
+ 80043fc:	3501      	adds	r5, #1
+ 80043fe:	e7f2      	b.n	80043e6 <__libc_init_array+0x1e>
+ 8004400:	08004460 	.word	0x08004460
+ 8004404:	08004460 	.word	0x08004460
+ 8004408:	08004460 	.word	0x08004460
+ 800440c:	08004464 	.word	0x08004464
+
+08004410 <memset>:
+ 8004410:	4402      	add	r2, r0
+ 8004412:	4603      	mov	r3, r0
+ 8004414:	4293      	cmp	r3, r2
+ 8004416:	d100      	bne.n	800441a <memset+0xa>
+ 8004418:	4770      	bx	lr
+ 800441a:	f803 1b01 	strb.w	r1, [r3], #1
+ 800441e:	e7f9      	b.n	8004414 <memset+0x4>
+
+08004420 <_init>:
+ 8004420:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8004422:	bf00      	nop
+ 8004424:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 8004426:	bc08      	pop	{r3}
+ 8004428:	469e      	mov	lr, r3
+ 800442a:	4770      	bx	lr
+
+0800442c <_fini>:
+ 800442c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 800442e:	bf00      	nop
+ 8004430:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 8004432:	bc08      	pop	{r3}
+ 8004434:	469e      	mov	lr, r3
+ 8004436:	4770      	bx	lr
diff --git a/otto_controller_source/Inc/encoder.h b/otto_controller_source/Inc/encoder.h
index 7d79a75..c2095ad 100644
--- a/otto_controller_source/Inc/encoder.h
+++ b/otto_controller_source/Inc/encoder.h
@@ -1,15 +1,21 @@
 #ifndef ENCODER_H
 #define ENCODER_H
 
-#include "stm32f7xx_hal_tim.h"
+#include "main.h"
 
 class Encoder {
  public:
-  TIM_HandleTypeDef timer_;
+  TIM_HandleTypeDef* timer_;
 
-  Encoder(TIM_HandleTypeDef timer);
+  Encoder(TIM_HandleTypeDef* timer);
+
+  int GetCount() {
+    return __HAL_TIM_GET_COUNTER(timer_);
+  }
+
+  void ResetCount() {
+    __HAL_TIM_SET_COUNTER(timer_, 0);
+  }
 
-  int GetCount();
-  void ResetCount();
 };
 #endif
diff --git a/otto_controller_source/Inc/main.h b/otto_controller_source/Inc/main.h
index 0c57f22..e3beadd 100644
--- a/otto_controller_source/Inc/main.h
+++ b/otto_controller_source/Inc/main.h
@@ -50,6 +50,8 @@ extern "C" {
 
 /* USER CODE END EM */
 
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+
 /* Exported functions prototypes ---------------------------------------------*/
 void Error_Handler(void);
 
@@ -58,6 +60,22 @@ void Error_Handler(void);
 /* USER CODE END EFP */
 
 /* Private defines -----------------------------------------------------------*/
+#define current_1_Pin GPIO_PIN_3
+#define current_1_GPIO_Port GPIOA
+#define fault_2_Pin GPIO_PIN_6
+#define fault_2_GPIO_Port GPIOA
+#define dir_1_Pin GPIO_PIN_13
+#define dir_1_GPIO_Port GPIOF
+#define sleep_2_Pin GPIO_PIN_14
+#define sleep_2_GPIO_Port GPIOF
+#define sleep_1_Pin GPIO_PIN_15
+#define sleep_1_GPIO_Port GPIOF
+#define fault_1_Pin GPIO_PIN_9
+#define fault_1_GPIO_Port GPIOE
+#define pwm_2_Pin GPIO_PIN_14
+#define pwm_2_GPIO_Port GPIOD
+#define pwm_1_Pin GPIO_PIN_15
+#define pwm_1_GPIO_Port GPIOD
 /* USER CODE BEGIN Private defines */
 
 /* USER CODE END Private defines */
diff --git a/otto_controller_source/Src/encoder.cpp b/otto_controller_source/Src/encoder.cpp
index 57ae4e9..2e0cfaa 100644
--- a/otto_controller_source/Src/encoder.cpp
+++ b/otto_controller_source/Src/encoder.cpp
@@ -1,13 +1,7 @@
 #include "encoder.h"
 
-Encoder::Encoder(TIM_HandleTypeDef timer){
+Encoder::Encoder(TIM_HandleTypeDef* timer) {
   timer_ = timer;
+  HAL_TIM_Encoder_Start(timer_, TIM_CHANNEL_ALL);
 }
 
-Encoder::GetCount(){
-  return __HAL_TIM_GetCounter(timer_);
-}
-
-Encoder::ResetCount(){
-  __HAL_TIM_SetCounter(timer_, 0);
-}
diff --git a/otto_controller_source/Src/main.cpp b/otto_controller_source/Src/main.cpp
index db249b3..51ce337 100644
--- a/otto_controller_source/Src/main.cpp
+++ b/otto_controller_source/Src/main.cpp
@@ -23,7 +23,7 @@
 
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
-
+#include "encoder.h"
 /* USER CODE END Includes */
 
 /* Private typedef -----------------------------------------------------------*/
@@ -44,6 +44,8 @@
 /* Private variables ---------------------------------------------------------*/
 
 TIM_HandleTypeDef htim2;
+TIM_HandleTypeDef htim4;
+TIM_HandleTypeDef htim5;
 
 UART_HandleTypeDef huart3;
 DMA_HandleTypeDef hdma_usart3_rx;
@@ -58,6 +60,8 @@ void SystemClock_Config(void);
 static void MX_GPIO_Init(void);
 static void MX_DMA_Init(void);
 static void MX_TIM2_Init(void);
+static void MX_TIM4_Init(void);
+static void MX_TIM5_Init(void);
 static void MX_USART3_UART_Init(void);
 /* USER CODE BEGIN PFP */
 
@@ -99,14 +103,19 @@ int main(void)
   MX_GPIO_Init();
   MX_DMA_Init();
   MX_TIM2_Init();
+  MX_TIM4_Init();
+  MX_TIM5_Init();
   MX_USART3_UART_Init();
   /* USER CODE BEGIN 2 */
-
+  Encoder encoder_left = Encoder(&htim2);
+  uint32_t count_left = 0;
   /* USER CODE END 2 */
 
   /* Infinite loop */
   /* USER CODE BEGIN WHILE */
   while (1) {
+    count_left = encoder_left.GetCount();
+    encoder_left.ResetCount();
     /* USER CODE END WHILE */
 
     /* USER CODE BEGIN 3 */
@@ -180,7 +189,7 @@ static void MX_TIM2_Init(void)
   htim2.Instance = TIM2;
   htim2.Init.Prescaler = 0;
   htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
-  htim2.Init.Period = 0;
+  htim2.Init.Period = 4294967295;
   htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
   htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
   sConfig.EncoderMode = TIM_ENCODERMODE_TI1;
@@ -208,6 +217,108 @@ static void MX_TIM2_Init(void)
 
 }
 
+/**
+  * @brief TIM4 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM4_Init(void)
+{
+
+  /* USER CODE BEGIN TIM4_Init 0 */
+
+  /* USER CODE END TIM4_Init 0 */
+
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+  TIM_OC_InitTypeDef sConfigOC = {0};
+
+  /* USER CODE BEGIN TIM4_Init 1 */
+
+  /* USER CODE END TIM4_Init 1 */
+  htim4.Instance = TIM4;
+  htim4.Init.Prescaler = 0;
+  htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim4.Init.Period = 0;
+  htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_PWM_Init(&htim4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigOC.OCMode = TIM_OCMODE_PWM1;
+  sConfigOC.Pulse = 0;
+  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
+  if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM4_Init 2 */
+
+  /* USER CODE END TIM4_Init 2 */
+  HAL_TIM_MspPostInit(&htim4);
+
+}
+
+/**
+  * @brief TIM5 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM5_Init(void)
+{
+
+  /* USER CODE BEGIN TIM5_Init 0 */
+
+  /* USER CODE END TIM5_Init 0 */
+
+  TIM_Encoder_InitTypeDef sConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM5_Init 1 */
+
+  /* USER CODE END TIM5_Init 1 */
+  htim5.Instance = TIM5;
+  htim5.Init.Prescaler = 0;
+  htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim5.Init.Period = 0;
+  htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  sConfig.EncoderMode = TIM_ENCODERMODE_TI1;
+  sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
+  sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
+  sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
+  sConfig.IC1Filter = 0;
+  sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
+  sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
+  sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
+  sConfig.IC2Filter = 0;
+  if (HAL_TIM_Encoder_Init(&htim5, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM5_Init 2 */
+
+  /* USER CODE END TIM5_Init 2 */
+
+}
+
 /**
   * @brief USART3 Initialization Function
   * @param None
@@ -269,10 +380,49 @@ static void MX_DMA_Init(void)
   */
 static void MX_GPIO_Init(void)
 {
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
 
   /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOC_CLK_ENABLE();
   __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
   __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOF, GPIO_PIN_12|dir_1_Pin|sleep_2_Pin|sleep_1_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin : PC0 */
+  GPIO_InitStruct.Pin = GPIO_PIN_0;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : current_1_Pin */
+  GPIO_InitStruct.Pin = current_1_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(current_1_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : fault_2_Pin */
+  GPIO_InitStruct.Pin = fault_2_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(fault_2_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PF12 dir_1_Pin sleep_2_Pin sleep_1_Pin */
+  GPIO_InitStruct.Pin = GPIO_PIN_12|dir_1_Pin|sleep_2_Pin|sleep_1_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : fault_1_Pin */
+  GPIO_InitStruct.Pin = fault_1_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(fault_1_GPIO_Port, &GPIO_InitStruct);
 
 }
 
diff --git a/otto_controller_source/Src/stm32f7xx_hal_msp.c b/otto_controller_source/Src/stm32f7xx_hal_msp.c
index 47501e8..404ec0c 100644
--- a/otto_controller_source/Src/stm32f7xx_hal_msp.c
+++ b/otto_controller_source/Src/stm32f7xx_hal_msp.c
@@ -61,7 +61,9 @@ extern DMA_HandleTypeDef hdma_usart3_tx;
 /* USER CODE BEGIN 0 */
 
 /* USER CODE END 0 */
-/**
+                        
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+                    /**
   * Initializes the Global MSP.
   */
 void HAL_MspInit(void)
@@ -98,24 +100,105 @@ void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
     __HAL_RCC_TIM2_CLK_ENABLE();
   
     __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
     /**TIM2 GPIO Configuration    
-    PA0/WKUP     ------> TIM2_CH1
-    PA1     ------> TIM2_CH2 
+    PA5     ------> TIM2_CH1
+    PB3     ------> TIM2_CH2 
     */
-    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
+    GPIO_InitStruct.Pin = GPIO_PIN_5;
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
     GPIO_InitStruct.Pull = GPIO_NOPULL;
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
     GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
+    GPIO_InitStruct.Pin = GPIO_PIN_3;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
   /* USER CODE BEGIN TIM2_MspInit 1 */
 
   /* USER CODE END TIM2_MspInit 1 */
   }
+  else if(htim_encoder->Instance==TIM5)
+  {
+  /* USER CODE BEGIN TIM5_MspInit 0 */
+
+  /* USER CODE END TIM5_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM5_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**TIM5 GPIO Configuration    
+    PA0/WKUP     ------> TIM5_CH1
+    PA1     ------> TIM5_CH2 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF2_TIM5;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN TIM5_MspInit 1 */
+
+  /* USER CODE END TIM5_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief TIM_PWM MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_pwm: TIM_PWM handle pointer
+* @retval None
+*/
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
+{
+  if(htim_pwm->Instance==TIM4)
+  {
+  /* USER CODE BEGIN TIM4_MspInit 0 */
+
+  /* USER CODE END TIM4_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM4_CLK_ENABLE();
+  /* USER CODE BEGIN TIM4_MspInit 1 */
+
+  /* USER CODE END TIM4_MspInit 1 */
+  }
 
 }
 
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(htim->Instance==TIM4)
+  {
+  /* USER CODE BEGIN TIM4_MspPostInit 0 */
+
+  /* USER CODE END TIM4_MspPostInit 0 */
+  
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    /**TIM4 GPIO Configuration    
+    PD14     ------> TIM4_CH3
+    PD15     ------> TIM4_CH4 
+    */
+    GPIO_InitStruct.Pin = pwm_2_Pin|pwm_1_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN TIM4_MspPostInit 1 */
+
+  /* USER CODE END TIM4_MspPostInit 1 */
+  }
+
+}
 /**
 * @brief TIM_Encoder MSP De-Initialization
 * This function freeze the hardware resources used in this example
@@ -133,15 +216,57 @@ void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef* htim_encoder)
     __HAL_RCC_TIM2_CLK_DISABLE();
   
     /**TIM2 GPIO Configuration    
-    PA0/WKUP     ------> TIM2_CH1
-    PA1     ------> TIM2_CH2 
+    PA5     ------> TIM2_CH1
+    PB3     ------> TIM2_CH2 
     */
-    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_1);
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5);
+
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3);
 
   /* USER CODE BEGIN TIM2_MspDeInit 1 */
 
   /* USER CODE END TIM2_MspDeInit 1 */
   }
+  else if(htim_encoder->Instance==TIM5)
+  {
+  /* USER CODE BEGIN TIM5_MspDeInit 0 */
+
+  /* USER CODE END TIM5_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM5_CLK_DISABLE();
+  
+    /**TIM5 GPIO Configuration    
+    PA0/WKUP     ------> TIM5_CH1
+    PA1     ------> TIM5_CH2 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_1);
+
+  /* USER CODE BEGIN TIM5_MspDeInit 1 */
+
+  /* USER CODE END TIM5_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief TIM_PWM MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_pwm: TIM_PWM handle pointer
+* @retval None
+*/
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm)
+{
+  if(htim_pwm->Instance==TIM4)
+  {
+  /* USER CODE BEGIN TIM4_MspDeInit 0 */
+
+  /* USER CODE END TIM4_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM4_CLK_DISABLE();
+  /* USER CODE BEGIN TIM4_MspDeInit 1 */
+
+  /* USER CODE END TIM4_MspDeInit 1 */
+  }
 
 }
 
diff --git a/otto_controller_source/otto_controller_source.elf.launch b/otto_controller_source/otto_controller_source.elf.launch
new file mode 100644
index 0000000..1e59c9c
--- /dev/null
+++ b/otto_controller_source/otto_controller_source.elf.launch
@@ -0,0 +1,63 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.st.stm32cube.ide.mcu.debug.launch.launchConfigurationType">
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_live_expr" value="true"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_swv" value="false"/>
+<intAttribute key="com.st.stm32cube.ide.mcu.debug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.remoteCommand" value="target remote"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startServer" value="true"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_trace_hclk" value="16000000"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.useRemoteTarget" value="true"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.verify_flash_download" value="true"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_external_loader" value="false"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_logging" value="false"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_shared_stlink" value="false"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.external_loader" value=""/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.log_file" value="/home/fdila/Projects/otto/otto_controller_source/Debug/st-link_gdbserver_log.txt"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_ap_id" value="0"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_check_serial_number" value="false"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_txt_serial_number" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="ST-LINK (ST-LINK GDB server)"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="61234"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-none-eabi-gdb"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="true"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/otto_controller_source.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="otto_controller_source"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/otto_controller_source"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/otto_controller_source/otto_controller_source.ioc b/otto_controller_source/otto_controller_source.ioc
index dd5b068..84d466b 100644
--- a/otto_controller_source/otto_controller_source.ioc
+++ b/otto_controller_source/otto_controller_source.ioc
@@ -31,16 +31,30 @@ Mcu.IP2=NVIC
 Mcu.IP3=RCC
 Mcu.IP4=SYS
 Mcu.IP5=TIM2
-Mcu.IP6=USART3
-Mcu.IPNb=7
+Mcu.IP6=TIM4
+Mcu.IP7=TIM5
+Mcu.IP8=USART3
+Mcu.IPNb=9
 Mcu.Name=STM32F767ZITx
 Mcu.Package=LQFP144
-Mcu.Pin0=PA0/WKUP
-Mcu.Pin1=PA1
-Mcu.Pin2=PD8
-Mcu.Pin3=PD9
-Mcu.Pin4=VP_SYS_VS_Systick
-Mcu.PinsNb=5
+Mcu.Pin0=PC0
+Mcu.Pin1=PA0/WKUP
+Mcu.Pin10=PE9
+Mcu.Pin11=PD8
+Mcu.Pin12=PD9
+Mcu.Pin13=PD14
+Mcu.Pin14=PD15
+Mcu.Pin15=PB3
+Mcu.Pin16=VP_SYS_VS_Systick
+Mcu.Pin2=PA1
+Mcu.Pin3=PA3
+Mcu.Pin4=PA5
+Mcu.Pin5=PA6
+Mcu.Pin6=PF12
+Mcu.Pin7=PF13
+Mcu.Pin8=PF14
+Mcu.Pin9=PF15
+Mcu.PinsNb=17
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32F767ZITx
@@ -59,8 +73,24 @@ NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
 NVIC.USART3_IRQn=true\:0\:0\:false\:false\:true\:true\:true
 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-PA0/WKUP.Signal=S_TIM2_CH1_ETR
-PA1.Signal=S_TIM2_CH2
+PA0/WKUP.Signal=S_TIM5_CH1
+PA1.Signal=S_TIM5_CH2
+PA3.GPIOParameters=GPIO_Label
+PA3.GPIO_Label=current_1
+PA3.Locked=true
+PA3.Signal=GPIO_Analog
+PA5.GPIOParameters=GPIO_PuPd
+PA5.GPIO_PuPd=GPIO_NOPULL
+PA5.Signal=S_TIM2_CH1_ETR
+PA6.GPIOParameters=GPIO_Label
+PA6.GPIO_Label=fault_2
+PA6.Locked=true
+PA6.Signal=GPIO_Input
+PB3.GPIOParameters=GPIO_PuPd
+PB3.GPIO_PuPd=GPIO_NOPULL
+PB3.Signal=S_TIM2_CH2
+PC0.Locked=true
+PC0.Signal=GPIO_Analog
 PCC.Checker=false
 PCC.Line=STM32F7x7
 PCC.MCU=STM32F767ZITx
@@ -69,12 +99,38 @@ PCC.Seq0=0
 PCC.Series=STM32F7
 PCC.Temperature=25
 PCC.Vdd=3.3
+PD14.GPIOParameters=GPIO_Label
+PD14.GPIO_Label=pwm_2
+PD14.Locked=true
+PD14.Signal=S_TIM4_CH3
+PD15.GPIOParameters=GPIO_Label
+PD15.GPIO_Label=pwm_1
+PD15.Locked=true
+PD15.Signal=S_TIM4_CH4
 PD8.Locked=true
 PD8.Mode=Asynchronous
 PD8.Signal=USART3_TX
 PD9.Locked=true
 PD9.Mode=Asynchronous
 PD9.Signal=USART3_RX
+PE9.GPIOParameters=GPIO_Label
+PE9.GPIO_Label=fault_1
+PE9.Locked=true
+PE9.Signal=GPIO_Input
+PF12.Locked=true
+PF12.Signal=GPIO_Output
+PF13.GPIOParameters=GPIO_Label
+PF13.GPIO_Label=dir_1
+PF13.Locked=true
+PF13.Signal=GPIO_Output
+PF14.GPIOParameters=GPIO_Label
+PF14.GPIO_Label=sleep_2
+PF14.Locked=true
+PF14.Signal=GPIO_Output
+PF15.GPIOParameters=GPIO_Label
+PF15.GPIO_Label=sleep_1
+PF15.Locked=true
+PF15.Signal=GPIO_Output
 PinOutPanel.RotationAngle=0
 ProjectManager.AskForMigrate=true
 ProjectManager.BackupPrevious=false
@@ -137,6 +193,19 @@ SH.S_TIM2_CH1_ETR.0=TIM2_CH1,Encoder_Interface
 SH.S_TIM2_CH1_ETR.ConfNb=1
 SH.S_TIM2_CH2.0=TIM2_CH2,Encoder_Interface
 SH.S_TIM2_CH2.ConfNb=1
+SH.S_TIM4_CH3.0=TIM4_CH3,PWM Generation3 CH3
+SH.S_TIM4_CH3.ConfNb=1
+SH.S_TIM4_CH4.0=TIM4_CH4,PWM Generation4 CH4
+SH.S_TIM4_CH4.ConfNb=1
+SH.S_TIM5_CH1.0=TIM5_CH1,Encoder_Interface
+SH.S_TIM5_CH1.ConfNb=1
+SH.S_TIM5_CH2.0=TIM5_CH2,Encoder_Interface
+SH.S_TIM5_CH2.ConfNb=1
+TIM2.IPParameters=Period
+TIM2.Period=4294967295
+TIM4.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
+TIM4.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4
+TIM4.IPParameters=Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4
 USART3.IPParameters=VirtualMode-Asynchronous
 USART3.VirtualMode-Asynchronous=VM_ASYNC
 VP_SYS_VS_Systick.Mode=SysTick
-- 
2.52.0