From 6182d58b07c4e125bcaebd43d5c470fcaca3929b Mon Sep 17 00:00:00 2001 From: Federica Di Lauro Date: Wed, 29 Jan 2020 09:16:45 +0100 Subject: [PATCH] fix pid_tuning --- otto_controller/.mxproject | 2 - .../Core/Inc/communication_utils.h | 5 + otto_controller/Core/Inc/constants.h | 4 +- otto_controller/Core/Inc/encoder.h | 4 +- otto_controller/Core/Src/encoder.cpp | 30 +- otto_controller/Core/Src/main.cpp | 241 +- otto_controller/otto_controller.ioc | 2 +- utils/.project | 11 + utils/README.md | 6 + .../scripts/cmd_vel_transmitter.py | 2 +- .../joypad_bridge/scripts/velocities_pb2.py | 76 + .../joypad_bridge/scripts/velocities_pb2.pyc | Bin 0 -> 2459 bytes utils/pid_tuning/otto_pid_tuning/.mxproject | 2 - .../Core/Inc/communication_utils.h | 7 +- .../otto_pid_tuning/Core/Inc/constants.h | 4 - .../otto_pid_tuning/Core/Inc/encoder.h | 8 +- .../otto_pid_tuning/Core/Inc/odometry.h | 2 +- .../otto_pid_tuning/Core/Src/encoder.cpp | 25 +- .../otto_pid_tuning/Core/Src/main.cpp | 221 +- .../otto_pid_tuning/Debug/Core/Src/subdir.mk | 53 + .../Debug/Core/Startup/subdir.mk | 16 + .../STM32F7xx_HAL_Driver/Src/subdir.mk | 104 + .../pid_tuning/otto_pid_tuning/Debug/makefile | 80 + .../otto_pid_tuning/Debug/objects.list | 26 + .../otto_pid_tuning/Debug/objects.mk | 8 + .../Debug/otto_pid_tuning.list | 13979 ++++++++++ .../otto_pid_tuning/Debug/sources.mk | 32 + .../otto_pid_tuning/otto_pid_tuning.ioc | 4 +- utils/proto_test/.project | 11 + .../__pycache__/velocities_pb2.cpython-36.pyc | Bin 0 -> 1767 bytes utils/proto_test/otto_proto_test/.cproject | 227 + utils/proto_test/otto_proto_test/.mxproject | 25 + utils/proto_test/otto_proto_test/.project | 34 + .../com.st.stm32cube.ide.mcu.sfrview.prefs | 3 + .../.settings/language.settings.xml | 27 + .../org.eclipse.cdt.codan.core.prefs | 56 + .../.settings/org.eclipse.cdt.ui.prefs | 2 + .../.settings/org.eclipse.core.runtime.prefs | 3 + .../Core/Inc/communication_utils.h | 32 + .../otto_proto_test/Core/Inc/constants.h | 14 + .../otto_proto_test/Core/Inc/encoder.h | 46 + .../otto_proto_test/Core/Inc/main.h | 104 + .../Core/Inc/motor_controller.h | 67 + .../otto_proto_test/Core/Inc/odometry.h | 49 + .../proto_test/otto_proto_test/Core/Inc/pb.h | 838 + .../otto_proto_test/Core/Inc/pb_common.h | 45 + .../otto_proto_test/Core/Inc/pb_decode.h | 193 + .../otto_proto_test/Core/Inc/pb_encode.h | 185 + .../proto_test/otto_proto_test/Core/Inc/pid.h | 84 + .../Core/Inc/stm32f7xx_hal_conf.h | 442 + .../otto_proto_test/Core/Inc/stm32f7xx_it.h | 73 + .../otto_proto_test/Core/Inc/velocities.pb.h | 50 + .../otto_proto_test/Core/Src/encoder.cpp | 50 + .../otto_proto_test/Core/Src/main.cpp | 712 + .../otto_proto_test/Core/Src/pb_common.c | 336 + .../otto_proto_test/Core/Src/pb_decode.c | 1728 ++ .../otto_proto_test/Core/Src/pb_encode.c | 958 + .../Core/Src/stm32f7xx_hal_msp.c | 391 + .../otto_proto_test/Core/Src/stm32f7xx_it.c | 261 + .../otto_proto_test/Core/Src/syscalls.c | 184 + .../otto_proto_test/Core/Src/sysmem.c | 83 + .../Core/Src/system_stm32f7xx.c | 278 + .../otto_proto_test/Core/Src/velocities.pb.c | 12 + .../Core/Startup/startup_stm32f767zitx.s | 634 + .../otto_proto_test/Debug/Core/Src/subdir.mk | 73 + .../Debug/Core/Startup/subdir.mk | 16 + .../STM32F7xx_HAL_Driver/Src/subdir.mk | 104 + .../proto_test/otto_proto_test/Debug/makefile | 80 + .../otto_proto_test/Debug/objects.list | 30 + .../otto_proto_test/Debug/objects.mk | 8 + .../Debug/otto_proto_test.list | 22202 ++++++++++++++++ .../otto_proto_test/Debug/sources.mk | 32 + .../Device/ST/STM32F7xx/Include/stm32f767xx.h | 18631 +++++++++++++ .../Device/ST/STM32F7xx/Include/stm32f7xx.h | 236 + .../ST/STM32F7xx/Include/system_stm32f7xx.h | 123 + .../Drivers/CMSIS/Include/cmsis_armcc.h | 865 + .../Drivers/CMSIS/Include/cmsis_armclang.h | 1869 ++ .../Drivers/CMSIS/Include/cmsis_compiler.h | 266 + .../Drivers/CMSIS/Include/cmsis_gcc.h | 2085 ++ .../Drivers/CMSIS/Include/cmsis_iccarm.h | 935 + .../Drivers/CMSIS/Include/cmsis_version.h | 39 + .../Drivers/CMSIS/Include/core_armv8mbl.h | 1918 ++ .../Drivers/CMSIS/Include/core_armv8mml.h | 2927 ++ .../Drivers/CMSIS/Include/core_cm0.h | 949 + .../Drivers/CMSIS/Include/core_cm0plus.h | 1083 + .../Drivers/CMSIS/Include/core_cm1.h | 976 + .../Drivers/CMSIS/Include/core_cm23.h | 1993 ++ .../Drivers/CMSIS/Include/core_cm3.h | 1941 ++ .../Drivers/CMSIS/Include/core_cm33.h | 3002 +++ .../Drivers/CMSIS/Include/core_cm4.h | 2129 ++ .../Drivers/CMSIS/Include/core_cm7.h | 2671 ++ .../Drivers/CMSIS/Include/core_sc000.h | 1022 + .../Drivers/CMSIS/Include/core_sc300.h | 1915 ++ .../Drivers/CMSIS/Include/mpu_armv7.h | 270 + .../Drivers/CMSIS/Include/mpu_armv8.h | 333 + .../Drivers/CMSIS/Include/tz_context.h | 70 + .../Inc/Legacy/stm32_hal_legacy.h | 3451 +++ .../STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h | 276 + .../Inc/stm32f7xx_hal_cortex.h | 406 + .../Inc/stm32f7xx_hal_def.h | 205 + .../Inc/stm32f7xx_hal_dma.h | 749 + .../Inc/stm32f7xx_hal_dma_ex.h | 185 + .../Inc/stm32f7xx_hal_exti.h | 260 + .../Inc/stm32f7xx_hal_flash.h | 418 + .../Inc/stm32f7xx_hal_flash_ex.h | 700 + .../Inc/stm32f7xx_hal_gpio.h | 309 + .../Inc/stm32f7xx_hal_gpio_ex.h | 658 + .../Inc/stm32f7xx_hal_i2c.h | 782 + .../Inc/stm32f7xx_hal_i2c_ex.h | 205 + .../Inc/stm32f7xx_hal_pwr.h | 404 + .../Inc/stm32f7xx_hal_pwr_ex.h | 262 + .../Inc/stm32f7xx_hal_rcc.h | 1310 + .../Inc/stm32f7xx_hal_rcc_ex.h | 3524 +++ .../Inc/stm32f7xx_hal_tim.h | 2166 ++ .../Inc/stm32f7xx_hal_tim_ex.h | 355 + .../Inc/stm32f7xx_hal_uart.h | 1429 + .../Inc/stm32f7xx_hal_uart_ex.h | 393 + .../STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c | 608 + .../Src/stm32f7xx_hal_cortex.c | 505 + .../Src/stm32f7xx_hal_dma.c | 1307 + .../Src/stm32f7xx_hal_dma_ex.c | 310 + .../Src/stm32f7xx_hal_exti.c | 451 + .../Src/stm32f7xx_hal_flash.c | 817 + .../Src/stm32f7xx_hal_flash_ex.c | 1122 + .../Src/stm32f7xx_hal_gpio.c | 531 + .../Src/stm32f7xx_hal_i2c.c | 6523 +++++ .../Src/stm32f7xx_hal_i2c_ex.c | 258 + .../Src/stm32f7xx_hal_pwr.c | 599 + .../Src/stm32f7xx_hal_pwr_ex.c | 554 + .../Src/stm32f7xx_hal_rcc.c | 1221 + .../Src/stm32f7xx_hal_rcc_ex.c | 1776 ++ .../Src/stm32f7xx_hal_tim.c | 6880 +++++ .../Src/stm32f7xx_hal_tim_ex.c | 2137 ++ .../Src/stm32f7xx_hal_uart.c | 3471 +++ .../Src/stm32f7xx_hal_uart_ex.c | 330 + .../otto_proto_test/STM32F767ZITX_FLASH.ld | 200 + .../otto_proto_test/STM32F767ZITX_RAM.ld | 200 + .../otto_proto_test Debug.launch | 64 + .../otto_proto_test/otto_proto_test.ioc | 245 + utils/proto_test/proto_receive.py | 28 + utils/proto_test/proto_transmit.py | 30 + utils/proto_test/velocities.pb.c | 12 + utils/proto_test/velocities.pb.h | 50 + utils/proto_test/velocities.proto | 6 + utils/proto_test/velocities_pb2.py | 76 + .../otto_ticks_calibration/Core/Inc/encoder.h | 4 +- .../Core/Src/encoder.cpp | 30 +- .../otto_ticks_calibration/Core/Src/main.cpp | 24 +- .../Debug/Core/Src/subdir.mk | 53 + .../Debug/Core/Startup/subdir.mk | 16 + .../STM32F7xx_HAL_Driver/Src/subdir.mk | 104 + .../otto_ticks_calibration/Debug/makefile | 80 + .../otto_ticks_calibration/Debug/objects.list | 26 + .../otto_ticks_calibration/Debug/objects.mk | 8 + .../Debug/otto_ticks_calibration.list | 13869 ++++++++++ .../otto_ticks_calibration/Debug/sources.mk | 32 + 156 files changed, 156704 insertions(+), 284 deletions(-) create mode 100644 utils/.project create mode 100644 utils/README.md create mode 100644 utils/catkin_ws/src/joypad_bridge/scripts/velocities_pb2.py create mode 100644 utils/catkin_ws/src/joypad_bridge/scripts/velocities_pb2.pyc create mode 100644 utils/pid_tuning/otto_pid_tuning/Debug/Core/Src/subdir.mk create mode 100644 utils/pid_tuning/otto_pid_tuning/Debug/Core/Startup/subdir.mk create mode 100644 utils/pid_tuning/otto_pid_tuning/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk create mode 100644 utils/pid_tuning/otto_pid_tuning/Debug/makefile create mode 100644 utils/pid_tuning/otto_pid_tuning/Debug/objects.list create mode 100644 utils/pid_tuning/otto_pid_tuning/Debug/objects.mk create mode 100644 utils/pid_tuning/otto_pid_tuning/Debug/otto_pid_tuning.list create mode 100644 utils/pid_tuning/otto_pid_tuning/Debug/sources.mk create mode 100644 utils/proto_test/.project create mode 100644 utils/proto_test/__pycache__/velocities_pb2.cpython-36.pyc create mode 100644 utils/proto_test/otto_proto_test/.cproject create mode 100644 utils/proto_test/otto_proto_test/.mxproject create mode 100644 utils/proto_test/otto_proto_test/.project create mode 100644 utils/proto_test/otto_proto_test/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs create mode 100644 utils/proto_test/otto_proto_test/.settings/language.settings.xml create mode 100644 utils/proto_test/otto_proto_test/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 utils/proto_test/otto_proto_test/.settings/org.eclipse.cdt.ui.prefs create mode 100644 utils/proto_test/otto_proto_test/.settings/org.eclipse.core.runtime.prefs create mode 100644 utils/proto_test/otto_proto_test/Core/Inc/communication_utils.h create mode 100644 utils/proto_test/otto_proto_test/Core/Inc/constants.h create mode 100644 utils/proto_test/otto_proto_test/Core/Inc/encoder.h create mode 100644 utils/proto_test/otto_proto_test/Core/Inc/main.h create mode 100644 utils/proto_test/otto_proto_test/Core/Inc/motor_controller.h create mode 100644 utils/proto_test/otto_proto_test/Core/Inc/odometry.h create mode 100644 utils/proto_test/otto_proto_test/Core/Inc/pb.h create mode 100644 utils/proto_test/otto_proto_test/Core/Inc/pb_common.h create mode 100644 utils/proto_test/otto_proto_test/Core/Inc/pb_decode.h create mode 100644 utils/proto_test/otto_proto_test/Core/Inc/pb_encode.h create mode 100644 utils/proto_test/otto_proto_test/Core/Inc/pid.h create mode 100644 utils/proto_test/otto_proto_test/Core/Inc/stm32f7xx_hal_conf.h create mode 100644 utils/proto_test/otto_proto_test/Core/Inc/stm32f7xx_it.h create mode 100644 utils/proto_test/otto_proto_test/Core/Inc/velocities.pb.h create mode 100644 utils/proto_test/otto_proto_test/Core/Src/encoder.cpp create mode 100644 utils/proto_test/otto_proto_test/Core/Src/main.cpp create mode 100644 utils/proto_test/otto_proto_test/Core/Src/pb_common.c create mode 100644 utils/proto_test/otto_proto_test/Core/Src/pb_decode.c create mode 100644 utils/proto_test/otto_proto_test/Core/Src/pb_encode.c create mode 100644 utils/proto_test/otto_proto_test/Core/Src/stm32f7xx_hal_msp.c create mode 100644 utils/proto_test/otto_proto_test/Core/Src/stm32f7xx_it.c create mode 100644 utils/proto_test/otto_proto_test/Core/Src/syscalls.c create mode 100644 utils/proto_test/otto_proto_test/Core/Src/sysmem.c create mode 100644 utils/proto_test/otto_proto_test/Core/Src/system_stm32f7xx.c create mode 100644 utils/proto_test/otto_proto_test/Core/Src/velocities.pb.c create mode 100644 utils/proto_test/otto_proto_test/Core/Startup/startup_stm32f767zitx.s create mode 100644 utils/proto_test/otto_proto_test/Debug/Core/Src/subdir.mk create mode 100644 utils/proto_test/otto_proto_test/Debug/Core/Startup/subdir.mk create mode 100644 utils/proto_test/otto_proto_test/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk create mode 100644 utils/proto_test/otto_proto_test/Debug/makefile create mode 100644 utils/proto_test/otto_proto_test/Debug/objects.list create mode 100644 utils/proto_test/otto_proto_test/Debug/objects.mk create mode 100644 utils/proto_test/otto_proto_test/Debug/otto_proto_test.list create mode 100644 utils/proto_test/otto_proto_test/Debug/sources.mk create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_armcc.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_armclang.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_compiler.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_gcc.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_iccarm.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_version.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_armv8mbl.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_armv8mml.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm0.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm0plus.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm1.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm23.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm3.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm33.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm4.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm7.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_sc000.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_sc300.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/mpu_armv7.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/mpu_armv8.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/tz_context.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c create mode 100644 utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c create mode 100644 utils/proto_test/otto_proto_test/STM32F767ZITX_FLASH.ld create mode 100644 utils/proto_test/otto_proto_test/STM32F767ZITX_RAM.ld create mode 100644 utils/proto_test/otto_proto_test/otto_proto_test Debug.launch create mode 100644 utils/proto_test/otto_proto_test/otto_proto_test.ioc create mode 100644 utils/proto_test/proto_receive.py create mode 100644 utils/proto_test/proto_transmit.py create mode 100644 utils/proto_test/velocities.pb.c create mode 100644 utils/proto_test/velocities.pb.h create mode 100644 utils/proto_test/velocities.proto create mode 100644 utils/proto_test/velocities_pb2.py create mode 100644 utils/ticks_calibration/otto_ticks_calibration/Debug/Core/Src/subdir.mk create mode 100644 utils/ticks_calibration/otto_ticks_calibration/Debug/Core/Startup/subdir.mk create mode 100644 utils/ticks_calibration/otto_ticks_calibration/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk create mode 100644 utils/ticks_calibration/otto_ticks_calibration/Debug/makefile create mode 100644 utils/ticks_calibration/otto_ticks_calibration/Debug/objects.list create mode 100644 utils/ticks_calibration/otto_ticks_calibration/Debug/objects.mk create mode 100644 utils/ticks_calibration/otto_ticks_calibration/Debug/otto_ticks_calibration.list create mode 100644 utils/ticks_calibration/otto_ticks_calibration/Debug/sources.mk diff --git a/otto_controller/.mxproject b/otto_controller/.mxproject index be93599..106deeb 100644 --- a/otto_controller/.mxproject +++ b/otto_controller/.mxproject @@ -12,8 +12,6 @@ SourceFiles#1=/home/fdila/Projects/otto/otto_controller/Core/Src/stm32f7xx_hal_m SourceFiles#2=/home/fdila/Projects/otto/otto_controller/Core/Src/main.c SourceFolderListSize=1 SourcePath#0=/home/fdila/Projects/otto/otto_controller/Core/Src -HeaderFiles=; -SourceFiles=; [PreviousLibFiles] LibFiles=Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm4.h; diff --git a/otto_controller/Core/Inc/communication_utils.h b/otto_controller/Core/Inc/communication_utils.h index 00841cf..c2d4582 100644 --- a/otto_controller/Core/Inc/communication_utils.h +++ b/otto_controller/Core/Inc/communication_utils.h @@ -30,3 +30,8 @@ typedef struct __attribute__((packed)){ int right_ticks; } ticks_msg; +typedef struct __attribute__((packed)){ + float left_vel; + float right_vel; +} wheel_msg; + diff --git a/otto_controller/Core/Inc/constants.h b/otto_controller/Core/Inc/constants.h index 2df0b3e..81f7ef6 100644 --- a/otto_controller/Core/Inc/constants.h +++ b/otto_controller/Core/Inc/constants.h @@ -4,8 +4,8 @@ #define BASELINE 0.3 //distance between wheels in meters #define MAX_DUTY_CYCLE 790 -#define LEFT_TICKS_PER_METER 195788 //no -#define RIGHT_TICKS_PER_METER 196829 //no +#define LEFT_TICKS_PER_METER 195788 +#define RIGHT_TICKS_PER_METER 196829 #define TICKS_PER_REVOLUTION 148000 //x4 resolution #define RIGHT_WHEEL_CIRCUMFERENCE 0.8 //in meters diff --git a/otto_controller/Core/Inc/encoder.h b/otto_controller/Core/Inc/encoder.h index bd05dfb..1bd94ab 100644 --- a/otto_controller/Core/Inc/encoder.h +++ b/otto_controller/Core/Inc/encoder.h @@ -19,8 +19,8 @@ class Encoder { ticks_per_meter_ = 0; } -// Encoder(TIM_HandleTypeDef *timer, float wheel_circ); - Encoder(TIM_HandleTypeDef *timer, int ticks_per_meters); + Encoder(TIM_HandleTypeDef *timer, float wheel_circ); +// Encoder(TIM_HandleTypeDef *timer, int ticks_per_meters); void Setup(); diff --git a/otto_controller/Core/Src/encoder.cpp b/otto_controller/Core/Src/encoder.cpp index 5deedf6..7e2ef9d 100644 --- a/otto_controller/Core/Src/encoder.cpp +++ b/otto_controller/Core/Src/encoder.cpp @@ -1,17 +1,17 @@ #include "encoder.h" -//Encoder::Encoder(TIM_HandleTypeDef *timer, float wheel_circ) { -// timer_ = timer; -// wheel_circumference_ = wheel_circ; -// -//} - -Encoder::Encoder(TIM_HandleTypeDef *timer, int ticks_per_meter) { +Encoder::Encoder(TIM_HandleTypeDef *timer, float wheel_circ) { timer_ = timer; - ticks_per_meter_ = ticks_per_meter; + wheel_circumference_ = wheel_circ; } +//Encoder::Encoder(TIM_HandleTypeDef *timer, int ticks_per_meter) { +// timer_ = timer; +// ticks_per_meter_ = ticks_per_meter; +// +//} + void Encoder::Setup() { HAL_TIM_Encoder_Start(timer_, TIM_CHANNEL_ALL); this->ResetCount(); @@ -26,17 +26,17 @@ void Encoder::UpdateValues() { this->ResetCount(); } -//float Encoder::GetMeters() { -// float meters = ((float) this->ticks_ * this->wheel_circumference_) -// / TICKS_PER_REVOLUTION; -// return meters; -//} - float Encoder::GetMeters() { - float meters = (((float) this->ticks_) / this->ticks_per_meter_); + float meters = ((float) this->ticks_ * this->wheel_circumference_) + / TICKS_PER_REVOLUTION; return meters; } +//float Encoder::GetMeters() { +// float meters = ((float) (this->ticks_) / this->ticks_per_meter_); +// return meters; +//} + float Encoder::GetLinearVelocity() { this->UpdateValues(); diff --git a/otto_controller/Core/Src/main.cpp b/otto_controller/Core/Src/main.cpp index 7357601..42f5890 100644 --- a/otto_controller/Core/Src/main.cpp +++ b/otto_controller/Core/Src/main.cpp @@ -58,8 +58,8 @@ UART_HandleTypeDef huart6; /* USER CODE BEGIN PV */ //Odometry -Encoder right_encoder = Encoder(&htim5, RIGHT_TICKS_PER_METER); -Encoder left_encoder = Encoder(&htim2, LEFT_TICKS_PER_METER); +Encoder right_encoder = Encoder(&htim2, RIGHT_WHEEL_CIRCUMFERENCE); +Encoder left_encoder = Encoder(&htim5, LEFT_WHEEL_CIRCUMFERENCE); Odometry odom = Odometry(); float left_velocity; @@ -94,6 +94,7 @@ uint8_t *rx_buffer; odometry_msg odom_msg; velocity_msg vel_msg; +wheel_msg wheels_msg; uint8_t mode = 0; //setup mode @@ -119,12 +120,14 @@ static void MX_NVIC_Init(void); /* USER CODE END 0 */ /** - * @brief The application entry point. - * @retval int - */ -int main(void) { + * @brief The application entry point. + * @retval int + */ +int main(void) +{ /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ + /* MCU Configuration--------------------------------------------------------*/ @@ -163,14 +166,14 @@ int main(void) { left_motor.coast(); right_motor.coast(); - tx_buffer = (uint8_t*) &odom_msg; + tx_buffer = (uint8_t*) &wheels_msg; rx_buffer = (uint8_t*) &vel_msg; //Enables UART RX interrupt HAL_UART_Receive_IT(&huart6, rx_buffer, 8); //Enables TIM6 interrupt (used for periodic transmission) - HAL_TIM_Base_Start_IT(&htim6); +// HAL_TIM_Base_Start_IT(&htim6); /* USER CODE END 2 */ @@ -185,51 +188,56 @@ int main(void) { } /** - * @brief System Clock Configuration - * @retval None - */ -void SystemClock_Config(void) { - RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; - RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 }; + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /** Configure the main internal regulator output voltage - */ + /** Configure the main internal regulator output voltage + */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); - /** Initializes the CPU, AHB and APB busses clocks - */ + /** Initializes the CPU, AHB and APB busses clocks + */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK - | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + { Error_Handler(); } PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6; PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { Error_Handler(); } } /** - * @brief NVIC Configuration. - * @retval None - */ -static void MX_NVIC_Init(void) { + * @brief NVIC Configuration. + * @retval None + */ +static void MX_NVIC_Init(void) +{ /* TIM3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(TIM3_IRQn, 2, 1); HAL_NVIC_EnableIRQ(TIM3_IRQn); @@ -237,23 +245,24 @@ static void MX_NVIC_Init(void) { HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 2, 2); HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); /* USART6_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(USART6_IRQn, 2, 0); + HAL_NVIC_SetPriority(USART6_IRQn, 1, 0); HAL_NVIC_EnableIRQ(USART6_IRQn); } /** - * @brief TIM2 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM2_Init(void) { + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) +{ /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ - TIM_Encoder_InitTypeDef sConfig = { 0 }; - TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + TIM_Encoder_InitTypeDef sConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; /* USER CODE BEGIN TIM2_Init 1 */ @@ -273,12 +282,14 @@ static void MX_TIM2_Init(void) { sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; sConfig.IC2Prescaler = TIM_ICPSC_DIV1; sConfig.IC2Filter = 0; - if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK) { + if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK) + { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) { + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + { Error_Handler(); } /* USER CODE BEGIN TIM2_Init 2 */ @@ -288,18 +299,19 @@ static void MX_TIM2_Init(void) { } /** - * @brief TIM3 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM3_Init(void) { + * @brief TIM3 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM3_Init(void) +{ /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ - TIM_ClockConfigTypeDef sClockSourceConfig = { 0 }; - TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; /* USER CODE BEGIN TIM3_Init 1 */ @@ -310,16 +322,19 @@ static void MX_TIM3_Init(void) { htim3.Init.Period = 159; htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim3) != HAL_OK) { + if (HAL_TIM_Base_Init(&htim3) != HAL_OK) + { Error_Handler(); } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; - if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) { + if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) + { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) { + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + { Error_Handler(); } /* USER CODE BEGIN TIM3_Init 2 */ @@ -329,19 +344,20 @@ static void MX_TIM3_Init(void) { } /** - * @brief TIM4 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM4_Init(void) { + * @brief TIM4 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM4_Init(void) +{ /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ - TIM_ClockConfigTypeDef sClockSourceConfig = { 0 }; - TIM_MasterConfigTypeDef sMasterConfig = { 0 }; - TIM_OC_InitTypeDef sConfigOC = { 0 }; + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; /* USER CODE BEGIN TIM4_Init 1 */ @@ -352,29 +368,35 @@ static void MX_TIM4_Init(void) { htim4.Init.Period = 799; htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim4) != HAL_OK) { + if (HAL_TIM_Base_Init(&htim4) != HAL_OK) + { Error_Handler(); } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; - if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) { + if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) + { Error_Handler(); } - if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) { + if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) + { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) { + if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) + { Error_Handler(); } sConfigOC.OCMode = TIM_OCMODE_PWM1; sConfigOC.Pulse = 0; sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; - if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) { + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + { Error_Handler(); } - if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) { + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { Error_Handler(); } /* USER CODE BEGIN TIM4_Init 2 */ @@ -385,18 +407,19 @@ static void MX_TIM4_Init(void) { } /** - * @brief TIM5 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM5_Init(void) { + * @brief TIM5 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM5_Init(void) +{ /* USER CODE BEGIN TIM5_Init 0 */ /* USER CODE END TIM5_Init 0 */ - TIM_Encoder_InitTypeDef sConfig = { 0 }; - TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + TIM_Encoder_InitTypeDef sConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; /* USER CODE BEGIN TIM5_Init 1 */ @@ -416,12 +439,14 @@ static void MX_TIM5_Init(void) { sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; sConfig.IC2Prescaler = TIM_ICPSC_DIV1; sConfig.IC2Filter = 0; - if (HAL_TIM_Encoder_Init(&htim5, &sConfig) != HAL_OK) { + if (HAL_TIM_Encoder_Init(&htim5, &sConfig) != HAL_OK) + { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) { + if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) + { Error_Handler(); } /* USER CODE BEGIN TIM5_Init 2 */ @@ -431,17 +456,18 @@ static void MX_TIM5_Init(void) { } /** - * @brief TIM6 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM6_Init(void) { + * @brief TIM6 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM6_Init(void) +{ /* USER CODE BEGIN TIM6_Init 0 */ /* USER CODE END TIM6_Init 0 */ - TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + TIM_MasterConfigTypeDef sMasterConfig = {0}; /* USER CODE BEGIN TIM6_Init 1 */ @@ -451,12 +477,14 @@ static void MX_TIM6_Init(void) { htim6.Init.CounterMode = TIM_COUNTERMODE_UP; htim6.Init.Period = 799; htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim6) != HAL_OK) { + if (HAL_TIM_Base_Init(&htim6) != HAL_OK) + { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) { + if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) + { Error_Handler(); } /* USER CODE BEGIN TIM6_Init 2 */ @@ -466,11 +494,12 @@ static void MX_TIM6_Init(void) { } /** - * @brief USART6 Initialization Function - * @param None - * @retval None - */ -static void MX_USART6_UART_Init(void) { + * @brief USART6 Initialization Function + * @param None + * @retval None + */ +static void MX_USART6_UART_Init(void) +{ /* USER CODE BEGIN USART6_Init 0 */ @@ -489,7 +518,8 @@ static void MX_USART6_UART_Init(void) { huart6.Init.OverSampling = UART_OVERSAMPLING_16; huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&huart6) != HAL_OK) { + if (HAL_UART_Init(&huart6) != HAL_OK) + { Error_Handler(); } /* USER CODE BEGIN USART6_Init 2 */ @@ -499,12 +529,13 @@ static void MX_USART6_UART_Init(void) { } /** - * @brief GPIO Initialization Function - * @param None - * @retval None - */ -static void MX_GPIO_Init(void) { - GPIO_InitTypeDef GPIO_InitStruct = { 0 }; + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); @@ -515,10 +546,10 @@ static void MX_GPIO_Init(void) { __HAL_RCC_GPIOB_CLK_ENABLE(); /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOF, dir2_Pin | dir1_Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOF, dir2_Pin|dir1_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOF, sleep2_Pin | sleep1_Pin, GPIO_PIN_SET); + HAL_GPIO_WritePin(GPIOF, sleep2_Pin|sleep1_Pin, GPIO_PIN_SET); /*Configure GPIO pin : user_button_Pin */ GPIO_InitStruct.Pin = user_button_Pin; @@ -545,14 +576,14 @@ static void MX_GPIO_Init(void) { HAL_GPIO_Init(fault2_GPIO_Port, &GPIO_InitStruct); /*Configure GPIO pins : dir2_Pin dir1_Pin */ - GPIO_InitStruct.Pin = dir2_Pin | dir1_Pin; + GPIO_InitStruct.Pin = dir2_Pin|dir1_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); /*Configure GPIO pins : sleep2_Pin sleep1_Pin */ - GPIO_InitStruct.Pin = sleep2_Pin | sleep1_Pin; + GPIO_InitStruct.Pin = sleep2_Pin|sleep1_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; @@ -591,6 +622,13 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { left_dutycycle += cross_dutycycle; right_dutycycle -= cross_dutycycle; + wheels_msg.left_vel = left_velocity; + wheels_msg.right_vel = right_velocity; + +// HAL_UART_Transmit(&huart6, tx_buffer, 4, 100); + +// HAL_UART_Transmit(&huart6, tx_buffer, 8, 100); + } //TIMER 2Hz Transmit @@ -633,10 +671,11 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { /* USER CODE END 4 */ /** - * @brief This function is executed in case of error occurrence. - * @retval None - */ -void Error_Handler(void) { + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ diff --git a/otto_controller/otto_controller.ioc b/otto_controller/otto_controller.ioc index a1b71b9..1d213fa 100644 --- a/otto_controller/otto_controller.ioc +++ b/otto_controller/otto_controller.ioc @@ -57,7 +57,7 @@ NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.TIM3_IRQn=true\:2\:1\:true\:true\:true\:1\:true\:true NVIC.TIM6_DAC_IRQn=true\:2\:2\:true\:true\:true\:2\:true\:true -NVIC.USART6_IRQn=true\:2\:0\:true\:true\:true\:3\:true\:true +NVIC.USART6_IRQn=true\:1\:0\:true\:true\:true\:3\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false PA0/WKUP.GPIOParameters=GPIO_Label PA0/WKUP.GPIO_Label=encoder_dx1 diff --git a/utils/.project b/utils/.project new file mode 100644 index 0000000..00f8a75 --- /dev/null +++ b/utils/.project @@ -0,0 +1,11 @@ + + + utils + + + + + + + + diff --git a/utils/README.md b/utils/README.md new file mode 100644 index 0000000..504a728 --- /dev/null +++ b/utils/README.md @@ -0,0 +1,6 @@ +## Utils + +* catikin_ws contains useful ROS nodes. +* pid_tuning contains Otto code and python scripts for PID tuning +* py_serial_examples contains pyserial_examples +* ticks_calibration contains Otto code and python scripts for ticks calibration \ No newline at end of file diff --git a/utils/catkin_ws/src/joypad_bridge/scripts/cmd_vel_transmitter.py b/utils/catkin_ws/src/joypad_bridge/scripts/cmd_vel_transmitter.py index 381ae56..c76b398 100755 --- a/utils/catkin_ws/src/joypad_bridge/scripts/cmd_vel_transmitter.py +++ b/utils/catkin_ws/src/joypad_bridge/scripts/cmd_vel_transmitter.py @@ -6,7 +6,7 @@ from serial import SerialException ser = serial.Serial( baudrate=115200, - parity=serial.PARITY_NONE, + parity=serial.PARITY_ODD, stopbits=serial.STOPBITS_ONE, bytesize=serial.EIGHTBITS, rtscts=False) diff --git a/utils/catkin_ws/src/joypad_bridge/scripts/velocities_pb2.py b/utils/catkin_ws/src/joypad_bridge/scripts/velocities_pb2.py new file mode 100644 index 0000000..2f13360 --- /dev/null +++ b/utils/catkin_ws/src/joypad_bridge/scripts/velocities_pb2.py @@ -0,0 +1,76 @@ +# Generated by the protocol buffer compiler. DO NOT EDIT! +# source: velocities.proto + +import sys +_b=sys.version_info[0]<3 and (lambda x:x) or (lambda x:x.encode('latin1')) +from google.protobuf import descriptor as _descriptor +from google.protobuf import message as _message +from google.protobuf import reflection as _reflection +from google.protobuf import symbol_database as _symbol_database +from google.protobuf import descriptor_pb2 +# @@protoc_insertion_point(imports) + +_sym_db = _symbol_database.Default() + + + + +DESCRIPTOR = _descriptor.FileDescriptor( + name='velocities.proto', + package='', + syntax='proto3', + serialized_pb=_b('\n\x10velocities.proto\"5\n\nVelocities\x12\x12\n\nlinear_vel\x18\x01 \x01(\x02\x12\x13\n\x0b\x61ngular_vel\x18\x02 \x01(\x02\x62\x06proto3') +) +_sym_db.RegisterFileDescriptor(DESCRIPTOR) + + + + +_VELOCITIES = _descriptor.Descriptor( + name='Velocities', + full_name='Velocities', + filename=None, + file=DESCRIPTOR, + containing_type=None, + fields=[ + _descriptor.FieldDescriptor( + name='linear_vel', full_name='Velocities.linear_vel', index=0, + number=1, type=2, cpp_type=6, label=1, + has_default_value=False, default_value=float(0), + message_type=None, enum_type=None, containing_type=None, + is_extension=False, extension_scope=None, + options=None), + _descriptor.FieldDescriptor( + name='angular_vel', full_name='Velocities.angular_vel', index=1, + number=2, type=2, cpp_type=6, label=1, + has_default_value=False, default_value=float(0), + message_type=None, enum_type=None, containing_type=None, + is_extension=False, extension_scope=None, + options=None), + ], + extensions=[ + ], + nested_types=[], + enum_types=[ + ], + options=None, + is_extendable=False, + syntax='proto3', + extension_ranges=[], + oneofs=[ + ], + serialized_start=20, + serialized_end=73, +) + +DESCRIPTOR.message_types_by_name['Velocities'] = _VELOCITIES + +Velocities = _reflection.GeneratedProtocolMessageType('Velocities', (_message.Message,), dict( + DESCRIPTOR = _VELOCITIES, + __module__ = 'velocities_pb2' + # @@protoc_insertion_point(class_scope:Velocities) + )) +_sym_db.RegisterMessage(Velocities) + + +# @@protoc_insertion_point(module_scope) diff --git a/utils/catkin_ws/src/joypad_bridge/scripts/velocities_pb2.pyc b/utils/catkin_ws/src/joypad_bridge/scripts/velocities_pb2.pyc new file mode 100644 index 0000000000000000000000000000000000000000..68b9ec6db01ebedde1fb65d9e237fecdb6c4711b GIT binary patch literal 2459 zcmcgtZEqVz5Pt5QIJM&>uKSj@=?jH|p(Um*pSaq z9U8$y{D7dDb?l^{0b5?}%+Ag{^UTb;^7mT(=fAdp$uRre1@H|3_gxHVKu54Z z4U)mwD5RmoPMYapUk4A(FPdh4KN3^$-xp&QU^(Cg3}&`s#GpcuM^X@n`3dQH$ehG#)d z)+pOJdv!!f3 z%Ws3sO7|0h&g)`CoxV0!bzYRkkTUN&h4)2g;*E8kO!+q^PkwV9S7x1IaX3~wNlT*# z)Nxs9#@=-f$QGILhFmgE?{AL}{TTp{tQw_SJzfUjIo=#;3f3ITgtpC z@?f;Vlpl`L!X{dIl`1zgUO(lLDfC>zT#d*z0W9d<9+!nLB-~hKZ`6PUnDFBcbFbdY zR;(U)X4g?^lr_JTPR6PG5kS59uD@Fk>-AUj61H0Px-~heGC3f-8QqN9aqC=tRpo<; zohf5hrqx*-W@K^S*8ub<)+U^QbVA=)5`oiVLAc0@+$)ote31CVF$wa%A*-EuTwrh) zP6gOroOrH{$u)(%^T{Zs(s0ov6uUKCIYE()#}deJH_1(_QnLOmfY-_;n)+&DeR81e zgoM1)n#Q8Y0Wc>@`D7F%J~l3)x1Mrmid=G>ONq;hF-hf$G53V?s{l@r>Mown^2Cww zF?Z!8R8G#5me7H(IT9z>kD+LlTJqdRa|cPO@&P#^yvV8OJ2^kmD$c9YoAb;QH|L2H z%C*^LJs17yv;8OC-4`#PcSTH+QK2W6l0glB4mG^_mN)}_+l^XIZlg#F>%QG0v7K7Ji3rQ|{XY#sSJSoT1P5yx->A(Q+fJ4@G&=+_S-A+(CIte)h7-)qa9@($*yk;Init.Period / 2)); + __HAL_TIM_SET_COUNTER(timer_, (timer_->Init.Period) / 2); } void UpdateValues(); diff --git a/utils/pid_tuning/otto_pid_tuning/Core/Inc/odometry.h b/utils/pid_tuning/otto_pid_tuning/Core/Inc/odometry.h index 56e0e8b..2d13eeb 100644 --- a/utils/pid_tuning/otto_pid_tuning/Core/Inc/odometry.h +++ b/utils/pid_tuning/otto_pid_tuning/Core/Inc/odometry.h @@ -18,7 +18,7 @@ class Odometry { void UpdateValues(float linear_vel, float angular_vel) { left_velocity_ = linear_vel - (BASELINE * angular_vel)/2; - right_velocity_ = linear_vel + (BASELINE * angular_vel)/2; + right_velocity_ = 2 * linear_vel - left_velocity_; } float GetLeftVelocity(){ diff --git a/utils/pid_tuning/otto_pid_tuning/Core/Src/encoder.cpp b/utils/pid_tuning/otto_pid_tuning/Core/Src/encoder.cpp index 5deedf6..b826703 100644 --- a/utils/pid_tuning/otto_pid_tuning/Core/Src/encoder.cpp +++ b/utils/pid_tuning/otto_pid_tuning/Core/Src/encoder.cpp @@ -1,15 +1,8 @@ #include "encoder.h" -//Encoder::Encoder(TIM_HandleTypeDef *timer, float wheel_circ) { -// timer_ = timer; -// wheel_circumference_ = wheel_circ; -// -//} - -Encoder::Encoder(TIM_HandleTypeDef *timer, int ticks_per_meter) { +Encoder::Encoder(TIM_HandleTypeDef *timer, float wheel_circ) { timer_ = timer; - ticks_per_meter_ = ticks_per_meter; - + wheel_circumference_ = wheel_circ; } void Encoder::Setup() { @@ -26,21 +19,17 @@ void Encoder::UpdateValues() { this->ResetCount(); } -//float Encoder::GetMeters() { -// float meters = ((float) this->ticks_ * this->wheel_circumference_) -// / TICKS_PER_REVOLUTION; -// return meters; -//} - float Encoder::GetMeters() { - float meters = (((float) this->ticks_) / this->ticks_per_meter_); + this->UpdateValues(); + float meters = ((float) this->ticks_ * this->wheel_circumference_) + / TICKS_PER_REVOLUTION; return meters; } - float Encoder::GetLinearVelocity() { this->UpdateValues(); - float meters = this->GetMeters(); + float meters = ((float) this->ticks_ * this->wheel_circumference_) + / TICKS_PER_REVOLUTION; float deltaTime = this->current_millis_ - this->previous_millis_; if (deltaTime == 0) return 0; diff --git a/utils/pid_tuning/otto_pid_tuning/Core/Src/main.cpp b/utils/pid_tuning/otto_pid_tuning/Core/Src/main.cpp index ebad4e5..519cc94 100644 --- a/utils/pid_tuning/otto_pid_tuning/Core/Src/main.cpp +++ b/utils/pid_tuning/otto_pid_tuning/Core/Src/main.cpp @@ -125,12 +125,14 @@ static void MX_NVIC_Init(void); /* USER CODE END 0 */ /** - * @brief The application entry point. - * @retval int - */ -int main(void) { + * @brief The application entry point. + * @retval int + */ +int main(void) +{ /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ + /* MCU Configuration--------------------------------------------------------*/ @@ -189,51 +191,56 @@ int main(void) { } /** - * @brief System Clock Configuration - * @retval None - */ -void SystemClock_Config(void) { - RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; - RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 }; + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; /** Configure the main internal regulator output voltage - */ + */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); /** Initializes the CPU, AHB and APB busses clocks - */ + */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { Error_Handler(); } /** Initializes the CPU, AHB and APB busses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK - | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + { Error_Handler(); } PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6; PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { Error_Handler(); } } /** - * @brief NVIC Configuration. - * @retval None - */ -static void MX_NVIC_Init(void) { + * @brief NVIC Configuration. + * @retval None + */ +static void MX_NVIC_Init(void) +{ /* TIM3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(TIM3_IRQn, 2, 1); HAL_NVIC_EnableIRQ(TIM3_IRQn); @@ -246,18 +253,19 @@ static void MX_NVIC_Init(void) { } /** - * @brief TIM2 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM2_Init(void) { + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) +{ /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ - TIM_Encoder_InitTypeDef sConfig = { 0 }; - TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + TIM_Encoder_InitTypeDef sConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; /* USER CODE BEGIN TIM2_Init 1 */ @@ -277,12 +285,14 @@ static void MX_TIM2_Init(void) { sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; sConfig.IC2Prescaler = TIM_ICPSC_DIV1; sConfig.IC2Filter = 0; - if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK) { + if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK) + { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) { + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + { Error_Handler(); } /* USER CODE BEGIN TIM2_Init 2 */ @@ -292,18 +302,19 @@ static void MX_TIM2_Init(void) { } /** - * @brief TIM3 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM3_Init(void) { + * @brief TIM3 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM3_Init(void) +{ /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ - TIM_ClockConfigTypeDef sClockSourceConfig = { 0 }; - TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; /* USER CODE BEGIN TIM3_Init 1 */ @@ -314,16 +325,19 @@ static void MX_TIM3_Init(void) { htim3.Init.Period = 159; htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim3) != HAL_OK) { + if (HAL_TIM_Base_Init(&htim3) != HAL_OK) + { Error_Handler(); } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; - if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) { + if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) + { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) { + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + { Error_Handler(); } /* USER CODE BEGIN TIM3_Init 2 */ @@ -333,19 +347,20 @@ static void MX_TIM3_Init(void) { } /** - * @brief TIM4 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM4_Init(void) { + * @brief TIM4 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM4_Init(void) +{ /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ - TIM_ClockConfigTypeDef sClockSourceConfig = { 0 }; - TIM_MasterConfigTypeDef sMasterConfig = { 0 }; - TIM_OC_InitTypeDef sConfigOC = { 0 }; + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; /* USER CODE BEGIN TIM4_Init 1 */ @@ -356,29 +371,35 @@ static void MX_TIM4_Init(void) { htim4.Init.Period = 799; htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim4) != HAL_OK) { + if (HAL_TIM_Base_Init(&htim4) != HAL_OK) + { Error_Handler(); } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; - if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) { + if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) + { Error_Handler(); } - if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) { + if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) + { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) { + if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) + { Error_Handler(); } sConfigOC.OCMode = TIM_OCMODE_PWM1; sConfigOC.Pulse = 0; sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; - if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) { + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + { Error_Handler(); } - if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) { + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { Error_Handler(); } /* USER CODE BEGIN TIM4_Init 2 */ @@ -389,18 +410,19 @@ static void MX_TIM4_Init(void) { } /** - * @brief TIM5 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM5_Init(void) { + * @brief TIM5 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM5_Init(void) +{ /* USER CODE BEGIN TIM5_Init 0 */ /* USER CODE END TIM5_Init 0 */ - TIM_Encoder_InitTypeDef sConfig = { 0 }; - TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + TIM_Encoder_InitTypeDef sConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; /* USER CODE BEGIN TIM5_Init 1 */ @@ -420,12 +442,14 @@ static void MX_TIM5_Init(void) { sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; sConfig.IC2Prescaler = TIM_ICPSC_DIV1; sConfig.IC2Filter = 0; - if (HAL_TIM_Encoder_Init(&htim5, &sConfig) != HAL_OK) { + if (HAL_TIM_Encoder_Init(&htim5, &sConfig) != HAL_OK) + { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) { + if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) + { Error_Handler(); } /* USER CODE BEGIN TIM5_Init 2 */ @@ -435,17 +459,18 @@ static void MX_TIM5_Init(void) { } /** - * @brief TIM6 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM6_Init(void) { + * @brief TIM6 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM6_Init(void) +{ /* USER CODE BEGIN TIM6_Init 0 */ /* USER CODE END TIM6_Init 0 */ - TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + TIM_MasterConfigTypeDef sMasterConfig = {0}; /* USER CODE BEGIN TIM6_Init 1 */ @@ -455,12 +480,14 @@ static void MX_TIM6_Init(void) { htim6.Init.CounterMode = TIM_COUNTERMODE_UP; htim6.Init.Period = 799; htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim6) != HAL_OK) { + if (HAL_TIM_Base_Init(&htim6) != HAL_OK) + { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) { + if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) + { Error_Handler(); } /* USER CODE BEGIN TIM6_Init 2 */ @@ -470,11 +497,12 @@ static void MX_TIM6_Init(void) { } /** - * @brief USART6 Initialization Function - * @param None - * @retval None - */ -static void MX_USART6_UART_Init(void) { + * @brief USART6 Initialization Function + * @param None + * @retval None + */ +static void MX_USART6_UART_Init(void) +{ /* USER CODE BEGIN USART6_Init 0 */ @@ -485,15 +513,16 @@ static void MX_USART6_UART_Init(void) { /* USER CODE END USART6_Init 1 */ huart6.Instance = USART6; huart6.Init.BaudRate = 115200; - huart6.Init.WordLength = UART_WORDLENGTH_9B; + huart6.Init.WordLength = UART_WORDLENGTH_8B; huart6.Init.StopBits = UART_STOPBITS_1; - huart6.Init.Parity = UART_PARITY_ODD; + huart6.Init.Parity = UART_PARITY_NONE; huart6.Init.Mode = UART_MODE_TX_RX; huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE; huart6.Init.OverSampling = UART_OVERSAMPLING_16; huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&huart6) != HAL_OK) { + if (HAL_UART_Init(&huart6) != HAL_OK) + { Error_Handler(); } /* USER CODE BEGIN USART6_Init 2 */ @@ -503,12 +532,13 @@ static void MX_USART6_UART_Init(void) { } /** - * @brief GPIO Initialization Function - * @param None - * @retval None - */ -static void MX_GPIO_Init(void) { - GPIO_InitTypeDef GPIO_InitStruct = { 0 }; + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); @@ -519,10 +549,10 @@ static void MX_GPIO_Init(void) { __HAL_RCC_GPIOB_CLK_ENABLE(); /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOF, dir2_Pin | dir1_Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOF, dir2_Pin|dir1_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOF, sleep2_Pin | sleep1_Pin, GPIO_PIN_SET); + HAL_GPIO_WritePin(GPIOF, sleep2_Pin|sleep1_Pin, GPIO_PIN_SET); /*Configure GPIO pin : user_button_Pin */ GPIO_InitStruct.Pin = user_button_Pin; @@ -549,14 +579,14 @@ static void MX_GPIO_Init(void) { HAL_GPIO_Init(fault2_GPIO_Port, &GPIO_InitStruct); /*Configure GPIO pins : dir2_Pin dir1_Pin */ - GPIO_InitStruct.Pin = dir2_Pin | dir1_Pin; + GPIO_InitStruct.Pin = dir2_Pin|dir1_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); /*Configure GPIO pins : sleep2_Pin sleep1_Pin */ - GPIO_InitStruct.Pin = sleep2_Pin | sleep1_Pin; + GPIO_InitStruct.Pin = sleep2_Pin|sleep1_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; @@ -675,10 +705,11 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { /* USER CODE END 4 */ /** - * @brief This function is executed in case of error occurrence. - * @retval None - */ -void Error_Handler(void) { + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ diff --git a/utils/pid_tuning/otto_pid_tuning/Debug/Core/Src/subdir.mk b/utils/pid_tuning/otto_pid_tuning/Debug/Core/Src/subdir.mk new file mode 100644 index 0000000..4fcd8af --- /dev/null +++ b/utils/pid_tuning/otto_pid_tuning/Debug/Core/Src/subdir.mk @@ -0,0 +1,53 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/stm32f7xx_hal_msp.c \ +../Core/Src/stm32f7xx_it.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32f7xx.c + +CPP_SRCS += \ +../Core/Src/encoder.cpp \ +../Core/Src/main.cpp + +OBJS += \ +./Core/Src/encoder.o \ +./Core/Src/main.o \ +./Core/Src/stm32f7xx_hal_msp.o \ +./Core/Src/stm32f7xx_it.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32f7xx.o + +C_DEPS += \ +./Core/Src/stm32f7xx_hal_msp.d \ +./Core/Src/stm32f7xx_it.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32f7xx.d + +CPP_DEPS += \ +./Core/Src/encoder.d \ +./Core/Src/main.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/encoder.o: ../Core/Src/encoder.cpp + arm-none-eabi-g++ "$<" -mcpu=cortex-m7 -std=gnu++14 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-threadsafe-statics -fno-use-cxa-atexit -Wall -fstack-usage -MMD -MP -MF"Core/Src/encoder.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/main.o: ../Core/Src/main.cpp + arm-none-eabi-g++ "$<" -mcpu=cortex-m7 -std=gnu++14 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-threadsafe-statics -fno-use-cxa-atexit -Wall -fstack-usage -MMD -MP -MF"Core/Src/main.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32f7xx_hal_msp.o: ../Core/Src/stm32f7xx_hal_msp.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f7xx_hal_msp.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32f7xx_it.o: ../Core/Src/stm32f7xx_it.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f7xx_it.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/syscalls.o: ../Core/Src/syscalls.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/syscalls.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/sysmem.o: ../Core/Src/sysmem.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/sysmem.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/system_stm32f7xx.o: ../Core/Src/system_stm32f7xx.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/system_stm32f7xx.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/utils/pid_tuning/otto_pid_tuning/Debug/Core/Startup/subdir.mk b/utils/pid_tuning/otto_pid_tuning/Debug/Core/Startup/subdir.mk new file mode 100644 index 0000000..481e2a5 --- /dev/null +++ b/utils/pid_tuning/otto_pid_tuning/Debug/Core/Startup/subdir.mk @@ -0,0 +1,16 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32f767zitx.s + +OBJS += \ +./Core/Startup/startup_stm32f767zitx.o + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/%.o: ../Core/Startup/%.s + arm-none-eabi-gcc -mcpu=cortex-m7 -g3 -c -x assembler-with-cpp --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" "$<" + diff --git a/utils/pid_tuning/otto_pid_tuning/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk b/utils/pid_tuning/otto_pid_tuning/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk new file mode 100644 index 0000000..2a0a6ce --- /dev/null +++ b/utils/pid_tuning/otto_pid_tuning/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,104 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c + +OBJS += \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + +C_DEPS += \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/utils/pid_tuning/otto_pid_tuning/Debug/makefile b/utils/pid_tuning/otto_pid_tuning/Debug/makefile new file mode 100644 index 0000000..792af69 --- /dev/null +++ b/utils/pid_tuning/otto_pid_tuning/Debug/makefile @@ -0,0 +1,80 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +otto_pid_tuning.elf \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +otto_pid_tuning.list \ + + +# All Target +all: otto_pid_tuning.elf secondary-outputs + +# Tool invocations +otto_pid_tuning.elf: $(OBJS) $(USER_OBJS) /home/fdila/Projects/otto/utils/pid_tuning/otto_pid_tuning/STM32F767ZITX_FLASH.ld + arm-none-eabi-g++ -o "otto_pid_tuning.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m7 -T"/home/fdila/Projects/otto/utils/pid_tuning/otto_pid_tuning/STM32F767ZITX_FLASH.ld" -Wl,-Map="otto_pid_tuning.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +otto_pid_tuning.list: $(EXECUTABLES) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "otto_pid_tuning.list" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) * + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets diff --git a/utils/pid_tuning/otto_pid_tuning/Debug/objects.list b/utils/pid_tuning/otto_pid_tuning/Debug/objects.list new file mode 100644 index 0000000..c7c9831 --- /dev/null +++ b/utils/pid_tuning/otto_pid_tuning/Debug/objects.list @@ -0,0 +1,26 @@ +"Core/Src/encoder.o" +"Core/Src/main.o" +"Core/Src/stm32f7xx_hal_msp.o" +"Core/Src/stm32f7xx_it.o" +"Core/Src/syscalls.o" +"Core/Src/sysmem.o" +"Core/Src/system_stm32f7xx.o" +"Core/Startup/startup_stm32f767zitx.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o" diff --git a/utils/pid_tuning/otto_pid_tuning/Debug/objects.mk b/utils/pid_tuning/otto_pid_tuning/Debug/objects.mk new file mode 100644 index 0000000..742c2da --- /dev/null +++ b/utils/pid_tuning/otto_pid_tuning/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/utils/pid_tuning/otto_pid_tuning/Debug/otto_pid_tuning.list b/utils/pid_tuning/otto_pid_tuning/Debug/otto_pid_tuning.list new file mode 100644 index 0000000..03f5b76 --- /dev/null +++ b/utils/pid_tuning/otto_pid_tuning/Debug/otto_pid_tuning.list @@ -0,0 +1,13979 @@ + +otto_pid_tuning.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 000001f8 08000000 08000000 00010000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 000053e0 080001f8 080001f8 000101f8 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00000018 080055d8 080055d8 000155d8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 080055f0 080055f0 00020010 2**0 + CONTENTS + 4 .ARM 00000008 080055f0 080055f0 000155f0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 080055f8 080055f8 00020010 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000008 080055f8 080055f8 000155f8 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .fini_array 00000004 08005600 08005600 00015600 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 .data 00000010 20000000 08005604 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 000002fc 20000010 08005614 00020010 2**2 + ALLOC + 10 ._user_heap_stack 00000604 2000030c 08005614 0002030c 2**0 + ALLOC + 11 .ARM.attributes 0000002e 00000000 00000000 00020010 2**0 + CONTENTS, READONLY + 12 .debug_info 0000dba7 00000000 00000000 0002003e 2**0 + CONTENTS, READONLY, DEBUGGING + 13 .debug_abbrev 00001e1a 00000000 00000000 0002dbe5 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_aranges 00000d60 00000000 00000000 0002fa00 2**3 + CONTENTS, READONLY, DEBUGGING + 15 .debug_ranges 00000c78 00000000 00000000 00030760 2**3 + CONTENTS, READONLY, DEBUGGING + 16 .debug_macro 00028237 00000000 00000000 000313d8 2**0 + CONTENTS, READONLY, DEBUGGING + 17 .debug_line 00009a73 00000000 00000000 0005960f 2**0 + CONTENTS, READONLY, DEBUGGING + 18 .debug_str 000f1e08 00000000 00000000 00063082 2**0 + CONTENTS, READONLY, DEBUGGING + 19 .comment 0000007b 00000000 00000000 00154e8a 2**0 + CONTENTS, READONLY + 20 .debug_frame 00003830 00000000 00000000 00154f08 2**2 + CONTENTS, READONLY, DEBUGGING + +Disassembly of section .text: + +080001f8 <__do_global_dtors_aux>: + 80001f8: b510 push {r4, lr} + 80001fa: 4c05 ldr r4, [pc, #20] ; (8000210 <__do_global_dtors_aux+0x18>) + 80001fc: 7823 ldrb r3, [r4, #0] + 80001fe: b933 cbnz r3, 800020e <__do_global_dtors_aux+0x16> + 8000200: 4b04 ldr r3, [pc, #16] ; (8000214 <__do_global_dtors_aux+0x1c>) + 8000202: b113 cbz r3, 800020a <__do_global_dtors_aux+0x12> + 8000204: 4804 ldr r0, [pc, #16] ; (8000218 <__do_global_dtors_aux+0x20>) + 8000206: f3af 8000 nop.w + 800020a: 2301 movs r3, #1 + 800020c: 7023 strb r3, [r4, #0] + 800020e: bd10 pop {r4, pc} + 8000210: 20000010 .word 0x20000010 + 8000214: 00000000 .word 0x00000000 + 8000218: 080055c0 .word 0x080055c0 + +0800021c : + 800021c: b508 push {r3, lr} + 800021e: 4b03 ldr r3, [pc, #12] ; (800022c ) + 8000220: b11b cbz r3, 800022a + 8000222: 4903 ldr r1, [pc, #12] ; (8000230 ) + 8000224: 4803 ldr r0, [pc, #12] ; (8000234 ) + 8000226: f3af 8000 nop.w + 800022a: bd08 pop {r3, pc} + 800022c: 00000000 .word 0x00000000 + 8000230: 20000014 .word 0x20000014 + 8000234: 080055c0 .word 0x080055c0 + +08000238 <__aeabi_uldivmod>: + 8000238: b953 cbnz r3, 8000250 <__aeabi_uldivmod+0x18> + 800023a: b94a cbnz r2, 8000250 <__aeabi_uldivmod+0x18> + 800023c: 2900 cmp r1, #0 + 800023e: bf08 it eq + 8000240: 2800 cmpeq r0, #0 + 8000242: bf1c itt ne + 8000244: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff + 8000248: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff + 800024c: f000 b972 b.w 8000534 <__aeabi_idiv0> + 8000250: f1ad 0c08 sub.w ip, sp, #8 + 8000254: e96d ce04 strd ip, lr, [sp, #-16]! + 8000258: f000 f806 bl 8000268 <__udivmoddi4> + 800025c: f8dd e004 ldr.w lr, [sp, #4] + 8000260: e9dd 2302 ldrd r2, r3, [sp, #8] + 8000264: b004 add sp, #16 + 8000266: 4770 bx lr + +08000268 <__udivmoddi4>: + 8000268: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800026c: 9e08 ldr r6, [sp, #32] + 800026e: 4604 mov r4, r0 + 8000270: 4688 mov r8, r1 + 8000272: 2b00 cmp r3, #0 + 8000274: d14b bne.n 800030e <__udivmoddi4+0xa6> + 8000276: 428a cmp r2, r1 + 8000278: 4615 mov r5, r2 + 800027a: d967 bls.n 800034c <__udivmoddi4+0xe4> + 800027c: fab2 f282 clz r2, r2 + 8000280: b14a cbz r2, 8000296 <__udivmoddi4+0x2e> + 8000282: f1c2 0720 rsb r7, r2, #32 + 8000286: fa01 f302 lsl.w r3, r1, r2 + 800028a: fa20 f707 lsr.w r7, r0, r7 + 800028e: 4095 lsls r5, r2 + 8000290: ea47 0803 orr.w r8, r7, r3 + 8000294: 4094 lsls r4, r2 + 8000296: ea4f 4e15 mov.w lr, r5, lsr #16 + 800029a: 0c23 lsrs r3, r4, #16 + 800029c: fbb8 f7fe udiv r7, r8, lr + 80002a0: fa1f fc85 uxth.w ip, r5 + 80002a4: fb0e 8817 mls r8, lr, r7, r8 + 80002a8: ea43 4308 orr.w r3, r3, r8, lsl #16 + 80002ac: fb07 f10c mul.w r1, r7, ip + 80002b0: 4299 cmp r1, r3 + 80002b2: d909 bls.n 80002c8 <__udivmoddi4+0x60> + 80002b4: 18eb adds r3, r5, r3 + 80002b6: f107 30ff add.w r0, r7, #4294967295 ; 0xffffffff + 80002ba: f080 811b bcs.w 80004f4 <__udivmoddi4+0x28c> + 80002be: 4299 cmp r1, r3 + 80002c0: f240 8118 bls.w 80004f4 <__udivmoddi4+0x28c> + 80002c4: 3f02 subs r7, #2 + 80002c6: 442b add r3, r5 + 80002c8: 1a5b subs r3, r3, r1 + 80002ca: b2a4 uxth r4, r4 + 80002cc: fbb3 f0fe udiv r0, r3, lr + 80002d0: fb0e 3310 mls r3, lr, r0, r3 + 80002d4: ea44 4403 orr.w r4, r4, r3, lsl #16 + 80002d8: fb00 fc0c mul.w ip, r0, ip + 80002dc: 45a4 cmp ip, r4 + 80002de: d909 bls.n 80002f4 <__udivmoddi4+0x8c> + 80002e0: 192c adds r4, r5, r4 + 80002e2: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff + 80002e6: f080 8107 bcs.w 80004f8 <__udivmoddi4+0x290> + 80002ea: 45a4 cmp ip, r4 + 80002ec: f240 8104 bls.w 80004f8 <__udivmoddi4+0x290> + 80002f0: 3802 subs r0, #2 + 80002f2: 442c add r4, r5 + 80002f4: ea40 4007 orr.w r0, r0, r7, lsl #16 + 80002f8: eba4 040c sub.w r4, r4, ip + 80002fc: 2700 movs r7, #0 + 80002fe: b11e cbz r6, 8000308 <__udivmoddi4+0xa0> + 8000300: 40d4 lsrs r4, r2 + 8000302: 2300 movs r3, #0 + 8000304: e9c6 4300 strd r4, r3, [r6] + 8000308: 4639 mov r1, r7 + 800030a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800030e: 428b cmp r3, r1 + 8000310: d909 bls.n 8000326 <__udivmoddi4+0xbe> + 8000312: 2e00 cmp r6, #0 + 8000314: f000 80eb beq.w 80004ee <__udivmoddi4+0x286> + 8000318: 2700 movs r7, #0 + 800031a: e9c6 0100 strd r0, r1, [r6] + 800031e: 4638 mov r0, r7 + 8000320: 4639 mov r1, r7 + 8000322: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000326: fab3 f783 clz r7, r3 + 800032a: 2f00 cmp r7, #0 + 800032c: d147 bne.n 80003be <__udivmoddi4+0x156> + 800032e: 428b cmp r3, r1 + 8000330: d302 bcc.n 8000338 <__udivmoddi4+0xd0> + 8000332: 4282 cmp r2, r0 + 8000334: f200 80fa bhi.w 800052c <__udivmoddi4+0x2c4> + 8000338: 1a84 subs r4, r0, r2 + 800033a: eb61 0303 sbc.w r3, r1, r3 + 800033e: 2001 movs r0, #1 + 8000340: 4698 mov r8, r3 + 8000342: 2e00 cmp r6, #0 + 8000344: d0e0 beq.n 8000308 <__udivmoddi4+0xa0> + 8000346: e9c6 4800 strd r4, r8, [r6] + 800034a: e7dd b.n 8000308 <__udivmoddi4+0xa0> + 800034c: b902 cbnz r2, 8000350 <__udivmoddi4+0xe8> + 800034e: deff udf #255 ; 0xff + 8000350: fab2 f282 clz r2, r2 + 8000354: 2a00 cmp r2, #0 + 8000356: f040 808f bne.w 8000478 <__udivmoddi4+0x210> + 800035a: 1b49 subs r1, r1, r5 + 800035c: ea4f 4e15 mov.w lr, r5, lsr #16 + 8000360: fa1f f885 uxth.w r8, r5 + 8000364: 2701 movs r7, #1 + 8000366: fbb1 fcfe udiv ip, r1, lr + 800036a: 0c23 lsrs r3, r4, #16 + 800036c: fb0e 111c mls r1, lr, ip, r1 + 8000370: ea43 4301 orr.w r3, r3, r1, lsl #16 + 8000374: fb08 f10c mul.w r1, r8, ip + 8000378: 4299 cmp r1, r3 + 800037a: d907 bls.n 800038c <__udivmoddi4+0x124> + 800037c: 18eb adds r3, r5, r3 + 800037e: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff + 8000382: d202 bcs.n 800038a <__udivmoddi4+0x122> + 8000384: 4299 cmp r1, r3 + 8000386: f200 80cd bhi.w 8000524 <__udivmoddi4+0x2bc> + 800038a: 4684 mov ip, r0 + 800038c: 1a59 subs r1, r3, r1 + 800038e: b2a3 uxth r3, r4 + 8000390: fbb1 f0fe udiv r0, r1, lr + 8000394: fb0e 1410 mls r4, lr, r0, r1 + 8000398: ea43 4404 orr.w r4, r3, r4, lsl #16 + 800039c: fb08 f800 mul.w r8, r8, r0 + 80003a0: 45a0 cmp r8, r4 + 80003a2: d907 bls.n 80003b4 <__udivmoddi4+0x14c> + 80003a4: 192c adds r4, r5, r4 + 80003a6: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff + 80003aa: d202 bcs.n 80003b2 <__udivmoddi4+0x14a> + 80003ac: 45a0 cmp r8, r4 + 80003ae: f200 80b6 bhi.w 800051e <__udivmoddi4+0x2b6> + 80003b2: 4618 mov r0, r3 + 80003b4: eba4 0408 sub.w r4, r4, r8 + 80003b8: ea40 400c orr.w r0, r0, ip, lsl #16 + 80003bc: e79f b.n 80002fe <__udivmoddi4+0x96> + 80003be: f1c7 0c20 rsb ip, r7, #32 + 80003c2: 40bb lsls r3, r7 + 80003c4: fa22 fe0c lsr.w lr, r2, ip + 80003c8: ea4e 0e03 orr.w lr, lr, r3 + 80003cc: fa01 f407 lsl.w r4, r1, r7 + 80003d0: fa20 f50c lsr.w r5, r0, ip + 80003d4: fa21 f30c lsr.w r3, r1, ip + 80003d8: ea4f 481e mov.w r8, lr, lsr #16 + 80003dc: 4325 orrs r5, r4 + 80003de: fbb3 f9f8 udiv r9, r3, r8 + 80003e2: 0c2c lsrs r4, r5, #16 + 80003e4: fb08 3319 mls r3, r8, r9, r3 + 80003e8: fa1f fa8e uxth.w sl, lr + 80003ec: ea44 4303 orr.w r3, r4, r3, lsl #16 + 80003f0: fb09 f40a mul.w r4, r9, sl + 80003f4: 429c cmp r4, r3 + 80003f6: fa02 f207 lsl.w r2, r2, r7 + 80003fa: fa00 f107 lsl.w r1, r0, r7 + 80003fe: d90b bls.n 8000418 <__udivmoddi4+0x1b0> + 8000400: eb1e 0303 adds.w r3, lr, r3 + 8000404: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff + 8000408: f080 8087 bcs.w 800051a <__udivmoddi4+0x2b2> + 800040c: 429c cmp r4, r3 + 800040e: f240 8084 bls.w 800051a <__udivmoddi4+0x2b2> + 8000412: f1a9 0902 sub.w r9, r9, #2 + 8000416: 4473 add r3, lr + 8000418: 1b1b subs r3, r3, r4 + 800041a: b2ad uxth r5, r5 + 800041c: fbb3 f0f8 udiv r0, r3, r8 + 8000420: fb08 3310 mls r3, r8, r0, r3 + 8000424: ea45 4403 orr.w r4, r5, r3, lsl #16 + 8000428: fb00 fa0a mul.w sl, r0, sl + 800042c: 45a2 cmp sl, r4 + 800042e: d908 bls.n 8000442 <__udivmoddi4+0x1da> + 8000430: eb1e 0404 adds.w r4, lr, r4 + 8000434: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff + 8000438: d26b bcs.n 8000512 <__udivmoddi4+0x2aa> + 800043a: 45a2 cmp sl, r4 + 800043c: d969 bls.n 8000512 <__udivmoddi4+0x2aa> + 800043e: 3802 subs r0, #2 + 8000440: 4474 add r4, lr + 8000442: ea40 4009 orr.w r0, r0, r9, lsl #16 + 8000446: fba0 8902 umull r8, r9, r0, r2 + 800044a: eba4 040a sub.w r4, r4, sl + 800044e: 454c cmp r4, r9 + 8000450: 46c2 mov sl, r8 + 8000452: 464b mov r3, r9 + 8000454: d354 bcc.n 8000500 <__udivmoddi4+0x298> + 8000456: d051 beq.n 80004fc <__udivmoddi4+0x294> + 8000458: 2e00 cmp r6, #0 + 800045a: d069 beq.n 8000530 <__udivmoddi4+0x2c8> + 800045c: ebb1 050a subs.w r5, r1, sl + 8000460: eb64 0403 sbc.w r4, r4, r3 + 8000464: fa04 fc0c lsl.w ip, r4, ip + 8000468: 40fd lsrs r5, r7 + 800046a: 40fc lsrs r4, r7 + 800046c: ea4c 0505 orr.w r5, ip, r5 + 8000470: e9c6 5400 strd r5, r4, [r6] + 8000474: 2700 movs r7, #0 + 8000476: e747 b.n 8000308 <__udivmoddi4+0xa0> + 8000478: f1c2 0320 rsb r3, r2, #32 + 800047c: fa20 f703 lsr.w r7, r0, r3 + 8000480: 4095 lsls r5, r2 + 8000482: fa01 f002 lsl.w r0, r1, r2 + 8000486: fa21 f303 lsr.w r3, r1, r3 + 800048a: ea4f 4e15 mov.w lr, r5, lsr #16 + 800048e: 4338 orrs r0, r7 + 8000490: 0c01 lsrs r1, r0, #16 + 8000492: fbb3 f7fe udiv r7, r3, lr + 8000496: fa1f f885 uxth.w r8, r5 + 800049a: fb0e 3317 mls r3, lr, r7, r3 + 800049e: ea41 4103 orr.w r1, r1, r3, lsl #16 + 80004a2: fb07 f308 mul.w r3, r7, r8 + 80004a6: 428b cmp r3, r1 + 80004a8: fa04 f402 lsl.w r4, r4, r2 + 80004ac: d907 bls.n 80004be <__udivmoddi4+0x256> + 80004ae: 1869 adds r1, r5, r1 + 80004b0: f107 3cff add.w ip, r7, #4294967295 ; 0xffffffff + 80004b4: d22f bcs.n 8000516 <__udivmoddi4+0x2ae> + 80004b6: 428b cmp r3, r1 + 80004b8: d92d bls.n 8000516 <__udivmoddi4+0x2ae> + 80004ba: 3f02 subs r7, #2 + 80004bc: 4429 add r1, r5 + 80004be: 1acb subs r3, r1, r3 + 80004c0: b281 uxth r1, r0 + 80004c2: fbb3 f0fe udiv r0, r3, lr + 80004c6: fb0e 3310 mls r3, lr, r0, r3 + 80004ca: ea41 4103 orr.w r1, r1, r3, lsl #16 + 80004ce: fb00 f308 mul.w r3, r0, r8 + 80004d2: 428b cmp r3, r1 + 80004d4: d907 bls.n 80004e6 <__udivmoddi4+0x27e> + 80004d6: 1869 adds r1, r5, r1 + 80004d8: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff + 80004dc: d217 bcs.n 800050e <__udivmoddi4+0x2a6> + 80004de: 428b cmp r3, r1 + 80004e0: d915 bls.n 800050e <__udivmoddi4+0x2a6> + 80004e2: 3802 subs r0, #2 + 80004e4: 4429 add r1, r5 + 80004e6: 1ac9 subs r1, r1, r3 + 80004e8: ea40 4707 orr.w r7, r0, r7, lsl #16 + 80004ec: e73b b.n 8000366 <__udivmoddi4+0xfe> + 80004ee: 4637 mov r7, r6 + 80004f0: 4630 mov r0, r6 + 80004f2: e709 b.n 8000308 <__udivmoddi4+0xa0> + 80004f4: 4607 mov r7, r0 + 80004f6: e6e7 b.n 80002c8 <__udivmoddi4+0x60> + 80004f8: 4618 mov r0, r3 + 80004fa: e6fb b.n 80002f4 <__udivmoddi4+0x8c> + 80004fc: 4541 cmp r1, r8 + 80004fe: d2ab bcs.n 8000458 <__udivmoddi4+0x1f0> + 8000500: ebb8 0a02 subs.w sl, r8, r2 + 8000504: eb69 020e sbc.w r2, r9, lr + 8000508: 3801 subs r0, #1 + 800050a: 4613 mov r3, r2 + 800050c: e7a4 b.n 8000458 <__udivmoddi4+0x1f0> + 800050e: 4660 mov r0, ip + 8000510: e7e9 b.n 80004e6 <__udivmoddi4+0x27e> + 8000512: 4618 mov r0, r3 + 8000514: e795 b.n 8000442 <__udivmoddi4+0x1da> + 8000516: 4667 mov r7, ip + 8000518: e7d1 b.n 80004be <__udivmoddi4+0x256> + 800051a: 4681 mov r9, r0 + 800051c: e77c b.n 8000418 <__udivmoddi4+0x1b0> + 800051e: 3802 subs r0, #2 + 8000520: 442c add r4, r5 + 8000522: e747 b.n 80003b4 <__udivmoddi4+0x14c> + 8000524: f1ac 0c02 sub.w ip, ip, #2 + 8000528: 442b add r3, r5 + 800052a: e72f b.n 800038c <__udivmoddi4+0x124> + 800052c: 4638 mov r0, r7 + 800052e: e708 b.n 8000342 <__udivmoddi4+0xda> + 8000530: 4637 mov r7, r6 + 8000532: e6e9 b.n 8000308 <__udivmoddi4+0xa0> + +08000534 <__aeabi_idiv0>: + 8000534: 4770 bx lr + 8000536: bf00 nop + +08000538 <_ZN7Encoder8GetCountEv>: + + Encoder(TIM_HandleTypeDef *timer, float wheel_circ); + + void Setup(); + + int GetCount() { + 8000538: b480 push {r7} + 800053a: b085 sub sp, #20 + 800053c: af00 add r7, sp, #0 + 800053e: 6078 str r0, [r7, #4] + int count = ((int) __HAL_TIM_GET_COUNTER(this->timer_) + 8000540: 687b ldr r3, [r7, #4] + 8000542: 681b ldr r3, [r3, #0] + 8000544: 681b ldr r3, [r3, #0] + 8000546: 6a5a ldr r2, [r3, #36] ; 0x24 + - ((this->timer_->Init.Period) / 2)); + 8000548: 687b ldr r3, [r7, #4] + 800054a: 681b ldr r3, [r3, #0] + 800054c: 68db ldr r3, [r3, #12] + 800054e: 085b lsrs r3, r3, #1 + 8000550: 1ad3 subs r3, r2, r3 + 8000552: 60fb str r3, [r7, #12] + return count; + 8000554: 68fb ldr r3, [r7, #12] + } + 8000556: 4618 mov r0, r3 + 8000558: 3714 adds r7, #20 + 800055a: 46bd mov sp, r7 + 800055c: f85d 7b04 ldr.w r7, [sp], #4 + 8000560: 4770 bx lr + +08000562 <_ZN7Encoder10ResetCountEv>: + + void ResetCount() { + 8000562: b480 push {r7} + 8000564: b083 sub sp, #12 + 8000566: af00 add r7, sp, #0 + 8000568: 6078 str r0, [r7, #4] + //set counter to half its maximum value + __HAL_TIM_SET_COUNTER(timer_, (timer_->Init.Period) / 2); + 800056a: 687b ldr r3, [r7, #4] + 800056c: 681b ldr r3, [r3, #0] + 800056e: 68da ldr r2, [r3, #12] + 8000570: 687b ldr r3, [r7, #4] + 8000572: 681b ldr r3, [r3, #0] + 8000574: 681b ldr r3, [r3, #0] + 8000576: 0852 lsrs r2, r2, #1 + 8000578: 625a str r2, [r3, #36] ; 0x24 + } + 800057a: bf00 nop + 800057c: 370c adds r7, #12 + 800057e: 46bd mov sp, r7 + 8000580: f85d 7b04 ldr.w r7, [sp], #4 + 8000584: 4770 bx lr + +08000586 <_ZN7EncoderC1EP17TIM_HandleTypeDeff>: +#include "encoder.h" + +Encoder::Encoder(TIM_HandleTypeDef *timer, float wheel_circ) { + 8000586: b480 push {r7} + 8000588: b085 sub sp, #20 + 800058a: af00 add r7, sp, #0 + 800058c: 60f8 str r0, [r7, #12] + 800058e: 60b9 str r1, [r7, #8] + 8000590: ed87 0a01 vstr s0, [r7, #4] + timer_ = timer; + 8000594: 68fb ldr r3, [r7, #12] + 8000596: 68ba ldr r2, [r7, #8] + 8000598: 601a str r2, [r3, #0] + wheel_circumference_ = wheel_circ; + 800059a: 68fb ldr r3, [r7, #12] + 800059c: 687a ldr r2, [r7, #4] + 800059e: 611a str r2, [r3, #16] +} + 80005a0: 68fb ldr r3, [r7, #12] + 80005a2: 4618 mov r0, r3 + 80005a4: 3714 adds r7, #20 + 80005a6: 46bd mov sp, r7 + 80005a8: f85d 7b04 ldr.w r7, [sp], #4 + 80005ac: 4770 bx lr + +080005ae <_ZN7Encoder5SetupEv>: + +void Encoder::Setup() { + 80005ae: b580 push {r7, lr} + 80005b0: b082 sub sp, #8 + 80005b2: af00 add r7, sp, #0 + 80005b4: 6078 str r0, [r7, #4] + HAL_TIM_Encoder_Start(timer_, TIM_CHANNEL_ALL); + 80005b6: 687b ldr r3, [r7, #4] + 80005b8: 681b ldr r3, [r3, #0] + 80005ba: 213c movs r1, #60 ; 0x3c + 80005bc: 4618 mov r0, r3 + 80005be: f003 f8e7 bl 8003790 + this->ResetCount(); + 80005c2: 6878 ldr r0, [r7, #4] + 80005c4: f7ff ffcd bl 8000562 <_ZN7Encoder10ResetCountEv> + this->previous_millis_ = 0; + 80005c8: 687b ldr r3, [r7, #4] + 80005ca: 2200 movs r2, #0 + 80005cc: 605a str r2, [r3, #4] + this->current_millis_ = HAL_GetTick(); + 80005ce: f001 fbfb bl 8001dc8 + 80005d2: 4602 mov r2, r0 + 80005d4: 687b ldr r3, [r7, #4] + 80005d6: 609a str r2, [r3, #8] +} + 80005d8: bf00 nop + 80005da: 3708 adds r7, #8 + 80005dc: 46bd mov sp, r7 + 80005de: bd80 pop {r7, pc} + +080005e0 <_ZN7Encoder12UpdateValuesEv>: + +void Encoder::UpdateValues() { + 80005e0: b580 push {r7, lr} + 80005e2: b082 sub sp, #8 + 80005e4: af00 add r7, sp, #0 + 80005e6: 6078 str r0, [r7, #4] + this->previous_millis_ = this->current_millis_; + 80005e8: 687b ldr r3, [r7, #4] + 80005ea: 689a ldr r2, [r3, #8] + 80005ec: 687b ldr r3, [r7, #4] + 80005ee: 605a str r2, [r3, #4] + this->current_millis_ = HAL_GetTick(); + 80005f0: f001 fbea bl 8001dc8 + 80005f4: 4602 mov r2, r0 + 80005f6: 687b ldr r3, [r7, #4] + 80005f8: 609a str r2, [r3, #8] + this->ticks_ = this->GetCount(); + 80005fa: 6878 ldr r0, [r7, #4] + 80005fc: f7ff ff9c bl 8000538 <_ZN7Encoder8GetCountEv> + 8000600: 4602 mov r2, r0 + 8000602: 687b ldr r3, [r7, #4] + 8000604: 60da str r2, [r3, #12] + this->ResetCount(); + 8000606: 6878 ldr r0, [r7, #4] + 8000608: f7ff ffab bl 8000562 <_ZN7Encoder10ResetCountEv> +} + 800060c: bf00 nop + 800060e: 3708 adds r7, #8 + 8000610: 46bd mov sp, r7 + 8000612: bd80 pop {r7, pc} + +08000614 <_ZN7Encoder17GetLinearVelocityEv>: + float meters = ((float) this->ticks_ * this->wheel_circumference_) + / TICKS_PER_REVOLUTION; + return meters; +} + +float Encoder::GetLinearVelocity() { + 8000614: b580 push {r7, lr} + 8000616: b086 sub sp, #24 + 8000618: af00 add r7, sp, #0 + 800061a: 6078 str r0, [r7, #4] + this->UpdateValues(); + 800061c: 6878 ldr r0, [r7, #4] + 800061e: f7ff ffdf bl 80005e0 <_ZN7Encoder12UpdateValuesEv> + float meters = ((float) this->ticks_ * this->wheel_circumference_) + 8000622: 687b ldr r3, [r7, #4] + 8000624: 68db ldr r3, [r3, #12] + 8000626: ee07 3a90 vmov s15, r3 + 800062a: eeb8 7ae7 vcvt.f32.s32 s14, s15 + 800062e: 687b ldr r3, [r7, #4] + 8000630: edd3 7a04 vldr s15, [r3, #16] + 8000634: ee27 7a27 vmul.f32 s14, s14, s15 + 8000638: eddf 6a17 vldr s13, [pc, #92] ; 8000698 <_ZN7Encoder17GetLinearVelocityEv+0x84> + 800063c: eec7 7a26 vdiv.f32 s15, s14, s13 + 8000640: edc7 7a05 vstr s15, [r7, #20] + / TICKS_PER_REVOLUTION; + float deltaTime = this->current_millis_ - this->previous_millis_; + 8000644: 687b ldr r3, [r7, #4] + 8000646: 689a ldr r2, [r3, #8] + 8000648: 687b ldr r3, [r7, #4] + 800064a: 685b ldr r3, [r3, #4] + 800064c: 1ad3 subs r3, r2, r3 + 800064e: ee07 3a90 vmov s15, r3 + 8000652: eef8 7a67 vcvt.f32.u32 s15, s15 + 8000656: edc7 7a04 vstr s15, [r7, #16] + if (deltaTime == 0) + 800065a: edd7 7a04 vldr s15, [r7, #16] + 800065e: eef5 7a40 vcmp.f32 s15, #0.0 + 8000662: eef1 fa10 vmrs APSR_nzcv, fpscr + 8000666: d102 bne.n 800066e <_ZN7Encoder17GetLinearVelocityEv+0x5a> + return 0; + 8000668: f04f 0300 mov.w r3, #0 + 800066c: e00c b.n 8000688 <_ZN7Encoder17GetLinearVelocityEv+0x74> + float linear_velocity = (meters / (deltaTime / 1000)); + 800066e: edd7 7a04 vldr s15, [r7, #16] + 8000672: eddf 6a0a vldr s13, [pc, #40] ; 800069c <_ZN7Encoder17GetLinearVelocityEv+0x88> + 8000676: ee87 7aa6 vdiv.f32 s14, s15, s13 + 800067a: edd7 6a05 vldr s13, [r7, #20] + 800067e: eec6 7a87 vdiv.f32 s15, s13, s14 + 8000682: edc7 7a03 vstr s15, [r7, #12] + return linear_velocity; + 8000686: 68fb ldr r3, [r7, #12] + 8000688: ee07 3a90 vmov s15, r3 +} + 800068c: eeb0 0a67 vmov.f32 s0, s15 + 8000690: 3718 adds r7, #24 + 8000692: 46bd mov sp, r7 + 8000694: bd80 pop {r7, pc} + 8000696: bf00 nop + 8000698: 48108800 .word 0x48108800 + 800069c: 447a0000 .word 0x447a0000 + +080006a0 <_ZN8OdometryC1Ev>: + float left_velocity_; + float right_velocity_; + + + public: + Odometry() { + 80006a0: b480 push {r7} + 80006a2: b083 sub sp, #12 + 80006a4: af00 add r7, sp, #0 + 80006a6: 6078 str r0, [r7, #4] + left_velocity_ = 0; + 80006a8: 687b ldr r3, [r7, #4] + 80006aa: f04f 0200 mov.w r2, #0 + 80006ae: 601a str r2, [r3, #0] + right_velocity_ = 0; + 80006b0: 687b ldr r3, [r7, #4] + 80006b2: f04f 0200 mov.w r2, #0 + 80006b6: 605a str r2, [r3, #4] + } + 80006b8: 687b ldr r3, [r7, #4] + 80006ba: 4618 mov r0, r3 + 80006bc: 370c adds r7, #12 + 80006be: 46bd mov sp, r7 + 80006c0: f85d 7b04 ldr.w r7, [sp], #4 + 80006c4: 4770 bx lr + ... + +080006c8 <_ZN8Odometry12UpdateValuesEff>: + + void UpdateValues(float linear_vel, float angular_vel) { + 80006c8: b480 push {r7} + 80006ca: b085 sub sp, #20 + 80006cc: af00 add r7, sp, #0 + 80006ce: 60f8 str r0, [r7, #12] + 80006d0: ed87 0a02 vstr s0, [r7, #8] + 80006d4: edc7 0a01 vstr s1, [r7, #4] + left_velocity_ = linear_vel - (BASELINE * angular_vel)/2; + 80006d8: edd7 7a02 vldr s15, [r7, #8] + 80006dc: eeb7 6ae7 vcvt.f64.f32 d6, s15 + 80006e0: edd7 7a01 vldr s15, [r7, #4] + 80006e4: eeb7 7ae7 vcvt.f64.f32 d7, s15 + 80006e8: ed9f 5b11 vldr d5, [pc, #68] ; 8000730 <_ZN8Odometry12UpdateValuesEff+0x68> + 80006ec: ee27 5b05 vmul.f64 d5, d7, d5 + 80006f0: eeb0 4b00 vmov.f64 d4, #0 ; 0x40000000 2.0 + 80006f4: ee85 7b04 vdiv.f64 d7, d5, d4 + 80006f8: ee36 7b47 vsub.f64 d7, d6, d7 + 80006fc: eef7 7bc7 vcvt.f32.f64 s15, d7 + 8000700: 68fb ldr r3, [r7, #12] + 8000702: edc3 7a00 vstr s15, [r3] + right_velocity_ = 2 * linear_vel - left_velocity_; + 8000706: edd7 7a02 vldr s15, [r7, #8] + 800070a: ee37 7aa7 vadd.f32 s14, s15, s15 + 800070e: 68fb ldr r3, [r7, #12] + 8000710: edd3 7a00 vldr s15, [r3] + 8000714: ee77 7a67 vsub.f32 s15, s14, s15 + 8000718: 68fb ldr r3, [r7, #12] + 800071a: edc3 7a01 vstr s15, [r3, #4] + } + 800071e: bf00 nop + 8000720: 3714 adds r7, #20 + 8000722: 46bd mov sp, r7 + 8000724: f85d 7b04 ldr.w r7, [sp], #4 + 8000728: 4770 bx lr + 800072a: bf00 nop + 800072c: f3af 8000 nop.w + 8000730: 33333333 .word 0x33333333 + 8000734: 3fd33333 .word 0x3fd33333 + +08000738 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>: + GPIO_TypeDef *dir_gpio_port_; + uint16_t dir_pin_; + TIM_HandleTypeDef *pwm_timer_; + uint32_t pwm_channel_; + + MotorController(GPIO_TypeDef *sleep_gpio_port, uint16_t sleep_pin, + 8000738: b480 push {r7} + 800073a: b085 sub sp, #20 + 800073c: af00 add r7, sp, #0 + 800073e: 60f8 str r0, [r7, #12] + 8000740: 60b9 str r1, [r7, #8] + 8000742: 603b str r3, [r7, #0] + 8000744: 4613 mov r3, r2 + 8000746: 80fb strh r3, [r7, #6] + GPIO_TypeDef *dir_gpio_port, uint16_t dir_pin, + TIM_HandleTypeDef *pwm_timer, uint32_t pwm_channel) { + this->sleep_gpio_port_ = sleep_gpio_port; + 8000748: 68fb ldr r3, [r7, #12] + 800074a: 68ba ldr r2, [r7, #8] + 800074c: 601a str r2, [r3, #0] + this->sleep_pin_ = sleep_pin; + 800074e: 68fb ldr r3, [r7, #12] + 8000750: 88fa ldrh r2, [r7, #6] + 8000752: 809a strh r2, [r3, #4] + this->dir_gpio_port_ = dir_gpio_port; + 8000754: 68fb ldr r3, [r7, #12] + 8000756: 683a ldr r2, [r7, #0] + 8000758: 609a str r2, [r3, #8] + this->dir_pin_ = dir_pin; + 800075a: 68fb ldr r3, [r7, #12] + 800075c: 8b3a ldrh r2, [r7, #24] + 800075e: 819a strh r2, [r3, #12] + this->pwm_timer_ = pwm_timer; + 8000760: 68fb ldr r3, [r7, #12] + 8000762: 69fa ldr r2, [r7, #28] + 8000764: 611a str r2, [r3, #16] + this->pwm_channel_ = pwm_channel; + 8000766: 68fb ldr r3, [r7, #12] + 8000768: 6a3a ldr r2, [r7, #32] + 800076a: 615a str r2, [r3, #20] + } + 800076c: 68fb ldr r3, [r7, #12] + 800076e: 4618 mov r0, r3 + 8000770: 3714 adds r7, #20 + 8000772: 46bd mov sp, r7 + 8000774: f85d 7b04 ldr.w r7, [sp], #4 + 8000778: 4770 bx lr + +0800077a <_ZN15MotorController5setupEv>: + + void setup() { + 800077a: b580 push {r7, lr} + 800077c: b082 sub sp, #8 + 800077e: af00 add r7, sp, #0 + 8000780: 6078 str r0, [r7, #4] + HAL_TIM_PWM_Start(pwm_timer_, pwm_channel_); + 8000782: 687b ldr r3, [r7, #4] + 8000784: 691a ldr r2, [r3, #16] + 8000786: 687b ldr r3, [r7, #4] + 8000788: 695b ldr r3, [r3, #20] + 800078a: 4619 mov r1, r3 + 800078c: 4610 mov r0, r2 + 800078e: f002 ff29 bl 80035e4 + } + 8000792: bf00 nop + 8000794: 3708 adds r7, #8 + 8000796: 46bd mov sp, r7 + 8000798: bd80 pop {r7, pc} + ... + +0800079c <_ZN15MotorController9set_speedEi>: + + void set_speed(int duty_cycle) { + 800079c: b580 push {r7, lr} + 800079e: b082 sub sp, #8 + 80007a0: af00 add r7, sp, #0 + 80007a2: 6078 str r0, [r7, #4] + 80007a4: 6039 str r1, [r7, #0] + if (duty_cycle >= 0) { + 80007a6: 683b ldr r3, [r7, #0] + 80007a8: 2b00 cmp r3, #0 + 80007aa: f2c0 8083 blt.w 80008b4 <_ZN15MotorController9set_speedEi+0x118> + //set direction to forward + HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_SET); + 80007ae: 687b ldr r3, [r7, #4] + 80007b0: 6898 ldr r0, [r3, #8] + 80007b2: 687b ldr r3, [r7, #4] + 80007b4: 899b ldrh r3, [r3, #12] + 80007b6: 2201 movs r2, #1 + 80007b8: 4619 mov r1, r3 + 80007ba: f001 fdef bl 800239c + + //check if duty_cycle exceeds maximum + if (duty_cycle > MAX_DUTY_CYCLE) + 80007be: 683b ldr r3, [r7, #0] + 80007c0: f240 3216 movw r2, #790 ; 0x316 + 80007c4: 4293 cmp r3, r2 + 80007c6: dd3d ble.n 8000844 <_ZN15MotorController9set_speedEi+0xa8> + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, MAX_DUTY_CYCLE); + 80007c8: 687b ldr r3, [r7, #4] + 80007ca: 695b ldr r3, [r3, #20] + 80007cc: 2b00 cmp r3, #0 + 80007ce: d106 bne.n 80007de <_ZN15MotorController9set_speedEi+0x42> + 80007d0: 687b ldr r3, [r7, #4] + 80007d2: 691b ldr r3, [r3, #16] + 80007d4: 681b ldr r3, [r3, #0] + 80007d6: f240 3216 movw r2, #790 ; 0x316 + 80007da: 635a str r2, [r3, #52] ; 0x34 + 80007dc: e0f5 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 80007de: 687b ldr r3, [r7, #4] + 80007e0: 695b ldr r3, [r3, #20] + 80007e2: 2b04 cmp r3, #4 + 80007e4: d106 bne.n 80007f4 <_ZN15MotorController9set_speedEi+0x58> + 80007e6: 687b ldr r3, [r7, #4] + 80007e8: 691b ldr r3, [r3, #16] + 80007ea: 681b ldr r3, [r3, #0] + 80007ec: f240 3216 movw r2, #790 ; 0x316 + 80007f0: 639a str r2, [r3, #56] ; 0x38 + 80007f2: e0ea b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 80007f4: 687b ldr r3, [r7, #4] + 80007f6: 695b ldr r3, [r3, #20] + 80007f8: 2b08 cmp r3, #8 + 80007fa: d106 bne.n 800080a <_ZN15MotorController9set_speedEi+0x6e> + 80007fc: 687b ldr r3, [r7, #4] + 80007fe: 691b ldr r3, [r3, #16] + 8000800: 681b ldr r3, [r3, #0] + 8000802: f240 3216 movw r2, #790 ; 0x316 + 8000806: 63da str r2, [r3, #60] ; 0x3c + 8000808: e0df b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 800080a: 687b ldr r3, [r7, #4] + 800080c: 695b ldr r3, [r3, #20] + 800080e: 2b0c cmp r3, #12 + 8000810: d106 bne.n 8000820 <_ZN15MotorController9set_speedEi+0x84> + 8000812: 687b ldr r3, [r7, #4] + 8000814: 691b ldr r3, [r3, #16] + 8000816: 681b ldr r3, [r3, #0] + 8000818: f240 3216 movw r2, #790 ; 0x316 + 800081c: 641a str r2, [r3, #64] ; 0x40 + 800081e: e0d4 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 8000820: 687b ldr r3, [r7, #4] + 8000822: 695b ldr r3, [r3, #20] + 8000824: 2b10 cmp r3, #16 + 8000826: d106 bne.n 8000836 <_ZN15MotorController9set_speedEi+0x9a> + 8000828: 687b ldr r3, [r7, #4] + 800082a: 691b ldr r3, [r3, #16] + 800082c: 681b ldr r3, [r3, #0] + 800082e: f240 3216 movw r2, #790 ; 0x316 + 8000832: 659a str r2, [r3, #88] ; 0x58 + 8000834: e0c9 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 8000836: 687b ldr r3, [r7, #4] + 8000838: 691b ldr r3, [r3, #16] + 800083a: 681b ldr r3, [r3, #0] + 800083c: f240 3216 movw r2, #790 ; 0x316 + 8000840: 65da str r2, [r3, #92] ; 0x5c + 8000842: e0c2 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + else + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle); + 8000844: 687b ldr r3, [r7, #4] + 8000846: 695b ldr r3, [r3, #20] + 8000848: 2b00 cmp r3, #0 + 800084a: d105 bne.n 8000858 <_ZN15MotorController9set_speedEi+0xbc> + 800084c: 683a ldr r2, [r7, #0] + 800084e: 687b ldr r3, [r7, #4] + 8000850: 691b ldr r3, [r3, #16] + 8000852: 681b ldr r3, [r3, #0] + 8000854: 635a str r2, [r3, #52] ; 0x34 + 8000856: e0b8 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 8000858: 687b ldr r3, [r7, #4] + 800085a: 695b ldr r3, [r3, #20] + 800085c: 2b04 cmp r3, #4 + 800085e: d105 bne.n 800086c <_ZN15MotorController9set_speedEi+0xd0> + 8000860: 683a ldr r2, [r7, #0] + 8000862: 687b ldr r3, [r7, #4] + 8000864: 691b ldr r3, [r3, #16] + 8000866: 681b ldr r3, [r3, #0] + 8000868: 639a str r2, [r3, #56] ; 0x38 + 800086a: e0ae b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 800086c: 687b ldr r3, [r7, #4] + 800086e: 695b ldr r3, [r3, #20] + 8000870: 2b08 cmp r3, #8 + 8000872: d105 bne.n 8000880 <_ZN15MotorController9set_speedEi+0xe4> + 8000874: 683a ldr r2, [r7, #0] + 8000876: 687b ldr r3, [r7, #4] + 8000878: 691b ldr r3, [r3, #16] + 800087a: 681b ldr r3, [r3, #0] + 800087c: 63da str r2, [r3, #60] ; 0x3c + 800087e: e0a4 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 8000880: 687b ldr r3, [r7, #4] + 8000882: 695b ldr r3, [r3, #20] + 8000884: 2b0c cmp r3, #12 + 8000886: d105 bne.n 8000894 <_ZN15MotorController9set_speedEi+0xf8> + 8000888: 683a ldr r2, [r7, #0] + 800088a: 687b ldr r3, [r7, #4] + 800088c: 691b ldr r3, [r3, #16] + 800088e: 681b ldr r3, [r3, #0] + 8000890: 641a str r2, [r3, #64] ; 0x40 + 8000892: e09a b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 8000894: 687b ldr r3, [r7, #4] + 8000896: 695b ldr r3, [r3, #20] + 8000898: 2b10 cmp r3, #16 + 800089a: d105 bne.n 80008a8 <_ZN15MotorController9set_speedEi+0x10c> + 800089c: 683a ldr r2, [r7, #0] + 800089e: 687b ldr r3, [r7, #4] + 80008a0: 691b ldr r3, [r3, #16] + 80008a2: 681b ldr r3, [r3, #0] + 80008a4: 659a str r2, [r3, #88] ; 0x58 + 80008a6: e090 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 80008a8: 683a ldr r2, [r7, #0] + 80008aa: 687b ldr r3, [r7, #4] + 80008ac: 691b ldr r3, [r3, #16] + 80008ae: 681b ldr r3, [r3, #0] + 80008b0: 65da str r2, [r3, #92] ; 0x5c + 80008b2: e08a b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + + } else if (duty_cycle < 0){ + 80008b4: 683b ldr r3, [r7, #0] + 80008b6: 2b00 cmp r3, #0 + 80008b8: f280 8087 bge.w 80009ca <_ZN15MotorController9set_speedEi+0x22e> + //set direction to backwards + HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_RESET); + 80008bc: 687b ldr r3, [r7, #4] + 80008be: 6898 ldr r0, [r3, #8] + 80008c0: 687b ldr r3, [r7, #4] + 80008c2: 899b ldrh r3, [r3, #12] + 80008c4: 2200 movs r2, #0 + 80008c6: 4619 mov r1, r3 + 80008c8: f001 fd68 bl 800239c + + //check if duty_cycle is lower than minimum + if (duty_cycle < -MAX_DUTY_CYCLE) + 80008cc: 683b ldr r3, [r7, #0] + 80008ce: 4a45 ldr r2, [pc, #276] ; (80009e4 <_ZN15MotorController9set_speedEi+0x248>) + 80008d0: 4293 cmp r3, r2 + 80008d2: da3d bge.n 8000950 <_ZN15MotorController9set_speedEi+0x1b4> + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, MAX_DUTY_CYCLE); + 80008d4: 687b ldr r3, [r7, #4] + 80008d6: 695b ldr r3, [r3, #20] + 80008d8: 2b00 cmp r3, #0 + 80008da: d106 bne.n 80008ea <_ZN15MotorController9set_speedEi+0x14e> + 80008dc: 687b ldr r3, [r7, #4] + 80008de: 691b ldr r3, [r3, #16] + 80008e0: 681b ldr r3, [r3, #0] + 80008e2: f240 3216 movw r2, #790 ; 0x316 + 80008e6: 635a str r2, [r3, #52] ; 0x34 + 80008e8: e06f b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 80008ea: 687b ldr r3, [r7, #4] + 80008ec: 695b ldr r3, [r3, #20] + 80008ee: 2b04 cmp r3, #4 + 80008f0: d106 bne.n 8000900 <_ZN15MotorController9set_speedEi+0x164> + 80008f2: 687b ldr r3, [r7, #4] + 80008f4: 691b ldr r3, [r3, #16] + 80008f6: 681b ldr r3, [r3, #0] + 80008f8: f240 3216 movw r2, #790 ; 0x316 + 80008fc: 639a str r2, [r3, #56] ; 0x38 + 80008fe: e064 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 8000900: 687b ldr r3, [r7, #4] + 8000902: 695b ldr r3, [r3, #20] + 8000904: 2b08 cmp r3, #8 + 8000906: d106 bne.n 8000916 <_ZN15MotorController9set_speedEi+0x17a> + 8000908: 687b ldr r3, [r7, #4] + 800090a: 691b ldr r3, [r3, #16] + 800090c: 681b ldr r3, [r3, #0] + 800090e: f240 3216 movw r2, #790 ; 0x316 + 8000912: 63da str r2, [r3, #60] ; 0x3c + 8000914: e059 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 8000916: 687b ldr r3, [r7, #4] + 8000918: 695b ldr r3, [r3, #20] + 800091a: 2b0c cmp r3, #12 + 800091c: d106 bne.n 800092c <_ZN15MotorController9set_speedEi+0x190> + 800091e: 687b ldr r3, [r7, #4] + 8000920: 691b ldr r3, [r3, #16] + 8000922: 681b ldr r3, [r3, #0] + 8000924: f240 3216 movw r2, #790 ; 0x316 + 8000928: 641a str r2, [r3, #64] ; 0x40 + 800092a: e04e b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 800092c: 687b ldr r3, [r7, #4] + 800092e: 695b ldr r3, [r3, #20] + 8000930: 2b10 cmp r3, #16 + 8000932: d106 bne.n 8000942 <_ZN15MotorController9set_speedEi+0x1a6> + 8000934: 687b ldr r3, [r7, #4] + 8000936: 691b ldr r3, [r3, #16] + 8000938: 681b ldr r3, [r3, #0] + 800093a: f240 3216 movw r2, #790 ; 0x316 + 800093e: 659a str r2, [r3, #88] ; 0x58 + 8000940: e043 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 8000942: 687b ldr r3, [r7, #4] + 8000944: 691b ldr r3, [r3, #16] + 8000946: 681b ldr r3, [r3, #0] + 8000948: f240 3216 movw r2, #790 ; 0x316 + 800094c: 65da str r2, [r3, #92] ; 0x5c + 800094e: e03c b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + else + //invert sign to make duty_cycle positive + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle); + 8000950: 687b ldr r3, [r7, #4] + 8000952: 695b ldr r3, [r3, #20] + 8000954: 2b00 cmp r3, #0 + 8000956: d106 bne.n 8000966 <_ZN15MotorController9set_speedEi+0x1ca> + 8000958: 683b ldr r3, [r7, #0] + 800095a: 425a negs r2, r3 + 800095c: 687b ldr r3, [r7, #4] + 800095e: 691b ldr r3, [r3, #16] + 8000960: 681b ldr r3, [r3, #0] + 8000962: 635a str r2, [r3, #52] ; 0x34 + 8000964: e031 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 8000966: 687b ldr r3, [r7, #4] + 8000968: 695b ldr r3, [r3, #20] + 800096a: 2b04 cmp r3, #4 + 800096c: d106 bne.n 800097c <_ZN15MotorController9set_speedEi+0x1e0> + 800096e: 683b ldr r3, [r7, #0] + 8000970: 425a negs r2, r3 + 8000972: 687b ldr r3, [r7, #4] + 8000974: 691b ldr r3, [r3, #16] + 8000976: 681b ldr r3, [r3, #0] + 8000978: 639a str r2, [r3, #56] ; 0x38 + 800097a: e026 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 800097c: 687b ldr r3, [r7, #4] + 800097e: 695b ldr r3, [r3, #20] + 8000980: 2b08 cmp r3, #8 + 8000982: d106 bne.n 8000992 <_ZN15MotorController9set_speedEi+0x1f6> + 8000984: 683b ldr r3, [r7, #0] + 8000986: 425a negs r2, r3 + 8000988: 687b ldr r3, [r7, #4] + 800098a: 691b ldr r3, [r3, #16] + 800098c: 681b ldr r3, [r3, #0] + 800098e: 63da str r2, [r3, #60] ; 0x3c + 8000990: e01b b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 8000992: 687b ldr r3, [r7, #4] + 8000994: 695b ldr r3, [r3, #20] + 8000996: 2b0c cmp r3, #12 + 8000998: d106 bne.n 80009a8 <_ZN15MotorController9set_speedEi+0x20c> + 800099a: 683b ldr r3, [r7, #0] + 800099c: 425a negs r2, r3 + 800099e: 687b ldr r3, [r7, #4] + 80009a0: 691b ldr r3, [r3, #16] + 80009a2: 681b ldr r3, [r3, #0] + 80009a4: 641a str r2, [r3, #64] ; 0x40 + 80009a6: e010 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 80009a8: 687b ldr r3, [r7, #4] + 80009aa: 695b ldr r3, [r3, #20] + 80009ac: 2b10 cmp r3, #16 + 80009ae: d106 bne.n 80009be <_ZN15MotorController9set_speedEi+0x222> + 80009b0: 683b ldr r3, [r7, #0] + 80009b2: 425a negs r2, r3 + 80009b4: 687b ldr r3, [r7, #4] + 80009b6: 691b ldr r3, [r3, #16] + 80009b8: 681b ldr r3, [r3, #0] + 80009ba: 659a str r2, [r3, #88] ; 0x58 + 80009bc: e005 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e> + 80009be: 683b ldr r3, [r7, #0] + 80009c0: 425a negs r2, r3 + 80009c2: 687b ldr r3, [r7, #4] + 80009c4: 691b ldr r3, [r3, #16] + 80009c6: 681b ldr r3, [r3, #0] + 80009c8: 65da str r2, [r3, #92] ; 0x5c + } + + HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET); + 80009ca: 687b ldr r3, [r7, #4] + 80009cc: 6818 ldr r0, [r3, #0] + 80009ce: 687b ldr r3, [r7, #4] + 80009d0: 889b ldrh r3, [r3, #4] + 80009d2: 2201 movs r2, #1 + 80009d4: 4619 mov r1, r3 + 80009d6: f001 fce1 bl 800239c + + } + 80009da: bf00 nop + 80009dc: 3708 adds r7, #8 + 80009de: 46bd mov sp, r7 + 80009e0: bd80 pop {r7, pc} + 80009e2: bf00 nop + 80009e4: fffffcea .word 0xfffffcea + +080009e8 <_ZN15MotorController5coastEv>: + void brake() { + HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET); + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 0); + } + + void coast() { + 80009e8: b580 push {r7, lr} + 80009ea: b082 sub sp, #8 + 80009ec: af00 add r7, sp, #0 + 80009ee: 6078 str r0, [r7, #4] + HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_RESET); + 80009f0: 687b ldr r3, [r7, #4] + 80009f2: 6818 ldr r0, [r3, #0] + 80009f4: 687b ldr r3, [r7, #4] + 80009f6: 889b ldrh r3, [r3, #4] + 80009f8: 2200 movs r2, #0 + 80009fa: 4619 mov r1, r3 + 80009fc: f001 fcce bl 800239c + } + 8000a00: bf00 nop + 8000a02: 3708 adds r7, #8 + 8000a04: 46bd mov sp, r7 + 8000a06: bd80 pop {r7, pc} + +08000a08 <_ZN3PidC1Efff>: + float previous_error_; + + int min_; + int max_; + + Pid(float kp, float ki, float kd) { + 8000a08: b480 push {r7} + 8000a0a: b085 sub sp, #20 + 8000a0c: af00 add r7, sp, #0 + 8000a0e: 60f8 str r0, [r7, #12] + 8000a10: ed87 0a02 vstr s0, [r7, #8] + 8000a14: edc7 0a01 vstr s1, [r7, #4] + 8000a18: ed87 1a00 vstr s2, [r7] + this->kp_ = kp; + 8000a1c: 68fb ldr r3, [r7, #12] + 8000a1e: 68ba ldr r2, [r7, #8] + 8000a20: 601a str r2, [r3, #0] + this->ki_ = ki; + 8000a22: 68fb ldr r3, [r7, #12] + 8000a24: 687a ldr r2, [r7, #4] + 8000a26: 605a str r2, [r3, #4] + this->kd_ = kd; + 8000a28: 68fb ldr r3, [r7, #12] + 8000a2a: 683a ldr r2, [r7, #0] + 8000a2c: 609a str r2, [r3, #8] + + this->error_ = 0; + 8000a2e: 68fb ldr r3, [r7, #12] + 8000a30: f04f 0200 mov.w r2, #0 + 8000a34: 60da str r2, [r3, #12] + this->setpoint_ = 0; + 8000a36: 68fb ldr r3, [r7, #12] + 8000a38: f04f 0200 mov.w r2, #0 + 8000a3c: 611a str r2, [r3, #16] + + this->previous_error_ = 0; + 8000a3e: 68fb ldr r3, [r7, #12] + 8000a40: f04f 0200 mov.w r2, #0 + 8000a44: 619a str r2, [r3, #24] + this->error_sum_ = 0; + 8000a46: 68fb ldr r3, [r7, #12] + 8000a48: f04f 0200 mov.w r2, #0 + 8000a4c: 615a str r2, [r3, #20] + + this->min_ = -MAX_DUTY_CYCLE; + 8000a4e: 68fb ldr r3, [r7, #12] + 8000a50: 4a06 ldr r2, [pc, #24] ; (8000a6c <_ZN3PidC1Efff+0x64>) + 8000a52: 61da str r2, [r3, #28] + this->max_ = MAX_DUTY_CYCLE; + 8000a54: 68fb ldr r3, [r7, #12] + 8000a56: f240 3216 movw r2, #790 ; 0x316 + 8000a5a: 621a str r2, [r3, #32] + + } + 8000a5c: 68fb ldr r3, [r7, #12] + 8000a5e: 4618 mov r0, r3 + 8000a60: 3714 adds r7, #20 + 8000a62: 46bd mov sp, r7 + 8000a64: f85d 7b04 ldr.w r7, [sp], #4 + 8000a68: 4770 bx lr + 8000a6a: bf00 nop + 8000a6c: fffffcea .word 0xfffffcea + +08000a70 <_ZN3Pid6configEfff>: + + void config(float kp, float ki, float kd) { + 8000a70: b480 push {r7} + 8000a72: b085 sub sp, #20 + 8000a74: af00 add r7, sp, #0 + 8000a76: 60f8 str r0, [r7, #12] + 8000a78: ed87 0a02 vstr s0, [r7, #8] + 8000a7c: edc7 0a01 vstr s1, [r7, #4] + 8000a80: ed87 1a00 vstr s2, [r7] + this->kp_ = kp; + 8000a84: 68fb ldr r3, [r7, #12] + 8000a86: 68ba ldr r2, [r7, #8] + 8000a88: 601a str r2, [r3, #0] + this->ki_ = ki; + 8000a8a: 68fb ldr r3, [r7, #12] + 8000a8c: 687a ldr r2, [r7, #4] + 8000a8e: 605a str r2, [r3, #4] + this->kd_ = kd; + 8000a90: 68fb ldr r3, [r7, #12] + 8000a92: 683a ldr r2, [r7, #0] + 8000a94: 609a str r2, [r3, #8] + + this->error_ = 0; + 8000a96: 68fb ldr r3, [r7, #12] + 8000a98: f04f 0200 mov.w r2, #0 + 8000a9c: 60da str r2, [r3, #12] + this->setpoint_ = 0; + 8000a9e: 68fb ldr r3, [r7, #12] + 8000aa0: f04f 0200 mov.w r2, #0 + 8000aa4: 611a str r2, [r3, #16] + + this->previous_error_ = 0; + 8000aa6: 68fb ldr r3, [r7, #12] + 8000aa8: f04f 0200 mov.w r2, #0 + 8000aac: 619a str r2, [r3, #24] + this->error_sum_ = 0; + 8000aae: 68fb ldr r3, [r7, #12] + 8000ab0: f04f 0200 mov.w r2, #0 + 8000ab4: 615a str r2, [r3, #20] + + } + 8000ab6: bf00 nop + 8000ab8: 3714 adds r7, #20 + 8000aba: 46bd mov sp, r7 + 8000abc: f85d 7b04 ldr.w r7, [sp], #4 + 8000ac0: 4770 bx lr + +08000ac2 <_ZN3Pid3setEf>: + + void set(float setpoint) { + 8000ac2: b480 push {r7} + 8000ac4: b083 sub sp, #12 + 8000ac6: af00 add r7, sp, #0 + 8000ac8: 6078 str r0, [r7, #4] + 8000aca: ed87 0a00 vstr s0, [r7] + this->setpoint_ = setpoint; + 8000ace: 687b ldr r3, [r7, #4] + 8000ad0: 683a ldr r2, [r7, #0] + 8000ad2: 611a str r2, [r3, #16] + } + 8000ad4: bf00 nop + 8000ad6: 370c adds r7, #12 + 8000ad8: 46bd mov sp, r7 + 8000ada: f85d 7b04 ldr.w r7, [sp], #4 + 8000ade: 4770 bx lr + +08000ae0 <_ZN3Pid6updateEf>: + + int update(float measure) { + 8000ae0: b480 push {r7} + 8000ae2: b085 sub sp, #20 + 8000ae4: af00 add r7, sp, #0 + 8000ae6: 6078 str r0, [r7, #4] + 8000ae8: ed87 0a00 vstr s0, [r7] + + this->error_ = this->setpoint_ - measure; + 8000aec: 687b ldr r3, [r7, #4] + 8000aee: ed93 7a04 vldr s14, [r3, #16] + 8000af2: edd7 7a00 vldr s15, [r7] + 8000af6: ee77 7a67 vsub.f32 s15, s14, s15 + 8000afa: 687b ldr r3, [r7, #4] + 8000afc: edc3 7a03 vstr s15, [r3, #12] + + //proportional term + float output = this->error_ * this->kp_; + 8000b00: 687b ldr r3, [r7, #4] + 8000b02: ed93 7a03 vldr s14, [r3, #12] + 8000b06: 687b ldr r3, [r7, #4] + 8000b08: edd3 7a00 vldr s15, [r3] + 8000b0c: ee67 7a27 vmul.f32 s15, s14, s15 + 8000b10: edc7 7a03 vstr s15, [r7, #12] + + //integral term without windup + error_sum_ += this->error_; + 8000b14: 687b ldr r3, [r7, #4] + 8000b16: ed93 7a05 vldr s14, [r3, #20] + 8000b1a: 687b ldr r3, [r7, #4] + 8000b1c: edd3 7a03 vldr s15, [r3, #12] + 8000b20: ee77 7a27 vadd.f32 s15, s14, s15 + 8000b24: 687b ldr r3, [r7, #4] + 8000b26: edc3 7a05 vstr s15, [r3, #20] + output += error_sum_ * this->ki_; + 8000b2a: 687b ldr r3, [r7, #4] + 8000b2c: ed93 7a05 vldr s14, [r3, #20] + 8000b30: 687b ldr r3, [r7, #4] + 8000b32: edd3 7a01 vldr s15, [r3, #4] + 8000b36: ee67 7a27 vmul.f32 s15, s14, s15 + 8000b3a: ed97 7a03 vldr s14, [r7, #12] + 8000b3e: ee77 7a27 vadd.f32 s15, s14, s15 + 8000b42: edc7 7a03 vstr s15, [r7, #12] + + //derivative term + output += (this->error_ - this->previous_error_) * kd_; + 8000b46: 687b ldr r3, [r7, #4] + 8000b48: ed93 7a03 vldr s14, [r3, #12] + 8000b4c: 687b ldr r3, [r7, #4] + 8000b4e: edd3 7a06 vldr s15, [r3, #24] + 8000b52: ee37 7a67 vsub.f32 s14, s14, s15 + 8000b56: 687b ldr r3, [r7, #4] + 8000b58: edd3 7a02 vldr s15, [r3, #8] + 8000b5c: ee67 7a27 vmul.f32 s15, s14, s15 + 8000b60: ed97 7a03 vldr s14, [r7, #12] + 8000b64: ee77 7a27 vadd.f32 s15, s14, s15 + 8000b68: edc7 7a03 vstr s15, [r7, #12] + this->previous_error_ = this->error_; + 8000b6c: 687b ldr r3, [r7, #4] + 8000b6e: 68da ldr r2, [r3, #12] + 8000b70: 687b ldr r3, [r7, #4] + 8000b72: 619a str r2, [r3, #24] + + int integer_output = static_cast (output); + 8000b74: edd7 7a03 vldr s15, [r7, #12] + 8000b78: eefd 7ae7 vcvt.s32.f32 s15, s15 + 8000b7c: ee17 3a90 vmov r3, s15 + 8000b80: 60bb str r3, [r7, #8] +// if(integer_output > this->max_) +// integer_output = this->max_; +// else if (integer_output < this->min_) +// integer_output = this->min_; + + return integer_output; + 8000b82: 68bb ldr r3, [r7, #8] + + } + 8000b84: 4618 mov r0, r3 + 8000b86: 3714 adds r7, #20 + 8000b88: 46bd mov sp, r7 + 8000b8a: f85d 7b04 ldr.w r7, [sp], #4 + 8000b8e: 4770 bx lr + +08000b90
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 8000b90: b580 push {r7, lr} + 8000b92: af00 add r7, sp, #0 + + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 8000b94: f001 f8c7 bl 8001d26 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 8000b98: f000 f842 bl 8000c20 <_Z18SystemClock_Configv> + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8000b9c: f000 fb18 bl 80011d0 <_ZL12MX_GPIO_Initv> + MX_TIM2_Init(); + 8000ba0: f000 f8e4 bl 8000d6c <_ZL12MX_TIM2_Initv> + MX_TIM3_Init(); + 8000ba4: f000 f940 bl 8000e28 <_ZL12MX_TIM3_Initv> + MX_TIM4_Init(); + 8000ba8: f000 f99c bl 8000ee4 <_ZL12MX_TIM4_Initv> + MX_TIM5_Init(); + 8000bac: f000 fa3a bl 8001024 <_ZL12MX_TIM5_Initv> + MX_USART6_UART_Init(); + 8000bb0: f000 fada bl 8001168 <_ZL19MX_USART6_UART_Initv> + MX_TIM6_Init(); + 8000bb4: f000 fa96 bl 80010e4 <_ZL12MX_TIM6_Initv> + + /* Initialize interrupts */ + MX_NVIC_Init(); + 8000bb8: f000 f8bc bl 8000d34 <_ZL12MX_NVIC_Initv> + /* USER CODE BEGIN 2 */ + + left_encoder.Setup(); + 8000bbc: 480f ldr r0, [pc, #60] ; (8000bfc ) + 8000bbe: f7ff fcf6 bl 80005ae <_ZN7Encoder5SetupEv> + right_encoder.Setup(); + 8000bc2: 480f ldr r0, [pc, #60] ; (8000c00 ) + 8000bc4: f7ff fcf3 bl 80005ae <_ZN7Encoder5SetupEv> + + left_motor.setup(); + 8000bc8: 480e ldr r0, [pc, #56] ; (8000c04 ) + 8000bca: f7ff fdd6 bl 800077a <_ZN15MotorController5setupEv> + right_motor.setup(); + 8000bce: 480e ldr r0, [pc, #56] ; (8000c08 ) + 8000bd0: f7ff fdd3 bl 800077a <_ZN15MotorController5setupEv> + + left_motor.coast(); + 8000bd4: 480b ldr r0, [pc, #44] ; (8000c04 ) + 8000bd6: f7ff ff07 bl 80009e8 <_ZN15MotorController5coastEv> + right_motor.coast(); + 8000bda: 480b ldr r0, [pc, #44] ; (8000c08 ) + 8000bdc: f7ff ff04 bl 80009e8 <_ZN15MotorController5coastEv> + + tx_buffer = (uint8_t*) &output_msg; + 8000be0: 4b0a ldr r3, [pc, #40] ; (8000c0c ) + 8000be2: 4a0b ldr r2, [pc, #44] ; (8000c10 ) + 8000be4: 601a str r2, [r3, #0] + rx_buffer = (uint8_t*) &input_msg; + 8000be6: 4b0b ldr r3, [pc, #44] ; (8000c14 ) + 8000be8: 4a0b ldr r2, [pc, #44] ; (8000c18 ) + 8000bea: 601a str r2, [r3, #0] + + //Enables UART RX interrupt + HAL_UART_Receive_IT(&huart6, rx_buffer, 28); + 8000bec: 4b09 ldr r3, [pc, #36] ; (8000c14 ) + 8000bee: 681b ldr r3, [r3, #0] + 8000bf0: 221c movs r2, #28 + 8000bf2: 4619 mov r1, r3 + 8000bf4: 4809 ldr r0, [pc, #36] ; (8000c1c ) + 8000bf6: f003 fe33 bl 8004860 + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) { + 8000bfa: e7fe b.n 8000bfa + 8000bfc: 20000200 .word 0x20000200 + 8000c00: 200001ec .word 0x200001ec + 8000c04: 200002bc .word 0x200002bc + 8000c08: 200002a4 .word 0x200002a4 + 8000c0c: 200002d4 .word 0x200002d4 + 8000c10: 200002f8 .word 0x200002f8 + 8000c14: 200002d8 .word 0x200002d8 + 8000c18: 200002dc .word 0x200002dc + 8000c1c: 2000016c .word 0x2000016c + +08000c20 <_Z18SystemClock_Configv>: +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 8000c20: b580 push {r7, lr} + 8000c22: b0b8 sub sp, #224 ; 0xe0 + 8000c24: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 8000c26: f107 03ac add.w r3, r7, #172 ; 0xac + 8000c2a: 2234 movs r2, #52 ; 0x34 + 8000c2c: 2100 movs r1, #0 + 8000c2e: 4618 mov r0, r3 + 8000c30: f004 fcbe bl 80055b0 + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8000c34: f107 0398 add.w r3, r7, #152 ; 0x98 + 8000c38: 2200 movs r2, #0 + 8000c3a: 601a str r2, [r3, #0] + 8000c3c: 605a str r2, [r3, #4] + 8000c3e: 609a str r2, [r3, #8] + 8000c40: 60da str r2, [r3, #12] + 8000c42: 611a str r2, [r3, #16] + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 8000c44: f107 0308 add.w r3, r7, #8 + 8000c48: 2290 movs r2, #144 ; 0x90 + 8000c4a: 2100 movs r1, #0 + 8000c4c: 4618 mov r0, r3 + 8000c4e: f004 fcaf bl 80055b0 + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + 8000c52: 4b36 ldr r3, [pc, #216] ; (8000d2c <_Z18SystemClock_Configv+0x10c>) + 8000c54: 6c1b ldr r3, [r3, #64] ; 0x40 + 8000c56: 4a35 ldr r2, [pc, #212] ; (8000d2c <_Z18SystemClock_Configv+0x10c>) + 8000c58: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8000c5c: 6413 str r3, [r2, #64] ; 0x40 + 8000c5e: 4b33 ldr r3, [pc, #204] ; (8000d2c <_Z18SystemClock_Configv+0x10c>) + 8000c60: 6c1b ldr r3, [r3, #64] ; 0x40 + 8000c62: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8000c66: 607b str r3, [r7, #4] + 8000c68: 687b ldr r3, [r7, #4] + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); + 8000c6a: 4b31 ldr r3, [pc, #196] ; (8000d30 <_Z18SystemClock_Configv+0x110>) + 8000c6c: 681b ldr r3, [r3, #0] + 8000c6e: f423 4340 bic.w r3, r3, #49152 ; 0xc000 + 8000c72: 4a2f ldr r2, [pc, #188] ; (8000d30 <_Z18SystemClock_Configv+0x110>) + 8000c74: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8000c78: 6013 str r3, [r2, #0] + 8000c7a: 4b2d ldr r3, [pc, #180] ; (8000d30 <_Z18SystemClock_Configv+0x110>) + 8000c7c: 681b ldr r3, [r3, #0] + 8000c7e: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 8000c82: 603b str r3, [r7, #0] + 8000c84: 683b ldr r3, [r7, #0] + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 8000c86: 2302 movs r3, #2 + 8000c88: f8c7 30ac str.w r3, [r7, #172] ; 0xac + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 8000c8c: 2301 movs r3, #1 + 8000c8e: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 8000c92: 2310 movs r3, #16 + 8000c94: f8c7 30bc str.w r3, [r7, #188] ; 0xbc + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 8000c98: 2300 movs r3, #0 + 8000c9a: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8000c9e: f107 03ac add.w r3, r7, #172 ; 0xac + 8000ca2: 4618 mov r0, r3 + 8000ca4: f001 fbac bl 8002400 + 8000ca8: 4603 mov r3, r0 + 8000caa: 2b00 cmp r3, #0 + 8000cac: bf14 ite ne + 8000cae: 2301 movne r3, #1 + 8000cb0: 2300 moveq r3, #0 + 8000cb2: b2db uxtb r3, r3 + 8000cb4: 2b00 cmp r3, #0 + 8000cb6: d001 beq.n 8000cbc <_Z18SystemClock_Configv+0x9c> + { + Error_Handler(); + 8000cb8: f000 fd84 bl 80017c4 + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 8000cbc: 230f movs r3, #15 + 8000cbe: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + 8000cc2: 2300 movs r3, #0 + 8000cc4: f8c7 309c str.w r3, [r7, #156] ; 0x9c + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 8000cc8: 2300 movs r3, #0 + 8000cca: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 8000cce: 2300 movs r3, #0 + 8000cd0: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 8000cd4: 2300 movs r3, #0 + 8000cd6: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 8000cda: f107 0398 add.w r3, r7, #152 ; 0x98 + 8000cde: 2100 movs r1, #0 + 8000ce0: 4618 mov r0, r3 + 8000ce2: f001 fdff bl 80028e4 + 8000ce6: 4603 mov r3, r0 + 8000ce8: 2b00 cmp r3, #0 + 8000cea: bf14 ite ne + 8000cec: 2301 movne r3, #1 + 8000cee: 2300 moveq r3, #0 + 8000cf0: b2db uxtb r3, r3 + 8000cf2: 2b00 cmp r3, #0 + 8000cf4: d001 beq.n 8000cfa <_Z18SystemClock_Configv+0xda> + { + Error_Handler(); + 8000cf6: f000 fd65 bl 80017c4 + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6; + 8000cfa: f44f 6300 mov.w r3, #2048 ; 0x800 + 8000cfe: 60bb str r3, [r7, #8] + PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2; + 8000d00: 2300 movs r3, #0 + 8000d02: 663b str r3, [r7, #96] ; 0x60 + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 8000d04: f107 0308 add.w r3, r7, #8 + 8000d08: 4618 mov r0, r3 + 8000d0a: f001 ffb9 bl 8002c80 + 8000d0e: 4603 mov r3, r0 + 8000d10: 2b00 cmp r3, #0 + 8000d12: bf14 ite ne + 8000d14: 2301 movne r3, #1 + 8000d16: 2300 moveq r3, #0 + 8000d18: b2db uxtb r3, r3 + 8000d1a: 2b00 cmp r3, #0 + 8000d1c: d001 beq.n 8000d22 <_Z18SystemClock_Configv+0x102> + { + Error_Handler(); + 8000d1e: f000 fd51 bl 80017c4 + } +} + 8000d22: bf00 nop + 8000d24: 37e0 adds r7, #224 ; 0xe0 + 8000d26: 46bd mov sp, r7 + 8000d28: bd80 pop {r7, pc} + 8000d2a: bf00 nop + 8000d2c: 40023800 .word 0x40023800 + 8000d30: 40007000 .word 0x40007000 + +08000d34 <_ZL12MX_NVIC_Initv>: +/** + * @brief NVIC Configuration. + * @retval None + */ +static void MX_NVIC_Init(void) +{ + 8000d34: b580 push {r7, lr} + 8000d36: af00 add r7, sp, #0 + /* TIM3_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(TIM3_IRQn, 2, 1); + 8000d38: 2201 movs r2, #1 + 8000d3a: 2102 movs r1, #2 + 8000d3c: 201d movs r0, #29 + 8000d3e: f001 f92a bl 8001f96 + HAL_NVIC_EnableIRQ(TIM3_IRQn); + 8000d42: 201d movs r0, #29 + 8000d44: f001 f943 bl 8001fce + /* TIM6_DAC_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 2, 2); + 8000d48: 2202 movs r2, #2 + 8000d4a: 2102 movs r1, #2 + 8000d4c: 2036 movs r0, #54 ; 0x36 + 8000d4e: f001 f922 bl 8001f96 + HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); + 8000d52: 2036 movs r0, #54 ; 0x36 + 8000d54: f001 f93b bl 8001fce + /* USART6_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(USART6_IRQn, 2, 0); + 8000d58: 2200 movs r2, #0 + 8000d5a: 2102 movs r1, #2 + 8000d5c: 2047 movs r0, #71 ; 0x47 + 8000d5e: f001 f91a bl 8001f96 + HAL_NVIC_EnableIRQ(USART6_IRQn); + 8000d62: 2047 movs r0, #71 ; 0x47 + 8000d64: f001 f933 bl 8001fce +} + 8000d68: bf00 nop + 8000d6a: bd80 pop {r7, pc} + +08000d6c <_ZL12MX_TIM2_Initv>: + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) +{ + 8000d6c: b580 push {r7, lr} + 8000d6e: b08c sub sp, #48 ; 0x30 + 8000d70: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_Encoder_InitTypeDef sConfig = {0}; + 8000d72: f107 030c add.w r3, r7, #12 + 8000d76: 2224 movs r2, #36 ; 0x24 + 8000d78: 2100 movs r1, #0 + 8000d7a: 4618 mov r0, r3 + 8000d7c: f004 fc18 bl 80055b0 + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 8000d80: 463b mov r3, r7 + 8000d82: 2200 movs r2, #0 + 8000d84: 601a str r2, [r3, #0] + 8000d86: 605a str r2, [r3, #4] + 8000d88: 609a str r2, [r3, #8] + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + 8000d8a: 4b26 ldr r3, [pc, #152] ; (8000e24 <_ZL12MX_TIM2_Initv+0xb8>) + 8000d8c: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 + 8000d90: 601a str r2, [r3, #0] + htim2.Init.Prescaler = 0; + 8000d92: 4b24 ldr r3, [pc, #144] ; (8000e24 <_ZL12MX_TIM2_Initv+0xb8>) + 8000d94: 2200 movs r2, #0 + 8000d96: 605a str r2, [r3, #4] + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + 8000d98: 4b22 ldr r3, [pc, #136] ; (8000e24 <_ZL12MX_TIM2_Initv+0xb8>) + 8000d9a: 2200 movs r2, #0 + 8000d9c: 609a str r2, [r3, #8] + htim2.Init.Period = 4294967295; + 8000d9e: 4b21 ldr r3, [pc, #132] ; (8000e24 <_ZL12MX_TIM2_Initv+0xb8>) + 8000da0: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 8000da4: 60da str r2, [r3, #12] + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8000da6: 4b1f ldr r3, [pc, #124] ; (8000e24 <_ZL12MX_TIM2_Initv+0xb8>) + 8000da8: 2200 movs r2, #0 + 8000daa: 611a str r2, [r3, #16] + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 8000dac: 4b1d ldr r3, [pc, #116] ; (8000e24 <_ZL12MX_TIM2_Initv+0xb8>) + 8000dae: 2200 movs r2, #0 + 8000db0: 619a str r2, [r3, #24] + sConfig.EncoderMode = TIM_ENCODERMODE_TI12; + 8000db2: 2303 movs r3, #3 + 8000db4: 60fb str r3, [r7, #12] + sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; + 8000db6: 2300 movs r3, #0 + 8000db8: 613b str r3, [r7, #16] + sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; + 8000dba: 2301 movs r3, #1 + 8000dbc: 617b str r3, [r7, #20] + sConfig.IC1Prescaler = TIM_ICPSC_DIV1; + 8000dbe: 2300 movs r3, #0 + 8000dc0: 61bb str r3, [r7, #24] + sConfig.IC1Filter = 0; + 8000dc2: 2300 movs r3, #0 + 8000dc4: 61fb str r3, [r7, #28] + sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; + 8000dc6: 2300 movs r3, #0 + 8000dc8: 623b str r3, [r7, #32] + sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; + 8000dca: 2301 movs r3, #1 + 8000dcc: 627b str r3, [r7, #36] ; 0x24 + sConfig.IC2Prescaler = TIM_ICPSC_DIV1; + 8000dce: 2300 movs r3, #0 + 8000dd0: 62bb str r3, [r7, #40] ; 0x28 + sConfig.IC2Filter = 0; + 8000dd2: 2300 movs r3, #0 + 8000dd4: 62fb str r3, [r7, #44] ; 0x2c + if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK) + 8000dd6: f107 030c add.w r3, r7, #12 + 8000dda: 4619 mov r1, r3 + 8000ddc: 4811 ldr r0, [pc, #68] ; (8000e24 <_ZL12MX_TIM2_Initv+0xb8>) + 8000dde: f002 fc45 bl 800366c + 8000de2: 4603 mov r3, r0 + 8000de4: 2b00 cmp r3, #0 + 8000de6: bf14 ite ne + 8000de8: 2301 movne r3, #1 + 8000dea: 2300 moveq r3, #0 + 8000dec: b2db uxtb r3, r3 + 8000dee: 2b00 cmp r3, #0 + 8000df0: d001 beq.n 8000df6 <_ZL12MX_TIM2_Initv+0x8a> + { + Error_Handler(); + 8000df2: f000 fce7 bl 80017c4 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8000df6: 2300 movs r3, #0 + 8000df8: 603b str r3, [r7, #0] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8000dfa: 2300 movs r3, #0 + 8000dfc: 60bb str r3, [r7, #8] + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + 8000dfe: 463b mov r3, r7 + 8000e00: 4619 mov r1, r3 + 8000e02: 4808 ldr r0, [pc, #32] ; (8000e24 <_ZL12MX_TIM2_Initv+0xb8>) + 8000e04: f003 fbd2 bl 80045ac + 8000e08: 4603 mov r3, r0 + 8000e0a: 2b00 cmp r3, #0 + 8000e0c: bf14 ite ne + 8000e0e: 2301 movne r3, #1 + 8000e10: 2300 moveq r3, #0 + 8000e12: b2db uxtb r3, r3 + 8000e14: 2b00 cmp r3, #0 + 8000e16: d001 beq.n 8000e1c <_ZL12MX_TIM2_Initv+0xb0> + { + Error_Handler(); + 8000e18: f000 fcd4 bl 80017c4 + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + +} + 8000e1c: bf00 nop + 8000e1e: 3730 adds r7, #48 ; 0x30 + 8000e20: 46bd mov sp, r7 + 8000e22: bd80 pop {r7, pc} + 8000e24: 2000002c .word 0x2000002c + +08000e28 <_ZL12MX_TIM3_Initv>: + * @brief TIM3 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM3_Init(void) +{ + 8000e28: b580 push {r7, lr} + 8000e2a: b088 sub sp, #32 + 8000e2c: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 8000e2e: f107 0310 add.w r3, r7, #16 + 8000e32: 2200 movs r2, #0 + 8000e34: 601a str r2, [r3, #0] + 8000e36: 605a str r2, [r3, #4] + 8000e38: 609a str r2, [r3, #8] + 8000e3a: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 8000e3c: 1d3b adds r3, r7, #4 + 8000e3e: 2200 movs r2, #0 + 8000e40: 601a str r2, [r3, #0] + 8000e42: 605a str r2, [r3, #4] + 8000e44: 609a str r2, [r3, #8] + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + htim3.Instance = TIM3; + 8000e46: 4b25 ldr r3, [pc, #148] ; (8000edc <_ZL12MX_TIM3_Initv+0xb4>) + 8000e48: 4a25 ldr r2, [pc, #148] ; (8000ee0 <_ZL12MX_TIM3_Initv+0xb8>) + 8000e4a: 601a str r2, [r3, #0] + htim3.Init.Prescaler = 999; + 8000e4c: 4b23 ldr r3, [pc, #140] ; (8000edc <_ZL12MX_TIM3_Initv+0xb4>) + 8000e4e: f240 32e7 movw r2, #999 ; 0x3e7 + 8000e52: 605a str r2, [r3, #4] + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + 8000e54: 4b21 ldr r3, [pc, #132] ; (8000edc <_ZL12MX_TIM3_Initv+0xb4>) + 8000e56: 2200 movs r2, #0 + 8000e58: 609a str r2, [r3, #8] + htim3.Init.Period = 159; + 8000e5a: 4b20 ldr r3, [pc, #128] ; (8000edc <_ZL12MX_TIM3_Initv+0xb4>) + 8000e5c: 229f movs r2, #159 ; 0x9f + 8000e5e: 60da str r2, [r3, #12] + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8000e60: 4b1e ldr r3, [pc, #120] ; (8000edc <_ZL12MX_TIM3_Initv+0xb4>) + 8000e62: 2200 movs r2, #0 + 8000e64: 611a str r2, [r3, #16] + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 8000e66: 4b1d ldr r3, [pc, #116] ; (8000edc <_ZL12MX_TIM3_Initv+0xb4>) + 8000e68: 2200 movs r2, #0 + 8000e6a: 619a str r2, [r3, #24] + if (HAL_TIM_Base_Init(&htim3) != HAL_OK) + 8000e6c: 481b ldr r0, [pc, #108] ; (8000edc <_ZL12MX_TIM3_Initv+0xb4>) + 8000e6e: f002 fb2d bl 80034cc + 8000e72: 4603 mov r3, r0 + 8000e74: 2b00 cmp r3, #0 + 8000e76: bf14 ite ne + 8000e78: 2301 movne r3, #1 + 8000e7a: 2300 moveq r3, #0 + 8000e7c: b2db uxtb r3, r3 + 8000e7e: 2b00 cmp r3, #0 + 8000e80: d001 beq.n 8000e86 <_ZL12MX_TIM3_Initv+0x5e> + { + Error_Handler(); + 8000e82: f000 fc9f bl 80017c4 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 8000e86: f44f 5380 mov.w r3, #4096 ; 0x1000 + 8000e8a: 613b str r3, [r7, #16] + if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) + 8000e8c: f107 0310 add.w r3, r7, #16 + 8000e90: 4619 mov r1, r3 + 8000e92: 4812 ldr r0, [pc, #72] ; (8000edc <_ZL12MX_TIM3_Initv+0xb4>) + 8000e94: f002 feea bl 8003c6c + 8000e98: 4603 mov r3, r0 + 8000e9a: 2b00 cmp r3, #0 + 8000e9c: bf14 ite ne + 8000e9e: 2301 movne r3, #1 + 8000ea0: 2300 moveq r3, #0 + 8000ea2: b2db uxtb r3, r3 + 8000ea4: 2b00 cmp r3, #0 + 8000ea6: d001 beq.n 8000eac <_ZL12MX_TIM3_Initv+0x84> + { + Error_Handler(); + 8000ea8: f000 fc8c bl 80017c4 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8000eac: 2300 movs r3, #0 + 8000eae: 607b str r3, [r7, #4] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8000eb0: 2300 movs r3, #0 + 8000eb2: 60fb str r3, [r7, #12] + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + 8000eb4: 1d3b adds r3, r7, #4 + 8000eb6: 4619 mov r1, r3 + 8000eb8: 4808 ldr r0, [pc, #32] ; (8000edc <_ZL12MX_TIM3_Initv+0xb4>) + 8000eba: f003 fb77 bl 80045ac + 8000ebe: 4603 mov r3, r0 + 8000ec0: 2b00 cmp r3, #0 + 8000ec2: bf14 ite ne + 8000ec4: 2301 movne r3, #1 + 8000ec6: 2300 moveq r3, #0 + 8000ec8: b2db uxtb r3, r3 + 8000eca: 2b00 cmp r3, #0 + 8000ecc: d001 beq.n 8000ed2 <_ZL12MX_TIM3_Initv+0xaa> + { + Error_Handler(); + 8000ece: f000 fc79 bl 80017c4 + } + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + +} + 8000ed2: bf00 nop + 8000ed4: 3720 adds r7, #32 + 8000ed6: 46bd mov sp, r7 + 8000ed8: bd80 pop {r7, pc} + 8000eda: bf00 nop + 8000edc: 2000006c .word 0x2000006c + 8000ee0: 40000400 .word 0x40000400 + +08000ee4 <_ZL12MX_TIM4_Initv>: + * @brief TIM4 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM4_Init(void) +{ + 8000ee4: b580 push {r7, lr} + 8000ee6: b08e sub sp, #56 ; 0x38 + 8000ee8: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM4_Init 0 */ + + /* USER CODE END TIM4_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 8000eea: f107 0328 add.w r3, r7, #40 ; 0x28 + 8000eee: 2200 movs r2, #0 + 8000ef0: 601a str r2, [r3, #0] + 8000ef2: 605a str r2, [r3, #4] + 8000ef4: 609a str r2, [r3, #8] + 8000ef6: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 8000ef8: f107 031c add.w r3, r7, #28 + 8000efc: 2200 movs r2, #0 + 8000efe: 601a str r2, [r3, #0] + 8000f00: 605a str r2, [r3, #4] + 8000f02: 609a str r2, [r3, #8] + TIM_OC_InitTypeDef sConfigOC = {0}; + 8000f04: 463b mov r3, r7 + 8000f06: 2200 movs r2, #0 + 8000f08: 601a str r2, [r3, #0] + 8000f0a: 605a str r2, [r3, #4] + 8000f0c: 609a str r2, [r3, #8] + 8000f0e: 60da str r2, [r3, #12] + 8000f10: 611a str r2, [r3, #16] + 8000f12: 615a str r2, [r3, #20] + 8000f14: 619a str r2, [r3, #24] + + /* USER CODE BEGIN TIM4_Init 1 */ + + /* USER CODE END TIM4_Init 1 */ + htim4.Instance = TIM4; + 8000f16: 4b41 ldr r3, [pc, #260] ; (800101c <_ZL12MX_TIM4_Initv+0x138>) + 8000f18: 4a41 ldr r2, [pc, #260] ; (8001020 <_ZL12MX_TIM4_Initv+0x13c>) + 8000f1a: 601a str r2, [r3, #0] + htim4.Init.Prescaler = 0; + 8000f1c: 4b3f ldr r3, [pc, #252] ; (800101c <_ZL12MX_TIM4_Initv+0x138>) + 8000f1e: 2200 movs r2, #0 + 8000f20: 605a str r2, [r3, #4] + htim4.Init.CounterMode = TIM_COUNTERMODE_UP; + 8000f22: 4b3e ldr r3, [pc, #248] ; (800101c <_ZL12MX_TIM4_Initv+0x138>) + 8000f24: 2200 movs r2, #0 + 8000f26: 609a str r2, [r3, #8] + htim4.Init.Period = 799; + 8000f28: 4b3c ldr r3, [pc, #240] ; (800101c <_ZL12MX_TIM4_Initv+0x138>) + 8000f2a: f240 321f movw r2, #799 ; 0x31f + 8000f2e: 60da str r2, [r3, #12] + htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8000f30: 4b3a ldr r3, [pc, #232] ; (800101c <_ZL12MX_TIM4_Initv+0x138>) + 8000f32: 2200 movs r2, #0 + 8000f34: 611a str r2, [r3, #16] + htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 8000f36: 4b39 ldr r3, [pc, #228] ; (800101c <_ZL12MX_TIM4_Initv+0x138>) + 8000f38: 2200 movs r2, #0 + 8000f3a: 619a str r2, [r3, #24] + if (HAL_TIM_Base_Init(&htim4) != HAL_OK) + 8000f3c: 4837 ldr r0, [pc, #220] ; (800101c <_ZL12MX_TIM4_Initv+0x138>) + 8000f3e: f002 fac5 bl 80034cc + 8000f42: 4603 mov r3, r0 + 8000f44: 2b00 cmp r3, #0 + 8000f46: bf14 ite ne + 8000f48: 2301 movne r3, #1 + 8000f4a: 2300 moveq r3, #0 + 8000f4c: b2db uxtb r3, r3 + 8000f4e: 2b00 cmp r3, #0 + 8000f50: d001 beq.n 8000f56 <_ZL12MX_TIM4_Initv+0x72> + { + Error_Handler(); + 8000f52: f000 fc37 bl 80017c4 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 8000f56: f44f 5380 mov.w r3, #4096 ; 0x1000 + 8000f5a: 62bb str r3, [r7, #40] ; 0x28 + if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) + 8000f5c: f107 0328 add.w r3, r7, #40 ; 0x28 + 8000f60: 4619 mov r1, r3 + 8000f62: 482e ldr r0, [pc, #184] ; (800101c <_ZL12MX_TIM4_Initv+0x138>) + 8000f64: f002 fe82 bl 8003c6c + 8000f68: 4603 mov r3, r0 + 8000f6a: 2b00 cmp r3, #0 + 8000f6c: bf14 ite ne + 8000f6e: 2301 movne r3, #1 + 8000f70: 2300 moveq r3, #0 + 8000f72: b2db uxtb r3, r3 + 8000f74: 2b00 cmp r3, #0 + 8000f76: d001 beq.n 8000f7c <_ZL12MX_TIM4_Initv+0x98> + { + Error_Handler(); + 8000f78: f000 fc24 bl 80017c4 + } + if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) + 8000f7c: 4827 ldr r0, [pc, #156] ; (800101c <_ZL12MX_TIM4_Initv+0x138>) + 8000f7e: f002 fafb bl 8003578 + 8000f82: 4603 mov r3, r0 + 8000f84: 2b00 cmp r3, #0 + 8000f86: bf14 ite ne + 8000f88: 2301 movne r3, #1 + 8000f8a: 2300 moveq r3, #0 + 8000f8c: b2db uxtb r3, r3 + 8000f8e: 2b00 cmp r3, #0 + 8000f90: d001 beq.n 8000f96 <_ZL12MX_TIM4_Initv+0xb2> + { + Error_Handler(); + 8000f92: f000 fc17 bl 80017c4 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8000f96: 2300 movs r3, #0 + 8000f98: 61fb str r3, [r7, #28] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8000f9a: 2300 movs r3, #0 + 8000f9c: 627b str r3, [r7, #36] ; 0x24 + if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) + 8000f9e: f107 031c add.w r3, r7, #28 + 8000fa2: 4619 mov r1, r3 + 8000fa4: 481d ldr r0, [pc, #116] ; (800101c <_ZL12MX_TIM4_Initv+0x138>) + 8000fa6: f003 fb01 bl 80045ac + 8000faa: 4603 mov r3, r0 + 8000fac: 2b00 cmp r3, #0 + 8000fae: bf14 ite ne + 8000fb0: 2301 movne r3, #1 + 8000fb2: 2300 moveq r3, #0 + 8000fb4: b2db uxtb r3, r3 + 8000fb6: 2b00 cmp r3, #0 + 8000fb8: d001 beq.n 8000fbe <_ZL12MX_TIM4_Initv+0xda> + { + Error_Handler(); + 8000fba: f000 fc03 bl 80017c4 + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + 8000fbe: 2360 movs r3, #96 ; 0x60 + 8000fc0: 603b str r3, [r7, #0] + sConfigOC.Pulse = 0; + 8000fc2: 2300 movs r3, #0 + 8000fc4: 607b str r3, [r7, #4] + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 8000fc6: 2300 movs r3, #0 + 8000fc8: 60bb str r3, [r7, #8] + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 8000fca: 2300 movs r3, #0 + 8000fcc: 613b str r3, [r7, #16] + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + 8000fce: 463b mov r3, r7 + 8000fd0: 2208 movs r2, #8 + 8000fd2: 4619 mov r1, r3 + 8000fd4: 4811 ldr r0, [pc, #68] ; (800101c <_ZL12MX_TIM4_Initv+0x138>) + 8000fd6: f002 fd31 bl 8003a3c + 8000fda: 4603 mov r3, r0 + 8000fdc: 2b00 cmp r3, #0 + 8000fde: bf14 ite ne + 8000fe0: 2301 movne r3, #1 + 8000fe2: 2300 moveq r3, #0 + 8000fe4: b2db uxtb r3, r3 + 8000fe6: 2b00 cmp r3, #0 + 8000fe8: d001 beq.n 8000fee <_ZL12MX_TIM4_Initv+0x10a> + { + Error_Handler(); + 8000fea: f000 fbeb bl 80017c4 + } + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + 8000fee: 463b mov r3, r7 + 8000ff0: 220c movs r2, #12 + 8000ff2: 4619 mov r1, r3 + 8000ff4: 4809 ldr r0, [pc, #36] ; (800101c <_ZL12MX_TIM4_Initv+0x138>) + 8000ff6: f002 fd21 bl 8003a3c + 8000ffa: 4603 mov r3, r0 + 8000ffc: 2b00 cmp r3, #0 + 8000ffe: bf14 ite ne + 8001000: 2301 movne r3, #1 + 8001002: 2300 moveq r3, #0 + 8001004: b2db uxtb r3, r3 + 8001006: 2b00 cmp r3, #0 + 8001008: d001 beq.n 800100e <_ZL12MX_TIM4_Initv+0x12a> + { + Error_Handler(); + 800100a: f000 fbdb bl 80017c4 + } + /* USER CODE BEGIN TIM4_Init 2 */ + + /* USER CODE END TIM4_Init 2 */ + HAL_TIM_MspPostInit(&htim4); + 800100e: 4803 ldr r0, [pc, #12] ; (800101c <_ZL12MX_TIM4_Initv+0x138>) + 8001010: f000 fd5a bl 8001ac8 + +} + 8001014: bf00 nop + 8001016: 3738 adds r7, #56 ; 0x38 + 8001018: 46bd mov sp, r7 + 800101a: bd80 pop {r7, pc} + 800101c: 200000ac .word 0x200000ac + 8001020: 40000800 .word 0x40000800 + +08001024 <_ZL12MX_TIM5_Initv>: + * @brief TIM5 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM5_Init(void) +{ + 8001024: b580 push {r7, lr} + 8001026: b08c sub sp, #48 ; 0x30 + 8001028: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM5_Init 0 */ + + /* USER CODE END TIM5_Init 0 */ + + TIM_Encoder_InitTypeDef sConfig = {0}; + 800102a: f107 030c add.w r3, r7, #12 + 800102e: 2224 movs r2, #36 ; 0x24 + 8001030: 2100 movs r1, #0 + 8001032: 4618 mov r0, r3 + 8001034: f004 fabc bl 80055b0 + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 8001038: 463b mov r3, r7 + 800103a: 2200 movs r2, #0 + 800103c: 601a str r2, [r3, #0] + 800103e: 605a str r2, [r3, #4] + 8001040: 609a str r2, [r3, #8] + + /* USER CODE BEGIN TIM5_Init 1 */ + + /* USER CODE END TIM5_Init 1 */ + htim5.Instance = TIM5; + 8001042: 4b26 ldr r3, [pc, #152] ; (80010dc <_ZL12MX_TIM5_Initv+0xb8>) + 8001044: 4a26 ldr r2, [pc, #152] ; (80010e0 <_ZL12MX_TIM5_Initv+0xbc>) + 8001046: 601a str r2, [r3, #0] + htim5.Init.Prescaler = 0; + 8001048: 4b24 ldr r3, [pc, #144] ; (80010dc <_ZL12MX_TIM5_Initv+0xb8>) + 800104a: 2200 movs r2, #0 + 800104c: 605a str r2, [r3, #4] + htim5.Init.CounterMode = TIM_COUNTERMODE_UP; + 800104e: 4b23 ldr r3, [pc, #140] ; (80010dc <_ZL12MX_TIM5_Initv+0xb8>) + 8001050: 2200 movs r2, #0 + 8001052: 609a str r2, [r3, #8] + htim5.Init.Period = 4294967295; + 8001054: 4b21 ldr r3, [pc, #132] ; (80010dc <_ZL12MX_TIM5_Initv+0xb8>) + 8001056: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 800105a: 60da str r2, [r3, #12] + htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 800105c: 4b1f ldr r3, [pc, #124] ; (80010dc <_ZL12MX_TIM5_Initv+0xb8>) + 800105e: 2200 movs r2, #0 + 8001060: 611a str r2, [r3, #16] + htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 8001062: 4b1e ldr r3, [pc, #120] ; (80010dc <_ZL12MX_TIM5_Initv+0xb8>) + 8001064: 2200 movs r2, #0 + 8001066: 619a str r2, [r3, #24] + sConfig.EncoderMode = TIM_ENCODERMODE_TI12; + 8001068: 2303 movs r3, #3 + 800106a: 60fb str r3, [r7, #12] + sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; + 800106c: 2300 movs r3, #0 + 800106e: 613b str r3, [r7, #16] + sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; + 8001070: 2301 movs r3, #1 + 8001072: 617b str r3, [r7, #20] + sConfig.IC1Prescaler = TIM_ICPSC_DIV1; + 8001074: 2300 movs r3, #0 + 8001076: 61bb str r3, [r7, #24] + sConfig.IC1Filter = 0; + 8001078: 2300 movs r3, #0 + 800107a: 61fb str r3, [r7, #28] + sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; + 800107c: 2300 movs r3, #0 + 800107e: 623b str r3, [r7, #32] + sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; + 8001080: 2301 movs r3, #1 + 8001082: 627b str r3, [r7, #36] ; 0x24 + sConfig.IC2Prescaler = TIM_ICPSC_DIV1; + 8001084: 2300 movs r3, #0 + 8001086: 62bb str r3, [r7, #40] ; 0x28 + sConfig.IC2Filter = 0; + 8001088: 2300 movs r3, #0 + 800108a: 62fb str r3, [r7, #44] ; 0x2c + if (HAL_TIM_Encoder_Init(&htim5, &sConfig) != HAL_OK) + 800108c: f107 030c add.w r3, r7, #12 + 8001090: 4619 mov r1, r3 + 8001092: 4812 ldr r0, [pc, #72] ; (80010dc <_ZL12MX_TIM5_Initv+0xb8>) + 8001094: f002 faea bl 800366c + 8001098: 4603 mov r3, r0 + 800109a: 2b00 cmp r3, #0 + 800109c: bf14 ite ne + 800109e: 2301 movne r3, #1 + 80010a0: 2300 moveq r3, #0 + 80010a2: b2db uxtb r3, r3 + 80010a4: 2b00 cmp r3, #0 + 80010a6: d001 beq.n 80010ac <_ZL12MX_TIM5_Initv+0x88> + { + Error_Handler(); + 80010a8: f000 fb8c bl 80017c4 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 80010ac: 2300 movs r3, #0 + 80010ae: 603b str r3, [r7, #0] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 80010b0: 2300 movs r3, #0 + 80010b2: 60bb str r3, [r7, #8] + if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) + 80010b4: 463b mov r3, r7 + 80010b6: 4619 mov r1, r3 + 80010b8: 4808 ldr r0, [pc, #32] ; (80010dc <_ZL12MX_TIM5_Initv+0xb8>) + 80010ba: f003 fa77 bl 80045ac + 80010be: 4603 mov r3, r0 + 80010c0: 2b00 cmp r3, #0 + 80010c2: bf14 ite ne + 80010c4: 2301 movne r3, #1 + 80010c6: 2300 moveq r3, #0 + 80010c8: b2db uxtb r3, r3 + 80010ca: 2b00 cmp r3, #0 + 80010cc: d001 beq.n 80010d2 <_ZL12MX_TIM5_Initv+0xae> + { + Error_Handler(); + 80010ce: f000 fb79 bl 80017c4 + } + /* USER CODE BEGIN TIM5_Init 2 */ + + /* USER CODE END TIM5_Init 2 */ + +} + 80010d2: bf00 nop + 80010d4: 3730 adds r7, #48 ; 0x30 + 80010d6: 46bd mov sp, r7 + 80010d8: bd80 pop {r7, pc} + 80010da: bf00 nop + 80010dc: 200000ec .word 0x200000ec + 80010e0: 40000c00 .word 0x40000c00 + +080010e4 <_ZL12MX_TIM6_Initv>: + * @brief TIM6 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM6_Init(void) +{ + 80010e4: b580 push {r7, lr} + 80010e6: b084 sub sp, #16 + 80010e8: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM6_Init 0 */ + + /* USER CODE END TIM6_Init 0 */ + + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 80010ea: 1d3b adds r3, r7, #4 + 80010ec: 2200 movs r2, #0 + 80010ee: 601a str r2, [r3, #0] + 80010f0: 605a str r2, [r3, #4] + 80010f2: 609a str r2, [r3, #8] + + /* USER CODE BEGIN TIM6_Init 1 */ + + /* USER CODE END TIM6_Init 1 */ + htim6.Instance = TIM6; + 80010f4: 4b1a ldr r3, [pc, #104] ; (8001160 <_ZL12MX_TIM6_Initv+0x7c>) + 80010f6: 4a1b ldr r2, [pc, #108] ; (8001164 <_ZL12MX_TIM6_Initv+0x80>) + 80010f8: 601a str r2, [r3, #0] + htim6.Init.Prescaler = 9999; + 80010fa: 4b19 ldr r3, [pc, #100] ; (8001160 <_ZL12MX_TIM6_Initv+0x7c>) + 80010fc: f242 720f movw r2, #9999 ; 0x270f + 8001100: 605a str r2, [r3, #4] + htim6.Init.CounterMode = TIM_COUNTERMODE_UP; + 8001102: 4b17 ldr r3, [pc, #92] ; (8001160 <_ZL12MX_TIM6_Initv+0x7c>) + 8001104: 2200 movs r2, #0 + 8001106: 609a str r2, [r3, #8] + htim6.Init.Period = 799; + 8001108: 4b15 ldr r3, [pc, #84] ; (8001160 <_ZL12MX_TIM6_Initv+0x7c>) + 800110a: f240 321f movw r2, #799 ; 0x31f + 800110e: 60da str r2, [r3, #12] + htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 8001110: 4b13 ldr r3, [pc, #76] ; (8001160 <_ZL12MX_TIM6_Initv+0x7c>) + 8001112: 2200 movs r2, #0 + 8001114: 619a str r2, [r3, #24] + if (HAL_TIM_Base_Init(&htim6) != HAL_OK) + 8001116: 4812 ldr r0, [pc, #72] ; (8001160 <_ZL12MX_TIM6_Initv+0x7c>) + 8001118: f002 f9d8 bl 80034cc + 800111c: 4603 mov r3, r0 + 800111e: 2b00 cmp r3, #0 + 8001120: bf14 ite ne + 8001122: 2301 movne r3, #1 + 8001124: 2300 moveq r3, #0 + 8001126: b2db uxtb r3, r3 + 8001128: 2b00 cmp r3, #0 + 800112a: d001 beq.n 8001130 <_ZL12MX_TIM6_Initv+0x4c> + { + Error_Handler(); + 800112c: f000 fb4a bl 80017c4 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8001130: 2300 movs r3, #0 + 8001132: 607b str r3, [r7, #4] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8001134: 2300 movs r3, #0 + 8001136: 60fb str r3, [r7, #12] + if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) + 8001138: 1d3b adds r3, r7, #4 + 800113a: 4619 mov r1, r3 + 800113c: 4808 ldr r0, [pc, #32] ; (8001160 <_ZL12MX_TIM6_Initv+0x7c>) + 800113e: f003 fa35 bl 80045ac + 8001142: 4603 mov r3, r0 + 8001144: 2b00 cmp r3, #0 + 8001146: bf14 ite ne + 8001148: 2301 movne r3, #1 + 800114a: 2300 moveq r3, #0 + 800114c: b2db uxtb r3, r3 + 800114e: 2b00 cmp r3, #0 + 8001150: d001 beq.n 8001156 <_ZL12MX_TIM6_Initv+0x72> + { + Error_Handler(); + 8001152: f000 fb37 bl 80017c4 + } + /* USER CODE BEGIN TIM6_Init 2 */ + + /* USER CODE END TIM6_Init 2 */ + +} + 8001156: bf00 nop + 8001158: 3710 adds r7, #16 + 800115a: 46bd mov sp, r7 + 800115c: bd80 pop {r7, pc} + 800115e: bf00 nop + 8001160: 2000012c .word 0x2000012c + 8001164: 40001000 .word 0x40001000 + +08001168 <_ZL19MX_USART6_UART_Initv>: + * @brief USART6 Initialization Function + * @param None + * @retval None + */ +static void MX_USART6_UART_Init(void) +{ + 8001168: b580 push {r7, lr} + 800116a: af00 add r7, sp, #0 + /* USER CODE END USART6_Init 0 */ + + /* USER CODE BEGIN USART6_Init 1 */ + + /* USER CODE END USART6_Init 1 */ + huart6.Instance = USART6; + 800116c: 4b16 ldr r3, [pc, #88] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>) + 800116e: 4a17 ldr r2, [pc, #92] ; (80011cc <_ZL19MX_USART6_UART_Initv+0x64>) + 8001170: 601a str r2, [r3, #0] + huart6.Init.BaudRate = 115200; + 8001172: 4b15 ldr r3, [pc, #84] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>) + 8001174: f44f 32e1 mov.w r2, #115200 ; 0x1c200 + 8001178: 605a str r2, [r3, #4] + huart6.Init.WordLength = UART_WORDLENGTH_8B; + 800117a: 4b13 ldr r3, [pc, #76] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>) + 800117c: 2200 movs r2, #0 + 800117e: 609a str r2, [r3, #8] + huart6.Init.StopBits = UART_STOPBITS_1; + 8001180: 4b11 ldr r3, [pc, #68] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>) + 8001182: 2200 movs r2, #0 + 8001184: 60da str r2, [r3, #12] + huart6.Init.Parity = UART_PARITY_NONE; + 8001186: 4b10 ldr r3, [pc, #64] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>) + 8001188: 2200 movs r2, #0 + 800118a: 611a str r2, [r3, #16] + huart6.Init.Mode = UART_MODE_TX_RX; + 800118c: 4b0e ldr r3, [pc, #56] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>) + 800118e: 220c movs r2, #12 + 8001190: 615a str r2, [r3, #20] + huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 8001192: 4b0d ldr r3, [pc, #52] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>) + 8001194: 2200 movs r2, #0 + 8001196: 619a str r2, [r3, #24] + huart6.Init.OverSampling = UART_OVERSAMPLING_16; + 8001198: 4b0b ldr r3, [pc, #44] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>) + 800119a: 2200 movs r2, #0 + 800119c: 61da str r2, [r3, #28] + huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 800119e: 4b0a ldr r3, [pc, #40] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>) + 80011a0: 2200 movs r2, #0 + 80011a2: 621a str r2, [r3, #32] + huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 80011a4: 4b08 ldr r3, [pc, #32] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>) + 80011a6: 2200 movs r2, #0 + 80011a8: 625a str r2, [r3, #36] ; 0x24 + if (HAL_UART_Init(&huart6) != HAL_OK) + 80011aa: 4807 ldr r0, [pc, #28] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>) + 80011ac: f003 fa78 bl 80046a0 + 80011b0: 4603 mov r3, r0 + 80011b2: 2b00 cmp r3, #0 + 80011b4: bf14 ite ne + 80011b6: 2301 movne r3, #1 + 80011b8: 2300 moveq r3, #0 + 80011ba: b2db uxtb r3, r3 + 80011bc: 2b00 cmp r3, #0 + 80011be: d001 beq.n 80011c4 <_ZL19MX_USART6_UART_Initv+0x5c> + { + Error_Handler(); + 80011c0: f000 fb00 bl 80017c4 + } + /* USER CODE BEGIN USART6_Init 2 */ + + /* USER CODE END USART6_Init 2 */ + +} + 80011c4: bf00 nop + 80011c6: bd80 pop {r7, pc} + 80011c8: 2000016c .word 0x2000016c + 80011cc: 40011400 .word 0x40011400 + +080011d0 <_ZL12MX_GPIO_Initv>: + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 80011d0: b580 push {r7, lr} + 80011d2: b08c sub sp, #48 ; 0x30 + 80011d4: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80011d6: f107 031c add.w r3, r7, #28 + 80011da: 2200 movs r2, #0 + 80011dc: 601a str r2, [r3, #0] + 80011de: 605a str r2, [r3, #4] + 80011e0: 609a str r2, [r3, #8] + 80011e2: 60da str r2, [r3, #12] + 80011e4: 611a str r2, [r3, #16] + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 80011e6: 4b5e ldr r3, [pc, #376] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>) + 80011e8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80011ea: 4a5d ldr r2, [pc, #372] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>) + 80011ec: f043 0304 orr.w r3, r3, #4 + 80011f0: 6313 str r3, [r2, #48] ; 0x30 + 80011f2: 4b5b ldr r3, [pc, #364] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>) + 80011f4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80011f6: f003 0304 and.w r3, r3, #4 + 80011fa: 61bb str r3, [r7, #24] + 80011fc: 69bb ldr r3, [r7, #24] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80011fe: 4b58 ldr r3, [pc, #352] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>) + 8001200: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001202: 4a57 ldr r2, [pc, #348] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>) + 8001204: f043 0301 orr.w r3, r3, #1 + 8001208: 6313 str r3, [r2, #48] ; 0x30 + 800120a: 4b55 ldr r3, [pc, #340] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>) + 800120c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800120e: f003 0301 and.w r3, r3, #1 + 8001212: 617b str r3, [r7, #20] + 8001214: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOF_CLK_ENABLE(); + 8001216: 4b52 ldr r3, [pc, #328] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>) + 8001218: 6b1b ldr r3, [r3, #48] ; 0x30 + 800121a: 4a51 ldr r2, [pc, #324] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>) + 800121c: f043 0320 orr.w r3, r3, #32 + 8001220: 6313 str r3, [r2, #48] ; 0x30 + 8001222: 4b4f ldr r3, [pc, #316] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>) + 8001224: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001226: f003 0320 and.w r3, r3, #32 + 800122a: 613b str r3, [r7, #16] + 800122c: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOE_CLK_ENABLE(); + 800122e: 4b4c ldr r3, [pc, #304] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>) + 8001230: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001232: 4a4b ldr r2, [pc, #300] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>) + 8001234: f043 0310 orr.w r3, r3, #16 + 8001238: 6313 str r3, [r2, #48] ; 0x30 + 800123a: 4b49 ldr r3, [pc, #292] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>) + 800123c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800123e: f003 0310 and.w r3, r3, #16 + 8001242: 60fb str r3, [r7, #12] + 8001244: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOD_CLK_ENABLE(); + 8001246: 4b46 ldr r3, [pc, #280] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>) + 8001248: 6b1b ldr r3, [r3, #48] ; 0x30 + 800124a: 4a45 ldr r2, [pc, #276] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>) + 800124c: f043 0308 orr.w r3, r3, #8 + 8001250: 6313 str r3, [r2, #48] ; 0x30 + 8001252: 4b43 ldr r3, [pc, #268] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>) + 8001254: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001256: f003 0308 and.w r3, r3, #8 + 800125a: 60bb str r3, [r7, #8] + 800125c: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 800125e: 4b40 ldr r3, [pc, #256] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>) + 8001260: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001262: 4a3f ldr r2, [pc, #252] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>) + 8001264: f043 0302 orr.w r3, r3, #2 + 8001268: 6313 str r3, [r2, #48] ; 0x30 + 800126a: 4b3d ldr r3, [pc, #244] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>) + 800126c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800126e: f003 0302 and.w r3, r3, #2 + 8001272: 607b str r3, [r7, #4] + 8001274: 687b ldr r3, [r7, #4] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOF, dir2_Pin|dir1_Pin, GPIO_PIN_RESET); + 8001276: 2200 movs r2, #0 + 8001278: f44f 5140 mov.w r1, #12288 ; 0x3000 + 800127c: 4839 ldr r0, [pc, #228] ; (8001364 <_ZL12MX_GPIO_Initv+0x194>) + 800127e: f001 f88d bl 800239c + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOF, sleep2_Pin|sleep1_Pin, GPIO_PIN_SET); + 8001282: 2201 movs r2, #1 + 8001284: f44f 4140 mov.w r1, #49152 ; 0xc000 + 8001288: 4836 ldr r0, [pc, #216] ; (8001364 <_ZL12MX_GPIO_Initv+0x194>) + 800128a: f001 f887 bl 800239c + + /*Configure GPIO pin : user_button_Pin */ + GPIO_InitStruct.Pin = user_button_Pin; + 800128e: f44f 5300 mov.w r3, #8192 ; 0x2000 + 8001292: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + 8001294: 4b34 ldr r3, [pc, #208] ; (8001368 <_ZL12MX_GPIO_Initv+0x198>) + 8001296: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001298: 2300 movs r3, #0 + 800129a: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(user_button_GPIO_Port, &GPIO_InitStruct); + 800129c: f107 031c add.w r3, r7, #28 + 80012a0: 4619 mov r1, r3 + 80012a2: 4832 ldr r0, [pc, #200] ; (800136c <_ZL12MX_GPIO_Initv+0x19c>) + 80012a4: f000 fed0 bl 8002048 + + /*Configure GPIO pin : current2_Pin */ + GPIO_InitStruct.Pin = current2_Pin; + 80012a8: 2301 movs r3, #1 + 80012aa: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 80012ac: 2303 movs r3, #3 + 80012ae: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80012b0: 2300 movs r3, #0 + 80012b2: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(current2_GPIO_Port, &GPIO_InitStruct); + 80012b4: f107 031c add.w r3, r7, #28 + 80012b8: 4619 mov r1, r3 + 80012ba: 482c ldr r0, [pc, #176] ; (800136c <_ZL12MX_GPIO_Initv+0x19c>) + 80012bc: f000 fec4 bl 8002048 + + /*Configure GPIO pin : current1_Pin */ + GPIO_InitStruct.Pin = current1_Pin; + 80012c0: 2308 movs r3, #8 + 80012c2: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 80012c4: 2303 movs r3, #3 + 80012c6: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80012c8: 2300 movs r3, #0 + 80012ca: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(current1_GPIO_Port, &GPIO_InitStruct); + 80012cc: f107 031c add.w r3, r7, #28 + 80012d0: 4619 mov r1, r3 + 80012d2: 4827 ldr r0, [pc, #156] ; (8001370 <_ZL12MX_GPIO_Initv+0x1a0>) + 80012d4: f000 feb8 bl 8002048 + + /*Configure GPIO pin : fault2_Pin */ + GPIO_InitStruct.Pin = fault2_Pin; + 80012d8: 2340 movs r3, #64 ; 0x40 + 80012da: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 80012dc: 2300 movs r3, #0 + 80012de: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80012e0: 2300 movs r3, #0 + 80012e2: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(fault2_GPIO_Port, &GPIO_InitStruct); + 80012e4: f107 031c add.w r3, r7, #28 + 80012e8: 4619 mov r1, r3 + 80012ea: 4821 ldr r0, [pc, #132] ; (8001370 <_ZL12MX_GPIO_Initv+0x1a0>) + 80012ec: f000 feac bl 8002048 + + /*Configure GPIO pins : dir2_Pin dir1_Pin */ + GPIO_InitStruct.Pin = dir2_Pin|dir1_Pin; + 80012f0: f44f 5340 mov.w r3, #12288 ; 0x3000 + 80012f4: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 80012f6: 2301 movs r3, #1 + 80012f8: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80012fa: 2300 movs r3, #0 + 80012fc: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80012fe: 2300 movs r3, #0 + 8001300: 62bb str r3, [r7, #40] ; 0x28 + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + 8001302: f107 031c add.w r3, r7, #28 + 8001306: 4619 mov r1, r3 + 8001308: 4816 ldr r0, [pc, #88] ; (8001364 <_ZL12MX_GPIO_Initv+0x194>) + 800130a: f000 fe9d bl 8002048 + + /*Configure GPIO pins : sleep2_Pin sleep1_Pin */ + GPIO_InitStruct.Pin = sleep2_Pin|sleep1_Pin; + 800130e: f44f 4340 mov.w r3, #49152 ; 0xc000 + 8001312: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8001314: 2301 movs r3, #1 + 8001316: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 8001318: 2301 movs r3, #1 + 800131a: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800131c: 2300 movs r3, #0 + 800131e: 62bb str r3, [r7, #40] ; 0x28 + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + 8001320: f107 031c add.w r3, r7, #28 + 8001324: 4619 mov r1, r3 + 8001326: 480f ldr r0, [pc, #60] ; (8001364 <_ZL12MX_GPIO_Initv+0x194>) + 8001328: f000 fe8e bl 8002048 + + /*Configure GPIO pin : fault1_Pin */ + GPIO_InitStruct.Pin = fault1_Pin; + 800132c: f44f 7300 mov.w r3, #512 ; 0x200 + 8001330: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8001332: 2300 movs r3, #0 + 8001334: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001336: 2300 movs r3, #0 + 8001338: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(fault1_GPIO_Port, &GPIO_InitStruct); + 800133a: f107 031c add.w r3, r7, #28 + 800133e: 4619 mov r1, r3 + 8001340: 480c ldr r0, [pc, #48] ; (8001374 <_ZL12MX_GPIO_Initv+0x1a4>) + 8001342: f000 fe81 bl 8002048 + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); + 8001346: 2200 movs r2, #0 + 8001348: 2100 movs r1, #0 + 800134a: 2028 movs r0, #40 ; 0x28 + 800134c: f000 fe23 bl 8001f96 + HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); + 8001350: 2028 movs r0, #40 ; 0x28 + 8001352: f000 fe3c bl 8001fce + +} + 8001356: bf00 nop + 8001358: 3730 adds r7, #48 ; 0x30 + 800135a: 46bd mov sp, r7 + 800135c: bd80 pop {r7, pc} + 800135e: bf00 nop + 8001360: 40023800 .word 0x40023800 + 8001364: 40021400 .word 0x40021400 + 8001368: 10110000 .word 0x10110000 + 800136c: 40020800 .word 0x40020800 + 8001370: 40020000 .word 0x40020000 + 8001374: 40021000 .word 0x40021000 + +08001378 : + +/* USER CODE BEGIN 4 */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { + 8001378: b580 push {r7, lr} + 800137a: b084 sub sp, #16 + 800137c: af00 add r7, sp, #0 + 800137e: 6078 str r0, [r7, #4] + + //TIMER 100Hz PID control + if (htim->Instance == TIM3) { + 8001380: 687b ldr r3, [r7, #4] + 8001382: 681b ldr r3, [r3, #0] + 8001384: 4a62 ldr r2, [pc, #392] ; (8001510 ) + 8001386: 4293 cmp r3, r2 + 8001388: f040 80be bne.w 8001508 + + if (mode == 1) { + 800138c: 4b61 ldr r3, [pc, #388] ; (8001514 ) + 800138e: edd3 7a00 vldr s15, [r3] + 8001392: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 + 8001396: eef4 7a47 vcmp.f32 s15, s14 + 800139a: eef1 fa10 vmrs APSR_nzcv, fpscr + 800139e: d123 bne.n 80013e8 + left_velocity = left_encoder.GetLinearVelocity(); + 80013a0: 485d ldr r0, [pc, #372] ; (8001518 ) + 80013a2: f7ff f937 bl 8000614 <_ZN7Encoder17GetLinearVelocityEv> + 80013a6: eef0 7a40 vmov.f32 s15, s0 + 80013aa: 4b5c ldr r3, [pc, #368] ; (800151c ) + 80013ac: edc3 7a00 vstr s15, [r3] + output_msg.velocity = left_velocity; + 80013b0: 4b5a ldr r3, [pc, #360] ; (800151c ) + 80013b2: 681b ldr r3, [r3, #0] + 80013b4: 4a5a ldr r2, [pc, #360] ; (8001520 ) + 80013b6: 6013 str r3, [r2, #0] + left_dutycycle = left_pid.update(left_velocity); + 80013b8: 4b58 ldr r3, [pc, #352] ; (800151c ) + 80013ba: edd3 7a00 vldr s15, [r3] + 80013be: eeb0 0a67 vmov.f32 s0, s15 + 80013c2: 4858 ldr r0, [pc, #352] ; (8001524 ) + 80013c4: f7ff fb8c bl 8000ae0 <_ZN3Pid6updateEf> + 80013c8: 4602 mov r2, r0 + 80013ca: 4b57 ldr r3, [pc, #348] ; (8001528 ) + 80013cc: 601a str r2, [r3, #0] + left_motor.set_speed(left_dutycycle); + 80013ce: 4b56 ldr r3, [pc, #344] ; (8001528 ) + 80013d0: 681b ldr r3, [r3, #0] + 80013d2: 4619 mov r1, r3 + 80013d4: 4855 ldr r0, [pc, #340] ; (800152c ) + 80013d6: f7ff f9e1 bl 800079c <_ZN15MotorController9set_speedEi> + HAL_UART_Transmit(&huart6, tx_buffer, 4, 100); + 80013da: 4b55 ldr r3, [pc, #340] ; (8001530 ) + 80013dc: 6819 ldr r1, [r3, #0] + 80013de: 2364 movs r3, #100 ; 0x64 + 80013e0: 2204 movs r2, #4 + 80013e2: 4854 ldr r0, [pc, #336] ; (8001534 ) + 80013e4: f003 f9aa bl 800473c + + } + if (mode == 2) { + 80013e8: 4b4a ldr r3, [pc, #296] ; (8001514 ) + 80013ea: edd3 7a00 vldr s15, [r3] + 80013ee: eeb0 7a00 vmov.f32 s14, #0 ; 0x40000000 2.0 + 80013f2: eef4 7a47 vcmp.f32 s15, s14 + 80013f6: eef1 fa10 vmrs APSR_nzcv, fpscr + 80013fa: d123 bne.n 8001444 + right_velocity = right_encoder.GetLinearVelocity(); + 80013fc: 484e ldr r0, [pc, #312] ; (8001538 ) + 80013fe: f7ff f909 bl 8000614 <_ZN7Encoder17GetLinearVelocityEv> + 8001402: eef0 7a40 vmov.f32 s15, s0 + 8001406: 4b4d ldr r3, [pc, #308] ; (800153c ) + 8001408: edc3 7a00 vstr s15, [r3] + output_msg.velocity = right_velocity; + 800140c: 4b4b ldr r3, [pc, #300] ; (800153c ) + 800140e: 681b ldr r3, [r3, #0] + 8001410: 4a43 ldr r2, [pc, #268] ; (8001520 ) + 8001412: 6013 str r3, [r2, #0] + right_dutycycle = right_pid.update(right_velocity); + 8001414: 4b49 ldr r3, [pc, #292] ; (800153c ) + 8001416: edd3 7a00 vldr s15, [r3] + 800141a: eeb0 0a67 vmov.f32 s0, s15 + 800141e: 4848 ldr r0, [pc, #288] ; (8001540 ) + 8001420: f7ff fb5e bl 8000ae0 <_ZN3Pid6updateEf> + 8001424: 4602 mov r2, r0 + 8001426: 4b47 ldr r3, [pc, #284] ; (8001544 ) + 8001428: 601a str r2, [r3, #0] + right_motor.set_speed(right_dutycycle); + 800142a: 4b46 ldr r3, [pc, #280] ; (8001544 ) + 800142c: 681b ldr r3, [r3, #0] + 800142e: 4619 mov r1, r3 + 8001430: 4845 ldr r0, [pc, #276] ; (8001548 ) + 8001432: f7ff f9b3 bl 800079c <_ZN15MotorController9set_speedEi> + HAL_UART_Transmit(&huart6, tx_buffer, 4, 100); + 8001436: 4b3e ldr r3, [pc, #248] ; (8001530 ) + 8001438: 6819 ldr r1, [r3, #0] + 800143a: 2364 movs r3, #100 ; 0x64 + 800143c: 2204 movs r2, #4 + 800143e: 483d ldr r0, [pc, #244] ; (8001534 ) + 8001440: f003 f97c bl 800473c + } + if (mode == 3) { + 8001444: 4b33 ldr r3, [pc, #204] ; (8001514 ) + 8001446: edd3 7a00 vldr s15, [r3] + 800144a: eeb0 7a08 vmov.f32 s14, #8 ; 0x40400000 3.0 + 800144e: eef4 7a47 vcmp.f32 s15, s14 + 8001452: eef1 fa10 vmrs APSR_nzcv, fpscr + 8001456: d157 bne.n 8001508 + + left_velocity = left_encoder.GetLinearVelocity(); + 8001458: 482f ldr r0, [pc, #188] ; (8001518 ) + 800145a: f7ff f8db bl 8000614 <_ZN7Encoder17GetLinearVelocityEv> + 800145e: eef0 7a40 vmov.f32 s15, s0 + 8001462: 4b2e ldr r3, [pc, #184] ; (800151c ) + 8001464: edc3 7a00 vstr s15, [r3] + left_dutycycle = left_pid.update(left_velocity); + 8001468: 4b2c ldr r3, [pc, #176] ; (800151c ) + 800146a: edd3 7a00 vldr s15, [r3] + 800146e: eeb0 0a67 vmov.f32 s0, s15 + 8001472: 482c ldr r0, [pc, #176] ; (8001524 ) + 8001474: f7ff fb34 bl 8000ae0 <_ZN3Pid6updateEf> + 8001478: 4602 mov r2, r0 + 800147a: 4b2b ldr r3, [pc, #172] ; (8001528 ) + 800147c: 601a str r2, [r3, #0] + left_motor.set_speed(left_dutycycle); + 800147e: 4b2a ldr r3, [pc, #168] ; (8001528 ) + 8001480: 681b ldr r3, [r3, #0] + 8001482: 4619 mov r1, r3 + 8001484: 4829 ldr r0, [pc, #164] ; (800152c ) + 8001486: f7ff f989 bl 800079c <_ZN15MotorController9set_speedEi> + + right_velocity = right_encoder.GetLinearVelocity(); + 800148a: 482b ldr r0, [pc, #172] ; (8001538 ) + 800148c: f7ff f8c2 bl 8000614 <_ZN7Encoder17GetLinearVelocityEv> + 8001490: eef0 7a40 vmov.f32 s15, s0 + 8001494: 4b29 ldr r3, [pc, #164] ; (800153c ) + 8001496: edc3 7a00 vstr s15, [r3] + right_dutycycle = right_pid.update(right_velocity); + 800149a: 4b28 ldr r3, [pc, #160] ; (800153c ) + 800149c: edd3 7a00 vldr s15, [r3] + 80014a0: eeb0 0a67 vmov.f32 s0, s15 + 80014a4: 4826 ldr r0, [pc, #152] ; (8001540 ) + 80014a6: f7ff fb1b bl 8000ae0 <_ZN3Pid6updateEf> + 80014aa: 4602 mov r2, r0 + 80014ac: 4b25 ldr r3, [pc, #148] ; (8001544 ) + 80014ae: 601a str r2, [r3, #0] + right_motor.set_speed(right_dutycycle); + 80014b0: 4b24 ldr r3, [pc, #144] ; (8001544 ) + 80014b2: 681b ldr r3, [r3, #0] + 80014b4: 4619 mov r1, r3 + 80014b6: 4824 ldr r0, [pc, #144] ; (8001548 ) + 80014b8: f7ff f970 bl 800079c <_ZN15MotorController9set_speedEi> + + float difference = left_velocity - right_velocity; + 80014bc: 4b17 ldr r3, [pc, #92] ; (800151c ) + 80014be: ed93 7a00 vldr s14, [r3] + 80014c2: 4b1e ldr r3, [pc, #120] ; (800153c ) + 80014c4: edd3 7a00 vldr s15, [r3] + 80014c8: ee77 7a67 vsub.f32 s15, s14, s15 + 80014cc: edc7 7a03 vstr s15, [r7, #12] + + int cross_dutycycle = cross_pid.update(difference); + 80014d0: ed97 0a03 vldr s0, [r7, #12] + 80014d4: 481d ldr r0, [pc, #116] ; (800154c ) + 80014d6: f7ff fb03 bl 8000ae0 <_ZN3Pid6updateEf> + 80014da: 60b8 str r0, [r7, #8] + + left_dutycycle += cross_dutycycle; + 80014dc: 4b12 ldr r3, [pc, #72] ; (8001528 ) + 80014de: 681a ldr r2, [r3, #0] + 80014e0: 68bb ldr r3, [r7, #8] + 80014e2: 4413 add r3, r2 + 80014e4: 4a10 ldr r2, [pc, #64] ; (8001528 ) + 80014e6: 6013 str r3, [r2, #0] + right_dutycycle -= cross_dutycycle; + 80014e8: 4b16 ldr r3, [pc, #88] ; (8001544 ) + 80014ea: 681a ldr r2, [r3, #0] + 80014ec: 68bb ldr r3, [r7, #8] + 80014ee: 1ad3 subs r3, r2, r3 + 80014f0: 4a14 ldr r2, [pc, #80] ; (8001544 ) + 80014f2: 6013 str r3, [r2, #0] + + output_msg.velocity = difference; + 80014f4: 4a0a ldr r2, [pc, #40] ; (8001520 ) + 80014f6: 68fb ldr r3, [r7, #12] + 80014f8: 6013 str r3, [r2, #0] + HAL_UART_Transmit(&huart6, tx_buffer, 4, 100); + 80014fa: 4b0d ldr r3, [pc, #52] ; (8001530 ) + 80014fc: 6819 ldr r1, [r3, #0] + 80014fe: 2364 movs r3, #100 ; 0x64 + 8001500: 2204 movs r2, #4 + 8001502: 480c ldr r0, [pc, #48] ; (8001534 ) + 8001504: f003 f91a bl 800473c + } + + //TIMER 2Hz Transmit + if (htim->Instance == TIM6) { + } +} + 8001508: bf00 nop + 800150a: 3710 adds r7, #16 + 800150c: 46bd mov sp, r7 + 800150e: bd80 pop {r7, pc} + 8001510: 40000400 .word 0x40000400 + 8001514: 20000304 .word 0x20000304 + 8001518: 20000200 .word 0x20000200 + 800151c: 2000021c .word 0x2000021c + 8001520: 200002f8 .word 0x200002f8 + 8001524: 20000224 .word 0x20000224 + 8001528: 2000029c .word 0x2000029c + 800152c: 200002bc .word 0x200002bc + 8001530: 200002d4 .word 0x200002d4 + 8001534: 2000016c .word 0x2000016c + 8001538: 200001ec .word 0x200001ec + 800153c: 20000220 .word 0x20000220 + 8001540: 20000248 .word 0x20000248 + 8001544: 200002a0 .word 0x200002a0 + 8001548: 200002a4 .word 0x200002a4 + 800154c: 2000026c .word 0x2000026c + +08001550 : + +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *UartHandle) { + 8001550: b580 push {r7, lr} + 8001552: b082 sub sp, #8 + 8001554: af00 add r7, sp, #0 + 8001556: 6078 str r0, [r7, #4] + + if (input_msg.pid_select == 1) { + 8001558: 4b6b ldr r3, [pc, #428] ; (8001708 ) + 800155a: edd3 7a00 vldr s15, [r3] + 800155e: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 + 8001562: eef4 7a47 vcmp.f32 s15, s14 + 8001566: eef1 fa10 vmrs APSR_nzcv, fpscr + 800156a: d11a bne.n 80015a2 + + left_pid.config(input_msg.pid_kp, input_msg.pid_ki, input_msg.pid_kd); + 800156c: 4b66 ldr r3, [pc, #408] ; (8001708 ) + 800156e: edd3 7a04 vldr s15, [r3, #16] + 8001572: 4b65 ldr r3, [pc, #404] ; (8001708 ) + 8001574: ed93 7a05 vldr s14, [r3, #20] + 8001578: 4b63 ldr r3, [pc, #396] ; (8001708 ) + 800157a: edd3 6a06 vldr s13, [r3, #24] + 800157e: eeb0 1a66 vmov.f32 s2, s13 + 8001582: eef0 0a47 vmov.f32 s1, s14 + 8001586: eeb0 0a67 vmov.f32 s0, s15 + 800158a: 4860 ldr r0, [pc, #384] ; (800170c ) + 800158c: f7ff fa70 bl 8000a70 <_ZN3Pid6configEfff> + left_pid.set(input_msg.pid_setpoint_fixed); + 8001590: 4b5d ldr r3, [pc, #372] ; (8001708 ) + 8001592: edd3 7a01 vldr s15, [r3, #4] + 8001596: eeb0 0a67 vmov.f32 s0, s15 + 800159a: 485c ldr r0, [pc, #368] ; (800170c ) + 800159c: f7ff fa91 bl 8000ac2 <_ZN3Pid3setEf> + + cross_setpoint = left_setpoint - right_setpoint; + cross_pid.set(cross_setpoint); + } + +} + 80015a0: e0a8 b.n 80016f4 + } else if (input_msg.pid_select == 2) { + 80015a2: 4b59 ldr r3, [pc, #356] ; (8001708 ) + 80015a4: edd3 7a00 vldr s15, [r3] + 80015a8: eeb0 7a00 vmov.f32 s14, #0 ; 0x40000000 2.0 + 80015ac: eef4 7a47 vcmp.f32 s15, s14 + 80015b0: eef1 fa10 vmrs APSR_nzcv, fpscr + 80015b4: d11a bne.n 80015ec + right_pid.config(input_msg.pid_kp, input_msg.pid_ki, input_msg.pid_kd); + 80015b6: 4b54 ldr r3, [pc, #336] ; (8001708 ) + 80015b8: edd3 7a04 vldr s15, [r3, #16] + 80015bc: 4b52 ldr r3, [pc, #328] ; (8001708 ) + 80015be: ed93 7a05 vldr s14, [r3, #20] + 80015c2: 4b51 ldr r3, [pc, #324] ; (8001708 ) + 80015c4: edd3 6a06 vldr s13, [r3, #24] + 80015c8: eeb0 1a66 vmov.f32 s2, s13 + 80015cc: eef0 0a47 vmov.f32 s1, s14 + 80015d0: eeb0 0a67 vmov.f32 s0, s15 + 80015d4: 484e ldr r0, [pc, #312] ; (8001710 ) + 80015d6: f7ff fa4b bl 8000a70 <_ZN3Pid6configEfff> + right_pid.set(input_msg.pid_setpoint_fixed); + 80015da: 4b4b ldr r3, [pc, #300] ; (8001708 ) + 80015dc: edd3 7a01 vldr s15, [r3, #4] + 80015e0: eeb0 0a67 vmov.f32 s0, s15 + 80015e4: 484a ldr r0, [pc, #296] ; (8001710 ) + 80015e6: f7ff fa6c bl 8000ac2 <_ZN3Pid3setEf> +} + 80015ea: e083 b.n 80016f4 + } else if (input_msg.pid_select == 3) { + 80015ec: 4b46 ldr r3, [pc, #280] ; (8001708 ) + 80015ee: edd3 7a00 vldr s15, [r3] + 80015f2: eeb0 7a08 vmov.f32 s14, #8 ; 0x40400000 3.0 + 80015f6: eef4 7a47 vcmp.f32 s15, s14 + 80015fa: eef1 fa10 vmrs APSR_nzcv, fpscr + 80015fe: d179 bne.n 80016f4 + left_pid.config(180, 200, 0); + 8001600: ed9f 1a44 vldr s2, [pc, #272] ; 8001714 + 8001604: eddf 0a44 vldr s1, [pc, #272] ; 8001718 + 8001608: ed9f 0a44 vldr s0, [pc, #272] ; 800171c + 800160c: 483f ldr r0, [pc, #252] ; (800170c ) + 800160e: f7ff fa2f bl 8000a70 <_ZN3Pid6configEfff> + right_pid.config(185, 195, 0); + 8001612: ed9f 1a40 vldr s2, [pc, #256] ; 8001714 + 8001616: eddf 0a42 vldr s1, [pc, #264] ; 8001720 + 800161a: ed9f 0a42 vldr s0, [pc, #264] ; 8001724 + 800161e: 483c ldr r0, [pc, #240] ; (8001710 ) + 8001620: f7ff fa26 bl 8000a70 <_ZN3Pid6configEfff> + cross_pid.config(input_msg.pid_kp, input_msg.pid_ki, input_msg.pid_kd); + 8001624: 4b38 ldr r3, [pc, #224] ; (8001708 ) + 8001626: edd3 7a04 vldr s15, [r3, #16] + 800162a: 4b37 ldr r3, [pc, #220] ; (8001708 ) + 800162c: ed93 7a05 vldr s14, [r3, #20] + 8001630: 4b35 ldr r3, [pc, #212] ; (8001708 ) + 8001632: edd3 6a06 vldr s13, [r3, #24] + 8001636: eeb0 1a66 vmov.f32 s2, s13 + 800163a: eef0 0a47 vmov.f32 s1, s14 + 800163e: eeb0 0a67 vmov.f32 s0, s15 + 8001642: 4839 ldr r0, [pc, #228] ; (8001728 ) + 8001644: f7ff fa14 bl 8000a70 <_ZN3Pid6configEfff> + odom.UpdateValues(input_msg.pid_setpoint_lin, input_msg.pid_setpoint_ang); + 8001648: 4b2f ldr r3, [pc, #188] ; (8001708 ) + 800164a: edd3 7a02 vldr s15, [r3, #8] + 800164e: 4b2e ldr r3, [pc, #184] ; (8001708 ) + 8001650: ed93 7a03 vldr s14, [r3, #12] + 8001654: eef0 0a47 vmov.f32 s1, s14 + 8001658: eeb0 0a67 vmov.f32 s0, s15 + 800165c: 4833 ldr r0, [pc, #204] ; (800172c ) + 800165e: f7ff f833 bl 80006c8 <_ZN8Odometry12UpdateValuesEff> + left_setpoint = input_msg.pid_setpoint_lin + 8001662: 4b29 ldr r3, [pc, #164] ; (8001708 ) + 8001664: edd3 7a02 vldr s15, [r3, #8] + 8001668: eeb7 6ae7 vcvt.f64.f32 d6, s15 + - (BASELINE * input_msg.pid_setpoint_ang) / 2; + 800166c: 4b26 ldr r3, [pc, #152] ; (8001708 ) + 800166e: edd3 7a03 vldr s15, [r3, #12] + 8001672: eeb7 7ae7 vcvt.f64.f32 d7, s15 + 8001676: ed9f 5b22 vldr d5, [pc, #136] ; 8001700 + 800167a: ee27 5b05 vmul.f64 d5, d7, d5 + 800167e: eeb0 4b00 vmov.f64 d4, #0 ; 0x40000000 2.0 + 8001682: ee85 7b04 vdiv.f64 d7, d5, d4 + 8001686: ee36 7b47 vsub.f64 d7, d6, d7 + 800168a: eef7 7bc7 vcvt.f32.f64 s15, d7 + left_setpoint = input_msg.pid_setpoint_lin + 800168e: 4b28 ldr r3, [pc, #160] ; (8001730 ) + 8001690: edc3 7a00 vstr s15, [r3] + right_setpoint = 2 * input_msg.pid_setpoint_lin - left_setpoint; + 8001694: 4b1c ldr r3, [pc, #112] ; (8001708 ) + 8001696: edd3 7a02 vldr s15, [r3, #8] + 800169a: ee37 7aa7 vadd.f32 s14, s15, s15 + 800169e: 4b24 ldr r3, [pc, #144] ; (8001730 ) + 80016a0: edd3 7a00 vldr s15, [r3] + 80016a4: ee77 7a67 vsub.f32 s15, s14, s15 + 80016a8: 4b22 ldr r3, [pc, #136] ; (8001734 ) + 80016aa: edc3 7a00 vstr s15, [r3] + left_pid.set(left_setpoint); + 80016ae: 4b20 ldr r3, [pc, #128] ; (8001730 ) + 80016b0: edd3 7a00 vldr s15, [r3] + 80016b4: eeb0 0a67 vmov.f32 s0, s15 + 80016b8: 4814 ldr r0, [pc, #80] ; (800170c ) + 80016ba: f7ff fa02 bl 8000ac2 <_ZN3Pid3setEf> + right_pid.set(right_setpoint); + 80016be: 4b1d ldr r3, [pc, #116] ; (8001734 ) + 80016c0: edd3 7a00 vldr s15, [r3] + 80016c4: eeb0 0a67 vmov.f32 s0, s15 + 80016c8: 4811 ldr r0, [pc, #68] ; (8001710 ) + 80016ca: f7ff f9fa bl 8000ac2 <_ZN3Pid3setEf> + cross_setpoint = left_setpoint - right_setpoint; + 80016ce: 4b18 ldr r3, [pc, #96] ; (8001730 ) + 80016d0: ed93 7a00 vldr s14, [r3] + 80016d4: 4b17 ldr r3, [pc, #92] ; (8001734 ) + 80016d6: edd3 7a00 vldr s15, [r3] + 80016da: ee77 7a67 vsub.f32 s15, s14, s15 + 80016de: 4b16 ldr r3, [pc, #88] ; (8001738 ) + 80016e0: edc3 7a00 vstr s15, [r3] + cross_pid.set(cross_setpoint); + 80016e4: 4b14 ldr r3, [pc, #80] ; (8001738 ) + 80016e6: edd3 7a00 vldr s15, [r3] + 80016ea: eeb0 0a67 vmov.f32 s0, s15 + 80016ee: 480e ldr r0, [pc, #56] ; (8001728 ) + 80016f0: f7ff f9e7 bl 8000ac2 <_ZN3Pid3setEf> +} + 80016f4: bf00 nop + 80016f6: 3708 adds r7, #8 + 80016f8: 46bd mov sp, r7 + 80016fa: bd80 pop {r7, pc} + 80016fc: f3af 8000 nop.w + 8001700: 33333333 .word 0x33333333 + 8001704: 3fd33333 .word 0x3fd33333 + 8001708: 200002dc .word 0x200002dc + 800170c: 20000224 .word 0x20000224 + 8001710: 20000248 .word 0x20000248 + 8001714: 00000000 .word 0x00000000 + 8001718: 43480000 .word 0x43480000 + 800171c: 43340000 .word 0x43340000 + 8001720: 43430000 .word 0x43430000 + 8001724: 43390000 .word 0x43390000 + 8001728: 2000026c .word 0x2000026c + 800172c: 20000214 .word 0x20000214 + 8001730: 20000290 .word 0x20000290 + 8001734: 20000294 .word 0x20000294 + 8001738: 20000298 .word 0x20000298 + +0800173c : + +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { + 800173c: b580 push {r7, lr} + 800173e: b082 sub sp, #8 + 8001740: af00 add r7, sp, #0 + 8001742: 4603 mov r3, r0 + 8001744: 80fb strh r3, [r7, #6] + //Blue user button + if (GPIO_Pin == GPIO_PIN_13) { + 8001746: 88fb ldrh r3, [r7, #6] + 8001748: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 800174c: d12a bne.n 80017a4 + previous_millis = current_millis; + 800174e: 4b17 ldr r3, [pc, #92] ; (80017ac ) + 8001750: 681b ldr r3, [r3, #0] + 8001752: 4a17 ldr r2, [pc, #92] ; (80017b0 ) + 8001754: 6013 str r3, [r2, #0] + current_millis = HAL_GetTick(); + 8001756: f000 fb37 bl 8001dc8 + 800175a: 4603 mov r3, r0 + 800175c: 461a mov r2, r3 + 800175e: 4b13 ldr r3, [pc, #76] ; (80017ac ) + 8001760: 601a str r2, [r3, #0] + if (current_millis - previous_millis < 200) + 8001762: 4b12 ldr r3, [pc, #72] ; (80017ac ) + 8001764: 681a ldr r2, [r3, #0] + 8001766: 4b12 ldr r3, [pc, #72] ; (80017b0 ) + 8001768: 681b ldr r3, [r3, #0] + 800176a: 1ad3 subs r3, r2, r3 + 800176c: 2bc7 cmp r3, #199 ; 0xc7 + 800176e: dc03 bgt.n 8001778 + debounce = false; + 8001770: 4b10 ldr r3, [pc, #64] ; (80017b4 ) + 8001772: 2200 movs r2, #0 + 8001774: 701a strb r2, [r3, #0] + 8001776: e002 b.n 800177e + else + debounce = true; + 8001778: 4b0e ldr r3, [pc, #56] ; (80017b4 ) + 800177a: 2201 movs r2, #1 + 800177c: 701a strb r2, [r3, #0] + if (mode == 0 && debounce) { + 800177e: 4b0e ldr r3, [pc, #56] ; (80017b8 ) + 8001780: edd3 7a00 vldr s15, [r3] + 8001784: eef5 7a40 vcmp.f32 s15, #0.0 + 8001788: eef1 fa10 vmrs APSR_nzcv, fpscr + 800178c: d10a bne.n 80017a4 + 800178e: 4b09 ldr r3, [pc, #36] ; (80017b4 ) + 8001790: 781b ldrb r3, [r3, #0] + 8001792: 2b00 cmp r3, #0 + 8001794: d006 beq.n 80017a4 + mode = input_msg.pid_select; + 8001796: 4b09 ldr r3, [pc, #36] ; (80017bc ) + 8001798: 681b ldr r3, [r3, #0] + 800179a: 4a07 ldr r2, [pc, #28] ; (80017b8 ) + 800179c: 6013 str r3, [r2, #0] + //Enables TIM3 interrupt (used for PID control) + HAL_TIM_Base_Start_IT(&htim3); + 800179e: 4808 ldr r0, [pc, #32] ; (80017c0 ) + 80017a0: f001 fec0 bl 8003524 + } + } +} + 80017a4: bf00 nop + 80017a6: 3708 adds r7, #8 + 80017a8: 46bd mov sp, r7 + 80017aa: bd80 pop {r7, pc} + 80017ac: 20000300 .word 0x20000300 + 80017b0: 200002fc .word 0x200002fc + 80017b4: 20000000 .word 0x20000000 + 80017b8: 20000304 .word 0x20000304 + 80017bc: 200002dc .word 0x200002dc + 80017c0: 2000006c .word 0x2000006c + +080017c4 : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 80017c4: b480 push {r7} + 80017c6: af00 add r7, sp, #0 + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} + 80017c8: bf00 nop + 80017ca: 46bd mov sp, r7 + 80017cc: f85d 7b04 ldr.w r7, [sp], #4 + 80017d0: 4770 bx lr + ... + +080017d4 <_Z41__static_initialization_and_destruction_0ii>: + 80017d4: b580 push {r7, lr} + 80017d6: b086 sub sp, #24 + 80017d8: af04 add r7, sp, #16 + 80017da: 6078 str r0, [r7, #4] + 80017dc: 6039 str r1, [r7, #0] + 80017de: 687b ldr r3, [r7, #4] + 80017e0: 2b01 cmp r3, #1 + 80017e2: d14a bne.n 800187a <_Z41__static_initialization_and_destruction_0ii+0xa6> + 80017e4: 683b ldr r3, [r7, #0] + 80017e6: f64f 72ff movw r2, #65535 ; 0xffff + 80017ea: 4293 cmp r3, r2 + 80017ec: d145 bne.n 800187a <_Z41__static_initialization_and_destruction_0ii+0xa6> +Encoder right_encoder = Encoder(&htim5, RIGHT_WHEEL_CIRCUMFERENCE); + 80017ee: ed9f 0a25 vldr s0, [pc, #148] ; 8001884 <_Z41__static_initialization_and_destruction_0ii+0xb0> + 80017f2: 4925 ldr r1, [pc, #148] ; (8001888 <_Z41__static_initialization_and_destruction_0ii+0xb4>) + 80017f4: 4825 ldr r0, [pc, #148] ; (800188c <_Z41__static_initialization_and_destruction_0ii+0xb8>) + 80017f6: f7fe fec6 bl 8000586 <_ZN7EncoderC1EP17TIM_HandleTypeDeff> +Encoder left_encoder = Encoder(&htim2, LEFT_WHEEL_CIRCUMFERENCE); + 80017fa: ed9f 0a25 vldr s0, [pc, #148] ; 8001890 <_Z41__static_initialization_and_destruction_0ii+0xbc> + 80017fe: 4925 ldr r1, [pc, #148] ; (8001894 <_Z41__static_initialization_and_destruction_0ii+0xc0>) + 8001800: 4825 ldr r0, [pc, #148] ; (8001898 <_Z41__static_initialization_and_destruction_0ii+0xc4>) + 8001802: f7fe fec0 bl 8000586 <_ZN7EncoderC1EP17TIM_HandleTypeDeff> +Odometry odom = Odometry(); + 8001806: 4825 ldr r0, [pc, #148] ; (800189c <_Z41__static_initialization_and_destruction_0ii+0xc8>) + 8001808: f7fe ff4a bl 80006a0 <_ZN8OdometryC1Ev> +Pid left_pid(0, 0, 0); + 800180c: ed9f 1a24 vldr s2, [pc, #144] ; 80018a0 <_Z41__static_initialization_and_destruction_0ii+0xcc> + 8001810: eddf 0a23 vldr s1, [pc, #140] ; 80018a0 <_Z41__static_initialization_and_destruction_0ii+0xcc> + 8001814: ed9f 0a22 vldr s0, [pc, #136] ; 80018a0 <_Z41__static_initialization_and_destruction_0ii+0xcc> + 8001818: 4822 ldr r0, [pc, #136] ; (80018a4 <_Z41__static_initialization_and_destruction_0ii+0xd0>) + 800181a: f7ff f8f5 bl 8000a08 <_ZN3PidC1Efff> +Pid right_pid(0, 0, 0); + 800181e: ed9f 1a20 vldr s2, [pc, #128] ; 80018a0 <_Z41__static_initialization_and_destruction_0ii+0xcc> + 8001822: eddf 0a1f vldr s1, [pc, #124] ; 80018a0 <_Z41__static_initialization_and_destruction_0ii+0xcc> + 8001826: ed9f 0a1e vldr s0, [pc, #120] ; 80018a0 <_Z41__static_initialization_and_destruction_0ii+0xcc> + 800182a: 481f ldr r0, [pc, #124] ; (80018a8 <_Z41__static_initialization_and_destruction_0ii+0xd4>) + 800182c: f7ff f8ec bl 8000a08 <_ZN3PidC1Efff> +Pid cross_pid(0, 0, 0); + 8001830: ed9f 1a1b vldr s2, [pc, #108] ; 80018a0 <_Z41__static_initialization_and_destruction_0ii+0xcc> + 8001834: eddf 0a1a vldr s1, [pc, #104] ; 80018a0 <_Z41__static_initialization_and_destruction_0ii+0xcc> + 8001838: ed9f 0a19 vldr s0, [pc, #100] ; 80018a0 <_Z41__static_initialization_and_destruction_0ii+0xcc> + 800183c: 481b ldr r0, [pc, #108] ; (80018ac <_Z41__static_initialization_and_destruction_0ii+0xd8>) + 800183e: f7ff f8e3 bl 8000a08 <_ZN3PidC1Efff> + TIM_CHANNEL_4); + 8001842: 230c movs r3, #12 + 8001844: 9302 str r3, [sp, #8] + 8001846: 4b1a ldr r3, [pc, #104] ; (80018b0 <_Z41__static_initialization_and_destruction_0ii+0xdc>) + 8001848: 9301 str r3, [sp, #4] + 800184a: f44f 5300 mov.w r3, #8192 ; 0x2000 + 800184e: 9300 str r3, [sp, #0] + 8001850: 4b18 ldr r3, [pc, #96] ; (80018b4 <_Z41__static_initialization_and_destruction_0ii+0xe0>) + 8001852: f44f 4200 mov.w r2, #32768 ; 0x8000 + 8001856: 4917 ldr r1, [pc, #92] ; (80018b4 <_Z41__static_initialization_and_destruction_0ii+0xe0>) + 8001858: 4817 ldr r0, [pc, #92] ; (80018b8 <_Z41__static_initialization_and_destruction_0ii+0xe4>) + 800185a: f7fe ff6d bl 8000738 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm> + TIM_CHANNEL_3); + 800185e: 2308 movs r3, #8 + 8001860: 9302 str r3, [sp, #8] + 8001862: 4b13 ldr r3, [pc, #76] ; (80018b0 <_Z41__static_initialization_and_destruction_0ii+0xdc>) + 8001864: 9301 str r3, [sp, #4] + 8001866: f44f 5380 mov.w r3, #4096 ; 0x1000 + 800186a: 9300 str r3, [sp, #0] + 800186c: 4b11 ldr r3, [pc, #68] ; (80018b4 <_Z41__static_initialization_and_destruction_0ii+0xe0>) + 800186e: f44f 4280 mov.w r2, #16384 ; 0x4000 + 8001872: 4910 ldr r1, [pc, #64] ; (80018b4 <_Z41__static_initialization_and_destruction_0ii+0xe0>) + 8001874: 4811 ldr r0, [pc, #68] ; (80018bc <_Z41__static_initialization_and_destruction_0ii+0xe8>) + 8001876: f7fe ff5f bl 8000738 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm> +} + 800187a: bf00 nop + 800187c: 3708 adds r7, #8 + 800187e: 46bd mov sp, r7 + 8001880: bd80 pop {r7, pc} + 8001882: bf00 nop + 8001884: 3f4ccccd .word 0x3f4ccccd + 8001888: 200000ec .word 0x200000ec + 800188c: 200001ec .word 0x200001ec + 8001890: 3f47ae14 .word 0x3f47ae14 + 8001894: 2000002c .word 0x2000002c + 8001898: 20000200 .word 0x20000200 + 800189c: 20000214 .word 0x20000214 + 80018a0: 00000000 .word 0x00000000 + 80018a4: 20000224 .word 0x20000224 + 80018a8: 20000248 .word 0x20000248 + 80018ac: 2000026c .word 0x2000026c + 80018b0: 200000ac .word 0x200000ac + 80018b4: 40021400 .word 0x40021400 + 80018b8: 200002a4 .word 0x200002a4 + 80018bc: 200002bc .word 0x200002bc + +080018c0 <_GLOBAL__sub_I_htim2>: + 80018c0: b580 push {r7, lr} + 80018c2: af00 add r7, sp, #0 + 80018c4: f64f 71ff movw r1, #65535 ; 0xffff + 80018c8: 2001 movs r0, #1 + 80018ca: f7ff ff83 bl 80017d4 <_Z41__static_initialization_and_destruction_0ii> + 80018ce: bd80 pop {r7, pc} + +080018d0 : +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 80018d0: b480 push {r7} + 80018d2: b083 sub sp, #12 + 80018d4: af00 add r7, sp, #0 + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_PWR_CLK_ENABLE(); + 80018d6: 4b0f ldr r3, [pc, #60] ; (8001914 ) + 80018d8: 6c1b ldr r3, [r3, #64] ; 0x40 + 80018da: 4a0e ldr r2, [pc, #56] ; (8001914 ) + 80018dc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 80018e0: 6413 str r3, [r2, #64] ; 0x40 + 80018e2: 4b0c ldr r3, [pc, #48] ; (8001914 ) + 80018e4: 6c1b ldr r3, [r3, #64] ; 0x40 + 80018e6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 80018ea: 607b str r3, [r7, #4] + 80018ec: 687b ldr r3, [r7, #4] + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 80018ee: 4b09 ldr r3, [pc, #36] ; (8001914 ) + 80018f0: 6c5b ldr r3, [r3, #68] ; 0x44 + 80018f2: 4a08 ldr r2, [pc, #32] ; (8001914 ) + 80018f4: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 80018f8: 6453 str r3, [r2, #68] ; 0x44 + 80018fa: 4b06 ldr r3, [pc, #24] ; (8001914 ) + 80018fc: 6c5b ldr r3, [r3, #68] ; 0x44 + 80018fe: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8001902: 603b str r3, [r7, #0] + 8001904: 683b ldr r3, [r7, #0] + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8001906: bf00 nop + 8001908: 370c adds r7, #12 + 800190a: 46bd mov sp, r7 + 800190c: f85d 7b04 ldr.w r7, [sp], #4 + 8001910: 4770 bx lr + 8001912: bf00 nop + 8001914: 40023800 .word 0x40023800 + +08001918 : +* This function configures the hardware resources used in this example +* @param htim_encoder: TIM_Encoder handle pointer +* @retval None +*/ +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder) +{ + 8001918: b580 push {r7, lr} + 800191a: b08c sub sp, #48 ; 0x30 + 800191c: af00 add r7, sp, #0 + 800191e: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8001920: f107 031c add.w r3, r7, #28 + 8001924: 2200 movs r2, #0 + 8001926: 601a str r2, [r3, #0] + 8001928: 605a str r2, [r3, #4] + 800192a: 609a str r2, [r3, #8] + 800192c: 60da str r2, [r3, #12] + 800192e: 611a str r2, [r3, #16] + if(htim_encoder->Instance==TIM2) + 8001930: 687b ldr r3, [r7, #4] + 8001932: 681b ldr r3, [r3, #0] + 8001934: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 8001938: d144 bne.n 80019c4 + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + 800193a: 4b3b ldr r3, [pc, #236] ; (8001a28 ) + 800193c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800193e: 4a3a ldr r2, [pc, #232] ; (8001a28 ) + 8001940: f043 0301 orr.w r3, r3, #1 + 8001944: 6413 str r3, [r2, #64] ; 0x40 + 8001946: 4b38 ldr r3, [pc, #224] ; (8001a28 ) + 8001948: 6c1b ldr r3, [r3, #64] ; 0x40 + 800194a: f003 0301 and.w r3, r3, #1 + 800194e: 61bb str r3, [r7, #24] + 8001950: 69bb ldr r3, [r7, #24] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8001952: 4b35 ldr r3, [pc, #212] ; (8001a28 ) + 8001954: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001956: 4a34 ldr r2, [pc, #208] ; (8001a28 ) + 8001958: f043 0301 orr.w r3, r3, #1 + 800195c: 6313 str r3, [r2, #48] ; 0x30 + 800195e: 4b32 ldr r3, [pc, #200] ; (8001a28 ) + 8001960: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001962: f003 0301 and.w r3, r3, #1 + 8001966: 617b str r3, [r7, #20] + 8001968: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 800196a: 4b2f ldr r3, [pc, #188] ; (8001a28 ) + 800196c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800196e: 4a2e ldr r2, [pc, #184] ; (8001a28 ) + 8001970: f043 0302 orr.w r3, r3, #2 + 8001974: 6313 str r3, [r2, #48] ; 0x30 + 8001976: 4b2c ldr r3, [pc, #176] ; (8001a28 ) + 8001978: 6b1b ldr r3, [r3, #48] ; 0x30 + 800197a: f003 0302 and.w r3, r3, #2 + 800197e: 613b str r3, [r7, #16] + 8001980: 693b ldr r3, [r7, #16] + /**TIM2 GPIO Configuration + PA5 ------> TIM2_CH1 + PB3 ------> TIM2_CH2 + */ + GPIO_InitStruct.Pin = encoder_sx1_Pin; + 8001982: 2320 movs r3, #32 + 8001984: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001986: 2302 movs r3, #2 + 8001988: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800198a: 2300 movs r3, #0 + 800198c: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800198e: 2300 movs r3, #0 + 8001990: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; + 8001992: 2301 movs r3, #1 + 8001994: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(encoder_sx1_GPIO_Port, &GPIO_InitStruct); + 8001996: f107 031c add.w r3, r7, #28 + 800199a: 4619 mov r1, r3 + 800199c: 4823 ldr r0, [pc, #140] ; (8001a2c ) + 800199e: f000 fb53 bl 8002048 + + GPIO_InitStruct.Pin = encoder_sx2_Pin; + 80019a2: 2308 movs r3, #8 + 80019a4: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80019a6: 2302 movs r3, #2 + 80019a8: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80019aa: 2300 movs r3, #0 + 80019ac: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80019ae: 2300 movs r3, #0 + 80019b0: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; + 80019b2: 2301 movs r3, #1 + 80019b4: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(encoder_sx2_GPIO_Port, &GPIO_InitStruct); + 80019b6: f107 031c add.w r3, r7, #28 + 80019ba: 4619 mov r1, r3 + 80019bc: 481c ldr r0, [pc, #112] ; (8001a30 ) + 80019be: f000 fb43 bl 8002048 + /* USER CODE BEGIN TIM5_MspInit 1 */ + + /* USER CODE END TIM5_MspInit 1 */ + } + +} + 80019c2: e02c b.n 8001a1e + else if(htim_encoder->Instance==TIM5) + 80019c4: 687b ldr r3, [r7, #4] + 80019c6: 681b ldr r3, [r3, #0] + 80019c8: 4a1a ldr r2, [pc, #104] ; (8001a34 ) + 80019ca: 4293 cmp r3, r2 + 80019cc: d127 bne.n 8001a1e + __HAL_RCC_TIM5_CLK_ENABLE(); + 80019ce: 4b16 ldr r3, [pc, #88] ; (8001a28 ) + 80019d0: 6c1b ldr r3, [r3, #64] ; 0x40 + 80019d2: 4a15 ldr r2, [pc, #84] ; (8001a28 ) + 80019d4: f043 0308 orr.w r3, r3, #8 + 80019d8: 6413 str r3, [r2, #64] ; 0x40 + 80019da: 4b13 ldr r3, [pc, #76] ; (8001a28 ) + 80019dc: 6c1b ldr r3, [r3, #64] ; 0x40 + 80019de: f003 0308 and.w r3, r3, #8 + 80019e2: 60fb str r3, [r7, #12] + 80019e4: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80019e6: 4b10 ldr r3, [pc, #64] ; (8001a28 ) + 80019e8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80019ea: 4a0f ldr r2, [pc, #60] ; (8001a28 ) + 80019ec: f043 0301 orr.w r3, r3, #1 + 80019f0: 6313 str r3, [r2, #48] ; 0x30 + 80019f2: 4b0d ldr r3, [pc, #52] ; (8001a28 ) + 80019f4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80019f6: f003 0301 and.w r3, r3, #1 + 80019fa: 60bb str r3, [r7, #8] + 80019fc: 68bb ldr r3, [r7, #8] + GPIO_InitStruct.Pin = encoder_dx1_Pin|encoder_dx2_Pin; + 80019fe: 2303 movs r3, #3 + 8001a00: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001a02: 2302 movs r3, #2 + 8001a04: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001a06: 2300 movs r3, #0 + 8001a08: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001a0a: 2300 movs r3, #0 + 8001a0c: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Alternate = GPIO_AF2_TIM5; + 8001a0e: 2302 movs r3, #2 + 8001a10: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8001a12: f107 031c add.w r3, r7, #28 + 8001a16: 4619 mov r1, r3 + 8001a18: 4804 ldr r0, [pc, #16] ; (8001a2c ) + 8001a1a: f000 fb15 bl 8002048 +} + 8001a1e: bf00 nop + 8001a20: 3730 adds r7, #48 ; 0x30 + 8001a22: 46bd mov sp, r7 + 8001a24: bd80 pop {r7, pc} + 8001a26: bf00 nop + 8001a28: 40023800 .word 0x40023800 + 8001a2c: 40020000 .word 0x40020000 + 8001a30: 40020400 .word 0x40020400 + 8001a34: 40000c00 .word 0x40000c00 + +08001a38 : +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + 8001a38: b480 push {r7} + 8001a3a: b087 sub sp, #28 + 8001a3c: af00 add r7, sp, #0 + 8001a3e: 6078 str r0, [r7, #4] + if(htim_base->Instance==TIM3) + 8001a40: 687b ldr r3, [r7, #4] + 8001a42: 681b ldr r3, [r3, #0] + 8001a44: 4a1c ldr r2, [pc, #112] ; (8001ab8 ) + 8001a46: 4293 cmp r3, r2 + 8001a48: d10c bne.n 8001a64 + { + /* USER CODE BEGIN TIM3_MspInit 0 */ + + /* USER CODE END TIM3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM3_CLK_ENABLE(); + 8001a4a: 4b1c ldr r3, [pc, #112] ; (8001abc ) + 8001a4c: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001a4e: 4a1b ldr r2, [pc, #108] ; (8001abc ) + 8001a50: f043 0302 orr.w r3, r3, #2 + 8001a54: 6413 str r3, [r2, #64] ; 0x40 + 8001a56: 4b19 ldr r3, [pc, #100] ; (8001abc ) + 8001a58: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001a5a: f003 0302 and.w r3, r3, #2 + 8001a5e: 617b str r3, [r7, #20] + 8001a60: 697b ldr r3, [r7, #20] + /* USER CODE BEGIN TIM6_MspInit 1 */ + + /* USER CODE END TIM6_MspInit 1 */ + } + +} + 8001a62: e022 b.n 8001aaa + else if(htim_base->Instance==TIM4) + 8001a64: 687b ldr r3, [r7, #4] + 8001a66: 681b ldr r3, [r3, #0] + 8001a68: 4a15 ldr r2, [pc, #84] ; (8001ac0 ) + 8001a6a: 4293 cmp r3, r2 + 8001a6c: d10c bne.n 8001a88 + __HAL_RCC_TIM4_CLK_ENABLE(); + 8001a6e: 4b13 ldr r3, [pc, #76] ; (8001abc ) + 8001a70: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001a72: 4a12 ldr r2, [pc, #72] ; (8001abc ) + 8001a74: f043 0304 orr.w r3, r3, #4 + 8001a78: 6413 str r3, [r2, #64] ; 0x40 + 8001a7a: 4b10 ldr r3, [pc, #64] ; (8001abc ) + 8001a7c: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001a7e: f003 0304 and.w r3, r3, #4 + 8001a82: 613b str r3, [r7, #16] + 8001a84: 693b ldr r3, [r7, #16] +} + 8001a86: e010 b.n 8001aaa + else if(htim_base->Instance==TIM6) + 8001a88: 687b ldr r3, [r7, #4] + 8001a8a: 681b ldr r3, [r3, #0] + 8001a8c: 4a0d ldr r2, [pc, #52] ; (8001ac4 ) + 8001a8e: 4293 cmp r3, r2 + 8001a90: d10b bne.n 8001aaa + __HAL_RCC_TIM6_CLK_ENABLE(); + 8001a92: 4b0a ldr r3, [pc, #40] ; (8001abc ) + 8001a94: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001a96: 4a09 ldr r2, [pc, #36] ; (8001abc ) + 8001a98: f043 0310 orr.w r3, r3, #16 + 8001a9c: 6413 str r3, [r2, #64] ; 0x40 + 8001a9e: 4b07 ldr r3, [pc, #28] ; (8001abc ) + 8001aa0: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001aa2: f003 0310 and.w r3, r3, #16 + 8001aa6: 60fb str r3, [r7, #12] + 8001aa8: 68fb ldr r3, [r7, #12] +} + 8001aaa: bf00 nop + 8001aac: 371c adds r7, #28 + 8001aae: 46bd mov sp, r7 + 8001ab0: f85d 7b04 ldr.w r7, [sp], #4 + 8001ab4: 4770 bx lr + 8001ab6: bf00 nop + 8001ab8: 40000400 .word 0x40000400 + 8001abc: 40023800 .word 0x40023800 + 8001ac0: 40000800 .word 0x40000800 + 8001ac4: 40001000 .word 0x40001000 + +08001ac8 : + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + 8001ac8: b580 push {r7, lr} + 8001aca: b088 sub sp, #32 + 8001acc: af00 add r7, sp, #0 + 8001ace: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8001ad0: f107 030c add.w r3, r7, #12 + 8001ad4: 2200 movs r2, #0 + 8001ad6: 601a str r2, [r3, #0] + 8001ad8: 605a str r2, [r3, #4] + 8001ada: 609a str r2, [r3, #8] + 8001adc: 60da str r2, [r3, #12] + 8001ade: 611a str r2, [r3, #16] + if(htim->Instance==TIM4) + 8001ae0: 687b ldr r3, [r7, #4] + 8001ae2: 681b ldr r3, [r3, #0] + 8001ae4: 4a11 ldr r2, [pc, #68] ; (8001b2c ) + 8001ae6: 4293 cmp r3, r2 + 8001ae8: d11c bne.n 8001b24 + { + /* USER CODE BEGIN TIM4_MspPostInit 0 */ + + /* USER CODE END TIM4_MspPostInit 0 */ + + __HAL_RCC_GPIOD_CLK_ENABLE(); + 8001aea: 4b11 ldr r3, [pc, #68] ; (8001b30 ) + 8001aec: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001aee: 4a10 ldr r2, [pc, #64] ; (8001b30 ) + 8001af0: f043 0308 orr.w r3, r3, #8 + 8001af4: 6313 str r3, [r2, #48] ; 0x30 + 8001af6: 4b0e ldr r3, [pc, #56] ; (8001b30 ) + 8001af8: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001afa: f003 0308 and.w r3, r3, #8 + 8001afe: 60bb str r3, [r7, #8] + 8001b00: 68bb ldr r3, [r7, #8] + /**TIM4 GPIO Configuration + PD14 ------> TIM4_CH3 + PD15 ------> TIM4_CH4 + */ + GPIO_InitStruct.Pin = pwm2_Pin|pwm1_Pin; + 8001b02: f44f 4340 mov.w r3, #49152 ; 0xc000 + 8001b06: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001b08: 2302 movs r3, #2 + 8001b0a: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001b0c: 2300 movs r3, #0 + 8001b0e: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001b10: 2300 movs r3, #0 + 8001b12: 61bb str r3, [r7, #24] + GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; + 8001b14: 2302 movs r3, #2 + 8001b16: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 8001b18: f107 030c add.w r3, r7, #12 + 8001b1c: 4619 mov r1, r3 + 8001b1e: 4805 ldr r0, [pc, #20] ; (8001b34 ) + 8001b20: f000 fa92 bl 8002048 + /* USER CODE BEGIN TIM4_MspPostInit 1 */ + + /* USER CODE END TIM4_MspPostInit 1 */ + } + +} + 8001b24: bf00 nop + 8001b26: 3720 adds r7, #32 + 8001b28: 46bd mov sp, r7 + 8001b2a: bd80 pop {r7, pc} + 8001b2c: 40000800 .word 0x40000800 + 8001b30: 40023800 .word 0x40023800 + 8001b34: 40020c00 .word 0x40020c00 + +08001b38 : +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + 8001b38: b580 push {r7, lr} + 8001b3a: b08a sub sp, #40 ; 0x28 + 8001b3c: af00 add r7, sp, #0 + 8001b3e: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8001b40: f107 0314 add.w r3, r7, #20 + 8001b44: 2200 movs r2, #0 + 8001b46: 601a str r2, [r3, #0] + 8001b48: 605a str r2, [r3, #4] + 8001b4a: 609a str r2, [r3, #8] + 8001b4c: 60da str r2, [r3, #12] + 8001b4e: 611a str r2, [r3, #16] + if(huart->Instance==USART6) + 8001b50: 687b ldr r3, [r7, #4] + 8001b52: 681b ldr r3, [r3, #0] + 8001b54: 4a17 ldr r2, [pc, #92] ; (8001bb4 ) + 8001b56: 4293 cmp r3, r2 + 8001b58: d127 bne.n 8001baa + { + /* USER CODE BEGIN USART6_MspInit 0 */ + + /* USER CODE END USART6_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART6_CLK_ENABLE(); + 8001b5a: 4b17 ldr r3, [pc, #92] ; (8001bb8 ) + 8001b5c: 6c5b ldr r3, [r3, #68] ; 0x44 + 8001b5e: 4a16 ldr r2, [pc, #88] ; (8001bb8 ) + 8001b60: f043 0320 orr.w r3, r3, #32 + 8001b64: 6453 str r3, [r2, #68] ; 0x44 + 8001b66: 4b14 ldr r3, [pc, #80] ; (8001bb8 ) + 8001b68: 6c5b ldr r3, [r3, #68] ; 0x44 + 8001b6a: f003 0320 and.w r3, r3, #32 + 8001b6e: 613b str r3, [r7, #16] + 8001b70: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8001b72: 4b11 ldr r3, [pc, #68] ; (8001bb8 ) + 8001b74: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001b76: 4a10 ldr r2, [pc, #64] ; (8001bb8 ) + 8001b78: f043 0304 orr.w r3, r3, #4 + 8001b7c: 6313 str r3, [r2, #48] ; 0x30 + 8001b7e: 4b0e ldr r3, [pc, #56] ; (8001bb8 ) + 8001b80: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001b82: f003 0304 and.w r3, r3, #4 + 8001b86: 60fb str r3, [r7, #12] + 8001b88: 68fb ldr r3, [r7, #12] + /**USART6 GPIO Configuration + PC6 ------> USART6_TX + PC7 ------> USART6_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + 8001b8a: 23c0 movs r3, #192 ; 0xc0 + 8001b8c: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001b8e: 2302 movs r3, #2 + 8001b90: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001b92: 2300 movs r3, #0 + 8001b94: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8001b96: 2303 movs r3, #3 + 8001b98: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF8_USART6; + 8001b9a: 2308 movs r3, #8 + 8001b9c: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 8001b9e: f107 0314 add.w r3, r7, #20 + 8001ba2: 4619 mov r1, r3 + 8001ba4: 4805 ldr r0, [pc, #20] ; (8001bbc ) + 8001ba6: f000 fa4f bl 8002048 + /* USER CODE BEGIN USART6_MspInit 1 */ + + /* USER CODE END USART6_MspInit 1 */ + } + +} + 8001baa: bf00 nop + 8001bac: 3728 adds r7, #40 ; 0x28 + 8001bae: 46bd mov sp, r7 + 8001bb0: bd80 pop {r7, pc} + 8001bb2: bf00 nop + 8001bb4: 40011400 .word 0x40011400 + 8001bb8: 40023800 .word 0x40023800 + 8001bbc: 40020800 .word 0x40020800 + +08001bc0 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 8001bc0: b480 push {r7} + 8001bc2: af00 add r7, sp, #0 + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + 8001bc4: bf00 nop + 8001bc6: 46bd mov sp, r7 + 8001bc8: f85d 7b04 ldr.w r7, [sp], #4 + 8001bcc: 4770 bx lr + +08001bce : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 8001bce: b480 push {r7} + 8001bd0: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8001bd2: e7fe b.n 8001bd2 + +08001bd4 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 8001bd4: b480 push {r7} + 8001bd6: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 8001bd8: e7fe b.n 8001bd8 + +08001bda : + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 8001bda: b480 push {r7} + 8001bdc: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 8001bde: e7fe b.n 8001bde + +08001be0 : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 8001be0: b480 push {r7} + 8001be2: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8001be4: e7fe b.n 8001be4 + +08001be6 : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 8001be6: b480 push {r7} + 8001be8: af00 add r7, sp, #0 + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + 8001bea: bf00 nop + 8001bec: 46bd mov sp, r7 + 8001bee: f85d 7b04 ldr.w r7, [sp], #4 + 8001bf2: 4770 bx lr + +08001bf4 : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 8001bf4: b480 push {r7} + 8001bf6: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 8001bf8: bf00 nop + 8001bfa: 46bd mov sp, r7 + 8001bfc: f85d 7b04 ldr.w r7, [sp], #4 + 8001c00: 4770 bx lr + +08001c02 : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8001c02: b480 push {r7} + 8001c04: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8001c06: bf00 nop + 8001c08: 46bd mov sp, r7 + 8001c0a: f85d 7b04 ldr.w r7, [sp], #4 + 8001c0e: 4770 bx lr + +08001c10 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 8001c10: b580 push {r7, lr} + 8001c12: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 8001c14: f000 f8c4 bl 8001da0 + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8001c18: bf00 nop + 8001c1a: bd80 pop {r7, pc} + +08001c1c : + +/** + * @brief This function handles TIM3 global interrupt. + */ +void TIM3_IRQHandler(void) +{ + 8001c1c: b580 push {r7, lr} + 8001c1e: af00 add r7, sp, #0 + /* USER CODE BEGIN TIM3_IRQn 0 */ + + /* USER CODE END TIM3_IRQn 0 */ + HAL_TIM_IRQHandler(&htim3); + 8001c20: 4802 ldr r0, [pc, #8] ; (8001c2c ) + 8001c22: f001 fdec bl 80037fe + /* USER CODE BEGIN TIM3_IRQn 1 */ + + /* USER CODE END TIM3_IRQn 1 */ +} + 8001c26: bf00 nop + 8001c28: bd80 pop {r7, pc} + 8001c2a: bf00 nop + 8001c2c: 2000006c .word 0x2000006c + +08001c30 : + +/** + * @brief This function handles EXTI line[15:10] interrupts. + */ +void EXTI15_10_IRQHandler(void) +{ + 8001c30: b580 push {r7, lr} + 8001c32: af00 add r7, sp, #0 + /* USER CODE BEGIN EXTI15_10_IRQn 0 */ + + /* USER CODE END EXTI15_10_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13); + 8001c34: f44f 5000 mov.w r0, #8192 ; 0x2000 + 8001c38: f000 fbca bl 80023d0 + /* USER CODE BEGIN EXTI15_10_IRQn 1 */ + + /* USER CODE END EXTI15_10_IRQn 1 */ +} + 8001c3c: bf00 nop + 8001c3e: bd80 pop {r7, pc} + +08001c40 : + +/** + * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts. + */ +void TIM6_DAC_IRQHandler(void) +{ + 8001c40: b580 push {r7, lr} + 8001c42: af00 add r7, sp, #0 + /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ + + /* USER CODE END TIM6_DAC_IRQn 0 */ + HAL_TIM_IRQHandler(&htim6); + 8001c44: 4802 ldr r0, [pc, #8] ; (8001c50 ) + 8001c46: f001 fdda bl 80037fe + /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ + + /* USER CODE END TIM6_DAC_IRQn 1 */ +} + 8001c4a: bf00 nop + 8001c4c: bd80 pop {r7, pc} + 8001c4e: bf00 nop + 8001c50: 2000012c .word 0x2000012c + +08001c54 : + +/** + * @brief This function handles USART6 global interrupt. + */ +void USART6_IRQHandler(void) +{ + 8001c54: b580 push {r7, lr} + 8001c56: af00 add r7, sp, #0 + /* USER CODE BEGIN USART6_IRQn 0 */ + + /* USER CODE END USART6_IRQn 0 */ + HAL_UART_IRQHandler(&huart6); + 8001c58: 4802 ldr r0, [pc, #8] ; (8001c64 ) + 8001c5a: f002 fea3 bl 80049a4 + /* USER CODE BEGIN USART6_IRQn 1 */ + + /* USER CODE END USART6_IRQn 1 */ +} + 8001c5e: bf00 nop + 8001c60: bd80 pop {r7, pc} + 8001c62: bf00 nop + 8001c64: 2000016c .word 0x2000016c + +08001c68 : + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + 8001c68: b480 push {r7} + 8001c6a: af00 add r7, sp, #0 + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + 8001c6c: 4b15 ldr r3, [pc, #84] ; (8001cc4 ) + 8001c6e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8001c72: 4a14 ldr r2, [pc, #80] ; (8001cc4 ) + 8001c74: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 + 8001c78: f8c2 3088 str.w r3, [r2, #136] ; 0x88 + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + 8001c7c: 4b12 ldr r3, [pc, #72] ; (8001cc8 ) + 8001c7e: 681b ldr r3, [r3, #0] + 8001c80: 4a11 ldr r2, [pc, #68] ; (8001cc8 ) + 8001c82: f043 0301 orr.w r3, r3, #1 + 8001c86: 6013 str r3, [r2, #0] + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + 8001c88: 4b0f ldr r3, [pc, #60] ; (8001cc8 ) + 8001c8a: 2200 movs r2, #0 + 8001c8c: 609a str r2, [r3, #8] + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + 8001c8e: 4b0e ldr r3, [pc, #56] ; (8001cc8 ) + 8001c90: 681a ldr r2, [r3, #0] + 8001c92: 490d ldr r1, [pc, #52] ; (8001cc8 ) + 8001c94: 4b0d ldr r3, [pc, #52] ; (8001ccc ) + 8001c96: 4013 ands r3, r2 + 8001c98: 600b str r3, [r1, #0] + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + 8001c9a: 4b0b ldr r3, [pc, #44] ; (8001cc8 ) + 8001c9c: 4a0c ldr r2, [pc, #48] ; (8001cd0 ) + 8001c9e: 605a str r2, [r3, #4] + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + 8001ca0: 4b09 ldr r3, [pc, #36] ; (8001cc8 ) + 8001ca2: 681b ldr r3, [r3, #0] + 8001ca4: 4a08 ldr r2, [pc, #32] ; (8001cc8 ) + 8001ca6: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8001caa: 6013 str r3, [r2, #0] + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + 8001cac: 4b06 ldr r3, [pc, #24] ; (8001cc8 ) + 8001cae: 2200 movs r2, #0 + 8001cb0: 60da str r2, [r3, #12] + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + 8001cb2: 4b04 ldr r3, [pc, #16] ; (8001cc4 ) + 8001cb4: f04f 6200 mov.w r2, #134217728 ; 0x8000000 + 8001cb8: 609a str r2, [r3, #8] +#endif +} + 8001cba: bf00 nop + 8001cbc: 46bd mov sp, r7 + 8001cbe: f85d 7b04 ldr.w r7, [sp], #4 + 8001cc2: 4770 bx lr + 8001cc4: e000ed00 .word 0xe000ed00 + 8001cc8: 40023800 .word 0x40023800 + 8001ccc: fef6ffff .word 0xfef6ffff + 8001cd0: 24003010 .word 0x24003010 + +08001cd4 : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + 8001cd4: f8df d034 ldr.w sp, [pc, #52] ; 8001d0c + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + 8001cd8: 2100 movs r1, #0 + b LoopCopyDataInit + 8001cda: e003 b.n 8001ce4 + +08001cdc : + +CopyDataInit: + ldr r3, =_sidata + 8001cdc: 4b0c ldr r3, [pc, #48] ; (8001d10 ) + ldr r3, [r3, r1] + 8001cde: 585b ldr r3, [r3, r1] + str r3, [r0, r1] + 8001ce0: 5043 str r3, [r0, r1] + adds r1, r1, #4 + 8001ce2: 3104 adds r1, #4 + +08001ce4 : + +LoopCopyDataInit: + ldr r0, =_sdata + 8001ce4: 480b ldr r0, [pc, #44] ; (8001d14 ) + ldr r3, =_edata + 8001ce6: 4b0c ldr r3, [pc, #48] ; (8001d18 ) + adds r2, r0, r1 + 8001ce8: 1842 adds r2, r0, r1 + cmp r2, r3 + 8001cea: 429a cmp r2, r3 + bcc CopyDataInit + 8001cec: d3f6 bcc.n 8001cdc + ldr r2, =_sbss + 8001cee: 4a0b ldr r2, [pc, #44] ; (8001d1c ) + b LoopFillZerobss + 8001cf0: e002 b.n 8001cf8 + +08001cf2 : +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + 8001cf2: 2300 movs r3, #0 + str r3, [r2], #4 + 8001cf4: f842 3b04 str.w r3, [r2], #4 + +08001cf8 : + +LoopFillZerobss: + ldr r3, = _ebss + 8001cf8: 4b09 ldr r3, [pc, #36] ; (8001d20 ) + cmp r2, r3 + 8001cfa: 429a cmp r2, r3 + bcc FillZerobss + 8001cfc: d3f9 bcc.n 8001cf2 + +/* Call the clock system initialization function.*/ + bl SystemInit + 8001cfe: f7ff ffb3 bl 8001c68 +/* Call static constructors */ + bl __libc_init_array + 8001d02: f003 fc31 bl 8005568 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 8001d06: f7fe ff43 bl 8000b90
+ bx lr + 8001d0a: 4770 bx lr + ldr sp, =_estack /* set stack pointer */ + 8001d0c: 20080000 .word 0x20080000 + ldr r3, =_sidata + 8001d10: 08005604 .word 0x08005604 + ldr r0, =_sdata + 8001d14: 20000000 .word 0x20000000 + ldr r3, =_edata + 8001d18: 20000010 .word 0x20000010 + ldr r2, =_sbss + 8001d1c: 20000010 .word 0x20000010 + ldr r3, = _ebss + 8001d20: 2000030c .word 0x2000030c + +08001d24 : + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8001d24: e7fe b.n 8001d24 + +08001d26 : + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8001d26: b580 push {r7, lr} + 8001d28: af00 add r7, sp, #0 +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8001d2a: 2003 movs r0, #3 + 8001d2c: f000 f928 bl 8001f80 + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + 8001d30: 2000 movs r0, #0 + 8001d32: f000 f805 bl 8001d40 + + /* Init the low level hardware */ + HAL_MspInit(); + 8001d36: f7ff fdcb bl 80018d0 + + /* Return function status */ + return HAL_OK; + 8001d3a: 2300 movs r3, #0 +} + 8001d3c: 4618 mov r0, r3 + 8001d3e: bd80 pop {r7, pc} + +08001d40 : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8001d40: b580 push {r7, lr} + 8001d42: b082 sub sp, #8 + 8001d44: af00 add r7, sp, #0 + 8001d46: 6078 str r0, [r7, #4] + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + 8001d48: 4b12 ldr r3, [pc, #72] ; (8001d94 ) + 8001d4a: 681a ldr r2, [r3, #0] + 8001d4c: 4b12 ldr r3, [pc, #72] ; (8001d98 ) + 8001d4e: 781b ldrb r3, [r3, #0] + 8001d50: 4619 mov r1, r3 + 8001d52: f44f 737a mov.w r3, #1000 ; 0x3e8 + 8001d56: fbb3 f3f1 udiv r3, r3, r1 + 8001d5a: fbb2 f3f3 udiv r3, r2, r3 + 8001d5e: 4618 mov r0, r3 + 8001d60: f000 f943 bl 8001fea + 8001d64: 4603 mov r3, r0 + 8001d66: 2b00 cmp r3, #0 + 8001d68: d001 beq.n 8001d6e + { + return HAL_ERROR; + 8001d6a: 2301 movs r3, #1 + 8001d6c: e00e b.n 8001d8c + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8001d6e: 687b ldr r3, [r7, #4] + 8001d70: 2b0f cmp r3, #15 + 8001d72: d80a bhi.n 8001d8a + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8001d74: 2200 movs r2, #0 + 8001d76: 6879 ldr r1, [r7, #4] + 8001d78: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8001d7c: f000 f90b bl 8001f96 + uwTickPrio = TickPriority; + 8001d80: 4a06 ldr r2, [pc, #24] ; (8001d9c ) + 8001d82: 687b ldr r3, [r7, #4] + 8001d84: 6013 str r3, [r2, #0] + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; + 8001d86: 2300 movs r3, #0 + 8001d88: e000 b.n 8001d8c + return HAL_ERROR; + 8001d8a: 2301 movs r3, #1 +} + 8001d8c: 4618 mov r0, r3 + 8001d8e: 3708 adds r7, #8 + 8001d90: 46bd mov sp, r7 + 8001d92: bd80 pop {r7, pc} + 8001d94: 20000004 .word 0x20000004 + 8001d98: 2000000c .word 0x2000000c + 8001d9c: 20000008 .word 0x20000008 + +08001da0 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 8001da0: b480 push {r7} + 8001da2: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 8001da4: 4b06 ldr r3, [pc, #24] ; (8001dc0 ) + 8001da6: 781b ldrb r3, [r3, #0] + 8001da8: 461a mov r2, r3 + 8001daa: 4b06 ldr r3, [pc, #24] ; (8001dc4 ) + 8001dac: 681b ldr r3, [r3, #0] + 8001dae: 4413 add r3, r2 + 8001db0: 4a04 ldr r2, [pc, #16] ; (8001dc4 ) + 8001db2: 6013 str r3, [r2, #0] +} + 8001db4: bf00 nop + 8001db6: 46bd mov sp, r7 + 8001db8: f85d 7b04 ldr.w r7, [sp], #4 + 8001dbc: 4770 bx lr + 8001dbe: bf00 nop + 8001dc0: 2000000c .word 0x2000000c + 8001dc4: 20000308 .word 0x20000308 + +08001dc8 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 8001dc8: b480 push {r7} + 8001dca: af00 add r7, sp, #0 + return uwTick; + 8001dcc: 4b03 ldr r3, [pc, #12] ; (8001ddc ) + 8001dce: 681b ldr r3, [r3, #0] +} + 8001dd0: 4618 mov r0, r3 + 8001dd2: 46bd mov sp, r7 + 8001dd4: f85d 7b04 ldr.w r7, [sp], #4 + 8001dd8: 4770 bx lr + 8001dda: bf00 nop + 8001ddc: 20000308 .word 0x20000308 + +08001de0 <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8001de0: b480 push {r7} + 8001de2: b085 sub sp, #20 + 8001de4: af00 add r7, sp, #0 + 8001de6: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8001de8: 687b ldr r3, [r7, #4] + 8001dea: f003 0307 and.w r3, r3, #7 + 8001dee: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 8001df0: 4b0b ldr r3, [pc, #44] ; (8001e20 <__NVIC_SetPriorityGrouping+0x40>) + 8001df2: 68db ldr r3, [r3, #12] + 8001df4: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8001df6: 68ba ldr r2, [r7, #8] + 8001df8: f64f 03ff movw r3, #63743 ; 0xf8ff + 8001dfc: 4013 ands r3, r2 + 8001dfe: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 8001e00: 68fb ldr r3, [r7, #12] + 8001e02: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8001e04: 68bb ldr r3, [r7, #8] + 8001e06: 431a orrs r2, r3 + reg_value = (reg_value | + 8001e08: 4b06 ldr r3, [pc, #24] ; (8001e24 <__NVIC_SetPriorityGrouping+0x44>) + 8001e0a: 4313 orrs r3, r2 + 8001e0c: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 8001e0e: 4a04 ldr r2, [pc, #16] ; (8001e20 <__NVIC_SetPriorityGrouping+0x40>) + 8001e10: 68bb ldr r3, [r7, #8] + 8001e12: 60d3 str r3, [r2, #12] +} + 8001e14: bf00 nop + 8001e16: 3714 adds r7, #20 + 8001e18: 46bd mov sp, r7 + 8001e1a: f85d 7b04 ldr.w r7, [sp], #4 + 8001e1e: 4770 bx lr + 8001e20: e000ed00 .word 0xe000ed00 + 8001e24: 05fa0000 .word 0x05fa0000 + +08001e28 <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 8001e28: b480 push {r7} + 8001e2a: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8001e2c: 4b04 ldr r3, [pc, #16] ; (8001e40 <__NVIC_GetPriorityGrouping+0x18>) + 8001e2e: 68db ldr r3, [r3, #12] + 8001e30: 0a1b lsrs r3, r3, #8 + 8001e32: f003 0307 and.w r3, r3, #7 +} + 8001e36: 4618 mov r0, r3 + 8001e38: 46bd mov sp, r7 + 8001e3a: f85d 7b04 ldr.w r7, [sp], #4 + 8001e3e: 4770 bx lr + 8001e40: e000ed00 .word 0xe000ed00 + +08001e44 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8001e44: b480 push {r7} + 8001e46: b083 sub sp, #12 + 8001e48: af00 add r7, sp, #0 + 8001e4a: 4603 mov r3, r0 + 8001e4c: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8001e4e: f997 3007 ldrsb.w r3, [r7, #7] + 8001e52: 2b00 cmp r3, #0 + 8001e54: db0b blt.n 8001e6e <__NVIC_EnableIRQ+0x2a> + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8001e56: 79fb ldrb r3, [r7, #7] + 8001e58: f003 021f and.w r2, r3, #31 + 8001e5c: 4907 ldr r1, [pc, #28] ; (8001e7c <__NVIC_EnableIRQ+0x38>) + 8001e5e: f997 3007 ldrsb.w r3, [r7, #7] + 8001e62: 095b lsrs r3, r3, #5 + 8001e64: 2001 movs r0, #1 + 8001e66: fa00 f202 lsl.w r2, r0, r2 + 8001e6a: f841 2023 str.w r2, [r1, r3, lsl #2] + } +} + 8001e6e: bf00 nop + 8001e70: 370c adds r7, #12 + 8001e72: 46bd mov sp, r7 + 8001e74: f85d 7b04 ldr.w r7, [sp], #4 + 8001e78: 4770 bx lr + 8001e7a: bf00 nop + 8001e7c: e000e100 .word 0xe000e100 + +08001e80 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8001e80: b480 push {r7} + 8001e82: b083 sub sp, #12 + 8001e84: af00 add r7, sp, #0 + 8001e86: 4603 mov r3, r0 + 8001e88: 6039 str r1, [r7, #0] + 8001e8a: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8001e8c: f997 3007 ldrsb.w r3, [r7, #7] + 8001e90: 2b00 cmp r3, #0 + 8001e92: db0a blt.n 8001eaa <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8001e94: 683b ldr r3, [r7, #0] + 8001e96: b2da uxtb r2, r3 + 8001e98: 490c ldr r1, [pc, #48] ; (8001ecc <__NVIC_SetPriority+0x4c>) + 8001e9a: f997 3007 ldrsb.w r3, [r7, #7] + 8001e9e: 0112 lsls r2, r2, #4 + 8001ea0: b2d2 uxtb r2, r2 + 8001ea2: 440b add r3, r1 + 8001ea4: f883 2300 strb.w r2, [r3, #768] ; 0x300 + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 8001ea8: e00a b.n 8001ec0 <__NVIC_SetPriority+0x40> + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8001eaa: 683b ldr r3, [r7, #0] + 8001eac: b2da uxtb r2, r3 + 8001eae: 4908 ldr r1, [pc, #32] ; (8001ed0 <__NVIC_SetPriority+0x50>) + 8001eb0: 79fb ldrb r3, [r7, #7] + 8001eb2: f003 030f and.w r3, r3, #15 + 8001eb6: 3b04 subs r3, #4 + 8001eb8: 0112 lsls r2, r2, #4 + 8001eba: b2d2 uxtb r2, r2 + 8001ebc: 440b add r3, r1 + 8001ebe: 761a strb r2, [r3, #24] +} + 8001ec0: bf00 nop + 8001ec2: 370c adds r7, #12 + 8001ec4: 46bd mov sp, r7 + 8001ec6: f85d 7b04 ldr.w r7, [sp], #4 + 8001eca: 4770 bx lr + 8001ecc: e000e100 .word 0xe000e100 + 8001ed0: e000ed00 .word 0xe000ed00 + +08001ed4 : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8001ed4: b480 push {r7} + 8001ed6: b089 sub sp, #36 ; 0x24 + 8001ed8: af00 add r7, sp, #0 + 8001eda: 60f8 str r0, [r7, #12] + 8001edc: 60b9 str r1, [r7, #8] + 8001ede: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8001ee0: 68fb ldr r3, [r7, #12] + 8001ee2: f003 0307 and.w r3, r3, #7 + 8001ee6: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8001ee8: 69fb ldr r3, [r7, #28] + 8001eea: f1c3 0307 rsb r3, r3, #7 + 8001eee: 2b04 cmp r3, #4 + 8001ef0: bf28 it cs + 8001ef2: 2304 movcs r3, #4 + 8001ef4: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8001ef6: 69fb ldr r3, [r7, #28] + 8001ef8: 3304 adds r3, #4 + 8001efa: 2b06 cmp r3, #6 + 8001efc: d902 bls.n 8001f04 + 8001efe: 69fb ldr r3, [r7, #28] + 8001f00: 3b03 subs r3, #3 + 8001f02: e000 b.n 8001f06 + 8001f04: 2300 movs r3, #0 + 8001f06: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8001f08: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 8001f0c: 69bb ldr r3, [r7, #24] + 8001f0e: fa02 f303 lsl.w r3, r2, r3 + 8001f12: 43da mvns r2, r3 + 8001f14: 68bb ldr r3, [r7, #8] + 8001f16: 401a ands r2, r3 + 8001f18: 697b ldr r3, [r7, #20] + 8001f1a: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8001f1c: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff + 8001f20: 697b ldr r3, [r7, #20] + 8001f22: fa01 f303 lsl.w r3, r1, r3 + 8001f26: 43d9 mvns r1, r3 + 8001f28: 687b ldr r3, [r7, #4] + 8001f2a: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8001f2c: 4313 orrs r3, r2 + ); +} + 8001f2e: 4618 mov r0, r3 + 8001f30: 3724 adds r7, #36 ; 0x24 + 8001f32: 46bd mov sp, r7 + 8001f34: f85d 7b04 ldr.w r7, [sp], #4 + 8001f38: 4770 bx lr + ... + +08001f3c : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8001f3c: b580 push {r7, lr} + 8001f3e: b082 sub sp, #8 + 8001f40: af00 add r7, sp, #0 + 8001f42: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8001f44: 687b ldr r3, [r7, #4] + 8001f46: 3b01 subs r3, #1 + 8001f48: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 + 8001f4c: d301 bcc.n 8001f52 + { + return (1UL); /* Reload value impossible */ + 8001f4e: 2301 movs r3, #1 + 8001f50: e00f b.n 8001f72 + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8001f52: 4a0a ldr r2, [pc, #40] ; (8001f7c ) + 8001f54: 687b ldr r3, [r7, #4] + 8001f56: 3b01 subs r3, #1 + 8001f58: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 8001f5a: 210f movs r1, #15 + 8001f5c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8001f60: f7ff ff8e bl 8001e80 <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8001f64: 4b05 ldr r3, [pc, #20] ; (8001f7c ) + 8001f66: 2200 movs r2, #0 + 8001f68: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8001f6a: 4b04 ldr r3, [pc, #16] ; (8001f7c ) + 8001f6c: 2207 movs r2, #7 + 8001f6e: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8001f70: 2300 movs r3, #0 +} + 8001f72: 4618 mov r0, r3 + 8001f74: 3708 adds r7, #8 + 8001f76: 46bd mov sp, r7 + 8001f78: bd80 pop {r7, pc} + 8001f7a: bf00 nop + 8001f7c: e000e010 .word 0xe000e010 + +08001f80 : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8001f80: b580 push {r7, lr} + 8001f82: b082 sub sp, #8 + 8001f84: af00 add r7, sp, #0 + 8001f86: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8001f88: 6878 ldr r0, [r7, #4] + 8001f8a: f7ff ff29 bl 8001de0 <__NVIC_SetPriorityGrouping> +} + 8001f8e: bf00 nop + 8001f90: 3708 adds r7, #8 + 8001f92: 46bd mov sp, r7 + 8001f94: bd80 pop {r7, pc} + +08001f96 : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8001f96: b580 push {r7, lr} + 8001f98: b086 sub sp, #24 + 8001f9a: af00 add r7, sp, #0 + 8001f9c: 4603 mov r3, r0 + 8001f9e: 60b9 str r1, [r7, #8] + 8001fa0: 607a str r2, [r7, #4] + 8001fa2: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00; + 8001fa4: 2300 movs r3, #0 + 8001fa6: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8001fa8: f7ff ff3e bl 8001e28 <__NVIC_GetPriorityGrouping> + 8001fac: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8001fae: 687a ldr r2, [r7, #4] + 8001fb0: 68b9 ldr r1, [r7, #8] + 8001fb2: 6978 ldr r0, [r7, #20] + 8001fb4: f7ff ff8e bl 8001ed4 + 8001fb8: 4602 mov r2, r0 + 8001fba: f997 300f ldrsb.w r3, [r7, #15] + 8001fbe: 4611 mov r1, r2 + 8001fc0: 4618 mov r0, r3 + 8001fc2: f7ff ff5d bl 8001e80 <__NVIC_SetPriority> +} + 8001fc6: bf00 nop + 8001fc8: 3718 adds r7, #24 + 8001fca: 46bd mov sp, r7 + 8001fcc: bd80 pop {r7, pc} + +08001fce : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8001fce: b580 push {r7, lr} + 8001fd0: b082 sub sp, #8 + 8001fd2: af00 add r7, sp, #0 + 8001fd4: 4603 mov r3, r0 + 8001fd6: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 8001fd8: f997 3007 ldrsb.w r3, [r7, #7] + 8001fdc: 4618 mov r0, r3 + 8001fde: f7ff ff31 bl 8001e44 <__NVIC_EnableIRQ> +} + 8001fe2: bf00 nop + 8001fe4: 3708 adds r7, #8 + 8001fe6: 46bd mov sp, r7 + 8001fe8: bd80 pop {r7, pc} + +08001fea : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 8001fea: b580 push {r7, lr} + 8001fec: b082 sub sp, #8 + 8001fee: af00 add r7, sp, #0 + 8001ff0: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 8001ff2: 6878 ldr r0, [r7, #4] + 8001ff4: f7ff ffa2 bl 8001f3c + 8001ff8: 4603 mov r3, r0 +} + 8001ffa: 4618 mov r0, r3 + 8001ffc: 3708 adds r7, #8 + 8001ffe: 46bd mov sp, r7 + 8002000: bd80 pop {r7, pc} + +08002002 : + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + 8002002: b480 push {r7} + 8002004: b083 sub sp, #12 + 8002006: af00 add r7, sp, #0 + 8002008: 6078 str r0, [r7, #4] + if(hdma->State != HAL_DMA_STATE_BUSY) + 800200a: 687b ldr r3, [r7, #4] + 800200c: f893 3035 ldrb.w r3, [r3, #53] ; 0x35 + 8002010: b2db uxtb r3, r3 + 8002012: 2b02 cmp r3, #2 + 8002014: d004 beq.n 8002020 + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 8002016: 687b ldr r3, [r7, #4] + 8002018: 2280 movs r2, #128 ; 0x80 + 800201a: 655a str r2, [r3, #84] ; 0x54 + return HAL_ERROR; + 800201c: 2301 movs r3, #1 + 800201e: e00c b.n 800203a + } + else + { + /* Set Abort State */ + hdma->State = HAL_DMA_STATE_ABORT; + 8002020: 687b ldr r3, [r7, #4] + 8002022: 2205 movs r2, #5 + 8002024: f883 2035 strb.w r2, [r3, #53] ; 0x35 + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + 8002028: 687b ldr r3, [r7, #4] + 800202a: 681b ldr r3, [r3, #0] + 800202c: 681a ldr r2, [r3, #0] + 800202e: 687b ldr r3, [r7, #4] + 8002030: 681b ldr r3, [r3, #0] + 8002032: f022 0201 bic.w r2, r2, #1 + 8002036: 601a str r2, [r3, #0] + } + + return HAL_OK; + 8002038: 2300 movs r3, #0 +} + 800203a: 4618 mov r0, r3 + 800203c: 370c adds r7, #12 + 800203e: 46bd mov sp, r7 + 8002040: f85d 7b04 ldr.w r7, [sp], #4 + 8002044: 4770 bx lr + ... + +08002048 : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8002048: b480 push {r7} + 800204a: b089 sub sp, #36 ; 0x24 + 800204c: af00 add r7, sp, #0 + 800204e: 6078 str r0, [r7, #4] + 8002050: 6039 str r1, [r7, #0] + uint32_t position = 0x00; + 8002052: 2300 movs r3, #0 + 8002054: 61fb str r3, [r7, #28] + uint32_t ioposition = 0x00; + 8002056: 2300 movs r3, #0 + 8002058: 617b str r3, [r7, #20] + uint32_t iocurrent = 0x00; + 800205a: 2300 movs r3, #0 + 800205c: 613b str r3, [r7, #16] + uint32_t temp = 0x00; + 800205e: 2300 movs r3, #0 + 8002060: 61bb str r3, [r7, #24] + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + for(position = 0; position < GPIO_NUMBER; position++) + 8002062: 2300 movs r3, #0 + 8002064: 61fb str r3, [r7, #28] + 8002066: e175 b.n 8002354 + { + /* Get the IO position */ + ioposition = ((uint32_t)0x01) << position; + 8002068: 2201 movs r2, #1 + 800206a: 69fb ldr r3, [r7, #28] + 800206c: fa02 f303 lsl.w r3, r2, r3 + 8002070: 617b str r3, [r7, #20] + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + 8002072: 683b ldr r3, [r7, #0] + 8002074: 681b ldr r3, [r3, #0] + 8002076: 697a ldr r2, [r7, #20] + 8002078: 4013 ands r3, r2 + 800207a: 613b str r3, [r7, #16] + + if(iocurrent == ioposition) + 800207c: 693a ldr r2, [r7, #16] + 800207e: 697b ldr r3, [r7, #20] + 8002080: 429a cmp r2, r3 + 8002082: f040 8164 bne.w 800234e + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 8002086: 683b ldr r3, [r7, #0] + 8002088: 685b ldr r3, [r3, #4] + 800208a: 2b02 cmp r3, #2 + 800208c: d003 beq.n 8002096 + 800208e: 683b ldr r3, [r7, #0] + 8002090: 685b ldr r3, [r3, #4] + 8002092: 2b12 cmp r3, #18 + 8002094: d123 bne.n 80020de + { + /* Check the Alternate function parameter */ + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3]; + 8002096: 69fb ldr r3, [r7, #28] + 8002098: 08da lsrs r2, r3, #3 + 800209a: 687b ldr r3, [r7, #4] + 800209c: 3208 adds r2, #8 + 800209e: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80020a2: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + 80020a4: 69fb ldr r3, [r7, #28] + 80020a6: f003 0307 and.w r3, r3, #7 + 80020aa: 009b lsls r3, r3, #2 + 80020ac: 220f movs r2, #15 + 80020ae: fa02 f303 lsl.w r3, r2, r3 + 80020b2: 43db mvns r3, r3 + 80020b4: 69ba ldr r2, [r7, #24] + 80020b6: 4013 ands r3, r2 + 80020b8: 61bb str r3, [r7, #24] + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); + 80020ba: 683b ldr r3, [r7, #0] + 80020bc: 691a ldr r2, [r3, #16] + 80020be: 69fb ldr r3, [r7, #28] + 80020c0: f003 0307 and.w r3, r3, #7 + 80020c4: 009b lsls r3, r3, #2 + 80020c6: fa02 f303 lsl.w r3, r2, r3 + 80020ca: 69ba ldr r2, [r7, #24] + 80020cc: 4313 orrs r3, r2 + 80020ce: 61bb str r3, [r7, #24] + GPIOx->AFR[position >> 3] = temp; + 80020d0: 69fb ldr r3, [r7, #28] + 80020d2: 08da lsrs r2, r3, #3 + 80020d4: 687b ldr r3, [r7, #4] + 80020d6: 3208 adds r2, #8 + 80020d8: 69b9 ldr r1, [r7, #24] + 80020da: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 80020de: 687b ldr r3, [r7, #4] + 80020e0: 681b ldr r3, [r3, #0] + 80020e2: 61bb str r3, [r7, #24] + temp &= ~(GPIO_MODER_MODER0 << (position * 2)); + 80020e4: 69fb ldr r3, [r7, #28] + 80020e6: 005b lsls r3, r3, #1 + 80020e8: 2203 movs r2, #3 + 80020ea: fa02 f303 lsl.w r3, r2, r3 + 80020ee: 43db mvns r3, r3 + 80020f0: 69ba ldr r2, [r7, #24] + 80020f2: 4013 ands r3, r2 + 80020f4: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 80020f6: 683b ldr r3, [r7, #0] + 80020f8: 685b ldr r3, [r3, #4] + 80020fa: f003 0203 and.w r2, r3, #3 + 80020fe: 69fb ldr r3, [r7, #28] + 8002100: 005b lsls r3, r3, #1 + 8002102: fa02 f303 lsl.w r3, r2, r3 + 8002106: 69ba ldr r2, [r7, #24] + 8002108: 4313 orrs r3, r2 + 800210a: 61bb str r3, [r7, #24] + GPIOx->MODER = temp; + 800210c: 687b ldr r3, [r7, #4] + 800210e: 69ba ldr r2, [r7, #24] + 8002110: 601a str r2, [r3, #0] + + /* In case of Output or Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 8002112: 683b ldr r3, [r7, #0] + 8002114: 685b ldr r3, [r3, #4] + 8002116: 2b01 cmp r3, #1 + 8002118: d00b beq.n 8002132 + 800211a: 683b ldr r3, [r7, #0] + 800211c: 685b ldr r3, [r3, #4] + 800211e: 2b02 cmp r3, #2 + 8002120: d007 beq.n 8002132 + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 8002122: 683b ldr r3, [r7, #0] + 8002124: 685b ldr r3, [r3, #4] + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 8002126: 2b11 cmp r3, #17 + 8002128: d003 beq.n 8002132 + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 800212a: 683b ldr r3, [r7, #0] + 800212c: 685b ldr r3, [r3, #4] + 800212e: 2b12 cmp r3, #18 + 8002130: d130 bne.n 8002194 + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8002132: 687b ldr r3, [r7, #4] + 8002134: 689b ldr r3, [r3, #8] + 8002136: 61bb str r3, [r7, #24] + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + 8002138: 69fb ldr r3, [r7, #28] + 800213a: 005b lsls r3, r3, #1 + 800213c: 2203 movs r2, #3 + 800213e: fa02 f303 lsl.w r3, r2, r3 + 8002142: 43db mvns r3, r3 + 8002144: 69ba ldr r2, [r7, #24] + 8002146: 4013 ands r3, r2 + 8002148: 61bb str r3, [r7, #24] + temp |= (GPIO_Init->Speed << (position * 2)); + 800214a: 683b ldr r3, [r7, #0] + 800214c: 68da ldr r2, [r3, #12] + 800214e: 69fb ldr r3, [r7, #28] + 8002150: 005b lsls r3, r3, #1 + 8002152: fa02 f303 lsl.w r3, r2, r3 + 8002156: 69ba ldr r2, [r7, #24] + 8002158: 4313 orrs r3, r2 + 800215a: 61bb str r3, [r7, #24] + GPIOx->OSPEEDR = temp; + 800215c: 687b ldr r3, [r7, #4] + 800215e: 69ba ldr r2, [r7, #24] + 8002160: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 8002162: 687b ldr r3, [r7, #4] + 8002164: 685b ldr r3, [r3, #4] + 8002166: 61bb str r3, [r7, #24] + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + 8002168: 2201 movs r2, #1 + 800216a: 69fb ldr r3, [r7, #28] + 800216c: fa02 f303 lsl.w r3, r2, r3 + 8002170: 43db mvns r3, r3 + 8002172: 69ba ldr r2, [r7, #24] + 8002174: 4013 ands r3, r2 + 8002176: 61bb str r3, [r7, #24] + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); + 8002178: 683b ldr r3, [r7, #0] + 800217a: 685b ldr r3, [r3, #4] + 800217c: 091b lsrs r3, r3, #4 + 800217e: f003 0201 and.w r2, r3, #1 + 8002182: 69fb ldr r3, [r7, #28] + 8002184: fa02 f303 lsl.w r3, r2, r3 + 8002188: 69ba ldr r2, [r7, #24] + 800218a: 4313 orrs r3, r2 + 800218c: 61bb str r3, [r7, #24] + GPIOx->OTYPER = temp; + 800218e: 687b ldr r3, [r7, #4] + 8002190: 69ba ldr r2, [r7, #24] + 8002192: 605a str r2, [r3, #4] + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 8002194: 687b ldr r3, [r7, #4] + 8002196: 68db ldr r3, [r3, #12] + 8002198: 61bb str r3, [r7, #24] + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + 800219a: 69fb ldr r3, [r7, #28] + 800219c: 005b lsls r3, r3, #1 + 800219e: 2203 movs r2, #3 + 80021a0: fa02 f303 lsl.w r3, r2, r3 + 80021a4: 43db mvns r3, r3 + 80021a6: 69ba ldr r2, [r7, #24] + 80021a8: 4013 ands r3, r2 + 80021aa: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Pull) << (position * 2)); + 80021ac: 683b ldr r3, [r7, #0] + 80021ae: 689a ldr r2, [r3, #8] + 80021b0: 69fb ldr r3, [r7, #28] + 80021b2: 005b lsls r3, r3, #1 + 80021b4: fa02 f303 lsl.w r3, r2, r3 + 80021b8: 69ba ldr r2, [r7, #24] + 80021ba: 4313 orrs r3, r2 + 80021bc: 61bb str r3, [r7, #24] + GPIOx->PUPDR = temp; + 80021be: 687b ldr r3, [r7, #4] + 80021c0: 69ba ldr r2, [r7, #24] + 80021c2: 60da str r2, [r3, #12] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + 80021c4: 683b ldr r3, [r7, #0] + 80021c6: 685b ldr r3, [r3, #4] + 80021c8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 80021cc: 2b00 cmp r3, #0 + 80021ce: f000 80be beq.w 800234e + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 80021d2: 4b65 ldr r3, [pc, #404] ; (8002368 ) + 80021d4: 6c5b ldr r3, [r3, #68] ; 0x44 + 80021d6: 4a64 ldr r2, [pc, #400] ; (8002368 ) + 80021d8: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 80021dc: 6453 str r3, [r2, #68] ; 0x44 + 80021de: 4b62 ldr r3, [pc, #392] ; (8002368 ) + 80021e0: 6c5b ldr r3, [r3, #68] ; 0x44 + 80021e2: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 80021e6: 60fb str r3, [r7, #12] + 80021e8: 68fb ldr r3, [r7, #12] + + temp = SYSCFG->EXTICR[position >> 2]; + 80021ea: 4a60 ldr r2, [pc, #384] ; (800236c ) + 80021ec: 69fb ldr r3, [r7, #28] + 80021ee: 089b lsrs r3, r3, #2 + 80021f0: 3302 adds r3, #2 + 80021f2: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80021f6: 61bb str r3, [r7, #24] + temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); + 80021f8: 69fb ldr r3, [r7, #28] + 80021fa: f003 0303 and.w r3, r3, #3 + 80021fe: 009b lsls r3, r3, #2 + 8002200: 220f movs r2, #15 + 8002202: fa02 f303 lsl.w r3, r2, r3 + 8002206: 43db mvns r3, r3 + 8002208: 69ba ldr r2, [r7, #24] + 800220a: 4013 ands r3, r2 + 800220c: 61bb str r3, [r7, #24] + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 800220e: 687b ldr r3, [r7, #4] + 8002210: 4a57 ldr r2, [pc, #348] ; (8002370 ) + 8002212: 4293 cmp r3, r2 + 8002214: d037 beq.n 8002286 + 8002216: 687b ldr r3, [r7, #4] + 8002218: 4a56 ldr r2, [pc, #344] ; (8002374 ) + 800221a: 4293 cmp r3, r2 + 800221c: d031 beq.n 8002282 + 800221e: 687b ldr r3, [r7, #4] + 8002220: 4a55 ldr r2, [pc, #340] ; (8002378 ) + 8002222: 4293 cmp r3, r2 + 8002224: d02b beq.n 800227e + 8002226: 687b ldr r3, [r7, #4] + 8002228: 4a54 ldr r2, [pc, #336] ; (800237c ) + 800222a: 4293 cmp r3, r2 + 800222c: d025 beq.n 800227a + 800222e: 687b ldr r3, [r7, #4] + 8002230: 4a53 ldr r2, [pc, #332] ; (8002380 ) + 8002232: 4293 cmp r3, r2 + 8002234: d01f beq.n 8002276 + 8002236: 687b ldr r3, [r7, #4] + 8002238: 4a52 ldr r2, [pc, #328] ; (8002384 ) + 800223a: 4293 cmp r3, r2 + 800223c: d019 beq.n 8002272 + 800223e: 687b ldr r3, [r7, #4] + 8002240: 4a51 ldr r2, [pc, #324] ; (8002388 ) + 8002242: 4293 cmp r3, r2 + 8002244: d013 beq.n 800226e + 8002246: 687b ldr r3, [r7, #4] + 8002248: 4a50 ldr r2, [pc, #320] ; (800238c ) + 800224a: 4293 cmp r3, r2 + 800224c: d00d beq.n 800226a + 800224e: 687b ldr r3, [r7, #4] + 8002250: 4a4f ldr r2, [pc, #316] ; (8002390 ) + 8002252: 4293 cmp r3, r2 + 8002254: d007 beq.n 8002266 + 8002256: 687b ldr r3, [r7, #4] + 8002258: 4a4e ldr r2, [pc, #312] ; (8002394 ) + 800225a: 4293 cmp r3, r2 + 800225c: d101 bne.n 8002262 + 800225e: 2309 movs r3, #9 + 8002260: e012 b.n 8002288 + 8002262: 230a movs r3, #10 + 8002264: e010 b.n 8002288 + 8002266: 2308 movs r3, #8 + 8002268: e00e b.n 8002288 + 800226a: 2307 movs r3, #7 + 800226c: e00c b.n 8002288 + 800226e: 2306 movs r3, #6 + 8002270: e00a b.n 8002288 + 8002272: 2305 movs r3, #5 + 8002274: e008 b.n 8002288 + 8002276: 2304 movs r3, #4 + 8002278: e006 b.n 8002288 + 800227a: 2303 movs r3, #3 + 800227c: e004 b.n 8002288 + 800227e: 2302 movs r3, #2 + 8002280: e002 b.n 8002288 + 8002282: 2301 movs r3, #1 + 8002284: e000 b.n 8002288 + 8002286: 2300 movs r3, #0 + 8002288: 69fa ldr r2, [r7, #28] + 800228a: f002 0203 and.w r2, r2, #3 + 800228e: 0092 lsls r2, r2, #2 + 8002290: 4093 lsls r3, r2 + 8002292: 69ba ldr r2, [r7, #24] + 8002294: 4313 orrs r3, r2 + 8002296: 61bb str r3, [r7, #24] + SYSCFG->EXTICR[position >> 2] = temp; + 8002298: 4934 ldr r1, [pc, #208] ; (800236c ) + 800229a: 69fb ldr r3, [r7, #28] + 800229c: 089b lsrs r3, r3, #2 + 800229e: 3302 adds r3, #2 + 80022a0: 69ba ldr r2, [r7, #24] + 80022a2: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 80022a6: 4b3c ldr r3, [pc, #240] ; (8002398 ) + 80022a8: 681b ldr r3, [r3, #0] + 80022aa: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 80022ac: 693b ldr r3, [r7, #16] + 80022ae: 43db mvns r3, r3 + 80022b0: 69ba ldr r2, [r7, #24] + 80022b2: 4013 ands r3, r2 + 80022b4: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + 80022b6: 683b ldr r3, [r7, #0] + 80022b8: 685b ldr r3, [r3, #4] + 80022ba: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 80022be: 2b00 cmp r3, #0 + 80022c0: d003 beq.n 80022ca + { + temp |= iocurrent; + 80022c2: 69ba ldr r2, [r7, #24] + 80022c4: 693b ldr r3, [r7, #16] + 80022c6: 4313 orrs r3, r2 + 80022c8: 61bb str r3, [r7, #24] + } + EXTI->IMR = temp; + 80022ca: 4a33 ldr r2, [pc, #204] ; (8002398 ) + 80022cc: 69bb ldr r3, [r7, #24] + 80022ce: 6013 str r3, [r2, #0] + + temp = EXTI->EMR; + 80022d0: 4b31 ldr r3, [pc, #196] ; (8002398 ) + 80022d2: 685b ldr r3, [r3, #4] + 80022d4: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 80022d6: 693b ldr r3, [r7, #16] + 80022d8: 43db mvns r3, r3 + 80022da: 69ba ldr r2, [r7, #24] + 80022dc: 4013 ands r3, r2 + 80022de: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + 80022e0: 683b ldr r3, [r7, #0] + 80022e2: 685b ldr r3, [r3, #4] + 80022e4: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80022e8: 2b00 cmp r3, #0 + 80022ea: d003 beq.n 80022f4 + { + temp |= iocurrent; + 80022ec: 69ba ldr r2, [r7, #24] + 80022ee: 693b ldr r3, [r7, #16] + 80022f0: 4313 orrs r3, r2 + 80022f2: 61bb str r3, [r7, #24] + } + EXTI->EMR = temp; + 80022f4: 4a28 ldr r2, [pc, #160] ; (8002398 ) + 80022f6: 69bb ldr r3, [r7, #24] + 80022f8: 6053 str r3, [r2, #4] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 80022fa: 4b27 ldr r3, [pc, #156] ; (8002398 ) + 80022fc: 689b ldr r3, [r3, #8] + 80022fe: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 8002300: 693b ldr r3, [r7, #16] + 8002302: 43db mvns r3, r3 + 8002304: 69ba ldr r2, [r7, #24] + 8002306: 4013 ands r3, r2 + 8002308: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + 800230a: 683b ldr r3, [r7, #0] + 800230c: 685b ldr r3, [r3, #4] + 800230e: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8002312: 2b00 cmp r3, #0 + 8002314: d003 beq.n 800231e + { + temp |= iocurrent; + 8002316: 69ba ldr r2, [r7, #24] + 8002318: 693b ldr r3, [r7, #16] + 800231a: 4313 orrs r3, r2 + 800231c: 61bb str r3, [r7, #24] + } + EXTI->RTSR = temp; + 800231e: 4a1e ldr r2, [pc, #120] ; (8002398 ) + 8002320: 69bb ldr r3, [r7, #24] + 8002322: 6093 str r3, [r2, #8] + + temp = EXTI->FTSR; + 8002324: 4b1c ldr r3, [pc, #112] ; (8002398 ) + 8002326: 68db ldr r3, [r3, #12] + 8002328: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 800232a: 693b ldr r3, [r7, #16] + 800232c: 43db mvns r3, r3 + 800232e: 69ba ldr r2, [r7, #24] + 8002330: 4013 ands r3, r2 + 8002332: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + 8002334: 683b ldr r3, [r7, #0] + 8002336: 685b ldr r3, [r3, #4] + 8002338: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 800233c: 2b00 cmp r3, #0 + 800233e: d003 beq.n 8002348 + { + temp |= iocurrent; + 8002340: 69ba ldr r2, [r7, #24] + 8002342: 693b ldr r3, [r7, #16] + 8002344: 4313 orrs r3, r2 + 8002346: 61bb str r3, [r7, #24] + } + EXTI->FTSR = temp; + 8002348: 4a13 ldr r2, [pc, #76] ; (8002398 ) + 800234a: 69bb ldr r3, [r7, #24] + 800234c: 60d3 str r3, [r2, #12] + for(position = 0; position < GPIO_NUMBER; position++) + 800234e: 69fb ldr r3, [r7, #28] + 8002350: 3301 adds r3, #1 + 8002352: 61fb str r3, [r7, #28] + 8002354: 69fb ldr r3, [r7, #28] + 8002356: 2b0f cmp r3, #15 + 8002358: f67f ae86 bls.w 8002068 + } + } + } +} + 800235c: bf00 nop + 800235e: 3724 adds r7, #36 ; 0x24 + 8002360: 46bd mov sp, r7 + 8002362: f85d 7b04 ldr.w r7, [sp], #4 + 8002366: 4770 bx lr + 8002368: 40023800 .word 0x40023800 + 800236c: 40013800 .word 0x40013800 + 8002370: 40020000 .word 0x40020000 + 8002374: 40020400 .word 0x40020400 + 8002378: 40020800 .word 0x40020800 + 800237c: 40020c00 .word 0x40020c00 + 8002380: 40021000 .word 0x40021000 + 8002384: 40021400 .word 0x40021400 + 8002388: 40021800 .word 0x40021800 + 800238c: 40021c00 .word 0x40021c00 + 8002390: 40022000 .word 0x40022000 + 8002394: 40022400 .word 0x40022400 + 8002398: 40013c00 .word 0x40013c00 + +0800239c : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 800239c: b480 push {r7} + 800239e: b083 sub sp, #12 + 80023a0: af00 add r7, sp, #0 + 80023a2: 6078 str r0, [r7, #4] + 80023a4: 460b mov r3, r1 + 80023a6: 807b strh r3, [r7, #2] + 80023a8: 4613 mov r3, r2 + 80023aa: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if(PinState != GPIO_PIN_RESET) + 80023ac: 787b ldrb r3, [r7, #1] + 80023ae: 2b00 cmp r3, #0 + 80023b0: d003 beq.n 80023ba + { + GPIOx->BSRR = GPIO_Pin; + 80023b2: 887a ldrh r2, [r7, #2] + 80023b4: 687b ldr r3, [r7, #4] + 80023b6: 619a str r2, [r3, #24] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; + } +} + 80023b8: e003 b.n 80023c2 + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; + 80023ba: 887b ldrh r3, [r7, #2] + 80023bc: 041a lsls r2, r3, #16 + 80023be: 687b ldr r3, [r7, #4] + 80023c0: 619a str r2, [r3, #24] +} + 80023c2: bf00 nop + 80023c4: 370c adds r7, #12 + 80023c6: 46bd mov sp, r7 + 80023c8: f85d 7b04 ldr.w r7, [sp], #4 + 80023cc: 4770 bx lr + ... + +080023d0 : + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin Specifies the pins connected EXTI line + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + 80023d0: b580 push {r7, lr} + 80023d2: b082 sub sp, #8 + 80023d4: af00 add r7, sp, #0 + 80023d6: 4603 mov r3, r0 + 80023d8: 80fb strh r3, [r7, #6] + /* EXTI line interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + 80023da: 4b08 ldr r3, [pc, #32] ; (80023fc ) + 80023dc: 695a ldr r2, [r3, #20] + 80023de: 88fb ldrh r3, [r7, #6] + 80023e0: 4013 ands r3, r2 + 80023e2: 2b00 cmp r3, #0 + 80023e4: d006 beq.n 80023f4 + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + 80023e6: 4a05 ldr r2, [pc, #20] ; (80023fc ) + 80023e8: 88fb ldrh r3, [r7, #6] + 80023ea: 6153 str r3, [r2, #20] + HAL_GPIO_EXTI_Callback(GPIO_Pin); + 80023ec: 88fb ldrh r3, [r7, #6] + 80023ee: 4618 mov r0, r3 + 80023f0: f7ff f9a4 bl 800173c + } +} + 80023f4: bf00 nop + 80023f6: 3708 adds r7, #8 + 80023f8: 46bd mov sp, r7 + 80023fa: bd80 pop {r7, pc} + 80023fc: 40013c00 .word 0x40013c00 + +08002400 : + * supported by this function. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8002400: b580 push {r7, lr} + 8002402: b086 sub sp, #24 + 8002404: af00 add r7, sp, #0 + 8002406: 6078 str r0, [r7, #4] + uint32_t tickstart; + FlagStatus pwrclkchanged = RESET; + 8002408: 2300 movs r3, #0 + 800240a: 75fb strb r3, [r7, #23] + + /* Check Null pointer */ + if(RCC_OscInitStruct == NULL) + 800240c: 687b ldr r3, [r7, #4] + 800240e: 2b00 cmp r3, #0 + 8002410: d101 bne.n 8002416 + { + return HAL_ERROR; + 8002412: 2301 movs r3, #1 + 8002414: e25e b.n 80028d4 + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 8002416: 687b ldr r3, [r7, #4] + 8002418: 681b ldr r3, [r3, #0] + 800241a: f003 0301 and.w r3, r3, #1 + 800241e: 2b00 cmp r3, #0 + 8002420: f000 8087 beq.w 8002532 + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + 8002424: 4b96 ldr r3, [pc, #600] ; (8002680 ) + 8002426: 689b ldr r3, [r3, #8] + 8002428: f003 030c and.w r3, r3, #12 + 800242c: 2b04 cmp r3, #4 + 800242e: d00c beq.n 800244a + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + 8002430: 4b93 ldr r3, [pc, #588] ; (8002680 ) + 8002432: 689b ldr r3, [r3, #8] + 8002434: f003 030c and.w r3, r3, #12 + 8002438: 2b08 cmp r3, #8 + 800243a: d112 bne.n 8002462 + 800243c: 4b90 ldr r3, [pc, #576] ; (8002680 ) + 800243e: 685b ldr r3, [r3, #4] + 8002440: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8002444: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 8002448: d10b bne.n 8002462 + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 800244a: 4b8d ldr r3, [pc, #564] ; (8002680 ) + 800244c: 681b ldr r3, [r3, #0] + 800244e: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002452: 2b00 cmp r3, #0 + 8002454: d06c beq.n 8002530 + 8002456: 687b ldr r3, [r7, #4] + 8002458: 685b ldr r3, [r3, #4] + 800245a: 2b00 cmp r3, #0 + 800245c: d168 bne.n 8002530 + { + return HAL_ERROR; + 800245e: 2301 movs r3, #1 + 8002460: e238 b.n 80028d4 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8002462: 687b ldr r3, [r7, #4] + 8002464: 685b ldr r3, [r3, #4] + 8002466: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800246a: d106 bne.n 800247a + 800246c: 4b84 ldr r3, [pc, #528] ; (8002680 ) + 800246e: 681b ldr r3, [r3, #0] + 8002470: 4a83 ldr r2, [pc, #524] ; (8002680 ) + 8002472: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8002476: 6013 str r3, [r2, #0] + 8002478: e02e b.n 80024d8 + 800247a: 687b ldr r3, [r7, #4] + 800247c: 685b ldr r3, [r3, #4] + 800247e: 2b00 cmp r3, #0 + 8002480: d10c bne.n 800249c + 8002482: 4b7f ldr r3, [pc, #508] ; (8002680 ) + 8002484: 681b ldr r3, [r3, #0] + 8002486: 4a7e ldr r2, [pc, #504] ; (8002680 ) + 8002488: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 800248c: 6013 str r3, [r2, #0] + 800248e: 4b7c ldr r3, [pc, #496] ; (8002680 ) + 8002490: 681b ldr r3, [r3, #0] + 8002492: 4a7b ldr r2, [pc, #492] ; (8002680 ) + 8002494: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8002498: 6013 str r3, [r2, #0] + 800249a: e01d b.n 80024d8 + 800249c: 687b ldr r3, [r7, #4] + 800249e: 685b ldr r3, [r3, #4] + 80024a0: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 + 80024a4: d10c bne.n 80024c0 + 80024a6: 4b76 ldr r3, [pc, #472] ; (8002680 ) + 80024a8: 681b ldr r3, [r3, #0] + 80024aa: 4a75 ldr r2, [pc, #468] ; (8002680 ) + 80024ac: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 80024b0: 6013 str r3, [r2, #0] + 80024b2: 4b73 ldr r3, [pc, #460] ; (8002680 ) + 80024b4: 681b ldr r3, [r3, #0] + 80024b6: 4a72 ldr r2, [pc, #456] ; (8002680 ) + 80024b8: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80024bc: 6013 str r3, [r2, #0] + 80024be: e00b b.n 80024d8 + 80024c0: 4b6f ldr r3, [pc, #444] ; (8002680 ) + 80024c2: 681b ldr r3, [r3, #0] + 80024c4: 4a6e ldr r2, [pc, #440] ; (8002680 ) + 80024c6: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 80024ca: 6013 str r3, [r2, #0] + 80024cc: 4b6c ldr r3, [pc, #432] ; (8002680 ) + 80024ce: 681b ldr r3, [r3, #0] + 80024d0: 4a6b ldr r2, [pc, #428] ; (8002680 ) + 80024d2: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 80024d6: 6013 str r3, [r2, #0] + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 80024d8: 687b ldr r3, [r7, #4] + 80024da: 685b ldr r3, [r3, #4] + 80024dc: 2b00 cmp r3, #0 + 80024de: d013 beq.n 8002508 + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80024e0: f7ff fc72 bl 8001dc8 + 80024e4: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 80024e6: e008 b.n 80024fa + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 80024e8: f7ff fc6e bl 8001dc8 + 80024ec: 4602 mov r2, r0 + 80024ee: 693b ldr r3, [r7, #16] + 80024f0: 1ad3 subs r3, r2, r3 + 80024f2: 2b64 cmp r3, #100 ; 0x64 + 80024f4: d901 bls.n 80024fa + { + return HAL_TIMEOUT; + 80024f6: 2303 movs r3, #3 + 80024f8: e1ec b.n 80028d4 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 80024fa: 4b61 ldr r3, [pc, #388] ; (8002680 ) + 80024fc: 681b ldr r3, [r3, #0] + 80024fe: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002502: 2b00 cmp r3, #0 + 8002504: d0f0 beq.n 80024e8 + 8002506: e014 b.n 8002532 + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002508: f7ff fc5e bl 8001dc8 + 800250c: 6138 str r0, [r7, #16] + + /* Wait till HSE is bypassed or disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 800250e: e008 b.n 8002522 + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8002510: f7ff fc5a bl 8001dc8 + 8002514: 4602 mov r2, r0 + 8002516: 693b ldr r3, [r7, #16] + 8002518: 1ad3 subs r3, r2, r3 + 800251a: 2b64 cmp r3, #100 ; 0x64 + 800251c: d901 bls.n 8002522 + { + return HAL_TIMEOUT; + 800251e: 2303 movs r3, #3 + 8002520: e1d8 b.n 80028d4 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 8002522: 4b57 ldr r3, [pc, #348] ; (8002680 ) + 8002524: 681b ldr r3, [r3, #0] + 8002526: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800252a: 2b00 cmp r3, #0 + 800252c: d1f0 bne.n 8002510 + 800252e: e000 b.n 8002532 + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8002530: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 8002532: 687b ldr r3, [r7, #4] + 8002534: 681b ldr r3, [r3, #0] + 8002536: f003 0302 and.w r3, r3, #2 + 800253a: 2b00 cmp r3, #0 + 800253c: d069 beq.n 8002612 + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + 800253e: 4b50 ldr r3, [pc, #320] ; (8002680 ) + 8002540: 689b ldr r3, [r3, #8] + 8002542: f003 030c and.w r3, r3, #12 + 8002546: 2b00 cmp r3, #0 + 8002548: d00b beq.n 8002562 + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + 800254a: 4b4d ldr r3, [pc, #308] ; (8002680 ) + 800254c: 689b ldr r3, [r3, #8] + 800254e: f003 030c and.w r3, r3, #12 + 8002552: 2b08 cmp r3, #8 + 8002554: d11c bne.n 8002590 + 8002556: 4b4a ldr r3, [pc, #296] ; (8002680 ) + 8002558: 685b ldr r3, [r3, #4] + 800255a: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 800255e: 2b00 cmp r3, #0 + 8002560: d116 bne.n 8002590 + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8002562: 4b47 ldr r3, [pc, #284] ; (8002680 ) + 8002564: 681b ldr r3, [r3, #0] + 8002566: f003 0302 and.w r3, r3, #2 + 800256a: 2b00 cmp r3, #0 + 800256c: d005 beq.n 800257a + 800256e: 687b ldr r3, [r7, #4] + 8002570: 68db ldr r3, [r3, #12] + 8002572: 2b01 cmp r3, #1 + 8002574: d001 beq.n 800257a + { + return HAL_ERROR; + 8002576: 2301 movs r3, #1 + 8002578: e1ac b.n 80028d4 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 800257a: 4b41 ldr r3, [pc, #260] ; (8002680 ) + 800257c: 681b ldr r3, [r3, #0] + 800257e: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 8002582: 687b ldr r3, [r7, #4] + 8002584: 691b ldr r3, [r3, #16] + 8002586: 00db lsls r3, r3, #3 + 8002588: 493d ldr r1, [pc, #244] ; (8002680 ) + 800258a: 4313 orrs r3, r2 + 800258c: 600b str r3, [r1, #0] + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 800258e: e040 b.n 8002612 + } + } + else + { + /* Check the HSI State */ + if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) + 8002590: 687b ldr r3, [r7, #4] + 8002592: 68db ldr r3, [r3, #12] + 8002594: 2b00 cmp r3, #0 + 8002596: d023 beq.n 80025e0 + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 8002598: 4b39 ldr r3, [pc, #228] ; (8002680 ) + 800259a: 681b ldr r3, [r3, #0] + 800259c: 4a38 ldr r2, [pc, #224] ; (8002680 ) + 800259e: f043 0301 orr.w r3, r3, #1 + 80025a2: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80025a4: f7ff fc10 bl 8001dc8 + 80025a8: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 80025aa: e008 b.n 80025be + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 80025ac: f7ff fc0c bl 8001dc8 + 80025b0: 4602 mov r2, r0 + 80025b2: 693b ldr r3, [r7, #16] + 80025b4: 1ad3 subs r3, r2, r3 + 80025b6: 2b02 cmp r3, #2 + 80025b8: d901 bls.n 80025be + { + return HAL_TIMEOUT; + 80025ba: 2303 movs r3, #3 + 80025bc: e18a b.n 80028d4 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 80025be: 4b30 ldr r3, [pc, #192] ; (8002680 ) + 80025c0: 681b ldr r3, [r3, #0] + 80025c2: f003 0302 and.w r3, r3, #2 + 80025c6: 2b00 cmp r3, #0 + 80025c8: d0f0 beq.n 80025ac + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 80025ca: 4b2d ldr r3, [pc, #180] ; (8002680 ) + 80025cc: 681b ldr r3, [r3, #0] + 80025ce: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 80025d2: 687b ldr r3, [r7, #4] + 80025d4: 691b ldr r3, [r3, #16] + 80025d6: 00db lsls r3, r3, #3 + 80025d8: 4929 ldr r1, [pc, #164] ; (8002680 ) + 80025da: 4313 orrs r3, r2 + 80025dc: 600b str r3, [r1, #0] + 80025de: e018 b.n 8002612 + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 80025e0: 4b27 ldr r3, [pc, #156] ; (8002680 ) + 80025e2: 681b ldr r3, [r3, #0] + 80025e4: 4a26 ldr r2, [pc, #152] ; (8002680 ) + 80025e6: f023 0301 bic.w r3, r3, #1 + 80025ea: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80025ec: f7ff fbec bl 8001dc8 + 80025f0: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 80025f2: e008 b.n 8002606 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 80025f4: f7ff fbe8 bl 8001dc8 + 80025f8: 4602 mov r2, r0 + 80025fa: 693b ldr r3, [r7, #16] + 80025fc: 1ad3 subs r3, r2, r3 + 80025fe: 2b02 cmp r3, #2 + 8002600: d901 bls.n 8002606 + { + return HAL_TIMEOUT; + 8002602: 2303 movs r3, #3 + 8002604: e166 b.n 80028d4 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 8002606: 4b1e ldr r3, [pc, #120] ; (8002680 ) + 8002608: 681b ldr r3, [r3, #0] + 800260a: f003 0302 and.w r3, r3, #2 + 800260e: 2b00 cmp r3, #0 + 8002610: d1f0 bne.n 80025f4 + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8002612: 687b ldr r3, [r7, #4] + 8002614: 681b ldr r3, [r3, #0] + 8002616: f003 0308 and.w r3, r3, #8 + 800261a: 2b00 cmp r3, #0 + 800261c: d038 beq.n 8002690 + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) + 800261e: 687b ldr r3, [r7, #4] + 8002620: 695b ldr r3, [r3, #20] + 8002622: 2b00 cmp r3, #0 + 8002624: d019 beq.n 800265a + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 8002626: 4b16 ldr r3, [pc, #88] ; (8002680 ) + 8002628: 6f5b ldr r3, [r3, #116] ; 0x74 + 800262a: 4a15 ldr r2, [pc, #84] ; (8002680 ) + 800262c: f043 0301 orr.w r3, r3, #1 + 8002630: 6753 str r3, [r2, #116] ; 0x74 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002632: f7ff fbc9 bl 8001dc8 + 8002636: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8002638: e008 b.n 800264c + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 800263a: f7ff fbc5 bl 8001dc8 + 800263e: 4602 mov r2, r0 + 8002640: 693b ldr r3, [r7, #16] + 8002642: 1ad3 subs r3, r2, r3 + 8002644: 2b02 cmp r3, #2 + 8002646: d901 bls.n 800264c + { + return HAL_TIMEOUT; + 8002648: 2303 movs r3, #3 + 800264a: e143 b.n 80028d4 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 800264c: 4b0c ldr r3, [pc, #48] ; (8002680 ) + 800264e: 6f5b ldr r3, [r3, #116] ; 0x74 + 8002650: f003 0302 and.w r3, r3, #2 + 8002654: 2b00 cmp r3, #0 + 8002656: d0f0 beq.n 800263a + 8002658: e01a b.n 8002690 + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 800265a: 4b09 ldr r3, [pc, #36] ; (8002680 ) + 800265c: 6f5b ldr r3, [r3, #116] ; 0x74 + 800265e: 4a08 ldr r2, [pc, #32] ; (8002680 ) + 8002660: f023 0301 bic.w r3, r3, #1 + 8002664: 6753 str r3, [r2, #116] ; 0x74 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002666: f7ff fbaf bl 8001dc8 + 800266a: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 800266c: e00a b.n 8002684 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 800266e: f7ff fbab bl 8001dc8 + 8002672: 4602 mov r2, r0 + 8002674: 693b ldr r3, [r7, #16] + 8002676: 1ad3 subs r3, r2, r3 + 8002678: 2b02 cmp r3, #2 + 800267a: d903 bls.n 8002684 + { + return HAL_TIMEOUT; + 800267c: 2303 movs r3, #3 + 800267e: e129 b.n 80028d4 + 8002680: 40023800 .word 0x40023800 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8002684: 4b95 ldr r3, [pc, #596] ; (80028dc ) + 8002686: 6f5b ldr r3, [r3, #116] ; 0x74 + 8002688: f003 0302 and.w r3, r3, #2 + 800268c: 2b00 cmp r3, #0 + 800268e: d1ee bne.n 800266e + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8002690: 687b ldr r3, [r7, #4] + 8002692: 681b ldr r3, [r3, #0] + 8002694: f003 0304 and.w r3, r3, #4 + 8002698: 2b00 cmp r3, #0 + 800269a: f000 80a4 beq.w 80027e6 + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 800269e: 4b8f ldr r3, [pc, #572] ; (80028dc ) + 80026a0: 6c1b ldr r3, [r3, #64] ; 0x40 + 80026a2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 80026a6: 2b00 cmp r3, #0 + 80026a8: d10d bne.n 80026c6 + { + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + 80026aa: 4b8c ldr r3, [pc, #560] ; (80028dc ) + 80026ac: 6c1b ldr r3, [r3, #64] ; 0x40 + 80026ae: 4a8b ldr r2, [pc, #556] ; (80028dc ) + 80026b0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 80026b4: 6413 str r3, [r2, #64] ; 0x40 + 80026b6: 4b89 ldr r3, [pc, #548] ; (80028dc ) + 80026b8: 6c1b ldr r3, [r3, #64] ; 0x40 + 80026ba: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 80026be: 60fb str r3, [r7, #12] + 80026c0: 68fb ldr r3, [r7, #12] + pwrclkchanged = SET; + 80026c2: 2301 movs r3, #1 + 80026c4: 75fb strb r3, [r7, #23] + } + + if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 80026c6: 4b86 ldr r3, [pc, #536] ; (80028e0 ) + 80026c8: 681b ldr r3, [r3, #0] + 80026ca: f403 7380 and.w r3, r3, #256 ; 0x100 + 80026ce: 2b00 cmp r3, #0 + 80026d0: d118 bne.n 8002704 + { + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + 80026d2: 4b83 ldr r3, [pc, #524] ; (80028e0 ) + 80026d4: 681b ldr r3, [r3, #0] + 80026d6: 4a82 ldr r2, [pc, #520] ; (80028e0 ) + 80026d8: f443 7380 orr.w r3, r3, #256 ; 0x100 + 80026dc: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 80026de: f7ff fb73 bl 8001dc8 + 80026e2: 6138 str r0, [r7, #16] + + while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 80026e4: e008 b.n 80026f8 + { + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + 80026e6: f7ff fb6f bl 8001dc8 + 80026ea: 4602 mov r2, r0 + 80026ec: 693b ldr r3, [r7, #16] + 80026ee: 1ad3 subs r3, r2, r3 + 80026f0: 2b64 cmp r3, #100 ; 0x64 + 80026f2: d901 bls.n 80026f8 + { + return HAL_TIMEOUT; + 80026f4: 2303 movs r3, #3 + 80026f6: e0ed b.n 80028d4 + while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 80026f8: 4b79 ldr r3, [pc, #484] ; (80028e0 ) + 80026fa: 681b ldr r3, [r3, #0] + 80026fc: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002700: 2b00 cmp r3, #0 + 8002702: d0f0 beq.n 80026e6 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8002704: 687b ldr r3, [r7, #4] + 8002706: 689b ldr r3, [r3, #8] + 8002708: 2b01 cmp r3, #1 + 800270a: d106 bne.n 800271a + 800270c: 4b73 ldr r3, [pc, #460] ; (80028dc ) + 800270e: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002710: 4a72 ldr r2, [pc, #456] ; (80028dc ) + 8002712: f043 0301 orr.w r3, r3, #1 + 8002716: 6713 str r3, [r2, #112] ; 0x70 + 8002718: e02d b.n 8002776 + 800271a: 687b ldr r3, [r7, #4] + 800271c: 689b ldr r3, [r3, #8] + 800271e: 2b00 cmp r3, #0 + 8002720: d10c bne.n 800273c + 8002722: 4b6e ldr r3, [pc, #440] ; (80028dc ) + 8002724: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002726: 4a6d ldr r2, [pc, #436] ; (80028dc ) + 8002728: f023 0301 bic.w r3, r3, #1 + 800272c: 6713 str r3, [r2, #112] ; 0x70 + 800272e: 4b6b ldr r3, [pc, #428] ; (80028dc ) + 8002730: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002732: 4a6a ldr r2, [pc, #424] ; (80028dc ) + 8002734: f023 0304 bic.w r3, r3, #4 + 8002738: 6713 str r3, [r2, #112] ; 0x70 + 800273a: e01c b.n 8002776 + 800273c: 687b ldr r3, [r7, #4] + 800273e: 689b ldr r3, [r3, #8] + 8002740: 2b05 cmp r3, #5 + 8002742: d10c bne.n 800275e + 8002744: 4b65 ldr r3, [pc, #404] ; (80028dc ) + 8002746: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002748: 4a64 ldr r2, [pc, #400] ; (80028dc ) + 800274a: f043 0304 orr.w r3, r3, #4 + 800274e: 6713 str r3, [r2, #112] ; 0x70 + 8002750: 4b62 ldr r3, [pc, #392] ; (80028dc ) + 8002752: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002754: 4a61 ldr r2, [pc, #388] ; (80028dc ) + 8002756: f043 0301 orr.w r3, r3, #1 + 800275a: 6713 str r3, [r2, #112] ; 0x70 + 800275c: e00b b.n 8002776 + 800275e: 4b5f ldr r3, [pc, #380] ; (80028dc ) + 8002760: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002762: 4a5e ldr r2, [pc, #376] ; (80028dc ) + 8002764: f023 0301 bic.w r3, r3, #1 + 8002768: 6713 str r3, [r2, #112] ; 0x70 + 800276a: 4b5c ldr r3, [pc, #368] ; (80028dc ) + 800276c: 6f1b ldr r3, [r3, #112] ; 0x70 + 800276e: 4a5b ldr r2, [pc, #364] ; (80028dc ) + 8002770: f023 0304 bic.w r3, r3, #4 + 8002774: 6713 str r3, [r2, #112] ; 0x70 + /* Check the LSE State */ + if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + 8002776: 687b ldr r3, [r7, #4] + 8002778: 689b ldr r3, [r3, #8] + 800277a: 2b00 cmp r3, #0 + 800277c: d015 beq.n 80027aa + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800277e: f7ff fb23 bl 8001dc8 + 8002782: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8002784: e00a b.n 800279c + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8002786: f7ff fb1f bl 8001dc8 + 800278a: 4602 mov r2, r0 + 800278c: 693b ldr r3, [r7, #16] + 800278e: 1ad3 subs r3, r2, r3 + 8002790: f241 3288 movw r2, #5000 ; 0x1388 + 8002794: 4293 cmp r3, r2 + 8002796: d901 bls.n 800279c + { + return HAL_TIMEOUT; + 8002798: 2303 movs r3, #3 + 800279a: e09b b.n 80028d4 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 800279c: 4b4f ldr r3, [pc, #316] ; (80028dc ) + 800279e: 6f1b ldr r3, [r3, #112] ; 0x70 + 80027a0: f003 0302 and.w r3, r3, #2 + 80027a4: 2b00 cmp r3, #0 + 80027a6: d0ee beq.n 8002786 + 80027a8: e014 b.n 80027d4 + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80027aa: f7ff fb0d bl 8001dc8 + 80027ae: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 80027b0: e00a b.n 80027c8 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 80027b2: f7ff fb09 bl 8001dc8 + 80027b6: 4602 mov r2, r0 + 80027b8: 693b ldr r3, [r7, #16] + 80027ba: 1ad3 subs r3, r2, r3 + 80027bc: f241 3288 movw r2, #5000 ; 0x1388 + 80027c0: 4293 cmp r3, r2 + 80027c2: d901 bls.n 80027c8 + { + return HAL_TIMEOUT; + 80027c4: 2303 movs r3, #3 + 80027c6: e085 b.n 80028d4 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 80027c8: 4b44 ldr r3, [pc, #272] ; (80028dc ) + 80027ca: 6f1b ldr r3, [r3, #112] ; 0x70 + 80027cc: f003 0302 and.w r3, r3, #2 + 80027d0: 2b00 cmp r3, #0 + 80027d2: d1ee bne.n 80027b2 + } + } + } + + /* Restore clock configuration if changed */ + if(pwrclkchanged == SET) + 80027d4: 7dfb ldrb r3, [r7, #23] + 80027d6: 2b01 cmp r3, #1 + 80027d8: d105 bne.n 80027e6 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 80027da: 4b40 ldr r3, [pc, #256] ; (80028dc ) + 80027dc: 6c1b ldr r3, [r3, #64] ; 0x40 + 80027de: 4a3f ldr r2, [pc, #252] ; (80028dc ) + 80027e0: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 80027e4: 6413 str r3, [r2, #64] ; 0x40 + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 80027e6: 687b ldr r3, [r7, #4] + 80027e8: 699b ldr r3, [r3, #24] + 80027ea: 2b00 cmp r3, #0 + 80027ec: d071 beq.n 80028d2 + { + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 80027ee: 4b3b ldr r3, [pc, #236] ; (80028dc ) + 80027f0: 689b ldr r3, [r3, #8] + 80027f2: f003 030c and.w r3, r3, #12 + 80027f6: 2b08 cmp r3, #8 + 80027f8: d069 beq.n 80028ce + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 80027fa: 687b ldr r3, [r7, #4] + 80027fc: 699b ldr r3, [r3, #24] + 80027fe: 2b02 cmp r3, #2 + 8002800: d14b bne.n 800289a +#if defined (RCC_PLLCFGR_PLLR) + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); +#endif + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8002802: 4b36 ldr r3, [pc, #216] ; (80028dc ) + 8002804: 681b ldr r3, [r3, #0] + 8002806: 4a35 ldr r2, [pc, #212] ; (80028dc ) + 8002808: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 800280c: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800280e: f7ff fadb bl 8001dc8 + 8002812: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8002814: e008 b.n 8002828 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8002816: f7ff fad7 bl 8001dc8 + 800281a: 4602 mov r2, r0 + 800281c: 693b ldr r3, [r7, #16] + 800281e: 1ad3 subs r3, r2, r3 + 8002820: 2b02 cmp r3, #2 + 8002822: d901 bls.n 8002828 + { + return HAL_TIMEOUT; + 8002824: 2303 movs r3, #3 + 8002826: e055 b.n 80028d4 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8002828: 4b2c ldr r3, [pc, #176] ; (80028dc ) + 800282a: 681b ldr r3, [r3, #0] + 800282c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8002830: 2b00 cmp r3, #0 + 8002832: d1f0 bne.n 8002816 + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ +#if defined (RCC_PLLCFGR_PLLR) + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8002834: 687b ldr r3, [r7, #4] + 8002836: 69da ldr r2, [r3, #28] + 8002838: 687b ldr r3, [r7, #4] + 800283a: 6a1b ldr r3, [r3, #32] + 800283c: 431a orrs r2, r3 + 800283e: 687b ldr r3, [r7, #4] + 8002840: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002842: 019b lsls r3, r3, #6 + 8002844: 431a orrs r2, r3 + 8002846: 687b ldr r3, [r7, #4] + 8002848: 6a9b ldr r3, [r3, #40] ; 0x28 + 800284a: 085b lsrs r3, r3, #1 + 800284c: 3b01 subs r3, #1 + 800284e: 041b lsls r3, r3, #16 + 8002850: 431a orrs r2, r3 + 8002852: 687b ldr r3, [r7, #4] + 8002854: 6adb ldr r3, [r3, #44] ; 0x2c + 8002856: 061b lsls r3, r3, #24 + 8002858: 431a orrs r2, r3 + 800285a: 687b ldr r3, [r7, #4] + 800285c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800285e: 071b lsls r3, r3, #28 + 8002860: 491e ldr r1, [pc, #120] ; (80028dc ) + 8002862: 4313 orrs r3, r2 + 8002864: 604b str r3, [r1, #4] + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ); +#endif + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8002866: 4b1d ldr r3, [pc, #116] ; (80028dc ) + 8002868: 681b ldr r3, [r3, #0] + 800286a: 4a1c ldr r2, [pc, #112] ; (80028dc ) + 800286c: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 8002870: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002872: f7ff faa9 bl 8001dc8 + 8002876: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8002878: e008 b.n 800288c + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 800287a: f7ff faa5 bl 8001dc8 + 800287e: 4602 mov r2, r0 + 8002880: 693b ldr r3, [r7, #16] + 8002882: 1ad3 subs r3, r2, r3 + 8002884: 2b02 cmp r3, #2 + 8002886: d901 bls.n 800288c + { + return HAL_TIMEOUT; + 8002888: 2303 movs r3, #3 + 800288a: e023 b.n 80028d4 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 800288c: 4b13 ldr r3, [pc, #76] ; (80028dc ) + 800288e: 681b ldr r3, [r3, #0] + 8002890: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8002894: 2b00 cmp r3, #0 + 8002896: d0f0 beq.n 800287a + 8002898: e01b b.n 80028d2 + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 800289a: 4b10 ldr r3, [pc, #64] ; (80028dc ) + 800289c: 681b ldr r3, [r3, #0] + 800289e: 4a0f ldr r2, [pc, #60] ; (80028dc ) + 80028a0: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 80028a4: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80028a6: f7ff fa8f bl 8001dc8 + 80028aa: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 80028ac: e008 b.n 80028c0 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 80028ae: f7ff fa8b bl 8001dc8 + 80028b2: 4602 mov r2, r0 + 80028b4: 693b ldr r3, [r7, #16] + 80028b6: 1ad3 subs r3, r2, r3 + 80028b8: 2b02 cmp r3, #2 + 80028ba: d901 bls.n 80028c0 + { + return HAL_TIMEOUT; + 80028bc: 2303 movs r3, #3 + 80028be: e009 b.n 80028d4 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 80028c0: 4b06 ldr r3, [pc, #24] ; (80028dc ) + 80028c2: 681b ldr r3, [r3, #0] + 80028c4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 80028c8: 2b00 cmp r3, #0 + 80028ca: d1f0 bne.n 80028ae + 80028cc: e001 b.n 80028d2 + } + } + } + else + { + return HAL_ERROR; + 80028ce: 2301 movs r3, #1 + 80028d0: e000 b.n 80028d4 + } + } + return HAL_OK; + 80028d2: 2300 movs r3, #0 +} + 80028d4: 4618 mov r0, r3 + 80028d6: 3718 adds r7, #24 + 80028d8: 46bd mov sp, r7 + 80028da: bd80 pop {r7, pc} + 80028dc: 40023800 .word 0x40023800 + 80028e0: 40007000 .word 0x40007000 + +080028e4 : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 80028e4: b580 push {r7, lr} + 80028e6: b084 sub sp, #16 + 80028e8: af00 add r7, sp, #0 + 80028ea: 6078 str r0, [r7, #4] + 80028ec: 6039 str r1, [r7, #0] + uint32_t tickstart = 0; + 80028ee: 2300 movs r3, #0 + 80028f0: 60fb str r3, [r7, #12] + + /* Check Null pointer */ + if(RCC_ClkInitStruct == NULL) + 80028f2: 687b ldr r3, [r7, #4] + 80028f4: 2b00 cmp r3, #0 + 80028f6: d101 bne.n 80028fc + { + return HAL_ERROR; + 80028f8: 2301 movs r3, #1 + 80028fa: e0ce b.n 8002a9a + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 80028fc: 4b69 ldr r3, [pc, #420] ; (8002aa4 ) + 80028fe: 681b ldr r3, [r3, #0] + 8002900: f003 030f and.w r3, r3, #15 + 8002904: 683a ldr r2, [r7, #0] + 8002906: 429a cmp r2, r3 + 8002908: d910 bls.n 800292c + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 800290a: 4b66 ldr r3, [pc, #408] ; (8002aa4 ) + 800290c: 681b ldr r3, [r3, #0] + 800290e: f023 020f bic.w r2, r3, #15 + 8002912: 4964 ldr r1, [pc, #400] ; (8002aa4 ) + 8002914: 683b ldr r3, [r7, #0] + 8002916: 4313 orrs r3, r2 + 8002918: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 800291a: 4b62 ldr r3, [pc, #392] ; (8002aa4 ) + 800291c: 681b ldr r3, [r3, #0] + 800291e: f003 030f and.w r3, r3, #15 + 8002922: 683a ldr r2, [r7, #0] + 8002924: 429a cmp r2, r3 + 8002926: d001 beq.n 800292c + { + return HAL_ERROR; + 8002928: 2301 movs r3, #1 + 800292a: e0b6 b.n 8002a9a + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 800292c: 687b ldr r3, [r7, #4] + 800292e: 681b ldr r3, [r3, #0] + 8002930: f003 0302 and.w r3, r3, #2 + 8002934: 2b00 cmp r3, #0 + 8002936: d020 beq.n 800297a + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8002938: 687b ldr r3, [r7, #4] + 800293a: 681b ldr r3, [r3, #0] + 800293c: f003 0304 and.w r3, r3, #4 + 8002940: 2b00 cmp r3, #0 + 8002942: d005 beq.n 8002950 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + 8002944: 4b58 ldr r3, [pc, #352] ; (8002aa8 ) + 8002946: 689b ldr r3, [r3, #8] + 8002948: 4a57 ldr r2, [pc, #348] ; (8002aa8 ) + 800294a: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00 + 800294e: 6093 str r3, [r2, #8] + } + + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8002950: 687b ldr r3, [r7, #4] + 8002952: 681b ldr r3, [r3, #0] + 8002954: f003 0308 and.w r3, r3, #8 + 8002958: 2b00 cmp r3, #0 + 800295a: d005 beq.n 8002968 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + 800295c: 4b52 ldr r3, [pc, #328] ; (8002aa8 ) + 800295e: 689b ldr r3, [r3, #8] + 8002960: 4a51 ldr r2, [pc, #324] ; (8002aa8 ) + 8002962: f443 4360 orr.w r3, r3, #57344 ; 0xe000 + 8002966: 6093 str r3, [r2, #8] + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8002968: 4b4f ldr r3, [pc, #316] ; (8002aa8 ) + 800296a: 689b ldr r3, [r3, #8] + 800296c: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 8002970: 687b ldr r3, [r7, #4] + 8002972: 689b ldr r3, [r3, #8] + 8002974: 494c ldr r1, [pc, #304] ; (8002aa8 ) + 8002976: 4313 orrs r3, r2 + 8002978: 608b str r3, [r1, #8] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 800297a: 687b ldr r3, [r7, #4] + 800297c: 681b ldr r3, [r3, #0] + 800297e: f003 0301 and.w r3, r3, #1 + 8002982: 2b00 cmp r3, #0 + 8002984: d040 beq.n 8002a08 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8002986: 687b ldr r3, [r7, #4] + 8002988: 685b ldr r3, [r3, #4] + 800298a: 2b01 cmp r3, #1 + 800298c: d107 bne.n 800299e + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 800298e: 4b46 ldr r3, [pc, #280] ; (8002aa8 ) + 8002990: 681b ldr r3, [r3, #0] + 8002992: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002996: 2b00 cmp r3, #0 + 8002998: d115 bne.n 80029c6 + { + return HAL_ERROR; + 800299a: 2301 movs r3, #1 + 800299c: e07d b.n 8002a9a + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 800299e: 687b ldr r3, [r7, #4] + 80029a0: 685b ldr r3, [r3, #4] + 80029a2: 2b02 cmp r3, #2 + 80029a4: d107 bne.n 80029b6 + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 80029a6: 4b40 ldr r3, [pc, #256] ; (8002aa8 ) + 80029a8: 681b ldr r3, [r3, #0] + 80029aa: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 80029ae: 2b00 cmp r3, #0 + 80029b0: d109 bne.n 80029c6 + { + return HAL_ERROR; + 80029b2: 2301 movs r3, #1 + 80029b4: e071 b.n 8002a9a + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 80029b6: 4b3c ldr r3, [pc, #240] ; (8002aa8 ) + 80029b8: 681b ldr r3, [r3, #0] + 80029ba: f003 0302 and.w r3, r3, #2 + 80029be: 2b00 cmp r3, #0 + 80029c0: d101 bne.n 80029c6 + { + return HAL_ERROR; + 80029c2: 2301 movs r3, #1 + 80029c4: e069 b.n 8002a9a + } + } + + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 80029c6: 4b38 ldr r3, [pc, #224] ; (8002aa8 ) + 80029c8: 689b ldr r3, [r3, #8] + 80029ca: f023 0203 bic.w r2, r3, #3 + 80029ce: 687b ldr r3, [r7, #4] + 80029d0: 685b ldr r3, [r3, #4] + 80029d2: 4935 ldr r1, [pc, #212] ; (8002aa8 ) + 80029d4: 4313 orrs r3, r2 + 80029d6: 608b str r3, [r1, #8] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80029d8: f7ff f9f6 bl 8001dc8 + 80029dc: 60f8 str r0, [r7, #12] + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 80029de: e00a b.n 80029f6 + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 80029e0: f7ff f9f2 bl 8001dc8 + 80029e4: 4602 mov r2, r0 + 80029e6: 68fb ldr r3, [r7, #12] + 80029e8: 1ad3 subs r3, r2, r3 + 80029ea: f241 3288 movw r2, #5000 ; 0x1388 + 80029ee: 4293 cmp r3, r2 + 80029f0: d901 bls.n 80029f6 + { + return HAL_TIMEOUT; + 80029f2: 2303 movs r3, #3 + 80029f4: e051 b.n 8002a9a + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 80029f6: 4b2c ldr r3, [pc, #176] ; (8002aa8 ) + 80029f8: 689b ldr r3, [r3, #8] + 80029fa: f003 020c and.w r2, r3, #12 + 80029fe: 687b ldr r3, [r7, #4] + 8002a00: 685b ldr r3, [r3, #4] + 8002a02: 009b lsls r3, r3, #2 + 8002a04: 429a cmp r2, r3 + 8002a06: d1eb bne.n 80029e0 + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 8002a08: 4b26 ldr r3, [pc, #152] ; (8002aa4 ) + 8002a0a: 681b ldr r3, [r3, #0] + 8002a0c: f003 030f and.w r3, r3, #15 + 8002a10: 683a ldr r2, [r7, #0] + 8002a12: 429a cmp r2, r3 + 8002a14: d210 bcs.n 8002a38 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8002a16: 4b23 ldr r3, [pc, #140] ; (8002aa4 ) + 8002a18: 681b ldr r3, [r3, #0] + 8002a1a: f023 020f bic.w r2, r3, #15 + 8002a1e: 4921 ldr r1, [pc, #132] ; (8002aa4 ) + 8002a20: 683b ldr r3, [r7, #0] + 8002a22: 4313 orrs r3, r2 + 8002a24: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8002a26: 4b1f ldr r3, [pc, #124] ; (8002aa4 ) + 8002a28: 681b ldr r3, [r3, #0] + 8002a2a: f003 030f and.w r3, r3, #15 + 8002a2e: 683a ldr r2, [r7, #0] + 8002a30: 429a cmp r2, r3 + 8002a32: d001 beq.n 8002a38 + { + return HAL_ERROR; + 8002a34: 2301 movs r3, #1 + 8002a36: e030 b.n 8002a9a + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8002a38: 687b ldr r3, [r7, #4] + 8002a3a: 681b ldr r3, [r3, #0] + 8002a3c: f003 0304 and.w r3, r3, #4 + 8002a40: 2b00 cmp r3, #0 + 8002a42: d008 beq.n 8002a56 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 8002a44: 4b18 ldr r3, [pc, #96] ; (8002aa8 ) + 8002a46: 689b ldr r3, [r3, #8] + 8002a48: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 + 8002a4c: 687b ldr r3, [r7, #4] + 8002a4e: 68db ldr r3, [r3, #12] + 8002a50: 4915 ldr r1, [pc, #84] ; (8002aa8 ) + 8002a52: 4313 orrs r3, r2 + 8002a54: 608b str r3, [r1, #8] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8002a56: 687b ldr r3, [r7, #4] + 8002a58: 681b ldr r3, [r3, #0] + 8002a5a: f003 0308 and.w r3, r3, #8 + 8002a5e: 2b00 cmp r3, #0 + 8002a60: d009 beq.n 8002a76 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + 8002a62: 4b11 ldr r3, [pc, #68] ; (8002aa8 ) + 8002a64: 689b ldr r3, [r3, #8] + 8002a66: f423 4260 bic.w r2, r3, #57344 ; 0xe000 + 8002a6a: 687b ldr r3, [r7, #4] + 8002a6c: 691b ldr r3, [r3, #16] + 8002a6e: 00db lsls r3, r3, #3 + 8002a70: 490d ldr r1, [pc, #52] ; (8002aa8 ) + 8002a72: 4313 orrs r3, r2 + 8002a74: 608b str r3, [r1, #8] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + 8002a76: f000 f81d bl 8002ab4 + 8002a7a: 4601 mov r1, r0 + 8002a7c: 4b0a ldr r3, [pc, #40] ; (8002aa8 ) + 8002a7e: 689b ldr r3, [r3, #8] + 8002a80: 091b lsrs r3, r3, #4 + 8002a82: f003 030f and.w r3, r3, #15 + 8002a86: 4a09 ldr r2, [pc, #36] ; (8002aac ) + 8002a88: 5cd3 ldrb r3, [r2, r3] + 8002a8a: fa21 f303 lsr.w r3, r1, r3 + 8002a8e: 4a08 ldr r2, [pc, #32] ; (8002ab0 ) + 8002a90: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick (TICK_INT_PRIORITY); + 8002a92: 2000 movs r0, #0 + 8002a94: f7ff f954 bl 8001d40 + + return HAL_OK; + 8002a98: 2300 movs r3, #0 +} + 8002a9a: 4618 mov r0, r3 + 8002a9c: 3710 adds r7, #16 + 8002a9e: 46bd mov sp, r7 + 8002aa0: bd80 pop {r7, pc} + 8002aa2: bf00 nop + 8002aa4: 40023c00 .word 0x40023c00 + 8002aa8: 40023800 .word 0x40023800 + 8002aac: 080055d8 .word 0x080055d8 + 8002ab0: 20000004 .word 0x20000004 + +08002ab4 : + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8002ab4: b5f0 push {r4, r5, r6, r7, lr} + 8002ab6: b085 sub sp, #20 + 8002ab8: af00 add r7, sp, #0 + uint32_t pllm = 0, pllvco = 0, pllp = 0; + 8002aba: 2300 movs r3, #0 + 8002abc: 607b str r3, [r7, #4] + 8002abe: 2300 movs r3, #0 + 8002ac0: 60fb str r3, [r7, #12] + 8002ac2: 2300 movs r3, #0 + 8002ac4: 603b str r3, [r7, #0] + uint32_t sysclockfreq = 0; + 8002ac6: 2300 movs r3, #0 + 8002ac8: 60bb str r3, [r7, #8] + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + 8002aca: 4b50 ldr r3, [pc, #320] ; (8002c0c ) + 8002acc: 689b ldr r3, [r3, #8] + 8002ace: f003 030c and.w r3, r3, #12 + 8002ad2: 2b04 cmp r3, #4 + 8002ad4: d007 beq.n 8002ae6 + 8002ad6: 2b08 cmp r3, #8 + 8002ad8: d008 beq.n 8002aec + 8002ada: 2b00 cmp r3, #0 + 8002adc: f040 808d bne.w 8002bfa + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + 8002ae0: 4b4b ldr r3, [pc, #300] ; (8002c10 ) + 8002ae2: 60bb str r3, [r7, #8] + break; + 8002ae4: e08c b.n 8002c00 + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + { + sysclockfreq = HSE_VALUE; + 8002ae6: 4b4b ldr r3, [pc, #300] ; (8002c14 ) + 8002ae8: 60bb str r3, [r7, #8] + break; + 8002aea: e089 b.n 8002c00 + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + 8002aec: 4b47 ldr r3, [pc, #284] ; (8002c0c ) + 8002aee: 685b ldr r3, [r3, #4] + 8002af0: f003 033f and.w r3, r3, #63 ; 0x3f + 8002af4: 607b str r3, [r7, #4] + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) + 8002af6: 4b45 ldr r3, [pc, #276] ; (8002c0c ) + 8002af8: 685b ldr r3, [r3, #4] + 8002afa: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8002afe: 2b00 cmp r3, #0 + 8002b00: d023 beq.n 8002b4a + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 8002b02: 4b42 ldr r3, [pc, #264] ; (8002c0c ) + 8002b04: 685b ldr r3, [r3, #4] + 8002b06: 099b lsrs r3, r3, #6 + 8002b08: f04f 0400 mov.w r4, #0 + 8002b0c: f240 11ff movw r1, #511 ; 0x1ff + 8002b10: f04f 0200 mov.w r2, #0 + 8002b14: ea03 0501 and.w r5, r3, r1 + 8002b18: ea04 0602 and.w r6, r4, r2 + 8002b1c: 4a3d ldr r2, [pc, #244] ; (8002c14 ) + 8002b1e: fb02 f106 mul.w r1, r2, r6 + 8002b22: 2200 movs r2, #0 + 8002b24: fb02 f205 mul.w r2, r2, r5 + 8002b28: 440a add r2, r1 + 8002b2a: 493a ldr r1, [pc, #232] ; (8002c14 ) + 8002b2c: fba5 0101 umull r0, r1, r5, r1 + 8002b30: 1853 adds r3, r2, r1 + 8002b32: 4619 mov r1, r3 + 8002b34: 687b ldr r3, [r7, #4] + 8002b36: f04f 0400 mov.w r4, #0 + 8002b3a: 461a mov r2, r3 + 8002b3c: 4623 mov r3, r4 + 8002b3e: f7fd fb7b bl 8000238 <__aeabi_uldivmod> + 8002b42: 4603 mov r3, r0 + 8002b44: 460c mov r4, r1 + 8002b46: 60fb str r3, [r7, #12] + 8002b48: e049 b.n 8002bde + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 8002b4a: 4b30 ldr r3, [pc, #192] ; (8002c0c ) + 8002b4c: 685b ldr r3, [r3, #4] + 8002b4e: 099b lsrs r3, r3, #6 + 8002b50: f04f 0400 mov.w r4, #0 + 8002b54: f240 11ff movw r1, #511 ; 0x1ff + 8002b58: f04f 0200 mov.w r2, #0 + 8002b5c: ea03 0501 and.w r5, r3, r1 + 8002b60: ea04 0602 and.w r6, r4, r2 + 8002b64: 4629 mov r1, r5 + 8002b66: 4632 mov r2, r6 + 8002b68: f04f 0300 mov.w r3, #0 + 8002b6c: f04f 0400 mov.w r4, #0 + 8002b70: 0154 lsls r4, r2, #5 + 8002b72: ea44 64d1 orr.w r4, r4, r1, lsr #27 + 8002b76: 014b lsls r3, r1, #5 + 8002b78: 4619 mov r1, r3 + 8002b7a: 4622 mov r2, r4 + 8002b7c: 1b49 subs r1, r1, r5 + 8002b7e: eb62 0206 sbc.w r2, r2, r6 + 8002b82: f04f 0300 mov.w r3, #0 + 8002b86: f04f 0400 mov.w r4, #0 + 8002b8a: 0194 lsls r4, r2, #6 + 8002b8c: ea44 6491 orr.w r4, r4, r1, lsr #26 + 8002b90: 018b lsls r3, r1, #6 + 8002b92: 1a5b subs r3, r3, r1 + 8002b94: eb64 0402 sbc.w r4, r4, r2 + 8002b98: f04f 0100 mov.w r1, #0 + 8002b9c: f04f 0200 mov.w r2, #0 + 8002ba0: 00e2 lsls r2, r4, #3 + 8002ba2: ea42 7253 orr.w r2, r2, r3, lsr #29 + 8002ba6: 00d9 lsls r1, r3, #3 + 8002ba8: 460b mov r3, r1 + 8002baa: 4614 mov r4, r2 + 8002bac: 195b adds r3, r3, r5 + 8002bae: eb44 0406 adc.w r4, r4, r6 + 8002bb2: f04f 0100 mov.w r1, #0 + 8002bb6: f04f 0200 mov.w r2, #0 + 8002bba: 02a2 lsls r2, r4, #10 + 8002bbc: ea42 5293 orr.w r2, r2, r3, lsr #22 + 8002bc0: 0299 lsls r1, r3, #10 + 8002bc2: 460b mov r3, r1 + 8002bc4: 4614 mov r4, r2 + 8002bc6: 4618 mov r0, r3 + 8002bc8: 4621 mov r1, r4 + 8002bca: 687b ldr r3, [r7, #4] + 8002bcc: f04f 0400 mov.w r4, #0 + 8002bd0: 461a mov r2, r3 + 8002bd2: 4623 mov r3, r4 + 8002bd4: f7fd fb30 bl 8000238 <__aeabi_uldivmod> + 8002bd8: 4603 mov r3, r0 + 8002bda: 460c mov r4, r1 + 8002bdc: 60fb str r3, [r7, #12] + } + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2); + 8002bde: 4b0b ldr r3, [pc, #44] ; (8002c0c ) + 8002be0: 685b ldr r3, [r3, #4] + 8002be2: 0c1b lsrs r3, r3, #16 + 8002be4: f003 0303 and.w r3, r3, #3 + 8002be8: 3301 adds r3, #1 + 8002bea: 005b lsls r3, r3, #1 + 8002bec: 603b str r3, [r7, #0] + + sysclockfreq = pllvco/pllp; + 8002bee: 68fa ldr r2, [r7, #12] + 8002bf0: 683b ldr r3, [r7, #0] + 8002bf2: fbb2 f3f3 udiv r3, r2, r3 + 8002bf6: 60bb str r3, [r7, #8] + break; + 8002bf8: e002 b.n 8002c00 + } + default: + { + sysclockfreq = HSI_VALUE; + 8002bfa: 4b05 ldr r3, [pc, #20] ; (8002c10 ) + 8002bfc: 60bb str r3, [r7, #8] + break; + 8002bfe: bf00 nop + } + } + return sysclockfreq; + 8002c00: 68bb ldr r3, [r7, #8] +} + 8002c02: 4618 mov r0, r3 + 8002c04: 3714 adds r7, #20 + 8002c06: 46bd mov sp, r7 + 8002c08: bdf0 pop {r4, r5, r6, r7, pc} + 8002c0a: bf00 nop + 8002c0c: 40023800 .word 0x40023800 + 8002c10: 00f42400 .word 0x00f42400 + 8002c14: 017d7840 .word 0x017d7840 + +08002c18 : + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + 8002c18: b480 push {r7} + 8002c1a: af00 add r7, sp, #0 + return SystemCoreClock; + 8002c1c: 4b03 ldr r3, [pc, #12] ; (8002c2c ) + 8002c1e: 681b ldr r3, [r3, #0] +} + 8002c20: 4618 mov r0, r3 + 8002c22: 46bd mov sp, r7 + 8002c24: f85d 7b04 ldr.w r7, [sp], #4 + 8002c28: 4770 bx lr + 8002c2a: bf00 nop + 8002c2c: 20000004 .word 0x20000004 + +08002c30 : + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + 8002c30: b580 push {r7, lr} + 8002c32: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]); + 8002c34: f7ff fff0 bl 8002c18 + 8002c38: 4601 mov r1, r0 + 8002c3a: 4b05 ldr r3, [pc, #20] ; (8002c50 ) + 8002c3c: 689b ldr r3, [r3, #8] + 8002c3e: 0a9b lsrs r3, r3, #10 + 8002c40: f003 0307 and.w r3, r3, #7 + 8002c44: 4a03 ldr r2, [pc, #12] ; (8002c54 ) + 8002c46: 5cd3 ldrb r3, [r2, r3] + 8002c48: fa21 f303 lsr.w r3, r1, r3 +} + 8002c4c: 4618 mov r0, r3 + 8002c4e: bd80 pop {r7, pc} + 8002c50: 40023800 .word 0x40023800 + 8002c54: 080055e8 .word 0x080055e8 + +08002c58 : + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + 8002c58: b580 push {r7, lr} + 8002c5a: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]); + 8002c5c: f7ff ffdc bl 8002c18 + 8002c60: 4601 mov r1, r0 + 8002c62: 4b05 ldr r3, [pc, #20] ; (8002c78 ) + 8002c64: 689b ldr r3, [r3, #8] + 8002c66: 0b5b lsrs r3, r3, #13 + 8002c68: f003 0307 and.w r3, r3, #7 + 8002c6c: 4a03 ldr r2, [pc, #12] ; (8002c7c ) + 8002c6e: 5cd3 ldrb r3, [r2, r3] + 8002c70: fa21 f303 lsr.w r3, r1, r3 +} + 8002c74: 4618 mov r0, r3 + 8002c76: bd80 pop {r7, pc} + 8002c78: 40023800 .word 0x40023800 + 8002c7c: 080055e8 .word 0x080055e8 + +08002c80 : + * the backup registers) are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + 8002c80: b580 push {r7, lr} + 8002c82: b088 sub sp, #32 + 8002c84: af00 add r7, sp, #0 + 8002c86: 6078 str r0, [r7, #4] + uint32_t tickstart = 0; + 8002c88: 2300 movs r3, #0 + 8002c8a: 617b str r3, [r7, #20] + uint32_t tmpreg0 = 0; + 8002c8c: 2300 movs r3, #0 + 8002c8e: 613b str r3, [r7, #16] + uint32_t tmpreg1 = 0; + 8002c90: 2300 movs r3, #0 + 8002c92: 60fb str r3, [r7, #12] + uint32_t plli2sused = 0; + 8002c94: 2300 movs r3, #0 + 8002c96: 61fb str r3, [r7, #28] + uint32_t pllsaiused = 0; + 8002c98: 2300 movs r3, #0 + 8002c9a: 61bb str r3, [r7, #24] + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*----------------------------------- I2S configuration ----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + 8002c9c: 687b ldr r3, [r7, #4] + 8002c9e: 681b ldr r3, [r3, #0] + 8002ca0: f003 0301 and.w r3, r3, #1 + 8002ca4: 2b00 cmp r3, #0 + 8002ca6: d012 beq.n 8002cce + { + /* Check the parameters */ + assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + 8002ca8: 4b69 ldr r3, [pc, #420] ; (8002e50 ) + 8002caa: 689b ldr r3, [r3, #8] + 8002cac: 4a68 ldr r2, [pc, #416] ; (8002e50 ) + 8002cae: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 + 8002cb2: 6093 str r3, [r2, #8] + 8002cb4: 4b66 ldr r3, [pc, #408] ; (8002e50 ) + 8002cb6: 689a ldr r2, [r3, #8] + 8002cb8: 687b ldr r3, [r7, #4] + 8002cba: 6b5b ldr r3, [r3, #52] ; 0x34 + 8002cbc: 4964 ldr r1, [pc, #400] ; (8002e50 ) + 8002cbe: 4313 orrs r3, r2 + 8002cc0: 608b str r3, [r1, #8] + + /* Enable the PLLI2S when it's used as clock source for I2S */ + if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) + 8002cc2: 687b ldr r3, [r7, #4] + 8002cc4: 6b5b ldr r3, [r3, #52] ; 0x34 + 8002cc6: 2b00 cmp r3, #0 + 8002cc8: d101 bne.n 8002cce + { + plli2sused = 1; + 8002cca: 2301 movs r3, #1 + 8002ccc: 61fb str r3, [r7, #28] + } + } + + /*------------------------------------ SAI1 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) + 8002cce: 687b ldr r3, [r7, #4] + 8002cd0: 681b ldr r3, [r3, #0] + 8002cd2: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 8002cd6: 2b00 cmp r3, #0 + 8002cd8: d017 beq.n 8002d0a + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + 8002cda: 4b5d ldr r3, [pc, #372] ; (8002e50 ) + 8002cdc: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8002ce0: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 + 8002ce4: 687b ldr r3, [r7, #4] + 8002ce6: 6bdb ldr r3, [r3, #60] ; 0x3c + 8002ce8: 4959 ldr r1, [pc, #356] ; (8002e50 ) + 8002cea: 4313 orrs r3, r2 + 8002cec: f8c1 308c str.w r3, [r1, #140] ; 0x8c + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) + 8002cf0: 687b ldr r3, [r7, #4] + 8002cf2: 6bdb ldr r3, [r3, #60] ; 0x3c + 8002cf4: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 8002cf8: d101 bne.n 8002cfe + { + plli2sused = 1; + 8002cfa: 2301 movs r3, #1 + 8002cfc: 61fb str r3, [r7, #28] + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) + 8002cfe: 687b ldr r3, [r7, #4] + 8002d00: 6bdb ldr r3, [r3, #60] ; 0x3c + 8002d02: 2b00 cmp r3, #0 + 8002d04: d101 bne.n 8002d0a + { + pllsaiused = 1; + 8002d06: 2301 movs r3, #1 + 8002d08: 61bb str r3, [r7, #24] + } + } + + /*------------------------------------ SAI2 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) + 8002d0a: 687b ldr r3, [r7, #4] + 8002d0c: 681b ldr r3, [r3, #0] + 8002d0e: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8002d12: 2b00 cmp r3, #0 + 8002d14: d017 beq.n 8002d46 + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + + /* Configure SAI2 Clock source */ + __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + 8002d16: 4b4e ldr r3, [pc, #312] ; (8002e50 ) + 8002d18: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8002d1c: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 + 8002d20: 687b ldr r3, [r7, #4] + 8002d22: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002d24: 494a ldr r1, [pc, #296] ; (8002e50 ) + 8002d26: 4313 orrs r3, r2 + 8002d28: f8c1 308c str.w r3, [r1, #140] ; 0x8c + + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) + 8002d2c: 687b ldr r3, [r7, #4] + 8002d2e: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002d30: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 8002d34: d101 bne.n 8002d3a + { + plli2sused = 1; + 8002d36: 2301 movs r3, #1 + 8002d38: 61fb str r3, [r7, #28] + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) + 8002d3a: 687b ldr r3, [r7, #4] + 8002d3c: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002d3e: 2b00 cmp r3, #0 + 8002d40: d101 bne.n 8002d46 + { + pllsaiused = 1; + 8002d42: 2301 movs r3, #1 + 8002d44: 61bb str r3, [r7, #24] + } + } + + /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + 8002d46: 687b ldr r3, [r7, #4] + 8002d48: 681b ldr r3, [r3, #0] + 8002d4a: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 8002d4e: 2b00 cmp r3, #0 + 8002d50: d001 beq.n 8002d56 + { + plli2sused = 1; + 8002d52: 2301 movs r3, #1 + 8002d54: 61fb str r3, [r7, #28] + } + + /*------------------------------------ RTC configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + 8002d56: 687b ldr r3, [r7, #4] + 8002d58: 681b ldr r3, [r3, #0] + 8002d5a: f003 0320 and.w r3, r3, #32 + 8002d5e: 2b00 cmp r3, #0 + 8002d60: f000 808b beq.w 8002e7a + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + 8002d64: 4b3a ldr r3, [pc, #232] ; (8002e50 ) + 8002d66: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002d68: 4a39 ldr r2, [pc, #228] ; (8002e50 ) + 8002d6a: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8002d6e: 6413 str r3, [r2, #64] ; 0x40 + 8002d70: 4b37 ldr r3, [pc, #220] ; (8002e50 ) + 8002d72: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002d74: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8002d78: 60bb str r3, [r7, #8] + 8002d7a: 68bb ldr r3, [r7, #8] + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + 8002d7c: 4b35 ldr r3, [pc, #212] ; (8002e54 ) + 8002d7e: 681b ldr r3, [r3, #0] + 8002d80: 4a34 ldr r2, [pc, #208] ; (8002e54 ) + 8002d82: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8002d86: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002d88: f7ff f81e bl 8001dc8 + 8002d8c: 6178 str r0, [r7, #20] + + /* Wait for Backup domain Write protection disable */ + while((PWR->CR1 & PWR_CR1_DBP) == RESET) + 8002d8e: e008 b.n 8002da2 + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8002d90: f7ff f81a bl 8001dc8 + 8002d94: 4602 mov r2, r0 + 8002d96: 697b ldr r3, [r7, #20] + 8002d98: 1ad3 subs r3, r2, r3 + 8002d9a: 2b64 cmp r3, #100 ; 0x64 + 8002d9c: d901 bls.n 8002da2 + { + return HAL_TIMEOUT; + 8002d9e: 2303 movs r3, #3 + 8002da0: e38d b.n 80034be + while((PWR->CR1 & PWR_CR1_DBP) == RESET) + 8002da2: 4b2c ldr r3, [pc, #176] ; (8002e54 ) + 8002da4: 681b ldr r3, [r3, #0] + 8002da6: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002daa: 2b00 cmp r3, #0 + 8002dac: d0f0 beq.n 8002d90 + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); + 8002dae: 4b28 ldr r3, [pc, #160] ; (8002e50 ) + 8002db0: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002db2: f403 7340 and.w r3, r3, #768 ; 0x300 + 8002db6: 613b str r3, [r7, #16] + + if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + 8002db8: 693b ldr r3, [r7, #16] + 8002dba: 2b00 cmp r3, #0 + 8002dbc: d035 beq.n 8002e2a + 8002dbe: 687b ldr r3, [r7, #4] + 8002dc0: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002dc2: f403 7340 and.w r3, r3, #768 ; 0x300 + 8002dc6: 693a ldr r2, [r7, #16] + 8002dc8: 429a cmp r2, r3 + 8002dca: d02e beq.n 8002e2a + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + 8002dcc: 4b20 ldr r3, [pc, #128] ; (8002e50 ) + 8002dce: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002dd0: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8002dd4: 613b str r3, [r7, #16] + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + 8002dd6: 4b1e ldr r3, [pc, #120] ; (8002e50 ) + 8002dd8: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002dda: 4a1d ldr r2, [pc, #116] ; (8002e50 ) + 8002ddc: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8002de0: 6713 str r3, [r2, #112] ; 0x70 + __HAL_RCC_BACKUPRESET_RELEASE(); + 8002de2: 4b1b ldr r3, [pc, #108] ; (8002e50 ) + 8002de4: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002de6: 4a1a ldr r2, [pc, #104] ; (8002e50 ) + 8002de8: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8002dec: 6713 str r3, [r2, #112] ; 0x70 + + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg0; + 8002dee: 4a18 ldr r2, [pc, #96] ; (8002e50 ) + 8002df0: 693b ldr r3, [r7, #16] + 8002df2: 6713 str r3, [r2, #112] ; 0x70 + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + 8002df4: 4b16 ldr r3, [pc, #88] ; (8002e50 ) + 8002df6: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002df8: f003 0301 and.w r3, r3, #1 + 8002dfc: 2b01 cmp r3, #1 + 8002dfe: d114 bne.n 8002e2a + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002e00: f7fe ffe2 bl 8001dc8 + 8002e04: 6178 str r0, [r7, #20] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8002e06: e00a b.n 8002e1e + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8002e08: f7fe ffde bl 8001dc8 + 8002e0c: 4602 mov r2, r0 + 8002e0e: 697b ldr r3, [r7, #20] + 8002e10: 1ad3 subs r3, r2, r3 + 8002e12: f241 3288 movw r2, #5000 ; 0x1388 + 8002e16: 4293 cmp r3, r2 + 8002e18: d901 bls.n 8002e1e + { + return HAL_TIMEOUT; + 8002e1a: 2303 movs r3, #3 + 8002e1c: e34f b.n 80034be + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8002e1e: 4b0c ldr r3, [pc, #48] ; (8002e50 ) + 8002e20: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002e22: f003 0302 and.w r3, r3, #2 + 8002e26: 2b00 cmp r3, #0 + 8002e28: d0ee beq.n 8002e08 + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 8002e2a: 687b ldr r3, [r7, #4] + 8002e2c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002e2e: f403 7340 and.w r3, r3, #768 ; 0x300 + 8002e32: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 8002e36: d111 bne.n 8002e5c + 8002e38: 4b05 ldr r3, [pc, #20] ; (8002e50 ) + 8002e3a: 689b ldr r3, [r3, #8] + 8002e3c: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000 + 8002e40: 687b ldr r3, [r7, #4] + 8002e42: 6b19 ldr r1, [r3, #48] ; 0x30 + 8002e44: 4b04 ldr r3, [pc, #16] ; (8002e58 ) + 8002e46: 400b ands r3, r1 + 8002e48: 4901 ldr r1, [pc, #4] ; (8002e50 ) + 8002e4a: 4313 orrs r3, r2 + 8002e4c: 608b str r3, [r1, #8] + 8002e4e: e00b b.n 8002e68 + 8002e50: 40023800 .word 0x40023800 + 8002e54: 40007000 .word 0x40007000 + 8002e58: 0ffffcff .word 0x0ffffcff + 8002e5c: 4bb3 ldr r3, [pc, #716] ; (800312c ) + 8002e5e: 689b ldr r3, [r3, #8] + 8002e60: 4ab2 ldr r2, [pc, #712] ; (800312c ) + 8002e62: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000 + 8002e66: 6093 str r3, [r2, #8] + 8002e68: 4bb0 ldr r3, [pc, #704] ; (800312c ) + 8002e6a: 6f1a ldr r2, [r3, #112] ; 0x70 + 8002e6c: 687b ldr r3, [r7, #4] + 8002e6e: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002e70: f3c3 030b ubfx r3, r3, #0, #12 + 8002e74: 49ad ldr r1, [pc, #692] ; (800312c ) + 8002e76: 4313 orrs r3, r2 + 8002e78: 670b str r3, [r1, #112] ; 0x70 + } + + /*------------------------------------ TIM configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + 8002e7a: 687b ldr r3, [r7, #4] + 8002e7c: 681b ldr r3, [r3, #0] + 8002e7e: f003 0310 and.w r3, r3, #16 + 8002e82: 2b00 cmp r3, #0 + 8002e84: d010 beq.n 8002ea8 + { + /* Check the parameters */ + assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + 8002e86: 4ba9 ldr r3, [pc, #676] ; (800312c ) + 8002e88: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8002e8c: 4aa7 ldr r2, [pc, #668] ; (800312c ) + 8002e8e: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 8002e92: f8c2 308c str.w r3, [r2, #140] ; 0x8c + 8002e96: 4ba5 ldr r3, [pc, #660] ; (800312c ) + 8002e98: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c + 8002e9c: 687b ldr r3, [r7, #4] + 8002e9e: 6b9b ldr r3, [r3, #56] ; 0x38 + 8002ea0: 49a2 ldr r1, [pc, #648] ; (800312c ) + 8002ea2: 4313 orrs r3, r2 + 8002ea4: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } + + /*-------------------------------------- I2C1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 8002ea8: 687b ldr r3, [r7, #4] + 8002eaa: 681b ldr r3, [r3, #0] + 8002eac: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8002eb0: 2b00 cmp r3, #0 + 8002eb2: d00a beq.n 8002eca + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 8002eb4: 4b9d ldr r3, [pc, #628] ; (800312c ) + 8002eb6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002eba: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 8002ebe: 687b ldr r3, [r7, #4] + 8002ec0: 6e5b ldr r3, [r3, #100] ; 0x64 + 8002ec2: 499a ldr r1, [pc, #616] ; (800312c ) + 8002ec4: 4313 orrs r3, r2 + 8002ec6: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- I2C2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + 8002eca: 687b ldr r3, [r7, #4] + 8002ecc: 681b ldr r3, [r3, #0] + 8002ece: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 8002ed2: 2b00 cmp r3, #0 + 8002ed4: d00a beq.n 8002eec + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + 8002ed6: 4b95 ldr r3, [pc, #596] ; (800312c ) + 8002ed8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002edc: f423 2240 bic.w r2, r3, #786432 ; 0xc0000 + 8002ee0: 687b ldr r3, [r7, #4] + 8002ee2: 6e9b ldr r3, [r3, #104] ; 0x68 + 8002ee4: 4991 ldr r1, [pc, #580] ; (800312c ) + 8002ee6: 4313 orrs r3, r2 + 8002ee8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- I2C3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + 8002eec: 687b ldr r3, [r7, #4] + 8002eee: 681b ldr r3, [r3, #0] + 8002ef0: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8002ef4: 2b00 cmp r3, #0 + 8002ef6: d00a beq.n 8002f0e + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + 8002ef8: 4b8c ldr r3, [pc, #560] ; (800312c ) + 8002efa: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002efe: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 + 8002f02: 687b ldr r3, [r7, #4] + 8002f04: 6edb ldr r3, [r3, #108] ; 0x6c + 8002f06: 4989 ldr r1, [pc, #548] ; (800312c ) + 8002f08: 4313 orrs r3, r2 + 8002f0a: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- I2C4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) + 8002f0e: 687b ldr r3, [r7, #4] + 8002f10: 681b ldr r3, [r3, #0] + 8002f12: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002f16: 2b00 cmp r3, #0 + 8002f18: d00a beq.n 8002f30 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); + + /* Configure the I2C4 clock source */ + __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); + 8002f1a: 4b84 ldr r3, [pc, #528] ; (800312c ) + 8002f1c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002f20: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 + 8002f24: 687b ldr r3, [r7, #4] + 8002f26: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002f28: 4980 ldr r1, [pc, #512] ; (800312c ) + 8002f2a: 4313 orrs r3, r2 + 8002f2c: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 8002f30: 687b ldr r3, [r7, #4] + 8002f32: 681b ldr r3, [r3, #0] + 8002f34: f003 0340 and.w r3, r3, #64 ; 0x40 + 8002f38: 2b00 cmp r3, #0 + 8002f3a: d00a beq.n 8002f52 + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 8002f3c: 4b7b ldr r3, [pc, #492] ; (800312c ) + 8002f3e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002f42: f023 0203 bic.w r2, r3, #3 + 8002f46: 687b ldr r3, [r7, #4] + 8002f48: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002f4a: 4978 ldr r1, [pc, #480] ; (800312c ) + 8002f4c: 4313 orrs r3, r2 + 8002f4e: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 8002f52: 687b ldr r3, [r7, #4] + 8002f54: 681b ldr r3, [r3, #0] + 8002f56: f003 0380 and.w r3, r3, #128 ; 0x80 + 8002f5a: 2b00 cmp r3, #0 + 8002f5c: d00a beq.n 8002f74 + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 8002f5e: 4b73 ldr r3, [pc, #460] ; (800312c ) + 8002f60: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002f64: f023 020c bic.w r2, r3, #12 + 8002f68: 687b ldr r3, [r7, #4] + 8002f6a: 6c9b ldr r3, [r3, #72] ; 0x48 + 8002f6c: 496f ldr r1, [pc, #444] ; (800312c ) + 8002f6e: 4313 orrs r3, r2 + 8002f70: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + 8002f74: 687b ldr r3, [r7, #4] + 8002f76: 681b ldr r3, [r3, #0] + 8002f78: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002f7c: 2b00 cmp r3, #0 + 8002f7e: d00a beq.n 8002f96 + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + 8002f80: 4b6a ldr r3, [pc, #424] ; (800312c ) + 8002f82: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002f86: f023 0230 bic.w r2, r3, #48 ; 0x30 + 8002f8a: 687b ldr r3, [r7, #4] + 8002f8c: 6cdb ldr r3, [r3, #76] ; 0x4c + 8002f8e: 4967 ldr r1, [pc, #412] ; (800312c ) + 8002f90: 4313 orrs r3, r2 + 8002f92: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + 8002f96: 687b ldr r3, [r7, #4] + 8002f98: 681b ldr r3, [r3, #0] + 8002f9a: f403 7300 and.w r3, r3, #512 ; 0x200 + 8002f9e: 2b00 cmp r3, #0 + 8002fa0: d00a beq.n 8002fb8 + { + /* Check the parameters */ + assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); + + /* Configure the UART4 clock source */ + __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); + 8002fa2: 4b62 ldr r3, [pc, #392] ; (800312c ) + 8002fa4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002fa8: f023 02c0 bic.w r2, r3, #192 ; 0xc0 + 8002fac: 687b ldr r3, [r7, #4] + 8002fae: 6d1b ldr r3, [r3, #80] ; 0x50 + 8002fb0: 495e ldr r1, [pc, #376] ; (800312c ) + 8002fb2: 4313 orrs r3, r2 + 8002fb4: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART5 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + 8002fb8: 687b ldr r3, [r7, #4] + 8002fba: 681b ldr r3, [r3, #0] + 8002fbc: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8002fc0: 2b00 cmp r3, #0 + 8002fc2: d00a beq.n 8002fda + { + /* Check the parameters */ + assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); + + /* Configure the UART5 clock source */ + __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); + 8002fc4: 4b59 ldr r3, [pc, #356] ; (800312c ) + 8002fc6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002fca: f423 7240 bic.w r2, r3, #768 ; 0x300 + 8002fce: 687b ldr r3, [r7, #4] + 8002fd0: 6d5b ldr r3, [r3, #84] ; 0x54 + 8002fd2: 4956 ldr r1, [pc, #344] ; (800312c ) + 8002fd4: 4313 orrs r3, r2 + 8002fd6: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART6 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) + 8002fda: 687b ldr r3, [r7, #4] + 8002fdc: 681b ldr r3, [r3, #0] + 8002fde: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8002fe2: 2b00 cmp r3, #0 + 8002fe4: d00a beq.n 8002ffc + { + /* Check the parameters */ + assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); + + /* Configure the USART6 clock source */ + __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); + 8002fe6: 4b51 ldr r3, [pc, #324] ; (800312c ) + 8002fe8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002fec: f423 6240 bic.w r2, r3, #3072 ; 0xc00 + 8002ff0: 687b ldr r3, [r7, #4] + 8002ff2: 6d9b ldr r3, [r3, #88] ; 0x58 + 8002ff4: 494d ldr r1, [pc, #308] ; (800312c ) + 8002ff6: 4313 orrs r3, r2 + 8002ff8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART7 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) + 8002ffc: 687b ldr r3, [r7, #4] + 8002ffe: 681b ldr r3, [r3, #0] + 8003000: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8003004: 2b00 cmp r3, #0 + 8003006: d00a beq.n 800301e + { + /* Check the parameters */ + assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); + + /* Configure the UART7 clock source */ + __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); + 8003008: 4b48 ldr r3, [pc, #288] ; (800312c ) + 800300a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800300e: f423 5240 bic.w r2, r3, #12288 ; 0x3000 + 8003012: 687b ldr r3, [r7, #4] + 8003014: 6ddb ldr r3, [r3, #92] ; 0x5c + 8003016: 4945 ldr r1, [pc, #276] ; (800312c ) + 8003018: 4313 orrs r3, r2 + 800301a: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART8 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) + 800301e: 687b ldr r3, [r7, #4] + 8003020: 681b ldr r3, [r3, #0] + 8003022: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8003026: 2b00 cmp r3, #0 + 8003028: d00a beq.n 8003040 + { + /* Check the parameters */ + assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); + + /* Configure the UART8 clock source */ + __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); + 800302a: 4b40 ldr r3, [pc, #256] ; (800312c ) + 800302c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003030: f423 4240 bic.w r2, r3, #49152 ; 0xc000 + 8003034: 687b ldr r3, [r7, #4] + 8003036: 6e1b ldr r3, [r3, #96] ; 0x60 + 8003038: 493c ldr r1, [pc, #240] ; (800312c ) + 800303a: 4313 orrs r3, r2 + 800303c: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*--------------------------------------- CEC Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + 8003040: 687b ldr r3, [r7, #4] + 8003042: 681b ldr r3, [r3, #0] + 8003044: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8003048: 2b00 cmp r3, #0 + 800304a: d00a beq.n 8003062 + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + 800304c: 4b37 ldr r3, [pc, #220] ; (800312c ) + 800304e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003052: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 + 8003056: 687b ldr r3, [r7, #4] + 8003058: 6f9b ldr r3, [r3, #120] ; 0x78 + 800305a: 4934 ldr r1, [pc, #208] ; (800312c ) + 800305c: 4313 orrs r3, r2 + 800305e: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- CK48 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + 8003062: 687b ldr r3, [r7, #4] + 8003064: 681b ldr r3, [r3, #0] + 8003066: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 800306a: 2b00 cmp r3, #0 + 800306c: d011 beq.n 8003092 + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + 800306e: 4b2f ldr r3, [pc, #188] ; (800312c ) + 8003070: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003074: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000 + 8003078: 687b ldr r3, [r7, #4] + 800307a: 6fdb ldr r3, [r3, #124] ; 0x7c + 800307c: 492b ldr r1, [pc, #172] ; (800312c ) + 800307e: 4313 orrs r3, r2 + 8003080: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + + /* Enable the PLLSAI when it's used as clock source for CK48 */ + if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) + 8003084: 687b ldr r3, [r7, #4] + 8003086: 6fdb ldr r3, [r3, #124] ; 0x7c + 8003088: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 + 800308c: d101 bne.n 8003092 + { + pllsaiused = 1; + 800308e: 2301 movs r3, #1 + 8003090: 61bb str r3, [r7, #24] + } + } + + /*-------------------------------------- LTDC Configuration -----------------------------------*/ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + 8003092: 687b ldr r3, [r7, #4] + 8003094: 681b ldr r3, [r3, #0] + 8003096: f003 0308 and.w r3, r3, #8 + 800309a: 2b00 cmp r3, #0 + 800309c: d001 beq.n 80030a2 + { + pllsaiused = 1; + 800309e: 2301 movs r3, #1 + 80030a0: 61bb str r3, [r7, #24] + } +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + 80030a2: 687b ldr r3, [r7, #4] + 80030a4: 681b ldr r3, [r3, #0] + 80030a6: f403 2380 and.w r3, r3, #262144 ; 0x40000 + 80030aa: 2b00 cmp r3, #0 + 80030ac: d00a beq.n 80030c4 + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LTPIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + 80030ae: 4b1f ldr r3, [pc, #124] ; (800312c ) + 80030b0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80030b4: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000 + 80030b8: 687b ldr r3, [r7, #4] + 80030ba: 6f5b ldr r3, [r3, #116] ; 0x74 + 80030bc: 491b ldr r1, [pc, #108] ; (800312c ) + 80030be: 4313 orrs r3, r2 + 80030c0: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) + 80030c4: 687b ldr r3, [r7, #4] + 80030c6: 681b ldr r3, [r3, #0] + 80030c8: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 80030cc: 2b00 cmp r3, #0 + 80030ce: d00b beq.n 80030e8 + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); + + /* Configure the SDMMC1 clock source */ + __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); + 80030d0: 4b16 ldr r3, [pc, #88] ; (800312c ) + 80030d2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80030d6: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000 + 80030da: 687b ldr r3, [r7, #4] + 80030dc: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 80030e0: 4912 ldr r1, [pc, #72] ; (800312c ) + 80030e2: 4313 orrs r3, r2 + 80030e4: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) + 80030e8: 687b ldr r3, [r7, #4] + 80030ea: 681b ldr r3, [r3, #0] + 80030ec: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 80030f0: 2b00 cmp r3, #0 + 80030f2: d00b beq.n 800310c + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); + + /* Configure the SDMMC2 clock source */ + __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); + 80030f4: 4b0d ldr r3, [pc, #52] ; (800312c ) + 80030f6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80030fa: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000 + 80030fe: 687b ldr r3, [r7, #4] + 8003100: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8003104: 4909 ldr r1, [pc, #36] ; (800312c ) + 8003106: 4313 orrs r3, r2 + 8003108: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*------------------------------------- DFSDM1 Configuration -------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) + 800310c: 687b ldr r3, [r7, #4] + 800310e: 681b ldr r3, [r3, #0] + 8003110: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 8003114: 2b00 cmp r3, #0 + 8003116: d00f beq.n 8003138 + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); + + /* Configure the DFSDM1 interface clock source */ + __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); + 8003118: 4b04 ldr r3, [pc, #16] ; (800312c ) + 800311a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 800311e: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000 + 8003122: 687b ldr r3, [r7, #4] + 8003124: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8003128: e002 b.n 8003130 + 800312a: bf00 nop + 800312c: 40023800 .word 0x40023800 + 8003130: 4985 ldr r1, [pc, #532] ; (8003348 ) + 8003132: 4313 orrs r3, r2 + 8003134: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } + + /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) + 8003138: 687b ldr r3, [r7, #4] + 800313a: 681b ldr r3, [r3, #0] + 800313c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8003140: 2b00 cmp r3, #0 + 8003142: d00b beq.n 800315c + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); + + /* Configure the DFSDM interface clock source */ + __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); + 8003144: 4b80 ldr r3, [pc, #512] ; (8003348 ) + 8003146: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 800314a: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 + 800314e: 687b ldr r3, [r7, #4] + 8003150: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8003154: 497c ldr r1, [pc, #496] ; (8003348 ) + 8003156: 4313 orrs r3, r2 + 8003158: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + + /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ + /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ + if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) + 800315c: 69fb ldr r3, [r7, #28] + 800315e: 2b01 cmp r3, #1 + 8003160: d005 beq.n 800316e + 8003162: 687b ldr r3, [r7, #4] + 8003164: 681b ldr r3, [r3, #0] + 8003166: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 + 800316a: f040 80d6 bne.w 800331a + { + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + 800316e: 4b76 ldr r3, [pc, #472] ; (8003348 ) + 8003170: 681b ldr r3, [r3, #0] + 8003172: 4a75 ldr r2, [pc, #468] ; (8003348 ) + 8003174: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 + 8003178: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800317a: f7fe fe25 bl 8001dc8 + 800317e: 6178 str r0, [r7, #20] + + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + 8003180: e008 b.n 8003194 + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + 8003182: f7fe fe21 bl 8001dc8 + 8003186: 4602 mov r2, r0 + 8003188: 697b ldr r3, [r7, #20] + 800318a: 1ad3 subs r3, r2, r3 + 800318c: 2b64 cmp r3, #100 ; 0x64 + 800318e: d901 bls.n 8003194 + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 8003190: 2303 movs r3, #3 + 8003192: e194 b.n 80034be + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + 8003194: 4b6c ldr r3, [pc, #432] ; (8003348 ) + 8003196: 681b ldr r3, [r3, #0] + 8003198: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 800319c: 2b00 cmp r3, #0 + 800319e: d1f0 bne.n 8003182 + + /* check for common PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) + 80031a0: 687b ldr r3, [r7, #4] + 80031a2: 681b ldr r3, [r3, #0] + 80031a4: f003 0301 and.w r3, r3, #1 + 80031a8: 2b00 cmp r3, #0 + 80031aa: d021 beq.n 80031f0 + 80031ac: 687b ldr r3, [r7, #4] + 80031ae: 6b5b ldr r3, [r3, #52] ; 0x34 + 80031b0: 2b00 cmp r3, #0 + 80031b2: d11d bne.n 80031f0 + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + 80031b4: 4b64 ldr r3, [pc, #400] ; (8003348 ) + 80031b6: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 80031ba: 0c1b lsrs r3, r3, #16 + 80031bc: f003 0303 and.w r3, r3, #3 + 80031c0: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + 80031c2: 4b61 ldr r3, [pc, #388] ; (8003348 ) + 80031c4: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 80031c8: 0e1b lsrs r3, r3, #24 + 80031ca: f003 030f and.w r3, r3, #15 + 80031ce: 60fb str r3, [r7, #12] + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR); + 80031d0: 687b ldr r3, [r7, #4] + 80031d2: 685b ldr r3, [r3, #4] + 80031d4: 019a lsls r2, r3, #6 + 80031d6: 693b ldr r3, [r7, #16] + 80031d8: 041b lsls r3, r3, #16 + 80031da: 431a orrs r2, r3 + 80031dc: 68fb ldr r3, [r7, #12] + 80031de: 061b lsls r3, r3, #24 + 80031e0: 431a orrs r2, r3 + 80031e2: 687b ldr r3, [r7, #4] + 80031e4: 689b ldr r3, [r3, #8] + 80031e6: 071b lsls r3, r3, #28 + 80031e8: 4957 ldr r1, [pc, #348] ; (8003348 ) + 80031ea: 4313 orrs r3, r2 + 80031ec: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + } + + /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + 80031f0: 687b ldr r3, [r7, #4] + 80031f2: 681b ldr r3, [r3, #0] + 80031f4: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 80031f8: 2b00 cmp r3, #0 + 80031fa: d004 beq.n 8003206 + 80031fc: 687b ldr r3, [r7, #4] + 80031fe: 6bdb ldr r3, [r3, #60] ; 0x3c + 8003200: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 8003204: d00a beq.n 800321c + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + 8003206: 687b ldr r3, [r7, #4] + 8003208: 681b ldr r3, [r3, #0] + 800320a: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + 800320e: 2b00 cmp r3, #0 + 8003210: d02e beq.n 8003270 + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + 8003212: 687b ldr r3, [r7, #4] + 8003214: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003216: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 800321a: d129 bne.n 8003270 + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + /* Check for PLLI2S/DIVQ parameters */ + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + 800321c: 4b4a ldr r3, [pc, #296] ; (8003348 ) + 800321e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8003222: 0c1b lsrs r3, r3, #16 + 8003224: f003 0303 and.w r3, r3, #3 + 8003228: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + 800322a: 4b47 ldr r3, [pc, #284] ; (8003348 ) + 800322c: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8003230: 0f1b lsrs r3, r3, #28 + 8003232: f003 0307 and.w r3, r3, #7 + 8003236: 60fb str r3, [r7, #12] + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); + 8003238: 687b ldr r3, [r7, #4] + 800323a: 685b ldr r3, [r3, #4] + 800323c: 019a lsls r2, r3, #6 + 800323e: 693b ldr r3, [r7, #16] + 8003240: 041b lsls r3, r3, #16 + 8003242: 431a orrs r2, r3 + 8003244: 687b ldr r3, [r7, #4] + 8003246: 68db ldr r3, [r3, #12] + 8003248: 061b lsls r3, r3, #24 + 800324a: 431a orrs r2, r3 + 800324c: 68fb ldr r3, [r7, #12] + 800324e: 071b lsls r3, r3, #28 + 8003250: 493d ldr r1, [pc, #244] ; (8003348 ) + 8003252: 4313 orrs r3, r2 + 8003254: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + 8003258: 4b3b ldr r3, [pc, #236] ; (8003348 ) + 800325a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 800325e: f023 021f bic.w r2, r3, #31 + 8003262: 687b ldr r3, [r7, #4] + 8003264: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003266: 3b01 subs r3, #1 + 8003268: 4937 ldr r1, [pc, #220] ; (8003348 ) + 800326a: 4313 orrs r3, r2 + 800326c: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } + + /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + 8003270: 687b ldr r3, [r7, #4] + 8003272: 681b ldr r3, [r3, #0] + 8003274: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 8003278: 2b00 cmp r3, #0 + 800327a: d01d beq.n 80032b8 + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + 800327c: 4b32 ldr r3, [pc, #200] ; (8003348 ) + 800327e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8003282: 0e1b lsrs r3, r3, #24 + 8003284: f003 030f and.w r3, r3, #15 + 8003288: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + 800328a: 4b2f ldr r3, [pc, #188] ; (8003348 ) + 800328c: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8003290: 0f1b lsrs r3, r3, #28 + 8003292: f003 0307 and.w r3, r3, #7 + 8003296: 60fb str r3, [r7, #12] + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1); + 8003298: 687b ldr r3, [r7, #4] + 800329a: 685b ldr r3, [r3, #4] + 800329c: 019a lsls r2, r3, #6 + 800329e: 687b ldr r3, [r7, #4] + 80032a0: 691b ldr r3, [r3, #16] + 80032a2: 041b lsls r3, r3, #16 + 80032a4: 431a orrs r2, r3 + 80032a6: 693b ldr r3, [r7, #16] + 80032a8: 061b lsls r3, r3, #24 + 80032aa: 431a orrs r2, r3 + 80032ac: 68fb ldr r3, [r7, #12] + 80032ae: 071b lsls r3, r3, #28 + 80032b0: 4925 ldr r1, [pc, #148] ; (8003348 ) + 80032b2: 4313 orrs r3, r2 + 80032b4: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + 80032b8: 687b ldr r3, [r7, #4] + 80032ba: 681b ldr r3, [r3, #0] + 80032bc: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 80032c0: 2b00 cmp r3, #0 + 80032c2: d011 beq.n 80032e8 + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ + /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + 80032c4: 687b ldr r3, [r7, #4] + 80032c6: 685b ldr r3, [r3, #4] + 80032c8: 019a lsls r2, r3, #6 + 80032ca: 687b ldr r3, [r7, #4] + 80032cc: 691b ldr r3, [r3, #16] + 80032ce: 041b lsls r3, r3, #16 + 80032d0: 431a orrs r2, r3 + 80032d2: 687b ldr r3, [r7, #4] + 80032d4: 68db ldr r3, [r3, #12] + 80032d6: 061b lsls r3, r3, #24 + 80032d8: 431a orrs r2, r3 + 80032da: 687b ldr r3, [r7, #4] + 80032dc: 689b ldr r3, [r3, #8] + 80032de: 071b lsls r3, r3, #28 + 80032e0: 4919 ldr r1, [pc, #100] ; (8003348 ) + 80032e2: 4313 orrs r3, r2 + 80032e4: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + 80032e8: 4b17 ldr r3, [pc, #92] ; (8003348 ) + 80032ea: 681b ldr r3, [r3, #0] + 80032ec: 4a16 ldr r2, [pc, #88] ; (8003348 ) + 80032ee: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 + 80032f2: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80032f4: f7fe fd68 bl 8001dc8 + 80032f8: 6178 str r0, [r7, #20] + + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 80032fa: e008 b.n 800330e + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + 80032fc: f7fe fd64 bl 8001dc8 + 8003300: 4602 mov r2, r0 + 8003302: 697b ldr r3, [r7, #20] + 8003304: 1ad3 subs r3, r2, r3 + 8003306: 2b64 cmp r3, #100 ; 0x64 + 8003308: d901 bls.n 800330e + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 800330a: 2303 movs r3, #3 + 800330c: e0d7 b.n 80034be + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 800330e: 4b0e ldr r3, [pc, #56] ; (8003348 ) + 8003310: 681b ldr r3, [r3, #0] + 8003312: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 8003316: 2b00 cmp r3, #0 + 8003318: d0f0 beq.n 80032fc + } + } + + /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ + /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ + if(pllsaiused == 1) + 800331a: 69bb ldr r3, [r7, #24] + 800331c: 2b01 cmp r3, #1 + 800331e: f040 80cd bne.w 80034bc + { + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + 8003322: 4b09 ldr r3, [pc, #36] ; (8003348 ) + 8003324: 681b ldr r3, [r3, #0] + 8003326: 4a08 ldr r2, [pc, #32] ; (8003348 ) + 8003328: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 800332c: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800332e: f7fe fd4b bl 8001dc8 + 8003332: 6178 str r0, [r7, #20] + + /* Wait till PLLSAI is disabled */ + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + 8003334: e00a b.n 800334c + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + 8003336: f7fe fd47 bl 8001dc8 + 800333a: 4602 mov r2, r0 + 800333c: 697b ldr r3, [r7, #20] + 800333e: 1ad3 subs r3, r2, r3 + 8003340: 2b64 cmp r3, #100 ; 0x64 + 8003342: d903 bls.n 800334c + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 8003344: 2303 movs r3, #3 + 8003346: e0ba b.n 80034be + 8003348: 40023800 .word 0x40023800 + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + 800334c: 4b5e ldr r3, [pc, #376] ; (80034c8 ) + 800334e: 681b ldr r3, [r3, #0] + 8003350: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 8003354: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 8003358: d0ed beq.n 8003336 + + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ + 800335a: 687b ldr r3, [r7, #4] + 800335c: 681b ldr r3, [r3, #0] + 800335e: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 8003362: 2b00 cmp r3, #0 + 8003364: d003 beq.n 800336e + 8003366: 687b ldr r3, [r7, #4] + 8003368: 6bdb ldr r3, [r3, #60] ; 0x3c + 800336a: 2b00 cmp r3, #0 + 800336c: d009 beq.n 8003382 + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + 800336e: 687b ldr r3, [r7, #4] + 8003370: 681b ldr r3, [r3, #0] + 8003372: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ + 8003376: 2b00 cmp r3, #0 + 8003378: d02e beq.n 80033d8 + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + 800337a: 687b ldr r3, [r7, #4] + 800337c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800337e: 2b00 cmp r3, #0 + 8003380: d12a bne.n 80033d8 + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + /* check for PLLSAI/DIVQ Parameter */ + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + 8003382: 4b51 ldr r3, [pc, #324] ; (80034c8 ) + 8003384: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8003388: 0c1b lsrs r3, r3, #16 + 800338a: f003 0303 and.w r3, r3, #3 + 800338e: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + 8003390: 4b4d ldr r3, [pc, #308] ; (80034c8 ) + 8003392: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8003396: 0f1b lsrs r3, r3, #28 + 8003398: f003 0307 and.w r3, r3, #7 + 800339c: 60fb str r3, [r7, #12] + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); + 800339e: 687b ldr r3, [r7, #4] + 80033a0: 695b ldr r3, [r3, #20] + 80033a2: 019a lsls r2, r3, #6 + 80033a4: 693b ldr r3, [r7, #16] + 80033a6: 041b lsls r3, r3, #16 + 80033a8: 431a orrs r2, r3 + 80033aa: 687b ldr r3, [r7, #4] + 80033ac: 699b ldr r3, [r3, #24] + 80033ae: 061b lsls r3, r3, #24 + 80033b0: 431a orrs r2, r3 + 80033b2: 68fb ldr r3, [r7, #12] + 80033b4: 071b lsls r3, r3, #28 + 80033b6: 4944 ldr r1, [pc, #272] ; (80034c8 ) + 80033b8: 4313 orrs r3, r2 + 80033ba: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + 80033be: 4b42 ldr r3, [pc, #264] ; (80034c8 ) + 80033c0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 80033c4: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00 + 80033c8: 687b ldr r3, [r7, #4] + 80033ca: 6a9b ldr r3, [r3, #40] ; 0x28 + 80033cc: 3b01 subs r3, #1 + 80033ce: 021b lsls r3, r3, #8 + 80033d0: 493d ldr r1, [pc, #244] ; (80034c8 ) + 80033d2: 4313 orrs r3, r2 + 80033d4: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } + + /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ + /* In Case of PLLI2S is selected as source clock for CK48 */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) + 80033d8: 687b ldr r3, [r7, #4] + 80033da: 681b ldr r3, [r3, #0] + 80033dc: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 80033e0: 2b00 cmp r3, #0 + 80033e2: d022 beq.n 800342a + 80033e4: 687b ldr r3, [r7, #4] + 80033e6: 6fdb ldr r3, [r3, #124] ; 0x7c + 80033e8: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 + 80033ec: d11d bne.n 800342a + { + /* check for Parameters */ + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + 80033ee: 4b36 ldr r3, [pc, #216] ; (80034c8 ) + 80033f0: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 80033f4: 0e1b lsrs r3, r3, #24 + 80033f6: f003 030f and.w r3, r3, #15 + 80033fa: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + 80033fc: 4b32 ldr r3, [pc, #200] ; (80034c8 ) + 80033fe: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8003402: 0f1b lsrs r3, r3, #28 + 8003404: f003 0307 and.w r3, r3, #7 + 8003408: 60fb str r3, [r7, #12] + + /* Configure the PLLSAI division factors */ + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ + /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); + 800340a: 687b ldr r3, [r7, #4] + 800340c: 695b ldr r3, [r3, #20] + 800340e: 019a lsls r2, r3, #6 + 8003410: 687b ldr r3, [r7, #4] + 8003412: 6a1b ldr r3, [r3, #32] + 8003414: 041b lsls r3, r3, #16 + 8003416: 431a orrs r2, r3 + 8003418: 693b ldr r3, [r7, #16] + 800341a: 061b lsls r3, r3, #24 + 800341c: 431a orrs r2, r3 + 800341e: 68fb ldr r3, [r7, #12] + 8003420: 071b lsls r3, r3, #28 + 8003422: 4929 ldr r1, [pc, #164] ; (80034c8 ) + 8003424: 4313 orrs r3, r2 + 8003426: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + } + +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + /*---------------------------- LTDC configuration -------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) + 800342a: 687b ldr r3, [r7, #4] + 800342c: 681b ldr r3, [r3, #0] + 800342e: f003 0308 and.w r3, r3, #8 + 8003432: 2b00 cmp r3, #0 + 8003434: d028 beq.n 8003488 + { + assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); + assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); + + /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + 8003436: 4b24 ldr r3, [pc, #144] ; (80034c8 ) + 8003438: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800343c: 0e1b lsrs r3, r3, #24 + 800343e: f003 030f and.w r3, r3, #15 + 8003442: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + 8003444: 4b20 ldr r3, [pc, #128] ; (80034c8 ) + 8003446: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800344a: 0c1b lsrs r3, r3, #16 + 800344c: f003 0303 and.w r3, r3, #3 + 8003450: 60fb str r3, [r7, #12] + + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR); + 8003452: 687b ldr r3, [r7, #4] + 8003454: 695b ldr r3, [r3, #20] + 8003456: 019a lsls r2, r3, #6 + 8003458: 68fb ldr r3, [r7, #12] + 800345a: 041b lsls r3, r3, #16 + 800345c: 431a orrs r2, r3 + 800345e: 693b ldr r3, [r7, #16] + 8003460: 061b lsls r3, r3, #24 + 8003462: 431a orrs r2, r3 + 8003464: 687b ldr r3, [r7, #4] + 8003466: 69db ldr r3, [r3, #28] + 8003468: 071b lsls r3, r3, #28 + 800346a: 4917 ldr r1, [pc, #92] ; (80034c8 ) + 800346c: 4313 orrs r3, r2 + 800346e: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); + 8003472: 4b15 ldr r3, [pc, #84] ; (80034c8 ) + 8003474: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8003478: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 800347c: 687b ldr r3, [r7, #4] + 800347e: 6adb ldr r3, [r3, #44] ; 0x2c + 8003480: 4911 ldr r1, [pc, #68] ; (80034c8 ) + 8003482: 4313 orrs r3, r2 + 8003484: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + 8003488: 4b0f ldr r3, [pc, #60] ; (80034c8 ) + 800348a: 681b ldr r3, [r3, #0] + 800348c: 4a0e ldr r2, [pc, #56] ; (80034c8 ) + 800348e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8003492: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003494: f7fe fc98 bl 8001dc8 + 8003498: 6178 str r0, [r7, #20] + + /* Wait till PLLSAI is ready */ + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + 800349a: e008 b.n 80034ae + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + 800349c: f7fe fc94 bl 8001dc8 + 80034a0: 4602 mov r2, r0 + 80034a2: 697b ldr r3, [r7, #20] + 80034a4: 1ad3 subs r3, r2, r3 + 80034a6: 2b64 cmp r3, #100 ; 0x64 + 80034a8: d901 bls.n 80034ae + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 80034aa: 2303 movs r3, #3 + 80034ac: e007 b.n 80034be + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + 80034ae: 4b06 ldr r3, [pc, #24] ; (80034c8 ) + 80034b0: 681b ldr r3, [r3, #0] + 80034b2: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 80034b6: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 80034ba: d1ef bne.n 800349c + } + } + } + return HAL_OK; + 80034bc: 2300 movs r3, #0 +} + 80034be: 4618 mov r0, r3 + 80034c0: 3720 adds r7, #32 + 80034c2: 46bd mov sp, r7 + 80034c4: bd80 pop {r7, pc} + 80034c6: bf00 nop + 80034c8: 40023800 .word 0x40023800 + +080034cc : + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + 80034cc: b580 push {r7, lr} + 80034ce: b082 sub sp, #8 + 80034d0: af00 add r7, sp, #0 + 80034d2: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 80034d4: 687b ldr r3, [r7, #4] + 80034d6: 2b00 cmp r3, #0 + 80034d8: d101 bne.n 80034de + { + return HAL_ERROR; + 80034da: 2301 movs r3, #1 + 80034dc: e01d b.n 800351a + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 80034de: 687b ldr r3, [r7, #4] + 80034e0: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 80034e4: b2db uxtb r3, r3 + 80034e6: 2b00 cmp r3, #0 + 80034e8: d106 bne.n 80034f8 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 80034ea: 687b ldr r3, [r7, #4] + 80034ec: 2200 movs r2, #0 + 80034ee: f883 203c strb.w r2, [r3, #60] ; 0x3c + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); + 80034f2: 6878 ldr r0, [r7, #4] + 80034f4: f7fe faa0 bl 8001a38 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 80034f8: 687b ldr r3, [r7, #4] + 80034fa: 2202 movs r2, #2 + 80034fc: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8003500: 687b ldr r3, [r7, #4] + 8003502: 681a ldr r2, [r3, #0] + 8003504: 687b ldr r3, [r7, #4] + 8003506: 3304 adds r3, #4 + 8003508: 4619 mov r1, r3 + 800350a: 4610 mov r0, r2 + 800350c: f000 fc90 bl 8003e30 + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 8003510: 687b ldr r3, [r7, #4] + 8003512: 2201 movs r2, #1 + 8003514: f883 203d strb.w r2, [r3, #61] ; 0x3d + + return HAL_OK; + 8003518: 2300 movs r3, #0 +} + 800351a: 4618 mov r0, r3 + 800351c: 3708 adds r7, #8 + 800351e: 46bd mov sp, r7 + 8003520: bd80 pop {r7, pc} + ... + +08003524 : + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + 8003524: b480 push {r7} + 8003526: b085 sub sp, #20 + 8003528: af00 add r7, sp, #0 + 800352a: 6078 str r0, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + 800352c: 687b ldr r3, [r7, #4] + 800352e: 681b ldr r3, [r3, #0] + 8003530: 68da ldr r2, [r3, #12] + 8003532: 687b ldr r3, [r7, #4] + 8003534: 681b ldr r3, [r3, #0] + 8003536: f042 0201 orr.w r2, r2, #1 + 800353a: 60da str r2, [r3, #12] + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 800353c: 687b ldr r3, [r7, #4] + 800353e: 681b ldr r3, [r3, #0] + 8003540: 689a ldr r2, [r3, #8] + 8003542: 4b0c ldr r3, [pc, #48] ; (8003574 ) + 8003544: 4013 ands r3, r2 + 8003546: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8003548: 68fb ldr r3, [r7, #12] + 800354a: 2b06 cmp r3, #6 + 800354c: d00b beq.n 8003566 + 800354e: 68fb ldr r3, [r7, #12] + 8003550: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8003554: d007 beq.n 8003566 + { + __HAL_TIM_ENABLE(htim); + 8003556: 687b ldr r3, [r7, #4] + 8003558: 681b ldr r3, [r3, #0] + 800355a: 681a ldr r2, [r3, #0] + 800355c: 687b ldr r3, [r7, #4] + 800355e: 681b ldr r3, [r3, #0] + 8003560: f042 0201 orr.w r2, r2, #1 + 8003564: 601a str r2, [r3, #0] + } + + /* Return function status */ + return HAL_OK; + 8003566: 2300 movs r3, #0 +} + 8003568: 4618 mov r0, r3 + 800356a: 3714 adds r7, #20 + 800356c: 46bd mov sp, r7 + 800356e: f85d 7b04 ldr.w r7, [sp], #4 + 8003572: 4770 bx lr + 8003574: 00010007 .word 0x00010007 + +08003578 : + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + 8003578: b580 push {r7, lr} + 800357a: b082 sub sp, #8 + 800357c: af00 add r7, sp, #0 + 800357e: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 8003580: 687b ldr r3, [r7, #4] + 8003582: 2b00 cmp r3, #0 + 8003584: d101 bne.n 800358a + { + return HAL_ERROR; + 8003586: 2301 movs r3, #1 + 8003588: e01d b.n 80035c6 + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 800358a: 687b ldr r3, [r7, #4] + 800358c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 8003590: b2db uxtb r3, r3 + 8003592: 2b00 cmp r3, #0 + 8003594: d106 bne.n 80035a4 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 8003596: 687b ldr r3, [r7, #4] + 8003598: 2200 movs r2, #0 + 800359a: f883 203c strb.w r2, [r3, #60] ; 0x3c + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); + 800359e: 6878 ldr r0, [r7, #4] + 80035a0: f000 f815 bl 80035ce +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 80035a4: 687b ldr r3, [r7, #4] + 80035a6: 2202 movs r2, #2 + 80035a8: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 80035ac: 687b ldr r3, [r7, #4] + 80035ae: 681a ldr r2, [r3, #0] + 80035b0: 687b ldr r3, [r7, #4] + 80035b2: 3304 adds r3, #4 + 80035b4: 4619 mov r1, r3 + 80035b6: 4610 mov r0, r2 + 80035b8: f000 fc3a bl 8003e30 + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 80035bc: 687b ldr r3, [r7, #4] + 80035be: 2201 movs r2, #1 + 80035c0: f883 203d strb.w r2, [r3, #61] ; 0x3d + + return HAL_OK; + 80035c4: 2300 movs r3, #0 +} + 80035c6: 4618 mov r0, r3 + 80035c8: 3708 adds r7, #8 + 80035ca: 46bd mov sp, r7 + 80035cc: bd80 pop {r7, pc} + +080035ce : + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + 80035ce: b480 push {r7} + 80035d0: b083 sub sp, #12 + 80035d2: af00 add r7, sp, #0 + 80035d4: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + 80035d6: bf00 nop + 80035d8: 370c adds r7, #12 + 80035da: 46bd mov sp, r7 + 80035dc: f85d 7b04 ldr.w r7, [sp], #4 + 80035e0: 4770 bx lr + ... + +080035e4 : + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + 80035e4: b580 push {r7, lr} + 80035e6: b084 sub sp, #16 + 80035e8: af00 add r7, sp, #0 + 80035ea: 6078 str r0, [r7, #4] + 80035ec: 6039 str r1, [r7, #0] + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 80035ee: 687b ldr r3, [r7, #4] + 80035f0: 681b ldr r3, [r3, #0] + 80035f2: 2201 movs r2, #1 + 80035f4: 6839 ldr r1, [r7, #0] + 80035f6: 4618 mov r0, r3 + 80035f8: f000 ffb2 bl 8004560 + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 80035fc: 687b ldr r3, [r7, #4] + 80035fe: 681b ldr r3, [r3, #0] + 8003600: 4a17 ldr r2, [pc, #92] ; (8003660 ) + 8003602: 4293 cmp r3, r2 + 8003604: d004 beq.n 8003610 + 8003606: 687b ldr r3, [r7, #4] + 8003608: 681b ldr r3, [r3, #0] + 800360a: 4a16 ldr r2, [pc, #88] ; (8003664 ) + 800360c: 4293 cmp r3, r2 + 800360e: d101 bne.n 8003614 + 8003610: 2301 movs r3, #1 + 8003612: e000 b.n 8003616 + 8003614: 2300 movs r3, #0 + 8003616: 2b00 cmp r3, #0 + 8003618: d007 beq.n 800362a + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + 800361a: 687b ldr r3, [r7, #4] + 800361c: 681b ldr r3, [r3, #0] + 800361e: 6c5a ldr r2, [r3, #68] ; 0x44 + 8003620: 687b ldr r3, [r7, #4] + 8003622: 681b ldr r3, [r3, #0] + 8003624: f442 4200 orr.w r2, r2, #32768 ; 0x8000 + 8003628: 645a str r2, [r3, #68] ; 0x44 + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 800362a: 687b ldr r3, [r7, #4] + 800362c: 681b ldr r3, [r3, #0] + 800362e: 689a ldr r2, [r3, #8] + 8003630: 4b0d ldr r3, [pc, #52] ; (8003668 ) + 8003632: 4013 ands r3, r2 + 8003634: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8003636: 68fb ldr r3, [r7, #12] + 8003638: 2b06 cmp r3, #6 + 800363a: d00b beq.n 8003654 + 800363c: 68fb ldr r3, [r7, #12] + 800363e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8003642: d007 beq.n 8003654 + { + __HAL_TIM_ENABLE(htim); + 8003644: 687b ldr r3, [r7, #4] + 8003646: 681b ldr r3, [r3, #0] + 8003648: 681a ldr r2, [r3, #0] + 800364a: 687b ldr r3, [r7, #4] + 800364c: 681b ldr r3, [r3, #0] + 800364e: f042 0201 orr.w r2, r2, #1 + 8003652: 601a str r2, [r3, #0] + } + + /* Return function status */ + return HAL_OK; + 8003654: 2300 movs r3, #0 +} + 8003656: 4618 mov r0, r3 + 8003658: 3710 adds r7, #16 + 800365a: 46bd mov sp, r7 + 800365c: bd80 pop {r7, pc} + 800365e: bf00 nop + 8003660: 40010000 .word 0x40010000 + 8003664: 40010400 .word 0x40010400 + 8003668: 00010007 .word 0x00010007 + +0800366c : + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +{ + 800366c: b580 push {r7, lr} + 800366e: b086 sub sp, #24 + 8003670: af00 add r7, sp, #0 + 8003672: 6078 str r0, [r7, #4] + 8003674: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + 8003676: 687b ldr r3, [r7, #4] + 8003678: 2b00 cmp r3, #0 + 800367a: d101 bne.n 8003680 + { + return HAL_ERROR; + 800367c: 2301 movs r3, #1 + 800367e: e07b b.n 8003778 + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + 8003680: 687b ldr r3, [r7, #4] + 8003682: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 8003686: b2db uxtb r3, r3 + 8003688: 2b00 cmp r3, #0 + 800368a: d106 bne.n 800369a + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 800368c: 687b ldr r3, [r7, #4] + 800368e: 2200 movs r2, #0 + 8003690: f883 203c strb.w r2, [r3, #60] ; 0x3c + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); + 8003694: 6878 ldr r0, [r7, #4] + 8003696: f7fe f93f bl 8001918 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 800369a: 687b ldr r3, [r7, #4] + 800369c: 2202 movs r2, #2 + 800369e: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + 80036a2: 687b ldr r3, [r7, #4] + 80036a4: 681b ldr r3, [r3, #0] + 80036a6: 6899 ldr r1, [r3, #8] + 80036a8: 687b ldr r3, [r7, #4] + 80036aa: 681a ldr r2, [r3, #0] + 80036ac: 4b34 ldr r3, [pc, #208] ; (8003780 ) + 80036ae: 400b ands r3, r1 + 80036b0: 6093 str r3, [r2, #8] + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 80036b2: 687b ldr r3, [r7, #4] + 80036b4: 681a ldr r2, [r3, #0] + 80036b6: 687b ldr r3, [r7, #4] + 80036b8: 3304 adds r3, #4 + 80036ba: 4619 mov r1, r3 + 80036bc: 4610 mov r0, r2 + 80036be: f000 fbb7 bl 8003e30 + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 80036c2: 687b ldr r3, [r7, #4] + 80036c4: 681b ldr r3, [r3, #0] + 80036c6: 689b ldr r3, [r3, #8] + 80036c8: 617b str r3, [r7, #20] + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + 80036ca: 687b ldr r3, [r7, #4] + 80036cc: 681b ldr r3, [r3, #0] + 80036ce: 699b ldr r3, [r3, #24] + 80036d0: 613b str r3, [r7, #16] + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + 80036d2: 687b ldr r3, [r7, #4] + 80036d4: 681b ldr r3, [r3, #0] + 80036d6: 6a1b ldr r3, [r3, #32] + 80036d8: 60fb str r3, [r7, #12] + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + 80036da: 683b ldr r3, [r7, #0] + 80036dc: 681b ldr r3, [r3, #0] + 80036de: 697a ldr r2, [r7, #20] + 80036e0: 4313 orrs r3, r2 + 80036e2: 617b str r3, [r7, #20] + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + 80036e4: 693a ldr r2, [r7, #16] + 80036e6: 4b27 ldr r3, [pc, #156] ; (8003784 ) + 80036e8: 4013 ands r3, r2 + 80036ea: 613b str r3, [r7, #16] + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + 80036ec: 683b ldr r3, [r7, #0] + 80036ee: 689a ldr r2, [r3, #8] + 80036f0: 683b ldr r3, [r7, #0] + 80036f2: 699b ldr r3, [r3, #24] + 80036f4: 021b lsls r3, r3, #8 + 80036f6: 4313 orrs r3, r2 + 80036f8: 693a ldr r2, [r7, #16] + 80036fa: 4313 orrs r3, r2 + 80036fc: 613b str r3, [r7, #16] + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + 80036fe: 693a ldr r2, [r7, #16] + 8003700: 4b21 ldr r3, [pc, #132] ; (8003788 ) + 8003702: 4013 ands r3, r2 + 8003704: 613b str r3, [r7, #16] + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + 8003706: 693a ldr r2, [r7, #16] + 8003708: 4b20 ldr r3, [pc, #128] ; (800378c ) + 800370a: 4013 ands r3, r2 + 800370c: 613b str r3, [r7, #16] + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + 800370e: 683b ldr r3, [r7, #0] + 8003710: 68da ldr r2, [r3, #12] + 8003712: 683b ldr r3, [r7, #0] + 8003714: 69db ldr r3, [r3, #28] + 8003716: 021b lsls r3, r3, #8 + 8003718: 4313 orrs r3, r2 + 800371a: 693a ldr r2, [r7, #16] + 800371c: 4313 orrs r3, r2 + 800371e: 613b str r3, [r7, #16] + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + 8003720: 683b ldr r3, [r7, #0] + 8003722: 691b ldr r3, [r3, #16] + 8003724: 011a lsls r2, r3, #4 + 8003726: 683b ldr r3, [r7, #0] + 8003728: 6a1b ldr r3, [r3, #32] + 800372a: 031b lsls r3, r3, #12 + 800372c: 4313 orrs r3, r2 + 800372e: 693a ldr r2, [r7, #16] + 8003730: 4313 orrs r3, r2 + 8003732: 613b str r3, [r7, #16] + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + 8003734: 68fb ldr r3, [r7, #12] + 8003736: f023 0322 bic.w r3, r3, #34 ; 0x22 + 800373a: 60fb str r3, [r7, #12] + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + 800373c: 68fb ldr r3, [r7, #12] + 800373e: f023 0388 bic.w r3, r3, #136 ; 0x88 + 8003742: 60fb str r3, [r7, #12] + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + 8003744: 683b ldr r3, [r7, #0] + 8003746: 685a ldr r2, [r3, #4] + 8003748: 683b ldr r3, [r7, #0] + 800374a: 695b ldr r3, [r3, #20] + 800374c: 011b lsls r3, r3, #4 + 800374e: 4313 orrs r3, r2 + 8003750: 68fa ldr r2, [r7, #12] + 8003752: 4313 orrs r3, r2 + 8003754: 60fb str r3, [r7, #12] + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8003756: 687b ldr r3, [r7, #4] + 8003758: 681b ldr r3, [r3, #0] + 800375a: 697a ldr r2, [r7, #20] + 800375c: 609a str r2, [r3, #8] + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + 800375e: 687b ldr r3, [r7, #4] + 8003760: 681b ldr r3, [r3, #0] + 8003762: 693a ldr r2, [r7, #16] + 8003764: 619a str r2, [r3, #24] + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + 8003766: 687b ldr r3, [r7, #4] + 8003768: 681b ldr r3, [r3, #0] + 800376a: 68fa ldr r2, [r7, #12] + 800376c: 621a str r2, [r3, #32] + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 800376e: 687b ldr r3, [r7, #4] + 8003770: 2201 movs r2, #1 + 8003772: f883 203d strb.w r2, [r3, #61] ; 0x3d + + return HAL_OK; + 8003776: 2300 movs r3, #0 +} + 8003778: 4618 mov r0, r3 + 800377a: 3718 adds r7, #24 + 800377c: 46bd mov sp, r7 + 800377e: bd80 pop {r7, pc} + 8003780: fffebff8 .word 0xfffebff8 + 8003784: fffffcfc .word 0xfffffcfc + 8003788: fffff3f3 .word 0xfffff3f3 + 800378c: ffff0f0f .word 0xffff0f0f + +08003790 : + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + 8003790: b580 push {r7, lr} + 8003792: b082 sub sp, #8 + 8003794: af00 add r7, sp, #0 + 8003796: 6078 str r0, [r7, #4] + 8003798: 6039 str r1, [r7, #0] + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + switch (Channel) + 800379a: 683b ldr r3, [r7, #0] + 800379c: 2b00 cmp r3, #0 + 800379e: d002 beq.n 80037a6 + 80037a0: 2b04 cmp r3, #4 + 80037a2: d008 beq.n 80037b6 + 80037a4: e00f b.n 80037c6 + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 80037a6: 687b ldr r3, [r7, #4] + 80037a8: 681b ldr r3, [r3, #0] + 80037aa: 2201 movs r2, #1 + 80037ac: 2100 movs r1, #0 + 80037ae: 4618 mov r0, r3 + 80037b0: f000 fed6 bl 8004560 + break; + 80037b4: e016 b.n 80037e4 + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 80037b6: 687b ldr r3, [r7, #4] + 80037b8: 681b ldr r3, [r3, #0] + 80037ba: 2201 movs r2, #1 + 80037bc: 2104 movs r1, #4 + 80037be: 4618 mov r0, r3 + 80037c0: f000 fece bl 8004560 + break; + 80037c4: e00e b.n 80037e4 + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 80037c6: 687b ldr r3, [r7, #4] + 80037c8: 681b ldr r3, [r3, #0] + 80037ca: 2201 movs r2, #1 + 80037cc: 2100 movs r1, #0 + 80037ce: 4618 mov r0, r3 + 80037d0: f000 fec6 bl 8004560 + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 80037d4: 687b ldr r3, [r7, #4] + 80037d6: 681b ldr r3, [r3, #0] + 80037d8: 2201 movs r2, #1 + 80037da: 2104 movs r1, #4 + 80037dc: 4618 mov r0, r3 + 80037de: f000 febf bl 8004560 + break; + 80037e2: bf00 nop + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + 80037e4: 687b ldr r3, [r7, #4] + 80037e6: 681b ldr r3, [r3, #0] + 80037e8: 681a ldr r2, [r3, #0] + 80037ea: 687b ldr r3, [r7, #4] + 80037ec: 681b ldr r3, [r3, #0] + 80037ee: f042 0201 orr.w r2, r2, #1 + 80037f2: 601a str r2, [r3, #0] + + /* Return function status */ + return HAL_OK; + 80037f4: 2300 movs r3, #0 +} + 80037f6: 4618 mov r0, r3 + 80037f8: 3708 adds r7, #8 + 80037fa: 46bd mov sp, r7 + 80037fc: bd80 pop {r7, pc} + +080037fe : + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + 80037fe: b580 push {r7, lr} + 8003800: b082 sub sp, #8 + 8003802: af00 add r7, sp, #0 + 8003804: 6078 str r0, [r7, #4] + /* Capture compare 1 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + 8003806: 687b ldr r3, [r7, #4] + 8003808: 681b ldr r3, [r3, #0] + 800380a: 691b ldr r3, [r3, #16] + 800380c: f003 0302 and.w r3, r3, #2 + 8003810: 2b02 cmp r3, #2 + 8003812: d122 bne.n 800385a + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + 8003814: 687b ldr r3, [r7, #4] + 8003816: 681b ldr r3, [r3, #0] + 8003818: 68db ldr r3, [r3, #12] + 800381a: f003 0302 and.w r3, r3, #2 + 800381e: 2b02 cmp r3, #2 + 8003820: d11b bne.n 800385a + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + 8003822: 687b ldr r3, [r7, #4] + 8003824: 681b ldr r3, [r3, #0] + 8003826: f06f 0202 mvn.w r2, #2 + 800382a: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 800382c: 687b ldr r3, [r7, #4] + 800382e: 2201 movs r2, #1 + 8003830: 771a strb r2, [r3, #28] + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + 8003832: 687b ldr r3, [r7, #4] + 8003834: 681b ldr r3, [r3, #0] + 8003836: 699b ldr r3, [r3, #24] + 8003838: f003 0303 and.w r3, r3, #3 + 800383c: 2b00 cmp r3, #0 + 800383e: d003 beq.n 8003848 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8003840: 6878 ldr r0, [r7, #4] + 8003842: f000 fad7 bl 8003df4 + 8003846: e005 b.n 8003854 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8003848: 6878 ldr r0, [r7, #4] + 800384a: f000 fac9 bl 8003de0 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 800384e: 6878 ldr r0, [r7, #4] + 8003850: f000 fada bl 8003e08 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8003854: 687b ldr r3, [r7, #4] + 8003856: 2200 movs r2, #0 + 8003858: 771a strb r2, [r3, #28] + } + } + } + /* Capture compare 2 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + 800385a: 687b ldr r3, [r7, #4] + 800385c: 681b ldr r3, [r3, #0] + 800385e: 691b ldr r3, [r3, #16] + 8003860: f003 0304 and.w r3, r3, #4 + 8003864: 2b04 cmp r3, #4 + 8003866: d122 bne.n 80038ae + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + 8003868: 687b ldr r3, [r7, #4] + 800386a: 681b ldr r3, [r3, #0] + 800386c: 68db ldr r3, [r3, #12] + 800386e: f003 0304 and.w r3, r3, #4 + 8003872: 2b04 cmp r3, #4 + 8003874: d11b bne.n 80038ae + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + 8003876: 687b ldr r3, [r7, #4] + 8003878: 681b ldr r3, [r3, #0] + 800387a: f06f 0204 mvn.w r2, #4 + 800387e: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 8003880: 687b ldr r3, [r7, #4] + 8003882: 2202 movs r2, #2 + 8003884: 771a strb r2, [r3, #28] + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + 8003886: 687b ldr r3, [r7, #4] + 8003888: 681b ldr r3, [r3, #0] + 800388a: 699b ldr r3, [r3, #24] + 800388c: f403 7340 and.w r3, r3, #768 ; 0x300 + 8003890: 2b00 cmp r3, #0 + 8003892: d003 beq.n 800389c + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8003894: 6878 ldr r0, [r7, #4] + 8003896: f000 faad bl 8003df4 + 800389a: e005 b.n 80038a8 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 800389c: 6878 ldr r0, [r7, #4] + 800389e: f000 fa9f bl 8003de0 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 80038a2: 6878 ldr r0, [r7, #4] + 80038a4: f000 fab0 bl 8003e08 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 80038a8: 687b ldr r3, [r7, #4] + 80038aa: 2200 movs r2, #0 + 80038ac: 771a strb r2, [r3, #28] + } + } + /* Capture compare 3 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + 80038ae: 687b ldr r3, [r7, #4] + 80038b0: 681b ldr r3, [r3, #0] + 80038b2: 691b ldr r3, [r3, #16] + 80038b4: f003 0308 and.w r3, r3, #8 + 80038b8: 2b08 cmp r3, #8 + 80038ba: d122 bne.n 8003902 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + 80038bc: 687b ldr r3, [r7, #4] + 80038be: 681b ldr r3, [r3, #0] + 80038c0: 68db ldr r3, [r3, #12] + 80038c2: f003 0308 and.w r3, r3, #8 + 80038c6: 2b08 cmp r3, #8 + 80038c8: d11b bne.n 8003902 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + 80038ca: 687b ldr r3, [r7, #4] + 80038cc: 681b ldr r3, [r3, #0] + 80038ce: f06f 0208 mvn.w r2, #8 + 80038d2: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 80038d4: 687b ldr r3, [r7, #4] + 80038d6: 2204 movs r2, #4 + 80038d8: 771a strb r2, [r3, #28] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + 80038da: 687b ldr r3, [r7, #4] + 80038dc: 681b ldr r3, [r3, #0] + 80038de: 69db ldr r3, [r3, #28] + 80038e0: f003 0303 and.w r3, r3, #3 + 80038e4: 2b00 cmp r3, #0 + 80038e6: d003 beq.n 80038f0 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 80038e8: 6878 ldr r0, [r7, #4] + 80038ea: f000 fa83 bl 8003df4 + 80038ee: e005 b.n 80038fc + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 80038f0: 6878 ldr r0, [r7, #4] + 80038f2: f000 fa75 bl 8003de0 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 80038f6: 6878 ldr r0, [r7, #4] + 80038f8: f000 fa86 bl 8003e08 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 80038fc: 687b ldr r3, [r7, #4] + 80038fe: 2200 movs r2, #0 + 8003900: 771a strb r2, [r3, #28] + } + } + /* Capture compare 4 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + 8003902: 687b ldr r3, [r7, #4] + 8003904: 681b ldr r3, [r3, #0] + 8003906: 691b ldr r3, [r3, #16] + 8003908: f003 0310 and.w r3, r3, #16 + 800390c: 2b10 cmp r3, #16 + 800390e: d122 bne.n 8003956 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + 8003910: 687b ldr r3, [r7, #4] + 8003912: 681b ldr r3, [r3, #0] + 8003914: 68db ldr r3, [r3, #12] + 8003916: f003 0310 and.w r3, r3, #16 + 800391a: 2b10 cmp r3, #16 + 800391c: d11b bne.n 8003956 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + 800391e: 687b ldr r3, [r7, #4] + 8003920: 681b ldr r3, [r3, #0] + 8003922: f06f 0210 mvn.w r2, #16 + 8003926: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 8003928: 687b ldr r3, [r7, #4] + 800392a: 2208 movs r2, #8 + 800392c: 771a strb r2, [r3, #28] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + 800392e: 687b ldr r3, [r7, #4] + 8003930: 681b ldr r3, [r3, #0] + 8003932: 69db ldr r3, [r3, #28] + 8003934: f403 7340 and.w r3, r3, #768 ; 0x300 + 8003938: 2b00 cmp r3, #0 + 800393a: d003 beq.n 8003944 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 800393c: 6878 ldr r0, [r7, #4] + 800393e: f000 fa59 bl 8003df4 + 8003942: e005 b.n 8003950 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8003944: 6878 ldr r0, [r7, #4] + 8003946: f000 fa4b bl 8003de0 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 800394a: 6878 ldr r0, [r7, #4] + 800394c: f000 fa5c bl 8003e08 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8003950: 687b ldr r3, [r7, #4] + 8003952: 2200 movs r2, #0 + 8003954: 771a strb r2, [r3, #28] + } + } + /* TIM Update event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + 8003956: 687b ldr r3, [r7, #4] + 8003958: 681b ldr r3, [r3, #0] + 800395a: 691b ldr r3, [r3, #16] + 800395c: f003 0301 and.w r3, r3, #1 + 8003960: 2b01 cmp r3, #1 + 8003962: d10e bne.n 8003982 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + 8003964: 687b ldr r3, [r7, #4] + 8003966: 681b ldr r3, [r3, #0] + 8003968: 68db ldr r3, [r3, #12] + 800396a: f003 0301 and.w r3, r3, #1 + 800396e: 2b01 cmp r3, #1 + 8003970: d107 bne.n 8003982 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + 8003972: 687b ldr r3, [r7, #4] + 8003974: 681b ldr r3, [r3, #0] + 8003976: f06f 0201 mvn.w r2, #1 + 800397a: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); + 800397c: 6878 ldr r0, [r7, #4] + 800397e: f7fd fcfb bl 8001378 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + 8003982: 687b ldr r3, [r7, #4] + 8003984: 681b ldr r3, [r3, #0] + 8003986: 691b ldr r3, [r3, #16] + 8003988: f003 0380 and.w r3, r3, #128 ; 0x80 + 800398c: 2b80 cmp r3, #128 ; 0x80 + 800398e: d10e bne.n 80039ae + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + 8003990: 687b ldr r3, [r7, #4] + 8003992: 681b ldr r3, [r3, #0] + 8003994: 68db ldr r3, [r3, #12] + 8003996: f003 0380 and.w r3, r3, #128 ; 0x80 + 800399a: 2b80 cmp r3, #128 ; 0x80 + 800399c: d107 bne.n 80039ae + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + 800399e: 687b ldr r3, [r7, #4] + 80039a0: 681b ldr r3, [r3, #0] + 80039a2: f06f 0280 mvn.w r2, #128 ; 0x80 + 80039a6: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); + 80039a8: 6878 ldr r0, [r7, #4] + 80039aa: f000 fe65 bl 8004678 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break2 input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + 80039ae: 687b ldr r3, [r7, #4] + 80039b0: 681b ldr r3, [r3, #0] + 80039b2: 691b ldr r3, [r3, #16] + 80039b4: f403 7380 and.w r3, r3, #256 ; 0x100 + 80039b8: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 80039bc: d10e bne.n 80039dc + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + 80039be: 687b ldr r3, [r7, #4] + 80039c0: 681b ldr r3, [r3, #0] + 80039c2: 68db ldr r3, [r3, #12] + 80039c4: f003 0380 and.w r3, r3, #128 ; 0x80 + 80039c8: 2b80 cmp r3, #128 ; 0x80 + 80039ca: d107 bne.n 80039dc + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); + 80039cc: 687b ldr r3, [r7, #4] + 80039ce: 681b ldr r3, [r3, #0] + 80039d0: f46f 7280 mvn.w r2, #256 ; 0x100 + 80039d4: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); + 80039d6: 6878 ldr r0, [r7, #4] + 80039d8: f000 fe58 bl 800468c +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + 80039dc: 687b ldr r3, [r7, #4] + 80039de: 681b ldr r3, [r3, #0] + 80039e0: 691b ldr r3, [r3, #16] + 80039e2: f003 0340 and.w r3, r3, #64 ; 0x40 + 80039e6: 2b40 cmp r3, #64 ; 0x40 + 80039e8: d10e bne.n 8003a08 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + 80039ea: 687b ldr r3, [r7, #4] + 80039ec: 681b ldr r3, [r3, #0] + 80039ee: 68db ldr r3, [r3, #12] + 80039f0: f003 0340 and.w r3, r3, #64 ; 0x40 + 80039f4: 2b40 cmp r3, #64 ; 0x40 + 80039f6: d107 bne.n 8003a08 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + 80039f8: 687b ldr r3, [r7, #4] + 80039fa: 681b ldr r3, [r3, #0] + 80039fc: f06f 0240 mvn.w r2, #64 ; 0x40 + 8003a00: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); + 8003a02: 6878 ldr r0, [r7, #4] + 8003a04: f000 fa0a bl 8003e1c +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + 8003a08: 687b ldr r3, [r7, #4] + 8003a0a: 681b ldr r3, [r3, #0] + 8003a0c: 691b ldr r3, [r3, #16] + 8003a0e: f003 0320 and.w r3, r3, #32 + 8003a12: 2b20 cmp r3, #32 + 8003a14: d10e bne.n 8003a34 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + 8003a16: 687b ldr r3, [r7, #4] + 8003a18: 681b ldr r3, [r3, #0] + 8003a1a: 68db ldr r3, [r3, #12] + 8003a1c: f003 0320 and.w r3, r3, #32 + 8003a20: 2b20 cmp r3, #32 + 8003a22: d107 bne.n 8003a34 + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + 8003a24: 687b ldr r3, [r7, #4] + 8003a26: 681b ldr r3, [r3, #0] + 8003a28: f06f 0220 mvn.w r2, #32 + 8003a2c: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); + 8003a2e: 6878 ldr r0, [r7, #4] + 8003a30: f000 fe18 bl 8004664 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + 8003a34: bf00 nop + 8003a36: 3708 adds r7, #8 + 8003a38: 46bd mov sp, r7 + 8003a3a: bd80 pop {r7, pc} + +08003a3c : + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + 8003a3c: b580 push {r7, lr} + 8003a3e: b084 sub sp, #16 + 8003a40: af00 add r7, sp, #0 + 8003a42: 60f8 str r0, [r7, #12] + 8003a44: 60b9 str r1, [r7, #8] + 8003a46: 607a str r2, [r7, #4] + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + 8003a48: 68fb ldr r3, [r7, #12] + 8003a4a: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 8003a4e: 2b01 cmp r3, #1 + 8003a50: d101 bne.n 8003a56 + 8003a52: 2302 movs r3, #2 + 8003a54: e105 b.n 8003c62 + 8003a56: 68fb ldr r3, [r7, #12] + 8003a58: 2201 movs r2, #1 + 8003a5a: f883 203c strb.w r2, [r3, #60] ; 0x3c + + htim->State = HAL_TIM_STATE_BUSY; + 8003a5e: 68fb ldr r3, [r7, #12] + 8003a60: 2202 movs r2, #2 + 8003a62: f883 203d strb.w r2, [r3, #61] ; 0x3d + + switch (Channel) + 8003a66: 687b ldr r3, [r7, #4] + 8003a68: 2b14 cmp r3, #20 + 8003a6a: f200 80f0 bhi.w 8003c4e + 8003a6e: a201 add r2, pc, #4 ; (adr r2, 8003a74 ) + 8003a70: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8003a74: 08003ac9 .word 0x08003ac9 + 8003a78: 08003c4f .word 0x08003c4f + 8003a7c: 08003c4f .word 0x08003c4f + 8003a80: 08003c4f .word 0x08003c4f + 8003a84: 08003b09 .word 0x08003b09 + 8003a88: 08003c4f .word 0x08003c4f + 8003a8c: 08003c4f .word 0x08003c4f + 8003a90: 08003c4f .word 0x08003c4f + 8003a94: 08003b4b .word 0x08003b4b + 8003a98: 08003c4f .word 0x08003c4f + 8003a9c: 08003c4f .word 0x08003c4f + 8003aa0: 08003c4f .word 0x08003c4f + 8003aa4: 08003b8b .word 0x08003b8b + 8003aa8: 08003c4f .word 0x08003c4f + 8003aac: 08003c4f .word 0x08003c4f + 8003ab0: 08003c4f .word 0x08003c4f + 8003ab4: 08003bcd .word 0x08003bcd + 8003ab8: 08003c4f .word 0x08003c4f + 8003abc: 08003c4f .word 0x08003c4f + 8003ac0: 08003c4f .word 0x08003c4f + 8003ac4: 08003c0d .word 0x08003c0d + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + 8003ac8: 68fb ldr r3, [r7, #12] + 8003aca: 681b ldr r3, [r3, #0] + 8003acc: 68b9 ldr r1, [r7, #8] + 8003ace: 4618 mov r0, r3 + 8003ad0: f000 fa4e bl 8003f70 + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + 8003ad4: 68fb ldr r3, [r7, #12] + 8003ad6: 681b ldr r3, [r3, #0] + 8003ad8: 699a ldr r2, [r3, #24] + 8003ada: 68fb ldr r3, [r7, #12] + 8003adc: 681b ldr r3, [r3, #0] + 8003ade: f042 0208 orr.w r2, r2, #8 + 8003ae2: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + 8003ae4: 68fb ldr r3, [r7, #12] + 8003ae6: 681b ldr r3, [r3, #0] + 8003ae8: 699a ldr r2, [r3, #24] + 8003aea: 68fb ldr r3, [r7, #12] + 8003aec: 681b ldr r3, [r3, #0] + 8003aee: f022 0204 bic.w r2, r2, #4 + 8003af2: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode; + 8003af4: 68fb ldr r3, [r7, #12] + 8003af6: 681b ldr r3, [r3, #0] + 8003af8: 6999 ldr r1, [r3, #24] + 8003afa: 68bb ldr r3, [r7, #8] + 8003afc: 691a ldr r2, [r3, #16] + 8003afe: 68fb ldr r3, [r7, #12] + 8003b00: 681b ldr r3, [r3, #0] + 8003b02: 430a orrs r2, r1 + 8003b04: 619a str r2, [r3, #24] + break; + 8003b06: e0a3 b.n 8003c50 + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + 8003b08: 68fb ldr r3, [r7, #12] + 8003b0a: 681b ldr r3, [r3, #0] + 8003b0c: 68b9 ldr r1, [r7, #8] + 8003b0e: 4618 mov r0, r3 + 8003b10: f000 faa0 bl 8004054 + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + 8003b14: 68fb ldr r3, [r7, #12] + 8003b16: 681b ldr r3, [r3, #0] + 8003b18: 699a ldr r2, [r3, #24] + 8003b1a: 68fb ldr r3, [r7, #12] + 8003b1c: 681b ldr r3, [r3, #0] + 8003b1e: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 8003b22: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + 8003b24: 68fb ldr r3, [r7, #12] + 8003b26: 681b ldr r3, [r3, #0] + 8003b28: 699a ldr r2, [r3, #24] + 8003b2a: 68fb ldr r3, [r7, #12] + 8003b2c: 681b ldr r3, [r3, #0] + 8003b2e: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 8003b32: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + 8003b34: 68fb ldr r3, [r7, #12] + 8003b36: 681b ldr r3, [r3, #0] + 8003b38: 6999 ldr r1, [r3, #24] + 8003b3a: 68bb ldr r3, [r7, #8] + 8003b3c: 691b ldr r3, [r3, #16] + 8003b3e: 021a lsls r2, r3, #8 + 8003b40: 68fb ldr r3, [r7, #12] + 8003b42: 681b ldr r3, [r3, #0] + 8003b44: 430a orrs r2, r1 + 8003b46: 619a str r2, [r3, #24] + break; + 8003b48: e082 b.n 8003c50 + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + 8003b4a: 68fb ldr r3, [r7, #12] + 8003b4c: 681b ldr r3, [r3, #0] + 8003b4e: 68b9 ldr r1, [r7, #8] + 8003b50: 4618 mov r0, r3 + 8003b52: f000 faf7 bl 8004144 + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + 8003b56: 68fb ldr r3, [r7, #12] + 8003b58: 681b ldr r3, [r3, #0] + 8003b5a: 69da ldr r2, [r3, #28] + 8003b5c: 68fb ldr r3, [r7, #12] + 8003b5e: 681b ldr r3, [r3, #0] + 8003b60: f042 0208 orr.w r2, r2, #8 + 8003b64: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + 8003b66: 68fb ldr r3, [r7, #12] + 8003b68: 681b ldr r3, [r3, #0] + 8003b6a: 69da ldr r2, [r3, #28] + 8003b6c: 68fb ldr r3, [r7, #12] + 8003b6e: 681b ldr r3, [r3, #0] + 8003b70: f022 0204 bic.w r2, r2, #4 + 8003b74: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode; + 8003b76: 68fb ldr r3, [r7, #12] + 8003b78: 681b ldr r3, [r3, #0] + 8003b7a: 69d9 ldr r1, [r3, #28] + 8003b7c: 68bb ldr r3, [r7, #8] + 8003b7e: 691a ldr r2, [r3, #16] + 8003b80: 68fb ldr r3, [r7, #12] + 8003b82: 681b ldr r3, [r3, #0] + 8003b84: 430a orrs r2, r1 + 8003b86: 61da str r2, [r3, #28] + break; + 8003b88: e062 b.n 8003c50 + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + 8003b8a: 68fb ldr r3, [r7, #12] + 8003b8c: 681b ldr r3, [r3, #0] + 8003b8e: 68b9 ldr r1, [r7, #8] + 8003b90: 4618 mov r0, r3 + 8003b92: f000 fb4d bl 8004230 + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + 8003b96: 68fb ldr r3, [r7, #12] + 8003b98: 681b ldr r3, [r3, #0] + 8003b9a: 69da ldr r2, [r3, #28] + 8003b9c: 68fb ldr r3, [r7, #12] + 8003b9e: 681b ldr r3, [r3, #0] + 8003ba0: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 8003ba4: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + 8003ba6: 68fb ldr r3, [r7, #12] + 8003ba8: 681b ldr r3, [r3, #0] + 8003baa: 69da ldr r2, [r3, #28] + 8003bac: 68fb ldr r3, [r7, #12] + 8003bae: 681b ldr r3, [r3, #0] + 8003bb0: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 8003bb4: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + 8003bb6: 68fb ldr r3, [r7, #12] + 8003bb8: 681b ldr r3, [r3, #0] + 8003bba: 69d9 ldr r1, [r3, #28] + 8003bbc: 68bb ldr r3, [r7, #8] + 8003bbe: 691b ldr r3, [r3, #16] + 8003bc0: 021a lsls r2, r3, #8 + 8003bc2: 68fb ldr r3, [r7, #12] + 8003bc4: 681b ldr r3, [r3, #0] + 8003bc6: 430a orrs r2, r1 + 8003bc8: 61da str r2, [r3, #28] + break; + 8003bca: e041 b.n 8003c50 + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the Channel 5 in PWM mode */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + 8003bcc: 68fb ldr r3, [r7, #12] + 8003bce: 681b ldr r3, [r3, #0] + 8003bd0: 68b9 ldr r1, [r7, #8] + 8003bd2: 4618 mov r0, r3 + 8003bd4: f000 fb84 bl 80042e0 + + /* Set the Preload enable bit for channel5*/ + htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; + 8003bd8: 68fb ldr r3, [r7, #12] + 8003bda: 681b ldr r3, [r3, #0] + 8003bdc: 6d5a ldr r2, [r3, #84] ; 0x54 + 8003bde: 68fb ldr r3, [r7, #12] + 8003be0: 681b ldr r3, [r3, #0] + 8003be2: f042 0208 orr.w r2, r2, #8 + 8003be6: 655a str r2, [r3, #84] ; 0x54 + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; + 8003be8: 68fb ldr r3, [r7, #12] + 8003bea: 681b ldr r3, [r3, #0] + 8003bec: 6d5a ldr r2, [r3, #84] ; 0x54 + 8003bee: 68fb ldr r3, [r7, #12] + 8003bf0: 681b ldr r3, [r3, #0] + 8003bf2: f022 0204 bic.w r2, r2, #4 + 8003bf6: 655a str r2, [r3, #84] ; 0x54 + htim->Instance->CCMR3 |= sConfig->OCFastMode; + 8003bf8: 68fb ldr r3, [r7, #12] + 8003bfa: 681b ldr r3, [r3, #0] + 8003bfc: 6d59 ldr r1, [r3, #84] ; 0x54 + 8003bfe: 68bb ldr r3, [r7, #8] + 8003c00: 691a ldr r2, [r3, #16] + 8003c02: 68fb ldr r3, [r7, #12] + 8003c04: 681b ldr r3, [r3, #0] + 8003c06: 430a orrs r2, r1 + 8003c08: 655a str r2, [r3, #84] ; 0x54 + break; + 8003c0a: e021 b.n 8003c50 + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the Channel 6 in PWM mode */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + 8003c0c: 68fb ldr r3, [r7, #12] + 8003c0e: 681b ldr r3, [r3, #0] + 8003c10: 68b9 ldr r1, [r7, #8] + 8003c12: 4618 mov r0, r3 + 8003c14: f000 fbb6 bl 8004384 + + /* Set the Preload enable bit for channel6 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; + 8003c18: 68fb ldr r3, [r7, #12] + 8003c1a: 681b ldr r3, [r3, #0] + 8003c1c: 6d5a ldr r2, [r3, #84] ; 0x54 + 8003c1e: 68fb ldr r3, [r7, #12] + 8003c20: 681b ldr r3, [r3, #0] + 8003c22: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 8003c26: 655a str r2, [r3, #84] ; 0x54 + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; + 8003c28: 68fb ldr r3, [r7, #12] + 8003c2a: 681b ldr r3, [r3, #0] + 8003c2c: 6d5a ldr r2, [r3, #84] ; 0x54 + 8003c2e: 68fb ldr r3, [r7, #12] + 8003c30: 681b ldr r3, [r3, #0] + 8003c32: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 8003c36: 655a str r2, [r3, #84] ; 0x54 + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + 8003c38: 68fb ldr r3, [r7, #12] + 8003c3a: 681b ldr r3, [r3, #0] + 8003c3c: 6d59 ldr r1, [r3, #84] ; 0x54 + 8003c3e: 68bb ldr r3, [r7, #8] + 8003c40: 691b ldr r3, [r3, #16] + 8003c42: 021a lsls r2, r3, #8 + 8003c44: 68fb ldr r3, [r7, #12] + 8003c46: 681b ldr r3, [r3, #0] + 8003c48: 430a orrs r2, r1 + 8003c4a: 655a str r2, [r3, #84] ; 0x54 + break; + 8003c4c: e000 b.n 8003c50 + } + + default: + break; + 8003c4e: bf00 nop + } + + htim->State = HAL_TIM_STATE_READY; + 8003c50: 68fb ldr r3, [r7, #12] + 8003c52: 2201 movs r2, #1 + 8003c54: f883 203d strb.w r2, [r3, #61] ; 0x3d + + __HAL_UNLOCK(htim); + 8003c58: 68fb ldr r3, [r7, #12] + 8003c5a: 2200 movs r2, #0 + 8003c5c: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_OK; + 8003c60: 2300 movs r3, #0 +} + 8003c62: 4618 mov r0, r3 + 8003c64: 3710 adds r7, #16 + 8003c66: 46bd mov sp, r7 + 8003c68: bd80 pop {r7, pc} + 8003c6a: bf00 nop + +08003c6c : + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + 8003c6c: b580 push {r7, lr} + 8003c6e: b084 sub sp, #16 + 8003c70: af00 add r7, sp, #0 + 8003c72: 6078 str r0, [r7, #4] + 8003c74: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + 8003c76: 687b ldr r3, [r7, #4] + 8003c78: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 8003c7c: 2b01 cmp r3, #1 + 8003c7e: d101 bne.n 8003c84 + 8003c80: 2302 movs r3, #2 + 8003c82: e0a6 b.n 8003dd2 + 8003c84: 687b ldr r3, [r7, #4] + 8003c86: 2201 movs r2, #1 + 8003c88: f883 203c strb.w r2, [r3, #60] ; 0x3c + + htim->State = HAL_TIM_STATE_BUSY; + 8003c8c: 687b ldr r3, [r7, #4] + 8003c8e: 2202 movs r2, #2 + 8003c90: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + 8003c94: 687b ldr r3, [r7, #4] + 8003c96: 681b ldr r3, [r3, #0] + 8003c98: 689b ldr r3, [r3, #8] + 8003c9a: 60fb str r3, [r7, #12] + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + 8003c9c: 68fa ldr r2, [r7, #12] + 8003c9e: 4b4f ldr r3, [pc, #316] ; (8003ddc ) + 8003ca0: 4013 ands r3, r2 + 8003ca2: 60fb str r3, [r7, #12] + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 8003ca4: 68fb ldr r3, [r7, #12] + 8003ca6: f423 437f bic.w r3, r3, #65280 ; 0xff00 + 8003caa: 60fb str r3, [r7, #12] + htim->Instance->SMCR = tmpsmcr; + 8003cac: 687b ldr r3, [r7, #4] + 8003cae: 681b ldr r3, [r3, #0] + 8003cb0: 68fa ldr r2, [r7, #12] + 8003cb2: 609a str r2, [r3, #8] + + switch (sClockSourceConfig->ClockSource) + 8003cb4: 683b ldr r3, [r7, #0] + 8003cb6: 681b ldr r3, [r3, #0] + 8003cb8: 2b40 cmp r3, #64 ; 0x40 + 8003cba: d067 beq.n 8003d8c + 8003cbc: 2b40 cmp r3, #64 ; 0x40 + 8003cbe: d80b bhi.n 8003cd8 + 8003cc0: 2b10 cmp r3, #16 + 8003cc2: d073 beq.n 8003dac + 8003cc4: 2b10 cmp r3, #16 + 8003cc6: d802 bhi.n 8003cce + 8003cc8: 2b00 cmp r3, #0 + 8003cca: d06f beq.n 8003dac + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + break; + 8003ccc: e078 b.n 8003dc0 + switch (sClockSourceConfig->ClockSource) + 8003cce: 2b20 cmp r3, #32 + 8003cd0: d06c beq.n 8003dac + 8003cd2: 2b30 cmp r3, #48 ; 0x30 + 8003cd4: d06a beq.n 8003dac + break; + 8003cd6: e073 b.n 8003dc0 + switch (sClockSourceConfig->ClockSource) + 8003cd8: 2b70 cmp r3, #112 ; 0x70 + 8003cda: d00d beq.n 8003cf8 + 8003cdc: 2b70 cmp r3, #112 ; 0x70 + 8003cde: d804 bhi.n 8003cea + 8003ce0: 2b50 cmp r3, #80 ; 0x50 + 8003ce2: d033 beq.n 8003d4c + 8003ce4: 2b60 cmp r3, #96 ; 0x60 + 8003ce6: d041 beq.n 8003d6c + break; + 8003ce8: e06a b.n 8003dc0 + switch (sClockSourceConfig->ClockSource) + 8003cea: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8003cee: d066 beq.n 8003dbe + 8003cf0: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 8003cf4: d017 beq.n 8003d26 + break; + 8003cf6: e063 b.n 8003dc0 + TIM_ETR_SetConfig(htim->Instance, + 8003cf8: 687b ldr r3, [r7, #4] + 8003cfa: 6818 ldr r0, [r3, #0] + 8003cfc: 683b ldr r3, [r7, #0] + 8003cfe: 6899 ldr r1, [r3, #8] + 8003d00: 683b ldr r3, [r7, #0] + 8003d02: 685a ldr r2, [r3, #4] + 8003d04: 683b ldr r3, [r7, #0] + 8003d06: 68db ldr r3, [r3, #12] + 8003d08: f000 fc0a bl 8004520 + tmpsmcr = htim->Instance->SMCR; + 8003d0c: 687b ldr r3, [r7, #4] + 8003d0e: 681b ldr r3, [r3, #0] + 8003d10: 689b ldr r3, [r3, #8] + 8003d12: 60fb str r3, [r7, #12] + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + 8003d14: 68fb ldr r3, [r7, #12] + 8003d16: f043 0377 orr.w r3, r3, #119 ; 0x77 + 8003d1a: 60fb str r3, [r7, #12] + htim->Instance->SMCR = tmpsmcr; + 8003d1c: 687b ldr r3, [r7, #4] + 8003d1e: 681b ldr r3, [r3, #0] + 8003d20: 68fa ldr r2, [r7, #12] + 8003d22: 609a str r2, [r3, #8] + break; + 8003d24: e04c b.n 8003dc0 + TIM_ETR_SetConfig(htim->Instance, + 8003d26: 687b ldr r3, [r7, #4] + 8003d28: 6818 ldr r0, [r3, #0] + 8003d2a: 683b ldr r3, [r7, #0] + 8003d2c: 6899 ldr r1, [r3, #8] + 8003d2e: 683b ldr r3, [r7, #0] + 8003d30: 685a ldr r2, [r3, #4] + 8003d32: 683b ldr r3, [r7, #0] + 8003d34: 68db ldr r3, [r3, #12] + 8003d36: f000 fbf3 bl 8004520 + htim->Instance->SMCR |= TIM_SMCR_ECE; + 8003d3a: 687b ldr r3, [r7, #4] + 8003d3c: 681b ldr r3, [r3, #0] + 8003d3e: 689a ldr r2, [r3, #8] + 8003d40: 687b ldr r3, [r7, #4] + 8003d42: 681b ldr r3, [r3, #0] + 8003d44: f442 4280 orr.w r2, r2, #16384 ; 0x4000 + 8003d48: 609a str r2, [r3, #8] + break; + 8003d4a: e039 b.n 8003dc0 + TIM_TI1_ConfigInputStage(htim->Instance, + 8003d4c: 687b ldr r3, [r7, #4] + 8003d4e: 6818 ldr r0, [r3, #0] + 8003d50: 683b ldr r3, [r7, #0] + 8003d52: 6859 ldr r1, [r3, #4] + 8003d54: 683b ldr r3, [r7, #0] + 8003d56: 68db ldr r3, [r3, #12] + 8003d58: 461a mov r2, r3 + 8003d5a: f000 fb67 bl 800442c + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + 8003d5e: 687b ldr r3, [r7, #4] + 8003d60: 681b ldr r3, [r3, #0] + 8003d62: 2150 movs r1, #80 ; 0x50 + 8003d64: 4618 mov r0, r3 + 8003d66: f000 fbc0 bl 80044ea + break; + 8003d6a: e029 b.n 8003dc0 + TIM_TI2_ConfigInputStage(htim->Instance, + 8003d6c: 687b ldr r3, [r7, #4] + 8003d6e: 6818 ldr r0, [r3, #0] + 8003d70: 683b ldr r3, [r7, #0] + 8003d72: 6859 ldr r1, [r3, #4] + 8003d74: 683b ldr r3, [r7, #0] + 8003d76: 68db ldr r3, [r3, #12] + 8003d78: 461a mov r2, r3 + 8003d7a: f000 fb86 bl 800448a + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + 8003d7e: 687b ldr r3, [r7, #4] + 8003d80: 681b ldr r3, [r3, #0] + 8003d82: 2160 movs r1, #96 ; 0x60 + 8003d84: 4618 mov r0, r3 + 8003d86: f000 fbb0 bl 80044ea + break; + 8003d8a: e019 b.n 8003dc0 + TIM_TI1_ConfigInputStage(htim->Instance, + 8003d8c: 687b ldr r3, [r7, #4] + 8003d8e: 6818 ldr r0, [r3, #0] + 8003d90: 683b ldr r3, [r7, #0] + 8003d92: 6859 ldr r1, [r3, #4] + 8003d94: 683b ldr r3, [r7, #0] + 8003d96: 68db ldr r3, [r3, #12] + 8003d98: 461a mov r2, r3 + 8003d9a: f000 fb47 bl 800442c + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + 8003d9e: 687b ldr r3, [r7, #4] + 8003da0: 681b ldr r3, [r3, #0] + 8003da2: 2140 movs r1, #64 ; 0x40 + 8003da4: 4618 mov r0, r3 + 8003da6: f000 fba0 bl 80044ea + break; + 8003daa: e009 b.n 8003dc0 + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + 8003dac: 687b ldr r3, [r7, #4] + 8003dae: 681a ldr r2, [r3, #0] + 8003db0: 683b ldr r3, [r7, #0] + 8003db2: 681b ldr r3, [r3, #0] + 8003db4: 4619 mov r1, r3 + 8003db6: 4610 mov r0, r2 + 8003db8: f000 fb97 bl 80044ea + break; + 8003dbc: e000 b.n 8003dc0 + break; + 8003dbe: bf00 nop + } + htim->State = HAL_TIM_STATE_READY; + 8003dc0: 687b ldr r3, [r7, #4] + 8003dc2: 2201 movs r2, #1 + 8003dc4: f883 203d strb.w r2, [r3, #61] ; 0x3d + + __HAL_UNLOCK(htim); + 8003dc8: 687b ldr r3, [r7, #4] + 8003dca: 2200 movs r2, #0 + 8003dcc: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_OK; + 8003dd0: 2300 movs r3, #0 +} + 8003dd2: 4618 mov r0, r3 + 8003dd4: 3710 adds r7, #16 + 8003dd6: 46bd mov sp, r7 + 8003dd8: bd80 pop {r7, pc} + 8003dda: bf00 nop + 8003ddc: fffeff88 .word 0xfffeff88 + +08003de0 : + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + 8003de0: b480 push {r7} + 8003de2: b083 sub sp, #12 + 8003de4: af00 add r7, sp, #0 + 8003de6: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + 8003de8: bf00 nop + 8003dea: 370c adds r7, #12 + 8003dec: 46bd mov sp, r7 + 8003dee: f85d 7b04 ldr.w r7, [sp], #4 + 8003df2: 4770 bx lr + +08003df4 : + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + 8003df4: b480 push {r7} + 8003df6: b083 sub sp, #12 + 8003df8: af00 add r7, sp, #0 + 8003dfa: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + 8003dfc: bf00 nop + 8003dfe: 370c adds r7, #12 + 8003e00: 46bd mov sp, r7 + 8003e02: f85d 7b04 ldr.w r7, [sp], #4 + 8003e06: 4770 bx lr + +08003e08 : + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + 8003e08: b480 push {r7} + 8003e0a: b083 sub sp, #12 + 8003e0c: af00 add r7, sp, #0 + 8003e0e: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + 8003e10: bf00 nop + 8003e12: 370c adds r7, #12 + 8003e14: 46bd mov sp, r7 + 8003e16: f85d 7b04 ldr.w r7, [sp], #4 + 8003e1a: 4770 bx lr + +08003e1c : + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + 8003e1c: b480 push {r7} + 8003e1e: b083 sub sp, #12 + 8003e20: af00 add r7, sp, #0 + 8003e22: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + 8003e24: bf00 nop + 8003e26: 370c adds r7, #12 + 8003e28: 46bd mov sp, r7 + 8003e2a: f85d 7b04 ldr.w r7, [sp], #4 + 8003e2e: 4770 bx lr + +08003e30 : + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + 8003e30: b480 push {r7} + 8003e32: b085 sub sp, #20 + 8003e34: af00 add r7, sp, #0 + 8003e36: 6078 str r0, [r7, #4] + 8003e38: 6039 str r1, [r7, #0] + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + 8003e3a: 687b ldr r3, [r7, #4] + 8003e3c: 681b ldr r3, [r3, #0] + 8003e3e: 60fb str r3, [r7, #12] + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + 8003e40: 687b ldr r3, [r7, #4] + 8003e42: 4a40 ldr r2, [pc, #256] ; (8003f44 ) + 8003e44: 4293 cmp r3, r2 + 8003e46: d013 beq.n 8003e70 + 8003e48: 687b ldr r3, [r7, #4] + 8003e4a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 8003e4e: d00f beq.n 8003e70 + 8003e50: 687b ldr r3, [r7, #4] + 8003e52: 4a3d ldr r2, [pc, #244] ; (8003f48 ) + 8003e54: 4293 cmp r3, r2 + 8003e56: d00b beq.n 8003e70 + 8003e58: 687b ldr r3, [r7, #4] + 8003e5a: 4a3c ldr r2, [pc, #240] ; (8003f4c ) + 8003e5c: 4293 cmp r3, r2 + 8003e5e: d007 beq.n 8003e70 + 8003e60: 687b ldr r3, [r7, #4] + 8003e62: 4a3b ldr r2, [pc, #236] ; (8003f50 ) + 8003e64: 4293 cmp r3, r2 + 8003e66: d003 beq.n 8003e70 + 8003e68: 687b ldr r3, [r7, #4] + 8003e6a: 4a3a ldr r2, [pc, #232] ; (8003f54 ) + 8003e6c: 4293 cmp r3, r2 + 8003e6e: d108 bne.n 8003e82 + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + 8003e70: 68fb ldr r3, [r7, #12] + 8003e72: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8003e76: 60fb str r3, [r7, #12] + tmpcr1 |= Structure->CounterMode; + 8003e78: 683b ldr r3, [r7, #0] + 8003e7a: 685b ldr r3, [r3, #4] + 8003e7c: 68fa ldr r2, [r7, #12] + 8003e7e: 4313 orrs r3, r2 + 8003e80: 60fb str r3, [r7, #12] + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + 8003e82: 687b ldr r3, [r7, #4] + 8003e84: 4a2f ldr r2, [pc, #188] ; (8003f44 ) + 8003e86: 4293 cmp r3, r2 + 8003e88: d02b beq.n 8003ee2 + 8003e8a: 687b ldr r3, [r7, #4] + 8003e8c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 8003e90: d027 beq.n 8003ee2 + 8003e92: 687b ldr r3, [r7, #4] + 8003e94: 4a2c ldr r2, [pc, #176] ; (8003f48 ) + 8003e96: 4293 cmp r3, r2 + 8003e98: d023 beq.n 8003ee2 + 8003e9a: 687b ldr r3, [r7, #4] + 8003e9c: 4a2b ldr r2, [pc, #172] ; (8003f4c ) + 8003e9e: 4293 cmp r3, r2 + 8003ea0: d01f beq.n 8003ee2 + 8003ea2: 687b ldr r3, [r7, #4] + 8003ea4: 4a2a ldr r2, [pc, #168] ; (8003f50 ) + 8003ea6: 4293 cmp r3, r2 + 8003ea8: d01b beq.n 8003ee2 + 8003eaa: 687b ldr r3, [r7, #4] + 8003eac: 4a29 ldr r2, [pc, #164] ; (8003f54 ) + 8003eae: 4293 cmp r3, r2 + 8003eb0: d017 beq.n 8003ee2 + 8003eb2: 687b ldr r3, [r7, #4] + 8003eb4: 4a28 ldr r2, [pc, #160] ; (8003f58 ) + 8003eb6: 4293 cmp r3, r2 + 8003eb8: d013 beq.n 8003ee2 + 8003eba: 687b ldr r3, [r7, #4] + 8003ebc: 4a27 ldr r2, [pc, #156] ; (8003f5c ) + 8003ebe: 4293 cmp r3, r2 + 8003ec0: d00f beq.n 8003ee2 + 8003ec2: 687b ldr r3, [r7, #4] + 8003ec4: 4a26 ldr r2, [pc, #152] ; (8003f60 ) + 8003ec6: 4293 cmp r3, r2 + 8003ec8: d00b beq.n 8003ee2 + 8003eca: 687b ldr r3, [r7, #4] + 8003ecc: 4a25 ldr r2, [pc, #148] ; (8003f64 ) + 8003ece: 4293 cmp r3, r2 + 8003ed0: d007 beq.n 8003ee2 + 8003ed2: 687b ldr r3, [r7, #4] + 8003ed4: 4a24 ldr r2, [pc, #144] ; (8003f68 ) + 8003ed6: 4293 cmp r3, r2 + 8003ed8: d003 beq.n 8003ee2 + 8003eda: 687b ldr r3, [r7, #4] + 8003edc: 4a23 ldr r2, [pc, #140] ; (8003f6c ) + 8003ede: 4293 cmp r3, r2 + 8003ee0: d108 bne.n 8003ef4 + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + 8003ee2: 68fb ldr r3, [r7, #12] + 8003ee4: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8003ee8: 60fb str r3, [r7, #12] + tmpcr1 |= (uint32_t)Structure->ClockDivision; + 8003eea: 683b ldr r3, [r7, #0] + 8003eec: 68db ldr r3, [r3, #12] + 8003eee: 68fa ldr r2, [r7, #12] + 8003ef0: 4313 orrs r3, r2 + 8003ef2: 60fb str r3, [r7, #12] + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + 8003ef4: 68fb ldr r3, [r7, #12] + 8003ef6: f023 0280 bic.w r2, r3, #128 ; 0x80 + 8003efa: 683b ldr r3, [r7, #0] + 8003efc: 695b ldr r3, [r3, #20] + 8003efe: 4313 orrs r3, r2 + 8003f00: 60fb str r3, [r7, #12] + + TIMx->CR1 = tmpcr1; + 8003f02: 687b ldr r3, [r7, #4] + 8003f04: 68fa ldr r2, [r7, #12] + 8003f06: 601a str r2, [r3, #0] + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + 8003f08: 683b ldr r3, [r7, #0] + 8003f0a: 689a ldr r2, [r3, #8] + 8003f0c: 687b ldr r3, [r7, #4] + 8003f0e: 62da str r2, [r3, #44] ; 0x2c + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + 8003f10: 683b ldr r3, [r7, #0] + 8003f12: 681a ldr r2, [r3, #0] + 8003f14: 687b ldr r3, [r7, #4] + 8003f16: 629a str r2, [r3, #40] ; 0x28 + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + 8003f18: 687b ldr r3, [r7, #4] + 8003f1a: 4a0a ldr r2, [pc, #40] ; (8003f44 ) + 8003f1c: 4293 cmp r3, r2 + 8003f1e: d003 beq.n 8003f28 + 8003f20: 687b ldr r3, [r7, #4] + 8003f22: 4a0c ldr r2, [pc, #48] ; (8003f54 ) + 8003f24: 4293 cmp r3, r2 + 8003f26: d103 bne.n 8003f30 + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + 8003f28: 683b ldr r3, [r7, #0] + 8003f2a: 691a ldr r2, [r3, #16] + 8003f2c: 687b ldr r3, [r7, #4] + 8003f2e: 631a str r2, [r3, #48] ; 0x30 + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + 8003f30: 687b ldr r3, [r7, #4] + 8003f32: 2201 movs r2, #1 + 8003f34: 615a str r2, [r3, #20] +} + 8003f36: bf00 nop + 8003f38: 3714 adds r7, #20 + 8003f3a: 46bd mov sp, r7 + 8003f3c: f85d 7b04 ldr.w r7, [sp], #4 + 8003f40: 4770 bx lr + 8003f42: bf00 nop + 8003f44: 40010000 .word 0x40010000 + 8003f48: 40000400 .word 0x40000400 + 8003f4c: 40000800 .word 0x40000800 + 8003f50: 40000c00 .word 0x40000c00 + 8003f54: 40010400 .word 0x40010400 + 8003f58: 40014000 .word 0x40014000 + 8003f5c: 40014400 .word 0x40014400 + 8003f60: 40014800 .word 0x40014800 + 8003f64: 40001800 .word 0x40001800 + 8003f68: 40001c00 .word 0x40001c00 + 8003f6c: 40002000 .word 0x40002000 + +08003f70 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 8003f70: b480 push {r7} + 8003f72: b087 sub sp, #28 + 8003f74: af00 add r7, sp, #0 + 8003f76: 6078 str r0, [r7, #4] + 8003f78: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + 8003f7a: 687b ldr r3, [r7, #4] + 8003f7c: 6a1b ldr r3, [r3, #32] + 8003f7e: f023 0201 bic.w r2, r3, #1 + 8003f82: 687b ldr r3, [r7, #4] + 8003f84: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8003f86: 687b ldr r3, [r7, #4] + 8003f88: 6a1b ldr r3, [r3, #32] + 8003f8a: 617b str r3, [r7, #20] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8003f8c: 687b ldr r3, [r7, #4] + 8003f8e: 685b ldr r3, [r3, #4] + 8003f90: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 8003f92: 687b ldr r3, [r7, #4] + 8003f94: 699b ldr r3, [r3, #24] + 8003f96: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + 8003f98: 68fa ldr r2, [r7, #12] + 8003f9a: 4b2b ldr r3, [pc, #172] ; (8004048 ) + 8003f9c: 4013 ands r3, r2 + 8003f9e: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC1S; + 8003fa0: 68fb ldr r3, [r7, #12] + 8003fa2: f023 0303 bic.w r3, r3, #3 + 8003fa6: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 8003fa8: 683b ldr r3, [r7, #0] + 8003faa: 681b ldr r3, [r3, #0] + 8003fac: 68fa ldr r2, [r7, #12] + 8003fae: 4313 orrs r3, r2 + 8003fb0: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + 8003fb2: 697b ldr r3, [r7, #20] + 8003fb4: f023 0302 bic.w r3, r3, #2 + 8003fb8: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + 8003fba: 683b ldr r3, [r7, #0] + 8003fbc: 689b ldr r3, [r3, #8] + 8003fbe: 697a ldr r2, [r7, #20] + 8003fc0: 4313 orrs r3, r2 + 8003fc2: 617b str r3, [r7, #20] + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + 8003fc4: 687b ldr r3, [r7, #4] + 8003fc6: 4a21 ldr r2, [pc, #132] ; (800404c ) + 8003fc8: 4293 cmp r3, r2 + 8003fca: d003 beq.n 8003fd4 + 8003fcc: 687b ldr r3, [r7, #4] + 8003fce: 4a20 ldr r2, [pc, #128] ; (8004050 ) + 8003fd0: 4293 cmp r3, r2 + 8003fd2: d10c bne.n 8003fee + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + 8003fd4: 697b ldr r3, [r7, #20] + 8003fd6: f023 0308 bic.w r3, r3, #8 + 8003fda: 617b str r3, [r7, #20] + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + 8003fdc: 683b ldr r3, [r7, #0] + 8003fde: 68db ldr r3, [r3, #12] + 8003fe0: 697a ldr r2, [r7, #20] + 8003fe2: 4313 orrs r3, r2 + 8003fe4: 617b str r3, [r7, #20] + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + 8003fe6: 697b ldr r3, [r7, #20] + 8003fe8: f023 0304 bic.w r3, r3, #4 + 8003fec: 617b str r3, [r7, #20] + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 8003fee: 687b ldr r3, [r7, #4] + 8003ff0: 4a16 ldr r2, [pc, #88] ; (800404c ) + 8003ff2: 4293 cmp r3, r2 + 8003ff4: d003 beq.n 8003ffe + 8003ff6: 687b ldr r3, [r7, #4] + 8003ff8: 4a15 ldr r2, [pc, #84] ; (8004050 ) + 8003ffa: 4293 cmp r3, r2 + 8003ffc: d111 bne.n 8004022 + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + 8003ffe: 693b ldr r3, [r7, #16] + 8004000: f423 7380 bic.w r3, r3, #256 ; 0x100 + 8004004: 613b str r3, [r7, #16] + tmpcr2 &= ~TIM_CR2_OIS1N; + 8004006: 693b ldr r3, [r7, #16] + 8004008: f423 7300 bic.w r3, r3, #512 ; 0x200 + 800400c: 613b str r3, [r7, #16] + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + 800400e: 683b ldr r3, [r7, #0] + 8004010: 695b ldr r3, [r3, #20] + 8004012: 693a ldr r2, [r7, #16] + 8004014: 4313 orrs r3, r2 + 8004016: 613b str r3, [r7, #16] + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + 8004018: 683b ldr r3, [r7, #0] + 800401a: 699b ldr r3, [r3, #24] + 800401c: 693a ldr r2, [r7, #16] + 800401e: 4313 orrs r3, r2 + 8004020: 613b str r3, [r7, #16] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8004022: 687b ldr r3, [r7, #4] + 8004024: 693a ldr r2, [r7, #16] + 8004026: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8004028: 687b ldr r3, [r7, #4] + 800402a: 68fa ldr r2, [r7, #12] + 800402c: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + 800402e: 683b ldr r3, [r7, #0] + 8004030: 685a ldr r2, [r3, #4] + 8004032: 687b ldr r3, [r7, #4] + 8004034: 635a str r2, [r3, #52] ; 0x34 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8004036: 687b ldr r3, [r7, #4] + 8004038: 697a ldr r2, [r7, #20] + 800403a: 621a str r2, [r3, #32] +} + 800403c: bf00 nop + 800403e: 371c adds r7, #28 + 8004040: 46bd mov sp, r7 + 8004042: f85d 7b04 ldr.w r7, [sp], #4 + 8004046: 4770 bx lr + 8004048: fffeff8f .word 0xfffeff8f + 800404c: 40010000 .word 0x40010000 + 8004050: 40010400 .word 0x40010400 + +08004054 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 8004054: b480 push {r7} + 8004056: b087 sub sp, #28 + 8004058: af00 add r7, sp, #0 + 800405a: 6078 str r0, [r7, #4] + 800405c: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + 800405e: 687b ldr r3, [r7, #4] + 8004060: 6a1b ldr r3, [r3, #32] + 8004062: f023 0210 bic.w r2, r3, #16 + 8004066: 687b ldr r3, [r7, #4] + 8004068: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 800406a: 687b ldr r3, [r7, #4] + 800406c: 6a1b ldr r3, [r3, #32] + 800406e: 617b str r3, [r7, #20] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8004070: 687b ldr r3, [r7, #4] + 8004072: 685b ldr r3, [r3, #4] + 8004074: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 8004076: 687b ldr r3, [r7, #4] + 8004078: 699b ldr r3, [r3, #24] + 800407a: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + 800407c: 68fa ldr r2, [r7, #12] + 800407e: 4b2e ldr r3, [pc, #184] ; (8004138 ) + 8004080: 4013 ands r3, r2 + 8004082: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC2S; + 8004084: 68fb ldr r3, [r7, #12] + 8004086: f423 7340 bic.w r3, r3, #768 ; 0x300 + 800408a: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 800408c: 683b ldr r3, [r7, #0] + 800408e: 681b ldr r3, [r3, #0] + 8004090: 021b lsls r3, r3, #8 + 8004092: 68fa ldr r2, [r7, #12] + 8004094: 4313 orrs r3, r2 + 8004096: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + 8004098: 697b ldr r3, [r7, #20] + 800409a: f023 0320 bic.w r3, r3, #32 + 800409e: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + 80040a0: 683b ldr r3, [r7, #0] + 80040a2: 689b ldr r3, [r3, #8] + 80040a4: 011b lsls r3, r3, #4 + 80040a6: 697a ldr r2, [r7, #20] + 80040a8: 4313 orrs r3, r2 + 80040aa: 617b str r3, [r7, #20] + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + 80040ac: 687b ldr r3, [r7, #4] + 80040ae: 4a23 ldr r2, [pc, #140] ; (800413c ) + 80040b0: 4293 cmp r3, r2 + 80040b2: d003 beq.n 80040bc + 80040b4: 687b ldr r3, [r7, #4] + 80040b6: 4a22 ldr r2, [pc, #136] ; (8004140 ) + 80040b8: 4293 cmp r3, r2 + 80040ba: d10d bne.n 80040d8 + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + 80040bc: 697b ldr r3, [r7, #20] + 80040be: f023 0380 bic.w r3, r3, #128 ; 0x80 + 80040c2: 617b str r3, [r7, #20] + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + 80040c4: 683b ldr r3, [r7, #0] + 80040c6: 68db ldr r3, [r3, #12] + 80040c8: 011b lsls r3, r3, #4 + 80040ca: 697a ldr r2, [r7, #20] + 80040cc: 4313 orrs r3, r2 + 80040ce: 617b str r3, [r7, #20] + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + 80040d0: 697b ldr r3, [r7, #20] + 80040d2: f023 0340 bic.w r3, r3, #64 ; 0x40 + 80040d6: 617b str r3, [r7, #20] + + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 80040d8: 687b ldr r3, [r7, #4] + 80040da: 4a18 ldr r2, [pc, #96] ; (800413c ) + 80040dc: 4293 cmp r3, r2 + 80040de: d003 beq.n 80040e8 + 80040e0: 687b ldr r3, [r7, #4] + 80040e2: 4a17 ldr r2, [pc, #92] ; (8004140 ) + 80040e4: 4293 cmp r3, r2 + 80040e6: d113 bne.n 8004110 + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + 80040e8: 693b ldr r3, [r7, #16] + 80040ea: f423 6380 bic.w r3, r3, #1024 ; 0x400 + 80040ee: 613b str r3, [r7, #16] + tmpcr2 &= ~TIM_CR2_OIS2N; + 80040f0: 693b ldr r3, [r7, #16] + 80040f2: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 80040f6: 613b str r3, [r7, #16] + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + 80040f8: 683b ldr r3, [r7, #0] + 80040fa: 695b ldr r3, [r3, #20] + 80040fc: 009b lsls r3, r3, #2 + 80040fe: 693a ldr r2, [r7, #16] + 8004100: 4313 orrs r3, r2 + 8004102: 613b str r3, [r7, #16] + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + 8004104: 683b ldr r3, [r7, #0] + 8004106: 699b ldr r3, [r3, #24] + 8004108: 009b lsls r3, r3, #2 + 800410a: 693a ldr r2, [r7, #16] + 800410c: 4313 orrs r3, r2 + 800410e: 613b str r3, [r7, #16] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8004110: 687b ldr r3, [r7, #4] + 8004112: 693a ldr r2, [r7, #16] + 8004114: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8004116: 687b ldr r3, [r7, #4] + 8004118: 68fa ldr r2, [r7, #12] + 800411a: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + 800411c: 683b ldr r3, [r7, #0] + 800411e: 685a ldr r2, [r3, #4] + 8004120: 687b ldr r3, [r7, #4] + 8004122: 639a str r2, [r3, #56] ; 0x38 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8004124: 687b ldr r3, [r7, #4] + 8004126: 697a ldr r2, [r7, #20] + 8004128: 621a str r2, [r3, #32] +} + 800412a: bf00 nop + 800412c: 371c adds r7, #28 + 800412e: 46bd mov sp, r7 + 8004130: f85d 7b04 ldr.w r7, [sp], #4 + 8004134: 4770 bx lr + 8004136: bf00 nop + 8004138: feff8fff .word 0xfeff8fff + 800413c: 40010000 .word 0x40010000 + 8004140: 40010400 .word 0x40010400 + +08004144 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 8004144: b480 push {r7} + 8004146: b087 sub sp, #28 + 8004148: af00 add r7, sp, #0 + 800414a: 6078 str r0, [r7, #4] + 800414c: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + 800414e: 687b ldr r3, [r7, #4] + 8004150: 6a1b ldr r3, [r3, #32] + 8004152: f423 7280 bic.w r2, r3, #256 ; 0x100 + 8004156: 687b ldr r3, [r7, #4] + 8004158: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 800415a: 687b ldr r3, [r7, #4] + 800415c: 6a1b ldr r3, [r3, #32] + 800415e: 617b str r3, [r7, #20] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8004160: 687b ldr r3, [r7, #4] + 8004162: 685b ldr r3, [r3, #4] + 8004164: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 8004166: 687b ldr r3, [r7, #4] + 8004168: 69db ldr r3, [r3, #28] + 800416a: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + 800416c: 68fa ldr r2, [r7, #12] + 800416e: 4b2d ldr r3, [pc, #180] ; (8004224 ) + 8004170: 4013 ands r3, r2 + 8004172: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC3S; + 8004174: 68fb ldr r3, [r7, #12] + 8004176: f023 0303 bic.w r3, r3, #3 + 800417a: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 800417c: 683b ldr r3, [r7, #0] + 800417e: 681b ldr r3, [r3, #0] + 8004180: 68fa ldr r2, [r7, #12] + 8004182: 4313 orrs r3, r2 + 8004184: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + 8004186: 697b ldr r3, [r7, #20] + 8004188: f423 7300 bic.w r3, r3, #512 ; 0x200 + 800418c: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + 800418e: 683b ldr r3, [r7, #0] + 8004190: 689b ldr r3, [r3, #8] + 8004192: 021b lsls r3, r3, #8 + 8004194: 697a ldr r2, [r7, #20] + 8004196: 4313 orrs r3, r2 + 8004198: 617b str r3, [r7, #20] + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + 800419a: 687b ldr r3, [r7, #4] + 800419c: 4a22 ldr r2, [pc, #136] ; (8004228 ) + 800419e: 4293 cmp r3, r2 + 80041a0: d003 beq.n 80041aa + 80041a2: 687b ldr r3, [r7, #4] + 80041a4: 4a21 ldr r2, [pc, #132] ; (800422c ) + 80041a6: 4293 cmp r3, r2 + 80041a8: d10d bne.n 80041c6 + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + 80041aa: 697b ldr r3, [r7, #20] + 80041ac: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 80041b0: 617b str r3, [r7, #20] + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + 80041b2: 683b ldr r3, [r7, #0] + 80041b4: 68db ldr r3, [r3, #12] + 80041b6: 021b lsls r3, r3, #8 + 80041b8: 697a ldr r2, [r7, #20] + 80041ba: 4313 orrs r3, r2 + 80041bc: 617b str r3, [r7, #20] + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + 80041be: 697b ldr r3, [r7, #20] + 80041c0: f423 6380 bic.w r3, r3, #1024 ; 0x400 + 80041c4: 617b str r3, [r7, #20] + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 80041c6: 687b ldr r3, [r7, #4] + 80041c8: 4a17 ldr r2, [pc, #92] ; (8004228 ) + 80041ca: 4293 cmp r3, r2 + 80041cc: d003 beq.n 80041d6 + 80041ce: 687b ldr r3, [r7, #4] + 80041d0: 4a16 ldr r2, [pc, #88] ; (800422c ) + 80041d2: 4293 cmp r3, r2 + 80041d4: d113 bne.n 80041fe + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + 80041d6: 693b ldr r3, [r7, #16] + 80041d8: f423 5380 bic.w r3, r3, #4096 ; 0x1000 + 80041dc: 613b str r3, [r7, #16] + tmpcr2 &= ~TIM_CR2_OIS3N; + 80041de: 693b ldr r3, [r7, #16] + 80041e0: f423 5300 bic.w r3, r3, #8192 ; 0x2000 + 80041e4: 613b str r3, [r7, #16] + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + 80041e6: 683b ldr r3, [r7, #0] + 80041e8: 695b ldr r3, [r3, #20] + 80041ea: 011b lsls r3, r3, #4 + 80041ec: 693a ldr r2, [r7, #16] + 80041ee: 4313 orrs r3, r2 + 80041f0: 613b str r3, [r7, #16] + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + 80041f2: 683b ldr r3, [r7, #0] + 80041f4: 699b ldr r3, [r3, #24] + 80041f6: 011b lsls r3, r3, #4 + 80041f8: 693a ldr r2, [r7, #16] + 80041fa: 4313 orrs r3, r2 + 80041fc: 613b str r3, [r7, #16] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 80041fe: 687b ldr r3, [r7, #4] + 8004200: 693a ldr r2, [r7, #16] + 8004202: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 8004204: 687b ldr r3, [r7, #4] + 8004206: 68fa ldr r2, [r7, #12] + 8004208: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + 800420a: 683b ldr r3, [r7, #0] + 800420c: 685a ldr r2, [r3, #4] + 800420e: 687b ldr r3, [r7, #4] + 8004210: 63da str r2, [r3, #60] ; 0x3c + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8004212: 687b ldr r3, [r7, #4] + 8004214: 697a ldr r2, [r7, #20] + 8004216: 621a str r2, [r3, #32] +} + 8004218: bf00 nop + 800421a: 371c adds r7, #28 + 800421c: 46bd mov sp, r7 + 800421e: f85d 7b04 ldr.w r7, [sp], #4 + 8004222: 4770 bx lr + 8004224: fffeff8f .word 0xfffeff8f + 8004228: 40010000 .word 0x40010000 + 800422c: 40010400 .word 0x40010400 + +08004230 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 8004230: b480 push {r7} + 8004232: b087 sub sp, #28 + 8004234: af00 add r7, sp, #0 + 8004236: 6078 str r0, [r7, #4] + 8004238: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + 800423a: 687b ldr r3, [r7, #4] + 800423c: 6a1b ldr r3, [r3, #32] + 800423e: f423 5280 bic.w r2, r3, #4096 ; 0x1000 + 8004242: 687b ldr r3, [r7, #4] + 8004244: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8004246: 687b ldr r3, [r7, #4] + 8004248: 6a1b ldr r3, [r3, #32] + 800424a: 613b str r3, [r7, #16] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 800424c: 687b ldr r3, [r7, #4] + 800424e: 685b ldr r3, [r3, #4] + 8004250: 617b str r3, [r7, #20] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 8004252: 687b ldr r3, [r7, #4] + 8004254: 69db ldr r3, [r3, #28] + 8004256: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + 8004258: 68fa ldr r2, [r7, #12] + 800425a: 4b1e ldr r3, [pc, #120] ; (80042d4 ) + 800425c: 4013 ands r3, r2 + 800425e: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC4S; + 8004260: 68fb ldr r3, [r7, #12] + 8004262: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8004266: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 8004268: 683b ldr r3, [r7, #0] + 800426a: 681b ldr r3, [r3, #0] + 800426c: 021b lsls r3, r3, #8 + 800426e: 68fa ldr r2, [r7, #12] + 8004270: 4313 orrs r3, r2 + 8004272: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + 8004274: 693b ldr r3, [r7, #16] + 8004276: f423 5300 bic.w r3, r3, #8192 ; 0x2000 + 800427a: 613b str r3, [r7, #16] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + 800427c: 683b ldr r3, [r7, #0] + 800427e: 689b ldr r3, [r3, #8] + 8004280: 031b lsls r3, r3, #12 + 8004282: 693a ldr r2, [r7, #16] + 8004284: 4313 orrs r3, r2 + 8004286: 613b str r3, [r7, #16] + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 8004288: 687b ldr r3, [r7, #4] + 800428a: 4a13 ldr r2, [pc, #76] ; (80042d8 ) + 800428c: 4293 cmp r3, r2 + 800428e: d003 beq.n 8004298 + 8004290: 687b ldr r3, [r7, #4] + 8004292: 4a12 ldr r2, [pc, #72] ; (80042dc ) + 8004294: 4293 cmp r3, r2 + 8004296: d109 bne.n 80042ac + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + 8004298: 697b ldr r3, [r7, #20] + 800429a: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 800429e: 617b str r3, [r7, #20] + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + 80042a0: 683b ldr r3, [r7, #0] + 80042a2: 695b ldr r3, [r3, #20] + 80042a4: 019b lsls r3, r3, #6 + 80042a6: 697a ldr r2, [r7, #20] + 80042a8: 4313 orrs r3, r2 + 80042aa: 617b str r3, [r7, #20] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 80042ac: 687b ldr r3, [r7, #4] + 80042ae: 697a ldr r2, [r7, #20] + 80042b0: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 80042b2: 687b ldr r3, [r7, #4] + 80042b4: 68fa ldr r2, [r7, #12] + 80042b6: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + 80042b8: 683b ldr r3, [r7, #0] + 80042ba: 685a ldr r2, [r3, #4] + 80042bc: 687b ldr r3, [r7, #4] + 80042be: 641a str r2, [r3, #64] ; 0x40 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 80042c0: 687b ldr r3, [r7, #4] + 80042c2: 693a ldr r2, [r7, #16] + 80042c4: 621a str r2, [r3, #32] +} + 80042c6: bf00 nop + 80042c8: 371c adds r7, #28 + 80042ca: 46bd mov sp, r7 + 80042cc: f85d 7b04 ldr.w r7, [sp], #4 + 80042d0: 4770 bx lr + 80042d2: bf00 nop + 80042d4: feff8fff .word 0xfeff8fff + 80042d8: 40010000 .word 0x40010000 + 80042dc: 40010400 .word 0x40010400 + +080042e0 : + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, + TIM_OC_InitTypeDef *OC_Config) +{ + 80042e0: b480 push {r7} + 80042e2: b087 sub sp, #28 + 80042e4: af00 add r7, sp, #0 + 80042e6: 6078 str r0, [r7, #4] + 80042e8: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC5E; + 80042ea: 687b ldr r3, [r7, #4] + 80042ec: 6a1b ldr r3, [r3, #32] + 80042ee: f423 3280 bic.w r2, r3, #65536 ; 0x10000 + 80042f2: 687b ldr r3, [r7, #4] + 80042f4: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 80042f6: 687b ldr r3, [r7, #4] + 80042f8: 6a1b ldr r3, [r3, #32] + 80042fa: 613b str r3, [r7, #16] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 80042fc: 687b ldr r3, [r7, #4] + 80042fe: 685b ldr r3, [r3, #4] + 8004300: 617b str r3, [r7, #20] + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + 8004302: 687b ldr r3, [r7, #4] + 8004304: 6d5b ldr r3, [r3, #84] ; 0x54 + 8004306: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC5M); + 8004308: 68fa ldr r2, [r7, #12] + 800430a: 4b1b ldr r3, [pc, #108] ; (8004378 ) + 800430c: 4013 ands r3, r2 + 800430e: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 8004310: 683b ldr r3, [r7, #0] + 8004312: 681b ldr r3, [r3, #0] + 8004314: 68fa ldr r2, [r7, #12] + 8004316: 4313 orrs r3, r2 + 8004318: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC5P; + 800431a: 693b ldr r3, [r7, #16] + 800431c: f423 3300 bic.w r3, r3, #131072 ; 0x20000 + 8004320: 613b str r3, [r7, #16] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 16U); + 8004322: 683b ldr r3, [r7, #0] + 8004324: 689b ldr r3, [r3, #8] + 8004326: 041b lsls r3, r3, #16 + 8004328: 693a ldr r2, [r7, #16] + 800432a: 4313 orrs r3, r2 + 800432c: 613b str r3, [r7, #16] + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 800432e: 687b ldr r3, [r7, #4] + 8004330: 4a12 ldr r2, [pc, #72] ; (800437c ) + 8004332: 4293 cmp r3, r2 + 8004334: d003 beq.n 800433e + 8004336: 687b ldr r3, [r7, #4] + 8004338: 4a11 ldr r2, [pc, #68] ; (8004380 ) + 800433a: 4293 cmp r3, r2 + 800433c: d109 bne.n 8004352 + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS5; + 800433e: 697b ldr r3, [r7, #20] + 8004340: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8004344: 617b str r3, [r7, #20] + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 8U); + 8004346: 683b ldr r3, [r7, #0] + 8004348: 695b ldr r3, [r3, #20] + 800434a: 021b lsls r3, r3, #8 + 800434c: 697a ldr r2, [r7, #20] + 800434e: 4313 orrs r3, r2 + 8004350: 617b str r3, [r7, #20] + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8004352: 687b ldr r3, [r7, #4] + 8004354: 697a ldr r2, [r7, #20] + 8004356: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + 8004358: 687b ldr r3, [r7, #4] + 800435a: 68fa ldr r2, [r7, #12] + 800435c: 655a str r2, [r3, #84] ; 0x54 + + /* Set the Capture Compare Register value */ + TIMx->CCR5 = OC_Config->Pulse; + 800435e: 683b ldr r3, [r7, #0] + 8004360: 685a ldr r2, [r3, #4] + 8004362: 687b ldr r3, [r7, #4] + 8004364: 659a str r2, [r3, #88] ; 0x58 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8004366: 687b ldr r3, [r7, #4] + 8004368: 693a ldr r2, [r7, #16] + 800436a: 621a str r2, [r3, #32] +} + 800436c: bf00 nop + 800436e: 371c adds r7, #28 + 8004370: 46bd mov sp, r7 + 8004372: f85d 7b04 ldr.w r7, [sp], #4 + 8004376: 4770 bx lr + 8004378: fffeff8f .word 0xfffeff8f + 800437c: 40010000 .word 0x40010000 + 8004380: 40010400 .word 0x40010400 + +08004384 : + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, + TIM_OC_InitTypeDef *OC_Config) +{ + 8004384: b480 push {r7} + 8004386: b087 sub sp, #28 + 8004388: af00 add r7, sp, #0 + 800438a: 6078 str r0, [r7, #4] + 800438c: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC6E; + 800438e: 687b ldr r3, [r7, #4] + 8004390: 6a1b ldr r3, [r3, #32] + 8004392: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 + 8004396: 687b ldr r3, [r7, #4] + 8004398: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 800439a: 687b ldr r3, [r7, #4] + 800439c: 6a1b ldr r3, [r3, #32] + 800439e: 613b str r3, [r7, #16] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 80043a0: 687b ldr r3, [r7, #4] + 80043a2: 685b ldr r3, [r3, #4] + 80043a4: 617b str r3, [r7, #20] + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + 80043a6: 687b ldr r3, [r7, #4] + 80043a8: 6d5b ldr r3, [r3, #84] ; 0x54 + 80043aa: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC6M); + 80043ac: 68fa ldr r2, [r7, #12] + 80043ae: 4b1c ldr r3, [pc, #112] ; (8004420 ) + 80043b0: 4013 ands r3, r2 + 80043b2: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 80043b4: 683b ldr r3, [r7, #0] + 80043b6: 681b ldr r3, [r3, #0] + 80043b8: 021b lsls r3, r3, #8 + 80043ba: 68fa ldr r2, [r7, #12] + 80043bc: 4313 orrs r3, r2 + 80043be: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)~TIM_CCER_CC6P; + 80043c0: 693b ldr r3, [r7, #16] + 80043c2: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 + 80043c6: 613b str r3, [r7, #16] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 20U); + 80043c8: 683b ldr r3, [r7, #0] + 80043ca: 689b ldr r3, [r3, #8] + 80043cc: 051b lsls r3, r3, #20 + 80043ce: 693a ldr r2, [r7, #16] + 80043d0: 4313 orrs r3, r2 + 80043d2: 613b str r3, [r7, #16] + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 80043d4: 687b ldr r3, [r7, #4] + 80043d6: 4a13 ldr r2, [pc, #76] ; (8004424 ) + 80043d8: 4293 cmp r3, r2 + 80043da: d003 beq.n 80043e4 + 80043dc: 687b ldr r3, [r7, #4] + 80043de: 4a12 ldr r2, [pc, #72] ; (8004428 ) + 80043e0: 4293 cmp r3, r2 + 80043e2: d109 bne.n 80043f8 + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS6; + 80043e4: 697b ldr r3, [r7, #20] + 80043e6: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 80043ea: 617b str r3, [r7, #20] + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 10U); + 80043ec: 683b ldr r3, [r7, #0] + 80043ee: 695b ldr r3, [r3, #20] + 80043f0: 029b lsls r3, r3, #10 + 80043f2: 697a ldr r2, [r7, #20] + 80043f4: 4313 orrs r3, r2 + 80043f6: 617b str r3, [r7, #20] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 80043f8: 687b ldr r3, [r7, #4] + 80043fa: 697a ldr r2, [r7, #20] + 80043fc: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + 80043fe: 687b ldr r3, [r7, #4] + 8004400: 68fa ldr r2, [r7, #12] + 8004402: 655a str r2, [r3, #84] ; 0x54 + + /* Set the Capture Compare Register value */ + TIMx->CCR6 = OC_Config->Pulse; + 8004404: 683b ldr r3, [r7, #0] + 8004406: 685a ldr r2, [r3, #4] + 8004408: 687b ldr r3, [r7, #4] + 800440a: 65da str r2, [r3, #92] ; 0x5c + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 800440c: 687b ldr r3, [r7, #4] + 800440e: 693a ldr r2, [r7, #16] + 8004410: 621a str r2, [r3, #32] +} + 8004412: bf00 nop + 8004414: 371c adds r7, #28 + 8004416: 46bd mov sp, r7 + 8004418: f85d 7b04 ldr.w r7, [sp], #4 + 800441c: 4770 bx lr + 800441e: bf00 nop + 8004420: feff8fff .word 0xfeff8fff + 8004424: 40010000 .word 0x40010000 + 8004428: 40010400 .word 0x40010400 + +0800442c : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 800442c: b480 push {r7} + 800442e: b087 sub sp, #28 + 8004430: af00 add r7, sp, #0 + 8004432: 60f8 str r0, [r7, #12] + 8004434: 60b9 str r1, [r7, #8] + 8004436: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + 8004438: 68fb ldr r3, [r7, #12] + 800443a: 6a1b ldr r3, [r3, #32] + 800443c: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC1E; + 800443e: 68fb ldr r3, [r7, #12] + 8004440: 6a1b ldr r3, [r3, #32] + 8004442: f023 0201 bic.w r2, r3, #1 + 8004446: 68fb ldr r3, [r7, #12] + 8004448: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 800444a: 68fb ldr r3, [r7, #12] + 800444c: 699b ldr r3, [r3, #24] + 800444e: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + 8004450: 693b ldr r3, [r7, #16] + 8004452: f023 03f0 bic.w r3, r3, #240 ; 0xf0 + 8004456: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 4U); + 8004458: 687b ldr r3, [r7, #4] + 800445a: 011b lsls r3, r3, #4 + 800445c: 693a ldr r2, [r7, #16] + 800445e: 4313 orrs r3, r2 + 8004460: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + 8004462: 697b ldr r3, [r7, #20] + 8004464: f023 030a bic.w r3, r3, #10 + 8004468: 617b str r3, [r7, #20] + tmpccer |= TIM_ICPolarity; + 800446a: 697a ldr r2, [r7, #20] + 800446c: 68bb ldr r3, [r7, #8] + 800446e: 4313 orrs r3, r2 + 8004470: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + 8004472: 68fb ldr r3, [r7, #12] + 8004474: 693a ldr r2, [r7, #16] + 8004476: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 8004478: 68fb ldr r3, [r7, #12] + 800447a: 697a ldr r2, [r7, #20] + 800447c: 621a str r2, [r3, #32] +} + 800447e: bf00 nop + 8004480: 371c adds r7, #28 + 8004482: 46bd mov sp, r7 + 8004484: f85d 7b04 ldr.w r7, [sp], #4 + 8004488: 4770 bx lr + +0800448a : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 800448a: b480 push {r7} + 800448c: b087 sub sp, #28 + 800448e: af00 add r7, sp, #0 + 8004490: 60f8 str r0, [r7, #12] + 8004492: 60b9 str r1, [r7, #8] + 8004494: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + 8004496: 68fb ldr r3, [r7, #12] + 8004498: 6a1b ldr r3, [r3, #32] + 800449a: f023 0210 bic.w r2, r3, #16 + 800449e: 68fb ldr r3, [r7, #12] + 80044a0: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 80044a2: 68fb ldr r3, [r7, #12] + 80044a4: 699b ldr r3, [r3, #24] + 80044a6: 617b str r3, [r7, #20] + tmpccer = TIMx->CCER; + 80044a8: 68fb ldr r3, [r7, #12] + 80044aa: 6a1b ldr r3, [r3, #32] + 80044ac: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + 80044ae: 697b ldr r3, [r7, #20] + 80044b0: f423 4370 bic.w r3, r3, #61440 ; 0xf000 + 80044b4: 617b str r3, [r7, #20] + tmpccmr1 |= (TIM_ICFilter << 12U); + 80044b6: 687b ldr r3, [r7, #4] + 80044b8: 031b lsls r3, r3, #12 + 80044ba: 697a ldr r2, [r7, #20] + 80044bc: 4313 orrs r3, r2 + 80044be: 617b str r3, [r7, #20] + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + 80044c0: 693b ldr r3, [r7, #16] + 80044c2: f023 03a0 bic.w r3, r3, #160 ; 0xa0 + 80044c6: 613b str r3, [r7, #16] + tmpccer |= (TIM_ICPolarity << 4U); + 80044c8: 68bb ldr r3, [r7, #8] + 80044ca: 011b lsls r3, r3, #4 + 80044cc: 693a ldr r2, [r7, #16] + 80044ce: 4313 orrs r3, r2 + 80044d0: 613b str r3, [r7, #16] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + 80044d2: 68fb ldr r3, [r7, #12] + 80044d4: 697a ldr r2, [r7, #20] + 80044d6: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 80044d8: 68fb ldr r3, [r7, #12] + 80044da: 693a ldr r2, [r7, #16] + 80044dc: 621a str r2, [r3, #32] +} + 80044de: bf00 nop + 80044e0: 371c adds r7, #28 + 80044e2: 46bd mov sp, r7 + 80044e4: f85d 7b04 ldr.w r7, [sp], #4 + 80044e8: 4770 bx lr + +080044ea : + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + 80044ea: b480 push {r7} + 80044ec: b085 sub sp, #20 + 80044ee: af00 add r7, sp, #0 + 80044f0: 6078 str r0, [r7, #4] + 80044f2: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + 80044f4: 687b ldr r3, [r7, #4] + 80044f6: 689b ldr r3, [r3, #8] + 80044f8: 60fb str r3, [r7, #12] + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + 80044fa: 68fb ldr r3, [r7, #12] + 80044fc: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004500: 60fb str r3, [r7, #12] + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + 8004502: 683a ldr r2, [r7, #0] + 8004504: 68fb ldr r3, [r7, #12] + 8004506: 4313 orrs r3, r2 + 8004508: f043 0307 orr.w r3, r3, #7 + 800450c: 60fb str r3, [r7, #12] + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 800450e: 687b ldr r3, [r7, #4] + 8004510: 68fa ldr r2, [r7, #12] + 8004512: 609a str r2, [r3, #8] +} + 8004514: bf00 nop + 8004516: 3714 adds r7, #20 + 8004518: 46bd mov sp, r7 + 800451a: f85d 7b04 ldr.w r7, [sp], #4 + 800451e: 4770 bx lr + +08004520 : + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + 8004520: b480 push {r7} + 8004522: b087 sub sp, #28 + 8004524: af00 add r7, sp, #0 + 8004526: 60f8 str r0, [r7, #12] + 8004528: 60b9 str r1, [r7, #8] + 800452a: 607a str r2, [r7, #4] + 800452c: 603b str r3, [r7, #0] + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + 800452e: 68fb ldr r3, [r7, #12] + 8004530: 689b ldr r3, [r3, #8] + 8004532: 617b str r3, [r7, #20] + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 8004534: 697b ldr r3, [r7, #20] + 8004536: f423 437f bic.w r3, r3, #65280 ; 0xff00 + 800453a: 617b str r3, [r7, #20] + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + 800453c: 683b ldr r3, [r7, #0] + 800453e: 021a lsls r2, r3, #8 + 8004540: 687b ldr r3, [r7, #4] + 8004542: 431a orrs r2, r3 + 8004544: 68bb ldr r3, [r7, #8] + 8004546: 4313 orrs r3, r2 + 8004548: 697a ldr r2, [r7, #20] + 800454a: 4313 orrs r3, r2 + 800454c: 617b str r3, [r7, #20] + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 800454e: 68fb ldr r3, [r7, #12] + 8004550: 697a ldr r2, [r7, #20] + 8004552: 609a str r2, [r3, #8] +} + 8004554: bf00 nop + 8004556: 371c adds r7, #28 + 8004558: 46bd mov sp, r7 + 800455a: f85d 7b04 ldr.w r7, [sp], #4 + 800455e: 4770 bx lr + +08004560 : + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + 8004560: b480 push {r7} + 8004562: b087 sub sp, #28 + 8004564: af00 add r7, sp, #0 + 8004566: 60f8 str r0, [r7, #12] + 8004568: 60b9 str r1, [r7, #8] + 800456a: 607a str r2, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + 800456c: 68bb ldr r3, [r7, #8] + 800456e: f003 031f and.w r3, r3, #31 + 8004572: 2201 movs r2, #1 + 8004574: fa02 f303 lsl.w r3, r2, r3 + 8004578: 617b str r3, [r7, #20] + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + 800457a: 68fb ldr r3, [r7, #12] + 800457c: 6a1a ldr r2, [r3, #32] + 800457e: 697b ldr r3, [r7, #20] + 8004580: 43db mvns r3, r3 + 8004582: 401a ands r2, r3 + 8004584: 68fb ldr r3, [r7, #12] + 8004586: 621a str r2, [r3, #32] + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + 8004588: 68fb ldr r3, [r7, #12] + 800458a: 6a1a ldr r2, [r3, #32] + 800458c: 68bb ldr r3, [r7, #8] + 800458e: f003 031f and.w r3, r3, #31 + 8004592: 6879 ldr r1, [r7, #4] + 8004594: fa01 f303 lsl.w r3, r1, r3 + 8004598: 431a orrs r2, r3 + 800459a: 68fb ldr r3, [r7, #12] + 800459c: 621a str r2, [r3, #32] +} + 800459e: bf00 nop + 80045a0: 371c adds r7, #28 + 80045a2: 46bd mov sp, r7 + 80045a4: f85d 7b04 ldr.w r7, [sp], #4 + 80045a8: 4770 bx lr + ... + +080045ac : + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig) +{ + 80045ac: b480 push {r7} + 80045ae: b085 sub sp, #20 + 80045b0: af00 add r7, sp, #0 + 80045b2: 6078 str r0, [r7, #4] + 80045b4: 6039 str r1, [r7, #0] + assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + 80045b6: 687b ldr r3, [r7, #4] + 80045b8: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 80045bc: 2b01 cmp r3, #1 + 80045be: d101 bne.n 80045c4 + 80045c0: 2302 movs r3, #2 + 80045c2: e045 b.n 8004650 + 80045c4: 687b ldr r3, [r7, #4] + 80045c6: 2201 movs r2, #1 + 80045c8: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + 80045cc: 687b ldr r3, [r7, #4] + 80045ce: 2202 movs r2, #2 + 80045d0: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + 80045d4: 687b ldr r3, [r7, #4] + 80045d6: 681b ldr r3, [r3, #0] + 80045d8: 685b ldr r3, [r3, #4] + 80045da: 60fb str r3, [r7, #12] + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 80045dc: 687b ldr r3, [r7, #4] + 80045de: 681b ldr r3, [r3, #0] + 80045e0: 689b ldr r3, [r3, #8] + 80045e2: 60bb str r3, [r7, #8] + + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) + 80045e4: 687b ldr r3, [r7, #4] + 80045e6: 681b ldr r3, [r3, #0] + 80045e8: 4a1c ldr r2, [pc, #112] ; (800465c ) + 80045ea: 4293 cmp r3, r2 + 80045ec: d004 beq.n 80045f8 + 80045ee: 687b ldr r3, [r7, #4] + 80045f0: 681b ldr r3, [r3, #0] + 80045f2: 4a1b ldr r2, [pc, #108] ; (8004660 ) + 80045f4: 4293 cmp r3, r2 + 80045f6: d108 bne.n 800460a + { + /* Check the parameters */ + assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); + + /* Clear the MMS2 bits */ + tmpcr2 &= ~TIM_CR2_MMS2; + 80045f8: 68fb ldr r3, [r7, #12] + 80045fa: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000 + 80045fe: 60fb str r3, [r7, #12] + /* Select the TRGO2 source*/ + tmpcr2 |= sMasterConfig->MasterOutputTrigger2; + 8004600: 683b ldr r3, [r7, #0] + 8004602: 685b ldr r3, [r3, #4] + 8004604: 68fa ldr r2, [r7, #12] + 8004606: 4313 orrs r3, r2 + 8004608: 60fb str r3, [r7, #12] + } + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + 800460a: 68fb ldr r3, [r7, #12] + 800460c: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004610: 60fb str r3, [r7, #12] + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + 8004612: 683b ldr r3, [r7, #0] + 8004614: 681b ldr r3, [r3, #0] + 8004616: 68fa ldr r2, [r7, #12] + 8004618: 4313 orrs r3, r2 + 800461a: 60fb str r3, [r7, #12] + + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + 800461c: 68bb ldr r3, [r7, #8] + 800461e: f023 0380 bic.w r3, r3, #128 ; 0x80 + 8004622: 60bb str r3, [r7, #8] + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + 8004624: 683b ldr r3, [r7, #0] + 8004626: 689b ldr r3, [r3, #8] + 8004628: 68ba ldr r2, [r7, #8] + 800462a: 4313 orrs r3, r2 + 800462c: 60bb str r3, [r7, #8] + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + 800462e: 687b ldr r3, [r7, #4] + 8004630: 681b ldr r3, [r3, #0] + 8004632: 68fa ldr r2, [r7, #12] + 8004634: 605a str r2, [r3, #4] + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8004636: 687b ldr r3, [r7, #4] + 8004638: 681b ldr r3, [r3, #0] + 800463a: 68ba ldr r2, [r7, #8] + 800463c: 609a str r2, [r3, #8] + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + 800463e: 687b ldr r3, [r7, #4] + 8004640: 2201 movs r2, #1 + 8004642: f883 203d strb.w r2, [r3, #61] ; 0x3d + + __HAL_UNLOCK(htim); + 8004646: 687b ldr r3, [r7, #4] + 8004648: 2200 movs r2, #0 + 800464a: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_OK; + 800464e: 2300 movs r3, #0 +} + 8004650: 4618 mov r0, r3 + 8004652: 3714 adds r7, #20 + 8004654: 46bd mov sp, r7 + 8004656: f85d 7b04 ldr.w r7, [sp], #4 + 800465a: 4770 bx lr + 800465c: 40010000 .word 0x40010000 + 8004660: 40010400 .word 0x40010400 + +08004664 : + * @brief Hall commutation changed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + 8004664: b480 push {r7} + 8004666: b083 sub sp, #12 + 8004668: af00 add r7, sp, #0 + 800466a: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} + 800466c: bf00 nop + 800466e: 370c adds r7, #12 + 8004670: 46bd mov sp, r7 + 8004672: f85d 7b04 ldr.w r7, [sp], #4 + 8004676: 4770 bx lr + +08004678 : + * @brief Hall Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + 8004678: b480 push {r7} + 800467a: b083 sub sp, #12 + 800467c: af00 add r7, sp, #0 + 800467e: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + 8004680: bf00 nop + 8004682: 370c adds r7, #12 + 8004684: 46bd mov sp, r7 + 8004686: f85d 7b04 ldr.w r7, [sp], #4 + 800468a: 4770 bx lr + +0800468c : + * @brief Hall Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + 800468c: b480 push {r7} + 800468e: b083 sub sp, #12 + 8004690: af00 add r7, sp, #0 + 8004692: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} + 8004694: bf00 nop + 8004696: 370c adds r7, #12 + 8004698: 46bd mov sp, r7 + 800469a: f85d 7b04 ldr.w r7, [sp], #4 + 800469e: 4770 bx lr + +080046a0 : + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + 80046a0: b580 push {r7, lr} + 80046a2: b082 sub sp, #8 + 80046a4: af00 add r7, sp, #0 + 80046a6: 6078 str r0, [r7, #4] + /* Check the UART handle allocation */ + if (huart == NULL) + 80046a8: 687b ldr r3, [r7, #4] + 80046aa: 2b00 cmp r3, #0 + 80046ac: d101 bne.n 80046b2 + { + return HAL_ERROR; + 80046ae: 2301 movs r3, #1 + 80046b0: e040 b.n 8004734 + { + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + + if (huart->gState == HAL_UART_STATE_RESET) + 80046b2: 687b ldr r3, [r7, #4] + 80046b4: 6f5b ldr r3, [r3, #116] ; 0x74 + 80046b6: 2b00 cmp r3, #0 + 80046b8: d106 bne.n 80046c8 + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + 80046ba: 687b ldr r3, [r7, #4] + 80046bc: 2200 movs r2, #0 + 80046be: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); + 80046c2: 6878 ldr r0, [r7, #4] + 80046c4: f7fd fa38 bl 8001b38 +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + 80046c8: 687b ldr r3, [r7, #4] + 80046ca: 2224 movs r2, #36 ; 0x24 + 80046cc: 675a str r2, [r3, #116] ; 0x74 + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + 80046ce: 687b ldr r3, [r7, #4] + 80046d0: 681b ldr r3, [r3, #0] + 80046d2: 681a ldr r2, [r3, #0] + 80046d4: 687b ldr r3, [r7, #4] + 80046d6: 681b ldr r3, [r3, #0] + 80046d8: f022 0201 bic.w r2, r2, #1 + 80046dc: 601a str r2, [r3, #0] + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + 80046de: 6878 ldr r0, [r7, #4] + 80046e0: f000 fa90 bl 8004c04 + 80046e4: 4603 mov r3, r0 + 80046e6: 2b01 cmp r3, #1 + 80046e8: d101 bne.n 80046ee + { + return HAL_ERROR; + 80046ea: 2301 movs r3, #1 + 80046ec: e022 b.n 8004734 + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 80046ee: 687b ldr r3, [r7, #4] + 80046f0: 6a5b ldr r3, [r3, #36] ; 0x24 + 80046f2: 2b00 cmp r3, #0 + 80046f4: d002 beq.n 80046fc + { + UART_AdvFeatureConfig(huart); + 80046f6: 6878 ldr r0, [r7, #4] + 80046f8: f000 fd28 bl 800514c + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 80046fc: 687b ldr r3, [r7, #4] + 80046fe: 681b ldr r3, [r3, #0] + 8004700: 685a ldr r2, [r3, #4] + 8004702: 687b ldr r3, [r7, #4] + 8004704: 681b ldr r3, [r3, #0] + 8004706: f422 4290 bic.w r2, r2, #18432 ; 0x4800 + 800470a: 605a str r2, [r3, #4] + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 800470c: 687b ldr r3, [r7, #4] + 800470e: 681b ldr r3, [r3, #0] + 8004710: 689a ldr r2, [r3, #8] + 8004712: 687b ldr r3, [r7, #4] + 8004714: 681b ldr r3, [r3, #0] + 8004716: f022 022a bic.w r2, r2, #42 ; 0x2a + 800471a: 609a str r2, [r3, #8] + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + 800471c: 687b ldr r3, [r7, #4] + 800471e: 681b ldr r3, [r3, #0] + 8004720: 681a ldr r2, [r3, #0] + 8004722: 687b ldr r3, [r7, #4] + 8004724: 681b ldr r3, [r3, #0] + 8004726: f042 0201 orr.w r2, r2, #1 + 800472a: 601a str r2, [r3, #0] + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); + 800472c: 6878 ldr r0, [r7, #4] + 800472e: f000 fdaf bl 8005290 + 8004732: 4603 mov r3, r0 +} + 8004734: 4618 mov r0, r3 + 8004736: 3708 adds r7, #8 + 8004738: 46bd mov sp, r7 + 800473a: bd80 pop {r7, pc} + +0800473c : + * @param Size Amount of data to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 800473c: b580 push {r7, lr} + 800473e: b08a sub sp, #40 ; 0x28 + 8004740: af02 add r7, sp, #8 + 8004742: 60f8 str r0, [r7, #12] + 8004744: 60b9 str r1, [r7, #8] + 8004746: 603b str r3, [r7, #0] + 8004748: 4613 mov r3, r2 + 800474a: 80fb strh r3, [r7, #6] + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + 800474c: 68fb ldr r3, [r7, #12] + 800474e: 6f5b ldr r3, [r3, #116] ; 0x74 + 8004750: 2b20 cmp r3, #32 + 8004752: d17f bne.n 8004854 + { + if ((pData == NULL) || (Size == 0U)) + 8004754: 68bb ldr r3, [r7, #8] + 8004756: 2b00 cmp r3, #0 + 8004758: d002 beq.n 8004760 + 800475a: 88fb ldrh r3, [r7, #6] + 800475c: 2b00 cmp r3, #0 + 800475e: d101 bne.n 8004764 + { + return HAL_ERROR; + 8004760: 2301 movs r3, #1 + 8004762: e078 b.n 8004856 + } + + /* Process Locked */ + __HAL_LOCK(huart); + 8004764: 68fb ldr r3, [r7, #12] + 8004766: f893 3070 ldrb.w r3, [r3, #112] ; 0x70 + 800476a: 2b01 cmp r3, #1 + 800476c: d101 bne.n 8004772 + 800476e: 2302 movs r3, #2 + 8004770: e071 b.n 8004856 + 8004772: 68fb ldr r3, [r7, #12] + 8004774: 2201 movs r2, #1 + 8004776: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 800477a: 68fb ldr r3, [r7, #12] + 800477c: 2200 movs r2, #0 + 800477e: 67da str r2, [r3, #124] ; 0x7c + huart->gState = HAL_UART_STATE_BUSY_TX; + 8004780: 68fb ldr r3, [r7, #12] + 8004782: 2221 movs r2, #33 ; 0x21 + 8004784: 675a str r2, [r3, #116] ; 0x74 + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + 8004786: f7fd fb1f bl 8001dc8 + 800478a: 6178 str r0, [r7, #20] + + huart->TxXferSize = Size; + 800478c: 68fb ldr r3, [r7, #12] + 800478e: 88fa ldrh r2, [r7, #6] + 8004790: f8a3 2050 strh.w r2, [r3, #80] ; 0x50 + huart->TxXferCount = Size; + 8004794: 68fb ldr r3, [r7, #12] + 8004796: 88fa ldrh r2, [r7, #6] + 8004798: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 800479c: 68fb ldr r3, [r7, #12] + 800479e: 689b ldr r3, [r3, #8] + 80047a0: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 80047a4: d108 bne.n 80047b8 + 80047a6: 68fb ldr r3, [r7, #12] + 80047a8: 691b ldr r3, [r3, #16] + 80047aa: 2b00 cmp r3, #0 + 80047ac: d104 bne.n 80047b8 + { + pdata8bits = NULL; + 80047ae: 2300 movs r3, #0 + 80047b0: 61fb str r3, [r7, #28] + pdata16bits = (uint16_t *) pData; + 80047b2: 68bb ldr r3, [r7, #8] + 80047b4: 61bb str r3, [r7, #24] + 80047b6: e003 b.n 80047c0 + } + else + { + pdata8bits = pData; + 80047b8: 68bb ldr r3, [r7, #8] + 80047ba: 61fb str r3, [r7, #28] + pdata16bits = NULL; + 80047bc: 2300 movs r3, #0 + 80047be: 61bb str r3, [r7, #24] + } + + while (huart->TxXferCount > 0U) + 80047c0: e02c b.n 800481c + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + 80047c2: 683b ldr r3, [r7, #0] + 80047c4: 9300 str r3, [sp, #0] + 80047c6: 697b ldr r3, [r7, #20] + 80047c8: 2200 movs r2, #0 + 80047ca: 2180 movs r1, #128 ; 0x80 + 80047cc: 68f8 ldr r0, [r7, #12] + 80047ce: f000 fd8e bl 80052ee + 80047d2: 4603 mov r3, r0 + 80047d4: 2b00 cmp r3, #0 + 80047d6: d001 beq.n 80047dc + { + return HAL_TIMEOUT; + 80047d8: 2303 movs r3, #3 + 80047da: e03c b.n 8004856 + } + if (pdata8bits == NULL) + 80047dc: 69fb ldr r3, [r7, #28] + 80047de: 2b00 cmp r3, #0 + 80047e0: d10b bne.n 80047fa + { + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + 80047e2: 69bb ldr r3, [r7, #24] + 80047e4: 881b ldrh r3, [r3, #0] + 80047e6: 461a mov r2, r3 + 80047e8: 68fb ldr r3, [r7, #12] + 80047ea: 681b ldr r3, [r3, #0] + 80047ec: f3c2 0208 ubfx r2, r2, #0, #9 + 80047f0: 629a str r2, [r3, #40] ; 0x28 + pdata16bits++; + 80047f2: 69bb ldr r3, [r7, #24] + 80047f4: 3302 adds r3, #2 + 80047f6: 61bb str r3, [r7, #24] + 80047f8: e007 b.n 800480a + } + else + { + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + 80047fa: 69fb ldr r3, [r7, #28] + 80047fc: 781a ldrb r2, [r3, #0] + 80047fe: 68fb ldr r3, [r7, #12] + 8004800: 681b ldr r3, [r3, #0] + 8004802: 629a str r2, [r3, #40] ; 0x28 + pdata8bits++; + 8004804: 69fb ldr r3, [r7, #28] + 8004806: 3301 adds r3, #1 + 8004808: 61fb str r3, [r7, #28] + } + huart->TxXferCount--; + 800480a: 68fb ldr r3, [r7, #12] + 800480c: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 + 8004810: b29b uxth r3, r3 + 8004812: 3b01 subs r3, #1 + 8004814: b29a uxth r2, r3 + 8004816: 68fb ldr r3, [r7, #12] + 8004818: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 + while (huart->TxXferCount > 0U) + 800481c: 68fb ldr r3, [r7, #12] + 800481e: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 + 8004822: b29b uxth r3, r3 + 8004824: 2b00 cmp r3, #0 + 8004826: d1cc bne.n 80047c2 + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + 8004828: 683b ldr r3, [r7, #0] + 800482a: 9300 str r3, [sp, #0] + 800482c: 697b ldr r3, [r7, #20] + 800482e: 2200 movs r2, #0 + 8004830: 2140 movs r1, #64 ; 0x40 + 8004832: 68f8 ldr r0, [r7, #12] + 8004834: f000 fd5b bl 80052ee + 8004838: 4603 mov r3, r0 + 800483a: 2b00 cmp r3, #0 + 800483c: d001 beq.n 8004842 + { + return HAL_TIMEOUT; + 800483e: 2303 movs r3, #3 + 8004840: e009 b.n 8004856 + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 8004842: 68fb ldr r3, [r7, #12] + 8004844: 2220 movs r2, #32 + 8004846: 675a str r2, [r3, #116] ; 0x74 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8004848: 68fb ldr r3, [r7, #12] + 800484a: 2200 movs r2, #0 + 800484c: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + return HAL_OK; + 8004850: 2300 movs r3, #0 + 8004852: e000 b.n 8004856 + } + else + { + return HAL_BUSY; + 8004854: 2302 movs r3, #2 + } +} + 8004856: 4618 mov r0, r3 + 8004858: 3720 adds r7, #32 + 800485a: 46bd mov sp, r7 + 800485c: bd80 pop {r7, pc} + ... + +08004860 : + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + 8004860: b480 push {r7} + 8004862: b085 sub sp, #20 + 8004864: af00 add r7, sp, #0 + 8004866: 60f8 str r0, [r7, #12] + 8004868: 60b9 str r1, [r7, #8] + 800486a: 4613 mov r3, r2 + 800486c: 80fb strh r3, [r7, #6] + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + 800486e: 68fb ldr r3, [r7, #12] + 8004870: 6f9b ldr r3, [r3, #120] ; 0x78 + 8004872: 2b20 cmp r3, #32 + 8004874: f040 808a bne.w 800498c + { + if ((pData == NULL) || (Size == 0U)) + 8004878: 68bb ldr r3, [r7, #8] + 800487a: 2b00 cmp r3, #0 + 800487c: d002 beq.n 8004884 + 800487e: 88fb ldrh r3, [r7, #6] + 8004880: 2b00 cmp r3, #0 + 8004882: d101 bne.n 8004888 + { + return HAL_ERROR; + 8004884: 2301 movs r3, #1 + 8004886: e082 b.n 800498e + } + + /* Process Locked */ + __HAL_LOCK(huart); + 8004888: 68fb ldr r3, [r7, #12] + 800488a: f893 3070 ldrb.w r3, [r3, #112] ; 0x70 + 800488e: 2b01 cmp r3, #1 + 8004890: d101 bne.n 8004896 + 8004892: 2302 movs r3, #2 + 8004894: e07b b.n 800498e + 8004896: 68fb ldr r3, [r7, #12] + 8004898: 2201 movs r2, #1 + 800489a: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + huart->pRxBuffPtr = pData; + 800489e: 68fb ldr r3, [r7, #12] + 80048a0: 68ba ldr r2, [r7, #8] + 80048a2: 655a str r2, [r3, #84] ; 0x54 + huart->RxXferSize = Size; + 80048a4: 68fb ldr r3, [r7, #12] + 80048a6: 88fa ldrh r2, [r7, #6] + 80048a8: f8a3 2058 strh.w r2, [r3, #88] ; 0x58 + huart->RxXferCount = Size; + 80048ac: 68fb ldr r3, [r7, #12] + 80048ae: 88fa ldrh r2, [r7, #6] + 80048b0: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + huart->RxISR = NULL; + 80048b4: 68fb ldr r3, [r7, #12] + 80048b6: 2200 movs r2, #0 + 80048b8: 661a str r2, [r3, #96] ; 0x60 + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + 80048ba: 68fb ldr r3, [r7, #12] + 80048bc: 689b ldr r3, [r3, #8] + 80048be: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 80048c2: d10e bne.n 80048e2 + 80048c4: 68fb ldr r3, [r7, #12] + 80048c6: 691b ldr r3, [r3, #16] + 80048c8: 2b00 cmp r3, #0 + 80048ca: d105 bne.n 80048d8 + 80048cc: 68fb ldr r3, [r7, #12] + 80048ce: f240 12ff movw r2, #511 ; 0x1ff + 80048d2: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 80048d6: e02d b.n 8004934 + 80048d8: 68fb ldr r3, [r7, #12] + 80048da: 22ff movs r2, #255 ; 0xff + 80048dc: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 80048e0: e028 b.n 8004934 + 80048e2: 68fb ldr r3, [r7, #12] + 80048e4: 689b ldr r3, [r3, #8] + 80048e6: 2b00 cmp r3, #0 + 80048e8: d10d bne.n 8004906 + 80048ea: 68fb ldr r3, [r7, #12] + 80048ec: 691b ldr r3, [r3, #16] + 80048ee: 2b00 cmp r3, #0 + 80048f0: d104 bne.n 80048fc + 80048f2: 68fb ldr r3, [r7, #12] + 80048f4: 22ff movs r2, #255 ; 0xff + 80048f6: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 80048fa: e01b b.n 8004934 + 80048fc: 68fb ldr r3, [r7, #12] + 80048fe: 227f movs r2, #127 ; 0x7f + 8004900: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8004904: e016 b.n 8004934 + 8004906: 68fb ldr r3, [r7, #12] + 8004908: 689b ldr r3, [r3, #8] + 800490a: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 + 800490e: d10d bne.n 800492c + 8004910: 68fb ldr r3, [r7, #12] + 8004912: 691b ldr r3, [r3, #16] + 8004914: 2b00 cmp r3, #0 + 8004916: d104 bne.n 8004922 + 8004918: 68fb ldr r3, [r7, #12] + 800491a: 227f movs r2, #127 ; 0x7f + 800491c: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8004920: e008 b.n 8004934 + 8004922: 68fb ldr r3, [r7, #12] + 8004924: 223f movs r2, #63 ; 0x3f + 8004926: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 800492a: e003 b.n 8004934 + 800492c: 68fb ldr r3, [r7, #12] + 800492e: 2200 movs r2, #0 + 8004930: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8004934: 68fb ldr r3, [r7, #12] + 8004936: 2200 movs r2, #0 + 8004938: 67da str r2, [r3, #124] ; 0x7c + huart->RxState = HAL_UART_STATE_BUSY_RX; + 800493a: 68fb ldr r3, [r7, #12] + 800493c: 2222 movs r2, #34 ; 0x22 + 800493e: 679a str r2, [r3, #120] ; 0x78 + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8004940: 68fb ldr r3, [r7, #12] + 8004942: 681b ldr r3, [r3, #0] + 8004944: 689a ldr r2, [r3, #8] + 8004946: 68fb ldr r3, [r7, #12] + 8004948: 681b ldr r3, [r3, #0] + 800494a: f042 0201 orr.w r2, r2, #1 + 800494e: 609a str r2, [r3, #8] + + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 8004950: 68fb ldr r3, [r7, #12] + 8004952: 689b ldr r3, [r3, #8] + 8004954: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8004958: d107 bne.n 800496a + 800495a: 68fb ldr r3, [r7, #12] + 800495c: 691b ldr r3, [r3, #16] + 800495e: 2b00 cmp r3, #0 + 8004960: d103 bne.n 800496a + { + huart->RxISR = UART_RxISR_16BIT; + 8004962: 68fb ldr r3, [r7, #12] + 8004964: 4a0d ldr r2, [pc, #52] ; (800499c ) + 8004966: 661a str r2, [r3, #96] ; 0x60 + 8004968: e002 b.n 8004970 + } + else + { + huart->RxISR = UART_RxISR_8BIT; + 800496a: 68fb ldr r3, [r7, #12] + 800496c: 4a0c ldr r2, [pc, #48] ; (80049a0 ) + 800496e: 661a str r2, [r3, #96] ; 0x60 + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8004970: 68fb ldr r3, [r7, #12] + 8004972: 2200 movs r2, #0 + 8004974: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + 8004978: 68fb ldr r3, [r7, #12] + 800497a: 681b ldr r3, [r3, #0] + 800497c: 681a ldr r2, [r3, #0] + 800497e: 68fb ldr r3, [r7, #12] + 8004980: 681b ldr r3, [r3, #0] + 8004982: f442 7290 orr.w r2, r2, #288 ; 0x120 + 8004986: 601a str r2, [r3, #0] + + return HAL_OK; + 8004988: 2300 movs r3, #0 + 800498a: e000 b.n 800498e + } + else + { + return HAL_BUSY; + 800498c: 2302 movs r3, #2 + } +} + 800498e: 4618 mov r0, r3 + 8004990: 3714 adds r7, #20 + 8004992: 46bd mov sp, r7 + 8004994: f85d 7b04 ldr.w r7, [sp], #4 + 8004998: 4770 bx lr + 800499a: bf00 nop + 800499c: 080054c3 .word 0x080054c3 + 80049a0: 0800541d .word 0x0800541d + +080049a4 : + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + 80049a4: b580 push {r7, lr} + 80049a6: b088 sub sp, #32 + 80049a8: af00 add r7, sp, #0 + 80049aa: 6078 str r0, [r7, #4] + uint32_t isrflags = READ_REG(huart->Instance->ISR); + 80049ac: 687b ldr r3, [r7, #4] + 80049ae: 681b ldr r3, [r3, #0] + 80049b0: 69db ldr r3, [r3, #28] + 80049b2: 61fb str r3, [r7, #28] + uint32_t cr1its = READ_REG(huart->Instance->CR1); + 80049b4: 687b ldr r3, [r7, #4] + 80049b6: 681b ldr r3, [r3, #0] + 80049b8: 681b ldr r3, [r3, #0] + 80049ba: 61bb str r3, [r7, #24] + uint32_t cr3its = READ_REG(huart->Instance->CR3); + 80049bc: 687b ldr r3, [r7, #4] + 80049be: 681b ldr r3, [r3, #0] + 80049c0: 689b ldr r3, [r3, #8] + 80049c2: 617b str r3, [r7, #20] + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + 80049c4: 69fb ldr r3, [r7, #28] + 80049c6: f003 030f and.w r3, r3, #15 + 80049ca: 613b str r3, [r7, #16] + if (errorflags == 0U) + 80049cc: 693b ldr r3, [r7, #16] + 80049ce: 2b00 cmp r3, #0 + 80049d0: d113 bne.n 80049fa + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE) != 0U) + 80049d2: 69fb ldr r3, [r7, #28] + 80049d4: f003 0320 and.w r3, r3, #32 + 80049d8: 2b00 cmp r3, #0 + 80049da: d00e beq.n 80049fa + && ((cr1its & USART_CR1_RXNEIE) != 0U)) + 80049dc: 69bb ldr r3, [r7, #24] + 80049de: f003 0320 and.w r3, r3, #32 + 80049e2: 2b00 cmp r3, #0 + 80049e4: d009 beq.n 80049fa + { + if (huart->RxISR != NULL) + 80049e6: 687b ldr r3, [r7, #4] + 80049e8: 6e1b ldr r3, [r3, #96] ; 0x60 + 80049ea: 2b00 cmp r3, #0 + 80049ec: f000 80eb beq.w 8004bc6 + { + huart->RxISR(huart); + 80049f0: 687b ldr r3, [r7, #4] + 80049f2: 6e1b ldr r3, [r3, #96] ; 0x60 + 80049f4: 6878 ldr r0, [r7, #4] + 80049f6: 4798 blx r3 + } + return; + 80049f8: e0e5 b.n 8004bc6 + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + 80049fa: 693b ldr r3, [r7, #16] + 80049fc: 2b00 cmp r3, #0 + 80049fe: f000 80c0 beq.w 8004b82 + && (((cr3its & USART_CR3_EIE) != 0U) + 8004a02: 697b ldr r3, [r7, #20] + 8004a04: f003 0301 and.w r3, r3, #1 + 8004a08: 2b00 cmp r3, #0 + 8004a0a: d105 bne.n 8004a18 + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U))) + 8004a0c: 69bb ldr r3, [r7, #24] + 8004a0e: f403 7390 and.w r3, r3, #288 ; 0x120 + 8004a12: 2b00 cmp r3, #0 + 8004a14: f000 80b5 beq.w 8004b82 + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + 8004a18: 69fb ldr r3, [r7, #28] + 8004a1a: f003 0301 and.w r3, r3, #1 + 8004a1e: 2b00 cmp r3, #0 + 8004a20: d00e beq.n 8004a40 + 8004a22: 69bb ldr r3, [r7, #24] + 8004a24: f403 7380 and.w r3, r3, #256 ; 0x100 + 8004a28: 2b00 cmp r3, #0 + 8004a2a: d009 beq.n 8004a40 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + 8004a2c: 687b ldr r3, [r7, #4] + 8004a2e: 681b ldr r3, [r3, #0] + 8004a30: 2201 movs r2, #1 + 8004a32: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_PE; + 8004a34: 687b ldr r3, [r7, #4] + 8004a36: 6fdb ldr r3, [r3, #124] ; 0x7c + 8004a38: f043 0201 orr.w r2, r3, #1 + 8004a3c: 687b ldr r3, [r7, #4] + 8004a3e: 67da str r2, [r3, #124] ; 0x7c + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8004a40: 69fb ldr r3, [r7, #28] + 8004a42: f003 0302 and.w r3, r3, #2 + 8004a46: 2b00 cmp r3, #0 + 8004a48: d00e beq.n 8004a68 + 8004a4a: 697b ldr r3, [r7, #20] + 8004a4c: f003 0301 and.w r3, r3, #1 + 8004a50: 2b00 cmp r3, #0 + 8004a52: d009 beq.n 8004a68 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + 8004a54: 687b ldr r3, [r7, #4] + 8004a56: 681b ldr r3, [r3, #0] + 8004a58: 2202 movs r2, #2 + 8004a5a: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_FE; + 8004a5c: 687b ldr r3, [r7, #4] + 8004a5e: 6fdb ldr r3, [r3, #124] ; 0x7c + 8004a60: f043 0204 orr.w r2, r3, #4 + 8004a64: 687b ldr r3, [r7, #4] + 8004a66: 67da str r2, [r3, #124] ; 0x7c + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8004a68: 69fb ldr r3, [r7, #28] + 8004a6a: f003 0304 and.w r3, r3, #4 + 8004a6e: 2b00 cmp r3, #0 + 8004a70: d00e beq.n 8004a90 + 8004a72: 697b ldr r3, [r7, #20] + 8004a74: f003 0301 and.w r3, r3, #1 + 8004a78: 2b00 cmp r3, #0 + 8004a7a: d009 beq.n 8004a90 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + 8004a7c: 687b ldr r3, [r7, #4] + 8004a7e: 681b ldr r3, [r3, #0] + 8004a80: 2204 movs r2, #4 + 8004a82: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_NE; + 8004a84: 687b ldr r3, [r7, #4] + 8004a86: 6fdb ldr r3, [r3, #124] ; 0x7c + 8004a88: f043 0202 orr.w r2, r3, #2 + 8004a8c: 687b ldr r3, [r7, #4] + 8004a8e: 67da str r2, [r3, #124] ; 0x7c + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + 8004a90: 69fb ldr r3, [r7, #28] + 8004a92: f003 0308 and.w r3, r3, #8 + 8004a96: 2b00 cmp r3, #0 + 8004a98: d013 beq.n 8004ac2 + && (((cr1its & USART_CR1_RXNEIE) != 0U) || + 8004a9a: 69bb ldr r3, [r7, #24] + 8004a9c: f003 0320 and.w r3, r3, #32 + 8004aa0: 2b00 cmp r3, #0 + 8004aa2: d104 bne.n 8004aae + ((cr3its & USART_CR3_EIE) != 0U))) + 8004aa4: 697b ldr r3, [r7, #20] + 8004aa6: f003 0301 and.w r3, r3, #1 + && (((cr1its & USART_CR1_RXNEIE) != 0U) || + 8004aaa: 2b00 cmp r3, #0 + 8004aac: d009 beq.n 8004ac2 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + 8004aae: 687b ldr r3, [r7, #4] + 8004ab0: 681b ldr r3, [r3, #0] + 8004ab2: 2208 movs r2, #8 + 8004ab4: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + 8004ab6: 687b ldr r3, [r7, #4] + 8004ab8: 6fdb ldr r3, [r3, #124] ; 0x7c + 8004aba: f043 0208 orr.w r2, r3, #8 + 8004abe: 687b ldr r3, [r7, #4] + 8004ac0: 67da str r2, [r3, #124] ; 0x7c + } + + /* Call UART Error Call back function if need be --------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + 8004ac2: 687b ldr r3, [r7, #4] + 8004ac4: 6fdb ldr r3, [r3, #124] ; 0x7c + 8004ac6: 2b00 cmp r3, #0 + 8004ac8: d07f beq.n 8004bca + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE) != 0U) + 8004aca: 69fb ldr r3, [r7, #28] + 8004acc: f003 0320 and.w r3, r3, #32 + 8004ad0: 2b00 cmp r3, #0 + 8004ad2: d00c beq.n 8004aee + && ((cr1its & USART_CR1_RXNEIE) != 0U)) + 8004ad4: 69bb ldr r3, [r7, #24] + 8004ad6: f003 0320 and.w r3, r3, #32 + 8004ada: 2b00 cmp r3, #0 + 8004adc: d007 beq.n 8004aee + { + if (huart->RxISR != NULL) + 8004ade: 687b ldr r3, [r7, #4] + 8004ae0: 6e1b ldr r3, [r3, #96] ; 0x60 + 8004ae2: 2b00 cmp r3, #0 + 8004ae4: d003 beq.n 8004aee + { + huart->RxISR(huart); + 8004ae6: 687b ldr r3, [r7, #4] + 8004ae8: 6e1b ldr r3, [r3, #96] ; 0x60 + 8004aea: 6878 ldr r0, [r7, #4] + 8004aec: 4798 blx r3 + } + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + errorcode = huart->ErrorCode; + 8004aee: 687b ldr r3, [r7, #4] + 8004af0: 6fdb ldr r3, [r3, #124] ; 0x7c + 8004af2: 60fb str r3, [r7, #12] + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + 8004af4: 687b ldr r3, [r7, #4] + 8004af6: 681b ldr r3, [r3, #0] + 8004af8: 689b ldr r3, [r3, #8] + 8004afa: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004afe: 2b40 cmp r3, #64 ; 0x40 + 8004b00: d004 beq.n 8004b0c + ((errorcode & HAL_UART_ERROR_ORE) != 0U)) + 8004b02: 68fb ldr r3, [r7, #12] + 8004b04: f003 0308 and.w r3, r3, #8 + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + 8004b08: 2b00 cmp r3, #0 + 8004b0a: d031 beq.n 8004b70 + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + 8004b0c: 6878 ldr r0, [r7, #4] + 8004b0e: f000 fc36 bl 800537e + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8004b12: 687b ldr r3, [r7, #4] + 8004b14: 681b ldr r3, [r3, #0] + 8004b16: 689b ldr r3, [r3, #8] + 8004b18: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004b1c: 2b40 cmp r3, #64 ; 0x40 + 8004b1e: d123 bne.n 8004b68 + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 8004b20: 687b ldr r3, [r7, #4] + 8004b22: 681b ldr r3, [r3, #0] + 8004b24: 689a ldr r2, [r3, #8] + 8004b26: 687b ldr r3, [r7, #4] + 8004b28: 681b ldr r3, [r3, #0] + 8004b2a: f022 0240 bic.w r2, r2, #64 ; 0x40 + 8004b2e: 609a str r2, [r3, #8] + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + 8004b30: 687b ldr r3, [r7, #4] + 8004b32: 6edb ldr r3, [r3, #108] ; 0x6c + 8004b34: 2b00 cmp r3, #0 + 8004b36: d013 beq.n 8004b60 + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + 8004b38: 687b ldr r3, [r7, #4] + 8004b3a: 6edb ldr r3, [r3, #108] ; 0x6c + 8004b3c: 4a26 ldr r2, [pc, #152] ; (8004bd8 ) + 8004b3e: 651a str r2, [r3, #80] ; 0x50 + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + 8004b40: 687b ldr r3, [r7, #4] + 8004b42: 6edb ldr r3, [r3, #108] ; 0x6c + 8004b44: 4618 mov r0, r3 + 8004b46: f7fd fa5c bl 8002002 + 8004b4a: 4603 mov r3, r0 + 8004b4c: 2b00 cmp r3, #0 + 8004b4e: d016 beq.n 8004b7e + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + 8004b50: 687b ldr r3, [r7, #4] + 8004b52: 6edb ldr r3, [r3, #108] ; 0x6c + 8004b54: 6d1b ldr r3, [r3, #80] ; 0x50 + 8004b56: 687a ldr r2, [r7, #4] + 8004b58: 6ed2 ldr r2, [r2, #108] ; 0x6c + 8004b5a: 4610 mov r0, r2 + 8004b5c: 4798 blx r3 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8004b5e: e00e b.n 8004b7e +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8004b60: 6878 ldr r0, [r7, #4] + 8004b62: f000 f845 bl 8004bf0 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8004b66: e00a b.n 8004b7e +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8004b68: 6878 ldr r0, [r7, #4] + 8004b6a: f000 f841 bl 8004bf0 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8004b6e: e006 b.n 8004b7e +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8004b70: 6878 ldr r0, [r7, #4] + 8004b72: f000 f83d bl 8004bf0 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8004b76: 687b ldr r3, [r7, #4] + 8004b78: 2200 movs r2, #0 + 8004b7a: 67da str r2, [r3, #124] ; 0x7c + } + } + return; + 8004b7c: e025 b.n 8004bca + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8004b7e: bf00 nop + return; + 8004b80: e023 b.n 8004bca + + } /* End if some error occurs */ + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE) != 0U) + 8004b82: 69fb ldr r3, [r7, #28] + 8004b84: f003 0380 and.w r3, r3, #128 ; 0x80 + 8004b88: 2b00 cmp r3, #0 + 8004b8a: d00d beq.n 8004ba8 + && ((cr1its & USART_CR1_TXEIE) != 0U)) + 8004b8c: 69bb ldr r3, [r7, #24] + 8004b8e: f003 0380 and.w r3, r3, #128 ; 0x80 + 8004b92: 2b00 cmp r3, #0 + 8004b94: d008 beq.n 8004ba8 + { + if (huart->TxISR != NULL) + 8004b96: 687b ldr r3, [r7, #4] + 8004b98: 6e5b ldr r3, [r3, #100] ; 0x64 + 8004b9a: 2b00 cmp r3, #0 + 8004b9c: d017 beq.n 8004bce + { + huart->TxISR(huart); + 8004b9e: 687b ldr r3, [r7, #4] + 8004ba0: 6e5b ldr r3, [r3, #100] ; 0x64 + 8004ba2: 6878 ldr r0, [r7, #4] + 8004ba4: 4798 blx r3 + } + return; + 8004ba6: e012 b.n 8004bce + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + 8004ba8: 69fb ldr r3, [r7, #28] + 8004baa: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004bae: 2b00 cmp r3, #0 + 8004bb0: d00e beq.n 8004bd0 + 8004bb2: 69bb ldr r3, [r7, #24] + 8004bb4: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004bb8: 2b00 cmp r3, #0 + 8004bba: d009 beq.n 8004bd0 + { + UART_EndTransmit_IT(huart); + 8004bbc: 6878 ldr r0, [r7, #4] + 8004bbe: f000 fc14 bl 80053ea + return; + 8004bc2: bf00 nop + 8004bc4: e004 b.n 8004bd0 + return; + 8004bc6: bf00 nop + 8004bc8: e002 b.n 8004bd0 + return; + 8004bca: bf00 nop + 8004bcc: e000 b.n 8004bd0 + return; + 8004bce: bf00 nop + } + +} + 8004bd0: 3720 adds r7, #32 + 8004bd2: 46bd mov sp, r7 + 8004bd4: bd80 pop {r7, pc} + 8004bd6: bf00 nop + 8004bd8: 080053bf .word 0x080053bf + +08004bdc : + * @brief Tx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + 8004bdc: b480 push {r7} + 8004bde: b083 sub sp, #12 + 8004be0: af00 add r7, sp, #0 + 8004be2: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file. + */ +} + 8004be4: bf00 nop + 8004be6: 370c adds r7, #12 + 8004be8: 46bd mov sp, r7 + 8004bea: f85d 7b04 ldr.w r7, [sp], #4 + 8004bee: 4770 bx lr + +08004bf0 : + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + 8004bf0: b480 push {r7} + 8004bf2: b083 sub sp, #12 + 8004bf4: af00 add r7, sp, #0 + 8004bf6: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + 8004bf8: bf00 nop + 8004bfa: 370c adds r7, #12 + 8004bfc: 46bd mov sp, r7 + 8004bfe: f85d 7b04 ldr.w r7, [sp], #4 + 8004c02: 4770 bx lr + +08004c04 : + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + 8004c04: b580 push {r7, lr} + 8004c06: b088 sub sp, #32 + 8004c08: af00 add r7, sp, #0 + 8004c0a: 6078 str r0, [r7, #4] + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv = 0x00000000U; + 8004c0c: 2300 movs r3, #0 + 8004c0e: 61bb str r3, [r7, #24] + HAL_StatusTypeDef ret = HAL_OK; + 8004c10: 2300 movs r3, #0 + 8004c12: 75fb strb r3, [r7, #23] + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + 8004c14: 687b ldr r3, [r7, #4] + 8004c16: 689a ldr r2, [r3, #8] + 8004c18: 687b ldr r3, [r7, #4] + 8004c1a: 691b ldr r3, [r3, #16] + 8004c1c: 431a orrs r2, r3 + 8004c1e: 687b ldr r3, [r7, #4] + 8004c20: 695b ldr r3, [r3, #20] + 8004c22: 431a orrs r2, r3 + 8004c24: 687b ldr r3, [r7, #4] + 8004c26: 69db ldr r3, [r3, #28] + 8004c28: 4313 orrs r3, r2 + 8004c2a: 613b str r3, [r7, #16] + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 8004c2c: 687b ldr r3, [r7, #4] + 8004c2e: 681b ldr r3, [r3, #0] + 8004c30: 681a ldr r2, [r3, #0] + 8004c32: 4bb1 ldr r3, [pc, #708] ; (8004ef8 ) + 8004c34: 4013 ands r3, r2 + 8004c36: 687a ldr r2, [r7, #4] + 8004c38: 6812 ldr r2, [r2, #0] + 8004c3a: 6939 ldr r1, [r7, #16] + 8004c3c: 430b orrs r3, r1 + 8004c3e: 6013 str r3, [r2, #0] + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + 8004c40: 687b ldr r3, [r7, #4] + 8004c42: 681b ldr r3, [r3, #0] + 8004c44: 685b ldr r3, [r3, #4] + 8004c46: f423 5140 bic.w r1, r3, #12288 ; 0x3000 + 8004c4a: 687b ldr r3, [r7, #4] + 8004c4c: 68da ldr r2, [r3, #12] + 8004c4e: 687b ldr r3, [r7, #4] + 8004c50: 681b ldr r3, [r3, #0] + 8004c52: 430a orrs r2, r1 + 8004c54: 605a str r2, [r3, #4] + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + 8004c56: 687b ldr r3, [r7, #4] + 8004c58: 699b ldr r3, [r3, #24] + 8004c5a: 613b str r3, [r7, #16] + + tmpreg |= huart->Init.OneBitSampling; + 8004c5c: 687b ldr r3, [r7, #4] + 8004c5e: 6a1b ldr r3, [r3, #32] + 8004c60: 693a ldr r2, [r7, #16] + 8004c62: 4313 orrs r3, r2 + 8004c64: 613b str r3, [r7, #16] + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + 8004c66: 687b ldr r3, [r7, #4] + 8004c68: 681b ldr r3, [r3, #0] + 8004c6a: 689b ldr r3, [r3, #8] + 8004c6c: f423 6130 bic.w r1, r3, #2816 ; 0xb00 + 8004c70: 687b ldr r3, [r7, #4] + 8004c72: 681b ldr r3, [r3, #0] + 8004c74: 693a ldr r2, [r7, #16] + 8004c76: 430a orrs r2, r1 + 8004c78: 609a str r2, [r3, #8] + + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + 8004c7a: 687b ldr r3, [r7, #4] + 8004c7c: 681b ldr r3, [r3, #0] + 8004c7e: 4a9f ldr r2, [pc, #636] ; (8004efc ) + 8004c80: 4293 cmp r3, r2 + 8004c82: d121 bne.n 8004cc8 + 8004c84: 4b9e ldr r3, [pc, #632] ; (8004f00 ) + 8004c86: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004c8a: f003 0303 and.w r3, r3, #3 + 8004c8e: 2b03 cmp r3, #3 + 8004c90: d816 bhi.n 8004cc0 + 8004c92: a201 add r2, pc, #4 ; (adr r2, 8004c98 ) + 8004c94: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8004c98: 08004ca9 .word 0x08004ca9 + 8004c9c: 08004cb5 .word 0x08004cb5 + 8004ca0: 08004caf .word 0x08004caf + 8004ca4: 08004cbb .word 0x08004cbb + 8004ca8: 2301 movs r3, #1 + 8004caa: 77fb strb r3, [r7, #31] + 8004cac: e151 b.n 8004f52 + 8004cae: 2302 movs r3, #2 + 8004cb0: 77fb strb r3, [r7, #31] + 8004cb2: e14e b.n 8004f52 + 8004cb4: 2304 movs r3, #4 + 8004cb6: 77fb strb r3, [r7, #31] + 8004cb8: e14b b.n 8004f52 + 8004cba: 2308 movs r3, #8 + 8004cbc: 77fb strb r3, [r7, #31] + 8004cbe: e148 b.n 8004f52 + 8004cc0: 2310 movs r3, #16 + 8004cc2: 77fb strb r3, [r7, #31] + 8004cc4: bf00 nop + 8004cc6: e144 b.n 8004f52 + 8004cc8: 687b ldr r3, [r7, #4] + 8004cca: 681b ldr r3, [r3, #0] + 8004ccc: 4a8d ldr r2, [pc, #564] ; (8004f04 ) + 8004cce: 4293 cmp r3, r2 + 8004cd0: d134 bne.n 8004d3c + 8004cd2: 4b8b ldr r3, [pc, #556] ; (8004f00 ) + 8004cd4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004cd8: f003 030c and.w r3, r3, #12 + 8004cdc: 2b0c cmp r3, #12 + 8004cde: d829 bhi.n 8004d34 + 8004ce0: a201 add r2, pc, #4 ; (adr r2, 8004ce8 ) + 8004ce2: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8004ce6: bf00 nop + 8004ce8: 08004d1d .word 0x08004d1d + 8004cec: 08004d35 .word 0x08004d35 + 8004cf0: 08004d35 .word 0x08004d35 + 8004cf4: 08004d35 .word 0x08004d35 + 8004cf8: 08004d29 .word 0x08004d29 + 8004cfc: 08004d35 .word 0x08004d35 + 8004d00: 08004d35 .word 0x08004d35 + 8004d04: 08004d35 .word 0x08004d35 + 8004d08: 08004d23 .word 0x08004d23 + 8004d0c: 08004d35 .word 0x08004d35 + 8004d10: 08004d35 .word 0x08004d35 + 8004d14: 08004d35 .word 0x08004d35 + 8004d18: 08004d2f .word 0x08004d2f + 8004d1c: 2300 movs r3, #0 + 8004d1e: 77fb strb r3, [r7, #31] + 8004d20: e117 b.n 8004f52 + 8004d22: 2302 movs r3, #2 + 8004d24: 77fb strb r3, [r7, #31] + 8004d26: e114 b.n 8004f52 + 8004d28: 2304 movs r3, #4 + 8004d2a: 77fb strb r3, [r7, #31] + 8004d2c: e111 b.n 8004f52 + 8004d2e: 2308 movs r3, #8 + 8004d30: 77fb strb r3, [r7, #31] + 8004d32: e10e b.n 8004f52 + 8004d34: 2310 movs r3, #16 + 8004d36: 77fb strb r3, [r7, #31] + 8004d38: bf00 nop + 8004d3a: e10a b.n 8004f52 + 8004d3c: 687b ldr r3, [r7, #4] + 8004d3e: 681b ldr r3, [r3, #0] + 8004d40: 4a71 ldr r2, [pc, #452] ; (8004f08 ) + 8004d42: 4293 cmp r3, r2 + 8004d44: d120 bne.n 8004d88 + 8004d46: 4b6e ldr r3, [pc, #440] ; (8004f00 ) + 8004d48: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004d4c: f003 0330 and.w r3, r3, #48 ; 0x30 + 8004d50: 2b10 cmp r3, #16 + 8004d52: d00f beq.n 8004d74 + 8004d54: 2b10 cmp r3, #16 + 8004d56: d802 bhi.n 8004d5e + 8004d58: 2b00 cmp r3, #0 + 8004d5a: d005 beq.n 8004d68 + 8004d5c: e010 b.n 8004d80 + 8004d5e: 2b20 cmp r3, #32 + 8004d60: d005 beq.n 8004d6e + 8004d62: 2b30 cmp r3, #48 ; 0x30 + 8004d64: d009 beq.n 8004d7a + 8004d66: e00b b.n 8004d80 + 8004d68: 2300 movs r3, #0 + 8004d6a: 77fb strb r3, [r7, #31] + 8004d6c: e0f1 b.n 8004f52 + 8004d6e: 2302 movs r3, #2 + 8004d70: 77fb strb r3, [r7, #31] + 8004d72: e0ee b.n 8004f52 + 8004d74: 2304 movs r3, #4 + 8004d76: 77fb strb r3, [r7, #31] + 8004d78: e0eb b.n 8004f52 + 8004d7a: 2308 movs r3, #8 + 8004d7c: 77fb strb r3, [r7, #31] + 8004d7e: e0e8 b.n 8004f52 + 8004d80: 2310 movs r3, #16 + 8004d82: 77fb strb r3, [r7, #31] + 8004d84: bf00 nop + 8004d86: e0e4 b.n 8004f52 + 8004d88: 687b ldr r3, [r7, #4] + 8004d8a: 681b ldr r3, [r3, #0] + 8004d8c: 4a5f ldr r2, [pc, #380] ; (8004f0c ) + 8004d8e: 4293 cmp r3, r2 + 8004d90: d120 bne.n 8004dd4 + 8004d92: 4b5b ldr r3, [pc, #364] ; (8004f00 ) + 8004d94: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004d98: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 8004d9c: 2b40 cmp r3, #64 ; 0x40 + 8004d9e: d00f beq.n 8004dc0 + 8004da0: 2b40 cmp r3, #64 ; 0x40 + 8004da2: d802 bhi.n 8004daa + 8004da4: 2b00 cmp r3, #0 + 8004da6: d005 beq.n 8004db4 + 8004da8: e010 b.n 8004dcc + 8004daa: 2b80 cmp r3, #128 ; 0x80 + 8004dac: d005 beq.n 8004dba + 8004dae: 2bc0 cmp r3, #192 ; 0xc0 + 8004db0: d009 beq.n 8004dc6 + 8004db2: e00b b.n 8004dcc + 8004db4: 2300 movs r3, #0 + 8004db6: 77fb strb r3, [r7, #31] + 8004db8: e0cb b.n 8004f52 + 8004dba: 2302 movs r3, #2 + 8004dbc: 77fb strb r3, [r7, #31] + 8004dbe: e0c8 b.n 8004f52 + 8004dc0: 2304 movs r3, #4 + 8004dc2: 77fb strb r3, [r7, #31] + 8004dc4: e0c5 b.n 8004f52 + 8004dc6: 2308 movs r3, #8 + 8004dc8: 77fb strb r3, [r7, #31] + 8004dca: e0c2 b.n 8004f52 + 8004dcc: 2310 movs r3, #16 + 8004dce: 77fb strb r3, [r7, #31] + 8004dd0: bf00 nop + 8004dd2: e0be b.n 8004f52 + 8004dd4: 687b ldr r3, [r7, #4] + 8004dd6: 681b ldr r3, [r3, #0] + 8004dd8: 4a4d ldr r2, [pc, #308] ; (8004f10 ) + 8004dda: 4293 cmp r3, r2 + 8004ddc: d124 bne.n 8004e28 + 8004dde: 4b48 ldr r3, [pc, #288] ; (8004f00 ) + 8004de0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004de4: f403 7340 and.w r3, r3, #768 ; 0x300 + 8004de8: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8004dec: d012 beq.n 8004e14 + 8004dee: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8004df2: d802 bhi.n 8004dfa + 8004df4: 2b00 cmp r3, #0 + 8004df6: d007 beq.n 8004e08 + 8004df8: e012 b.n 8004e20 + 8004dfa: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8004dfe: d006 beq.n 8004e0e + 8004e00: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 8004e04: d009 beq.n 8004e1a + 8004e06: e00b b.n 8004e20 + 8004e08: 2300 movs r3, #0 + 8004e0a: 77fb strb r3, [r7, #31] + 8004e0c: e0a1 b.n 8004f52 + 8004e0e: 2302 movs r3, #2 + 8004e10: 77fb strb r3, [r7, #31] + 8004e12: e09e b.n 8004f52 + 8004e14: 2304 movs r3, #4 + 8004e16: 77fb strb r3, [r7, #31] + 8004e18: e09b b.n 8004f52 + 8004e1a: 2308 movs r3, #8 + 8004e1c: 77fb strb r3, [r7, #31] + 8004e1e: e098 b.n 8004f52 + 8004e20: 2310 movs r3, #16 + 8004e22: 77fb strb r3, [r7, #31] + 8004e24: bf00 nop + 8004e26: e094 b.n 8004f52 + 8004e28: 687b ldr r3, [r7, #4] + 8004e2a: 681b ldr r3, [r3, #0] + 8004e2c: 4a39 ldr r2, [pc, #228] ; (8004f14 ) + 8004e2e: 4293 cmp r3, r2 + 8004e30: d124 bne.n 8004e7c + 8004e32: 4b33 ldr r3, [pc, #204] ; (8004f00 ) + 8004e34: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004e38: f403 6340 and.w r3, r3, #3072 ; 0xc00 + 8004e3c: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8004e40: d012 beq.n 8004e68 + 8004e42: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8004e46: d802 bhi.n 8004e4e + 8004e48: 2b00 cmp r3, #0 + 8004e4a: d007 beq.n 8004e5c + 8004e4c: e012 b.n 8004e74 + 8004e4e: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 8004e52: d006 beq.n 8004e62 + 8004e54: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 + 8004e58: d009 beq.n 8004e6e + 8004e5a: e00b b.n 8004e74 + 8004e5c: 2301 movs r3, #1 + 8004e5e: 77fb strb r3, [r7, #31] + 8004e60: e077 b.n 8004f52 + 8004e62: 2302 movs r3, #2 + 8004e64: 77fb strb r3, [r7, #31] + 8004e66: e074 b.n 8004f52 + 8004e68: 2304 movs r3, #4 + 8004e6a: 77fb strb r3, [r7, #31] + 8004e6c: e071 b.n 8004f52 + 8004e6e: 2308 movs r3, #8 + 8004e70: 77fb strb r3, [r7, #31] + 8004e72: e06e b.n 8004f52 + 8004e74: 2310 movs r3, #16 + 8004e76: 77fb strb r3, [r7, #31] + 8004e78: bf00 nop + 8004e7a: e06a b.n 8004f52 + 8004e7c: 687b ldr r3, [r7, #4] + 8004e7e: 681b ldr r3, [r3, #0] + 8004e80: 4a25 ldr r2, [pc, #148] ; (8004f18 ) + 8004e82: 4293 cmp r3, r2 + 8004e84: d124 bne.n 8004ed0 + 8004e86: 4b1e ldr r3, [pc, #120] ; (8004f00 ) + 8004e88: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004e8c: f403 5340 and.w r3, r3, #12288 ; 0x3000 + 8004e90: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8004e94: d012 beq.n 8004ebc + 8004e96: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8004e9a: d802 bhi.n 8004ea2 + 8004e9c: 2b00 cmp r3, #0 + 8004e9e: d007 beq.n 8004eb0 + 8004ea0: e012 b.n 8004ec8 + 8004ea2: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 8004ea6: d006 beq.n 8004eb6 + 8004ea8: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 + 8004eac: d009 beq.n 8004ec2 + 8004eae: e00b b.n 8004ec8 + 8004eb0: 2300 movs r3, #0 + 8004eb2: 77fb strb r3, [r7, #31] + 8004eb4: e04d b.n 8004f52 + 8004eb6: 2302 movs r3, #2 + 8004eb8: 77fb strb r3, [r7, #31] + 8004eba: e04a b.n 8004f52 + 8004ebc: 2304 movs r3, #4 + 8004ebe: 77fb strb r3, [r7, #31] + 8004ec0: e047 b.n 8004f52 + 8004ec2: 2308 movs r3, #8 + 8004ec4: 77fb strb r3, [r7, #31] + 8004ec6: e044 b.n 8004f52 + 8004ec8: 2310 movs r3, #16 + 8004eca: 77fb strb r3, [r7, #31] + 8004ecc: bf00 nop + 8004ece: e040 b.n 8004f52 + 8004ed0: 687b ldr r3, [r7, #4] + 8004ed2: 681b ldr r3, [r3, #0] + 8004ed4: 4a11 ldr r2, [pc, #68] ; (8004f1c ) + 8004ed6: 4293 cmp r3, r2 + 8004ed8: d139 bne.n 8004f4e + 8004eda: 4b09 ldr r3, [pc, #36] ; (8004f00 ) + 8004edc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004ee0: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 8004ee4: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 8004ee8: d027 beq.n 8004f3a + 8004eea: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 8004eee: d817 bhi.n 8004f20 + 8004ef0: 2b00 cmp r3, #0 + 8004ef2: d01c beq.n 8004f2e + 8004ef4: e027 b.n 8004f46 + 8004ef6: bf00 nop + 8004ef8: efff69f3 .word 0xefff69f3 + 8004efc: 40011000 .word 0x40011000 + 8004f00: 40023800 .word 0x40023800 + 8004f04: 40004400 .word 0x40004400 + 8004f08: 40004800 .word 0x40004800 + 8004f0c: 40004c00 .word 0x40004c00 + 8004f10: 40005000 .word 0x40005000 + 8004f14: 40011400 .word 0x40011400 + 8004f18: 40007800 .word 0x40007800 + 8004f1c: 40007c00 .word 0x40007c00 + 8004f20: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8004f24: d006 beq.n 8004f34 + 8004f26: f5b3 4f40 cmp.w r3, #49152 ; 0xc000 + 8004f2a: d009 beq.n 8004f40 + 8004f2c: e00b b.n 8004f46 + 8004f2e: 2300 movs r3, #0 + 8004f30: 77fb strb r3, [r7, #31] + 8004f32: e00e b.n 8004f52 + 8004f34: 2302 movs r3, #2 + 8004f36: 77fb strb r3, [r7, #31] + 8004f38: e00b b.n 8004f52 + 8004f3a: 2304 movs r3, #4 + 8004f3c: 77fb strb r3, [r7, #31] + 8004f3e: e008 b.n 8004f52 + 8004f40: 2308 movs r3, #8 + 8004f42: 77fb strb r3, [r7, #31] + 8004f44: e005 b.n 8004f52 + 8004f46: 2310 movs r3, #16 + 8004f48: 77fb strb r3, [r7, #31] + 8004f4a: bf00 nop + 8004f4c: e001 b.n 8004f52 + 8004f4e: 2310 movs r3, #16 + 8004f50: 77fb strb r3, [r7, #31] + + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + 8004f52: 687b ldr r3, [r7, #4] + 8004f54: 69db ldr r3, [r3, #28] + 8004f56: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8004f5a: d17c bne.n 8005056 + { + switch (clocksource) + 8004f5c: 7ffb ldrb r3, [r7, #31] + 8004f5e: 2b08 cmp r3, #8 + 8004f60: d859 bhi.n 8005016 + 8004f62: a201 add r2, pc, #4 ; (adr r2, 8004f68 ) + 8004f64: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8004f68: 08004f8d .word 0x08004f8d + 8004f6c: 08004fab .word 0x08004fab + 8004f70: 08004fc9 .word 0x08004fc9 + 8004f74: 08005017 .word 0x08005017 + 8004f78: 08004fe1 .word 0x08004fe1 + 8004f7c: 08005017 .word 0x08005017 + 8004f80: 08005017 .word 0x08005017 + 8004f84: 08005017 .word 0x08005017 + 8004f88: 08004fff .word 0x08004fff + { + case UART_CLOCKSOURCE_PCLK1: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + 8004f8c: f7fd fe50 bl 8002c30 + 8004f90: 4603 mov r3, r0 + 8004f92: 005a lsls r2, r3, #1 + 8004f94: 687b ldr r3, [r7, #4] + 8004f96: 685b ldr r3, [r3, #4] + 8004f98: 085b lsrs r3, r3, #1 + 8004f9a: 441a add r2, r3 + 8004f9c: 687b ldr r3, [r7, #4] + 8004f9e: 685b ldr r3, [r3, #4] + 8004fa0: fbb2 f3f3 udiv r3, r2, r3 + 8004fa4: b29b uxth r3, r3 + 8004fa6: 61bb str r3, [r7, #24] + break; + 8004fa8: e038 b.n 800501c + case UART_CLOCKSOURCE_PCLK2: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); + 8004faa: f7fd fe55 bl 8002c58 + 8004fae: 4603 mov r3, r0 + 8004fb0: 005a lsls r2, r3, #1 + 8004fb2: 687b ldr r3, [r7, #4] + 8004fb4: 685b ldr r3, [r3, #4] + 8004fb6: 085b lsrs r3, r3, #1 + 8004fb8: 441a add r2, r3 + 8004fba: 687b ldr r3, [r7, #4] + 8004fbc: 685b ldr r3, [r3, #4] + 8004fbe: fbb2 f3f3 udiv r3, r2, r3 + 8004fc2: b29b uxth r3, r3 + 8004fc4: 61bb str r3, [r7, #24] + break; + 8004fc6: e029 b.n 800501c + case UART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); + 8004fc8: 687b ldr r3, [r7, #4] + 8004fca: 685b ldr r3, [r3, #4] + 8004fcc: 085a lsrs r2, r3, #1 + 8004fce: 4b5d ldr r3, [pc, #372] ; (8005144 ) + 8004fd0: 4413 add r3, r2 + 8004fd2: 687a ldr r2, [r7, #4] + 8004fd4: 6852 ldr r2, [r2, #4] + 8004fd6: fbb3 f3f2 udiv r3, r3, r2 + 8004fda: b29b uxth r3, r3 + 8004fdc: 61bb str r3, [r7, #24] + break; + 8004fde: e01d b.n 800501c + case UART_CLOCKSOURCE_SYSCLK: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + 8004fe0: f7fd fd68 bl 8002ab4 + 8004fe4: 4603 mov r3, r0 + 8004fe6: 005a lsls r2, r3, #1 + 8004fe8: 687b ldr r3, [r7, #4] + 8004fea: 685b ldr r3, [r3, #4] + 8004fec: 085b lsrs r3, r3, #1 + 8004fee: 441a add r2, r3 + 8004ff0: 687b ldr r3, [r7, #4] + 8004ff2: 685b ldr r3, [r3, #4] + 8004ff4: fbb2 f3f3 udiv r3, r2, r3 + 8004ff8: b29b uxth r3, r3 + 8004ffa: 61bb str r3, [r7, #24] + break; + 8004ffc: e00e b.n 800501c + case UART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); + 8004ffe: 687b ldr r3, [r7, #4] + 8005000: 685b ldr r3, [r3, #4] + 8005002: 085b lsrs r3, r3, #1 + 8005004: f503 3280 add.w r2, r3, #65536 ; 0x10000 + 8005008: 687b ldr r3, [r7, #4] + 800500a: 685b ldr r3, [r3, #4] + 800500c: fbb2 f3f3 udiv r3, r2, r3 + 8005010: b29b uxth r3, r3 + 8005012: 61bb str r3, [r7, #24] + break; + 8005014: e002 b.n 800501c + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + 8005016: 2301 movs r3, #1 + 8005018: 75fb strb r3, [r7, #23] + break; + 800501a: bf00 nop + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 800501c: 69bb ldr r3, [r7, #24] + 800501e: 2b0f cmp r3, #15 + 8005020: d916 bls.n 8005050 + 8005022: 69bb ldr r3, [r7, #24] + 8005024: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8005028: d212 bcs.n 8005050 + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + 800502a: 69bb ldr r3, [r7, #24] + 800502c: b29b uxth r3, r3 + 800502e: f023 030f bic.w r3, r3, #15 + 8005032: 81fb strh r3, [r7, #14] + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + 8005034: 69bb ldr r3, [r7, #24] + 8005036: 085b lsrs r3, r3, #1 + 8005038: b29b uxth r3, r3 + 800503a: f003 0307 and.w r3, r3, #7 + 800503e: b29a uxth r2, r3 + 8005040: 89fb ldrh r3, [r7, #14] + 8005042: 4313 orrs r3, r2 + 8005044: 81fb strh r3, [r7, #14] + huart->Instance->BRR = brrtemp; + 8005046: 687b ldr r3, [r7, #4] + 8005048: 681b ldr r3, [r3, #0] + 800504a: 89fa ldrh r2, [r7, #14] + 800504c: 60da str r2, [r3, #12] + 800504e: e06e b.n 800512e + } + else + { + ret = HAL_ERROR; + 8005050: 2301 movs r3, #1 + 8005052: 75fb strb r3, [r7, #23] + 8005054: e06b b.n 800512e + } + } + else + { + switch (clocksource) + 8005056: 7ffb ldrb r3, [r7, #31] + 8005058: 2b08 cmp r3, #8 + 800505a: d857 bhi.n 800510c + 800505c: a201 add r2, pc, #4 ; (adr r2, 8005064 ) + 800505e: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8005062: bf00 nop + 8005064: 08005089 .word 0x08005089 + 8005068: 080050a5 .word 0x080050a5 + 800506c: 080050c1 .word 0x080050c1 + 8005070: 0800510d .word 0x0800510d + 8005074: 080050d9 .word 0x080050d9 + 8005078: 0800510d .word 0x0800510d + 800507c: 0800510d .word 0x0800510d + 8005080: 0800510d .word 0x0800510d + 8005084: 080050f5 .word 0x080050f5 + { + case UART_CLOCKSOURCE_PCLK1: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + 8005088: f7fd fdd2 bl 8002c30 + 800508c: 4602 mov r2, r0 + 800508e: 687b ldr r3, [r7, #4] + 8005090: 685b ldr r3, [r3, #4] + 8005092: 085b lsrs r3, r3, #1 + 8005094: 441a add r2, r3 + 8005096: 687b ldr r3, [r7, #4] + 8005098: 685b ldr r3, [r3, #4] + 800509a: fbb2 f3f3 udiv r3, r2, r3 + 800509e: b29b uxth r3, r3 + 80050a0: 61bb str r3, [r7, #24] + break; + 80050a2: e036 b.n 8005112 + case UART_CLOCKSOURCE_PCLK2: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); + 80050a4: f7fd fdd8 bl 8002c58 + 80050a8: 4602 mov r2, r0 + 80050aa: 687b ldr r3, [r7, #4] + 80050ac: 685b ldr r3, [r3, #4] + 80050ae: 085b lsrs r3, r3, #1 + 80050b0: 441a add r2, r3 + 80050b2: 687b ldr r3, [r7, #4] + 80050b4: 685b ldr r3, [r3, #4] + 80050b6: fbb2 f3f3 udiv r3, r2, r3 + 80050ba: b29b uxth r3, r3 + 80050bc: 61bb str r3, [r7, #24] + break; + 80050be: e028 b.n 8005112 + case UART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); + 80050c0: 687b ldr r3, [r7, #4] + 80050c2: 685b ldr r3, [r3, #4] + 80050c4: 085a lsrs r2, r3, #1 + 80050c6: 4b20 ldr r3, [pc, #128] ; (8005148 ) + 80050c8: 4413 add r3, r2 + 80050ca: 687a ldr r2, [r7, #4] + 80050cc: 6852 ldr r2, [r2, #4] + 80050ce: fbb3 f3f2 udiv r3, r3, r2 + 80050d2: b29b uxth r3, r3 + 80050d4: 61bb str r3, [r7, #24] + break; + 80050d6: e01c b.n 8005112 + case UART_CLOCKSOURCE_SYSCLK: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + 80050d8: f7fd fcec bl 8002ab4 + 80050dc: 4602 mov r2, r0 + 80050de: 687b ldr r3, [r7, #4] + 80050e0: 685b ldr r3, [r3, #4] + 80050e2: 085b lsrs r3, r3, #1 + 80050e4: 441a add r2, r3 + 80050e6: 687b ldr r3, [r7, #4] + 80050e8: 685b ldr r3, [r3, #4] + 80050ea: fbb2 f3f3 udiv r3, r2, r3 + 80050ee: b29b uxth r3, r3 + 80050f0: 61bb str r3, [r7, #24] + break; + 80050f2: e00e b.n 8005112 + case UART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); + 80050f4: 687b ldr r3, [r7, #4] + 80050f6: 685b ldr r3, [r3, #4] + 80050f8: 085b lsrs r3, r3, #1 + 80050fa: f503 4200 add.w r2, r3, #32768 ; 0x8000 + 80050fe: 687b ldr r3, [r7, #4] + 8005100: 685b ldr r3, [r3, #4] + 8005102: fbb2 f3f3 udiv r3, r2, r3 + 8005106: b29b uxth r3, r3 + 8005108: 61bb str r3, [r7, #24] + break; + 800510a: e002 b.n 8005112 + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + 800510c: 2301 movs r3, #1 + 800510e: 75fb strb r3, [r7, #23] + break; + 8005110: bf00 nop + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 8005112: 69bb ldr r3, [r7, #24] + 8005114: 2b0f cmp r3, #15 + 8005116: d908 bls.n 800512a + 8005118: 69bb ldr r3, [r7, #24] + 800511a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800511e: d204 bcs.n 800512a + { + huart->Instance->BRR = usartdiv; + 8005120: 687b ldr r3, [r7, #4] + 8005122: 681b ldr r3, [r3, #0] + 8005124: 69ba ldr r2, [r7, #24] + 8005126: 60da str r2, [r3, #12] + 8005128: e001 b.n 800512e + } + else + { + ret = HAL_ERROR; + 800512a: 2301 movs r3, #1 + 800512c: 75fb strb r3, [r7, #23] + } + } + + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + 800512e: 687b ldr r3, [r7, #4] + 8005130: 2200 movs r2, #0 + 8005132: 661a str r2, [r3, #96] ; 0x60 + huart->TxISR = NULL; + 8005134: 687b ldr r3, [r7, #4] + 8005136: 2200 movs r2, #0 + 8005138: 665a str r2, [r3, #100] ; 0x64 + + return ret; + 800513a: 7dfb ldrb r3, [r7, #23] +} + 800513c: 4618 mov r0, r3 + 800513e: 3720 adds r7, #32 + 8005140: 46bd mov sp, r7 + 8005142: bd80 pop {r7, pc} + 8005144: 01e84800 .word 0x01e84800 + 8005148: 00f42400 .word 0x00f42400 + +0800514c : + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + 800514c: b480 push {r7} + 800514e: b083 sub sp, #12 + 8005150: af00 add r7, sp, #0 + 8005152: 6078 str r0, [r7, #4] + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + 8005154: 687b ldr r3, [r7, #4] + 8005156: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005158: f003 0301 and.w r3, r3, #1 + 800515c: 2b00 cmp r3, #0 + 800515e: d00a beq.n 8005176 + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + 8005160: 687b ldr r3, [r7, #4] + 8005162: 681b ldr r3, [r3, #0] + 8005164: 685b ldr r3, [r3, #4] + 8005166: f423 3100 bic.w r1, r3, #131072 ; 0x20000 + 800516a: 687b ldr r3, [r7, #4] + 800516c: 6a9a ldr r2, [r3, #40] ; 0x28 + 800516e: 687b ldr r3, [r7, #4] + 8005170: 681b ldr r3, [r3, #0] + 8005172: 430a orrs r2, r1 + 8005174: 605a str r2, [r3, #4] + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + 8005176: 687b ldr r3, [r7, #4] + 8005178: 6a5b ldr r3, [r3, #36] ; 0x24 + 800517a: f003 0302 and.w r3, r3, #2 + 800517e: 2b00 cmp r3, #0 + 8005180: d00a beq.n 8005198 + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + 8005182: 687b ldr r3, [r7, #4] + 8005184: 681b ldr r3, [r3, #0] + 8005186: 685b ldr r3, [r3, #4] + 8005188: f423 3180 bic.w r1, r3, #65536 ; 0x10000 + 800518c: 687b ldr r3, [r7, #4] + 800518e: 6ada ldr r2, [r3, #44] ; 0x2c + 8005190: 687b ldr r3, [r7, #4] + 8005192: 681b ldr r3, [r3, #0] + 8005194: 430a orrs r2, r1 + 8005196: 605a str r2, [r3, #4] + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + 8005198: 687b ldr r3, [r7, #4] + 800519a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800519c: f003 0304 and.w r3, r3, #4 + 80051a0: 2b00 cmp r3, #0 + 80051a2: d00a beq.n 80051ba + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + 80051a4: 687b ldr r3, [r7, #4] + 80051a6: 681b ldr r3, [r3, #0] + 80051a8: 685b ldr r3, [r3, #4] + 80051aa: f423 2180 bic.w r1, r3, #262144 ; 0x40000 + 80051ae: 687b ldr r3, [r7, #4] + 80051b0: 6b1a ldr r2, [r3, #48] ; 0x30 + 80051b2: 687b ldr r3, [r7, #4] + 80051b4: 681b ldr r3, [r3, #0] + 80051b6: 430a orrs r2, r1 + 80051b8: 605a str r2, [r3, #4] + } + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + 80051ba: 687b ldr r3, [r7, #4] + 80051bc: 6a5b ldr r3, [r3, #36] ; 0x24 + 80051be: f003 0308 and.w r3, r3, #8 + 80051c2: 2b00 cmp r3, #0 + 80051c4: d00a beq.n 80051dc + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + 80051c6: 687b ldr r3, [r7, #4] + 80051c8: 681b ldr r3, [r3, #0] + 80051ca: 685b ldr r3, [r3, #4] + 80051cc: f423 4100 bic.w r1, r3, #32768 ; 0x8000 + 80051d0: 687b ldr r3, [r7, #4] + 80051d2: 6b5a ldr r2, [r3, #52] ; 0x34 + 80051d4: 687b ldr r3, [r7, #4] + 80051d6: 681b ldr r3, [r3, #0] + 80051d8: 430a orrs r2, r1 + 80051da: 605a str r2, [r3, #4] + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + 80051dc: 687b ldr r3, [r7, #4] + 80051de: 6a5b ldr r3, [r3, #36] ; 0x24 + 80051e0: f003 0310 and.w r3, r3, #16 + 80051e4: 2b00 cmp r3, #0 + 80051e6: d00a beq.n 80051fe + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + 80051e8: 687b ldr r3, [r7, #4] + 80051ea: 681b ldr r3, [r3, #0] + 80051ec: 689b ldr r3, [r3, #8] + 80051ee: f423 5180 bic.w r1, r3, #4096 ; 0x1000 + 80051f2: 687b ldr r3, [r7, #4] + 80051f4: 6b9a ldr r2, [r3, #56] ; 0x38 + 80051f6: 687b ldr r3, [r7, #4] + 80051f8: 681b ldr r3, [r3, #0] + 80051fa: 430a orrs r2, r1 + 80051fc: 609a str r2, [r3, #8] + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + 80051fe: 687b ldr r3, [r7, #4] + 8005200: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005202: f003 0320 and.w r3, r3, #32 + 8005206: 2b00 cmp r3, #0 + 8005208: d00a beq.n 8005220 + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + 800520a: 687b ldr r3, [r7, #4] + 800520c: 681b ldr r3, [r3, #0] + 800520e: 689b ldr r3, [r3, #8] + 8005210: f423 5100 bic.w r1, r3, #8192 ; 0x2000 + 8005214: 687b ldr r3, [r7, #4] + 8005216: 6bda ldr r2, [r3, #60] ; 0x3c + 8005218: 687b ldr r3, [r7, #4] + 800521a: 681b ldr r3, [r3, #0] + 800521c: 430a orrs r2, r1 + 800521e: 609a str r2, [r3, #8] + } + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + 8005220: 687b ldr r3, [r7, #4] + 8005222: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005224: f003 0340 and.w r3, r3, #64 ; 0x40 + 8005228: 2b00 cmp r3, #0 + 800522a: d01a beq.n 8005262 + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + 800522c: 687b ldr r3, [r7, #4] + 800522e: 681b ldr r3, [r3, #0] + 8005230: 685b ldr r3, [r3, #4] + 8005232: f423 1180 bic.w r1, r3, #1048576 ; 0x100000 + 8005236: 687b ldr r3, [r7, #4] + 8005238: 6c1a ldr r2, [r3, #64] ; 0x40 + 800523a: 687b ldr r3, [r7, #4] + 800523c: 681b ldr r3, [r3, #0] + 800523e: 430a orrs r2, r1 + 8005240: 605a str r2, [r3, #4] + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + 8005242: 687b ldr r3, [r7, #4] + 8005244: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005246: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 800524a: d10a bne.n 8005262 + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + 800524c: 687b ldr r3, [r7, #4] + 800524e: 681b ldr r3, [r3, #0] + 8005250: 685b ldr r3, [r3, #4] + 8005252: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000 + 8005256: 687b ldr r3, [r7, #4] + 8005258: 6c5a ldr r2, [r3, #68] ; 0x44 + 800525a: 687b ldr r3, [r7, #4] + 800525c: 681b ldr r3, [r3, #0] + 800525e: 430a orrs r2, r1 + 8005260: 605a str r2, [r3, #4] + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + 8005262: 687b ldr r3, [r7, #4] + 8005264: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005266: f003 0380 and.w r3, r3, #128 ; 0x80 + 800526a: 2b00 cmp r3, #0 + 800526c: d00a beq.n 8005284 + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + 800526e: 687b ldr r3, [r7, #4] + 8005270: 681b ldr r3, [r3, #0] + 8005272: 685b ldr r3, [r3, #4] + 8005274: f423 2100 bic.w r1, r3, #524288 ; 0x80000 + 8005278: 687b ldr r3, [r7, #4] + 800527a: 6c9a ldr r2, [r3, #72] ; 0x48 + 800527c: 687b ldr r3, [r7, #4] + 800527e: 681b ldr r3, [r3, #0] + 8005280: 430a orrs r2, r1 + 8005282: 605a str r2, [r3, #4] + } +} + 8005284: bf00 nop + 8005286: 370c adds r7, #12 + 8005288: 46bd mov sp, r7 + 800528a: f85d 7b04 ldr.w r7, [sp], #4 + 800528e: 4770 bx lr + +08005290 : + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + 8005290: b580 push {r7, lr} + 8005292: b086 sub sp, #24 + 8005294: af02 add r7, sp, #8 + 8005296: 6078 str r0, [r7, #4] + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8005298: 687b ldr r3, [r7, #4] + 800529a: 2200 movs r2, #0 + 800529c: 67da str r2, [r3, #124] ; 0x7c + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + 800529e: f7fc fd93 bl 8001dc8 + 80052a2: 60f8 str r0, [r7, #12] + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + 80052a4: 687b ldr r3, [r7, #4] + 80052a6: 681b ldr r3, [r3, #0] + 80052a8: 681b ldr r3, [r3, #0] + 80052aa: f003 0308 and.w r3, r3, #8 + 80052ae: 2b08 cmp r3, #8 + 80052b0: d10e bne.n 80052d0 + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + 80052b2: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 + 80052b6: 9300 str r3, [sp, #0] + 80052b8: 68fb ldr r3, [r7, #12] + 80052ba: 2200 movs r2, #0 + 80052bc: f44f 1100 mov.w r1, #2097152 ; 0x200000 + 80052c0: 6878 ldr r0, [r7, #4] + 80052c2: f000 f814 bl 80052ee + 80052c6: 4603 mov r3, r0 + 80052c8: 2b00 cmp r3, #0 + 80052ca: d001 beq.n 80052d0 + { + /* Timeout occurred */ + return HAL_TIMEOUT; + 80052cc: 2303 movs r3, #3 + 80052ce: e00a b.n 80052e6 + } + } + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + 80052d0: 687b ldr r3, [r7, #4] + 80052d2: 2220 movs r2, #32 + 80052d4: 675a str r2, [r3, #116] ; 0x74 + huart->RxState = HAL_UART_STATE_READY; + 80052d6: 687b ldr r3, [r7, #4] + 80052d8: 2220 movs r2, #32 + 80052da: 679a str r2, [r3, #120] ; 0x78 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 80052dc: 687b ldr r3, [r7, #4] + 80052de: 2200 movs r2, #0 + 80052e0: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + return HAL_OK; + 80052e4: 2300 movs r3, #0 +} + 80052e6: 4618 mov r0, r3 + 80052e8: 3710 adds r7, #16 + 80052ea: 46bd mov sp, r7 + 80052ec: bd80 pop {r7, pc} + +080052ee : + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +{ + 80052ee: b580 push {r7, lr} + 80052f0: b084 sub sp, #16 + 80052f2: af00 add r7, sp, #0 + 80052f4: 60f8 str r0, [r7, #12] + 80052f6: 60b9 str r1, [r7, #8] + 80052f8: 603b str r3, [r7, #0] + 80052fa: 4613 mov r3, r2 + 80052fc: 71fb strb r3, [r7, #7] + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 80052fe: e02a b.n 8005356 + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8005300: 69bb ldr r3, [r7, #24] + 8005302: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8005306: d026 beq.n 8005356 + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 8005308: f7fc fd5e bl 8001dc8 + 800530c: 4602 mov r2, r0 + 800530e: 683b ldr r3, [r7, #0] + 8005310: 1ad3 subs r3, r2, r3 + 8005312: 69ba ldr r2, [r7, #24] + 8005314: 429a cmp r2, r3 + 8005316: d302 bcc.n 800531e + 8005318: 69bb ldr r3, [r7, #24] + 800531a: 2b00 cmp r3, #0 + 800531c: d11b bne.n 8005356 + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + 800531e: 68fb ldr r3, [r7, #12] + 8005320: 681b ldr r3, [r3, #0] + 8005322: 681a ldr r2, [r3, #0] + 8005324: 68fb ldr r3, [r7, #12] + 8005326: 681b ldr r3, [r3, #0] + 8005328: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 + 800532c: 601a str r2, [r3, #0] + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 800532e: 68fb ldr r3, [r7, #12] + 8005330: 681b ldr r3, [r3, #0] + 8005332: 689a ldr r2, [r3, #8] + 8005334: 68fb ldr r3, [r7, #12] + 8005336: 681b ldr r3, [r3, #0] + 8005338: f022 0201 bic.w r2, r2, #1 + 800533c: 609a str r2, [r3, #8] + + huart->gState = HAL_UART_STATE_READY; + 800533e: 68fb ldr r3, [r7, #12] + 8005340: 2220 movs r2, #32 + 8005342: 675a str r2, [r3, #116] ; 0x74 + huart->RxState = HAL_UART_STATE_READY; + 8005344: 68fb ldr r3, [r7, #12] + 8005346: 2220 movs r2, #32 + 8005348: 679a str r2, [r3, #120] ; 0x78 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 800534a: 68fb ldr r3, [r7, #12] + 800534c: 2200 movs r2, #0 + 800534e: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + return HAL_TIMEOUT; + 8005352: 2303 movs r3, #3 + 8005354: e00f b.n 8005376 + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 8005356: 68fb ldr r3, [r7, #12] + 8005358: 681b ldr r3, [r3, #0] + 800535a: 69da ldr r2, [r3, #28] + 800535c: 68bb ldr r3, [r7, #8] + 800535e: 4013 ands r3, r2 + 8005360: 68ba ldr r2, [r7, #8] + 8005362: 429a cmp r2, r3 + 8005364: bf0c ite eq + 8005366: 2301 moveq r3, #1 + 8005368: 2300 movne r3, #0 + 800536a: b2db uxtb r3, r3 + 800536c: 461a mov r2, r3 + 800536e: 79fb ldrb r3, [r7, #7] + 8005370: 429a cmp r2, r3 + 8005372: d0c5 beq.n 8005300 + } + } + } + return HAL_OK; + 8005374: 2300 movs r3, #0 +} + 8005376: 4618 mov r0, r3 + 8005378: 3710 adds r7, #16 + 800537a: 46bd mov sp, r7 + 800537c: bd80 pop {r7, pc} + +0800537e : + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + 800537e: b480 push {r7} + 8005380: b083 sub sp, #12 + 8005382: af00 add r7, sp, #0 + 8005384: 6078 str r0, [r7, #4] + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + 8005386: 687b ldr r3, [r7, #4] + 8005388: 681b ldr r3, [r3, #0] + 800538a: 681a ldr r2, [r3, #0] + 800538c: 687b ldr r3, [r7, #4] + 800538e: 681b ldr r3, [r3, #0] + 8005390: f422 7290 bic.w r2, r2, #288 ; 0x120 + 8005394: 601a str r2, [r3, #0] + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8005396: 687b ldr r3, [r7, #4] + 8005398: 681b ldr r3, [r3, #0] + 800539a: 689a ldr r2, [r3, #8] + 800539c: 687b ldr r3, [r7, #4] + 800539e: 681b ldr r3, [r3, #0] + 80053a0: f022 0201 bic.w r2, r2, #1 + 80053a4: 609a str r2, [r3, #8] + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 80053a6: 687b ldr r3, [r7, #4] + 80053a8: 2220 movs r2, #32 + 80053aa: 679a str r2, [r3, #120] ; 0x78 + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; + 80053ac: 687b ldr r3, [r7, #4] + 80053ae: 2200 movs r2, #0 + 80053b0: 661a str r2, [r3, #96] ; 0x60 +} + 80053b2: bf00 nop + 80053b4: 370c adds r7, #12 + 80053b6: 46bd mov sp, r7 + 80053b8: f85d 7b04 ldr.w r7, [sp], #4 + 80053bc: 4770 bx lr + +080053be : + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + 80053be: b580 push {r7, lr} + 80053c0: b084 sub sp, #16 + 80053c2: af00 add r7, sp, #0 + 80053c4: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 80053c6: 687b ldr r3, [r7, #4] + 80053c8: 6b9b ldr r3, [r3, #56] ; 0x38 + 80053ca: 60fb str r3, [r7, #12] + huart->RxXferCount = 0U; + 80053cc: 68fb ldr r3, [r7, #12] + 80053ce: 2200 movs r2, #0 + 80053d0: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + huart->TxXferCount = 0U; + 80053d4: 68fb ldr r3, [r7, #12] + 80053d6: 2200 movs r2, #0 + 80053d8: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 80053dc: 68f8 ldr r0, [r7, #12] + 80053de: f7ff fc07 bl 8004bf0 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 80053e2: bf00 nop + 80053e4: 3710 adds r7, #16 + 80053e6: 46bd mov sp, r7 + 80053e8: bd80 pop {r7, pc} + +080053ea : + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + 80053ea: b580 push {r7, lr} + 80053ec: b082 sub sp, #8 + 80053ee: af00 add r7, sp, #0 + 80053f0: 6078 str r0, [r7, #4] + /* Disable the UART Transmit Complete Interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + 80053f2: 687b ldr r3, [r7, #4] + 80053f4: 681b ldr r3, [r3, #0] + 80053f6: 681a ldr r2, [r3, #0] + 80053f8: 687b ldr r3, [r7, #4] + 80053fa: 681b ldr r3, [r3, #0] + 80053fc: f022 0240 bic.w r2, r2, #64 ; 0x40 + 8005400: 601a str r2, [r3, #0] + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 8005402: 687b ldr r3, [r7, #4] + 8005404: 2220 movs r2, #32 + 8005406: 675a str r2, [r3, #116] ; 0x74 + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + 8005408: 687b ldr r3, [r7, #4] + 800540a: 2200 movs r2, #0 + 800540c: 665a str r2, [r3, #100] ; 0x64 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); + 800540e: 6878 ldr r0, [r7, #4] + 8005410: f7ff fbe4 bl 8004bdc +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 8005414: bf00 nop + 8005416: 3708 adds r7, #8 + 8005418: 46bd mov sp, r7 + 800541a: bd80 pop {r7, pc} + +0800541c : + * @brief RX interrrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + 800541c: b580 push {r7, lr} + 800541e: b084 sub sp, #16 + 8005420: af00 add r7, sp, #0 + 8005422: 6078 str r0, [r7, #4] + uint16_t uhMask = huart->Mask; + 8005424: 687b ldr r3, [r7, #4] + 8005426: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c + 800542a: 81fb strh r3, [r7, #14] + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 800542c: 687b ldr r3, [r7, #4] + 800542e: 6f9b ldr r3, [r3, #120] ; 0x78 + 8005430: 2b22 cmp r3, #34 ; 0x22 + 8005432: d13a bne.n 80054aa + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 8005434: 687b ldr r3, [r7, #4] + 8005436: 681b ldr r3, [r3, #0] + 8005438: 6a5b ldr r3, [r3, #36] ; 0x24 + 800543a: 81bb strh r3, [r7, #12] + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + 800543c: 89bb ldrh r3, [r7, #12] + 800543e: b2d9 uxtb r1, r3 + 8005440: 89fb ldrh r3, [r7, #14] + 8005442: b2da uxtb r2, r3 + 8005444: 687b ldr r3, [r7, #4] + 8005446: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005448: 400a ands r2, r1 + 800544a: b2d2 uxtb r2, r2 + 800544c: 701a strb r2, [r3, #0] + huart->pRxBuffPtr++; + 800544e: 687b ldr r3, [r7, #4] + 8005450: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005452: 1c5a adds r2, r3, #1 + 8005454: 687b ldr r3, [r7, #4] + 8005456: 655a str r2, [r3, #84] ; 0x54 + huart->RxXferCount--; + 8005458: 687b ldr r3, [r7, #4] + 800545a: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 800545e: b29b uxth r3, r3 + 8005460: 3b01 subs r3, #1 + 8005462: b29a uxth r2, r3 + 8005464: 687b ldr r3, [r7, #4] + 8005466: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + + if (huart->RxXferCount == 0U) + 800546a: 687b ldr r3, [r7, #4] + 800546c: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 8005470: b29b uxth r3, r3 + 8005472: 2b00 cmp r3, #0 + 8005474: d121 bne.n 80054ba + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + 8005476: 687b ldr r3, [r7, #4] + 8005478: 681b ldr r3, [r3, #0] + 800547a: 681a ldr r2, [r3, #0] + 800547c: 687b ldr r3, [r7, #4] + 800547e: 681b ldr r3, [r3, #0] + 8005480: f422 7290 bic.w r2, r2, #288 ; 0x120 + 8005484: 601a str r2, [r3, #0] + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8005486: 687b ldr r3, [r7, #4] + 8005488: 681b ldr r3, [r3, #0] + 800548a: 689a ldr r2, [r3, #8] + 800548c: 687b ldr r3, [r7, #4] + 800548e: 681b ldr r3, [r3, #0] + 8005490: f022 0201 bic.w r2, r2, #1 + 8005494: 609a str r2, [r3, #8] + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8005496: 687b ldr r3, [r7, #4] + 8005498: 2220 movs r2, #32 + 800549a: 679a str r2, [r3, #120] ; 0x78 + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 800549c: 687b ldr r3, [r7, #4] + 800549e: 2200 movs r2, #0 + 80054a0: 661a str r2, [r3, #96] ; 0x60 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); + 80054a2: 6878 ldr r0, [r7, #4] + 80054a4: f7fc f854 bl 8001550 + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + 80054a8: e007 b.n 80054ba + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 80054aa: 687b ldr r3, [r7, #4] + 80054ac: 681b ldr r3, [r3, #0] + 80054ae: 699a ldr r2, [r3, #24] + 80054b0: 687b ldr r3, [r7, #4] + 80054b2: 681b ldr r3, [r3, #0] + 80054b4: f042 0208 orr.w r2, r2, #8 + 80054b8: 619a str r2, [r3, #24] +} + 80054ba: bf00 nop + 80054bc: 3710 adds r7, #16 + 80054be: 46bd mov sp, r7 + 80054c0: bd80 pop {r7, pc} + +080054c2 : + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + 80054c2: b580 push {r7, lr} + 80054c4: b084 sub sp, #16 + 80054c6: af00 add r7, sp, #0 + 80054c8: 6078 str r0, [r7, #4] + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + 80054ca: 687b ldr r3, [r7, #4] + 80054cc: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c + 80054d0: 81fb strh r3, [r7, #14] + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 80054d2: 687b ldr r3, [r7, #4] + 80054d4: 6f9b ldr r3, [r3, #120] ; 0x78 + 80054d6: 2b22 cmp r3, #34 ; 0x22 + 80054d8: d13a bne.n 8005550 + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 80054da: 687b ldr r3, [r7, #4] + 80054dc: 681b ldr r3, [r3, #0] + 80054de: 6a5b ldr r3, [r3, #36] ; 0x24 + 80054e0: 81bb strh r3, [r7, #12] + tmp = (uint16_t *) huart->pRxBuffPtr ; + 80054e2: 687b ldr r3, [r7, #4] + 80054e4: 6d5b ldr r3, [r3, #84] ; 0x54 + 80054e6: 60bb str r3, [r7, #8] + *tmp = (uint16_t)(uhdata & uhMask); + 80054e8: 89ba ldrh r2, [r7, #12] + 80054ea: 89fb ldrh r3, [r7, #14] + 80054ec: 4013 ands r3, r2 + 80054ee: b29a uxth r2, r3 + 80054f0: 68bb ldr r3, [r7, #8] + 80054f2: 801a strh r2, [r3, #0] + huart->pRxBuffPtr += 2U; + 80054f4: 687b ldr r3, [r7, #4] + 80054f6: 6d5b ldr r3, [r3, #84] ; 0x54 + 80054f8: 1c9a adds r2, r3, #2 + 80054fa: 687b ldr r3, [r7, #4] + 80054fc: 655a str r2, [r3, #84] ; 0x54 + huart->RxXferCount--; + 80054fe: 687b ldr r3, [r7, #4] + 8005500: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 8005504: b29b uxth r3, r3 + 8005506: 3b01 subs r3, #1 + 8005508: b29a uxth r2, r3 + 800550a: 687b ldr r3, [r7, #4] + 800550c: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + + if (huart->RxXferCount == 0U) + 8005510: 687b ldr r3, [r7, #4] + 8005512: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 8005516: b29b uxth r3, r3 + 8005518: 2b00 cmp r3, #0 + 800551a: d121 bne.n 8005560 + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + 800551c: 687b ldr r3, [r7, #4] + 800551e: 681b ldr r3, [r3, #0] + 8005520: 681a ldr r2, [r3, #0] + 8005522: 687b ldr r3, [r7, #4] + 8005524: 681b ldr r3, [r3, #0] + 8005526: f422 7290 bic.w r2, r2, #288 ; 0x120 + 800552a: 601a str r2, [r3, #0] + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 800552c: 687b ldr r3, [r7, #4] + 800552e: 681b ldr r3, [r3, #0] + 8005530: 689a ldr r2, [r3, #8] + 8005532: 687b ldr r3, [r7, #4] + 8005534: 681b ldr r3, [r3, #0] + 8005536: f022 0201 bic.w r2, r2, #1 + 800553a: 609a str r2, [r3, #8] + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 800553c: 687b ldr r3, [r7, #4] + 800553e: 2220 movs r2, #32 + 8005540: 679a str r2, [r3, #120] ; 0x78 + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 8005542: 687b ldr r3, [r7, #4] + 8005544: 2200 movs r2, #0 + 8005546: 661a str r2, [r3, #96] ; 0x60 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); + 8005548: 6878 ldr r0, [r7, #4] + 800554a: f7fc f801 bl 8001550 + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + 800554e: e007 b.n 8005560 + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 8005550: 687b ldr r3, [r7, #4] + 8005552: 681b ldr r3, [r3, #0] + 8005554: 699a ldr r2, [r3, #24] + 8005556: 687b ldr r3, [r7, #4] + 8005558: 681b ldr r3, [r3, #0] + 800555a: f042 0208 orr.w r2, r2, #8 + 800555e: 619a str r2, [r3, #24] +} + 8005560: bf00 nop + 8005562: 3710 adds r7, #16 + 8005564: 46bd mov sp, r7 + 8005566: bd80 pop {r7, pc} + +08005568 <__libc_init_array>: + 8005568: b570 push {r4, r5, r6, lr} + 800556a: 4e0d ldr r6, [pc, #52] ; (80055a0 <__libc_init_array+0x38>) + 800556c: 4c0d ldr r4, [pc, #52] ; (80055a4 <__libc_init_array+0x3c>) + 800556e: 1ba4 subs r4, r4, r6 + 8005570: 10a4 asrs r4, r4, #2 + 8005572: 2500 movs r5, #0 + 8005574: 42a5 cmp r5, r4 + 8005576: d109 bne.n 800558c <__libc_init_array+0x24> + 8005578: 4e0b ldr r6, [pc, #44] ; (80055a8 <__libc_init_array+0x40>) + 800557a: 4c0c ldr r4, [pc, #48] ; (80055ac <__libc_init_array+0x44>) + 800557c: f000 f820 bl 80055c0 <_init> + 8005580: 1ba4 subs r4, r4, r6 + 8005582: 10a4 asrs r4, r4, #2 + 8005584: 2500 movs r5, #0 + 8005586: 42a5 cmp r5, r4 + 8005588: d105 bne.n 8005596 <__libc_init_array+0x2e> + 800558a: bd70 pop {r4, r5, r6, pc} + 800558c: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 8005590: 4798 blx r3 + 8005592: 3501 adds r5, #1 + 8005594: e7ee b.n 8005574 <__libc_init_array+0xc> + 8005596: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 800559a: 4798 blx r3 + 800559c: 3501 adds r5, #1 + 800559e: e7f2 b.n 8005586 <__libc_init_array+0x1e> + 80055a0: 080055f8 .word 0x080055f8 + 80055a4: 080055f8 .word 0x080055f8 + 80055a8: 080055f8 .word 0x080055f8 + 80055ac: 08005600 .word 0x08005600 + +080055b0 : + 80055b0: 4402 add r2, r0 + 80055b2: 4603 mov r3, r0 + 80055b4: 4293 cmp r3, r2 + 80055b6: d100 bne.n 80055ba + 80055b8: 4770 bx lr + 80055ba: f803 1b01 strb.w r1, [r3], #1 + 80055be: e7f9 b.n 80055b4 + +080055c0 <_init>: + 80055c0: b5f8 push {r3, r4, r5, r6, r7, lr} + 80055c2: bf00 nop + 80055c4: bcf8 pop {r3, r4, r5, r6, r7} + 80055c6: bc08 pop {r3} + 80055c8: 469e mov lr, r3 + 80055ca: 4770 bx lr + +080055cc <_fini>: + 80055cc: b5f8 push {r3, r4, r5, r6, r7, lr} + 80055ce: bf00 nop + 80055d0: bcf8 pop {r3, r4, r5, r6, r7} + 80055d2: bc08 pop {r3} + 80055d4: 469e mov lr, r3 + 80055d6: 4770 bx lr diff --git a/utils/pid_tuning/otto_pid_tuning/Debug/sources.mk b/utils/pid_tuning/otto_pid_tuning/Debug/sources.mk new file mode 100644 index 0000000..ab6831f --- /dev/null +++ b/utils/pid_tuning/otto_pid_tuning/Debug/sources.mk @@ -0,0 +1,32 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +ELF_SRCS := +C_UPPER_SRCS := +CXX_SRCS := +C++_SRCS := +OBJ_SRCS := +S_SRCS := +CC_SRCS := +C_SRCS := +CPP_SRCS := +S_UPPER_SRCS := +O_SRCS := +CC_DEPS := +SIZE_OUTPUT := +OBJDUMP_LIST := +C++_DEPS := +EXECUTABLES := +OBJS := +C_UPPER_DEPS := +CXX_DEPS := +C_DEPS := +CPP_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Drivers/STM32F7xx_HAL_Driver/Src \ + diff --git a/utils/pid_tuning/otto_pid_tuning/otto_pid_tuning.ioc b/utils/pid_tuning/otto_pid_tuning/otto_pid_tuning.ioc index 844db89..40f3e64 100644 --- a/utils/pid_tuning/otto_pid_tuning/otto_pid_tuning.ioc +++ b/utils/pid_tuning/otto_pid_tuning/otto_pid_tuning.ioc @@ -230,9 +230,9 @@ TIM6.IPParameters=Prescaler,Period TIM6.Period=799 TIM6.Prescaler=9999 USART6.IPParameters=VirtualMode-Asynchronous,WordLength,Parity -USART6.Parity=PARITY_ODD +USART6.Parity=PARITY_NONE USART6.VirtualMode-Asynchronous=VM_ASYNC -USART6.WordLength=WORDLENGTH_9B +USART6.WordLength=WORDLENGTH_8B VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick VP_TIM3_VS_ClockSourceINT.Mode=Internal diff --git a/utils/proto_test/.project b/utils/proto_test/.project new file mode 100644 index 0000000..772433e --- /dev/null +++ b/utils/proto_test/.project @@ -0,0 +1,11 @@ + + + proto_test + + + + + + + + diff --git a/utils/proto_test/__pycache__/velocities_pb2.cpython-36.pyc b/utils/proto_test/__pycache__/velocities_pb2.cpython-36.pyc new file mode 100644 index 0000000000000000000000000000000000000000..d7534c99a2edf197ced993ddef6c6338e32d4ce4 GIT binary patch literal 1767 zcmaJ>OK;;g5FW}eS$@Vzyh%3QZHpeNON@5WOA#yzB)bgr-HI$d$&MM$Q;gt^UcR0Uo{%u&wm~L@`nrXH*Ea&0N^_S z(BCou1Y{C85R4eYKA`g+)C(+N@pl-1fh9Y02La2n5Eprg*@%iP#ARN|WmgtrmsfMS zDhsj4Yq{*nLR{x{22>k0X26?N8nv*7b!?D>%^AbiW0AM1IohK3j4`0nsDo{6BP08j zM%%cB9R%FQ9o)rj?9vXxjNxK*^ZD6hEBD;P{oL<=J%`Q^>_CQHY~<1bKF7nyHs7UP zYLB|uJ_f3eo?)9RqrCy6ecHuO@WrDuEARtqj-Jzj#ft0({Fie}>gBuu0DZP3*v|Gl zu>=2agU{lLlmz|Hjz!P${*u!o^W_Mju9Z6S>Vp4DNB(>$yYuz zWlH)flFyVyyT+&N#`&JB3_dd+lJ2W$oTbWVrV^9ZVo27YXdtPdMQP$Q)6&y8Ol5!~ z6QR)7p}CH$v)9tXKpk|HF@x84aI zAPvMsX2G416XJ~zm-Qvri?AvslQ|E7E^PHk2XvoNqN6n7t(6$)emW*o zNyqk-G~Zj~+M zFbAf&w?eJefemRqK}8WtQd?HnUWErrBtz1?oF5SBeM((X0dF$K~zE+shK&B$&wczd94{uH`ZZFPm`0i%k=pdZtZOIS6r-YQq2(Roj z(@*7(i@SVl`?IoKm?B2~Om!@x))S(oZR4rPA2s_-825O=@N4^+=wAWAWiMF$X%yU2 pkvaLOJKjomnBx>#nYqkmWoD(#mFqZ;^;pC$B)8x>P3ADK@Gp + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/utils/proto_test/otto_proto_test/.mxproject b/utils/proto_test/otto_proto_test/.mxproject new file mode 100644 index 0000000..75ebd33 --- /dev/null +++ b/utils/proto_test/otto_proto_test/.mxproject @@ -0,0 +1,25 @@ +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=3 +HeaderFiles#0=/home/fdila/Projects/otto/utils/ticks_calibration/otto_ticks_calibration/Core/Inc/stm32f7xx_it.h +HeaderFiles#1=/home/fdila/Projects/otto/utils/ticks_calibration/otto_ticks_calibration/Core/Inc/stm32f7xx_hal_conf.h +HeaderFiles#2=/home/fdila/Projects/otto/utils/ticks_calibration/otto_ticks_calibration/Core/Inc/main.h +HeaderFolderListSize=1 +HeaderPath#0=/home/fdila/Projects/otto/utils/ticks_calibration/otto_ticks_calibration/Core/Inc +SourceFileListSize=3 +SourceFiles#0=/home/fdila/Projects/otto/utils/ticks_calibration/otto_ticks_calibration/Core/Src/stm32f7xx_it.c +SourceFiles#1=/home/fdila/Projects/otto/utils/ticks_calibration/otto_ticks_calibration/Core/Src/stm32f7xx_hal_msp.c +SourceFiles#2=/home/fdila/Projects/otto/utils/ticks_calibration/otto_ticks_calibration/Core/Src/main.c +SourceFolderListSize=1 +SourcePath#0=/home/fdila/Projects/otto/utils/ticks_calibration/otto_ticks_calibration/Core/Src +HeaderFiles=; +SourceFiles=; + +[PreviousLibFiles] +LibFiles=Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm4.h; + +[PreviousUsedCubeIDEFiles] +SourceFiles=Core/Src/main.c;Core/Src/stm32f7xx_it.c;Core/Src/stm32f7xx_hal_msp.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;Core/Src/system_stm32f7xx.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;Core/Src/system_stm32f7xx.c;Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;; +HeaderPath=Drivers/STM32F7xx_HAL_Driver/Inc;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32F7xx/Include;Drivers/CMSIS/Include;Core/Inc; +CDefines=USE_HAL_DRIVER;STM32F767xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + diff --git a/utils/proto_test/otto_proto_test/.project b/utils/proto_test/otto_proto_test/.project new file mode 100644 index 0000000..ed3ac57 --- /dev/null +++ b/utils/proto_test/otto_proto_test/.project @@ -0,0 +1,34 @@ + + + otto_proto_test + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + org.eclipse.cdt.core.cnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature + com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature + com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + com.st.stm32cube.ide.mcu.MCURootProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + + diff --git a/utils/proto_test/otto_proto_test/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs b/utils/proto_test/otto_proto_test/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs new file mode 100644 index 0000000..366a7f2 --- /dev/null +++ b/utils/proto_test/otto_proto_test/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +svd_custom_file_path= +svd_file_path=platform\:/plugin/com.st.stm32cube.ide.mcu.productdb.debug/resources/cmsis/STMicroelectronics_CMSIS_SVD/STM32F7x7.svd diff --git a/utils/proto_test/otto_proto_test/.settings/language.settings.xml b/utils/proto_test/otto_proto_test/.settings/language.settings.xml new file mode 100644 index 0000000..65e4170 --- /dev/null +++ b/utils/proto_test/otto_proto_test/.settings/language.settings.xml @@ -0,0 +1,27 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/utils/proto_test/otto_proto_test/.settings/org.eclipse.cdt.codan.core.prefs b/utils/proto_test/otto_proto_test/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..f957b85 --- /dev/null +++ b/utils/proto_test/otto_proto_test/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,56 @@ +com.st.stm32cube.ide.mcu.ide.oss.source.checker.libnano.problem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Float formatting support\\")"} +eclipse.preferences.version=1 +org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false} +org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"} +org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"} +org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"} +org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false} +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"} +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"} +org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"C-Style cast instead of C++ cast\\")"} +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false,enable_fallthrough_quickfix_param\=>false} +org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"} +org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true} +org.eclipse.cdt.codan.internal.checkers.CopyrightProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.CopyrightProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Lack of copyright information\\")",regex\=>".*Copyright.*"} +org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid 'decltype(auto)' specifier\\")"} +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Goto statement used\\")"} +org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"} +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"} +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"} +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"} +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.MissCaseProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissCaseProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing cases in switch\\")"} +org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing default in switch\\")",defaultWithAllEnums\=>false} +org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing reference return value in assignment operator\\")"} +org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing self check in assignment operator\\")"} +org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"} +org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"} +org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"} +org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"} +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"} +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"} +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false} +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false} +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")} +org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Using directive in header\\")"} +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem=-Error +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Virtual method call in constructor/destructor\\")"} diff --git a/utils/proto_test/otto_proto_test/.settings/org.eclipse.cdt.ui.prefs b/utils/proto_test/otto_proto_test/.settings/org.eclipse.cdt.ui.prefs new file mode 100644 index 0000000..4ee12a4 --- /dev/null +++ b/utils/proto_test/otto_proto_test/.settings/org.eclipse.cdt.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +formatter_settings_version=1 diff --git a/utils/proto_test/otto_proto_test/.settings/org.eclipse.core.runtime.prefs b/utils/proto_test/otto_proto_test/.settings/org.eclipse.core.runtime.prefs new file mode 100644 index 0000000..0e915ed --- /dev/null +++ b/utils/proto_test/otto_proto_test/.settings/org.eclipse.core.runtime.prefs @@ -0,0 +1,3 @@ +content-types/enabled=true +content-types/org.eclipse.cdt.core.cxxHeader/file-names=.h +eclipse.preferences.version=1 diff --git a/utils/proto_test/otto_proto_test/Core/Inc/communication_utils.h b/utils/proto_test/otto_proto_test/Core/Inc/communication_utils.h new file mode 100644 index 0000000..00841cf --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Inc/communication_utils.h @@ -0,0 +1,32 @@ +// __attribute__((packed)) -> no padding bytes +typedef struct __attribute__((packed)) { + float angular_velocity; + float linear_velocity; + float delta_time; +} odometry_msg; + +typedef struct __attribute__((packed)) { + float linear_velocity; + float angular_velocity; +} velocity_msg; + +typedef struct __attribute__((packed)) { + float pid_select; + float pid_setpoint_fixed; + float pid_setpoint_lin; + float pid_setpoint_ang; + float pid_kp; + float pid_ki; + float pid_kd; +} pid_setup_msg; + +typedef struct __attribute__((packed)) { + float velocity; +// float millis; +} plot_msg; + +typedef struct __attribute__((packed)){ + int left_ticks; + int right_ticks; +} ticks_msg; + diff --git a/utils/proto_test/otto_proto_test/Core/Inc/constants.h b/utils/proto_test/otto_proto_test/Core/Inc/constants.h new file mode 100644 index 0000000..2df0b3e --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Inc/constants.h @@ -0,0 +1,14 @@ +#ifndef CONSTANTS_H +#define CONSTANTS_H + +#define BASELINE 0.3 //distance between wheels in meters +#define MAX_DUTY_CYCLE 790 + +#define LEFT_TICKS_PER_METER 195788 //no +#define RIGHT_TICKS_PER_METER 196829 //no + +#define TICKS_PER_REVOLUTION 148000 //x4 resolution +#define RIGHT_WHEEL_CIRCUMFERENCE 0.8 //in meters +#define LEFT_WHEEL_CIRCUMFERENCE 0.78 //in meters + +#endif diff --git a/utils/proto_test/otto_proto_test/Core/Inc/encoder.h b/utils/proto_test/otto_proto_test/Core/Inc/encoder.h new file mode 100644 index 0000000..bd05dfb --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Inc/encoder.h @@ -0,0 +1,46 @@ +#ifndef ENCODER_H +#define ENCODER_H + +#include "main.h" +#include "constants.h" + +class Encoder { + public: + TIM_HandleTypeDef *timer_; + uint32_t previous_millis_; + uint32_t current_millis_; + int32_t ticks_; //if negative the wheel is going backwards + float wheel_circumference_; + int ticks_per_meter_; + + Encoder() { + timer_ = NULL; + wheel_circumference_ = 0; + ticks_per_meter_ = 0; + } + +// Encoder(TIM_HandleTypeDef *timer, float wheel_circ); + Encoder(TIM_HandleTypeDef *timer, int ticks_per_meters); + + + void Setup(); + + int GetCount() { + int count = ((int) __HAL_TIM_GET_COUNTER(this->timer_) + - ((this->timer_->Init.Period) / 2)); + return count; + } + + void ResetCount() { + //set counter to half its maximum value + __HAL_TIM_SET_COUNTER(timer_, (timer_->Init.Period / 2)); + } + + void UpdateValues(); + + float GetMeters(); + + float GetLinearVelocity(); + +}; +#endif diff --git a/utils/proto_test/otto_proto_test/Core/Inc/main.h b/utils/proto_test/otto_proto_test/Core/Inc/main.h new file mode 100644 index 0000000..6b45ffa --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Inc/main.h @@ -0,0 +1,104 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define user_button_Pin GPIO_PIN_13 +#define user_button_GPIO_Port GPIOC +#define user_button_EXTI_IRQn EXTI15_10_IRQn +#define current2_Pin GPIO_PIN_0 +#define current2_GPIO_Port GPIOC +#define encoder_dx1_Pin GPIO_PIN_0 +#define encoder_dx1_GPIO_Port GPIOA +#define encoder_dx2_Pin GPIO_PIN_1 +#define encoder_dx2_GPIO_Port GPIOA +#define current1_Pin GPIO_PIN_3 +#define current1_GPIO_Port GPIOA +#define encoder_sx1_Pin GPIO_PIN_5 +#define encoder_sx1_GPIO_Port GPIOA +#define fault2_Pin GPIO_PIN_6 +#define fault2_GPIO_Port GPIOA +#define dir2_Pin GPIO_PIN_12 +#define dir2_GPIO_Port GPIOF +#define dir1_Pin GPIO_PIN_13 +#define dir1_GPIO_Port GPIOF +#define sleep2_Pin GPIO_PIN_14 +#define sleep2_GPIO_Port GPIOF +#define sleep1_Pin GPIO_PIN_15 +#define sleep1_GPIO_Port GPIOF +#define fault1_Pin GPIO_PIN_9 +#define fault1_GPIO_Port GPIOE +#define pwm2_Pin GPIO_PIN_14 +#define pwm2_GPIO_Port GPIOD +#define pwm1_Pin GPIO_PIN_15 +#define pwm1_GPIO_Port GPIOD +#define encoder_sx2_Pin GPIO_PIN_3 +#define encoder_sx2_GPIO_Port GPIOB +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Core/Inc/motor_controller.h b/utils/proto_test/otto_proto_test/Core/Inc/motor_controller.h new file mode 100644 index 0000000..c4b5e8d --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Inc/motor_controller.h @@ -0,0 +1,67 @@ +#ifndef MOTOR_CONTROLLER_H +#define MOTOR_CONTROLLER_H + +#include "main.h" +#include "constants.h" + +class MotorController { + public: + GPIO_TypeDef *sleep_gpio_port_; + uint16_t sleep_pin_; + GPIO_TypeDef *dir_gpio_port_; + uint16_t dir_pin_; + TIM_HandleTypeDef *pwm_timer_; + uint32_t pwm_channel_; + + MotorController(GPIO_TypeDef *sleep_gpio_port, uint16_t sleep_pin, + GPIO_TypeDef *dir_gpio_port, uint16_t dir_pin, + TIM_HandleTypeDef *pwm_timer, uint32_t pwm_channel) { + this->sleep_gpio_port_ = sleep_gpio_port; + this->sleep_pin_ = sleep_pin; + this->dir_gpio_port_ = dir_gpio_port; + this->dir_pin_ = dir_pin; + this->pwm_timer_ = pwm_timer; + this->pwm_channel_ = pwm_channel; + } + + void setup() { + HAL_TIM_PWM_Start(pwm_timer_, pwm_channel_); + } + + void set_speed(int duty_cycle) { + if (duty_cycle >= 0) { + //set direction to forward + HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_SET); + + //check if duty_cycle exceeds maximum + if (duty_cycle > MAX_DUTY_CYCLE) + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, MAX_DUTY_CYCLE); + else + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle); + + } else if (duty_cycle < 0){ + //set direction to backwards + HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_RESET); + + //check if duty_cycle is lower than minimum + if (duty_cycle < -MAX_DUTY_CYCLE) + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, MAX_DUTY_CYCLE); + else + //invert sign to make duty_cycle positive + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle); + } + + HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET); + + } + + void brake() { + HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET); + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 0); + } + + void coast() { + HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_RESET); + } +}; +#endif diff --git a/utils/proto_test/otto_proto_test/Core/Inc/odometry.h b/utils/proto_test/otto_proto_test/Core/Inc/odometry.h new file mode 100644 index 0000000..c9a405d --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Inc/odometry.h @@ -0,0 +1,49 @@ +#ifndef ODOMETRY_H +#define ODOMETRY_H + +#include "constants.h" + +class Odometry { + private: + + float left_velocity_; + float right_velocity_; + float linear_velocity_; + float angular_velocity_; + + + public: + Odometry() { + left_velocity_ = 0; + right_velocity_ = 0; + linear_velocity_ = 0; + angular_velocity_ = 0; + } + + void UpdateValuesFromVel(float linear_vel, float angular_vel) { + left_velocity_ = linear_vel - (BASELINE * angular_vel)/2; + right_velocity_ = linear_vel + (BASELINE * angular_vel)/2; + } + + void UpdateValuesFromWheels(float left_velocity, float right_velocity){ + linear_velocity_ = (left_velocity + right_velocity)/2; + angular_velocity_ = (right_velocity - left_velocity)/BASELINE; + } + + + float GetLeftVelocity(){ + return left_velocity_; + } + float GetRightVelocity(){ + return right_velocity_; + } + float GetLinearVelocity(){ + return linear_velocity_; + } + float GetAngularVelocity(){ + return angular_velocity_; + } + +}; + +#endif diff --git a/utils/proto_test/otto_proto_test/Core/Inc/pb.h b/utils/proto_test/otto_proto_test/Core/Inc/pb.h new file mode 100644 index 0000000..9e74e3e --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Inc/pb.h @@ -0,0 +1,838 @@ +/* Common parts of the nanopb library. Most of these are quite low-level + * stuff. For the high-level interface, see pb_encode.h and pb_decode.h. + */ + +#ifndef PB_H_INCLUDED +#define PB_H_INCLUDED + +/***************************************************************** + * Nanopb compilation time options. You can change these here by * + * uncommenting the lines, or on the compiler command line. * + *****************************************************************/ + +/* Enable support for dynamically allocated fields */ +/* #define PB_ENABLE_MALLOC 1 */ + +/* Define this if your CPU / compiler combination does not support + * unaligned memory access to packed structures. */ +/* #define PB_NO_PACKED_STRUCTS 1 */ + +/* Increase the number of required fields that are tracked. + * A compiler warning will tell if you need this. */ +/* #define PB_MAX_REQUIRED_FIELDS 256 */ + +/* Add support for tag numbers > 65536 and fields larger than 65536 bytes. */ +/* #define PB_FIELD_32BIT 1 */ + +/* Disable support for error messages in order to save some code space. */ +/* #define PB_NO_ERRMSG 1 */ + +/* Disable support for custom streams (support only memory buffers). */ +/* #define PB_BUFFER_ONLY 1 */ + +/* Disable support for 64-bit datatypes, for compilers without int64_t + or to save some code space. */ +/* #define PB_WITHOUT_64BIT 1 */ + +/* Set the fieldinfo width for all messages using automatic width + * selection. Valid values are 2, 4 and 8. Usually even if you need + * to change the width manually for some reason, it is preferrable + * to do so through the descriptorsize option in .options file. */ +/* #define PB_FIELDINFO_WIDTH 4 */ + +/* Don't encode scalar arrays as packed. This is only to be used when + * the decoder on the receiving side cannot process packed scalar arrays. + * Such example is older protobuf.js. */ +/* #define PB_ENCODE_ARRAYS_UNPACKED 1 */ + +/* Enable conversion of doubles to floats for platforms that do not + * support 64-bit doubles. Most commonly AVR. */ +/* #define PB_CONVERT_DOUBLE_FLOAT 1 */ + +/* Check whether incoming strings are valid UTF-8 sequences. Slows down + * the string processing slightly and slightly increases code size. */ +/* #define PB_VALIDATE_UTF8 1 */ + +/****************************************************************** + * You usually don't need to change anything below this line. * + * Feel free to look around and use the defined macros, though. * + ******************************************************************/ + + +/* Version of the nanopb library. Just in case you want to check it in + * your own program. */ +#define NANOPB_VERSION 0.4.1-dev + +/* Include all the system headers needed by nanopb. You will need the + * definitions of the following: + * - strlen, memcpy, memset functions + * - [u]int_least8_t, uint_fast8_t, [u]int_least16_t, [u]int32_t, [u]int64_t + * - size_t + * - bool + * + * If you don't have the standard header files, you can instead provide + * a custom header that defines or includes all this. In that case, + * define PB_SYSTEM_HEADER to the path of this file. + */ +#ifdef PB_SYSTEM_HEADER +#include PB_SYSTEM_HEADER +#else +#include +#include +#include +#include +#include + +#ifdef PB_ENABLE_MALLOC +#include +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* Macro for defining packed structures (compiler dependent). + * This just reduces memory requirements, but is not required. + */ +#if defined(PB_NO_PACKED_STRUCTS) + /* Disable struct packing */ +# define PB_PACKED_STRUCT_START +# define PB_PACKED_STRUCT_END +# define pb_packed +#elif defined(__GNUC__) || defined(__clang__) + /* For GCC and clang */ +# define PB_PACKED_STRUCT_START +# define PB_PACKED_STRUCT_END +# define pb_packed __attribute__((packed)) +#elif defined(__ICCARM__) || defined(__CC_ARM) + /* For IAR ARM and Keil MDK-ARM compilers */ +# define PB_PACKED_STRUCT_START _Pragma("pack(push, 1)") +# define PB_PACKED_STRUCT_END _Pragma("pack(pop)") +# define pb_packed +#elif defined(_MSC_VER) && (_MSC_VER >= 1500) + /* For Microsoft Visual C++ */ +# define PB_PACKED_STRUCT_START __pragma(pack(push, 1)) +# define PB_PACKED_STRUCT_END __pragma(pack(pop)) +# define pb_packed +#else + /* Unknown compiler */ +# define PB_PACKED_STRUCT_START +# define PB_PACKED_STRUCT_END +# define pb_packed +#endif + +/* Handly macro for suppressing unreferenced-parameter compiler warnings. */ +#ifndef PB_UNUSED +#define PB_UNUSED(x) (void)(x) +#endif + +/* Harvard-architecture processors may need special attributes for storing + * field information in program memory. */ +#ifndef PB_PROGMEM +#ifdef __AVR__ +#include +#define PB_PROGMEM PROGMEM +#define PB_PROGMEM_READU32(x) pgm_read_dword(&x) +#else +#define PB_PROGMEM +#define PB_PROGMEM_READU32(x) (x) +#endif +#endif + +/* Compile-time assertion, used for checking compatible compilation options. + * If this does not work properly on your compiler, use + * #define PB_NO_STATIC_ASSERT to disable it. + * + * But before doing that, check carefully the error message / place where it + * comes from to see if the error has a real cause. Unfortunately the error + * message is not always very clear to read, but you can see the reason better + * in the place where the PB_STATIC_ASSERT macro was called. + */ +#ifndef PB_NO_STATIC_ASSERT +# ifndef PB_STATIC_ASSERT +# if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L + /* C11 standard _Static_assert mechanism */ +# define PB_STATIC_ASSERT(COND,MSG) _Static_assert(COND,#MSG); +# else + /* Classic negative-size-array static assert mechanism */ +# define PB_STATIC_ASSERT(COND,MSG) typedef char PB_STATIC_ASSERT_MSG(MSG, __LINE__, __COUNTER__)[(COND)?1:-1]; +# define PB_STATIC_ASSERT_MSG(MSG, LINE, COUNTER) PB_STATIC_ASSERT_MSG_(MSG, LINE, COUNTER) +# define PB_STATIC_ASSERT_MSG_(MSG, LINE, COUNTER) pb_static_assertion_##MSG##_##LINE##_##COUNTER +# endif +# endif +#else + /* Static asserts disabled by PB_NO_STATIC_ASSERT */ +# define PB_STATIC_ASSERT(COND,MSG) +#endif + +/* Number of required fields to keep track of. */ +#ifndef PB_MAX_REQUIRED_FIELDS +#define PB_MAX_REQUIRED_FIELDS 64 +#endif + +#if PB_MAX_REQUIRED_FIELDS < 64 +#error You should not lower PB_MAX_REQUIRED_FIELDS from the default value (64). +#endif + +#ifdef PB_WITHOUT_64BIT +#ifdef PB_CONVERT_DOUBLE_FLOAT +/* Cannot use doubles without 64-bit types */ +#undef PB_CONVERT_DOUBLE_FLOAT +#endif +#endif + +/* List of possible field types. These are used in the autogenerated code. + * Least-significant 4 bits tell the scalar type + * Most-significant 4 bits specify repeated/required/packed etc. + */ + +typedef uint_least8_t pb_type_t; + +/**** Field data types ****/ + +/* Numeric types */ +#define PB_LTYPE_BOOL 0x00U /* bool */ +#define PB_LTYPE_VARINT 0x01U /* int32, int64, enum, bool */ +#define PB_LTYPE_UVARINT 0x02U /* uint32, uint64 */ +#define PB_LTYPE_SVARINT 0x03U /* sint32, sint64 */ +#define PB_LTYPE_FIXED32 0x04U /* fixed32, sfixed32, float */ +#define PB_LTYPE_FIXED64 0x05U /* fixed64, sfixed64, double */ + +/* Marker for last packable field type. */ +#define PB_LTYPE_LAST_PACKABLE 0x05U + +/* Byte array with pre-allocated buffer. + * data_size is the length of the allocated PB_BYTES_ARRAY structure. */ +#define PB_LTYPE_BYTES 0x06U + +/* String with pre-allocated buffer. + * data_size is the maximum length. */ +#define PB_LTYPE_STRING 0x07U + +/* Submessage + * submsg_fields is pointer to field descriptions */ +#define PB_LTYPE_SUBMESSAGE 0x08U + +/* Submessage with pre-decoding callback + * The pre-decoding callback is stored as pb_callback_t right before pSize. + * submsg_fields is pointer to field descriptions */ +#define PB_LTYPE_SUBMSG_W_CB 0x09U + +/* Extension pseudo-field + * The field contains a pointer to pb_extension_t */ +#define PB_LTYPE_EXTENSION 0x0AU + +/* Byte array with inline, pre-allocated byffer. + * data_size is the length of the inline, allocated buffer. + * This differs from PB_LTYPE_BYTES by defining the element as + * pb_byte_t[data_size] rather than pb_bytes_array_t. */ +#define PB_LTYPE_FIXED_LENGTH_BYTES 0x0BU + +/* Number of declared LTYPES */ +#define PB_LTYPES_COUNT 0x0CU +#define PB_LTYPE_MASK 0x0FU + +/**** Field repetition rules ****/ + +#define PB_HTYPE_REQUIRED 0x00U +#define PB_HTYPE_OPTIONAL 0x10U +#define PB_HTYPE_SINGULAR 0x10U +#define PB_HTYPE_REPEATED 0x20U +#define PB_HTYPE_FIXARRAY 0x20U +#define PB_HTYPE_ONEOF 0x30U +#define PB_HTYPE_MASK 0x30U + +/**** Field allocation types ****/ + +#define PB_ATYPE_STATIC 0x00U +#define PB_ATYPE_POINTER 0x80U +#define PB_ATYPE_CALLBACK 0x40U +#define PB_ATYPE_MASK 0xC0U + +#define PB_ATYPE(x) ((x) & PB_ATYPE_MASK) +#define PB_HTYPE(x) ((x) & PB_HTYPE_MASK) +#define PB_LTYPE(x) ((x) & PB_LTYPE_MASK) +#define PB_LTYPE_IS_SUBMSG(x) (PB_LTYPE(x) == PB_LTYPE_SUBMESSAGE || \ + PB_LTYPE(x) == PB_LTYPE_SUBMSG_W_CB) + +/* Data type used for storing sizes of struct fields + * and array counts. + */ +#if defined(PB_FIELD_32BIT) + typedef uint32_t pb_size_t; + typedef int32_t pb_ssize_t; +#else + typedef uint_least16_t pb_size_t; + typedef int_least16_t pb_ssize_t; +#endif +#define PB_SIZE_MAX ((pb_size_t)-1) + +/* Data type for storing encoded data and other byte streams. + * This typedef exists to support platforms where uint8_t does not exist. + * You can regard it as equivalent on uint8_t on other platforms. + */ +typedef uint_least8_t pb_byte_t; + +/* Forward declaration of struct types */ +typedef struct pb_istream_s pb_istream_t; +typedef struct pb_ostream_s pb_ostream_t; +typedef struct pb_field_iter_s pb_field_iter_t; + +/* This structure is used in auto-generated constants + * to specify struct fields. + */ +PB_PACKED_STRUCT_START +typedef struct pb_msgdesc_s pb_msgdesc_t; +struct pb_msgdesc_s { + pb_size_t field_count; + const uint32_t *field_info; + const pb_msgdesc_t * const * submsg_info; + const pb_byte_t *default_value; + + bool (*field_callback)(pb_istream_t *istream, pb_ostream_t *ostream, const pb_field_iter_t *field); +} pb_packed; +PB_PACKED_STRUCT_END + +/* Iterator for message descriptor */ +struct pb_field_iter_s { + const pb_msgdesc_t *descriptor; /* Pointer to message descriptor constant */ + void *message; /* Pointer to start of the structure */ + + pb_size_t index; /* Index of the field */ + pb_size_t field_info_index; /* Index to descriptor->field_info array */ + pb_size_t required_field_index; /* Index that counts only the required fields */ + pb_size_t submessage_index; /* Index that counts only submessages */ + + pb_size_t tag; /* Tag of current field */ + pb_size_t data_size; /* sizeof() of a single item */ + pb_size_t array_size; /* Number of array entries */ + pb_type_t type; /* Type of current field */ + + void *pField; /* Pointer to current field in struct */ + void *pData; /* Pointer to current data contents. Different than pField for arrays and pointers. */ + void *pSize; /* Pointer to count/has field */ + + const pb_msgdesc_t *submsg_desc; /* For submessage fields, pointer to field descriptor for the submessage. */ +}; + +/* For compatibility with legacy code */ +typedef pb_field_iter_t pb_field_t; + +/* Make sure that the standard integer types are of the expected sizes. + * Otherwise fixed32/fixed64 fields can break. + * + * If you get errors here, it probably means that your stdint.h is not + * correct for your platform. + */ +#ifndef PB_WITHOUT_64BIT +PB_STATIC_ASSERT(sizeof(int64_t) == 2 * sizeof(int32_t), INT64_T_WRONG_SIZE) +PB_STATIC_ASSERT(sizeof(uint64_t) == 2 * sizeof(uint32_t), UINT64_T_WRONG_SIZE) +#endif + +/* This structure is used for 'bytes' arrays. + * It has the number of bytes in the beginning, and after that an array. + * Note that actual structs used will have a different length of bytes array. + */ +#define PB_BYTES_ARRAY_T(n) struct { pb_size_t size; pb_byte_t bytes[n]; } +#define PB_BYTES_ARRAY_T_ALLOCSIZE(n) ((size_t)n + offsetof(pb_bytes_array_t, bytes)) + +struct pb_bytes_array_s { + pb_size_t size; + pb_byte_t bytes[1]; +}; +typedef struct pb_bytes_array_s pb_bytes_array_t; + +/* This structure is used for giving the callback function. + * It is stored in the message structure and filled in by the method that + * calls pb_decode. + * + * The decoding callback will be given a limited-length stream + * If the wire type was string, the length is the length of the string. + * If the wire type was a varint/fixed32/fixed64, the length is the length + * of the actual value. + * The function may be called multiple times (especially for repeated types, + * but also otherwise if the message happens to contain the field multiple + * times.) + * + * The encoding callback will receive the actual output stream. + * It should write all the data in one call, including the field tag and + * wire type. It can write multiple fields. + * + * The callback can be null if you want to skip a field. + */ +typedef struct pb_callback_s pb_callback_t; +struct pb_callback_s { + /* Callback functions receive a pointer to the arg field. + * You can access the value of the field as *arg, and modify it if needed. + */ + union { + bool (*decode)(pb_istream_t *stream, const pb_field_t *field, void **arg); + bool (*encode)(pb_ostream_t *stream, const pb_field_t *field, void * const *arg); + } funcs; + + /* Free arg for use by callback */ + void *arg; +}; + +extern bool pb_default_field_callback(pb_istream_t *istream, pb_ostream_t *ostream, const pb_field_t *field); + +/* Wire types. Library user needs these only in encoder callbacks. */ +typedef enum { + PB_WT_VARINT = 0, + PB_WT_64BIT = 1, + PB_WT_STRING = 2, + PB_WT_32BIT = 5 +} pb_wire_type_t; + +/* Structure for defining the handling of unknown/extension fields. + * Usually the pb_extension_type_t structure is automatically generated, + * while the pb_extension_t structure is created by the user. However, + * if you want to catch all unknown fields, you can also create a custom + * pb_extension_type_t with your own callback. + */ +typedef struct pb_extension_type_s pb_extension_type_t; +typedef struct pb_extension_s pb_extension_t; +struct pb_extension_type_s { + /* Called for each unknown field in the message. + * If you handle the field, read off all of its data and return true. + * If you do not handle the field, do not read anything and return true. + * If you run into an error, return false. + * Set to NULL for default handler. + */ + bool (*decode)(pb_istream_t *stream, pb_extension_t *extension, + uint32_t tag, pb_wire_type_t wire_type); + + /* Called once after all regular fields have been encoded. + * If you have something to write, do so and return true. + * If you do not have anything to write, just return true. + * If you run into an error, return false. + * Set to NULL for default handler. + */ + bool (*encode)(pb_ostream_t *stream, const pb_extension_t *extension); + + /* Free field for use by the callback. */ + const void *arg; +}; + +struct pb_extension_s { + /* Type describing the extension field. Usually you'll initialize + * this to a pointer to the automatically generated structure. */ + const pb_extension_type_t *type; + + /* Destination for the decoded data. This must match the datatype + * of the extension field. */ + void *dest; + + /* Pointer to the next extension handler, or NULL. + * If this extension does not match a field, the next handler is + * automatically called. */ + pb_extension_t *next; + + /* The decoder sets this to true if the extension was found. + * Ignored for encoding. */ + bool found; +}; + +#define pb_extension_init_zero {NULL,NULL,NULL,false} + +/* Memory allocation functions to use. You can define pb_realloc and + * pb_free to custom functions if you want. */ +#ifdef PB_ENABLE_MALLOC +# ifndef pb_realloc +# define pb_realloc(ptr, size) realloc(ptr, size) +# endif +# ifndef pb_free +# define pb_free(ptr) free(ptr) +# endif +#endif + +/* This is used to inform about need to regenerate .pb.h/.pb.c files. */ +#define PB_PROTO_HEADER_VERSION 40 + +/* These macros are used to declare pb_field_t's in the constant array. */ +/* Size of a structure member, in bytes. */ +#define pb_membersize(st, m) (sizeof ((st*)0)->m) +/* Number of entries in an array. */ +#define pb_arraysize(st, m) (pb_membersize(st, m) / pb_membersize(st, m[0])) +/* Delta from start of one member to the start of another member. */ +#define pb_delta(st, m1, m2) ((int)offsetof(st, m1) - (int)offsetof(st, m2)) + +/* Force expansion of macro value */ +#define PB_EXPAND(x) x + +/* Binding of a message field set into a specific structure */ +#define PB_BIND(msgname, structname, width) \ + const uint32_t structname ## _field_info[] PB_PROGMEM = \ + { \ + msgname ## _FIELDLIST(PB_GEN_FIELD_INFO_ ## width, structname) \ + 0 \ + }; \ + const pb_msgdesc_t* const structname ## _submsg_info[] = \ + { \ + msgname ## _FIELDLIST(PB_GEN_SUBMSG_INFO, structname) \ + NULL \ + }; \ + const pb_msgdesc_t structname ## _msg = \ + { \ + 0 msgname ## _FIELDLIST(PB_GEN_FIELD_COUNT, structname), \ + structname ## _field_info, \ + structname ## _submsg_info, \ + msgname ## _DEFAULT, \ + msgname ## _CALLBACK, \ + }; \ + msgname ## _FIELDLIST(PB_GEN_FIELD_INFO_ASSERT_ ## width, structname) + +#define PB_GEN_FIELD_COUNT(structname, atype, htype, ltype, fieldname, tag) +1 + +#define PB_GEN_FIELD_INFO_1(structname, atype, htype, ltype, fieldname, tag) \ + PB_GEN_FIELD_INFO(1, structname, atype, htype, ltype, fieldname, tag) + +#define PB_GEN_FIELD_INFO_2(structname, atype, htype, ltype, fieldname, tag) \ + PB_GEN_FIELD_INFO(2, structname, atype, htype, ltype, fieldname, tag) + +#define PB_GEN_FIELD_INFO_4(structname, atype, htype, ltype, fieldname, tag) \ + PB_GEN_FIELD_INFO(4, structname, atype, htype, ltype, fieldname, tag) + +#define PB_GEN_FIELD_INFO_8(structname, atype, htype, ltype, fieldname, tag) \ + PB_GEN_FIELD_INFO(8, structname, atype, htype, ltype, fieldname, tag) + +#define PB_GEN_FIELD_INFO_AUTO(structname, atype, htype, ltype, fieldname, tag) \ + PB_GEN_FIELD_INFO_AUTO2(PB_FIELDINFO_WIDTH_AUTO(atype, htype, ltype), structname, atype, htype, ltype, fieldname, tag) + +#define PB_GEN_FIELD_INFO_AUTO2(width, structname, atype, htype, ltype, fieldname, tag) \ + PB_GEN_FIELD_INFO(width, structname, atype, htype, ltype, fieldname, tag) + +#define PB_GEN_FIELD_INFO(width, structname, atype, htype, ltype, fieldname, tag) \ + PB_FIELDINFO_ ## width(tag, PB_ATYPE_ ## atype | PB_HTYPE_ ## htype | PB_LTYPE_MAP_ ## ltype, \ + PB_DATA_OFFSET_ ## atype(htype, structname, fieldname), \ + PB_DATA_SIZE_ ## atype(htype, structname, fieldname), \ + PB_SIZE_OFFSET_ ## atype(htype, structname, fieldname), \ + PB_ARRAY_SIZE_ ## atype(htype, structname, fieldname)) + +#define PB_GEN_FIELD_INFO_ASSERT_1(structname, atype, htype, ltype, fieldname, tag) \ + PB_GEN_FIELD_INFO_ASSERT(1, structname, atype, htype, ltype, fieldname, tag) + +#define PB_GEN_FIELD_INFO_ASSERT_2(structname, atype, htype, ltype, fieldname, tag) \ + PB_GEN_FIELD_INFO_ASSERT(2, structname, atype, htype, ltype, fieldname, tag) + +#define PB_GEN_FIELD_INFO_ASSERT_4(structname, atype, htype, ltype, fieldname, tag) \ + PB_GEN_FIELD_INFO_ASSERT(4, structname, atype, htype, ltype, fieldname, tag) + +#define PB_GEN_FIELD_INFO_ASSERT_8(structname, atype, htype, ltype, fieldname, tag) \ + PB_GEN_FIELD_INFO_ASSERT(8, structname, atype, htype, ltype, fieldname, tag) + +#define PB_GEN_FIELD_INFO_ASSERT_AUTO(structname, atype, htype, ltype, fieldname, tag) \ + PB_GEN_FIELD_INFO_ASSERT_AUTO2(PB_FIELDINFO_WIDTH_AUTO(atype, htype, ltype), structname, atype, htype, ltype, fieldname, tag) + +#define PB_GEN_FIELD_INFO_ASSERT_AUTO2(width, structname, atype, htype, ltype, fieldname, tag) \ + PB_GEN_FIELD_INFO_ASSERT(width, structname, atype, htype, ltype, fieldname, tag) + +#define PB_GEN_FIELD_INFO_ASSERT(width, structname, atype, htype, ltype, fieldname, tag) \ + PB_FIELDINFO_ASSERT_ ## width(tag, PB_ATYPE_ ## atype | PB_HTYPE_ ## htype | PB_LTYPE_MAP_ ## ltype, \ + PB_DATA_OFFSET_ ## atype(htype, structname, fieldname), \ + PB_DATA_SIZE_ ## atype(htype, structname, fieldname), \ + PB_SIZE_OFFSET_ ## atype(htype, structname, fieldname), \ + PB_ARRAY_SIZE_ ## atype(htype, structname, fieldname)) + +#define PB_DATA_OFFSET_STATIC(htype, structname, fieldname) PB_DATA_OFFSET_ ## htype(structname, fieldname) +#define PB_DATA_OFFSET_POINTER(htype, structname, fieldname) PB_DATA_OFFSET_ ## htype(structname, fieldname) +#define PB_DATA_OFFSET_CALLBACK(htype, structname, fieldname) PB_DATA_OFFSET_ ## htype(structname, fieldname) +#define PB_DATA_OFFSET_REQUIRED(structname, fieldname) offsetof(structname, fieldname) +#define PB_DATA_OFFSET_SINGULAR(structname, fieldname) offsetof(structname, fieldname) +#define PB_DATA_OFFSET_ONEOF(structname, fieldname) offsetof(structname, PB_ONEOF_NAME(FULL, fieldname)) +#define PB_DATA_OFFSET_OPTIONAL(structname, fieldname) offsetof(structname, fieldname) +#define PB_DATA_OFFSET_REPEATED(structname, fieldname) offsetof(structname, fieldname) +#define PB_DATA_OFFSET_FIXARRAY(structname, fieldname) offsetof(structname, fieldname) + +#define PB_SIZE_OFFSET_STATIC(htype, structname, fieldname) PB_SIZE_OFFSET_ ## htype(structname, fieldname) +#define PB_SIZE_OFFSET_POINTER(htype, structname, fieldname) PB_SIZE_OFFSET_PTR_ ## htype(structname, fieldname) +#define PB_SIZE_OFFSET_CALLBACK(htype, structname, fieldname) PB_SIZE_OFFSET_CB_ ## htype(structname, fieldname) +#define PB_SIZE_OFFSET_REQUIRED(structname, fieldname) 0 +#define PB_SIZE_OFFSET_SINGULAR(structname, fieldname) 0 +#define PB_SIZE_OFFSET_ONEOF(structname, fieldname) PB_SIZE_OFFSET_ONEOF2(structname, PB_ONEOF_NAME(FULL, fieldname), PB_ONEOF_NAME(UNION, fieldname)) +#define PB_SIZE_OFFSET_ONEOF2(structname, fullname, unionname) PB_SIZE_OFFSET_ONEOF3(structname, fullname, unionname) +#define PB_SIZE_OFFSET_ONEOF3(structname, fullname, unionname) pb_delta(structname, fullname, which_ ## unionname) +#define PB_SIZE_OFFSET_OPTIONAL(structname, fieldname) pb_delta(structname, fieldname, has_ ## fieldname) +#define PB_SIZE_OFFSET_REPEATED(structname, fieldname) pb_delta(structname, fieldname, fieldname ## _count) +#define PB_SIZE_OFFSET_FIXARRAY(structname, fieldname) 0 +#define PB_SIZE_OFFSET_PTR_REQUIRED(structname, fieldname) 0 +#define PB_SIZE_OFFSET_PTR_SINGULAR(structname, fieldname) 0 +#define PB_SIZE_OFFSET_PTR_ONEOF(structname, fieldname) PB_SIZE_OFFSET_ONEOF(structname, fieldname) +#define PB_SIZE_OFFSET_PTR_OPTIONAL(structname, fieldname) 0 +#define PB_SIZE_OFFSET_PTR_REPEATED(structname, fieldname) PB_SIZE_OFFSET_REPEATED(structname, fieldname) +#define PB_SIZE_OFFSET_PTR_FIXARRAY(structname, fieldname) 0 +#define PB_SIZE_OFFSET_CB_REQUIRED(structname, fieldname) 0 +#define PB_SIZE_OFFSET_CB_SINGULAR(structname, fieldname) 0 +#define PB_SIZE_OFFSET_CB_ONEOF(structname, fieldname) PB_SIZE_OFFSET_ONEOF(structname, fieldname) +#define PB_SIZE_OFFSET_CB_OPTIONAL(structname, fieldname) 0 +#define PB_SIZE_OFFSET_CB_REPEATED(structname, fieldname) 0 +#define PB_SIZE_OFFSET_CB_FIXARRAY(structname, fieldname) 0 + +#define PB_ARRAY_SIZE_STATIC(htype, structname, fieldname) PB_ARRAY_SIZE_ ## htype(structname, fieldname) +#define PB_ARRAY_SIZE_POINTER(htype, structname, fieldname) PB_ARRAY_SIZE_PTR_ ## htype(structname, fieldname) +#define PB_ARRAY_SIZE_CALLBACK(htype, structname, fieldname) 1 +#define PB_ARRAY_SIZE_REQUIRED(structname, fieldname) 1 +#define PB_ARRAY_SIZE_SINGULAR(structname, fieldname) 1 +#define PB_ARRAY_SIZE_OPTIONAL(structname, fieldname) 1 +#define PB_ARRAY_SIZE_ONEOF(structname, fieldname) 1 +#define PB_ARRAY_SIZE_REPEATED(structname, fieldname) pb_arraysize(structname, fieldname) +#define PB_ARRAY_SIZE_FIXARRAY(structname, fieldname) pb_arraysize(structname, fieldname) +#define PB_ARRAY_SIZE_PTR_REQUIRED(structname, fieldname) 1 +#define PB_ARRAY_SIZE_PTR_SINGULAR(structname, fieldname) 1 +#define PB_ARRAY_SIZE_PTR_OPTIONAL(structname, fieldname) 1 +#define PB_ARRAY_SIZE_PTR_ONEOF(structname, fieldname) 1 +#define PB_ARRAY_SIZE_PTR_REPEATED(structname, fieldname) 1 +#define PB_ARRAY_SIZE_PTR_FIXARRAY(structname, fieldname) pb_arraysize(structname, fieldname[0]) + +#define PB_DATA_SIZE_STATIC(htype, structname, fieldname) PB_DATA_SIZE_ ## htype(structname, fieldname) +#define PB_DATA_SIZE_POINTER(htype, structname, fieldname) PB_DATA_SIZE_PTR_ ## htype(structname, fieldname) +#define PB_DATA_SIZE_CALLBACK(htype, structname, fieldname) PB_DATA_SIZE_CB_ ## htype(structname, fieldname) +#define PB_DATA_SIZE_REQUIRED(structname, fieldname) pb_membersize(structname, fieldname) +#define PB_DATA_SIZE_SINGULAR(structname, fieldname) pb_membersize(structname, fieldname) +#define PB_DATA_SIZE_OPTIONAL(structname, fieldname) pb_membersize(structname, fieldname) +#define PB_DATA_SIZE_ONEOF(structname, fieldname) pb_membersize(structname, PB_ONEOF_NAME(FULL, fieldname)) +#define PB_DATA_SIZE_REPEATED(structname, fieldname) pb_membersize(structname, fieldname[0]) +#define PB_DATA_SIZE_FIXARRAY(structname, fieldname) pb_membersize(structname, fieldname[0]) +#define PB_DATA_SIZE_PTR_REQUIRED(structname, fieldname) pb_membersize(structname, fieldname[0]) +#define PB_DATA_SIZE_PTR_SINGULAR(structname, fieldname) pb_membersize(structname, fieldname[0]) +#define PB_DATA_SIZE_PTR_OPTIONAL(structname, fieldname) pb_membersize(structname, fieldname[0]) +#define PB_DATA_SIZE_PTR_ONEOF(structname, fieldname) pb_membersize(structname, PB_ONEOF_NAME(FULL, fieldname)[0]) +#define PB_DATA_SIZE_PTR_REPEATED(structname, fieldname) pb_membersize(structname, fieldname[0]) +#define PB_DATA_SIZE_PTR_FIXARRAY(structname, fieldname) pb_membersize(structname, fieldname[0][0]) +#define PB_DATA_SIZE_CB_REQUIRED(structname, fieldname) pb_membersize(structname, fieldname) +#define PB_DATA_SIZE_CB_SINGULAR(structname, fieldname) pb_membersize(structname, fieldname) +#define PB_DATA_SIZE_CB_OPTIONAL(structname, fieldname) pb_membersize(structname, fieldname) +#define PB_DATA_SIZE_CB_ONEOF(structname, fieldname) pb_membersize(structname, PB_ONEOF_NAME(FULL, fieldname)) +#define PB_DATA_SIZE_CB_REPEATED(structname, fieldname) pb_membersize(structname, fieldname) +#define PB_DATA_SIZE_CB_FIXARRAY(structname, fieldname) pb_membersize(structname, fieldname) + +#define PB_ONEOF_NAME(type, tuple) PB_EXPAND(PB_ONEOF_NAME_ ## type tuple) +#define PB_ONEOF_NAME_UNION(unionname,membername,fullname) unionname +#define PB_ONEOF_NAME_MEMBER(unionname,membername,fullname) membername +#define PB_ONEOF_NAME_FULL(unionname,membername,fullname) fullname + +#define PB_GEN_SUBMSG_INFO(structname, atype, htype, ltype, fieldname, tag) \ + PB_SUBMSG_INFO_ ## htype(ltype, structname, fieldname) + +#define PB_SUBMSG_INFO_REQUIRED(ltype, structname, fieldname) PB_SUBMSG_INFO_ ## ltype(structname ## _ ## fieldname ## _MSGTYPE) +#define PB_SUBMSG_INFO_SINGULAR(ltype, structname, fieldname) PB_SUBMSG_INFO_ ## ltype(structname ## _ ## fieldname ## _MSGTYPE) +#define PB_SUBMSG_INFO_OPTIONAL(ltype, structname, fieldname) PB_SUBMSG_INFO_ ## ltype(structname ## _ ## fieldname ## _MSGTYPE) +#define PB_SUBMSG_INFO_ONEOF(ltype, structname, fieldname) PB_SUBMSG_INFO_ONEOF2(ltype, structname, PB_ONEOF_NAME(UNION, fieldname), PB_ONEOF_NAME(MEMBER, fieldname)) +#define PB_SUBMSG_INFO_ONEOF2(ltype, structname, unionname, membername) PB_SUBMSG_INFO_ONEOF3(ltype, structname, unionname, membername) +#define PB_SUBMSG_INFO_ONEOF3(ltype, structname, unionname, membername) PB_SUBMSG_INFO_ ## ltype(structname ## _ ## unionname ## _ ## membername ## _MSGTYPE) +#define PB_SUBMSG_INFO_REPEATED(ltype, structname, fieldname) PB_SUBMSG_INFO_ ## ltype(structname ## _ ## fieldname ## _MSGTYPE) +#define PB_SUBMSG_INFO_FIXARRAY(ltype, structname, fieldname) PB_SUBMSG_INFO_ ## ltype(structname ## _ ## fieldname ## _MSGTYPE) +#define PB_SUBMSG_INFO_BOOL(t) +#define PB_SUBMSG_INFO_BYTES(t) +#define PB_SUBMSG_INFO_DOUBLE(t) +#define PB_SUBMSG_INFO_ENUM(t) +#define PB_SUBMSG_INFO_UENUM(t) +#define PB_SUBMSG_INFO_FIXED32(t) +#define PB_SUBMSG_INFO_FIXED64(t) +#define PB_SUBMSG_INFO_FLOAT(t) +#define PB_SUBMSG_INFO_INT32(t) +#define PB_SUBMSG_INFO_INT64(t) +#define PB_SUBMSG_INFO_MESSAGE(t) PB_SUBMSG_DESCRIPTOR(t) +#define PB_SUBMSG_INFO_MSG_W_CB(t) PB_SUBMSG_DESCRIPTOR(t) +#define PB_SUBMSG_INFO_SFIXED32(t) +#define PB_SUBMSG_INFO_SFIXED64(t) +#define PB_SUBMSG_INFO_SINT32(t) +#define PB_SUBMSG_INFO_SINT64(t) +#define PB_SUBMSG_INFO_STRING(t) +#define PB_SUBMSG_INFO_UINT32(t) +#define PB_SUBMSG_INFO_UINT64(t) +#define PB_SUBMSG_INFO_EXTENSION(t) +#define PB_SUBMSG_INFO_FIXED_LENGTH_BYTES(t) +#define PB_SUBMSG_DESCRIPTOR(t) &(t ## _msg), + +/* The field descriptors use a variable width format, with width of either + * 1, 2, 4 or 8 of 32-bit words. The two lowest bytes of the first byte always + * encode the descriptor size, 6 lowest bits of field tag number, and 8 bits + * of the field type. + * + * Descriptor size is encoded as 0 = 1 word, 1 = 2 words, 2 = 4 words, 3 = 8 words. + * + * Formats, listed starting with the least significant bit of the first word. + * 1 word: [2-bit len] [6-bit tag] [8-bit type] [8-bit data_offset] [4-bit size_offset] [4-bit data_size] + * + * 2 words: [2-bit len] [6-bit tag] [8-bit type] [12-bit array_size] [4-bit size_offset] + * [16-bit data_offset] [12-bit data_size] [4-bit tag>>6] + * + * 4 words: [2-bit len] [6-bit tag] [8-bit type] [16-bit array_size] + * [8-bit size_offset] [24-bit tag>>6] + * [32-bit data_offset] + * [32-bit data_size] + * + * 8 words: [2-bit len] [6-bit tag] [8-bit type] [16-bit reserved] + * [8-bit size_offset] [24-bit tag>>6] + * [32-bit data_offset] + * [32-bit data_size] + * [32-bit array_size] + * [32-bit reserved] + * [32-bit reserved] + * [32-bit reserved] + */ + +#define PB_FIELDINFO_1(tag, type, data_offset, data_size, size_offset, array_size) \ + (0 | (((tag) << 2) & 0xFF) | ((type) << 8) | (((uint32_t)(data_offset) & 0xFF) << 16) | \ + (((uint32_t)(size_offset) & 0x0F) << 24) | (((uint32_t)(data_size) & 0x0F) << 28)), + +#define PB_FIELDINFO_2(tag, type, data_offset, data_size, size_offset, array_size) \ + (1 | (((tag) << 2) & 0xFF) | ((type) << 8) | (((uint32_t)(array_size) & 0xFFF) << 16) | (((uint32_t)(size_offset) & 0x0F) << 28)), \ + (((uint32_t)(data_offset) & 0xFFFF) | (((uint32_t)(data_size) & 0xFFF) << 16) | (((uint32_t)(tag) & 0x3c0) << 22)), + +#define PB_FIELDINFO_4(tag, type, data_offset, data_size, size_offset, array_size) \ + (2 | (((tag) << 2) & 0xFF) | ((type) << 8) | (((uint32_t)(array_size) & 0xFFFF) << 16)), \ + ((uint32_t)(int8_t)(size_offset) | (((uint32_t)(tag) << 2) & 0xFFFFFF00)), \ + (data_offset), (data_size), + +#define PB_FIELDINFO_8(tag, type, data_offset, data_size, size_offset, array_size) \ + (3 | (((tag) << 2) & 0xFF) | ((type) << 8)), \ + ((uint32_t)(int8_t)(size_offset) | (((uint32_t)(tag) << 2) & 0xFFFFFF00)), \ + (data_offset), (data_size), (array_size), 0, 0, 0, + +/* These assertions verify that the field information fits in the allocated space. + * The generator tries to automatically determine the correct width that can fit all + * data associated with a message. These asserts will fail only if there has been a + * problem in the automatic logic - this may be worth reporting as a bug. As a workaround, + * you can increase the descriptor width by defining PB_FIELDINFO_WIDTH or by setting + * descriptorsize option in .options file. + */ +#define PB_FITS(value,bits) ((uint32_t)(value) < ((uint32_t)1<2GB messages with nanopb anyway. + */ +#define PB_FIELDINFO_ASSERT_4(tag, type, data_offset, data_size, size_offset, array_size) \ + PB_STATIC_ASSERT(PB_FITS(tag,30) && PB_FITS(data_offset,31) && PB_FITS((int8_t)size_offset,8) && PB_FITS(data_size,31) && PB_FITS(array_size,16), FIELDINFO_DOES_NOT_FIT_width4_field ## tag) + +#define PB_FIELDINFO_ASSERT_8(tag, type, data_offset, data_size, size_offset, array_size) \ + PB_STATIC_ASSERT(PB_FITS(tag,30) && PB_FITS(data_offset,31) && PB_FITS((int8_t)size_offset,8) && PB_FITS(data_size,31) && PB_FITS(array_size,31), FIELDINFO_DOES_NOT_FIT_width8_field ## tag) +#endif + + +/* Automatic picking of FIELDINFO width: + * Uses width 1 when possible, otherwise resorts to width 2. + */ + +#ifndef PB_FIELDINFO_WIDTH +#define PB_FIELDINFO_WIDTH_AUTO(atype, htype, ltype) PB_FIELDINFO_WIDTH_ ## atype(htype, ltype) +#define PB_FIELDINFO_WIDTH_STATIC(htype, ltype) PB_FIELDINFO_WIDTH_ ## htype(ltype) +#define PB_FIELDINFO_WIDTH_POINTER(htype, ltype) PB_FIELDINFO_WIDTH_ ## htype(ltype) +#define PB_FIELDINFO_WIDTH_CALLBACK(htype, ltype) 2 +#define PB_FIELDINFO_WIDTH_REQUIRED(ltype) PB_FIELDINFO_WIDTH_ ## ltype +#define PB_FIELDINFO_WIDTH_SINGULAR(ltype) PB_FIELDINFO_WIDTH_ ## ltype +#define PB_FIELDINFO_WIDTH_OPTIONAL(ltype) PB_FIELDINFO_WIDTH_ ## ltype +#define PB_FIELDINFO_WIDTH_ONEOF(ltype) PB_FIELDINFO_WIDTH_ ## ltype +#define PB_FIELDINFO_WIDTH_REPEATED(ltype) 2 +#define PB_FIELDINFO_WIDTH_FIXARRAY(ltype) 2 +#define PB_FIELDINFO_WIDTH_BOOL 1 +#define PB_FIELDINFO_WIDTH_BYTES 2 +#define PB_FIELDINFO_WIDTH_DOUBLE 1 +#define PB_FIELDINFO_WIDTH_ENUM 1 +#define PB_FIELDINFO_WIDTH_UENUM 1 +#define PB_FIELDINFO_WIDTH_FIXED32 1 +#define PB_FIELDINFO_WIDTH_FIXED64 1 +#define PB_FIELDINFO_WIDTH_FLOAT 1 +#define PB_FIELDINFO_WIDTH_INT32 1 +#define PB_FIELDINFO_WIDTH_INT64 1 +#define PB_FIELDINFO_WIDTH_MESSAGE 2 +#define PB_FIELDINFO_WIDTH_MSG_W_CB 2 +#define PB_FIELDINFO_WIDTH_SFIXED32 1 +#define PB_FIELDINFO_WIDTH_SFIXED64 1 +#define PB_FIELDINFO_WIDTH_SINT32 1 +#define PB_FIELDINFO_WIDTH_SINT64 1 +#define PB_FIELDINFO_WIDTH_STRING 2 +#define PB_FIELDINFO_WIDTH_UINT32 1 +#define PB_FIELDINFO_WIDTH_UINT64 1 +#define PB_FIELDINFO_WIDTH_EXTENSION 1 +#define PB_FIELDINFO_WIDTH_FIXED_LENGTH_BYTES 2 +#else +#define PB_FIELDINFO_WIDTH_AUTO(atype, htype, ltype) PB_FIELDINFO_WIDTH +#endif + +/* The mapping from protobuf types to LTYPEs is done using these macros. */ +#define PB_LTYPE_MAP_BOOL PB_LTYPE_BOOL +#define PB_LTYPE_MAP_BYTES PB_LTYPE_BYTES +#define PB_LTYPE_MAP_DOUBLE PB_LTYPE_FIXED64 +#define PB_LTYPE_MAP_ENUM PB_LTYPE_VARINT +#define PB_LTYPE_MAP_UENUM PB_LTYPE_UVARINT +#define PB_LTYPE_MAP_FIXED32 PB_LTYPE_FIXED32 +#define PB_LTYPE_MAP_FIXED64 PB_LTYPE_FIXED64 +#define PB_LTYPE_MAP_FLOAT PB_LTYPE_FIXED32 +#define PB_LTYPE_MAP_INT32 PB_LTYPE_VARINT +#define PB_LTYPE_MAP_INT64 PB_LTYPE_VARINT +#define PB_LTYPE_MAP_MESSAGE PB_LTYPE_SUBMESSAGE +#define PB_LTYPE_MAP_MSG_W_CB PB_LTYPE_SUBMSG_W_CB +#define PB_LTYPE_MAP_SFIXED32 PB_LTYPE_FIXED32 +#define PB_LTYPE_MAP_SFIXED64 PB_LTYPE_FIXED64 +#define PB_LTYPE_MAP_SINT32 PB_LTYPE_SVARINT +#define PB_LTYPE_MAP_SINT64 PB_LTYPE_SVARINT +#define PB_LTYPE_MAP_STRING PB_LTYPE_STRING +#define PB_LTYPE_MAP_UINT32 PB_LTYPE_UVARINT +#define PB_LTYPE_MAP_UINT64 PB_LTYPE_UVARINT +#define PB_LTYPE_MAP_EXTENSION PB_LTYPE_EXTENSION +#define PB_LTYPE_MAP_FIXED_LENGTH_BYTES PB_LTYPE_FIXED_LENGTH_BYTES + +/* These macros are used for giving out error messages. + * They are mostly a debugging aid; the main error information + * is the true/false return value from functions. + * Some code space can be saved by disabling the error + * messages if not used. + * + * PB_SET_ERROR() sets the error message if none has been set yet. + * msg must be a constant string literal. + * PB_GET_ERROR() always returns a pointer to a string. + * PB_RETURN_ERROR() sets the error and returns false from current + * function. + */ +#ifdef PB_NO_ERRMSG +#define PB_SET_ERROR(stream, msg) PB_UNUSED(stream) +#define PB_GET_ERROR(stream) "(errmsg disabled)" +#else +#define PB_SET_ERROR(stream, msg) (stream->errmsg = (stream)->errmsg ? (stream)->errmsg : (msg)) +#define PB_GET_ERROR(stream) ((stream)->errmsg ? (stream)->errmsg : "(none)") +#endif + +#define PB_RETURN_ERROR(stream, msg) return PB_SET_ERROR(stream, msg), false + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#ifdef __cplusplus +#if __cplusplus >= 201103L +#define PB_CONSTEXPR constexpr +#else // __cplusplus >= 201103L +#define PB_CONSTEXPR +#endif // __cplusplus >= 201103L + +#if __cplusplus >= 201703L +#define PB_INLINE_CONSTEXPR inline constexpr +#else // __cplusplus >= 201703L +#define PB_INLINE_CONSTEXPR PB_CONSTEXPR +#endif // __cplusplus >= 201703L + +namespace nanopb { +// Each type will be partially specialized by the generator. +template struct MessageDescriptor; +} // namespace nanopb +#endif /* __cplusplus */ + +#endif + diff --git a/utils/proto_test/otto_proto_test/Core/Inc/pb_common.h b/utils/proto_test/otto_proto_test/Core/Inc/pb_common.h new file mode 100644 index 0000000..47fa2c9 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Inc/pb_common.h @@ -0,0 +1,45 @@ +/* pb_common.h: Common support functions for pb_encode.c and pb_decode.c. + * These functions are rarely needed by applications directly. + */ + +#ifndef PB_COMMON_H_INCLUDED +#define PB_COMMON_H_INCLUDED + +#include "pb.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Initialize the field iterator structure to beginning. + * Returns false if the message type is empty. */ +bool pb_field_iter_begin(pb_field_iter_t *iter, const pb_msgdesc_t *desc, void *message); + +/* Get a field iterator for extension field. */ +bool pb_field_iter_begin_extension(pb_field_iter_t *iter, pb_extension_t *extension); + +/* Same as pb_field_iter_begin(), but for const message pointer. + * Note that the pointers in pb_field_iter_t will be non-const but shouldn't + * be written to when using these functions. */ +bool pb_field_iter_begin_const(pb_field_iter_t *iter, const pb_msgdesc_t *desc, const void *message); +bool pb_field_iter_begin_extension_const(pb_field_iter_t *iter, const pb_extension_t *extension); + +/* Advance the iterator to the next field. + * Returns false when the iterator wraps back to the first field. */ +bool pb_field_iter_next(pb_field_iter_t *iter); + +/* Advance the iterator until it points at a field with the given tag. + * Returns false if no such field exists. */ +bool pb_field_iter_find(pb_field_iter_t *iter, uint32_t tag); + +#ifdef PB_VALIDATE_UTF8 +/* Validate UTF-8 text string */ +bool pb_validate_utf8(const char *s); +#endif + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif + diff --git a/utils/proto_test/otto_proto_test/Core/Inc/pb_decode.h b/utils/proto_test/otto_proto_test/Core/Inc/pb_decode.h new file mode 100644 index 0000000..b64d95a --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Inc/pb_decode.h @@ -0,0 +1,193 @@ +/* pb_decode.h: Functions to decode protocol buffers. Depends on pb_decode.c. + * The main function is pb_decode. You also need an input stream, and the + * field descriptions created by nanopb_generator.py. + */ + +#ifndef PB_DECODE_H_INCLUDED +#define PB_DECODE_H_INCLUDED + +#include "pb.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Structure for defining custom input streams. You will need to provide + * a callback function to read the bytes from your storage, which can be + * for example a file or a network socket. + * + * The callback must conform to these rules: + * + * 1) Return false on IO errors. This will cause decoding to abort. + * 2) You can use state to store your own data (e.g. buffer pointer), + * and rely on pb_read to verify that no-body reads past bytes_left. + * 3) Your callback may be used with substreams, in which case bytes_left + * is different than from the main stream. Don't use bytes_left to compute + * any pointers. + */ +struct pb_istream_s +{ +#ifdef PB_BUFFER_ONLY + /* Callback pointer is not used in buffer-only configuration. + * Having an int pointer here allows binary compatibility but + * gives an error if someone tries to assign callback function. + */ + int *callback; +#else + bool (*callback)(pb_istream_t *stream, pb_byte_t *buf, size_t count); +#endif + + void *state; /* Free field for use by callback implementation */ + size_t bytes_left; + +#ifndef PB_NO_ERRMSG + const char *errmsg; +#endif +}; + +#ifndef PB_NO_ERRMSG +#define PB_ISTREAM_EMPTY {0,0,0,0} +#else +#define PB_ISTREAM_EMPTY {0,0,0} +#endif + +/*************************** + * Main decoding functions * + ***************************/ + +/* Decode a single protocol buffers message from input stream into a C structure. + * Returns true on success, false on any failure. + * The actual struct pointed to by dest must match the description in fields. + * Callback fields of the destination structure must be initialized by caller. + * All other fields will be initialized by this function. + * + * Example usage: + * MyMessage msg = {}; + * uint8_t buffer[64]; + * pb_istream_t stream; + * + * // ... read some data into buffer ... + * + * stream = pb_istream_from_buffer(buffer, count); + * pb_decode(&stream, MyMessage_fields, &msg); + */ +bool pb_decode(pb_istream_t *stream, const pb_msgdesc_t *fields, void *dest_struct); + +/* Extended version of pb_decode, with several options to control + * the decoding process: + * + * PB_DECODE_NOINIT: Do not initialize the fields to default values. + * This is slightly faster if you do not need the default + * values and instead initialize the structure to 0 using + * e.g. memset(). This can also be used for merging two + * messages, i.e. combine already existing data with new + * values. + * + * PB_DECODE_DELIMITED: Input message starts with the message size as varint. + * Corresponds to parseDelimitedFrom() in Google's + * protobuf API. + * + * PB_DECODE_NULLTERMINATED: Stop reading when field tag is read as 0. This allows + * reading null terminated messages. + * NOTE: Until nanopb-0.4.0, pb_decode() also allows + * null-termination. This behaviour is not supported in + * most other protobuf implementations, so PB_DECODE_DELIMITED + * is a better option for compatibility. + * + * Multiple flags can be combined with bitwise or (| operator) + */ +#define PB_DECODE_NOINIT 0x01U +#define PB_DECODE_DELIMITED 0x02U +#define PB_DECODE_NULLTERMINATED 0x04U +bool pb_decode_ex(pb_istream_t *stream, const pb_msgdesc_t *fields, void *dest_struct, unsigned int flags); + +/* Defines for backwards compatibility with code written before nanopb-0.4.0 */ +#define pb_decode_noinit(s,f,d) pb_decode_ex(s,f,d, PB_DECODE_NOINIT) +#define pb_decode_delimited(s,f,d) pb_decode_ex(s,f,d, PB_DECODE_DELIMITED) +#define pb_decode_delimited_noinit(s,f,d) pb_decode_ex(s,f,d, PB_DECODE_DELIMITED | PB_DECODE_NOINIT) +#define pb_decode_nullterminated(s,f,d) pb_decode_ex(s,f,d, PB_DECODE_NULLTERMINATED) + +#ifdef PB_ENABLE_MALLOC +/* Release any allocated pointer fields. If you use dynamic allocation, you should + * call this for any successfully decoded message when you are done with it. If + * pb_decode() returns with an error, the message is already released. + */ +void pb_release(const pb_msgdesc_t *fields, void *dest_struct); +#endif + + +/************************************** + * Functions for manipulating streams * + **************************************/ + +/* Create an input stream for reading from a memory buffer. + * + * Alternatively, you can use a custom stream that reads directly from e.g. + * a file or a network socket. + */ +pb_istream_t pb_istream_from_buffer(const pb_byte_t *buf, size_t bufsize); + +/* Function to read from a pb_istream_t. You can use this if you need to + * read some custom header data, or to read data in field callbacks. + */ +bool pb_read(pb_istream_t *stream, pb_byte_t *buf, size_t count); + + +/************************************************ + * Helper functions for writing field callbacks * + ************************************************/ + +/* Decode the tag for the next field in the stream. Gives the wire type and + * field tag. At end of the message, returns false and sets eof to true. */ +bool pb_decode_tag(pb_istream_t *stream, pb_wire_type_t *wire_type, uint32_t *tag, bool *eof); + +/* Skip the field payload data, given the wire type. */ +bool pb_skip_field(pb_istream_t *stream, pb_wire_type_t wire_type); + +/* Decode an integer in the varint format. This works for enum, int32, + * int64, uint32 and uint64 field types. */ +#ifndef PB_WITHOUT_64BIT +bool pb_decode_varint(pb_istream_t *stream, uint64_t *dest); +#else +#define pb_decode_varint pb_decode_varint32 +#endif + +/* Decode an integer in the varint format. This works for enum, int32, + * and uint32 field types. */ +bool pb_decode_varint32(pb_istream_t *stream, uint32_t *dest); + +/* Decode a bool value in varint format. */ +bool pb_decode_bool(pb_istream_t *stream, bool *dest); + +/* Decode an integer in the zig-zagged svarint format. This works for sint32 + * and sint64. */ +#ifndef PB_WITHOUT_64BIT +bool pb_decode_svarint(pb_istream_t *stream, int64_t *dest); +#else +bool pb_decode_svarint(pb_istream_t *stream, int32_t *dest); +#endif + +/* Decode a fixed32, sfixed32 or float value. You need to pass a pointer to + * a 4-byte wide C variable. */ +bool pb_decode_fixed32(pb_istream_t *stream, void *dest); + +#ifndef PB_WITHOUT_64BIT +/* Decode a fixed64, sfixed64 or double value. You need to pass a pointer to + * a 8-byte wide C variable. */ +bool pb_decode_fixed64(pb_istream_t *stream, void *dest); +#endif + +#ifdef PB_CONVERT_DOUBLE_FLOAT +/* Decode a double value into float variable. */ +bool pb_decode_double_as_float(pb_istream_t *stream, float *dest); +#endif + +/* Make a limited-length substream for reading a PB_WT_STRING field. */ +bool pb_make_string_substream(pb_istream_t *stream, pb_istream_t *substream); +bool pb_close_string_substream(pb_istream_t *stream, pb_istream_t *substream); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif diff --git a/utils/proto_test/otto_proto_test/Core/Inc/pb_encode.h b/utils/proto_test/otto_proto_test/Core/Inc/pb_encode.h new file mode 100644 index 0000000..88e246a --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Inc/pb_encode.h @@ -0,0 +1,185 @@ +/* pb_encode.h: Functions to encode protocol buffers. Depends on pb_encode.c. + * The main function is pb_encode. You also need an output stream, and the + * field descriptions created by nanopb_generator.py. + */ + +#ifndef PB_ENCODE_H_INCLUDED +#define PB_ENCODE_H_INCLUDED + +#include "pb.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Structure for defining custom output streams. You will need to provide + * a callback function to write the bytes to your storage, which can be + * for example a file or a network socket. + * + * The callback must conform to these rules: + * + * 1) Return false on IO errors. This will cause encoding to abort. + * 2) You can use state to store your own data (e.g. buffer pointer). + * 3) pb_write will update bytes_written after your callback runs. + * 4) Substreams will modify max_size and bytes_written. Don't use them + * to calculate any pointers. + */ +struct pb_ostream_s +{ +#ifdef PB_BUFFER_ONLY + /* Callback pointer is not used in buffer-only configuration. + * Having an int pointer here allows binary compatibility but + * gives an error if someone tries to assign callback function. + * Also, NULL pointer marks a 'sizing stream' that does not + * write anything. + */ + int *callback; +#else + bool (*callback)(pb_ostream_t *stream, const pb_byte_t *buf, size_t count); +#endif + void *state; /* Free field for use by callback implementation. */ + size_t max_size; /* Limit number of output bytes written (or use SIZE_MAX). */ + size_t bytes_written; /* Number of bytes written so far. */ + +#ifndef PB_NO_ERRMSG + const char *errmsg; +#endif +}; + +/*************************** + * Main encoding functions * + ***************************/ + +/* Encode a single protocol buffers message from C structure into a stream. + * Returns true on success, false on any failure. + * The actual struct pointed to by src_struct must match the description in fields. + * All required fields in the struct are assumed to have been filled in. + * + * Example usage: + * MyMessage msg = {}; + * uint8_t buffer[64]; + * pb_ostream_t stream; + * + * msg.field1 = 42; + * stream = pb_ostream_from_buffer(buffer, sizeof(buffer)); + * pb_encode(&stream, MyMessage_fields, &msg); + */ +bool pb_encode(pb_ostream_t *stream, const pb_msgdesc_t *fields, const void *src_struct); + +/* Extended version of pb_encode, with several options to control the + * encoding process: + * + * PB_ENCODE_DELIMITED: Prepend the length of message as a varint. + * Corresponds to writeDelimitedTo() in Google's + * protobuf API. + * + * PB_ENCODE_NULLTERMINATED: Append a null byte to the message for termination. + * NOTE: This behaviour is not supported in most other + * protobuf implementations, so PB_ENCODE_DELIMITED + * is a better option for compatibility. + */ +#define PB_ENCODE_DELIMITED 0x02U +#define PB_ENCODE_NULLTERMINATED 0x04U +bool pb_encode_ex(pb_ostream_t *stream, const pb_msgdesc_t *fields, const void *src_struct, unsigned int flags); + +/* Defines for backwards compatibility with code written before nanopb-0.4.0 */ +#define pb_encode_delimited(s,f,d) pb_encode_ex(s,f,d, PB_ENCODE_DELIMITED) +#define pb_encode_nullterminated(s,f,d) pb_encode_ex(s,f,d, PB_ENCODE_NULLTERMINATED) + +/* Encode the message to get the size of the encoded data, but do not store + * the data. */ +bool pb_get_encoded_size(size_t *size, const pb_msgdesc_t *fields, const void *src_struct); + +/************************************** + * Functions for manipulating streams * + **************************************/ + +/* Create an output stream for writing into a memory buffer. + * The number of bytes written can be found in stream.bytes_written after + * encoding the message. + * + * Alternatively, you can use a custom stream that writes directly to e.g. + * a file or a network socket. + */ +pb_ostream_t pb_ostream_from_buffer(pb_byte_t *buf, size_t bufsize); + +/* Pseudo-stream for measuring the size of a message without actually storing + * the encoded data. + * + * Example usage: + * MyMessage msg = {}; + * pb_ostream_t stream = PB_OSTREAM_SIZING; + * pb_encode(&stream, MyMessage_fields, &msg); + * printf("Message size is %d\n", stream.bytes_written); + */ +#ifndef PB_NO_ERRMSG +#define PB_OSTREAM_SIZING {0,0,0,0,0} +#else +#define PB_OSTREAM_SIZING {0,0,0,0} +#endif + +/* Function to write into a pb_ostream_t stream. You can use this if you need + * to append or prepend some custom headers to the message. + */ +bool pb_write(pb_ostream_t *stream, const pb_byte_t *buf, size_t count); + + +/************************************************ + * Helper functions for writing field callbacks * + ************************************************/ + +/* Encode field header based on type and field number defined in the field + * structure. Call this from the callback before writing out field contents. */ +bool pb_encode_tag_for_field(pb_ostream_t *stream, const pb_field_iter_t *field); + +/* Encode field header by manually specifing wire type. You need to use this + * if you want to write out packed arrays from a callback field. */ +bool pb_encode_tag(pb_ostream_t *stream, pb_wire_type_t wiretype, uint32_t field_number); + +/* Encode an integer in the varint format. + * This works for bool, enum, int32, int64, uint32 and uint64 field types. */ +#ifndef PB_WITHOUT_64BIT +bool pb_encode_varint(pb_ostream_t *stream, uint64_t value); +#else +bool pb_encode_varint(pb_ostream_t *stream, uint32_t value); +#endif + +/* Encode an integer in the zig-zagged svarint format. + * This works for sint32 and sint64. */ +#ifndef PB_WITHOUT_64BIT +bool pb_encode_svarint(pb_ostream_t *stream, int64_t value); +#else +bool pb_encode_svarint(pb_ostream_t *stream, int32_t value); +#endif + +/* Encode a string or bytes type field. For strings, pass strlen(s) as size. */ +bool pb_encode_string(pb_ostream_t *stream, const pb_byte_t *buffer, size_t size); + +/* Encode a fixed32, sfixed32 or float value. + * You need to pass a pointer to a 4-byte wide C variable. */ +bool pb_encode_fixed32(pb_ostream_t *stream, const void *value); + +#ifndef PB_WITHOUT_64BIT +/* Encode a fixed64, sfixed64 or double value. + * You need to pass a pointer to a 8-byte wide C variable. */ +bool pb_encode_fixed64(pb_ostream_t *stream, const void *value); +#endif + +#ifdef PB_CONVERT_DOUBLE_FLOAT +/* Encode a float value so that it appears like a double in the encoded + * message. */ +bool pb_encode_float_as_double(pb_ostream_t *stream, float value); +#endif + +/* Encode a submessage field. + * You need to pass the pb_field_t array and pointer to struct, just like + * with pb_encode(). This internally encodes the submessage twice, first to + * calculate message size and then to actually write it out. + */ +bool pb_encode_submessage(pb_ostream_t *stream, const pb_msgdesc_t *fields, const void *src_struct); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif diff --git a/utils/proto_test/otto_proto_test/Core/Inc/pid.h b/utils/proto_test/otto_proto_test/Core/Inc/pid.h new file mode 100644 index 0000000..7663f6b --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Inc/pid.h @@ -0,0 +1,84 @@ +#ifndef PID_H +#define PID_H + +#include "constants.h" + +class Pid { + public: + //PID constants + float kp_; + float ki_; + float kd_; + + float error_; + float setpoint_; + + //needed for integrative term + float error_sum_; + + //needed for derivative term + float previous_error_; + + int min_; + int max_; + + Pid(float kp, float ki, float kd) { + this->kp_ = kp; + this->ki_ = ki; + this->kd_ = kd; + + this->error_ = 0; + this->setpoint_ = 0; + + this->previous_error_ = 0; + this->error_sum_ = 0; + + this->min_ = -MAX_DUTY_CYCLE; + this->max_ = MAX_DUTY_CYCLE; + + } + + void config(float kp, float ki, float kd) { + this->kp_ = kp; + this->ki_ = ki; + this->kd_ = kd; + + this->error_ = 0; + this->setpoint_ = 0; + + this->previous_error_ = 0; + this->error_sum_ = 0; + + } + + void set(float setpoint) { + this->setpoint_ = setpoint; + } + + int update(float measure) { + + this->error_ = this->setpoint_ - measure; + + //proportional term + float output = this->error_ * this->kp_; + + //integral term without windup + error_sum_ += this->error_; + output += error_sum_ * this->ki_; + + //derivative term + output += (this->error_ - this->previous_error_) * kd_; + this->previous_error_ = this->error_; + + int integer_output = static_cast (output); + +// if(integer_output > this->max_) +// integer_output = this->max_; +// else if (integer_output < this->min_) +// integer_output = this->min_; + + return integer_output; + + } +}; +#endif diff --git a/utils/proto_test/otto_proto_test/Core/Inc/stm32f7xx_hal_conf.h b/utils/proto_test/otto_proto_test/Core/Inc/stm32f7xx_hal_conf.h new file mode 100644 index 0000000..de63831 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Inc/stm32f7xx_hal_conf.h @@ -0,0 +1,442 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f7xx_hal_conf.h. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_EXTI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define ART_ACCLERATOR_ENABLE 0U /* To enable instruction cache and prefetch */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f7xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32f7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32f7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Core/Inc/stm32f7xx_it.h b/utils/proto_test/otto_proto_test/Core/Inc/stm32f7xx_it.h new file mode 100644 index 0000000..f138f64 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Inc/stm32f7xx_it.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_IT_H +#define __STM32F7xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void TIM3_IRQHandler(void); +void EXTI15_10_IRQHandler(void); +void TIM6_DAC_IRQHandler(void); +void USART6_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Core/Inc/velocities.pb.h b/utils/proto_test/otto_proto_test/Core/Inc/velocities.pb.h new file mode 100644 index 0000000..fdede34 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Inc/velocities.pb.h @@ -0,0 +1,50 @@ +/* Automatically generated nanopb header */ +/* Generated by 0.4.1-dev */ + +#ifndef PB_VELOCITIES_PB_H_INCLUDED +#define PB_VELOCITIES_PB_H_INCLUDED +#include + +#if PB_PROTO_HEADER_VERSION != 40 +#error Regenerate this file with the current version of nanopb generator. +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* Struct definitions */ +typedef struct _Velocities { + float linear_vel; + float angular_vel; +} Velocities; + + +/* Initializer values for message structs */ +#define Velocities_init_default {0, 0} +#define Velocities_init_zero {0, 0} + +/* Field tags (for use in manual encoding/decoding) */ +#define Velocities_linear_vel_tag 1 +#define Velocities_angular_vel_tag 2 + +/* Struct field encoding specification for nanopb */ +#define Velocities_FIELDLIST(X, a) \ +X(a, STATIC, SINGULAR, FLOAT, linear_vel, 1) \ +X(a, STATIC, SINGULAR, FLOAT, angular_vel, 2) +#define Velocities_CALLBACK NULL +#define Velocities_DEFAULT NULL + +extern const pb_msgdesc_t Velocities_msg; + +/* Defines for backwards compatibility with code written before nanopb-0.4.0 */ +#define Velocities_fields &Velocities_msg + +/* Maximum encoded size of messages (where known) */ +#define Velocities_size 10 + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif diff --git a/utils/proto_test/otto_proto_test/Core/Src/encoder.cpp b/utils/proto_test/otto_proto_test/Core/Src/encoder.cpp new file mode 100644 index 0000000..5deedf6 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Src/encoder.cpp @@ -0,0 +1,50 @@ +#include "encoder.h" + +//Encoder::Encoder(TIM_HandleTypeDef *timer, float wheel_circ) { +// timer_ = timer; +// wheel_circumference_ = wheel_circ; +// +//} + +Encoder::Encoder(TIM_HandleTypeDef *timer, int ticks_per_meter) { + timer_ = timer; + ticks_per_meter_ = ticks_per_meter; + +} + +void Encoder::Setup() { + HAL_TIM_Encoder_Start(timer_, TIM_CHANNEL_ALL); + this->ResetCount(); + this->previous_millis_ = 0; + this->current_millis_ = HAL_GetTick(); +} + +void Encoder::UpdateValues() { + this->previous_millis_ = this->current_millis_; + this->current_millis_ = HAL_GetTick(); + this->ticks_ = this->GetCount(); + this->ResetCount(); +} + +//float Encoder::GetMeters() { +// float meters = ((float) this->ticks_ * this->wheel_circumference_) +// / TICKS_PER_REVOLUTION; +// return meters; +//} + +float Encoder::GetMeters() { + float meters = (((float) this->ticks_) / this->ticks_per_meter_); + return meters; +} + + +float Encoder::GetLinearVelocity() { + this->UpdateValues(); + float meters = this->GetMeters(); + float deltaTime = this->current_millis_ - this->previous_millis_; + if (deltaTime == 0) + return 0; + float linear_velocity = (meters / (deltaTime / 1000)); + return linear_velocity; +} + diff --git a/utils/proto_test/otto_proto_test/Core/Src/main.cpp b/utils/proto_test/otto_proto_test/Core/Src/main.cpp new file mode 100644 index 0000000..0327787 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Src/main.cpp @@ -0,0 +1,712 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +#include "encoder.h" +#include "odometry.h" +#include "motor_controller.h" +#include "pid.h" +#include "communication_utils.h" +#include "constants.h" + +#include +#include +#include "velocities.pb.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +TIM_HandleTypeDef htim2; +TIM_HandleTypeDef htim3; +TIM_HandleTypeDef htim4; +TIM_HandleTypeDef htim5; +TIM_HandleTypeDef htim6; + +UART_HandleTypeDef huart6; + +/* USER CODE BEGIN PV */ + +//Odometry +Encoder right_encoder = Encoder(&htim5, RIGHT_TICKS_PER_METER); +Encoder left_encoder = Encoder(&htim2, LEFT_TICKS_PER_METER); +Odometry odom = Odometry(); +float left_velocity = 0; +float right_velocity = 0; + +//PID +Pid left_pid(0, 0, 0); +Pid right_pid(0, 0, 0); +Pid cross_pid(0, 0, 0); +float left_setpoint; +float right_setpoint; +float cross_setpoint; +int left_dutycycle; +int right_dutycycle; + +//MotorController +MotorController right_motor(sleep1_GPIO_Port, +sleep1_Pin, + dir1_GPIO_Port, + dir1_Pin, + &htim4, + TIM_CHANNEL_4); +MotorController left_motor(sleep2_GPIO_Port, +sleep2_Pin, + dir2_GPIO_Port, + dir2_Pin, + &htim4, + TIM_CHANNEL_3); + +//Communication +uint8_t *tx_buffer; +uint8_t *rx_buffer; +velocity_msg input_msg; +ticks_msg output_msg; + +//user button variables +int previous_millis = 0; +int current_millis = 0; +bool debounce = true; + +//test stuff +float mode = 0; //0 for setup, 1 go, 2 send data +int left_ticks = 0; +int right_ticks = 0; + +//protobuffers +Velocities vel_output; +uint8_t buffer_tx[10]; +pb_ostream_t stream_tx; + +Velocities vel_input; +uint8_t buffer_rx[10]; +pb_istream_t stream_rx; + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_TIM2_Init(void); +static void MX_TIM3_Init(void); +static void MX_TIM4_Init(void); +static void MX_TIM5_Init(void); +static void MX_USART6_UART_Init(void); +static void MX_TIM6_Init(void); +static void MX_NVIC_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) { + /* USER CODE BEGIN 1 */ + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_TIM2_Init(); + MX_TIM3_Init(); + MX_TIM4_Init(); + MX_TIM5_Init(); + MX_USART6_UART_Init(); + MX_TIM6_Init(); + + /* Initialize interrupts */ + MX_NVIC_Init(); + /* USER CODE BEGIN 2 */ + + left_encoder.Setup(); + right_encoder.Setup(); + + left_motor.setup(); + right_motor.setup(); + left_motor.coast(); + right_motor.coast(); + + left_pid.config(180, 200, 0); + right_pid.config(185, 195, 0); + cross_pid.config(50, 20, 0); + + tx_buffer = (uint8_t*) &output_msg; + rx_buffer = (uint8_t*) &input_msg; + + vel_output.angular_vel = 1; + vel_output.linear_vel = 2; + stream_tx = pb_ostream_from_buffer(buffer_tx, sizeof(buffer_tx)); + + //Enables UART RX interrupt + HAL_UART_Receive_IT(&huart6, buffer_rx, 10); + HAL_TIM_Base_Start_IT(&htim6); + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) { + + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval Nonewheel_circumference_ + */ +void SystemClock_Config(void) { + RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; + RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 }; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) { + Error_Handler(); + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6; + PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } +} + +/** + * @brief NVIC Configuration. + * @retval None + */ +static void MX_NVIC_Init(void) { + /* TIM3_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(TIM3_IRQn, 2, 1); + HAL_NVIC_EnableIRQ(TIM3_IRQn); + /* TIM6_DAC_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 2, 2); + HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); + /* USART6_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(USART6_IRQn, 1, 0); + HAL_NVIC_EnableIRQ(USART6_IRQn); +} + +/** + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) { + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_Encoder_InitTypeDef sConfig = { 0 }; + TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + htim2.Init.Prescaler = 0; + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + htim2.Init.Period = 4294967295; + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + sConfig.EncoderMode = TIM_ENCODERMODE_TI12; + sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; + sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; + sConfig.IC1Prescaler = TIM_ICPSC_DIV1; + sConfig.IC1Filter = 0; + sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; + sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; + sConfig.IC2Prescaler = TIM_ICPSC_DIV1; + sConfig.IC2Filter = 0; + if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK) { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + +} + +/** + * @brief TIM3 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM3_Init(void) { + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = { 0 }; + TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + htim3.Instance = TIM3; + htim3.Init.Prescaler = 999; + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + htim3.Init.Period = 159; + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim3) != HAL_OK) { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + +} + +/** + * @brief TIM4 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM4_Init(void) { + + /* USER CODE BEGIN TIM4_Init 0 */ + + /* USER CODE END TIM4_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = { 0 }; + TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + TIM_OC_InitTypeDef sConfigOC = { 0 }; + + /* USER CODE BEGIN TIM4_Init 1 */ + + /* USER CODE END TIM4_Init 1 */ + htim4.Instance = TIM4; + htim4.Init.Prescaler = 0; + htim4.Init.CounterMode = TIM_COUNTERMODE_UP; + htim4.Init.Period = 799; + htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim4) != HAL_OK) { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) { + Error_Handler(); + } + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN TIM4_Init 2 */ + + /* USER CODE END TIM4_Init 2 */ + HAL_TIM_MspPostInit(&htim4); + +} + +/** + * @brief TIM5 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM5_Init(void) { + + /* USER CODE BEGIN TIM5_Init 0 */ + + /* USER CODE END TIM5_Init 0 */ + + TIM_Encoder_InitTypeDef sConfig = { 0 }; + TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + + /* USER CODE BEGIN TIM5_Init 1 */ + + /* USER CODE END TIM5_Init 1 */ + htim5.Instance = TIM5; + htim5.Init.Prescaler = 0; + htim5.Init.CounterMode = TIM_COUNTERMODE_UP; + htim5.Init.Period = 4294967295; + htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + sConfig.EncoderMode = TIM_ENCODERMODE_TI12; + sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; + sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; + sConfig.IC1Prescaler = TIM_ICPSC_DIV1; + sConfig.IC1Filter = 0; + sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; + sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; + sConfig.IC2Prescaler = TIM_ICPSC_DIV1; + sConfig.IC2Filter = 0; + if (HAL_TIM_Encoder_Init(&htim5, &sConfig) != HAL_OK) { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN TIM5_Init 2 */ + + /* USER CODE END TIM5_Init 2 */ + +} + +/** + * @brief TIM6 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM6_Init(void) { + + /* USER CODE BEGIN TIM6_Init 0 */ + + /* USER CODE END TIM6_Init 0 */ + + TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + + /* USER CODE BEGIN TIM6_Init 1 */ + + /* USER CODE END TIM6_Init 1 */ + htim6.Instance = TIM6; + htim6.Init.Prescaler = 9999; + htim6.Init.CounterMode = TIM_COUNTERMODE_UP; + htim6.Init.Period = 799; + htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim6) != HAL_OK) { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN TIM6_Init 2 */ + + /* USER CODE END TIM6_Init 2 */ + +} + +/** + * @brief USART6 Initialization Function + * @param None + * @retval None + */ +static void MX_USART6_UART_Init(void) { + + /* USER CODE BEGIN USART6_Init 0 */ + + /* USER CODE END USART6_Init 0 */ + + /* USER CODE BEGIN USART6_Init 1 */ + + /* USER CODE END USART6_Init 1 */ + huart6.Instance = USART6; + huart6.Init.BaudRate = 115200; + huart6.Init.WordLength = UART_WORDLENGTH_8B; + huart6.Init.StopBits = UART_STOPBITS_1; + huart6.Init.Parity = UART_PARITY_NONE; + huart6.Init.Mode = UART_MODE_TX_RX; + huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart6.Init.OverSampling = UART_OVERSAMPLING_16; + huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart6) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN USART6_Init 2 */ + + /* USER CODE END USART6_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) { + GPIO_InitTypeDef GPIO_InitStruct = { 0 }; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOF, dir2_Pin | dir1_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOF, sleep2_Pin | sleep1_Pin, GPIO_PIN_SET); + + /*Configure GPIO pin : user_button_Pin */ + GPIO_InitStruct.Pin = user_button_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(user_button_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : current2_Pin */ + GPIO_InitStruct.Pin = current2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(current2_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : current1_Pin */ + GPIO_InitStruct.Pin = current1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(current1_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : fault2_Pin */ + GPIO_InitStruct.Pin = fault2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(fault2_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : dir2_Pin dir1_Pin */ + GPIO_InitStruct.Pin = dir2_Pin | dir1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /*Configure GPIO pins : sleep2_Pin sleep1_Pin */ + GPIO_InitStruct.Pin = sleep2_Pin | sleep1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /*Configure GPIO pin : fault1_Pin */ + GPIO_InitStruct.Pin = fault1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(fault1_GPIO_Port, &GPIO_InitStruct); + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); + +} + +/* USER CODE BEGIN 4 */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { + + //TIMER 100Hz PID control + if (htim->Instance == TIM3) { + + left_velocity = left_encoder.GetLinearVelocity(); + left_dutycycle = left_pid.update(left_velocity); + left_motor.set_speed(left_dutycycle); + + right_velocity = right_encoder.GetLinearVelocity(); + right_dutycycle = right_pid.update(right_velocity); + right_motor.set_speed(right_dutycycle); + + float difference = left_velocity - right_velocity; + + int cross_dutycycle = cross_pid.update(difference); + + left_dutycycle += cross_dutycycle; + right_dutycycle -= cross_dutycycle; + + } + + //TIMER 2Hz Transmit + if (htim->Instance == TIM6) { + + odom.UpdateValuesFromWheels(left_encoder.GetLinearVelocity(), + right_encoder.GetLinearVelocity()); + + vel_output.linear_vel = odom.GetLinearVelocity(); + vel_output.angular_vel = odom.GetAngularVelocity(); + + stream_tx = pb_ostream_from_buffer(buffer_tx, sizeof(buffer_tx)); + + pb_encode(&stream_tx, Velocities_fields, &vel_output); + + HAL_UART_Transmit(&huart6, buffer_tx, 10, 100); + } +} + +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *UartHandle) { + + pb_istream_t stream = pb_istream_from_buffer(buffer_rx, 10); + + bool status = pb_decode(&stream, Velocities_fields, &vel_input); + + // if decoding went ok + if (status) { + + odom.UpdateValuesFromVel(vel_input.linear_vel, vel_input.angular_vel); + + left_setpoint = odom.GetLeftVelocity(); + right_setpoint = odom.GetRightVelocity(); + + left_pid.set(left_setpoint); + right_pid.set(right_setpoint); + + cross_setpoint = left_setpoint - right_setpoint; + cross_pid.set(cross_setpoint); + } + + HAL_UART_Receive_IT(&huart6, buffer_rx, 10); + +} + +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { + //Blue user button + if (GPIO_Pin == GPIO_PIN_13) { + previous_millis = current_millis; + current_millis = HAL_GetTick(); + if (current_millis - previous_millis < 500) + debounce = false; + else + debounce = true; + if (mode == 0 && debounce) { + mode = 1; + //Enables TIM3 interrupt (used for PID control) + HAL_TIM_Base_Start_IT(&htim3); + } + } +} + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) { + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameduty_cycleters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Core/Src/pb_common.c b/utils/proto_test/otto_proto_test/Core/Src/pb_common.c new file mode 100644 index 0000000..2bbbeb8 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Src/pb_common.c @@ -0,0 +1,336 @@ +/* pb_common.c: Common support functions for pb_encode.c and pb_decode.c. + * + * 2014 Petteri Aimonen + */ + +#include "pb_common.h" + +static bool load_descriptor_values(pb_field_iter_t *iter) +{ + uint32_t word0; + uint32_t data_offset; + uint8_t format; + int8_t size_offset; + + if (iter->index >= iter->descriptor->field_count) + return false; + + word0 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index]); + format = word0 & 3; + iter->tag = (pb_size_t)((word0 >> 2) & 0x3F); + iter->type = (pb_type_t)((word0 >> 8) & 0xFF); + + if (format == 0) + { + /* 1-word format */ + iter->array_size = 1; + size_offset = (int8_t)((word0 >> 24) & 0x0F); + data_offset = (word0 >> 16) & 0xFF; + iter->data_size = (pb_size_t)((word0 >> 28) & 0x0F); + } + else if (format == 1) + { + /* 2-word format */ + uint32_t word1 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 1]); + + iter->array_size = (pb_size_t)((word0 >> 16) & 0x0FFF); + iter->tag = (pb_size_t)(iter->tag | ((word1 >> 28) << 6)); + size_offset = (int8_t)((word0 >> 28) & 0x0F); + data_offset = word1 & 0xFFFF; + iter->data_size = (pb_size_t)((word1 >> 16) & 0x0FFF); + } + else if (format == 2) + { + /* 4-word format */ + uint32_t word1 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 1]); + uint32_t word2 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 2]); + uint32_t word3 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 3]); + + iter->array_size = (pb_size_t)(word0 >> 16); + iter->tag = (pb_size_t)(iter->tag | ((word1 >> 8) << 6)); + size_offset = (int8_t)(word1 & 0xFF); + data_offset = word2; + iter->data_size = (pb_size_t)word3; + } + else + { + /* 8-word format */ + uint32_t word1 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 1]); + uint32_t word2 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 2]); + uint32_t word3 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 3]); + uint32_t word4 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 4]); + + iter->array_size = (pb_size_t)word4; + iter->tag = (pb_size_t)(iter->tag | ((word1 >> 8) << 6)); + size_offset = (int8_t)(word1 & 0xFF); + data_offset = word2; + iter->data_size = (pb_size_t)word3; + } + + iter->pField = (char*)iter->message + data_offset; + + if (size_offset) + { + iter->pSize = (char*)iter->pField - size_offset; + } + else if (PB_HTYPE(iter->type) == PB_HTYPE_REPEATED && + (PB_ATYPE(iter->type) == PB_ATYPE_STATIC || + PB_ATYPE(iter->type) == PB_ATYPE_POINTER)) + { + /* Fixed count array */ + iter->pSize = &iter->array_size; + } + else + { + iter->pSize = NULL; + } + + if (PB_ATYPE(iter->type) == PB_ATYPE_POINTER && iter->pField != NULL) + { + iter->pData = *(void**)iter->pField; + } + else + { + iter->pData = iter->pField; + } + + if (PB_LTYPE_IS_SUBMSG(iter->type)) + { + iter->submsg_desc = iter->descriptor->submsg_info[iter->submessage_index]; + } + else + { + iter->submsg_desc = NULL; + } + + return true; +} + +static void advance_iterator(pb_field_iter_t *iter) +{ + iter->index++; + + if (iter->index >= iter->descriptor->field_count) + { + /* Restart */ + iter->index = 0; + iter->field_info_index = 0; + iter->submessage_index = 0; + iter->required_field_index = 0; + } + else + { + /* Increment indexes based on previous field type. + * All field info formats have the following fields: + * - lowest 2 bits tell the amount of words in the descriptor (2^n words) + * - bits 2..7 give the lowest bits of tag number. + * - bits 8..15 give the field type. + */ + uint32_t prev_descriptor = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index]); + pb_type_t prev_type = (prev_descriptor >> 8) & 0xFF; + pb_size_t descriptor_len = (pb_size_t)(1 << (prev_descriptor & 3)); + + iter->field_info_index = (pb_size_t)(iter->field_info_index + descriptor_len); + + if (PB_HTYPE(prev_type) == PB_HTYPE_REQUIRED) + { + iter->required_field_index++; + } + + if (PB_LTYPE_IS_SUBMSG(prev_type)) + { + iter->submessage_index++; + } + } +} + +bool pb_field_iter_begin(pb_field_iter_t *iter, const pb_msgdesc_t *desc, void *message) +{ + memset(iter, 0, sizeof(*iter)); + + iter->descriptor = desc; + iter->message = message; + + return load_descriptor_values(iter); +} + +bool pb_field_iter_begin_extension(pb_field_iter_t *iter, pb_extension_t *extension) +{ + const pb_msgdesc_t *msg = (const pb_msgdesc_t*)extension->type->arg; + bool status; + + uint32_t word0 = PB_PROGMEM_READU32(msg->field_info[0]); + if (PB_ATYPE(word0 >> 8) == PB_ATYPE_POINTER) + { + /* For pointer extensions, the pointer is stored directly + * in the extension structure. This avoids having an extra + * indirection. */ + status = pb_field_iter_begin(iter, msg, &extension->dest); + } + else + { + status = pb_field_iter_begin(iter, msg, extension->dest); + } + + iter->pSize = &extension->found; + return status; +} + +bool pb_field_iter_next(pb_field_iter_t *iter) +{ + advance_iterator(iter); + (void)load_descriptor_values(iter); + return iter->index != 0; +} + +bool pb_field_iter_find(pb_field_iter_t *iter, uint32_t tag) +{ + if (iter->tag == tag) + { + return true; /* Nothing to do, correct field already. */ + } + else + { + pb_size_t start = iter->index; + uint32_t fieldinfo; + + do + { + /* Advance iterator but don't load values yet */ + advance_iterator(iter); + + /* Do fast check for tag number match */ + fieldinfo = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index]); + + if (((fieldinfo >> 2) & 0x3F) == (tag & 0x3F)) + { + /* Good candidate, check further */ + (void)load_descriptor_values(iter); + + if (iter->tag == tag && + PB_LTYPE(iter->type) != PB_LTYPE_EXTENSION) + { + /* Found it */ + return true; + } + } + } while (iter->index != start); + + /* Searched all the way back to start, and found nothing. */ + (void)load_descriptor_values(iter); + return false; + } +} + +static void *pb_const_cast(const void *p) +{ + /* Note: this casts away const, in order to use the common field iterator + * logic for both encoding and decoding. The cast is done using union + * to avoid spurious compiler warnings. */ + union { + void *p1; + const void *p2; + } t; + t.p2 = p; + return t.p1; +} + +bool pb_field_iter_begin_const(pb_field_iter_t *iter, const pb_msgdesc_t *desc, const void *message) +{ + return pb_field_iter_begin(iter, desc, pb_const_cast(message)); +} + +bool pb_field_iter_begin_extension_const(pb_field_iter_t *iter, const pb_extension_t *extension) +{ + return pb_field_iter_begin_extension(iter, (pb_extension_t*)pb_const_cast(extension)); +} + +bool pb_default_field_callback(pb_istream_t *istream, pb_ostream_t *ostream, const pb_field_t *field) +{ + if (field->data_size == sizeof(pb_callback_t)) + { + pb_callback_t *pCallback = (pb_callback_t*)field->pData; + + if (pCallback != NULL) + { + if (istream != NULL && pCallback->funcs.decode != NULL) + { + return pCallback->funcs.decode(istream, field, &pCallback->arg); + } + + if (ostream != NULL && pCallback->funcs.encode != NULL) + { + return pCallback->funcs.encode(ostream, field, &pCallback->arg); + } + } + } + + return true; /* Success, but didn't do anything */ + +} + +#ifdef PB_VALIDATE_UTF8 + +/* This function checks whether a string is valid UTF-8 text. + * + * Algorithm is adapted from https://www.cl.cam.ac.uk/~mgk25/ucs/utf8_check.c + * Original copyright: Markus Kuhn 2005-03-30 + * Licensed under "Short code license", which allows use under MIT license or + * any compatible with it. + */ + +bool pb_validate_utf8(const char *str) +{ + const pb_byte_t *s = (const pb_byte_t*)str; + while (*s) + { + if (*s < 0x80) + { + /* 0xxxxxxx */ + s++; + } + else if ((s[0] & 0xe0) == 0xc0) + { + /* 110XXXXx 10xxxxxx */ + if ((s[1] & 0xc0) != 0x80 || + (s[0] & 0xfe) == 0xc0) /* overlong? */ + return false; + else + s += 2; + } + else if ((s[0] & 0xf0) == 0xe0) + { + /* 1110XXXX 10Xxxxxx 10xxxxxx */ + if ((s[1] & 0xc0) != 0x80 || + (s[2] & 0xc0) != 0x80 || + (s[0] == 0xe0 && (s[1] & 0xe0) == 0x80) || /* overlong? */ + (s[0] == 0xed && (s[1] & 0xe0) == 0xa0) || /* surrogate? */ + (s[0] == 0xef && s[1] == 0xbf && + (s[2] & 0xfe) == 0xbe)) /* U+FFFE or U+FFFF? */ + return false; + else + s += 3; + } + else if ((s[0] & 0xf8) == 0xf0) + { + /* 11110XXX 10XXxxxx 10xxxxxx 10xxxxxx */ + if ((s[1] & 0xc0) != 0x80 || + (s[2] & 0xc0) != 0x80 || + (s[3] & 0xc0) != 0x80 || + (s[0] == 0xf0 && (s[1] & 0xf0) == 0x80) || /* overlong? */ + (s[0] == 0xf4 && s[1] > 0x8f) || s[0] > 0xf4) /* > U+10FFFF? */ + return false; + else + s += 4; + } + else + { + return false; + } + } + + return true; +} + +#endif + diff --git a/utils/proto_test/otto_proto_test/Core/Src/pb_decode.c b/utils/proto_test/otto_proto_test/Core/Src/pb_decode.c new file mode 100644 index 0000000..5085d20 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Src/pb_decode.c @@ -0,0 +1,1728 @@ +/* pb_decode.c -- decode a protobuf using minimal resources + * + * 2011 Petteri Aimonen + */ + +/* Use the GCC warn_unused_result attribute to check that all return values + * are propagated correctly. On other compilers and gcc before 3.4.0 just + * ignore the annotation. + */ +#if !defined(__GNUC__) || ( __GNUC__ < 3) || (__GNUC__ == 3 && __GNUC_MINOR__ < 4) + #define checkreturn +#else + #define checkreturn __attribute__((warn_unused_result)) +#endif + +#include "pb.h" +#include "pb_decode.h" +#include "pb_common.h" + +/************************************** + * Declarations internal to this file * + **************************************/ + +static bool checkreturn buf_read(pb_istream_t *stream, pb_byte_t *buf, size_t count); +static bool checkreturn pb_decode_varint32_eof(pb_istream_t *stream, uint32_t *dest, bool *eof); +static bool checkreturn read_raw_value(pb_istream_t *stream, pb_wire_type_t wire_type, pb_byte_t *buf, size_t *size); +static bool checkreturn check_wire_type(pb_wire_type_t wire_type, pb_field_iter_t *field); +static bool checkreturn decode_basic_field(pb_istream_t *stream, pb_field_iter_t *field); +static bool checkreturn decode_static_field(pb_istream_t *stream, pb_wire_type_t wire_type, pb_field_iter_t *field); +static bool checkreturn decode_pointer_field(pb_istream_t *stream, pb_wire_type_t wire_type, pb_field_iter_t *field); +static bool checkreturn decode_callback_field(pb_istream_t *stream, pb_wire_type_t wire_type, pb_field_iter_t *field); +static bool checkreturn decode_field(pb_istream_t *stream, pb_wire_type_t wire_type, pb_field_iter_t *field); +static bool checkreturn default_extension_decoder(pb_istream_t *stream, pb_extension_t *extension, uint32_t tag, pb_wire_type_t wire_type); +static bool checkreturn decode_extension(pb_istream_t *stream, uint32_t tag, pb_wire_type_t wire_type, pb_field_iter_t *iter); +static bool checkreturn find_extension_field(pb_field_iter_t *iter); +static bool pb_message_set_to_defaults(pb_field_iter_t *iter); +static bool checkreturn pb_dec_bool(pb_istream_t *stream, const pb_field_iter_t *field); +static bool checkreturn pb_dec_varint(pb_istream_t *stream, const pb_field_iter_t *field); +static bool checkreturn pb_dec_fixed(pb_istream_t *stream, const pb_field_iter_t *field); +static bool checkreturn pb_dec_bytes(pb_istream_t *stream, const pb_field_iter_t *field); +static bool checkreturn pb_dec_string(pb_istream_t *stream, const pb_field_iter_t *field); +static bool checkreturn pb_dec_submessage(pb_istream_t *stream, const pb_field_iter_t *field); +static bool checkreturn pb_dec_fixed_length_bytes(pb_istream_t *stream, const pb_field_iter_t *field); +static bool checkreturn pb_skip_varint(pb_istream_t *stream); +static bool checkreturn pb_skip_string(pb_istream_t *stream); + +#ifdef PB_ENABLE_MALLOC +static bool checkreturn allocate_field(pb_istream_t *stream, void *pData, size_t data_size, size_t array_size); +static void initialize_pointer_field(void *pItem, pb_field_iter_t *field); +static bool checkreturn pb_release_union_field(pb_istream_t *stream, pb_field_iter_t *field); +static void pb_release_single_field(pb_field_iter_t *field); +#endif + +#ifdef PB_WITHOUT_64BIT +#define pb_int64_t int32_t +#define pb_uint64_t uint32_t +#else +#define pb_int64_t int64_t +#define pb_uint64_t uint64_t +#endif + +typedef struct { + uint32_t bitfield[(PB_MAX_REQUIRED_FIELDS + 31) / 32]; +} pb_fields_seen_t; + +/******************************* + * pb_istream_t implementation * + *******************************/ + +static bool checkreturn buf_read(pb_istream_t *stream, pb_byte_t *buf, size_t count) +{ + size_t i; + const pb_byte_t *source = (const pb_byte_t*)stream->state; + stream->state = (pb_byte_t*)stream->state + count; + + if (buf != NULL) + { + for (i = 0; i < count; i++) + buf[i] = source[i]; + } + + return true; +} + +bool checkreturn pb_read(pb_istream_t *stream, pb_byte_t *buf, size_t count) +{ + if (count == 0) + return true; + +#ifndef PB_BUFFER_ONLY + if (buf == NULL && stream->callback != buf_read) + { + /* Skip input bytes */ + pb_byte_t tmp[16]; + while (count > 16) + { + if (!pb_read(stream, tmp, 16)) + return false; + + count -= 16; + } + + return pb_read(stream, tmp, count); + } +#endif + + if (stream->bytes_left < count) + PB_RETURN_ERROR(stream, "end-of-stream"); + +#ifndef PB_BUFFER_ONLY + if (!stream->callback(stream, buf, count)) + PB_RETURN_ERROR(stream, "io error"); +#else + if (!buf_read(stream, buf, count)) + return false; +#endif + + stream->bytes_left -= count; + return true; +} + +/* Read a single byte from input stream. buf may not be NULL. + * This is an optimization for the varint decoding. */ +static bool checkreturn pb_readbyte(pb_istream_t *stream, pb_byte_t *buf) +{ + if (stream->bytes_left == 0) + PB_RETURN_ERROR(stream, "end-of-stream"); + +#ifndef PB_BUFFER_ONLY + if (!stream->callback(stream, buf, 1)) + PB_RETURN_ERROR(stream, "io error"); +#else + *buf = *(const pb_byte_t*)stream->state; + stream->state = (pb_byte_t*)stream->state + 1; +#endif + + stream->bytes_left--; + + return true; +} + +pb_istream_t pb_istream_from_buffer(const pb_byte_t *buf, size_t bufsize) +{ + pb_istream_t stream; + /* Cast away the const from buf without a compiler error. We are + * careful to use it only in a const manner in the callbacks. + */ + union { + void *state; + const void *c_state; + } state; +#ifdef PB_BUFFER_ONLY + stream.callback = NULL; +#else + stream.callback = &buf_read; +#endif + state.c_state = buf; + stream.state = state.state; + stream.bytes_left = bufsize; +#ifndef PB_NO_ERRMSG + stream.errmsg = NULL; +#endif + return stream; +} + +/******************** + * Helper functions * + ********************/ + +static bool checkreturn pb_decode_varint32_eof(pb_istream_t *stream, uint32_t *dest, bool *eof) +{ + pb_byte_t byte; + uint32_t result; + + if (!pb_readbyte(stream, &byte)) + { + if (stream->bytes_left == 0) + { + if (eof) + { + *eof = true; + } + } + + return false; + } + + if ((byte & 0x80) == 0) + { + /* Quick case, 1 byte value */ + result = byte; + } + else + { + /* Multibyte case */ + uint_fast8_t bitpos = 7; + result = byte & 0x7F; + + do + { + if (!pb_readbyte(stream, &byte)) + return false; + + if (bitpos >= 32) + { + /* Note: The varint could have trailing 0x80 bytes, or 0xFF for negative. */ + uint8_t sign_extension = (bitpos < 63) ? 0xFF : 0x01; + + if ((byte & 0x7F) != 0x00 && ((result >> 31) == 0 || byte != sign_extension)) + { + PB_RETURN_ERROR(stream, "varint overflow"); + } + } + else + { + result |= (uint32_t)(byte & 0x7F) << bitpos; + } + bitpos = (uint_fast8_t)(bitpos + 7); + } while (byte & 0x80); + + if (bitpos == 35 && (byte & 0x70) != 0) + { + /* The last byte was at bitpos=28, so only bottom 4 bits fit. */ + PB_RETURN_ERROR(stream, "varint overflow"); + } + } + + *dest = result; + return true; +} + +bool checkreturn pb_decode_varint32(pb_istream_t *stream, uint32_t *dest) +{ + return pb_decode_varint32_eof(stream, dest, NULL); +} + +#ifndef PB_WITHOUT_64BIT +bool checkreturn pb_decode_varint(pb_istream_t *stream, uint64_t *dest) +{ + pb_byte_t byte; + uint_fast8_t bitpos = 0; + uint64_t result = 0; + + do + { + if (bitpos >= 64) + PB_RETURN_ERROR(stream, "varint overflow"); + + if (!pb_readbyte(stream, &byte)) + return false; + + result |= (uint64_t)(byte & 0x7F) << bitpos; + bitpos = (uint_fast8_t)(bitpos + 7); + } while (byte & 0x80); + + *dest = result; + return true; +} +#endif + +bool checkreturn pb_skip_varint(pb_istream_t *stream) +{ + pb_byte_t byte; + do + { + if (!pb_read(stream, &byte, 1)) + return false; + } while (byte & 0x80); + return true; +} + +bool checkreturn pb_skip_string(pb_istream_t *stream) +{ + uint32_t length; + if (!pb_decode_varint32(stream, &length)) + return false; + + if ((size_t)length != length) + { + PB_RETURN_ERROR(stream, "size too large"); + } + + return pb_read(stream, NULL, (size_t)length); +} + +bool checkreturn pb_decode_tag(pb_istream_t *stream, pb_wire_type_t *wire_type, uint32_t *tag, bool *eof) +{ + uint32_t temp; + *eof = false; + *wire_type = (pb_wire_type_t) 0; + *tag = 0; + + if (!pb_decode_varint32_eof(stream, &temp, eof)) + { + return false; + } + + *tag = temp >> 3; + *wire_type = (pb_wire_type_t)(temp & 7); + return true; +} + +bool checkreturn pb_skip_field(pb_istream_t *stream, pb_wire_type_t wire_type) +{ + switch (wire_type) + { + case PB_WT_VARINT: return pb_skip_varint(stream); + case PB_WT_64BIT: return pb_read(stream, NULL, 8); + case PB_WT_STRING: return pb_skip_string(stream); + case PB_WT_32BIT: return pb_read(stream, NULL, 4); + default: PB_RETURN_ERROR(stream, "invalid wire_type"); + } +} + +/* Read a raw value to buffer, for the purpose of passing it to callback as + * a substream. Size is maximum size on call, and actual size on return. + */ +static bool checkreturn read_raw_value(pb_istream_t *stream, pb_wire_type_t wire_type, pb_byte_t *buf, size_t *size) +{ + size_t max_size = *size; + switch (wire_type) + { + case PB_WT_VARINT: + *size = 0; + do + { + (*size)++; + if (*size > max_size) + PB_RETURN_ERROR(stream, "varint overflow"); + + if (!pb_read(stream, buf, 1)) + return false; + } while (*buf++ & 0x80); + return true; + + case PB_WT_64BIT: + *size = 8; + return pb_read(stream, buf, 8); + + case PB_WT_32BIT: + *size = 4; + return pb_read(stream, buf, 4); + + case PB_WT_STRING: + /* Calling read_raw_value with a PB_WT_STRING is an error. + * Explicitly handle this case and fallthrough to default to avoid + * compiler warnings. + */ + + default: PB_RETURN_ERROR(stream, "invalid wire_type"); + } +} + +/* Decode string length from stream and return a substream with limited length. + * Remember to close the substream using pb_close_string_substream(). + */ +bool checkreturn pb_make_string_substream(pb_istream_t *stream, pb_istream_t *substream) +{ + uint32_t size; + if (!pb_decode_varint32(stream, &size)) + return false; + + *substream = *stream; + if (substream->bytes_left < size) + PB_RETURN_ERROR(stream, "parent stream too short"); + + substream->bytes_left = (size_t)size; + stream->bytes_left -= (size_t)size; + return true; +} + +bool checkreturn pb_close_string_substream(pb_istream_t *stream, pb_istream_t *substream) +{ + if (substream->bytes_left) { + if (!pb_read(substream, NULL, substream->bytes_left)) + return false; + } + + stream->state = substream->state; + +#ifndef PB_NO_ERRMSG + stream->errmsg = substream->errmsg; +#endif + return true; +} + +/************************* + * Decode a single field * + *************************/ + +static bool checkreturn check_wire_type(pb_wire_type_t wire_type, pb_field_iter_t *field) +{ + switch (PB_LTYPE(field->type)) + { + case PB_LTYPE_BOOL: + case PB_LTYPE_VARINT: + case PB_LTYPE_UVARINT: + case PB_LTYPE_SVARINT: + return wire_type == PB_WT_VARINT; + + case PB_LTYPE_FIXED32: + return wire_type == PB_WT_32BIT; + + case PB_LTYPE_FIXED64: + return wire_type == PB_WT_64BIT; + + case PB_LTYPE_BYTES: + case PB_LTYPE_STRING: + case PB_LTYPE_SUBMESSAGE: + case PB_LTYPE_SUBMSG_W_CB: + case PB_LTYPE_FIXED_LENGTH_BYTES: + return wire_type == PB_WT_STRING; + + default: + return false; + } +} + +static bool checkreturn decode_basic_field(pb_istream_t *stream, pb_field_iter_t *field) +{ + switch (PB_LTYPE(field->type)) + { + case PB_LTYPE_BOOL: + return pb_dec_bool(stream, field); + + case PB_LTYPE_VARINT: + case PB_LTYPE_UVARINT: + case PB_LTYPE_SVARINT: + return pb_dec_varint(stream, field); + + case PB_LTYPE_FIXED32: + case PB_LTYPE_FIXED64: + return pb_dec_fixed(stream, field); + + case PB_LTYPE_BYTES: + return pb_dec_bytes(stream, field); + + case PB_LTYPE_STRING: + return pb_dec_string(stream, field); + + case PB_LTYPE_SUBMESSAGE: + case PB_LTYPE_SUBMSG_W_CB: + return pb_dec_submessage(stream, field); + + case PB_LTYPE_FIXED_LENGTH_BYTES: + return pb_dec_fixed_length_bytes(stream, field); + + default: + PB_RETURN_ERROR(stream, "invalid field type"); + } +} + +static bool checkreturn decode_static_field(pb_istream_t *stream, pb_wire_type_t wire_type, pb_field_iter_t *field) +{ + switch (PB_HTYPE(field->type)) + { + case PB_HTYPE_REQUIRED: + if (!check_wire_type(wire_type, field)) + PB_RETURN_ERROR(stream, "wrong wire type"); + + return decode_basic_field(stream, field); + + case PB_HTYPE_OPTIONAL: + if (!check_wire_type(wire_type, field)) + PB_RETURN_ERROR(stream, "wrong wire type"); + + if (field->pSize != NULL) + *(bool*)field->pSize = true; + return decode_basic_field(stream, field); + + case PB_HTYPE_REPEATED: + if (wire_type == PB_WT_STRING + && PB_LTYPE(field->type) <= PB_LTYPE_LAST_PACKABLE) + { + /* Packed array */ + bool status = true; + pb_istream_t substream; + pb_size_t *size = (pb_size_t*)field->pSize; + field->pData = (char*)field->pField + field->data_size * (*size); + + if (!pb_make_string_substream(stream, &substream)) + return false; + + while (substream.bytes_left > 0 && *size < field->array_size) + { + if (!decode_basic_field(&substream, field)) + { + status = false; + break; + } + (*size)++; + field->pData = (char*)field->pData + field->data_size; + } + + if (substream.bytes_left != 0) + PB_RETURN_ERROR(stream, "array overflow"); + if (!pb_close_string_substream(stream, &substream)) + return false; + + return status; + } + else + { + /* Repeated field */ + pb_size_t *size = (pb_size_t*)field->pSize; + field->pData = (char*)field->pField + field->data_size * (*size); + + if (!check_wire_type(wire_type, field)) + PB_RETURN_ERROR(stream, "wrong wire type"); + + if ((*size)++ >= field->array_size) + PB_RETURN_ERROR(stream, "array overflow"); + + return decode_basic_field(stream, field); + } + + case PB_HTYPE_ONEOF: + *(pb_size_t*)field->pSize = field->tag; + if (PB_LTYPE_IS_SUBMSG(field->type)) + { + /* We memset to zero so that any callbacks are set to NULL. + * This is because the callbacks might otherwise have values + * from some other union field. + * If callbacks are needed inside oneof field, use .proto + * option submsg_callback to have a separate callback function + * that can set the fields before submessage is decoded. + * pb_dec_submessage() will set any default values. */ + memset(field->pData, 0, (size_t)field->data_size); + } + + if (!check_wire_type(wire_type, field)) + PB_RETURN_ERROR(stream, "wrong wire type"); + + return decode_basic_field(stream, field); + + default: + PB_RETURN_ERROR(stream, "invalid field type"); + } +} + +#ifdef PB_ENABLE_MALLOC +/* Allocate storage for the field and store the pointer at iter->pData. + * array_size is the number of entries to reserve in an array. + * Zero size is not allowed, use pb_free() for releasing. + */ +static bool checkreturn allocate_field(pb_istream_t *stream, void *pData, size_t data_size, size_t array_size) +{ + void *ptr = *(void**)pData; + + if (data_size == 0 || array_size == 0) + PB_RETURN_ERROR(stream, "invalid size"); + +#ifdef __AVR__ + /* Workaround for AVR libc bug 53284: http://savannah.nongnu.org/bugs/?53284 + * Realloc to size of 1 byte can cause corruption of the malloc structures. + */ + if (data_size == 1 && array_size == 1) + { + data_size = 2; + } +#endif + + /* Check for multiplication overflows. + * This code avoids the costly division if the sizes are small enough. + * Multiplication is safe as long as only half of bits are set + * in either multiplicand. + */ + { + const size_t check_limit = (size_t)1 << (sizeof(size_t) * 4); + if (data_size >= check_limit || array_size >= check_limit) + { + const size_t size_max = (size_t)-1; + if (size_max / array_size < data_size) + { + PB_RETURN_ERROR(stream, "size too large"); + } + } + } + + /* Allocate new or expand previous allocation */ + /* Note: on failure the old pointer will remain in the structure, + * the message must be freed by caller also on error return. */ + ptr = pb_realloc(ptr, array_size * data_size); + if (ptr == NULL) + PB_RETURN_ERROR(stream, "realloc failed"); + + *(void**)pData = ptr; + return true; +} + +/* Clear a newly allocated item in case it contains a pointer, or is a submessage. */ +static void initialize_pointer_field(void *pItem, pb_field_iter_t *field) +{ + if (PB_LTYPE(field->type) == PB_LTYPE_STRING || + PB_LTYPE(field->type) == PB_LTYPE_BYTES) + { + *(void**)pItem = NULL; + } + else if (PB_LTYPE_IS_SUBMSG(field->type)) + { + /* We memset to zero so that any callbacks are set to NULL. + * Then set any default values. */ + pb_field_iter_t submsg_iter; + memset(pItem, 0, field->data_size); + + if (pb_field_iter_begin(&submsg_iter, field->submsg_desc, pItem)) + { + (void)pb_message_set_to_defaults(&submsg_iter); + } + } +} +#endif + +static bool checkreturn decode_pointer_field(pb_istream_t *stream, pb_wire_type_t wire_type, pb_field_iter_t *field) +{ +#ifndef PB_ENABLE_MALLOC + PB_UNUSED(wire_type); + PB_UNUSED(field); + PB_RETURN_ERROR(stream, "no malloc support"); +#else + switch (PB_HTYPE(field->type)) + { + case PB_HTYPE_REQUIRED: + case PB_HTYPE_OPTIONAL: + case PB_HTYPE_ONEOF: + if (!check_wire_type(wire_type, field)) + PB_RETURN_ERROR(stream, "wrong wire type"); + + if (PB_LTYPE_IS_SUBMSG(field->type) && *(void**)field->pField != NULL) + { + /* Duplicate field, have to release the old allocation first. */ + /* FIXME: Does this work correctly for oneofs? */ + pb_release_single_field(field); + } + + if (PB_HTYPE(field->type) == PB_HTYPE_ONEOF) + { + *(pb_size_t*)field->pSize = field->tag; + } + + if (PB_LTYPE(field->type) == PB_LTYPE_STRING || + PB_LTYPE(field->type) == PB_LTYPE_BYTES) + { + /* pb_dec_string and pb_dec_bytes handle allocation themselves */ + field->pData = field->pField; + return decode_basic_field(stream, field); + } + else + { + if (!allocate_field(stream, field->pField, field->data_size, 1)) + return false; + + field->pData = *(void**)field->pField; + initialize_pointer_field(field->pData, field); + return decode_basic_field(stream, field); + } + + case PB_HTYPE_REPEATED: + if (wire_type == PB_WT_STRING + && PB_LTYPE(field->type) <= PB_LTYPE_LAST_PACKABLE) + { + /* Packed array, multiple items come in at once. */ + bool status = true; + pb_size_t *size = (pb_size_t*)field->pSize; + size_t allocated_size = *size; + pb_istream_t substream; + + if (!pb_make_string_substream(stream, &substream)) + return false; + + while (substream.bytes_left) + { + if ((size_t)*size + 1 > allocated_size) + { + /* Allocate more storage. This tries to guess the + * number of remaining entries. Round the division + * upwards. */ + allocated_size += (substream.bytes_left - 1) / field->data_size + 1; + + if (!allocate_field(&substream, field->pField, field->data_size, allocated_size)) + { + status = false; + break; + } + } + + /* Decode the array entry */ + field->pData = *(char**)field->pField + field->data_size * (*size); + initialize_pointer_field(field->pData, field); + if (!decode_basic_field(&substream, field)) + { + status = false; + break; + } + + if (*size == PB_SIZE_MAX) + { +#ifndef PB_NO_ERRMSG + stream->errmsg = "too many array entries"; +#endif + status = false; + break; + } + + (*size)++; + } + if (!pb_close_string_substream(stream, &substream)) + return false; + + return status; + } + else + { + /* Normal repeated field, i.e. only one item at a time. */ + pb_size_t *size = (pb_size_t*)field->pSize; + + if (*size == PB_SIZE_MAX) + PB_RETURN_ERROR(stream, "too many array entries"); + + if (!check_wire_type(wire_type, field)) + PB_RETURN_ERROR(stream, "wrong wire type"); + + (*size)++; + if (!allocate_field(stream, field->pField, field->data_size, *size)) + return false; + + field->pData = *(char**)field->pField + field->data_size * (*size - 1); + initialize_pointer_field(field->pData, field); + return decode_basic_field(stream, field); + } + + default: + PB_RETURN_ERROR(stream, "invalid field type"); + } +#endif +} + +static bool checkreturn decode_callback_field(pb_istream_t *stream, pb_wire_type_t wire_type, pb_field_iter_t *field) +{ + if (!field->descriptor->field_callback) + return pb_skip_field(stream, wire_type); + + if (wire_type == PB_WT_STRING) + { + pb_istream_t substream; + size_t prev_bytes_left; + + if (!pb_make_string_substream(stream, &substream)) + return false; + + do + { + prev_bytes_left = substream.bytes_left; + if (!field->descriptor->field_callback(&substream, NULL, field)) + PB_RETURN_ERROR(stream, "callback failed"); + } while (substream.bytes_left > 0 && substream.bytes_left < prev_bytes_left); + + if (!pb_close_string_substream(stream, &substream)) + return false; + + return true; + } + else + { + /* Copy the single scalar value to stack. + * This is required so that we can limit the stream length, + * which in turn allows to use same callback for packed and + * not-packed fields. */ + pb_istream_t substream; + pb_byte_t buffer[10]; + size_t size = sizeof(buffer); + + if (!read_raw_value(stream, wire_type, buffer, &size)) + return false; + substream = pb_istream_from_buffer(buffer, size); + + return field->descriptor->field_callback(&substream, NULL, field); + } +} + +static bool checkreturn decode_field(pb_istream_t *stream, pb_wire_type_t wire_type, pb_field_iter_t *field) +{ +#ifdef PB_ENABLE_MALLOC + /* When decoding an oneof field, check if there is old data that must be + * released first. */ + if (PB_HTYPE(field->type) == PB_HTYPE_ONEOF) + { + if (!pb_release_union_field(stream, field)) + return false; + } +#endif + + switch (PB_ATYPE(field->type)) + { + case PB_ATYPE_STATIC: + return decode_static_field(stream, wire_type, field); + + case PB_ATYPE_POINTER: + return decode_pointer_field(stream, wire_type, field); + + case PB_ATYPE_CALLBACK: + return decode_callback_field(stream, wire_type, field); + + default: + PB_RETURN_ERROR(stream, "invalid field type"); + } +} + +/* Default handler for extension fields. Expects to have a pb_msgdesc_t + * pointer in the extension->type->arg field, pointing to a message with + * only one field in it. */ +static bool checkreturn default_extension_decoder(pb_istream_t *stream, + pb_extension_t *extension, uint32_t tag, pb_wire_type_t wire_type) +{ + pb_field_iter_t iter; + + if (!pb_field_iter_begin_extension(&iter, extension)) + PB_RETURN_ERROR(stream, "invalid extension"); + + if (iter.tag != tag) + return true; + + extension->found = true; + return decode_field(stream, wire_type, &iter); +} + +/* Try to decode an unknown field as an extension field. Tries each extension + * decoder in turn, until one of them handles the field or loop ends. */ +static bool checkreturn decode_extension(pb_istream_t *stream, + uint32_t tag, pb_wire_type_t wire_type, pb_field_iter_t *iter) +{ + pb_extension_t *extension = *(pb_extension_t* const *)iter->pData; + size_t pos = stream->bytes_left; + + while (extension != NULL && pos == stream->bytes_left) + { + bool status; + if (extension->type->decode) + status = extension->type->decode(stream, extension, tag, wire_type); + else + status = default_extension_decoder(stream, extension, tag, wire_type); + + if (!status) + return false; + + extension = extension->next; + } + + return true; +} + +/* Step through the iterator until an extension field is found or until all + * entries have been checked. There can be only one extension field per + * message. Returns false if no extension field is found. */ +static bool checkreturn find_extension_field(pb_field_iter_t *iter) +{ + pb_size_t start = iter->index; + + do { + if (PB_LTYPE(iter->type) == PB_LTYPE_EXTENSION) + return true; + (void)pb_field_iter_next(iter); + } while (iter->index != start); + + return false; +} + +/* Initialize message fields to default values, recursively */ +static bool pb_field_set_to_default(pb_field_iter_t *field) +{ + pb_type_t type; + type = field->type; + + if (PB_LTYPE(type) == PB_LTYPE_EXTENSION) + { + pb_extension_t *ext = *(pb_extension_t* const *)field->pData; + while (ext != NULL) + { + pb_field_iter_t ext_iter; + if (pb_field_iter_begin_extension(&ext_iter, ext)) + { + ext->found = false; + if (!pb_message_set_to_defaults(&ext_iter)) + return false; + } + ext = ext->next; + } + } + else if (PB_ATYPE(type) == PB_ATYPE_STATIC) + { + bool init_data = true; + if (PB_HTYPE(type) == PB_HTYPE_OPTIONAL && field->pSize != NULL) + { + /* Set has_field to false. Still initialize the optional field + * itself also. */ + *(bool*)field->pSize = false; + } + else if (PB_HTYPE(type) == PB_HTYPE_REPEATED || + PB_HTYPE(type) == PB_HTYPE_ONEOF) + { + /* REPEATED: Set array count to 0, no need to initialize contents. + ONEOF: Set which_field to 0. */ + *(pb_size_t*)field->pSize = 0; + init_data = false; + } + + if (init_data) + { + if (PB_LTYPE_IS_SUBMSG(field->type)) + { + /* Initialize submessage to defaults */ + pb_field_iter_t submsg_iter; + if (pb_field_iter_begin(&submsg_iter, field->submsg_desc, field->pData)) + { + if (!pb_message_set_to_defaults(&submsg_iter)) + return false; + } + } + else + { + /* Initialize to zeros */ + memset(field->pData, 0, (size_t)field->data_size); + } + } + } + else if (PB_ATYPE(type) == PB_ATYPE_POINTER) + { + /* Initialize the pointer to NULL. */ + *(void**)field->pField = NULL; + + /* Initialize array count to 0. */ + if (PB_HTYPE(type) == PB_HTYPE_REPEATED || + PB_HTYPE(type) == PB_HTYPE_ONEOF) + { + *(pb_size_t*)field->pSize = 0; + } + } + else if (PB_ATYPE(type) == PB_ATYPE_CALLBACK) + { + /* Don't overwrite callback */ + } + + return true; +} + +static bool pb_message_set_to_defaults(pb_field_iter_t *iter) +{ + pb_istream_t defstream = PB_ISTREAM_EMPTY; + uint32_t tag = 0; + pb_wire_type_t wire_type = PB_WT_VARINT; + bool eof; + + if (iter->descriptor->default_value) + { + defstream = pb_istream_from_buffer(iter->descriptor->default_value, (size_t)-1); + if (!pb_decode_tag(&defstream, &wire_type, &tag, &eof)) + return false; + } + + do + { + if (!pb_field_set_to_default(iter)) + return false; + + if (tag != 0 && iter->tag == tag) + { + /* We have a default value for this field in the defstream */ + if (!decode_field(&defstream, wire_type, iter)) + return false; + if (!pb_decode_tag(&defstream, &wire_type, &tag, &eof)) + return false; + + if (iter->pSize) + *(bool*)iter->pSize = false; + } + } while (pb_field_iter_next(iter)); + + return true; +} + +/********************* + * Decode all fields * + *********************/ + +static bool checkreturn pb_decode_inner(pb_istream_t *stream, const pb_msgdesc_t *fields, void *dest_struct, unsigned int flags) +{ + uint32_t extension_range_start = 0; + + /* 'fixed_count_field' and 'fixed_count_size' track position of a repeated fixed + * count field. This can only handle _one_ repeated fixed count field that + * is unpacked and unordered among other (non repeated fixed count) fields. + */ + pb_size_t fixed_count_field = PB_SIZE_MAX; + pb_size_t fixed_count_size = 0; + pb_size_t fixed_count_total_size = 0; + + pb_fields_seen_t fields_seen = {{0, 0}}; + const uint32_t allbits = ~(uint32_t)0; + pb_field_iter_t iter; + + /* Return value ignored, as empty message types will be correctly handled by + * pb_field_iter_find() anyway. */ + (void)pb_field_iter_begin(&iter, fields, dest_struct); + + while (stream->bytes_left) + { + uint32_t tag; + pb_wire_type_t wire_type; + bool eof; + + if (!pb_decode_tag(stream, &wire_type, &tag, &eof)) + { + if (eof) + break; + else + return false; + } + + if (tag == 0) + { + if (flags & PB_DECODE_NULLTERMINATED) + { + break; + } + else + { + PB_RETURN_ERROR(stream, "zero tag"); + } + } + + if (!pb_field_iter_find(&iter, tag) || PB_LTYPE(iter.type) == PB_LTYPE_EXTENSION) + { + /* No match found, check if it matches an extension. */ + if (tag >= extension_range_start) + { + if (!find_extension_field(&iter)) + extension_range_start = (uint32_t)-1; + else + extension_range_start = iter.tag; + + if (tag >= extension_range_start) + { + size_t pos = stream->bytes_left; + + if (!decode_extension(stream, tag, wire_type, &iter)) + return false; + + if (pos != stream->bytes_left) + { + /* The field was handled */ + continue; + } + } + } + + /* No match found, skip data */ + if (!pb_skip_field(stream, wire_type)) + return false; + continue; + } + + /* If a repeated fixed count field was found, get size from + * 'fixed_count_field' as there is no counter contained in the struct. + */ + if (PB_HTYPE(iter.type) == PB_HTYPE_REPEATED && iter.pSize == &iter.array_size) + { + if (fixed_count_field != iter.index) { + /* If the new fixed count field does not match the previous one, + * check that the previous one is NULL or that it finished + * receiving all the expected data. + */ + if (fixed_count_field != PB_SIZE_MAX && + fixed_count_size != fixed_count_total_size) + { + PB_RETURN_ERROR(stream, "wrong size for fixed count field"); + } + + fixed_count_field = iter.index; + fixed_count_size = 0; + fixed_count_total_size = iter.array_size; + } + + iter.pSize = &fixed_count_size; + } + + if (PB_HTYPE(iter.type) == PB_HTYPE_REQUIRED + && iter.required_field_index < PB_MAX_REQUIRED_FIELDS) + { + uint32_t tmp = ((uint32_t)1 << (iter.required_field_index & 31)); + fields_seen.bitfield[iter.required_field_index >> 5] |= tmp; + } + + if (!decode_field(stream, wire_type, &iter)) + return false; + } + + /* Check that all elements of the last decoded fixed count field were present. */ + if (fixed_count_field != PB_SIZE_MAX && + fixed_count_size != fixed_count_total_size) + { + PB_RETURN_ERROR(stream, "wrong size for fixed count field"); + } + + /* Check that all required fields were present. */ + { + /* First figure out the number of required fields by + * seeking to the end of the field array. Usually we + * are already close to end after decoding. + */ + pb_size_t req_field_count; + pb_type_t last_type; + pb_size_t i; + do { + req_field_count = iter.required_field_index; + last_type = iter.type; + } while (pb_field_iter_next(&iter)); + + /* Fixup if last field was also required. */ + if (PB_HTYPE(last_type) == PB_HTYPE_REQUIRED && iter.tag != 0) + req_field_count++; + + if (req_field_count > PB_MAX_REQUIRED_FIELDS) + req_field_count = PB_MAX_REQUIRED_FIELDS; + + if (req_field_count > 0) + { + /* Check the whole words */ + for (i = 0; i < (req_field_count >> 5); i++) + { + if (fields_seen.bitfield[i] != allbits) + PB_RETURN_ERROR(stream, "missing required field"); + } + + /* Check the remaining bits (if any) */ + if ((req_field_count & 31) != 0) + { + if (fields_seen.bitfield[req_field_count >> 5] != + (allbits >> (uint8_t)(32 - (req_field_count & 31)))) + { + PB_RETURN_ERROR(stream, "missing required field"); + } + } + } + } + + return true; +} + +bool checkreturn pb_decode_ex(pb_istream_t *stream, const pb_msgdesc_t *fields, void *dest_struct, unsigned int flags) +{ + bool status; + + if ((flags & PB_DECODE_NOINIT) == 0) + { + pb_field_iter_t iter; + + if (pb_field_iter_begin(&iter, fields, dest_struct)) + { + if (!pb_message_set_to_defaults(&iter)) + PB_RETURN_ERROR(stream, "failed to set defaults"); + } + } + + if ((flags & PB_DECODE_DELIMITED) == 0) + { + status = pb_decode_inner(stream, fields, dest_struct, flags); + } + else + { + pb_istream_t substream; + if (!pb_make_string_substream(stream, &substream)) + return false; + + status = pb_decode_inner(&substream, fields, dest_struct, flags); + + if (!pb_close_string_substream(stream, &substream)) + return false; + } + +#ifdef PB_ENABLE_MALLOC + if (!status) + pb_release(fields, dest_struct); +#endif + + return status; +} + +bool checkreturn pb_decode(pb_istream_t *stream, const pb_msgdesc_t *fields, void *dest_struct) +{ + return pb_decode_ex(stream, fields, dest_struct, 0); +} + +#ifdef PB_ENABLE_MALLOC +/* Given an oneof field, if there has already been a field inside this oneof, + * release it before overwriting with a different one. */ +static bool pb_release_union_field(pb_istream_t *stream, pb_field_iter_t *field) +{ + pb_field_iter_t old_field = *field; + pb_size_t old_tag = *(pb_size_t*)field->pSize; /* Previous which_ value */ + pb_size_t new_tag = field->tag; /* New which_ value */ + + if (old_tag == 0) + return true; /* Ok, no old data in union */ + + if (old_tag == new_tag) + return true; /* Ok, old data is of same type => merge */ + + /* Release old data. The find can fail if the message struct contains + * invalid data. */ + if (!pb_field_iter_find(&old_field, old_tag)) + PB_RETURN_ERROR(stream, "invalid union tag"); + + pb_release_single_field(&old_field); + + return true; +} + +static void pb_release_single_field(pb_field_iter_t *field) +{ + pb_type_t type; + type = field->type; + + if (PB_HTYPE(type) == PB_HTYPE_ONEOF) + { + if (*(pb_size_t*)field->pSize != field->tag) + return; /* This is not the current field in the union */ + } + + /* Release anything contained inside an extension or submsg. + * This has to be done even if the submsg itself is statically + * allocated. */ + if (PB_LTYPE(type) == PB_LTYPE_EXTENSION) + { + /* Release fields from all extensions in the linked list */ + pb_extension_t *ext = *(pb_extension_t**)field->pData; + while (ext != NULL) + { + pb_field_iter_t ext_iter; + if (pb_field_iter_begin_extension(&ext_iter, ext)) + { + pb_release_single_field(&ext_iter); + } + ext = ext->next; + } + } + else if (PB_LTYPE_IS_SUBMSG(type) && PB_ATYPE(type) != PB_ATYPE_CALLBACK) + { + /* Release fields in submessage or submsg array */ + pb_size_t count = 1; + + if (PB_ATYPE(type) == PB_ATYPE_POINTER) + { + field->pData = *(void**)field->pField; + } + else + { + field->pData = field->pField; + } + + if (PB_HTYPE(type) == PB_HTYPE_REPEATED) + { + count = *(pb_size_t*)field->pSize; + + if (PB_ATYPE(type) == PB_ATYPE_STATIC && count > field->array_size) + { + /* Protect against corrupted _count fields */ + count = field->array_size; + } + } + + if (field->pData) + { + while (count--) + { + pb_release(field->submsg_desc, field->pData); + field->pData = (char*)field->pData + field->data_size; + } + } + } + + if (PB_ATYPE(type) == PB_ATYPE_POINTER) + { + if (PB_HTYPE(type) == PB_HTYPE_REPEATED && + (PB_LTYPE(type) == PB_LTYPE_STRING || + PB_LTYPE(type) == PB_LTYPE_BYTES)) + { + /* Release entries in repeated string or bytes array */ + void **pItem = *(void***)field->pField; + pb_size_t count = *(pb_size_t*)field->pSize; + while (count--) + { + pb_free(*pItem); + *pItem++ = NULL; + } + } + + if (PB_HTYPE(type) == PB_HTYPE_REPEATED) + { + /* We are going to release the array, so set the size to 0 */ + *(pb_size_t*)field->pSize = 0; + } + + /* Release main pointer */ + pb_free(*(void**)field->pField); + *(void**)field->pField = NULL; + } +} + +void pb_release(const pb_msgdesc_t *fields, void *dest_struct) +{ + pb_field_iter_t iter; + + if (!dest_struct) + return; /* Ignore NULL pointers, similar to free() */ + + if (!pb_field_iter_begin(&iter, fields, dest_struct)) + return; /* Empty message type */ + + do + { + pb_release_single_field(&iter); + } while (pb_field_iter_next(&iter)); +} +#endif + +/* Field decoders */ + +bool pb_decode_bool(pb_istream_t *stream, bool *dest) +{ + uint32_t value; + if (!pb_decode_varint32(stream, &value)) + return false; + + *(bool*)dest = (value != 0); + return true; +} + +bool pb_decode_svarint(pb_istream_t *stream, pb_int64_t *dest) +{ + pb_uint64_t value; + if (!pb_decode_varint(stream, &value)) + return false; + + if (value & 1) + *dest = (pb_int64_t)(~(value >> 1)); + else + *dest = (pb_int64_t)(value >> 1); + + return true; +} + +bool pb_decode_fixed32(pb_istream_t *stream, void *dest) +{ + union { + uint32_t fixed32; + pb_byte_t bytes[4]; + } u; + + if (!pb_read(stream, u.bytes, 4)) + return false; + +#if defined(__BYTE_ORDER) && __BYTE_ORDER == __LITTLE_ENDIAN && CHAR_BIT == 8 + /* fast path - if we know that we're on little endian, assign directly */ + *(uint32_t*)dest = u.fixed32; +#else + *(uint32_t*)dest = ((uint32_t)u.bytes[0] << 0) | + ((uint32_t)u.bytes[1] << 8) | + ((uint32_t)u.bytes[2] << 16) | + ((uint32_t)u.bytes[3] << 24); +#endif + return true; +} + +#ifndef PB_WITHOUT_64BIT +bool pb_decode_fixed64(pb_istream_t *stream, void *dest) +{ + union { + uint64_t fixed64; + pb_byte_t bytes[8]; + } u; + + if (!pb_read(stream, u.bytes, 8)) + return false; + +#if defined(__BYTE_ORDER) && __BYTE_ORDER == __LITTLE_ENDIAN && CHAR_BIT == 8 + /* fast path - if we know that we're on little endian, assign directly */ + *(uint64_t*)dest = u.fixed64; +#else + *(uint64_t*)dest = ((uint64_t)u.bytes[0] << 0) | + ((uint64_t)u.bytes[1] << 8) | + ((uint64_t)u.bytes[2] << 16) | + ((uint64_t)u.bytes[3] << 24) | + ((uint64_t)u.bytes[4] << 32) | + ((uint64_t)u.bytes[5] << 40) | + ((uint64_t)u.bytes[6] << 48) | + ((uint64_t)u.bytes[7] << 56); +#endif + return true; +} +#endif + +static bool checkreturn pb_dec_bool(pb_istream_t *stream, const pb_field_iter_t *field) +{ + return pb_decode_bool(stream, (bool*)field->pData); +} + +static bool checkreturn pb_dec_varint(pb_istream_t *stream, const pb_field_iter_t *field) +{ + if (PB_LTYPE(field->type) == PB_LTYPE_UVARINT) + { + pb_uint64_t value, clamped; + if (!pb_decode_varint(stream, &value)) + return false; + + /* Cast to the proper field size, while checking for overflows */ + if (field->data_size == sizeof(pb_uint64_t)) + clamped = *(pb_uint64_t*)field->pData = value; + else if (field->data_size == sizeof(uint32_t)) + clamped = *(uint32_t*)field->pData = (uint32_t)value; + else if (field->data_size == sizeof(uint_least16_t)) + clamped = *(uint_least16_t*)field->pData = (uint_least16_t)value; + else if (field->data_size == sizeof(uint_least8_t)) + clamped = *(uint_least8_t*)field->pData = (uint_least8_t)value; + else + PB_RETURN_ERROR(stream, "invalid data_size"); + + if (clamped != value) + PB_RETURN_ERROR(stream, "integer too large"); + + return true; + } + else + { + pb_uint64_t value; + pb_int64_t svalue; + pb_int64_t clamped; + + if (PB_LTYPE(field->type) == PB_LTYPE_SVARINT) + { + if (!pb_decode_svarint(stream, &svalue)) + return false; + } + else + { + if (!pb_decode_varint(stream, &value)) + return false; + + /* See issue 97: Google's C++ protobuf allows negative varint values to + * be cast as int32_t, instead of the int64_t that should be used when + * encoding. Previous nanopb versions had a bug in encoding. In order to + * not break decoding of such messages, we cast <=32 bit fields to + * int32_t first to get the sign correct. + */ + if (field->data_size == sizeof(pb_int64_t)) + svalue = (pb_int64_t)value; + else + svalue = (int32_t)value; + } + + /* Cast to the proper field size, while checking for overflows */ + if (field->data_size == sizeof(pb_int64_t)) + clamped = *(pb_int64_t*)field->pData = svalue; + else if (field->data_size == sizeof(int32_t)) + clamped = *(int32_t*)field->pData = (int32_t)svalue; + else if (field->data_size == sizeof(int_least16_t)) + clamped = *(int_least16_t*)field->pData = (int_least16_t)svalue; + else if (field->data_size == sizeof(int_least8_t)) + clamped = *(int_least8_t*)field->pData = (int_least8_t)svalue; + else + PB_RETURN_ERROR(stream, "invalid data_size"); + + if (clamped != svalue) + PB_RETURN_ERROR(stream, "integer too large"); + + return true; + } +} + +static bool checkreturn pb_dec_fixed(pb_istream_t *stream, const pb_field_iter_t *field) +{ +#ifdef PB_CONVERT_DOUBLE_FLOAT + if (field->data_size == sizeof(float) && PB_LTYPE(field->type) == PB_LTYPE_FIXED64) + { + return pb_decode_double_as_float(stream, (float*)field->pData); + } +#endif + + if (field->data_size == sizeof(uint32_t)) + { + return pb_decode_fixed32(stream, field->pData); + } +#ifndef PB_WITHOUT_64BIT + else if (field->data_size == sizeof(uint64_t)) + { + return pb_decode_fixed64(stream, field->pData); + } +#endif + else + { + PB_RETURN_ERROR(stream, "invalid data_size"); + } +} + +static bool checkreturn pb_dec_bytes(pb_istream_t *stream, const pb_field_iter_t *field) +{ + uint32_t size; + size_t alloc_size; + pb_bytes_array_t *dest; + + if (!pb_decode_varint32(stream, &size)) + return false; + + if (size > PB_SIZE_MAX) + PB_RETURN_ERROR(stream, "bytes overflow"); + + alloc_size = PB_BYTES_ARRAY_T_ALLOCSIZE(size); + if (size > alloc_size) + PB_RETURN_ERROR(stream, "size too large"); + + if (PB_ATYPE(field->type) == PB_ATYPE_POINTER) + { +#ifndef PB_ENABLE_MALLOC + PB_RETURN_ERROR(stream, "no malloc support"); +#else + if (stream->bytes_left < size) + PB_RETURN_ERROR(stream, "end-of-stream"); + + if (!allocate_field(stream, field->pData, alloc_size, 1)) + return false; + dest = *(pb_bytes_array_t**)field->pData; +#endif + } + else + { + if (alloc_size > field->data_size) + PB_RETURN_ERROR(stream, "bytes overflow"); + dest = (pb_bytes_array_t*)field->pData; + } + + dest->size = (pb_size_t)size; + return pb_read(stream, dest->bytes, (size_t)size); +} + +static bool checkreturn pb_dec_string(pb_istream_t *stream, const pb_field_iter_t *field) +{ + uint32_t size; + size_t alloc_size; + pb_byte_t *dest = (pb_byte_t*)field->pData; + + if (!pb_decode_varint32(stream, &size)) + return false; + + if (size == (uint32_t)-1) + PB_RETURN_ERROR(stream, "size too large"); + + /* Space for null terminator */ + alloc_size = (size_t)(size + 1); + + if (alloc_size < size) + PB_RETURN_ERROR(stream, "size too large"); + + if (PB_ATYPE(field->type) == PB_ATYPE_POINTER) + { +#ifndef PB_ENABLE_MALLOC + PB_RETURN_ERROR(stream, "no malloc support"); +#else + if (stream->bytes_left < size) + PB_RETURN_ERROR(stream, "end-of-stream"); + + if (!allocate_field(stream, field->pData, alloc_size, 1)) + return false; + dest = *(pb_byte_t**)field->pData; +#endif + } + else + { + if (alloc_size > field->data_size) + PB_RETURN_ERROR(stream, "string overflow"); + } + + dest[size] = 0; + + if (!pb_read(stream, dest, (size_t)size)) + return false; + +#ifdef PB_VALIDATE_UTF8 + if (!pb_validate_utf8((const char*)dest)) + PB_RETURN_ERROR(stream, "invalid utf8"); +#endif + + return true; +} + +static bool checkreturn pb_dec_submessage(pb_istream_t *stream, const pb_field_iter_t *field) +{ + bool status = true; + pb_istream_t substream; + + if (!pb_make_string_substream(stream, &substream)) + return false; + + if (field->submsg_desc == NULL) + PB_RETURN_ERROR(stream, "invalid field descriptor"); + + /* New array entries need to be initialized, while required and optional + * submessages have already been initialized in the top-level pb_decode. */ + if (PB_HTYPE(field->type) == PB_HTYPE_REPEATED || + PB_HTYPE(field->type) == PB_HTYPE_ONEOF) + { + pb_field_iter_t submsg_iter; + if (pb_field_iter_begin(&submsg_iter, field->submsg_desc, field->pData)) + { + if (!pb_message_set_to_defaults(&submsg_iter)) + PB_RETURN_ERROR(stream, "failed to set defaults"); + } + } + + /* Submessages can have a separate message-level callback that is called + * before decoding the message. Typically it is used to set callback fields + * inside oneofs. */ + if (PB_LTYPE(field->type) == PB_LTYPE_SUBMSG_W_CB && field->pSize != NULL) + { + /* Message callback is stored right before pSize. */ + pb_callback_t *callback = (pb_callback_t*)field->pSize - 1; + if (callback->funcs.decode) + { + status = callback->funcs.decode(&substream, field, &callback->arg); + } + } + + /* Now decode the submessage contents */ + if (status) + { + status = pb_decode_noinit(&substream, field->submsg_desc, field->pData); + } + + if (!pb_close_string_substream(stream, &substream)) + return false; + + return status; +} + +static bool checkreturn pb_dec_fixed_length_bytes(pb_istream_t *stream, const pb_field_iter_t *field) +{ + uint32_t size; + + if (!pb_decode_varint32(stream, &size)) + return false; + + if (size > PB_SIZE_MAX) + PB_RETURN_ERROR(stream, "bytes overflow"); + + if (size == 0) + { + /* As a special case, treat empty bytes string as all zeros for fixed_length_bytes. */ + memset(field->pData, 0, (size_t)field->data_size); + return true; + } + + if (size != field->data_size) + PB_RETURN_ERROR(stream, "incorrect fixed length bytes size"); + + return pb_read(stream, (pb_byte_t*)field->pData, (size_t)field->data_size); +} + +#ifdef PB_CONVERT_DOUBLE_FLOAT +bool pb_decode_double_as_float(pb_istream_t *stream, float *dest) +{ + uint8_t sign; + int exponent; + uint32_t mantissa; + uint64_t value; + union { float f; uint32_t i; } out; + + if (!pb_decode_fixed64(stream, &value)) + return false; + + /* Decompose input value */ + sign = (uint8_t)((value >> 63) & 1); + exponent = (int)((value >> 52) & 0x7FF) - 1023; + mantissa = (value >> 28) & 0xFFFFFF; /* Highest 24 bits */ + + /* Figure if value is in range representable by floats. */ + if (exponent == 1024) + { + /* Special value */ + exponent = 128; + } + else if (exponent > 127) + { + /* Too large, convert to infinity */ + exponent = 128; + mantissa = 0; + } + else if (exponent < -150) + { + /* Too small, convert to zero */ + exponent = -127; + mantissa = 0; + } + else if (exponent < -126) + { + /* Denormalized */ + mantissa |= 0x1000000; + mantissa >>= (-126 - exponent); + exponent = -127; + } + + /* Round off mantissa */ + mantissa = (mantissa + 1) >> 1; + + /* Check if mantissa went over 2.0 */ + if (mantissa & 0x800000) + { + exponent += 1; + mantissa &= 0x7FFFFF; + mantissa >>= 1; + } + + /* Combine fields */ + out.i = mantissa; + out.i |= (uint32_t)(exponent + 127) << 23; + out.i |= (uint32_t)sign << 31; + + *dest = out.f; + return true; +} +#endif diff --git a/utils/proto_test/otto_proto_test/Core/Src/pb_encode.c b/utils/proto_test/otto_proto_test/Core/Src/pb_encode.c new file mode 100644 index 0000000..b851bfa --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Src/pb_encode.c @@ -0,0 +1,958 @@ +/* pb_encode.c -- encode a protobuf using minimal resources + * + * 2011 Petteri Aimonen + */ + +#include "pb.h" +#include "pb_encode.h" +#include "pb_common.h" + +/* Use the GCC warn_unused_result attribute to check that all return values + * are propagated correctly. On other compilers and gcc before 3.4.0 just + * ignore the annotation. + */ +#if !defined(__GNUC__) || ( __GNUC__ < 3) || (__GNUC__ == 3 && __GNUC_MINOR__ < 4) + #define checkreturn +#else + #define checkreturn __attribute__((warn_unused_result)) +#endif + +/************************************** + * Declarations internal to this file * + **************************************/ +static bool checkreturn buf_write(pb_ostream_t *stream, const pb_byte_t *buf, size_t count); +static bool checkreturn encode_array(pb_ostream_t *stream, pb_field_iter_t *field); +static bool checkreturn pb_check_proto3_default_value(const pb_field_iter_t *field); +static bool checkreturn encode_basic_field(pb_ostream_t *stream, const pb_field_iter_t *field); +static bool checkreturn encode_callback_field(pb_ostream_t *stream, const pb_field_iter_t *field); +static bool checkreturn encode_field(pb_ostream_t *stream, pb_field_iter_t *field); +static bool checkreturn encode_extension_field(pb_ostream_t *stream, const pb_field_iter_t *field); +static bool checkreturn default_extension_encoder(pb_ostream_t *stream, const pb_extension_t *extension); +static bool checkreturn pb_encode_varint_32(pb_ostream_t *stream, uint32_t low, uint32_t high); +static bool checkreturn pb_enc_bool(pb_ostream_t *stream, const pb_field_iter_t *field); +static bool checkreturn pb_enc_varint(pb_ostream_t *stream, const pb_field_iter_t *field); +static bool checkreturn pb_enc_fixed(pb_ostream_t *stream, const pb_field_iter_t *field); +static bool checkreturn pb_enc_bytes(pb_ostream_t *stream, const pb_field_iter_t *field); +static bool checkreturn pb_enc_string(pb_ostream_t *stream, const pb_field_iter_t *field); +static bool checkreturn pb_enc_submessage(pb_ostream_t *stream, const pb_field_iter_t *field); +static bool checkreturn pb_enc_fixed_length_bytes(pb_ostream_t *stream, const pb_field_iter_t *field); + +#ifdef PB_WITHOUT_64BIT +#define pb_int64_t int32_t +#define pb_uint64_t uint32_t +#else +#define pb_int64_t int64_t +#define pb_uint64_t uint64_t +#endif + +/******************************* + * pb_ostream_t implementation * + *******************************/ + +static bool checkreturn buf_write(pb_ostream_t *stream, const pb_byte_t *buf, size_t count) +{ + size_t i; + pb_byte_t *dest = (pb_byte_t*)stream->state; + stream->state = dest + count; + + for (i = 0; i < count; i++) + dest[i] = buf[i]; + + return true; +} + +pb_ostream_t pb_ostream_from_buffer(pb_byte_t *buf, size_t bufsize) +{ + pb_ostream_t stream; +#ifdef PB_BUFFER_ONLY + stream.callback = (void*)1; /* Just a marker value */ +#else + stream.callback = &buf_write; +#endif + stream.state = buf; + stream.max_size = bufsize; + stream.bytes_written = 0; +#ifndef PB_NO_ERRMSG + stream.errmsg = NULL; +#endif + return stream; +} + +bool checkreturn pb_write(pb_ostream_t *stream, const pb_byte_t *buf, size_t count) +{ + if (count > 0 && stream->callback != NULL) + { + if (stream->bytes_written + count > stream->max_size) + PB_RETURN_ERROR(stream, "stream full"); + +#ifdef PB_BUFFER_ONLY + if (!buf_write(stream, buf, count)) + PB_RETURN_ERROR(stream, "io error"); +#else + if (!stream->callback(stream, buf, count)) + PB_RETURN_ERROR(stream, "io error"); +#endif + } + + stream->bytes_written += count; + return true; +} + +/************************* + * Encode a single field * + *************************/ + +/* Read a bool value without causing undefined behavior even if the value + * is invalid. See issue #434 and + * https://stackoverflow.com/questions/27661768/weird-results-for-conditional + */ +static bool safe_read_bool(const void *pSize) +{ + const char *p = (const char *)pSize; + size_t i; + for (i = 0; i < sizeof(bool); i++) + { + if (p[i] != 0) + return true; + } + return false; +} + +/* Encode a static array. Handles the size calculations and possible packing. */ +static bool checkreturn encode_array(pb_ostream_t *stream, pb_field_iter_t *field) +{ + pb_size_t i; + pb_size_t count; +#ifndef PB_ENCODE_ARRAYS_UNPACKED + size_t size; +#endif + + count = *(pb_size_t*)field->pSize; + + if (count == 0) + return true; + + if (PB_ATYPE(field->type) != PB_ATYPE_POINTER && count > field->array_size) + PB_RETURN_ERROR(stream, "array max size exceeded"); + +#ifndef PB_ENCODE_ARRAYS_UNPACKED + /* We always pack arrays if the datatype allows it. */ + if (PB_LTYPE(field->type) <= PB_LTYPE_LAST_PACKABLE) + { + if (!pb_encode_tag(stream, PB_WT_STRING, field->tag)) + return false; + + /* Determine the total size of packed array. */ + if (PB_LTYPE(field->type) == PB_LTYPE_FIXED32) + { + size = 4 * (size_t)count; + } + else if (PB_LTYPE(field->type) == PB_LTYPE_FIXED64) + { + size = 8 * (size_t)count; + } + else + { + pb_ostream_t sizestream = PB_OSTREAM_SIZING; + void *pData_orig = field->pData; + for (i = 0; i < count; i++) + { + if (!pb_enc_varint(&sizestream, field)) + PB_RETURN_ERROR(stream, PB_GET_ERROR(&sizestream)); + field->pData = (char*)field->pData + field->data_size; + } + field->pData = pData_orig; + size = sizestream.bytes_written; + } + + if (!pb_encode_varint(stream, (pb_uint64_t)size)) + return false; + + if (stream->callback == NULL) + return pb_write(stream, NULL, size); /* Just sizing.. */ + + /* Write the data */ + for (i = 0; i < count; i++) + { + if (PB_LTYPE(field->type) == PB_LTYPE_FIXED32 || PB_LTYPE(field->type) == PB_LTYPE_FIXED64) + { + if (!pb_enc_fixed(stream, field)) + return false; + } + else + { + if (!pb_enc_varint(stream, field)) + return false; + } + + field->pData = (char*)field->pData + field->data_size; + } + } + else /* Unpacked fields */ +#endif + { + for (i = 0; i < count; i++) + { + /* Normally the data is stored directly in the array entries, but + * for pointer-type string and bytes fields, the array entries are + * actually pointers themselves also. So we have to dereference once + * more to get to the actual data. */ + if (PB_ATYPE(field->type) == PB_ATYPE_POINTER && + (PB_LTYPE(field->type) == PB_LTYPE_STRING || + PB_LTYPE(field->type) == PB_LTYPE_BYTES)) + { + bool status; + void *pData_orig = field->pData; + field->pData = *(void* const*)field->pData; + + if (!field->pData) + { + /* Null pointer in array is treated as empty string / bytes */ + status = pb_encode_tag_for_field(stream, field) && + pb_encode_varint(stream, 0); + } + else + { + status = encode_basic_field(stream, field); + } + + field->pData = pData_orig; + + if (!status) + return false; + } + else + { + if (!encode_basic_field(stream, field)) + return false; + } + field->pData = (char*)field->pData + field->data_size; + } + } + + return true; +} + +/* In proto3, all fields are optional and are only encoded if their value is "non-zero". + * This function implements the check for the zero value. */ +static bool checkreturn pb_check_proto3_default_value(const pb_field_iter_t *field) +{ + pb_type_t type = field->type; + + if (PB_ATYPE(type) == PB_ATYPE_STATIC) + { + if (PB_HTYPE(type) == PB_HTYPE_REQUIRED) + { + /* Required proto2 fields inside proto3 submessage, pretty rare case */ + return false; + } + else if (PB_HTYPE(type) == PB_HTYPE_REPEATED) + { + /* Repeated fields inside proto3 submessage: present if count != 0 */ + return *(const pb_size_t*)field->pSize == 0; + } + else if (PB_HTYPE(type) == PB_HTYPE_ONEOF) + { + /* Oneof fields */ + return *(const pb_size_t*)field->pSize == 0; + } + else if (PB_HTYPE(type) == PB_HTYPE_OPTIONAL && field->pSize != NULL) + { + /* Proto2 optional fields inside proto3 message, or proto3 + * submessage fields. */ + return safe_read_bool(field->pSize) == false; + } + + /* Rest is proto3 singular fields */ + if (PB_LTYPE(type) == PB_LTYPE_BYTES) + { + const pb_bytes_array_t *bytes = (const pb_bytes_array_t*)field->pData; + return bytes->size == 0; + } + else if (PB_LTYPE(type) == PB_LTYPE_STRING) + { + return *(const char*)field->pData == '\0'; + } + else if (PB_LTYPE(type) == PB_LTYPE_FIXED_LENGTH_BYTES) + { + /* Fixed length bytes is only empty if its length is fixed + * as 0. Which would be pretty strange, but we can check + * it anyway. */ + return field->data_size == 0; + } + else if (PB_LTYPE_IS_SUBMSG(type)) + { + /* Check all fields in the submessage to find if any of them + * are non-zero. The comparison cannot be done byte-per-byte + * because the C struct may contain padding bytes that must + * be skipped. Note that usually proto3 submessages have + * a separate has_field that is checked earlier in this if. + */ + pb_field_iter_t iter; + if (pb_field_iter_begin(&iter, field->submsg_desc, field->pData)) + { + do + { + if (!pb_check_proto3_default_value(&iter)) + { + return false; + } + } while (pb_field_iter_next(&iter)); + } + return true; + } + } + + { + /* Catch-all branch that does byte-per-byte comparison for zero value. + * + * This is for all pointer fields, and for static PB_LTYPE_VARINT, + * UVARINT, SVARINT, FIXED32, FIXED64, EXTENSION fields, and also + * callback fields. These all have integer or pointer value which + * can be compared with 0. + */ + pb_size_t i; + const char *p = (const char*)field->pData; + for (i = 0; i < field->data_size; i++) + { + if (p[i] != 0) + { + return false; + } + } + + return true; + } +} + +/* Encode a field with static or pointer allocation, i.e. one whose data + * is available to the encoder directly. */ +static bool checkreturn encode_basic_field(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + if (!field->pData) + { + /* Missing pointer field */ + return true; + } + + if (!pb_encode_tag_for_field(stream, field)) + return false; + + switch (PB_LTYPE(field->type)) + { + case PB_LTYPE_BOOL: + return pb_enc_bool(stream, field); + + case PB_LTYPE_VARINT: + case PB_LTYPE_UVARINT: + case PB_LTYPE_SVARINT: + return pb_enc_varint(stream, field); + + case PB_LTYPE_FIXED32: + case PB_LTYPE_FIXED64: + return pb_enc_fixed(stream, field); + + case PB_LTYPE_BYTES: + return pb_enc_bytes(stream, field); + + case PB_LTYPE_STRING: + return pb_enc_string(stream, field); + + case PB_LTYPE_SUBMESSAGE: + case PB_LTYPE_SUBMSG_W_CB: + return pb_enc_submessage(stream, field); + + case PB_LTYPE_FIXED_LENGTH_BYTES: + return pb_enc_fixed_length_bytes(stream, field); + + default: + PB_RETURN_ERROR(stream, "invalid field type"); + } +} + +/* Encode a field with callback semantics. This means that a user function is + * called to provide and encode the actual data. */ +static bool checkreturn encode_callback_field(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + if (field->descriptor->field_callback != NULL) + { + if (!field->descriptor->field_callback(NULL, stream, field)) + PB_RETURN_ERROR(stream, "callback error"); + } + return true; +} + +/* Encode a single field of any callback, pointer or static type. */ +static bool checkreturn encode_field(pb_ostream_t *stream, pb_field_iter_t *field) +{ + /* Check field presence */ + if (PB_HTYPE(field->type) == PB_HTYPE_ONEOF) + { + if (*(const pb_size_t*)field->pSize != field->tag) + { + /* Different type oneof field */ + return true; + } + } + else if (PB_HTYPE(field->type) == PB_HTYPE_OPTIONAL) + { + if (field->pSize) + { + if (safe_read_bool(field->pSize) == false) + { + /* Missing optional field */ + return true; + } + } + else if (PB_ATYPE(field->type) == PB_ATYPE_STATIC) + { + /* Proto3 singular field */ + if (pb_check_proto3_default_value(field)) + return true; + } + } + + if (!field->pData) + { + if (PB_HTYPE(field->type) == PB_HTYPE_REQUIRED) + PB_RETURN_ERROR(stream, "missing required field"); + + /* Pointer field set to NULL */ + return true; + } + + /* Then encode field contents */ + if (PB_ATYPE(field->type) == PB_ATYPE_CALLBACK) + { + return encode_callback_field(stream, field); + } + else if (PB_HTYPE(field->type) == PB_HTYPE_REPEATED) + { + return encode_array(stream, field); + } + else + { + return encode_basic_field(stream, field); + } +} + +/* Default handler for extension fields. Expects to have a pb_msgdesc_t + * pointer in the extension->type->arg field, pointing to a message with + * only one field in it. */ +static bool checkreturn default_extension_encoder(pb_ostream_t *stream, const pb_extension_t *extension) +{ + pb_field_iter_t iter; + + if (!pb_field_iter_begin_extension_const(&iter, extension)) + PB_RETURN_ERROR(stream, "invalid extension"); + + return encode_field(stream, &iter); +} + + +/* Walk through all the registered extensions and give them a chance + * to encode themselves. */ +static bool checkreturn encode_extension_field(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + const pb_extension_t *extension = *(const pb_extension_t* const *)field->pData; + + while (extension) + { + bool status; + if (extension->type->encode) + status = extension->type->encode(stream, extension); + else + status = default_extension_encoder(stream, extension); + + if (!status) + return false; + + extension = extension->next; + } + + return true; +} + +/********************* + * Encode all fields * + *********************/ + +bool checkreturn pb_encode(pb_ostream_t *stream, const pb_msgdesc_t *fields, const void *src_struct) +{ + pb_field_iter_t iter; + if (!pb_field_iter_begin_const(&iter, fields, src_struct)) + return true; /* Empty message type */ + + do { + if (PB_LTYPE(iter.type) == PB_LTYPE_EXTENSION) + { + /* Special case for the extension field placeholder */ + if (!encode_extension_field(stream, &iter)) + return false; + } + else + { + /* Regular field */ + if (!encode_field(stream, &iter)) + return false; + } + } while (pb_field_iter_next(&iter)); + + return true; +} + +bool checkreturn pb_encode_ex(pb_ostream_t *stream, const pb_msgdesc_t *fields, const void *src_struct, unsigned int flags) +{ + if ((flags & PB_ENCODE_DELIMITED) != 0) + { + return pb_encode_submessage(stream, fields, src_struct); + } + else if ((flags & PB_ENCODE_NULLTERMINATED) != 0) + { + const pb_byte_t zero = 0; + + if (!pb_encode(stream, fields, src_struct)) + return false; + + return pb_write(stream, &zero, 1); + } + else + { + return pb_encode(stream, fields, src_struct); + } +} + +bool pb_get_encoded_size(size_t *size, const pb_msgdesc_t *fields, const void *src_struct) +{ + pb_ostream_t stream = PB_OSTREAM_SIZING; + + if (!pb_encode(&stream, fields, src_struct)) + return false; + + *size = stream.bytes_written; + return true; +} + +/******************** + * Helper functions * + ********************/ + +/* This function avoids 64-bit shifts as they are quite slow on many platforms. */ +static bool checkreturn pb_encode_varint_32(pb_ostream_t *stream, uint32_t low, uint32_t high) +{ + size_t i = 0; + pb_byte_t buffer[10]; + pb_byte_t byte = (pb_byte_t)(low & 0x7F); + low >>= 7; + + while (i < 4 && (low != 0 || high != 0)) + { + byte |= 0x80; + buffer[i++] = byte; + byte = (pb_byte_t)(low & 0x7F); + low >>= 7; + } + + if (high) + { + byte = (pb_byte_t)(byte | ((high & 0x07) << 4)); + high >>= 3; + + while (high) + { + byte |= 0x80; + buffer[i++] = byte; + byte = (pb_byte_t)(high & 0x7F); + high >>= 7; + } + } + + buffer[i++] = byte; + + return pb_write(stream, buffer, i); +} + +bool checkreturn pb_encode_varint(pb_ostream_t *stream, pb_uint64_t value) +{ + if (value <= 0x7F) + { + /* Fast path: single byte */ + pb_byte_t byte = (pb_byte_t)value; + return pb_write(stream, &byte, 1); + } + else + { +#ifdef PB_WITHOUT_64BIT + return pb_encode_varint_32(stream, value, 0); +#else + return pb_encode_varint_32(stream, (uint32_t)value, (uint32_t)(value >> 32)); +#endif + } +} + +bool checkreturn pb_encode_svarint(pb_ostream_t *stream, pb_int64_t value) +{ + pb_uint64_t zigzagged; + if (value < 0) + zigzagged = ~((pb_uint64_t)value << 1); + else + zigzagged = (pb_uint64_t)value << 1; + + return pb_encode_varint(stream, zigzagged); +} + +bool checkreturn pb_encode_fixed32(pb_ostream_t *stream, const void *value) +{ + uint32_t val = *(const uint32_t*)value; + pb_byte_t bytes[4]; + bytes[0] = (pb_byte_t)(val & 0xFF); + bytes[1] = (pb_byte_t)((val >> 8) & 0xFF); + bytes[2] = (pb_byte_t)((val >> 16) & 0xFF); + bytes[3] = (pb_byte_t)((val >> 24) & 0xFF); + return pb_write(stream, bytes, 4); +} + +#ifndef PB_WITHOUT_64BIT +bool checkreturn pb_encode_fixed64(pb_ostream_t *stream, const void *value) +{ + uint64_t val = *(const uint64_t*)value; + pb_byte_t bytes[8]; + bytes[0] = (pb_byte_t)(val & 0xFF); + bytes[1] = (pb_byte_t)((val >> 8) & 0xFF); + bytes[2] = (pb_byte_t)((val >> 16) & 0xFF); + bytes[3] = (pb_byte_t)((val >> 24) & 0xFF); + bytes[4] = (pb_byte_t)((val >> 32) & 0xFF); + bytes[5] = (pb_byte_t)((val >> 40) & 0xFF); + bytes[6] = (pb_byte_t)((val >> 48) & 0xFF); + bytes[7] = (pb_byte_t)((val >> 56) & 0xFF); + return pb_write(stream, bytes, 8); +} +#endif + +bool checkreturn pb_encode_tag(pb_ostream_t *stream, pb_wire_type_t wiretype, uint32_t field_number) +{ + pb_uint64_t tag = ((pb_uint64_t)field_number << 3) | wiretype; + return pb_encode_varint(stream, tag); +} + +bool pb_encode_tag_for_field ( pb_ostream_t* stream, const pb_field_iter_t* field ) +{ + pb_wire_type_t wiretype; + switch (PB_LTYPE(field->type)) + { + case PB_LTYPE_BOOL: + case PB_LTYPE_VARINT: + case PB_LTYPE_UVARINT: + case PB_LTYPE_SVARINT: + wiretype = PB_WT_VARINT; + break; + + case PB_LTYPE_FIXED32: + wiretype = PB_WT_32BIT; + break; + + case PB_LTYPE_FIXED64: + wiretype = PB_WT_64BIT; + break; + + case PB_LTYPE_BYTES: + case PB_LTYPE_STRING: + case PB_LTYPE_SUBMESSAGE: + case PB_LTYPE_SUBMSG_W_CB: + case PB_LTYPE_FIXED_LENGTH_BYTES: + wiretype = PB_WT_STRING; + break; + + default: + PB_RETURN_ERROR(stream, "invalid field type"); + } + + return pb_encode_tag(stream, wiretype, field->tag); +} + +bool checkreturn pb_encode_string(pb_ostream_t *stream, const pb_byte_t *buffer, size_t size) +{ + if (!pb_encode_varint(stream, (pb_uint64_t)size)) + return false; + + return pb_write(stream, buffer, size); +} + +bool checkreturn pb_encode_submessage(pb_ostream_t *stream, const pb_msgdesc_t *fields, const void *src_struct) +{ + /* First calculate the message size using a non-writing substream. */ + pb_ostream_t substream = PB_OSTREAM_SIZING; + size_t size; + bool status; + + if (!pb_encode(&substream, fields, src_struct)) + { +#ifndef PB_NO_ERRMSG + stream->errmsg = substream.errmsg; +#endif + return false; + } + + size = substream.bytes_written; + + if (!pb_encode_varint(stream, (pb_uint64_t)size)) + return false; + + if (stream->callback == NULL) + return pb_write(stream, NULL, size); /* Just sizing */ + + if (stream->bytes_written + size > stream->max_size) + PB_RETURN_ERROR(stream, "stream full"); + + /* Use a substream to verify that a callback doesn't write more than + * what it did the first time. */ + substream.callback = stream->callback; + substream.state = stream->state; + substream.max_size = size; + substream.bytes_written = 0; +#ifndef PB_NO_ERRMSG + substream.errmsg = NULL; +#endif + + status = pb_encode(&substream, fields, src_struct); + + stream->bytes_written += substream.bytes_written; + stream->state = substream.state; +#ifndef PB_NO_ERRMSG + stream->errmsg = substream.errmsg; +#endif + + if (substream.bytes_written != size) + PB_RETURN_ERROR(stream, "submsg size changed"); + + return status; +} + +/* Field encoders */ + +static bool checkreturn pb_enc_bool(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + uint32_t value = safe_read_bool(field->pData) ? 1 : 0; + PB_UNUSED(field); + return pb_encode_varint(stream, value); +} + +static bool checkreturn pb_enc_varint(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + if (PB_LTYPE(field->type) == PB_LTYPE_UVARINT) + { + /* Perform unsigned integer extension */ + pb_uint64_t value = 0; + + if (field->data_size == sizeof(uint_least8_t)) + value = *(const uint_least8_t*)field->pData; + else if (field->data_size == sizeof(uint_least16_t)) + value = *(const uint_least16_t*)field->pData; + else if (field->data_size == sizeof(uint32_t)) + value = *(const uint32_t*)field->pData; + else if (field->data_size == sizeof(pb_uint64_t)) + value = *(const pb_uint64_t*)field->pData; + else + PB_RETURN_ERROR(stream, "invalid data_size"); + + return pb_encode_varint(stream, value); + } + else + { + /* Perform signed integer extension */ + pb_int64_t value = 0; + + if (field->data_size == sizeof(int_least8_t)) + value = *(const int_least8_t*)field->pData; + else if (field->data_size == sizeof(int_least16_t)) + value = *(const int_least16_t*)field->pData; + else if (field->data_size == sizeof(int32_t)) + value = *(const int32_t*)field->pData; + else if (field->data_size == sizeof(pb_int64_t)) + value = *(const pb_int64_t*)field->pData; + else + PB_RETURN_ERROR(stream, "invalid data_size"); + + if (PB_LTYPE(field->type) == PB_LTYPE_SVARINT) + return pb_encode_svarint(stream, value); +#ifdef PB_WITHOUT_64BIT + else if (value < 0) + return pb_encode_varint_32(stream, (uint32_t)value, (uint32_t)-1); +#endif + else + return pb_encode_varint(stream, (pb_uint64_t)value); + + } +} + +static bool checkreturn pb_enc_fixed(pb_ostream_t *stream, const pb_field_iter_t *field) +{ +#ifdef PB_CONVERT_DOUBLE_FLOAT + if (field->data_size == sizeof(float) && PB_LTYPE(field->type) == PB_LTYPE_FIXED64) + { + return pb_encode_float_as_double(stream, *(float*)field->pData); + } +#endif + + if (field->data_size == sizeof(uint32_t)) + { + return pb_encode_fixed32(stream, field->pData); + } +#ifndef PB_WITHOUT_64BIT + else if (field->data_size == sizeof(uint64_t)) + { + return pb_encode_fixed64(stream, field->pData); + } +#endif + else + { + PB_RETURN_ERROR(stream, "invalid data_size"); + } +} + +static bool checkreturn pb_enc_bytes(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + const pb_bytes_array_t *bytes = NULL; + + bytes = (const pb_bytes_array_t*)field->pData; + + if (bytes == NULL) + { + /* Treat null pointer as an empty bytes field */ + return pb_encode_string(stream, NULL, 0); + } + + if (PB_ATYPE(field->type) == PB_ATYPE_STATIC && + PB_BYTES_ARRAY_T_ALLOCSIZE(bytes->size) > field->data_size) + { + PB_RETURN_ERROR(stream, "bytes size exceeded"); + } + + return pb_encode_string(stream, bytes->bytes, (size_t)bytes->size); +} + +static bool checkreturn pb_enc_string(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + size_t size = 0; + size_t max_size = (size_t)field->data_size; + const char *str = (const char*)field->pData; + + if (PB_ATYPE(field->type) == PB_ATYPE_POINTER) + { + max_size = (size_t)-1; + } + else + { + /* pb_dec_string() assumes string fields end with a null + * terminator when the type isn't PB_ATYPE_POINTER, so we + * shouldn't allow more than max-1 bytes to be written to + * allow space for the null terminator. + */ + if (max_size == 0) + PB_RETURN_ERROR(stream, "zero-length string"); + + max_size -= 1; + } + + + if (str == NULL) + { + size = 0; /* Treat null pointer as an empty string */ + } + else + { + const char *p = str; + + /* strnlen() is not always available, so just use a loop */ + while (size < max_size && *p != '\0') + { + size++; + p++; + } + + if (*p != '\0') + { + PB_RETURN_ERROR(stream, "unterminated string"); + } + } + +#ifdef PB_VALIDATE_UTF8 + if (!pb_validate_utf8(str)) + PB_RETURN_ERROR(stream, "invalid utf8"); +#endif + + return pb_encode_string(stream, (const pb_byte_t*)str, size); +} + +static bool checkreturn pb_enc_submessage(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + if (field->submsg_desc == NULL) + PB_RETURN_ERROR(stream, "invalid field descriptor"); + + if (PB_LTYPE(field->type) == PB_LTYPE_SUBMSG_W_CB && field->pSize != NULL) + { + /* Message callback is stored right before pSize. */ + pb_callback_t *callback = (pb_callback_t*)field->pSize - 1; + if (callback->funcs.encode) + { + if (!callback->funcs.encode(stream, field, &callback->arg)) + return false; + } + } + + return pb_encode_submessage(stream, field->submsg_desc, field->pData); +} + +static bool checkreturn pb_enc_fixed_length_bytes(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + return pb_encode_string(stream, (const pb_byte_t*)field->pData, (size_t)field->data_size); +} + +#ifdef PB_CONVERT_DOUBLE_FLOAT +bool pb_encode_float_as_double(pb_ostream_t *stream, float value) +{ + union { float f; uint32_t i; } in; + uint8_t sign; + int exponent; + uint64_t mantissa; + + in.f = value; + + /* Decompose input value */ + sign = (uint8_t)((in.i >> 31) & 1); + exponent = (int)((in.i >> 23) & 0xFF) - 127; + mantissa = in.i & 0x7FFFFF; + + if (exponent == 128) + { + /* Special value (NaN etc.) */ + exponent = 1024; + } + else if (exponent == -127) + { + if (!mantissa) + { + /* Zero */ + exponent = -1023; + } + else + { + /* Denormalized */ + mantissa <<= 1; + while (!(mantissa & 0x800000)) + { + mantissa <<= 1; + exponent--; + } + mantissa &= 0x7FFFFF; + } + } + + /* Combine fields */ + mantissa <<= 29; + mantissa |= (uint64_t)(exponent + 1023) << 52; + mantissa |= (uint64_t)sign << 63; + + return pb_encode_fixed64(stream, &mantissa); +} +#endif diff --git a/utils/proto_test/otto_proto_test/Core/Src/stm32f7xx_hal_msp.c b/utils/proto_test/otto_proto_test/Core/Src/stm32f7xx_hal_msp.c new file mode 100644 index 0000000..2918b9b --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Src/stm32f7xx_hal_msp.c @@ -0,0 +1,391 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : stm32f7xx_hal_msp.c + * Description : This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief TIM_Encoder MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_encoder: TIM_Encoder handle pointer +* @retval None +*/ +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(htim_encoder->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**TIM2 GPIO Configuration + PA5 ------> TIM2_CH1 + PB3 ------> TIM2_CH2 + */ + GPIO_InitStruct.Pin = encoder_sx1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; + HAL_GPIO_Init(encoder_sx1_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = encoder_sx2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; + HAL_GPIO_Init(encoder_sx2_GPIO_Port, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM2_MspInit 1 */ + + /* USER CODE END TIM2_MspInit 1 */ + } + else if(htim_encoder->Instance==TIM5) + { + /* USER CODE BEGIN TIM5_MspInit 0 */ + + /* USER CODE END TIM5_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM5_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**TIM5 GPIO Configuration + PA0/WKUP ------> TIM5_CH1 + PA1 ------> TIM5_CH2 + */ + GPIO_InitStruct.Pin = encoder_dx1_Pin|encoder_dx2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF2_TIM5; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM5_MspInit 1 */ + + /* USER CODE END TIM5_MspInit 1 */ + } + +} + +/** +* @brief TIM_Base MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspInit 0 */ + + /* USER CODE END TIM3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM3_CLK_ENABLE(); + /* USER CODE BEGIN TIM3_MspInit 1 */ + + /* USER CODE END TIM3_MspInit 1 */ + } + else if(htim_base->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspInit 0 */ + + /* USER CODE END TIM4_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM4_CLK_ENABLE(); + /* USER CODE BEGIN TIM4_MspInit 1 */ + + /* USER CODE END TIM4_MspInit 1 */ + } + else if(htim_base->Instance==TIM6) + { + /* USER CODE BEGIN TIM6_MspInit 0 */ + + /* USER CODE END TIM6_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM6_CLK_ENABLE(); + /* USER CODE BEGIN TIM6_MspInit 1 */ + + /* USER CODE END TIM6_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(htim->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspPostInit 0 */ + + /* USER CODE END TIM4_MspPostInit 0 */ + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**TIM4 GPIO Configuration + PD14 ------> TIM4_CH3 + PD15 ------> TIM4_CH4 + */ + GPIO_InitStruct.Pin = pwm2_Pin|pwm1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM4_MspPostInit 1 */ + + /* USER CODE END TIM4_MspPostInit 1 */ + } + +} +/** +* @brief TIM_Encoder MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_encoder: TIM_Encoder handle pointer +* @retval None +*/ +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef* htim_encoder) +{ + if(htim_encoder->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspDeInit 0 */ + + /* USER CODE END TIM2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM2_CLK_DISABLE(); + + /**TIM2 GPIO Configuration + PA5 ------> TIM2_CH1 + PB3 ------> TIM2_CH2 + */ + HAL_GPIO_DeInit(encoder_sx1_GPIO_Port, encoder_sx1_Pin); + + HAL_GPIO_DeInit(encoder_sx2_GPIO_Port, encoder_sx2_Pin); + + /* USER CODE BEGIN TIM2_MspDeInit 1 */ + + /* USER CODE END TIM2_MspDeInit 1 */ + } + else if(htim_encoder->Instance==TIM5) + { + /* USER CODE BEGIN TIM5_MspDeInit 0 */ + + /* USER CODE END TIM5_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM5_CLK_DISABLE(); + + /**TIM5 GPIO Configuration + PA0/WKUP ------> TIM5_CH1 + PA1 ------> TIM5_CH2 + */ + HAL_GPIO_DeInit(GPIOA, encoder_dx1_Pin|encoder_dx2_Pin); + + /* USER CODE BEGIN TIM5_MspDeInit 1 */ + + /* USER CODE END TIM5_MspDeInit 1 */ + } + +} + +/** +* @brief TIM_Base MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspDeInit 0 */ + + /* USER CODE END TIM3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM3_CLK_DISABLE(); + + /* TIM3 interrupt DeInit */ + HAL_NVIC_DisableIRQ(TIM3_IRQn); + /* USER CODE BEGIN TIM3_MspDeInit 1 */ + + /* USER CODE END TIM3_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspDeInit 0 */ + + /* USER CODE END TIM4_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM4_CLK_DISABLE(); + /* USER CODE BEGIN TIM4_MspDeInit 1 */ + + /* USER CODE END TIM4_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM6) + { + /* USER CODE BEGIN TIM6_MspDeInit 0 */ + + /* USER CODE END TIM6_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM6_CLK_DISABLE(); + + /* TIM6 interrupt DeInit */ + HAL_NVIC_DisableIRQ(TIM6_DAC_IRQn); + /* USER CODE BEGIN TIM6_MspDeInit 1 */ + + /* USER CODE END TIM6_MspDeInit 1 */ + } + +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(huart->Instance==USART6) + { + /* USER CODE BEGIN USART6_MspInit 0 */ + + /* USER CODE END USART6_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART6_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + /**USART6 GPIO Configuration + PC6 ------> USART6_TX + PC7 ------> USART6_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF8_USART6; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* USER CODE BEGIN USART6_MspInit 1 */ + + /* USER CODE END USART6_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART6) + { + /* USER CODE BEGIN USART6_MspDeInit 0 */ + + /* USER CODE END USART6_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART6_CLK_DISABLE(); + + /**USART6 GPIO Configuration + PC6 ------> USART6_TX + PC7 ------> USART6_RX + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_6|GPIO_PIN_7); + + /* USART6 interrupt DeInit */ + HAL_NVIC_DisableIRQ(USART6_IRQn); + /* USER CODE BEGIN USART6_MspDeInit 1 */ + + /* USER CODE END USART6_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Core/Src/stm32f7xx_it.c b/utils/proto_test/otto_proto_test/Core/Src/stm32f7xx_it.c new file mode 100644 index 0000000..88e7f7d --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Src/stm32f7xx_it.c @@ -0,0 +1,261 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f7xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern TIM_HandleTypeDef htim3; +extern TIM_HandleTypeDef htim6; +extern UART_HandleTypeDef huart6; +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M7 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F7xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f7xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles TIM3 global interrupt. + */ +void TIM3_IRQHandler(void) +{ + /* USER CODE BEGIN TIM3_IRQn 0 */ + + /* USER CODE END TIM3_IRQn 0 */ + HAL_TIM_IRQHandler(&htim3); + /* USER CODE BEGIN TIM3_IRQn 1 */ + + /* USER CODE END TIM3_IRQn 1 */ +} + +/** + * @brief This function handles EXTI line[15:10] interrupts. + */ +void EXTI15_10_IRQHandler(void) +{ + /* USER CODE BEGIN EXTI15_10_IRQn 0 */ + + /* USER CODE END EXTI15_10_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13); + /* USER CODE BEGIN EXTI15_10_IRQn 1 */ + + /* USER CODE END EXTI15_10_IRQn 1 */ +} + +/** + * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts. + */ +void TIM6_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ + + /* USER CODE END TIM6_DAC_IRQn 0 */ + HAL_TIM_IRQHandler(&htim6); + /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ + + /* USER CODE END TIM6_DAC_IRQn 1 */ +} + +/** + * @brief This function handles USART6 global interrupt. + */ +void USART6_IRQHandler(void) +{ + /* USER CODE BEGIN USART6_IRQn 0 */ + + /* USER CODE END USART6_IRQn 0 */ + HAL_UART_IRQHandler(&huart6); + /* USER CODE BEGIN USART6_IRQn 1 */ + + /* USER CODE END USART6_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Core/Src/syscalls.c b/utils/proto_test/otto_proto_test/Core/Src/syscalls.c new file mode 100644 index 0000000..9f32dad --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Src/syscalls.c @@ -0,0 +1,184 @@ +/** +***************************************************************************** +** +** File : syscalls.c +** +** Author : Auto-generated by STM32CubeIDE +** +** Abstract : STM32CubeIDE Minimal System calls file +** +** For more information about which c-functions +** need which of these lowlevel functions +** please consult the Newlib libc-manual +** +** Environment : STM32CubeIDE MCU +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +***************************************************************************** +** +**

© COPYRIGHT(c) 2018 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +***************************************************************************** +*/ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +//#undef errno +extern int errno; +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + +register char * stack_ptr asm("sp"); + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + +return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + return 0; +} + +int _open(char *path, int flags, ...) +{ + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + return -1; +} + +int _stat(char *file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + errno = ENOMEM; + return -1; +} diff --git a/utils/proto_test/otto_proto_test/Core/Src/sysmem.c b/utils/proto_test/otto_proto_test/Core/Src/sysmem.c new file mode 100644 index 0000000..e5e1bc2 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Src/sysmem.c @@ -0,0 +1,83 @@ +/** +***************************************************************************** +** +** File : sysmem.c +** +** Author : Auto-generated by STM32CubeIDE +** +** Abstract : STM32CubeIDE Minimal System Memory calls file +** +** For more information about which c-functions +** need which of these lowlevel functions +** please consult the Newlib libc-manual +** +** Environment : STM32CubeIDE MCU +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +***************************************************************************** +** +**

© COPYRIGHT(c) 2018 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +***************************************************************************** +*/ + +/* Includes */ +#include +#include + +/* Variables */ +extern int errno; +register char * stack_ptr asm("sp"); + +/* Functions */ + +/** + _sbrk + Increase program data space. Malloc and related functions depend on this +**/ +caddr_t _sbrk(int incr) +{ + extern char end asm("end"); + static char *heap_end; + char *prev_heap_end; + + if (heap_end == 0) + heap_end = &end; + + prev_heap_end = heap_end; + if (heap_end + incr > stack_ptr) + { + errno = ENOMEM; + return (caddr_t) -1; + } + + heap_end += incr; + + return (caddr_t) prev_heap_end; +} + diff --git a/utils/proto_test/otto_proto_test/Core/Src/system_stm32f7xx.c b/utils/proto_test/otto_proto_test/Core/Src/system_stm32f7xx.c new file mode 100644 index 0000000..1a362bd --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Src/system_stm32f7xx.c @@ -0,0 +1,278 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** @addtogroup STM32F7xx_System_Private_Includes + * @{ + */ + +#include "stm32f7xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Variables + * @{ + */ + + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000; + const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Core/Src/velocities.pb.c b/utils/proto_test/otto_proto_test/Core/Src/velocities.pb.c new file mode 100644 index 0000000..b3f3839 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Src/velocities.pb.c @@ -0,0 +1,12 @@ +/* Automatically generated nanopb constant definitions */ +/* Generated by 0.4.1-dev */ + +#include "velocities.pb.h" +#if PB_PROTO_HEADER_VERSION != 40 +#error Regenerate this file with the current version of nanopb generator. +#endif + +PB_BIND(Velocities, Velocities, AUTO) + + + diff --git a/utils/proto_test/otto_proto_test/Core/Startup/startup_stm32f767zitx.s b/utils/proto_test/otto_proto_test/Core/Startup/startup_stm32f767zitx.s new file mode 100644 index 0000000..c33cf89 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Core/Startup/startup_stm32f767zitx.s @@ -0,0 +1,634 @@ +/** + ****************************************************************************** + * @file startup_stm32f767xx.s + * @author MCD Application Team + * @brief STM32F767xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M7 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system initialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M7. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word 0 /* Reserved */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */ + .word SDMMC2_IRQHandler /* SDMMC2 */ + .word CAN3_TX_IRQHandler /* CAN3 TX */ + .word CAN3_RX0_IRQHandler /* CAN3 RX0 */ + .word CAN3_RX1_IRQHandler /* CAN3 RX1 */ + .word CAN3_SCE_IRQHandler /* CAN3 SCE */ + .word JPEG_IRQHandler /* JPEG */ + .word MDIOS_IRQHandler /* MDIOS */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak CAN3_TX_IRQHandler + .thumb_set CAN3_TX_IRQHandler,Default_Handler + + .weak CAN3_RX0_IRQHandler + .thumb_set CAN3_RX0_IRQHandler,Default_Handler + + .weak CAN3_RX1_IRQHandler + .thumb_set CAN3_RX1_IRQHandler,Default_Handler + + .weak CAN3_SCE_IRQHandler + .thumb_set CAN3_SCE_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/utils/proto_test/otto_proto_test/Debug/Core/Src/subdir.mk b/utils/proto_test/otto_proto_test/Debug/Core/Src/subdir.mk new file mode 100644 index 0000000..b457078 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Debug/Core/Src/subdir.mk @@ -0,0 +1,73 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/pb_common.c \ +../Core/Src/pb_decode.c \ +../Core/Src/pb_encode.c \ +../Core/Src/stm32f7xx_hal_msp.c \ +../Core/Src/stm32f7xx_it.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32f7xx.c \ +../Core/Src/velocities.pb.c + +CPP_SRCS += \ +../Core/Src/encoder.cpp \ +../Core/Src/main.cpp + +OBJS += \ +./Core/Src/encoder.o \ +./Core/Src/main.o \ +./Core/Src/pb_common.o \ +./Core/Src/pb_decode.o \ +./Core/Src/pb_encode.o \ +./Core/Src/stm32f7xx_hal_msp.o \ +./Core/Src/stm32f7xx_it.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32f7xx.o \ +./Core/Src/velocities.pb.o + +C_DEPS += \ +./Core/Src/pb_common.d \ +./Core/Src/pb_decode.d \ +./Core/Src/pb_encode.d \ +./Core/Src/stm32f7xx_hal_msp.d \ +./Core/Src/stm32f7xx_it.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32f7xx.d \ +./Core/Src/velocities.pb.d + +CPP_DEPS += \ +./Core/Src/encoder.d \ +./Core/Src/main.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/encoder.o: ../Core/Src/encoder.cpp + arm-none-eabi-g++ "$<" -mcpu=cortex-m7 -std=gnu++14 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-threadsafe-statics -fno-use-cxa-atexit -Wall -fstack-usage -MMD -MP -MF"Core/Src/encoder.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/main.o: ../Core/Src/main.cpp + arm-none-eabi-g++ "$<" -mcpu=cortex-m7 -std=gnu++14 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-threadsafe-statics -fno-use-cxa-atexit -Wall -fstack-usage -MMD -MP -MF"Core/Src/main.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/pb_common.o: ../Core/Src/pb_common.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/pb_common.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/pb_decode.o: ../Core/Src/pb_decode.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/pb_decode.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/pb_encode.o: ../Core/Src/pb_encode.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/pb_encode.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32f7xx_hal_msp.o: ../Core/Src/stm32f7xx_hal_msp.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f7xx_hal_msp.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32f7xx_it.o: ../Core/Src/stm32f7xx_it.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f7xx_it.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/syscalls.o: ../Core/Src/syscalls.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/syscalls.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/sysmem.o: ../Core/Src/sysmem.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/sysmem.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/system_stm32f7xx.o: ../Core/Src/system_stm32f7xx.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/system_stm32f7xx.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/velocities.pb.o: ../Core/Src/velocities.pb.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/velocities.pb.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/utils/proto_test/otto_proto_test/Debug/Core/Startup/subdir.mk b/utils/proto_test/otto_proto_test/Debug/Core/Startup/subdir.mk new file mode 100644 index 0000000..481e2a5 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Debug/Core/Startup/subdir.mk @@ -0,0 +1,16 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32f767zitx.s + +OBJS += \ +./Core/Startup/startup_stm32f767zitx.o + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/%.o: ../Core/Startup/%.s + arm-none-eabi-gcc -mcpu=cortex-m7 -g3 -c -x assembler-with-cpp --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" "$<" + diff --git a/utils/proto_test/otto_proto_test/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk b/utils/proto_test/otto_proto_test/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk new file mode 100644 index 0000000..2a0a6ce --- /dev/null +++ b/utils/proto_test/otto_proto_test/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,104 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c + +OBJS += \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + +C_DEPS += \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/utils/proto_test/otto_proto_test/Debug/makefile b/utils/proto_test/otto_proto_test/Debug/makefile new file mode 100644 index 0000000..f370701 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Debug/makefile @@ -0,0 +1,80 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +otto_proto_test.elf \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +otto_proto_test.list \ + + +# All Target +all: otto_proto_test.elf secondary-outputs + +# Tool invocations +otto_proto_test.elf: $(OBJS) $(USER_OBJS) /home/fdila/Projects/otto/utils/proto_test/otto_proto_test/STM32F767ZITX_FLASH.ld + arm-none-eabi-g++ -o "otto_proto_test.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m7 -T"/home/fdila/Projects/otto/utils/proto_test/otto_proto_test/STM32F767ZITX_FLASH.ld" -Wl,-Map="otto_proto_test.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +otto_proto_test.list: $(EXECUTABLES) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "otto_proto_test.list" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) * + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets diff --git a/utils/proto_test/otto_proto_test/Debug/objects.list b/utils/proto_test/otto_proto_test/Debug/objects.list new file mode 100644 index 0000000..e33814f --- /dev/null +++ b/utils/proto_test/otto_proto_test/Debug/objects.list @@ -0,0 +1,30 @@ +"Core/Src/encoder.o" +"Core/Src/main.o" +"Core/Src/pb_common.o" +"Core/Src/pb_decode.o" +"Core/Src/pb_encode.o" +"Core/Src/stm32f7xx_hal_msp.o" +"Core/Src/stm32f7xx_it.o" +"Core/Src/syscalls.o" +"Core/Src/sysmem.o" +"Core/Src/system_stm32f7xx.o" +"Core/Src/velocities.pb.o" +"Core/Startup/startup_stm32f767zitx.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o" diff --git a/utils/proto_test/otto_proto_test/Debug/objects.mk b/utils/proto_test/otto_proto_test/Debug/objects.mk new file mode 100644 index 0000000..742c2da --- /dev/null +++ b/utils/proto_test/otto_proto_test/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/utils/proto_test/otto_proto_test/Debug/otto_proto_test.list b/utils/proto_test/otto_proto_test/Debug/otto_proto_test.list new file mode 100644 index 0000000..80b67fd --- /dev/null +++ b/utils/proto_test/otto_proto_test/Debug/otto_proto_test.list @@ -0,0 +1,22202 @@ + +otto_proto_test.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 000001f8 08000000 08000000 00010000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 000087ec 080001f8 080001f8 000101f8 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00000300 080089e4 080089e4 000189e4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 08008ce4 08008ce4 00020010 2**0 + CONTENTS + 4 .ARM 00000008 08008ce4 08008ce4 00018ce4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 08008cec 08008cec 00020010 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000008 08008cec 08008cec 00018cec 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .fini_array 00000004 08008cf4 08008cf4 00018cf4 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 .data 00000010 20000000 08008cf8 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 00000338 20000010 08008d08 00020010 2**2 + ALLOC + 10 ._user_heap_stack 00000600 20000348 08008d08 00020348 2**0 + ALLOC + 11 .ARM.attributes 0000002e 00000000 00000000 00020010 2**0 + CONTENTS, READONLY + 12 .debug_info 00013a2c 00000000 00000000 0002003e 2**0 + CONTENTS, READONLY, DEBUGGING + 13 .debug_abbrev 000027df 00000000 00000000 00033a6a 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_aranges 00001060 00000000 00000000 00036250 2**3 + CONTENTS, READONLY, DEBUGGING + 15 .debug_ranges 00000f78 00000000 00000000 000372b0 2**3 + CONTENTS, READONLY, DEBUGGING + 16 .debug_macro 0002a477 00000000 00000000 00038228 2**0 + CONTENTS, READONLY, DEBUGGING + 17 .debug_line 0000c3e8 00000000 00000000 0006269f 2**0 + CONTENTS, READONLY, DEBUGGING + 18 .debug_str 000fa3a7 00000000 00000000 0006ea87 2**0 + CONTENTS, READONLY, DEBUGGING + 19 .comment 0000007b 00000000 00000000 00168e2e 2**0 + CONTENTS, READONLY + 20 .debug_frame 000044e8 00000000 00000000 00168eac 2**2 + CONTENTS, READONLY, DEBUGGING + +Disassembly of section .text: + +080001f8 <__do_global_dtors_aux>: + 80001f8: b510 push {r4, lr} + 80001fa: 4c05 ldr r4, [pc, #20] ; (8000210 <__do_global_dtors_aux+0x18>) + 80001fc: 7823 ldrb r3, [r4, #0] + 80001fe: b933 cbnz r3, 800020e <__do_global_dtors_aux+0x16> + 8000200: 4b04 ldr r3, [pc, #16] ; (8000214 <__do_global_dtors_aux+0x1c>) + 8000202: b113 cbz r3, 800020a <__do_global_dtors_aux+0x12> + 8000204: 4804 ldr r0, [pc, #16] ; (8000218 <__do_global_dtors_aux+0x20>) + 8000206: f3af 8000 nop.w + 800020a: 2301 movs r3, #1 + 800020c: 7023 strb r3, [r4, #0] + 800020e: bd10 pop {r4, pc} + 8000210: 20000010 .word 0x20000010 + 8000214: 00000000 .word 0x00000000 + 8000218: 080089cc .word 0x080089cc + +0800021c : + 800021c: b508 push {r3, lr} + 800021e: 4b03 ldr r3, [pc, #12] ; (800022c ) + 8000220: b11b cbz r3, 800022a + 8000222: 4903 ldr r1, [pc, #12] ; (8000230 ) + 8000224: 4803 ldr r0, [pc, #12] ; (8000234 ) + 8000226: f3af 8000 nop.w + 800022a: bd08 pop {r3, pc} + 800022c: 00000000 .word 0x00000000 + 8000230: 20000014 .word 0x20000014 + 8000234: 080089cc .word 0x080089cc + +08000238 <__aeabi_uldivmod>: + 8000238: b953 cbnz r3, 8000250 <__aeabi_uldivmod+0x18> + 800023a: b94a cbnz r2, 8000250 <__aeabi_uldivmod+0x18> + 800023c: 2900 cmp r1, #0 + 800023e: bf08 it eq + 8000240: 2800 cmpeq r0, #0 + 8000242: bf1c itt ne + 8000244: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff + 8000248: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff + 800024c: f000 b972 b.w 8000534 <__aeabi_idiv0> + 8000250: f1ad 0c08 sub.w ip, sp, #8 + 8000254: e96d ce04 strd ip, lr, [sp, #-16]! + 8000258: f000 f806 bl 8000268 <__udivmoddi4> + 800025c: f8dd e004 ldr.w lr, [sp, #4] + 8000260: e9dd 2302 ldrd r2, r3, [sp, #8] + 8000264: b004 add sp, #16 + 8000266: 4770 bx lr + +08000268 <__udivmoddi4>: + 8000268: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800026c: 9e08 ldr r6, [sp, #32] + 800026e: 4604 mov r4, r0 + 8000270: 4688 mov r8, r1 + 8000272: 2b00 cmp r3, #0 + 8000274: d14b bne.n 800030e <__udivmoddi4+0xa6> + 8000276: 428a cmp r2, r1 + 8000278: 4615 mov r5, r2 + 800027a: d967 bls.n 800034c <__udivmoddi4+0xe4> + 800027c: fab2 f282 clz r2, r2 + 8000280: b14a cbz r2, 8000296 <__udivmoddi4+0x2e> + 8000282: f1c2 0720 rsb r7, r2, #32 + 8000286: fa01 f302 lsl.w r3, r1, r2 + 800028a: fa20 f707 lsr.w r7, r0, r7 + 800028e: 4095 lsls r5, r2 + 8000290: ea47 0803 orr.w r8, r7, r3 + 8000294: 4094 lsls r4, r2 + 8000296: ea4f 4e15 mov.w lr, r5, lsr #16 + 800029a: 0c23 lsrs r3, r4, #16 + 800029c: fbb8 f7fe udiv r7, r8, lr + 80002a0: fa1f fc85 uxth.w ip, r5 + 80002a4: fb0e 8817 mls r8, lr, r7, r8 + 80002a8: ea43 4308 orr.w r3, r3, r8, lsl #16 + 80002ac: fb07 f10c mul.w r1, r7, ip + 80002b0: 4299 cmp r1, r3 + 80002b2: d909 bls.n 80002c8 <__udivmoddi4+0x60> + 80002b4: 18eb adds r3, r5, r3 + 80002b6: f107 30ff add.w r0, r7, #4294967295 ; 0xffffffff + 80002ba: f080 811b bcs.w 80004f4 <__udivmoddi4+0x28c> + 80002be: 4299 cmp r1, r3 + 80002c0: f240 8118 bls.w 80004f4 <__udivmoddi4+0x28c> + 80002c4: 3f02 subs r7, #2 + 80002c6: 442b add r3, r5 + 80002c8: 1a5b subs r3, r3, r1 + 80002ca: b2a4 uxth r4, r4 + 80002cc: fbb3 f0fe udiv r0, r3, lr + 80002d0: fb0e 3310 mls r3, lr, r0, r3 + 80002d4: ea44 4403 orr.w r4, r4, r3, lsl #16 + 80002d8: fb00 fc0c mul.w ip, r0, ip + 80002dc: 45a4 cmp ip, r4 + 80002de: d909 bls.n 80002f4 <__udivmoddi4+0x8c> + 80002e0: 192c adds r4, r5, r4 + 80002e2: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff + 80002e6: f080 8107 bcs.w 80004f8 <__udivmoddi4+0x290> + 80002ea: 45a4 cmp ip, r4 + 80002ec: f240 8104 bls.w 80004f8 <__udivmoddi4+0x290> + 80002f0: 3802 subs r0, #2 + 80002f2: 442c add r4, r5 + 80002f4: ea40 4007 orr.w r0, r0, r7, lsl #16 + 80002f8: eba4 040c sub.w r4, r4, ip + 80002fc: 2700 movs r7, #0 + 80002fe: b11e cbz r6, 8000308 <__udivmoddi4+0xa0> + 8000300: 40d4 lsrs r4, r2 + 8000302: 2300 movs r3, #0 + 8000304: e9c6 4300 strd r4, r3, [r6] + 8000308: 4639 mov r1, r7 + 800030a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800030e: 428b cmp r3, r1 + 8000310: d909 bls.n 8000326 <__udivmoddi4+0xbe> + 8000312: 2e00 cmp r6, #0 + 8000314: f000 80eb beq.w 80004ee <__udivmoddi4+0x286> + 8000318: 2700 movs r7, #0 + 800031a: e9c6 0100 strd r0, r1, [r6] + 800031e: 4638 mov r0, r7 + 8000320: 4639 mov r1, r7 + 8000322: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000326: fab3 f783 clz r7, r3 + 800032a: 2f00 cmp r7, #0 + 800032c: d147 bne.n 80003be <__udivmoddi4+0x156> + 800032e: 428b cmp r3, r1 + 8000330: d302 bcc.n 8000338 <__udivmoddi4+0xd0> + 8000332: 4282 cmp r2, r0 + 8000334: f200 80fa bhi.w 800052c <__udivmoddi4+0x2c4> + 8000338: 1a84 subs r4, r0, r2 + 800033a: eb61 0303 sbc.w r3, r1, r3 + 800033e: 2001 movs r0, #1 + 8000340: 4698 mov r8, r3 + 8000342: 2e00 cmp r6, #0 + 8000344: d0e0 beq.n 8000308 <__udivmoddi4+0xa0> + 8000346: e9c6 4800 strd r4, r8, [r6] + 800034a: e7dd b.n 8000308 <__udivmoddi4+0xa0> + 800034c: b902 cbnz r2, 8000350 <__udivmoddi4+0xe8> + 800034e: deff udf #255 ; 0xff + 8000350: fab2 f282 clz r2, r2 + 8000354: 2a00 cmp r2, #0 + 8000356: f040 808f bne.w 8000478 <__udivmoddi4+0x210> + 800035a: 1b49 subs r1, r1, r5 + 800035c: ea4f 4e15 mov.w lr, r5, lsr #16 + 8000360: fa1f f885 uxth.w r8, r5 + 8000364: 2701 movs r7, #1 + 8000366: fbb1 fcfe udiv ip, r1, lr + 800036a: 0c23 lsrs r3, r4, #16 + 800036c: fb0e 111c mls r1, lr, ip, r1 + 8000370: ea43 4301 orr.w r3, r3, r1, lsl #16 + 8000374: fb08 f10c mul.w r1, r8, ip + 8000378: 4299 cmp r1, r3 + 800037a: d907 bls.n 800038c <__udivmoddi4+0x124> + 800037c: 18eb adds r3, r5, r3 + 800037e: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff + 8000382: d202 bcs.n 800038a <__udivmoddi4+0x122> + 8000384: 4299 cmp r1, r3 + 8000386: f200 80cd bhi.w 8000524 <__udivmoddi4+0x2bc> + 800038a: 4684 mov ip, r0 + 800038c: 1a59 subs r1, r3, r1 + 800038e: b2a3 uxth r3, r4 + 8000390: fbb1 f0fe udiv r0, r1, lr + 8000394: fb0e 1410 mls r4, lr, r0, r1 + 8000398: ea43 4404 orr.w r4, r3, r4, lsl #16 + 800039c: fb08 f800 mul.w r8, r8, r0 + 80003a0: 45a0 cmp r8, r4 + 80003a2: d907 bls.n 80003b4 <__udivmoddi4+0x14c> + 80003a4: 192c adds r4, r5, r4 + 80003a6: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff + 80003aa: d202 bcs.n 80003b2 <__udivmoddi4+0x14a> + 80003ac: 45a0 cmp r8, r4 + 80003ae: f200 80b6 bhi.w 800051e <__udivmoddi4+0x2b6> + 80003b2: 4618 mov r0, r3 + 80003b4: eba4 0408 sub.w r4, r4, r8 + 80003b8: ea40 400c orr.w r0, r0, ip, lsl #16 + 80003bc: e79f b.n 80002fe <__udivmoddi4+0x96> + 80003be: f1c7 0c20 rsb ip, r7, #32 + 80003c2: 40bb lsls r3, r7 + 80003c4: fa22 fe0c lsr.w lr, r2, ip + 80003c8: ea4e 0e03 orr.w lr, lr, r3 + 80003cc: fa01 f407 lsl.w r4, r1, r7 + 80003d0: fa20 f50c lsr.w r5, r0, ip + 80003d4: fa21 f30c lsr.w r3, r1, ip + 80003d8: ea4f 481e mov.w r8, lr, lsr #16 + 80003dc: 4325 orrs r5, r4 + 80003de: fbb3 f9f8 udiv r9, r3, r8 + 80003e2: 0c2c lsrs r4, r5, #16 + 80003e4: fb08 3319 mls r3, r8, r9, r3 + 80003e8: fa1f fa8e uxth.w sl, lr + 80003ec: ea44 4303 orr.w r3, r4, r3, lsl #16 + 80003f0: fb09 f40a mul.w r4, r9, sl + 80003f4: 429c cmp r4, r3 + 80003f6: fa02 f207 lsl.w r2, r2, r7 + 80003fa: fa00 f107 lsl.w r1, r0, r7 + 80003fe: d90b bls.n 8000418 <__udivmoddi4+0x1b0> + 8000400: eb1e 0303 adds.w r3, lr, r3 + 8000404: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff + 8000408: f080 8087 bcs.w 800051a <__udivmoddi4+0x2b2> + 800040c: 429c cmp r4, r3 + 800040e: f240 8084 bls.w 800051a <__udivmoddi4+0x2b2> + 8000412: f1a9 0902 sub.w r9, r9, #2 + 8000416: 4473 add r3, lr + 8000418: 1b1b subs r3, r3, r4 + 800041a: b2ad uxth r5, r5 + 800041c: fbb3 f0f8 udiv r0, r3, r8 + 8000420: fb08 3310 mls r3, r8, r0, r3 + 8000424: ea45 4403 orr.w r4, r5, r3, lsl #16 + 8000428: fb00 fa0a mul.w sl, r0, sl + 800042c: 45a2 cmp sl, r4 + 800042e: d908 bls.n 8000442 <__udivmoddi4+0x1da> + 8000430: eb1e 0404 adds.w r4, lr, r4 + 8000434: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff + 8000438: d26b bcs.n 8000512 <__udivmoddi4+0x2aa> + 800043a: 45a2 cmp sl, r4 + 800043c: d969 bls.n 8000512 <__udivmoddi4+0x2aa> + 800043e: 3802 subs r0, #2 + 8000440: 4474 add r4, lr + 8000442: ea40 4009 orr.w r0, r0, r9, lsl #16 + 8000446: fba0 8902 umull r8, r9, r0, r2 + 800044a: eba4 040a sub.w r4, r4, sl + 800044e: 454c cmp r4, r9 + 8000450: 46c2 mov sl, r8 + 8000452: 464b mov r3, r9 + 8000454: d354 bcc.n 8000500 <__udivmoddi4+0x298> + 8000456: d051 beq.n 80004fc <__udivmoddi4+0x294> + 8000458: 2e00 cmp r6, #0 + 800045a: d069 beq.n 8000530 <__udivmoddi4+0x2c8> + 800045c: ebb1 050a subs.w r5, r1, sl + 8000460: eb64 0403 sbc.w r4, r4, r3 + 8000464: fa04 fc0c lsl.w ip, r4, ip + 8000468: 40fd lsrs r5, r7 + 800046a: 40fc lsrs r4, r7 + 800046c: ea4c 0505 orr.w r5, ip, r5 + 8000470: e9c6 5400 strd r5, r4, [r6] + 8000474: 2700 movs r7, #0 + 8000476: e747 b.n 8000308 <__udivmoddi4+0xa0> + 8000478: f1c2 0320 rsb r3, r2, #32 + 800047c: fa20 f703 lsr.w r7, r0, r3 + 8000480: 4095 lsls r5, r2 + 8000482: fa01 f002 lsl.w r0, r1, r2 + 8000486: fa21 f303 lsr.w r3, r1, r3 + 800048a: ea4f 4e15 mov.w lr, r5, lsr #16 + 800048e: 4338 orrs r0, r7 + 8000490: 0c01 lsrs r1, r0, #16 + 8000492: fbb3 f7fe udiv r7, r3, lr + 8000496: fa1f f885 uxth.w r8, r5 + 800049a: fb0e 3317 mls r3, lr, r7, r3 + 800049e: ea41 4103 orr.w r1, r1, r3, lsl #16 + 80004a2: fb07 f308 mul.w r3, r7, r8 + 80004a6: 428b cmp r3, r1 + 80004a8: fa04 f402 lsl.w r4, r4, r2 + 80004ac: d907 bls.n 80004be <__udivmoddi4+0x256> + 80004ae: 1869 adds r1, r5, r1 + 80004b0: f107 3cff add.w ip, r7, #4294967295 ; 0xffffffff + 80004b4: d22f bcs.n 8000516 <__udivmoddi4+0x2ae> + 80004b6: 428b cmp r3, r1 + 80004b8: d92d bls.n 8000516 <__udivmoddi4+0x2ae> + 80004ba: 3f02 subs r7, #2 + 80004bc: 4429 add r1, r5 + 80004be: 1acb subs r3, r1, r3 + 80004c0: b281 uxth r1, r0 + 80004c2: fbb3 f0fe udiv r0, r3, lr + 80004c6: fb0e 3310 mls r3, lr, r0, r3 + 80004ca: ea41 4103 orr.w r1, r1, r3, lsl #16 + 80004ce: fb00 f308 mul.w r3, r0, r8 + 80004d2: 428b cmp r3, r1 + 80004d4: d907 bls.n 80004e6 <__udivmoddi4+0x27e> + 80004d6: 1869 adds r1, r5, r1 + 80004d8: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff + 80004dc: d217 bcs.n 800050e <__udivmoddi4+0x2a6> + 80004de: 428b cmp r3, r1 + 80004e0: d915 bls.n 800050e <__udivmoddi4+0x2a6> + 80004e2: 3802 subs r0, #2 + 80004e4: 4429 add r1, r5 + 80004e6: 1ac9 subs r1, r1, r3 + 80004e8: ea40 4707 orr.w r7, r0, r7, lsl #16 + 80004ec: e73b b.n 8000366 <__udivmoddi4+0xfe> + 80004ee: 4637 mov r7, r6 + 80004f0: 4630 mov r0, r6 + 80004f2: e709 b.n 8000308 <__udivmoddi4+0xa0> + 80004f4: 4607 mov r7, r0 + 80004f6: e6e7 b.n 80002c8 <__udivmoddi4+0x60> + 80004f8: 4618 mov r0, r3 + 80004fa: e6fb b.n 80002f4 <__udivmoddi4+0x8c> + 80004fc: 4541 cmp r1, r8 + 80004fe: d2ab bcs.n 8000458 <__udivmoddi4+0x1f0> + 8000500: ebb8 0a02 subs.w sl, r8, r2 + 8000504: eb69 020e sbc.w r2, r9, lr + 8000508: 3801 subs r0, #1 + 800050a: 4613 mov r3, r2 + 800050c: e7a4 b.n 8000458 <__udivmoddi4+0x1f0> + 800050e: 4660 mov r0, ip + 8000510: e7e9 b.n 80004e6 <__udivmoddi4+0x27e> + 8000512: 4618 mov r0, r3 + 8000514: e795 b.n 8000442 <__udivmoddi4+0x1da> + 8000516: 4667 mov r7, ip + 8000518: e7d1 b.n 80004be <__udivmoddi4+0x256> + 800051a: 4681 mov r9, r0 + 800051c: e77c b.n 8000418 <__udivmoddi4+0x1b0> + 800051e: 3802 subs r0, #2 + 8000520: 442c add r4, r5 + 8000522: e747 b.n 80003b4 <__udivmoddi4+0x14c> + 8000524: f1ac 0c02 sub.w ip, ip, #2 + 8000528: 442b add r3, r5 + 800052a: e72f b.n 800038c <__udivmoddi4+0x124> + 800052c: 4638 mov r0, r7 + 800052e: e708 b.n 8000342 <__udivmoddi4+0xda> + 8000530: 4637 mov r7, r6 + 8000532: e6e9 b.n 8000308 <__udivmoddi4+0xa0> + +08000534 <__aeabi_idiv0>: + 8000534: 4770 bx lr + 8000536: bf00 nop + +08000538 <_ZN7Encoder8GetCountEv>: + Encoder(TIM_HandleTypeDef *timer, int ticks_per_meters); + + + void Setup(); + + int GetCount() { + 8000538: b480 push {r7} + 800053a: b085 sub sp, #20 + 800053c: af00 add r7, sp, #0 + 800053e: 6078 str r0, [r7, #4] + int count = ((int) __HAL_TIM_GET_COUNTER(this->timer_) + 8000540: 687b ldr r3, [r7, #4] + 8000542: 681b ldr r3, [r3, #0] + 8000544: 681b ldr r3, [r3, #0] + 8000546: 6a5a ldr r2, [r3, #36] ; 0x24 + - ((this->timer_->Init.Period) / 2)); + 8000548: 687b ldr r3, [r7, #4] + 800054a: 681b ldr r3, [r3, #0] + 800054c: 68db ldr r3, [r3, #12] + 800054e: 085b lsrs r3, r3, #1 + 8000550: 1ad3 subs r3, r2, r3 + 8000552: 60fb str r3, [r7, #12] + return count; + 8000554: 68fb ldr r3, [r7, #12] + } + 8000556: 4618 mov r0, r3 + 8000558: 3714 adds r7, #20 + 800055a: 46bd mov sp, r7 + 800055c: f85d 7b04 ldr.w r7, [sp], #4 + 8000560: 4770 bx lr + +08000562 <_ZN7Encoder10ResetCountEv>: + + void ResetCount() { + 8000562: b480 push {r7} + 8000564: b083 sub sp, #12 + 8000566: af00 add r7, sp, #0 + 8000568: 6078 str r0, [r7, #4] + //set counter to half its maximum value + __HAL_TIM_SET_COUNTER(timer_, (timer_->Init.Period / 2)); + 800056a: 687b ldr r3, [r7, #4] + 800056c: 681b ldr r3, [r3, #0] + 800056e: 68da ldr r2, [r3, #12] + 8000570: 687b ldr r3, [r7, #4] + 8000572: 681b ldr r3, [r3, #0] + 8000574: 681b ldr r3, [r3, #0] + 8000576: 0852 lsrs r2, r2, #1 + 8000578: 625a str r2, [r3, #36] ; 0x24 + } + 800057a: bf00 nop + 800057c: 370c adds r7, #12 + 800057e: 46bd mov sp, r7 + 8000580: f85d 7b04 ldr.w r7, [sp], #4 + 8000584: 4770 bx lr + +08000586 <_ZN7EncoderC1EP17TIM_HandleTypeDefi>: +// timer_ = timer; +// wheel_circumference_ = wheel_circ; +// +//} + +Encoder::Encoder(TIM_HandleTypeDef *timer, int ticks_per_meter) { + 8000586: b480 push {r7} + 8000588: b085 sub sp, #20 + 800058a: af00 add r7, sp, #0 + 800058c: 60f8 str r0, [r7, #12] + 800058e: 60b9 str r1, [r7, #8] + 8000590: 607a str r2, [r7, #4] + timer_ = timer; + 8000592: 68fb ldr r3, [r7, #12] + 8000594: 68ba ldr r2, [r7, #8] + 8000596: 601a str r2, [r3, #0] + ticks_per_meter_ = ticks_per_meter; + 8000598: 68fb ldr r3, [r7, #12] + 800059a: 687a ldr r2, [r7, #4] + 800059c: 615a str r2, [r3, #20] + +} + 800059e: 68fb ldr r3, [r7, #12] + 80005a0: 4618 mov r0, r3 + 80005a2: 3714 adds r7, #20 + 80005a4: 46bd mov sp, r7 + 80005a6: f85d 7b04 ldr.w r7, [sp], #4 + 80005aa: 4770 bx lr + +080005ac <_ZN7Encoder5SetupEv>: + +void Encoder::Setup() { + 80005ac: b580 push {r7, lr} + 80005ae: b082 sub sp, #8 + 80005b0: af00 add r7, sp, #0 + 80005b2: 6078 str r0, [r7, #4] + HAL_TIM_Encoder_Start(timer_, TIM_CHANNEL_ALL); + 80005b4: 687b ldr r3, [r7, #4] + 80005b6: 681b ldr r3, [r3, #0] + 80005b8: 213c movs r1, #60 ; 0x3c + 80005ba: 4618 mov r0, r3 + 80005bc: f006 faee bl 8006b9c + this->ResetCount(); + 80005c0: 6878 ldr r0, [r7, #4] + 80005c2: f7ff ffce bl 8000562 <_ZN7Encoder10ResetCountEv> + this->previous_millis_ = 0; + 80005c6: 687b ldr r3, [r7, #4] + 80005c8: 2200 movs r2, #0 + 80005ca: 605a str r2, [r3, #4] + this->current_millis_ = HAL_GetTick(); + 80005cc: f004 fe02 bl 80051d4 + 80005d0: 4602 mov r2, r0 + 80005d2: 687b ldr r3, [r7, #4] + 80005d4: 609a str r2, [r3, #8] +} + 80005d6: bf00 nop + 80005d8: 3708 adds r7, #8 + 80005da: 46bd mov sp, r7 + 80005dc: bd80 pop {r7, pc} + +080005de <_ZN7Encoder12UpdateValuesEv>: + +void Encoder::UpdateValues() { + 80005de: b580 push {r7, lr} + 80005e0: b082 sub sp, #8 + 80005e2: af00 add r7, sp, #0 + 80005e4: 6078 str r0, [r7, #4] + this->previous_millis_ = this->current_millis_; + 80005e6: 687b ldr r3, [r7, #4] + 80005e8: 689a ldr r2, [r3, #8] + 80005ea: 687b ldr r3, [r7, #4] + 80005ec: 605a str r2, [r3, #4] + this->current_millis_ = HAL_GetTick(); + 80005ee: f004 fdf1 bl 80051d4 + 80005f2: 4602 mov r2, r0 + 80005f4: 687b ldr r3, [r7, #4] + 80005f6: 609a str r2, [r3, #8] + this->ticks_ = this->GetCount(); + 80005f8: 6878 ldr r0, [r7, #4] + 80005fa: f7ff ff9d bl 8000538 <_ZN7Encoder8GetCountEv> + 80005fe: 4602 mov r2, r0 + 8000600: 687b ldr r3, [r7, #4] + 8000602: 60da str r2, [r3, #12] + this->ResetCount(); + 8000604: 6878 ldr r0, [r7, #4] + 8000606: f7ff ffac bl 8000562 <_ZN7Encoder10ResetCountEv> +} + 800060a: bf00 nop + 800060c: 3708 adds r7, #8 + 800060e: 46bd mov sp, r7 + 8000610: bd80 pop {r7, pc} + +08000612 <_ZN7Encoder9GetMetersEv>: +// float meters = ((float) this->ticks_ * this->wheel_circumference_) +// / TICKS_PER_REVOLUTION; +// return meters; +//} + +float Encoder::GetMeters() { + 8000612: b480 push {r7} + 8000614: b085 sub sp, #20 + 8000616: af00 add r7, sp, #0 + 8000618: 6078 str r0, [r7, #4] + float meters = (((float) this->ticks_) / this->ticks_per_meter_); + 800061a: 687b ldr r3, [r7, #4] + 800061c: 68db ldr r3, [r3, #12] + 800061e: ee07 3a90 vmov s15, r3 + 8000622: eef8 6ae7 vcvt.f32.s32 s13, s15 + 8000626: 687b ldr r3, [r7, #4] + 8000628: 695b ldr r3, [r3, #20] + 800062a: ee07 3a90 vmov s15, r3 + 800062e: eeb8 7ae7 vcvt.f32.s32 s14, s15 + 8000632: eec6 7a87 vdiv.f32 s15, s13, s14 + 8000636: edc7 7a03 vstr s15, [r7, #12] + return meters; + 800063a: 68fb ldr r3, [r7, #12] + 800063c: ee07 3a90 vmov s15, r3 +} + 8000640: eeb0 0a67 vmov.f32 s0, s15 + 8000644: 3714 adds r7, #20 + 8000646: 46bd mov sp, r7 + 8000648: f85d 7b04 ldr.w r7, [sp], #4 + 800064c: 4770 bx lr + ... + +08000650 <_ZN7Encoder17GetLinearVelocityEv>: + + +float Encoder::GetLinearVelocity() { + 8000650: b580 push {r7, lr} + 8000652: b086 sub sp, #24 + 8000654: af00 add r7, sp, #0 + 8000656: 6078 str r0, [r7, #4] + this->UpdateValues(); + 8000658: 6878 ldr r0, [r7, #4] + 800065a: f7ff ffc0 bl 80005de <_ZN7Encoder12UpdateValuesEv> + float meters = this->GetMeters(); + 800065e: 6878 ldr r0, [r7, #4] + 8000660: f7ff ffd7 bl 8000612 <_ZN7Encoder9GetMetersEv> + 8000664: ed87 0a05 vstr s0, [r7, #20] + float deltaTime = this->current_millis_ - this->previous_millis_; + 8000668: 687b ldr r3, [r7, #4] + 800066a: 689a ldr r2, [r3, #8] + 800066c: 687b ldr r3, [r7, #4] + 800066e: 685b ldr r3, [r3, #4] + 8000670: 1ad3 subs r3, r2, r3 + 8000672: ee07 3a90 vmov s15, r3 + 8000676: eef8 7a67 vcvt.f32.u32 s15, s15 + 800067a: edc7 7a04 vstr s15, [r7, #16] + if (deltaTime == 0) + 800067e: edd7 7a04 vldr s15, [r7, #16] + 8000682: eef5 7a40 vcmp.f32 s15, #0.0 + 8000686: eef1 fa10 vmrs APSR_nzcv, fpscr + 800068a: d102 bne.n 8000692 <_ZN7Encoder17GetLinearVelocityEv+0x42> + return 0; + 800068c: f04f 0300 mov.w r3, #0 + 8000690: e00c b.n 80006ac <_ZN7Encoder17GetLinearVelocityEv+0x5c> + float linear_velocity = (meters / (deltaTime / 1000)); + 8000692: edd7 7a04 vldr s15, [r7, #16] + 8000696: eddf 6a09 vldr s13, [pc, #36] ; 80006bc <_ZN7Encoder17GetLinearVelocityEv+0x6c> + 800069a: ee87 7aa6 vdiv.f32 s14, s15, s13 + 800069e: edd7 6a05 vldr s13, [r7, #20] + 80006a2: eec6 7a87 vdiv.f32 s15, s13, s14 + 80006a6: edc7 7a03 vstr s15, [r7, #12] + return linear_velocity; + 80006aa: 68fb ldr r3, [r7, #12] + 80006ac: ee07 3a90 vmov s15, r3 +} + 80006b0: eeb0 0a67 vmov.f32 s0, s15 + 80006b4: 3718 adds r7, #24 + 80006b6: 46bd mov sp, r7 + 80006b8: bd80 pop {r7, pc} + 80006ba: bf00 nop + 80006bc: 447a0000 .word 0x447a0000 + +080006c0 <_ZN8OdometryC1Ev>: + float linear_velocity_; + float angular_velocity_; + + + public: + Odometry() { + 80006c0: b480 push {r7} + 80006c2: b083 sub sp, #12 + 80006c4: af00 add r7, sp, #0 + 80006c6: 6078 str r0, [r7, #4] + left_velocity_ = 0; + 80006c8: 687b ldr r3, [r7, #4] + 80006ca: f04f 0200 mov.w r2, #0 + 80006ce: 601a str r2, [r3, #0] + right_velocity_ = 0; + 80006d0: 687b ldr r3, [r7, #4] + 80006d2: f04f 0200 mov.w r2, #0 + 80006d6: 605a str r2, [r3, #4] + linear_velocity_ = 0; + 80006d8: 687b ldr r3, [r7, #4] + 80006da: f04f 0200 mov.w r2, #0 + 80006de: 609a str r2, [r3, #8] + angular_velocity_ = 0; + 80006e0: 687b ldr r3, [r7, #4] + 80006e2: f04f 0200 mov.w r2, #0 + 80006e6: 60da str r2, [r3, #12] + } + 80006e8: 687b ldr r3, [r7, #4] + 80006ea: 4618 mov r0, r3 + 80006ec: 370c adds r7, #12 + 80006ee: 46bd mov sp, r7 + 80006f0: f85d 7b04 ldr.w r7, [sp], #4 + 80006f4: 4770 bx lr + ... + +080006f8 <_ZN8Odometry19UpdateValuesFromVelEff>: + + void UpdateValuesFromVel(float linear_vel, float angular_vel) { + 80006f8: b480 push {r7} + 80006fa: b085 sub sp, #20 + 80006fc: af00 add r7, sp, #0 + 80006fe: 60f8 str r0, [r7, #12] + 8000700: ed87 0a02 vstr s0, [r7, #8] + 8000704: edc7 0a01 vstr s1, [r7, #4] + left_velocity_ = linear_vel - (BASELINE * angular_vel)/2; + 8000708: edd7 7a02 vldr s15, [r7, #8] + 800070c: eeb7 6ae7 vcvt.f64.f32 d6, s15 + 8000710: edd7 7a01 vldr s15, [r7, #4] + 8000714: eeb7 7ae7 vcvt.f64.f32 d7, s15 + 8000718: ed9f 5b15 vldr d5, [pc, #84] ; 8000770 <_ZN8Odometry19UpdateValuesFromVelEff+0x78> + 800071c: ee27 5b05 vmul.f64 d5, d7, d5 + 8000720: eeb0 4b00 vmov.f64 d4, #0 ; 0x40000000 2.0 + 8000724: ee85 7b04 vdiv.f64 d7, d5, d4 + 8000728: ee36 7b47 vsub.f64 d7, d6, d7 + 800072c: eef7 7bc7 vcvt.f32.f64 s15, d7 + 8000730: 68fb ldr r3, [r7, #12] + 8000732: edc3 7a00 vstr s15, [r3] + right_velocity_ = linear_vel + (BASELINE * angular_vel)/2; + 8000736: edd7 7a02 vldr s15, [r7, #8] + 800073a: eeb7 6ae7 vcvt.f64.f32 d6, s15 + 800073e: edd7 7a01 vldr s15, [r7, #4] + 8000742: eeb7 7ae7 vcvt.f64.f32 d7, s15 + 8000746: ed9f 5b0a vldr d5, [pc, #40] ; 8000770 <_ZN8Odometry19UpdateValuesFromVelEff+0x78> + 800074a: ee27 5b05 vmul.f64 d5, d7, d5 + 800074e: eeb0 4b00 vmov.f64 d4, #0 ; 0x40000000 2.0 + 8000752: ee85 7b04 vdiv.f64 d7, d5, d4 + 8000756: ee36 7b07 vadd.f64 d7, d6, d7 + 800075a: eef7 7bc7 vcvt.f32.f64 s15, d7 + 800075e: 68fb ldr r3, [r7, #12] + 8000760: edc3 7a01 vstr s15, [r3, #4] + } + 8000764: bf00 nop + 8000766: 3714 adds r7, #20 + 8000768: 46bd mov sp, r7 + 800076a: f85d 7b04 ldr.w r7, [sp], #4 + 800076e: 4770 bx lr + 8000770: 33333333 .word 0x33333333 + 8000774: 3fd33333 .word 0x3fd33333 + +08000778 <_ZN8Odometry22UpdateValuesFromWheelsEff>: + + void UpdateValuesFromWheels(float left_velocity, float right_velocity){ + 8000778: b480 push {r7} + 800077a: b085 sub sp, #20 + 800077c: af00 add r7, sp, #0 + 800077e: 60f8 str r0, [r7, #12] + 8000780: ed87 0a02 vstr s0, [r7, #8] + 8000784: edc7 0a01 vstr s1, [r7, #4] + linear_velocity_ = (left_velocity + right_velocity)/2; + 8000788: ed97 7a02 vldr s14, [r7, #8] + 800078c: edd7 7a01 vldr s15, [r7, #4] + 8000790: ee37 7a27 vadd.f32 s14, s14, s15 + 8000794: eef0 6a00 vmov.f32 s13, #0 ; 0x40000000 2.0 + 8000798: eec7 7a26 vdiv.f32 s15, s14, s13 + 800079c: 68fb ldr r3, [r7, #12] + 800079e: edc3 7a02 vstr s15, [r3, #8] + angular_velocity_ = (right_velocity - left_velocity)/BASELINE; + 80007a2: ed97 7a01 vldr s14, [r7, #4] + 80007a6: edd7 7a02 vldr s15, [r7, #8] + 80007aa: ee77 7a67 vsub.f32 s15, s14, s15 + 80007ae: eeb7 6ae7 vcvt.f64.f32 d6, s15 + 80007b2: ed9f 5b07 vldr d5, [pc, #28] ; 80007d0 <_ZN8Odometry22UpdateValuesFromWheelsEff+0x58> + 80007b6: ee86 7b05 vdiv.f64 d7, d6, d5 + 80007ba: eef7 7bc7 vcvt.f32.f64 s15, d7 + 80007be: 68fb ldr r3, [r7, #12] + 80007c0: edc3 7a03 vstr s15, [r3, #12] + } + 80007c4: bf00 nop + 80007c6: 3714 adds r7, #20 + 80007c8: 46bd mov sp, r7 + 80007ca: f85d 7b04 ldr.w r7, [sp], #4 + 80007ce: 4770 bx lr + 80007d0: 33333333 .word 0x33333333 + 80007d4: 3fd33333 .word 0x3fd33333 + +080007d8 <_ZN8Odometry15GetLeftVelocityEv>: + + + float GetLeftVelocity(){ + 80007d8: b480 push {r7} + 80007da: b083 sub sp, #12 + 80007dc: af00 add r7, sp, #0 + 80007de: 6078 str r0, [r7, #4] + return left_velocity_; + 80007e0: 687b ldr r3, [r7, #4] + 80007e2: 681b ldr r3, [r3, #0] + 80007e4: ee07 3a90 vmov s15, r3 + } + 80007e8: eeb0 0a67 vmov.f32 s0, s15 + 80007ec: 370c adds r7, #12 + 80007ee: 46bd mov sp, r7 + 80007f0: f85d 7b04 ldr.w r7, [sp], #4 + 80007f4: 4770 bx lr + +080007f6 <_ZN8Odometry16GetRightVelocityEv>: + float GetRightVelocity(){ + 80007f6: b480 push {r7} + 80007f8: b083 sub sp, #12 + 80007fa: af00 add r7, sp, #0 + 80007fc: 6078 str r0, [r7, #4] + return right_velocity_; + 80007fe: 687b ldr r3, [r7, #4] + 8000800: 685b ldr r3, [r3, #4] + 8000802: ee07 3a90 vmov s15, r3 + } + 8000806: eeb0 0a67 vmov.f32 s0, s15 + 800080a: 370c adds r7, #12 + 800080c: 46bd mov sp, r7 + 800080e: f85d 7b04 ldr.w r7, [sp], #4 + 8000812: 4770 bx lr + +08000814 <_ZN8Odometry17GetLinearVelocityEv>: + float GetLinearVelocity(){ + 8000814: b480 push {r7} + 8000816: b083 sub sp, #12 + 8000818: af00 add r7, sp, #0 + 800081a: 6078 str r0, [r7, #4] + return linear_velocity_; + 800081c: 687b ldr r3, [r7, #4] + 800081e: 689b ldr r3, [r3, #8] + 8000820: ee07 3a90 vmov s15, r3 + } + 8000824: eeb0 0a67 vmov.f32 s0, s15 + 8000828: 370c adds r7, #12 + 800082a: 46bd mov sp, r7 + 800082c: f85d 7b04 ldr.w r7, [sp], #4 + 8000830: 4770 bx lr + +08000832 <_ZN8Odometry18GetAngularVelocityEv>: + float GetAngularVelocity(){ + 8000832: b480 push {r7} + 8000834: b083 sub sp, #12 + 8000836: af00 add r7, sp, #0 + 8000838: 6078 str r0, [r7, #4] + return angular_velocity_; + 800083a: 687b ldr r3, [r7, #4] + 800083c: 68db ldr r3, [r3, #12] + 800083e: ee07 3a90 vmov s15, r3 + } + 8000842: eeb0 0a67 vmov.f32 s0, s15 + 8000846: 370c adds r7, #12 + 8000848: 46bd mov sp, r7 + 800084a: f85d 7b04 ldr.w r7, [sp], #4 + 800084e: 4770 bx lr + +08000850 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>: + GPIO_TypeDef *dir_gpio_port_; + uint16_t dir_pin_; + TIM_HandleTypeDef *pwm_timer_; + uint32_t pwm_channel_; + + MotorController(GPIO_TypeDef *sleep_gpio_port, uint16_t sleep_pin, + 8000850: b480 push {r7} + 8000852: b085 sub sp, #20 + 8000854: af00 add r7, sp, #0 + 8000856: 60f8 str r0, [r7, #12] + 8000858: 60b9 str r1, [r7, #8] + 800085a: 603b str r3, [r7, #0] + 800085c: 4613 mov r3, r2 + 800085e: 80fb strh r3, [r7, #6] + GPIO_TypeDef *dir_gpio_port, uint16_t dir_pin, + TIM_HandleTypeDef *pwm_timer, uint32_t pwm_channel) { + this->sleep_gpio_port_ = sleep_gpio_port; + 8000860: 68fb ldr r3, [r7, #12] + 8000862: 68ba ldr r2, [r7, #8] + 8000864: 601a str r2, [r3, #0] + this->sleep_pin_ = sleep_pin; + 8000866: 68fb ldr r3, [r7, #12] + 8000868: 88fa ldrh r2, [r7, #6] + 800086a: 809a strh r2, [r3, #4] + this->dir_gpio_port_ = dir_gpio_port; + 800086c: 68fb ldr r3, [r7, #12] + 800086e: 683a ldr r2, [r7, #0] + 8000870: 609a str r2, [r3, #8] + this->dir_pin_ = dir_pin; + 8000872: 68fb ldr r3, [r7, #12] + 8000874: 8b3a ldrh r2, [r7, #24] + 8000876: 819a strh r2, [r3, #12] + this->pwm_timer_ = pwm_timer; + 8000878: 68fb ldr r3, [r7, #12] + 800087a: 69fa ldr r2, [r7, #28] + 800087c: 611a str r2, [r3, #16] + this->pwm_channel_ = pwm_channel; + 800087e: 68fb ldr r3, [r7, #12] + 8000880: 6a3a ldr r2, [r7, #32] + 8000882: 615a str r2, [r3, #20] + } + 8000884: 68fb ldr r3, [r7, #12] + 8000886: 4618 mov r0, r3 + 8000888: 3714 adds r7, #20 + 800088a: 46bd mov sp, r7 + 800088c: f85d 7b04 ldr.w r7, [sp], #4 + 8000890: 4770 bx lr + +08000892 <_ZN15MotorController5setupEv>: + + void setup() { + 8000892: b580 push {r7, lr} + 8000894: b082 sub sp, #8 + 8000896: af00 add r7, sp, #0 + 8000898: 6078 str r0, [r7, #4] + HAL_TIM_PWM_Start(pwm_timer_, pwm_channel_); + 800089a: 687b ldr r3, [r7, #4] + 800089c: 691a ldr r2, [r3, #16] + 800089e: 687b ldr r3, [r7, #4] + 80008a0: 695b ldr r3, [r3, #20] + 80008a2: 4619 mov r1, r3 + 80008a4: 4610 mov r0, r2 + 80008a6: f006 f8a3 bl 80069f0 + } + 80008aa: bf00 nop + 80008ac: 3708 adds r7, #8 + 80008ae: 46bd mov sp, r7 + 80008b0: bd80 pop {r7, pc} + ... + +080008b4 <_ZN15MotorController9set_speedEi>: + + void set_speed(int duty_cycle) { + 80008b4: b580 push {r7, lr} + 80008b6: b082 sub sp, #8 + 80008b8: af00 add r7, sp, #0 + 80008ba: 6078 str r0, [r7, #4] + 80008bc: 6039 str r1, [r7, #0] + if (duty_cycle >= 0) { + 80008be: 683b ldr r3, [r7, #0] + 80008c0: 2b00 cmp r3, #0 + 80008c2: f2c0 8083 blt.w 80009cc <_ZN15MotorController9set_speedEi+0x118> + //set direction to forward + HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_SET); + 80008c6: 687b ldr r3, [r7, #4] + 80008c8: 6898 ldr r0, [r3, #8] + 80008ca: 687b ldr r3, [r7, #4] + 80008cc: 899b ldrh r3, [r3, #12] + 80008ce: 2201 movs r2, #1 + 80008d0: 4619 mov r1, r3 + 80008d2: f004 ff69 bl 80057a8 + + //check if duty_cycle exceeds maximum + if (duty_cycle > MAX_DUTY_CYCLE) + 80008d6: 683b ldr r3, [r7, #0] + 80008d8: f240 3216 movw r2, #790 ; 0x316 + 80008dc: 4293 cmp r3, r2 + 80008de: dd3d ble.n 800095c <_ZN15MotorController9set_speedEi+0xa8> + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, MAX_DUTY_CYCLE); + 80008e0: 687b ldr r3, [r7, #4] + 80008e2: 695b ldr r3, [r3, #20] + 80008e4: 2b00 cmp r3, #0 + 80008e6: d106 bne.n 80008f6 <_ZN15MotorController9set_speedEi+0x42> + 80008e8: 687b ldr r3, [r7, #4] + 80008ea: 691b ldr r3, [r3, #16] + 80008ec: 681b ldr r3, [r3, #0] + 80008ee: f240 3216 movw r2, #790 ; 0x316 + 80008f2: 635a str r2, [r3, #52] ; 0x34 + 80008f4: e0f5 b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 80008f6: 687b ldr r3, [r7, #4] + 80008f8: 695b ldr r3, [r3, #20] + 80008fa: 2b04 cmp r3, #4 + 80008fc: d106 bne.n 800090c <_ZN15MotorController9set_speedEi+0x58> + 80008fe: 687b ldr r3, [r7, #4] + 8000900: 691b ldr r3, [r3, #16] + 8000902: 681b ldr r3, [r3, #0] + 8000904: f240 3216 movw r2, #790 ; 0x316 + 8000908: 639a str r2, [r3, #56] ; 0x38 + 800090a: e0ea b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 800090c: 687b ldr r3, [r7, #4] + 800090e: 695b ldr r3, [r3, #20] + 8000910: 2b08 cmp r3, #8 + 8000912: d106 bne.n 8000922 <_ZN15MotorController9set_speedEi+0x6e> + 8000914: 687b ldr r3, [r7, #4] + 8000916: 691b ldr r3, [r3, #16] + 8000918: 681b ldr r3, [r3, #0] + 800091a: f240 3216 movw r2, #790 ; 0x316 + 800091e: 63da str r2, [r3, #60] ; 0x3c + 8000920: e0df b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 8000922: 687b ldr r3, [r7, #4] + 8000924: 695b ldr r3, [r3, #20] + 8000926: 2b0c cmp r3, #12 + 8000928: d106 bne.n 8000938 <_ZN15MotorController9set_speedEi+0x84> + 800092a: 687b ldr r3, [r7, #4] + 800092c: 691b ldr r3, [r3, #16] + 800092e: 681b ldr r3, [r3, #0] + 8000930: f240 3216 movw r2, #790 ; 0x316 + 8000934: 641a str r2, [r3, #64] ; 0x40 + 8000936: e0d4 b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 8000938: 687b ldr r3, [r7, #4] + 800093a: 695b ldr r3, [r3, #20] + 800093c: 2b10 cmp r3, #16 + 800093e: d106 bne.n 800094e <_ZN15MotorController9set_speedEi+0x9a> + 8000940: 687b ldr r3, [r7, #4] + 8000942: 691b ldr r3, [r3, #16] + 8000944: 681b ldr r3, [r3, #0] + 8000946: f240 3216 movw r2, #790 ; 0x316 + 800094a: 659a str r2, [r3, #88] ; 0x58 + 800094c: e0c9 b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 800094e: 687b ldr r3, [r7, #4] + 8000950: 691b ldr r3, [r3, #16] + 8000952: 681b ldr r3, [r3, #0] + 8000954: f240 3216 movw r2, #790 ; 0x316 + 8000958: 65da str r2, [r3, #92] ; 0x5c + 800095a: e0c2 b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + else + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle); + 800095c: 687b ldr r3, [r7, #4] + 800095e: 695b ldr r3, [r3, #20] + 8000960: 2b00 cmp r3, #0 + 8000962: d105 bne.n 8000970 <_ZN15MotorController9set_speedEi+0xbc> + 8000964: 683a ldr r2, [r7, #0] + 8000966: 687b ldr r3, [r7, #4] + 8000968: 691b ldr r3, [r3, #16] + 800096a: 681b ldr r3, [r3, #0] + 800096c: 635a str r2, [r3, #52] ; 0x34 + 800096e: e0b8 b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 8000970: 687b ldr r3, [r7, #4] + 8000972: 695b ldr r3, [r3, #20] + 8000974: 2b04 cmp r3, #4 + 8000976: d105 bne.n 8000984 <_ZN15MotorController9set_speedEi+0xd0> + 8000978: 683a ldr r2, [r7, #0] + 800097a: 687b ldr r3, [r7, #4] + 800097c: 691b ldr r3, [r3, #16] + 800097e: 681b ldr r3, [r3, #0] + 8000980: 639a str r2, [r3, #56] ; 0x38 + 8000982: e0ae b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 8000984: 687b ldr r3, [r7, #4] + 8000986: 695b ldr r3, [r3, #20] + 8000988: 2b08 cmp r3, #8 + 800098a: d105 bne.n 8000998 <_ZN15MotorController9set_speedEi+0xe4> + 800098c: 683a ldr r2, [r7, #0] + 800098e: 687b ldr r3, [r7, #4] + 8000990: 691b ldr r3, [r3, #16] + 8000992: 681b ldr r3, [r3, #0] + 8000994: 63da str r2, [r3, #60] ; 0x3c + 8000996: e0a4 b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 8000998: 687b ldr r3, [r7, #4] + 800099a: 695b ldr r3, [r3, #20] + 800099c: 2b0c cmp r3, #12 + 800099e: d105 bne.n 80009ac <_ZN15MotorController9set_speedEi+0xf8> + 80009a0: 683a ldr r2, [r7, #0] + 80009a2: 687b ldr r3, [r7, #4] + 80009a4: 691b ldr r3, [r3, #16] + 80009a6: 681b ldr r3, [r3, #0] + 80009a8: 641a str r2, [r3, #64] ; 0x40 + 80009aa: e09a b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 80009ac: 687b ldr r3, [r7, #4] + 80009ae: 695b ldr r3, [r3, #20] + 80009b0: 2b10 cmp r3, #16 + 80009b2: d105 bne.n 80009c0 <_ZN15MotorController9set_speedEi+0x10c> + 80009b4: 683a ldr r2, [r7, #0] + 80009b6: 687b ldr r3, [r7, #4] + 80009b8: 691b ldr r3, [r3, #16] + 80009ba: 681b ldr r3, [r3, #0] + 80009bc: 659a str r2, [r3, #88] ; 0x58 + 80009be: e090 b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 80009c0: 683a ldr r2, [r7, #0] + 80009c2: 687b ldr r3, [r7, #4] + 80009c4: 691b ldr r3, [r3, #16] + 80009c6: 681b ldr r3, [r3, #0] + 80009c8: 65da str r2, [r3, #92] ; 0x5c + 80009ca: e08a b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + + } else if (duty_cycle < 0){ + 80009cc: 683b ldr r3, [r7, #0] + 80009ce: 2b00 cmp r3, #0 + 80009d0: f280 8087 bge.w 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + //set direction to backwards + HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_RESET); + 80009d4: 687b ldr r3, [r7, #4] + 80009d6: 6898 ldr r0, [r3, #8] + 80009d8: 687b ldr r3, [r7, #4] + 80009da: 899b ldrh r3, [r3, #12] + 80009dc: 2200 movs r2, #0 + 80009de: 4619 mov r1, r3 + 80009e0: f004 fee2 bl 80057a8 + + //check if duty_cycle is lower than minimum + if (duty_cycle < -MAX_DUTY_CYCLE) + 80009e4: 683b ldr r3, [r7, #0] + 80009e6: 4a45 ldr r2, [pc, #276] ; (8000afc <_ZN15MotorController9set_speedEi+0x248>) + 80009e8: 4293 cmp r3, r2 + 80009ea: da3d bge.n 8000a68 <_ZN15MotorController9set_speedEi+0x1b4> + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, MAX_DUTY_CYCLE); + 80009ec: 687b ldr r3, [r7, #4] + 80009ee: 695b ldr r3, [r3, #20] + 80009f0: 2b00 cmp r3, #0 + 80009f2: d106 bne.n 8000a02 <_ZN15MotorController9set_speedEi+0x14e> + 80009f4: 687b ldr r3, [r7, #4] + 80009f6: 691b ldr r3, [r3, #16] + 80009f8: 681b ldr r3, [r3, #0] + 80009fa: f240 3216 movw r2, #790 ; 0x316 + 80009fe: 635a str r2, [r3, #52] ; 0x34 + 8000a00: e06f b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 8000a02: 687b ldr r3, [r7, #4] + 8000a04: 695b ldr r3, [r3, #20] + 8000a06: 2b04 cmp r3, #4 + 8000a08: d106 bne.n 8000a18 <_ZN15MotorController9set_speedEi+0x164> + 8000a0a: 687b ldr r3, [r7, #4] + 8000a0c: 691b ldr r3, [r3, #16] + 8000a0e: 681b ldr r3, [r3, #0] + 8000a10: f240 3216 movw r2, #790 ; 0x316 + 8000a14: 639a str r2, [r3, #56] ; 0x38 + 8000a16: e064 b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 8000a18: 687b ldr r3, [r7, #4] + 8000a1a: 695b ldr r3, [r3, #20] + 8000a1c: 2b08 cmp r3, #8 + 8000a1e: d106 bne.n 8000a2e <_ZN15MotorController9set_speedEi+0x17a> + 8000a20: 687b ldr r3, [r7, #4] + 8000a22: 691b ldr r3, [r3, #16] + 8000a24: 681b ldr r3, [r3, #0] + 8000a26: f240 3216 movw r2, #790 ; 0x316 + 8000a2a: 63da str r2, [r3, #60] ; 0x3c + 8000a2c: e059 b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 8000a2e: 687b ldr r3, [r7, #4] + 8000a30: 695b ldr r3, [r3, #20] + 8000a32: 2b0c cmp r3, #12 + 8000a34: d106 bne.n 8000a44 <_ZN15MotorController9set_speedEi+0x190> + 8000a36: 687b ldr r3, [r7, #4] + 8000a38: 691b ldr r3, [r3, #16] + 8000a3a: 681b ldr r3, [r3, #0] + 8000a3c: f240 3216 movw r2, #790 ; 0x316 + 8000a40: 641a str r2, [r3, #64] ; 0x40 + 8000a42: e04e b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 8000a44: 687b ldr r3, [r7, #4] + 8000a46: 695b ldr r3, [r3, #20] + 8000a48: 2b10 cmp r3, #16 + 8000a4a: d106 bne.n 8000a5a <_ZN15MotorController9set_speedEi+0x1a6> + 8000a4c: 687b ldr r3, [r7, #4] + 8000a4e: 691b ldr r3, [r3, #16] + 8000a50: 681b ldr r3, [r3, #0] + 8000a52: f240 3216 movw r2, #790 ; 0x316 + 8000a56: 659a str r2, [r3, #88] ; 0x58 + 8000a58: e043 b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 8000a5a: 687b ldr r3, [r7, #4] + 8000a5c: 691b ldr r3, [r3, #16] + 8000a5e: 681b ldr r3, [r3, #0] + 8000a60: f240 3216 movw r2, #790 ; 0x316 + 8000a64: 65da str r2, [r3, #92] ; 0x5c + 8000a66: e03c b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + else + //invert sign to make duty_cycle positive + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle); + 8000a68: 687b ldr r3, [r7, #4] + 8000a6a: 695b ldr r3, [r3, #20] + 8000a6c: 2b00 cmp r3, #0 + 8000a6e: d106 bne.n 8000a7e <_ZN15MotorController9set_speedEi+0x1ca> + 8000a70: 683b ldr r3, [r7, #0] + 8000a72: 425a negs r2, r3 + 8000a74: 687b ldr r3, [r7, #4] + 8000a76: 691b ldr r3, [r3, #16] + 8000a78: 681b ldr r3, [r3, #0] + 8000a7a: 635a str r2, [r3, #52] ; 0x34 + 8000a7c: e031 b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 8000a7e: 687b ldr r3, [r7, #4] + 8000a80: 695b ldr r3, [r3, #20] + 8000a82: 2b04 cmp r3, #4 + 8000a84: d106 bne.n 8000a94 <_ZN15MotorController9set_speedEi+0x1e0> + 8000a86: 683b ldr r3, [r7, #0] + 8000a88: 425a negs r2, r3 + 8000a8a: 687b ldr r3, [r7, #4] + 8000a8c: 691b ldr r3, [r3, #16] + 8000a8e: 681b ldr r3, [r3, #0] + 8000a90: 639a str r2, [r3, #56] ; 0x38 + 8000a92: e026 b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 8000a94: 687b ldr r3, [r7, #4] + 8000a96: 695b ldr r3, [r3, #20] + 8000a98: 2b08 cmp r3, #8 + 8000a9a: d106 bne.n 8000aaa <_ZN15MotorController9set_speedEi+0x1f6> + 8000a9c: 683b ldr r3, [r7, #0] + 8000a9e: 425a negs r2, r3 + 8000aa0: 687b ldr r3, [r7, #4] + 8000aa2: 691b ldr r3, [r3, #16] + 8000aa4: 681b ldr r3, [r3, #0] + 8000aa6: 63da str r2, [r3, #60] ; 0x3c + 8000aa8: e01b b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 8000aaa: 687b ldr r3, [r7, #4] + 8000aac: 695b ldr r3, [r3, #20] + 8000aae: 2b0c cmp r3, #12 + 8000ab0: d106 bne.n 8000ac0 <_ZN15MotorController9set_speedEi+0x20c> + 8000ab2: 683b ldr r3, [r7, #0] + 8000ab4: 425a negs r2, r3 + 8000ab6: 687b ldr r3, [r7, #4] + 8000ab8: 691b ldr r3, [r3, #16] + 8000aba: 681b ldr r3, [r3, #0] + 8000abc: 641a str r2, [r3, #64] ; 0x40 + 8000abe: e010 b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 8000ac0: 687b ldr r3, [r7, #4] + 8000ac2: 695b ldr r3, [r3, #20] + 8000ac4: 2b10 cmp r3, #16 + 8000ac6: d106 bne.n 8000ad6 <_ZN15MotorController9set_speedEi+0x222> + 8000ac8: 683b ldr r3, [r7, #0] + 8000aca: 425a negs r2, r3 + 8000acc: 687b ldr r3, [r7, #4] + 8000ace: 691b ldr r3, [r3, #16] + 8000ad0: 681b ldr r3, [r3, #0] + 8000ad2: 659a str r2, [r3, #88] ; 0x58 + 8000ad4: e005 b.n 8000ae2 <_ZN15MotorController9set_speedEi+0x22e> + 8000ad6: 683b ldr r3, [r7, #0] + 8000ad8: 425a negs r2, r3 + 8000ada: 687b ldr r3, [r7, #4] + 8000adc: 691b ldr r3, [r3, #16] + 8000ade: 681b ldr r3, [r3, #0] + 8000ae0: 65da str r2, [r3, #92] ; 0x5c + } + + HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET); + 8000ae2: 687b ldr r3, [r7, #4] + 8000ae4: 6818 ldr r0, [r3, #0] + 8000ae6: 687b ldr r3, [r7, #4] + 8000ae8: 889b ldrh r3, [r3, #4] + 8000aea: 2201 movs r2, #1 + 8000aec: 4619 mov r1, r3 + 8000aee: f004 fe5b bl 80057a8 + + } + 8000af2: bf00 nop + 8000af4: 3708 adds r7, #8 + 8000af6: 46bd mov sp, r7 + 8000af8: bd80 pop {r7, pc} + 8000afa: bf00 nop + 8000afc: fffffcea .word 0xfffffcea + +08000b00 <_ZN15MotorController5coastEv>: + void brake() { + HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET); + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 0); + } + + void coast() { + 8000b00: b580 push {r7, lr} + 8000b02: b082 sub sp, #8 + 8000b04: af00 add r7, sp, #0 + 8000b06: 6078 str r0, [r7, #4] + HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_RESET); + 8000b08: 687b ldr r3, [r7, #4] + 8000b0a: 6818 ldr r0, [r3, #0] + 8000b0c: 687b ldr r3, [r7, #4] + 8000b0e: 889b ldrh r3, [r3, #4] + 8000b10: 2200 movs r2, #0 + 8000b12: 4619 mov r1, r3 + 8000b14: f004 fe48 bl 80057a8 + } + 8000b18: bf00 nop + 8000b1a: 3708 adds r7, #8 + 8000b1c: 46bd mov sp, r7 + 8000b1e: bd80 pop {r7, pc} + +08000b20 <_ZN3PidC1Efff>: + float previous_error_; + + int min_; + int max_; + + Pid(float kp, float ki, float kd) { + 8000b20: b480 push {r7} + 8000b22: b085 sub sp, #20 + 8000b24: af00 add r7, sp, #0 + 8000b26: 60f8 str r0, [r7, #12] + 8000b28: ed87 0a02 vstr s0, [r7, #8] + 8000b2c: edc7 0a01 vstr s1, [r7, #4] + 8000b30: ed87 1a00 vstr s2, [r7] + this->kp_ = kp; + 8000b34: 68fb ldr r3, [r7, #12] + 8000b36: 68ba ldr r2, [r7, #8] + 8000b38: 601a str r2, [r3, #0] + this->ki_ = ki; + 8000b3a: 68fb ldr r3, [r7, #12] + 8000b3c: 687a ldr r2, [r7, #4] + 8000b3e: 605a str r2, [r3, #4] + this->kd_ = kd; + 8000b40: 68fb ldr r3, [r7, #12] + 8000b42: 683a ldr r2, [r7, #0] + 8000b44: 609a str r2, [r3, #8] + + this->error_ = 0; + 8000b46: 68fb ldr r3, [r7, #12] + 8000b48: f04f 0200 mov.w r2, #0 + 8000b4c: 60da str r2, [r3, #12] + this->setpoint_ = 0; + 8000b4e: 68fb ldr r3, [r7, #12] + 8000b50: f04f 0200 mov.w r2, #0 + 8000b54: 611a str r2, [r3, #16] + + this->previous_error_ = 0; + 8000b56: 68fb ldr r3, [r7, #12] + 8000b58: f04f 0200 mov.w r2, #0 + 8000b5c: 619a str r2, [r3, #24] + this->error_sum_ = 0; + 8000b5e: 68fb ldr r3, [r7, #12] + 8000b60: f04f 0200 mov.w r2, #0 + 8000b64: 615a str r2, [r3, #20] + + this->min_ = -MAX_DUTY_CYCLE; + 8000b66: 68fb ldr r3, [r7, #12] + 8000b68: 4a06 ldr r2, [pc, #24] ; (8000b84 <_ZN3PidC1Efff+0x64>) + 8000b6a: 61da str r2, [r3, #28] + this->max_ = MAX_DUTY_CYCLE; + 8000b6c: 68fb ldr r3, [r7, #12] + 8000b6e: f240 3216 movw r2, #790 ; 0x316 + 8000b72: 621a str r2, [r3, #32] + + } + 8000b74: 68fb ldr r3, [r7, #12] + 8000b76: 4618 mov r0, r3 + 8000b78: 3714 adds r7, #20 + 8000b7a: 46bd mov sp, r7 + 8000b7c: f85d 7b04 ldr.w r7, [sp], #4 + 8000b80: 4770 bx lr + 8000b82: bf00 nop + 8000b84: fffffcea .word 0xfffffcea + +08000b88 <_ZN3Pid6configEfff>: + + void config(float kp, float ki, float kd) { + 8000b88: b480 push {r7} + 8000b8a: b085 sub sp, #20 + 8000b8c: af00 add r7, sp, #0 + 8000b8e: 60f8 str r0, [r7, #12] + 8000b90: ed87 0a02 vstr s0, [r7, #8] + 8000b94: edc7 0a01 vstr s1, [r7, #4] + 8000b98: ed87 1a00 vstr s2, [r7] + this->kp_ = kp; + 8000b9c: 68fb ldr r3, [r7, #12] + 8000b9e: 68ba ldr r2, [r7, #8] + 8000ba0: 601a str r2, [r3, #0] + this->ki_ = ki; + 8000ba2: 68fb ldr r3, [r7, #12] + 8000ba4: 687a ldr r2, [r7, #4] + 8000ba6: 605a str r2, [r3, #4] + this->kd_ = kd; + 8000ba8: 68fb ldr r3, [r7, #12] + 8000baa: 683a ldr r2, [r7, #0] + 8000bac: 609a str r2, [r3, #8] + + this->error_ = 0; + 8000bae: 68fb ldr r3, [r7, #12] + 8000bb0: f04f 0200 mov.w r2, #0 + 8000bb4: 60da str r2, [r3, #12] + this->setpoint_ = 0; + 8000bb6: 68fb ldr r3, [r7, #12] + 8000bb8: f04f 0200 mov.w r2, #0 + 8000bbc: 611a str r2, [r3, #16] + + this->previous_error_ = 0; + 8000bbe: 68fb ldr r3, [r7, #12] + 8000bc0: f04f 0200 mov.w r2, #0 + 8000bc4: 619a str r2, [r3, #24] + this->error_sum_ = 0; + 8000bc6: 68fb ldr r3, [r7, #12] + 8000bc8: f04f 0200 mov.w r2, #0 + 8000bcc: 615a str r2, [r3, #20] + + } + 8000bce: bf00 nop + 8000bd0: 3714 adds r7, #20 + 8000bd2: 46bd mov sp, r7 + 8000bd4: f85d 7b04 ldr.w r7, [sp], #4 + 8000bd8: 4770 bx lr + +08000bda <_ZN3Pid3setEf>: + + void set(float setpoint) { + 8000bda: b480 push {r7} + 8000bdc: b083 sub sp, #12 + 8000bde: af00 add r7, sp, #0 + 8000be0: 6078 str r0, [r7, #4] + 8000be2: ed87 0a00 vstr s0, [r7] + this->setpoint_ = setpoint; + 8000be6: 687b ldr r3, [r7, #4] + 8000be8: 683a ldr r2, [r7, #0] + 8000bea: 611a str r2, [r3, #16] + } + 8000bec: bf00 nop + 8000bee: 370c adds r7, #12 + 8000bf0: 46bd mov sp, r7 + 8000bf2: f85d 7b04 ldr.w r7, [sp], #4 + 8000bf6: 4770 bx lr + +08000bf8 <_ZN3Pid6updateEf>: + + int update(float measure) { + 8000bf8: b480 push {r7} + 8000bfa: b085 sub sp, #20 + 8000bfc: af00 add r7, sp, #0 + 8000bfe: 6078 str r0, [r7, #4] + 8000c00: ed87 0a00 vstr s0, [r7] + + this->error_ = this->setpoint_ - measure; + 8000c04: 687b ldr r3, [r7, #4] + 8000c06: ed93 7a04 vldr s14, [r3, #16] + 8000c0a: edd7 7a00 vldr s15, [r7] + 8000c0e: ee77 7a67 vsub.f32 s15, s14, s15 + 8000c12: 687b ldr r3, [r7, #4] + 8000c14: edc3 7a03 vstr s15, [r3, #12] + + //proportional term + float output = this->error_ * this->kp_; + 8000c18: 687b ldr r3, [r7, #4] + 8000c1a: ed93 7a03 vldr s14, [r3, #12] + 8000c1e: 687b ldr r3, [r7, #4] + 8000c20: edd3 7a00 vldr s15, [r3] + 8000c24: ee67 7a27 vmul.f32 s15, s14, s15 + 8000c28: edc7 7a03 vstr s15, [r7, #12] + + //integral term without windup + error_sum_ += this->error_; + 8000c2c: 687b ldr r3, [r7, #4] + 8000c2e: ed93 7a05 vldr s14, [r3, #20] + 8000c32: 687b ldr r3, [r7, #4] + 8000c34: edd3 7a03 vldr s15, [r3, #12] + 8000c38: ee77 7a27 vadd.f32 s15, s14, s15 + 8000c3c: 687b ldr r3, [r7, #4] + 8000c3e: edc3 7a05 vstr s15, [r3, #20] + output += error_sum_ * this->ki_; + 8000c42: 687b ldr r3, [r7, #4] + 8000c44: ed93 7a05 vldr s14, [r3, #20] + 8000c48: 687b ldr r3, [r7, #4] + 8000c4a: edd3 7a01 vldr s15, [r3, #4] + 8000c4e: ee67 7a27 vmul.f32 s15, s14, s15 + 8000c52: ed97 7a03 vldr s14, [r7, #12] + 8000c56: ee77 7a27 vadd.f32 s15, s14, s15 + 8000c5a: edc7 7a03 vstr s15, [r7, #12] + + //derivative term + output += (this->error_ - this->previous_error_) * kd_; + 8000c5e: 687b ldr r3, [r7, #4] + 8000c60: ed93 7a03 vldr s14, [r3, #12] + 8000c64: 687b ldr r3, [r7, #4] + 8000c66: edd3 7a06 vldr s15, [r3, #24] + 8000c6a: ee37 7a67 vsub.f32 s14, s14, s15 + 8000c6e: 687b ldr r3, [r7, #4] + 8000c70: edd3 7a02 vldr s15, [r3, #8] + 8000c74: ee67 7a27 vmul.f32 s15, s14, s15 + 8000c78: ed97 7a03 vldr s14, [r7, #12] + 8000c7c: ee77 7a27 vadd.f32 s15, s14, s15 + 8000c80: edc7 7a03 vstr s15, [r7, #12] + this->previous_error_ = this->error_; + 8000c84: 687b ldr r3, [r7, #4] + 8000c86: 68da ldr r2, [r3, #12] + 8000c88: 687b ldr r3, [r7, #4] + 8000c8a: 619a str r2, [r3, #24] + + int integer_output = static_cast (output); + 8000c8c: edd7 7a03 vldr s15, [r7, #12] + 8000c90: eefd 7ae7 vcvt.s32.f32 s15, s15 + 8000c94: ee17 3a90 vmov r3, s15 + 8000c98: 60bb str r3, [r7, #8] +// if(integer_output > this->max_) +// integer_output = this->max_; +// else if (integer_output < this->min_) +// integer_output = this->min_; + + return integer_output; + 8000c9a: 68bb ldr r3, [r7, #8] + + } + 8000c9c: 4618 mov r0, r3 + 8000c9e: 3714 adds r7, #20 + 8000ca0: 46bd mov sp, r7 + 8000ca2: f85d 7b04 ldr.w r7, [sp], #4 + 8000ca6: 4770 bx lr + +08000ca8
: + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) { + 8000ca8: b5b0 push {r4, r5, r7, lr} + 8000caa: b086 sub sp, #24 + 8000cac: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 8000cae: f004 fa40 bl 8005132 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 8000cb2: f000 f88f bl 8000dd4 <_Z18SystemClock_Configv> + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8000cb6: f000 fb65 bl 8001384 <_ZL12MX_GPIO_Initv> + MX_TIM2_Init(); + 8000cba: f000 f931 bl 8000f20 <_ZL12MX_TIM2_Initv> + MX_TIM3_Init(); + 8000cbe: f000 f98d bl 8000fdc <_ZL12MX_TIM3_Initv> + MX_TIM4_Init(); + 8000cc2: f000 f9e9 bl 8001098 <_ZL12MX_TIM4_Initv> + MX_TIM5_Init(); + 8000cc6: f000 fa87 bl 80011d8 <_ZL12MX_TIM5_Initv> + MX_USART6_UART_Init(); + 8000cca: f000 fb27 bl 800131c <_ZL19MX_USART6_UART_Initv> + MX_TIM6_Init(); + 8000cce: f000 fae3 bl 8001298 <_ZL12MX_TIM6_Initv> + + /* Initialize interrupts */ + MX_NVIC_Init(); + 8000cd2: f000 f909 bl 8000ee8 <_ZL12MX_NVIC_Initv> + /* USER CODE BEGIN 2 */ + + left_encoder.Setup(); + 8000cd6: 4828 ldr r0, [pc, #160] ; (8000d78 ) + 8000cd8: f7ff fc68 bl 80005ac <_ZN7Encoder5SetupEv> + right_encoder.Setup(); + 8000cdc: 4827 ldr r0, [pc, #156] ; (8000d7c ) + 8000cde: f7ff fc65 bl 80005ac <_ZN7Encoder5SetupEv> + + left_motor.setup(); + 8000ce2: 4827 ldr r0, [pc, #156] ; (8000d80 ) + 8000ce4: f7ff fdd5 bl 8000892 <_ZN15MotorController5setupEv> + right_motor.setup(); + 8000ce8: 4826 ldr r0, [pc, #152] ; (8000d84 ) + 8000cea: f7ff fdd2 bl 8000892 <_ZN15MotorController5setupEv> + left_motor.coast(); + 8000cee: 4824 ldr r0, [pc, #144] ; (8000d80 ) + 8000cf0: f7ff ff06 bl 8000b00 <_ZN15MotorController5coastEv> + right_motor.coast(); + 8000cf4: 4823 ldr r0, [pc, #140] ; (8000d84 ) + 8000cf6: f7ff ff03 bl 8000b00 <_ZN15MotorController5coastEv> + + left_pid.config(180, 200, 0); + 8000cfa: ed9f 1a23 vldr s2, [pc, #140] ; 8000d88 + 8000cfe: eddf 0a23 vldr s1, [pc, #140] ; 8000d8c + 8000d02: ed9f 0a23 vldr s0, [pc, #140] ; 8000d90 + 8000d06: 4823 ldr r0, [pc, #140] ; (8000d94 ) + 8000d08: f7ff ff3e bl 8000b88 <_ZN3Pid6configEfff> + right_pid.config(185, 195, 0); + 8000d0c: ed9f 1a1e vldr s2, [pc, #120] ; 8000d88 + 8000d10: eddf 0a21 vldr s1, [pc, #132] ; 8000d98 + 8000d14: ed9f 0a21 vldr s0, [pc, #132] ; 8000d9c + 8000d18: 4821 ldr r0, [pc, #132] ; (8000da0 ) + 8000d1a: f7ff ff35 bl 8000b88 <_ZN3Pid6configEfff> + cross_pid.config(50, 20, 0); + 8000d1e: ed9f 1a1a vldr s2, [pc, #104] ; 8000d88 + 8000d22: eef3 0a04 vmov.f32 s1, #52 ; 0x41a00000 20.0 + 8000d26: ed9f 0a1f vldr s0, [pc, #124] ; 8000da4 + 8000d2a: 481f ldr r0, [pc, #124] ; (8000da8 ) + 8000d2c: f7ff ff2c bl 8000b88 <_ZN3Pid6configEfff> + + tx_buffer = (uint8_t*) &output_msg; + 8000d30: 4b1e ldr r3, [pc, #120] ; (8000dac ) + 8000d32: 4a1f ldr r2, [pc, #124] ; (8000db0 ) + 8000d34: 601a str r2, [r3, #0] + rx_buffer = (uint8_t*) &input_msg; + 8000d36: 4b1f ldr r3, [pc, #124] ; (8000db4 ) + 8000d38: 4a1f ldr r2, [pc, #124] ; (8000db8 ) + 8000d3a: 601a str r2, [r3, #0] + + vel_output.angular_vel = 1; + 8000d3c: 4b1f ldr r3, [pc, #124] ; (8000dbc ) + 8000d3e: f04f 527e mov.w r2, #1065353216 ; 0x3f800000 + 8000d42: 605a str r2, [r3, #4] + vel_output.linear_vel = 2; + 8000d44: 4b1d ldr r3, [pc, #116] ; (8000dbc ) + 8000d46: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 + 8000d4a: 601a str r2, [r3, #0] + stream_tx = pb_ostream_from_buffer(buffer_tx, sizeof(buffer_tx)); + 8000d4c: 4c1c ldr r4, [pc, #112] ; (8000dc0 ) + 8000d4e: 463b mov r3, r7 + 8000d50: 220a movs r2, #10 + 8000d52: 491c ldr r1, [pc, #112] ; (8000dc4 ) + 8000d54: 4618 mov r0, r3 + 8000d56: f002 ff11 bl 8003b7c + 8000d5a: 4625 mov r5, r4 + 8000d5c: 463c mov r4, r7 + 8000d5e: cc0f ldmia r4!, {r0, r1, r2, r3} + 8000d60: c50f stmia r5!, {r0, r1, r2, r3} + 8000d62: 6823 ldr r3, [r4, #0] + 8000d64: 602b str r3, [r5, #0] + + //Enables UART RX interrupt + HAL_UART_Receive_IT(&huart6, buffer_rx, 10); + 8000d66: 220a movs r2, #10 + 8000d68: 4917 ldr r1, [pc, #92] ; (8000dc8 ) + 8000d6a: 4818 ldr r0, [pc, #96] ; (8000dcc ) + 8000d6c: f006 ff7e bl 8007c6c + HAL_TIM_Base_Start_IT(&htim6); + 8000d70: 4817 ldr r0, [pc, #92] ; (8000dd0 ) + 8000d72: f005 fddd bl 8006930 + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) { + 8000d76: e7fe b.n 8000d76 + 8000d78: 20000204 .word 0x20000204 + 8000d7c: 200001ec .word 0x200001ec + 8000d80: 200002cc .word 0x200002cc + 8000d84: 200002b4 .word 0x200002b4 + 8000d88: 00000000 .word 0x00000000 + 8000d8c: 43480000 .word 0x43480000 + 8000d90: 43340000 .word 0x43340000 + 8000d94: 20000234 .word 0x20000234 + 8000d98: 43430000 .word 0x43430000 + 8000d9c: 43390000 .word 0x43390000 + 8000da0: 20000258 .word 0x20000258 + 8000da4: 42480000 .word 0x42480000 + 8000da8: 2000027c .word 0x2000027c + 8000dac: 200002e4 .word 0x200002e4 + 8000db0: 200002f4 .word 0x200002f4 + 8000db4: 200002e8 .word 0x200002e8 + 8000db8: 200002ec .word 0x200002ec + 8000dbc: 20000308 .word 0x20000308 + 8000dc0: 2000031c .word 0x2000031c + 8000dc4: 20000310 .word 0x20000310 + 8000dc8: 20000338 .word 0x20000338 + 8000dcc: 2000016c .word 0x2000016c + 8000dd0: 2000012c .word 0x2000012c + +08000dd4 <_Z18SystemClock_Configv>: + +/** + * @brief System Clock Configuration + * @retval Nonewheel_circumference_ + */ +void SystemClock_Config(void) { + 8000dd4: b580 push {r7, lr} + 8000dd6: b0b8 sub sp, #224 ; 0xe0 + 8000dd8: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; + 8000dda: f107 03ac add.w r3, r7, #172 ; 0xac + 8000dde: 2234 movs r2, #52 ; 0x34 + 8000de0: 2100 movs r1, #0 + 8000de2: 4618 mov r0, r3 + 8000de4: f007 fdea bl 80089bc + RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; + 8000de8: f107 0398 add.w r3, r7, #152 ; 0x98 + 8000dec: 2200 movs r2, #0 + 8000dee: 601a str r2, [r3, #0] + 8000df0: 605a str r2, [r3, #4] + 8000df2: 609a str r2, [r3, #8] + 8000df4: 60da str r2, [r3, #12] + 8000df6: 611a str r2, [r3, #16] + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 }; + 8000df8: f107 0308 add.w r3, r7, #8 + 8000dfc: 2290 movs r2, #144 ; 0x90 + 8000dfe: 2100 movs r1, #0 + 8000e00: 4618 mov r0, r3 + 8000e02: f007 fddb bl 80089bc + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + 8000e06: 4b36 ldr r3, [pc, #216] ; (8000ee0 <_Z18SystemClock_Configv+0x10c>) + 8000e08: 6c1b ldr r3, [r3, #64] ; 0x40 + 8000e0a: 4a35 ldr r2, [pc, #212] ; (8000ee0 <_Z18SystemClock_Configv+0x10c>) + 8000e0c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8000e10: 6413 str r3, [r2, #64] ; 0x40 + 8000e12: 4b33 ldr r3, [pc, #204] ; (8000ee0 <_Z18SystemClock_Configv+0x10c>) + 8000e14: 6c1b ldr r3, [r3, #64] ; 0x40 + 8000e16: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8000e1a: 607b str r3, [r7, #4] + 8000e1c: 687b ldr r3, [r7, #4] + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); + 8000e1e: 4b31 ldr r3, [pc, #196] ; (8000ee4 <_Z18SystemClock_Configv+0x110>) + 8000e20: 681b ldr r3, [r3, #0] + 8000e22: f423 4340 bic.w r3, r3, #49152 ; 0xc000 + 8000e26: 4a2f ldr r2, [pc, #188] ; (8000ee4 <_Z18SystemClock_Configv+0x110>) + 8000e28: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8000e2c: 6013 str r3, [r2, #0] + 8000e2e: 4b2d ldr r3, [pc, #180] ; (8000ee4 <_Z18SystemClock_Configv+0x110>) + 8000e30: 681b ldr r3, [r3, #0] + 8000e32: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 8000e36: 603b str r3, [r7, #0] + 8000e38: 683b ldr r3, [r7, #0] + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 8000e3a: 2302 movs r3, #2 + 8000e3c: f8c7 30ac str.w r3, [r7, #172] ; 0xac + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 8000e40: 2301 movs r3, #1 + 8000e42: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 8000e46: 2310 movs r3, #16 + 8000e48: f8c7 30bc str.w r3, [r7, #188] ; 0xbc + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 8000e4c: 2300 movs r3, #0 + 8000e4e: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + 8000e52: f107 03ac add.w r3, r7, #172 ; 0xac + 8000e56: 4618 mov r0, r3 + 8000e58: f004 fcd8 bl 800580c + 8000e5c: 4603 mov r3, r0 + 8000e5e: 2b00 cmp r3, #0 + 8000e60: bf14 ite ne + 8000e62: 2301 movne r3, #1 + 8000e64: 2300 moveq r3, #0 + 8000e66: b2db uxtb r3, r3 + 8000e68: 2b00 cmp r3, #0 + 8000e6a: d001 beq.n 8000e70 <_Z18SystemClock_Configv+0x9c> + Error_Handler(); + 8000e6c: f000 fcdc bl 8001828 + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + 8000e70: 230f movs r3, #15 + 8000e72: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + 8000e76: 2300 movs r3, #0 + 8000e78: f8c7 309c str.w r3, [r7, #156] ; 0x9c + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 8000e7c: 2300 movs r3, #0 + 8000e7e: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 8000e82: 2300 movs r3, #0 + 8000e84: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 8000e88: 2300 movs r3, #0 + 8000e8a: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) { + 8000e8e: f107 0398 add.w r3, r7, #152 ; 0x98 + 8000e92: 2100 movs r1, #0 + 8000e94: 4618 mov r0, r3 + 8000e96: f004 ff2b bl 8005cf0 + 8000e9a: 4603 mov r3, r0 + 8000e9c: 2b00 cmp r3, #0 + 8000e9e: bf14 ite ne + 8000ea0: 2301 movne r3, #1 + 8000ea2: 2300 moveq r3, #0 + 8000ea4: b2db uxtb r3, r3 + 8000ea6: 2b00 cmp r3, #0 + 8000ea8: d001 beq.n 8000eae <_Z18SystemClock_Configv+0xda> + Error_Handler(); + 8000eaa: f000 fcbd bl 8001828 + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6; + 8000eae: f44f 6300 mov.w r3, #2048 ; 0x800 + 8000eb2: 60bb str r3, [r7, #8] + PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2; + 8000eb4: 2300 movs r3, #0 + 8000eb6: 663b str r3, [r7, #96] ; 0x60 + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + 8000eb8: f107 0308 add.w r3, r7, #8 + 8000ebc: 4618 mov r0, r3 + 8000ebe: f005 f8e5 bl 800608c + 8000ec2: 4603 mov r3, r0 + 8000ec4: 2b00 cmp r3, #0 + 8000ec6: bf14 ite ne + 8000ec8: 2301 movne r3, #1 + 8000eca: 2300 moveq r3, #0 + 8000ecc: b2db uxtb r3, r3 + 8000ece: 2b00 cmp r3, #0 + 8000ed0: d001 beq.n 8000ed6 <_Z18SystemClock_Configv+0x102> + Error_Handler(); + 8000ed2: f000 fca9 bl 8001828 + } +} + 8000ed6: bf00 nop + 8000ed8: 37e0 adds r7, #224 ; 0xe0 + 8000eda: 46bd mov sp, r7 + 8000edc: bd80 pop {r7, pc} + 8000ede: bf00 nop + 8000ee0: 40023800 .word 0x40023800 + 8000ee4: 40007000 .word 0x40007000 + +08000ee8 <_ZL12MX_NVIC_Initv>: + +/** + * @brief NVIC Configuration. + * @retval None + */ +static void MX_NVIC_Init(void) { + 8000ee8: b580 push {r7, lr} + 8000eea: af00 add r7, sp, #0 + /* TIM3_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(TIM3_IRQn, 2, 1); + 8000eec: 2201 movs r2, #1 + 8000eee: 2102 movs r1, #2 + 8000ef0: 201d movs r0, #29 + 8000ef2: f004 fa56 bl 80053a2 + HAL_NVIC_EnableIRQ(TIM3_IRQn); + 8000ef6: 201d movs r0, #29 + 8000ef8: f004 fa6f bl 80053da + /* TIM6_DAC_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 2, 2); + 8000efc: 2202 movs r2, #2 + 8000efe: 2102 movs r1, #2 + 8000f00: 2036 movs r0, #54 ; 0x36 + 8000f02: f004 fa4e bl 80053a2 + HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); + 8000f06: 2036 movs r0, #54 ; 0x36 + 8000f08: f004 fa67 bl 80053da + /* USART6_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(USART6_IRQn, 1, 0); + 8000f0c: 2200 movs r2, #0 + 8000f0e: 2101 movs r1, #1 + 8000f10: 2047 movs r0, #71 ; 0x47 + 8000f12: f004 fa46 bl 80053a2 + HAL_NVIC_EnableIRQ(USART6_IRQn); + 8000f16: 2047 movs r0, #71 ; 0x47 + 8000f18: f004 fa5f bl 80053da +} + 8000f1c: bf00 nop + 8000f1e: bd80 pop {r7, pc} + +08000f20 <_ZL12MX_TIM2_Initv>: +/** + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) { + 8000f20: b580 push {r7, lr} + 8000f22: b08c sub sp, #48 ; 0x30 + 8000f24: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_Encoder_InitTypeDef sConfig = { 0 }; + 8000f26: f107 030c add.w r3, r7, #12 + 8000f2a: 2224 movs r2, #36 ; 0x24 + 8000f2c: 2100 movs r1, #0 + 8000f2e: 4618 mov r0, r3 + 8000f30: f007 fd44 bl 80089bc + TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + 8000f34: 463b mov r3, r7 + 8000f36: 2200 movs r2, #0 + 8000f38: 601a str r2, [r3, #0] + 8000f3a: 605a str r2, [r3, #4] + 8000f3c: 609a str r2, [r3, #8] + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + 8000f3e: 4b26 ldr r3, [pc, #152] ; (8000fd8 <_ZL12MX_TIM2_Initv+0xb8>) + 8000f40: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 + 8000f44: 601a str r2, [r3, #0] + htim2.Init.Prescaler = 0; + 8000f46: 4b24 ldr r3, [pc, #144] ; (8000fd8 <_ZL12MX_TIM2_Initv+0xb8>) + 8000f48: 2200 movs r2, #0 + 8000f4a: 605a str r2, [r3, #4] + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + 8000f4c: 4b22 ldr r3, [pc, #136] ; (8000fd8 <_ZL12MX_TIM2_Initv+0xb8>) + 8000f4e: 2200 movs r2, #0 + 8000f50: 609a str r2, [r3, #8] + htim2.Init.Period = 4294967295; + 8000f52: 4b21 ldr r3, [pc, #132] ; (8000fd8 <_ZL12MX_TIM2_Initv+0xb8>) + 8000f54: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 8000f58: 60da str r2, [r3, #12] + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8000f5a: 4b1f ldr r3, [pc, #124] ; (8000fd8 <_ZL12MX_TIM2_Initv+0xb8>) + 8000f5c: 2200 movs r2, #0 + 8000f5e: 611a str r2, [r3, #16] + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 8000f60: 4b1d ldr r3, [pc, #116] ; (8000fd8 <_ZL12MX_TIM2_Initv+0xb8>) + 8000f62: 2200 movs r2, #0 + 8000f64: 619a str r2, [r3, #24] + sConfig.EncoderMode = TIM_ENCODERMODE_TI12; + 8000f66: 2303 movs r3, #3 + 8000f68: 60fb str r3, [r7, #12] + sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; + 8000f6a: 2300 movs r3, #0 + 8000f6c: 613b str r3, [r7, #16] + sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; + 8000f6e: 2301 movs r3, #1 + 8000f70: 617b str r3, [r7, #20] + sConfig.IC1Prescaler = TIM_ICPSC_DIV1; + 8000f72: 2300 movs r3, #0 + 8000f74: 61bb str r3, [r7, #24] + sConfig.IC1Filter = 0; + 8000f76: 2300 movs r3, #0 + 8000f78: 61fb str r3, [r7, #28] + sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; + 8000f7a: 2300 movs r3, #0 + 8000f7c: 623b str r3, [r7, #32] + sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; + 8000f7e: 2301 movs r3, #1 + 8000f80: 627b str r3, [r7, #36] ; 0x24 + sConfig.IC2Prescaler = TIM_ICPSC_DIV1; + 8000f82: 2300 movs r3, #0 + 8000f84: 62bb str r3, [r7, #40] ; 0x28 + sConfig.IC2Filter = 0; + 8000f86: 2300 movs r3, #0 + 8000f88: 62fb str r3, [r7, #44] ; 0x2c + if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK) { + 8000f8a: f107 030c add.w r3, r7, #12 + 8000f8e: 4619 mov r1, r3 + 8000f90: 4811 ldr r0, [pc, #68] ; (8000fd8 <_ZL12MX_TIM2_Initv+0xb8>) + 8000f92: f005 fd71 bl 8006a78 + 8000f96: 4603 mov r3, r0 + 8000f98: 2b00 cmp r3, #0 + 8000f9a: bf14 ite ne + 8000f9c: 2301 movne r3, #1 + 8000f9e: 2300 moveq r3, #0 + 8000fa0: b2db uxtb r3, r3 + 8000fa2: 2b00 cmp r3, #0 + 8000fa4: d001 beq.n 8000faa <_ZL12MX_TIM2_Initv+0x8a> + Error_Handler(); + 8000fa6: f000 fc3f bl 8001828 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8000faa: 2300 movs r3, #0 + 8000fac: 603b str r3, [r7, #0] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8000fae: 2300 movs r3, #0 + 8000fb0: 60bb str r3, [r7, #8] + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) { + 8000fb2: 463b mov r3, r7 + 8000fb4: 4619 mov r1, r3 + 8000fb6: 4808 ldr r0, [pc, #32] ; (8000fd8 <_ZL12MX_TIM2_Initv+0xb8>) + 8000fb8: f006 fcfe bl 80079b8 + 8000fbc: 4603 mov r3, r0 + 8000fbe: 2b00 cmp r3, #0 + 8000fc0: bf14 ite ne + 8000fc2: 2301 movne r3, #1 + 8000fc4: 2300 moveq r3, #0 + 8000fc6: b2db uxtb r3, r3 + 8000fc8: 2b00 cmp r3, #0 + 8000fca: d001 beq.n 8000fd0 <_ZL12MX_TIM2_Initv+0xb0> + Error_Handler(); + 8000fcc: f000 fc2c bl 8001828 + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + +} + 8000fd0: bf00 nop + 8000fd2: 3730 adds r7, #48 ; 0x30 + 8000fd4: 46bd mov sp, r7 + 8000fd6: bd80 pop {r7, pc} + 8000fd8: 2000002c .word 0x2000002c + +08000fdc <_ZL12MX_TIM3_Initv>: +/** + * @brief TIM3 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM3_Init(void) { + 8000fdc: b580 push {r7, lr} + 8000fde: b088 sub sp, #32 + 8000fe0: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = { 0 }; + 8000fe2: f107 0310 add.w r3, r7, #16 + 8000fe6: 2200 movs r2, #0 + 8000fe8: 601a str r2, [r3, #0] + 8000fea: 605a str r2, [r3, #4] + 8000fec: 609a str r2, [r3, #8] + 8000fee: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + 8000ff0: 1d3b adds r3, r7, #4 + 8000ff2: 2200 movs r2, #0 + 8000ff4: 601a str r2, [r3, #0] + 8000ff6: 605a str r2, [r3, #4] + 8000ff8: 609a str r2, [r3, #8] + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + htim3.Instance = TIM3; + 8000ffa: 4b25 ldr r3, [pc, #148] ; (8001090 <_ZL12MX_TIM3_Initv+0xb4>) + 8000ffc: 4a25 ldr r2, [pc, #148] ; (8001094 <_ZL12MX_TIM3_Initv+0xb8>) + 8000ffe: 601a str r2, [r3, #0] + htim3.Init.Prescaler = 999; + 8001000: 4b23 ldr r3, [pc, #140] ; (8001090 <_ZL12MX_TIM3_Initv+0xb4>) + 8001002: f240 32e7 movw r2, #999 ; 0x3e7 + 8001006: 605a str r2, [r3, #4] + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + 8001008: 4b21 ldr r3, [pc, #132] ; (8001090 <_ZL12MX_TIM3_Initv+0xb4>) + 800100a: 2200 movs r2, #0 + 800100c: 609a str r2, [r3, #8] + htim3.Init.Period = 159; + 800100e: 4b20 ldr r3, [pc, #128] ; (8001090 <_ZL12MX_TIM3_Initv+0xb4>) + 8001010: 229f movs r2, #159 ; 0x9f + 8001012: 60da str r2, [r3, #12] + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8001014: 4b1e ldr r3, [pc, #120] ; (8001090 <_ZL12MX_TIM3_Initv+0xb4>) + 8001016: 2200 movs r2, #0 + 8001018: 611a str r2, [r3, #16] + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 800101a: 4b1d ldr r3, [pc, #116] ; (8001090 <_ZL12MX_TIM3_Initv+0xb4>) + 800101c: 2200 movs r2, #0 + 800101e: 619a str r2, [r3, #24] + if (HAL_TIM_Base_Init(&htim3) != HAL_OK) { + 8001020: 481b ldr r0, [pc, #108] ; (8001090 <_ZL12MX_TIM3_Initv+0xb4>) + 8001022: f005 fc59 bl 80068d8 + 8001026: 4603 mov r3, r0 + 8001028: 2b00 cmp r3, #0 + 800102a: bf14 ite ne + 800102c: 2301 movne r3, #1 + 800102e: 2300 moveq r3, #0 + 8001030: b2db uxtb r3, r3 + 8001032: 2b00 cmp r3, #0 + 8001034: d001 beq.n 800103a <_ZL12MX_TIM3_Initv+0x5e> + Error_Handler(); + 8001036: f000 fbf7 bl 8001828 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 800103a: f44f 5380 mov.w r3, #4096 ; 0x1000 + 800103e: 613b str r3, [r7, #16] + if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) { + 8001040: f107 0310 add.w r3, r7, #16 + 8001044: 4619 mov r1, r3 + 8001046: 4812 ldr r0, [pc, #72] ; (8001090 <_ZL12MX_TIM3_Initv+0xb4>) + 8001048: f006 f816 bl 8007078 + 800104c: 4603 mov r3, r0 + 800104e: 2b00 cmp r3, #0 + 8001050: bf14 ite ne + 8001052: 2301 movne r3, #1 + 8001054: 2300 moveq r3, #0 + 8001056: b2db uxtb r3, r3 + 8001058: 2b00 cmp r3, #0 + 800105a: d001 beq.n 8001060 <_ZL12MX_TIM3_Initv+0x84> + Error_Handler(); + 800105c: f000 fbe4 bl 8001828 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8001060: 2300 movs r3, #0 + 8001062: 607b str r3, [r7, #4] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8001064: 2300 movs r3, #0 + 8001066: 60fb str r3, [r7, #12] + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) { + 8001068: 1d3b adds r3, r7, #4 + 800106a: 4619 mov r1, r3 + 800106c: 4808 ldr r0, [pc, #32] ; (8001090 <_ZL12MX_TIM3_Initv+0xb4>) + 800106e: f006 fca3 bl 80079b8 + 8001072: 4603 mov r3, r0 + 8001074: 2b00 cmp r3, #0 + 8001076: bf14 ite ne + 8001078: 2301 movne r3, #1 + 800107a: 2300 moveq r3, #0 + 800107c: b2db uxtb r3, r3 + 800107e: 2b00 cmp r3, #0 + 8001080: d001 beq.n 8001086 <_ZL12MX_TIM3_Initv+0xaa> + Error_Handler(); + 8001082: f000 fbd1 bl 8001828 + } + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + +} + 8001086: bf00 nop + 8001088: 3720 adds r7, #32 + 800108a: 46bd mov sp, r7 + 800108c: bd80 pop {r7, pc} + 800108e: bf00 nop + 8001090: 2000006c .word 0x2000006c + 8001094: 40000400 .word 0x40000400 + +08001098 <_ZL12MX_TIM4_Initv>: +/** + * @brief TIM4 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM4_Init(void) { + 8001098: b580 push {r7, lr} + 800109a: b08e sub sp, #56 ; 0x38 + 800109c: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM4_Init 0 */ + + /* USER CODE END TIM4_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = { 0 }; + 800109e: f107 0328 add.w r3, r7, #40 ; 0x28 + 80010a2: 2200 movs r2, #0 + 80010a4: 601a str r2, [r3, #0] + 80010a6: 605a str r2, [r3, #4] + 80010a8: 609a str r2, [r3, #8] + 80010aa: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + 80010ac: f107 031c add.w r3, r7, #28 + 80010b0: 2200 movs r2, #0 + 80010b2: 601a str r2, [r3, #0] + 80010b4: 605a str r2, [r3, #4] + 80010b6: 609a str r2, [r3, #8] + TIM_OC_InitTypeDef sConfigOC = { 0 }; + 80010b8: 463b mov r3, r7 + 80010ba: 2200 movs r2, #0 + 80010bc: 601a str r2, [r3, #0] + 80010be: 605a str r2, [r3, #4] + 80010c0: 609a str r2, [r3, #8] + 80010c2: 60da str r2, [r3, #12] + 80010c4: 611a str r2, [r3, #16] + 80010c6: 615a str r2, [r3, #20] + 80010c8: 619a str r2, [r3, #24] + + /* USER CODE BEGIN TIM4_Init 1 */ + + /* USER CODE END TIM4_Init 1 */ + htim4.Instance = TIM4; + 80010ca: 4b41 ldr r3, [pc, #260] ; (80011d0 <_ZL12MX_TIM4_Initv+0x138>) + 80010cc: 4a41 ldr r2, [pc, #260] ; (80011d4 <_ZL12MX_TIM4_Initv+0x13c>) + 80010ce: 601a str r2, [r3, #0] + htim4.Init.Prescaler = 0; + 80010d0: 4b3f ldr r3, [pc, #252] ; (80011d0 <_ZL12MX_TIM4_Initv+0x138>) + 80010d2: 2200 movs r2, #0 + 80010d4: 605a str r2, [r3, #4] + htim4.Init.CounterMode = TIM_COUNTERMODE_UP; + 80010d6: 4b3e ldr r3, [pc, #248] ; (80011d0 <_ZL12MX_TIM4_Initv+0x138>) + 80010d8: 2200 movs r2, #0 + 80010da: 609a str r2, [r3, #8] + htim4.Init.Period = 799; + 80010dc: 4b3c ldr r3, [pc, #240] ; (80011d0 <_ZL12MX_TIM4_Initv+0x138>) + 80010de: f240 321f movw r2, #799 ; 0x31f + 80010e2: 60da str r2, [r3, #12] + htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 80010e4: 4b3a ldr r3, [pc, #232] ; (80011d0 <_ZL12MX_TIM4_Initv+0x138>) + 80010e6: 2200 movs r2, #0 + 80010e8: 611a str r2, [r3, #16] + htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 80010ea: 4b39 ldr r3, [pc, #228] ; (80011d0 <_ZL12MX_TIM4_Initv+0x138>) + 80010ec: 2200 movs r2, #0 + 80010ee: 619a str r2, [r3, #24] + if (HAL_TIM_Base_Init(&htim4) != HAL_OK) { + 80010f0: 4837 ldr r0, [pc, #220] ; (80011d0 <_ZL12MX_TIM4_Initv+0x138>) + 80010f2: f005 fbf1 bl 80068d8 + 80010f6: 4603 mov r3, r0 + 80010f8: 2b00 cmp r3, #0 + 80010fa: bf14 ite ne + 80010fc: 2301 movne r3, #1 + 80010fe: 2300 moveq r3, #0 + 8001100: b2db uxtb r3, r3 + 8001102: 2b00 cmp r3, #0 + 8001104: d001 beq.n 800110a <_ZL12MX_TIM4_Initv+0x72> + Error_Handler(); + 8001106: f000 fb8f bl 8001828 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 800110a: f44f 5380 mov.w r3, #4096 ; 0x1000 + 800110e: 62bb str r3, [r7, #40] ; 0x28 + if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) { + 8001110: f107 0328 add.w r3, r7, #40 ; 0x28 + 8001114: 4619 mov r1, r3 + 8001116: 482e ldr r0, [pc, #184] ; (80011d0 <_ZL12MX_TIM4_Initv+0x138>) + 8001118: f005 ffae bl 8007078 + 800111c: 4603 mov r3, r0 + 800111e: 2b00 cmp r3, #0 + 8001120: bf14 ite ne + 8001122: 2301 movne r3, #1 + 8001124: 2300 moveq r3, #0 + 8001126: b2db uxtb r3, r3 + 8001128: 2b00 cmp r3, #0 + 800112a: d001 beq.n 8001130 <_ZL12MX_TIM4_Initv+0x98> + Error_Handler(); + 800112c: f000 fb7c bl 8001828 + } + if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) { + 8001130: 4827 ldr r0, [pc, #156] ; (80011d0 <_ZL12MX_TIM4_Initv+0x138>) + 8001132: f005 fc27 bl 8006984 + 8001136: 4603 mov r3, r0 + 8001138: 2b00 cmp r3, #0 + 800113a: bf14 ite ne + 800113c: 2301 movne r3, #1 + 800113e: 2300 moveq r3, #0 + 8001140: b2db uxtb r3, r3 + 8001142: 2b00 cmp r3, #0 + 8001144: d001 beq.n 800114a <_ZL12MX_TIM4_Initv+0xb2> + Error_Handler(); + 8001146: f000 fb6f bl 8001828 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 800114a: 2300 movs r3, #0 + 800114c: 61fb str r3, [r7, #28] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 800114e: 2300 movs r3, #0 + 8001150: 627b str r3, [r7, #36] ; 0x24 + if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) { + 8001152: f107 031c add.w r3, r7, #28 + 8001156: 4619 mov r1, r3 + 8001158: 481d ldr r0, [pc, #116] ; (80011d0 <_ZL12MX_TIM4_Initv+0x138>) + 800115a: f006 fc2d bl 80079b8 + 800115e: 4603 mov r3, r0 + 8001160: 2b00 cmp r3, #0 + 8001162: bf14 ite ne + 8001164: 2301 movne r3, #1 + 8001166: 2300 moveq r3, #0 + 8001168: b2db uxtb r3, r3 + 800116a: 2b00 cmp r3, #0 + 800116c: d001 beq.n 8001172 <_ZL12MX_TIM4_Initv+0xda> + Error_Handler(); + 800116e: f000 fb5b bl 8001828 + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + 8001172: 2360 movs r3, #96 ; 0x60 + 8001174: 603b str r3, [r7, #0] + sConfigOC.Pulse = 0; + 8001176: 2300 movs r3, #0 + 8001178: 607b str r3, [r7, #4] + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 800117a: 2300 movs r3, #0 + 800117c: 60bb str r3, [r7, #8] + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 800117e: 2300 movs r3, #0 + 8001180: 613b str r3, [r7, #16] + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) { + 8001182: 463b mov r3, r7 + 8001184: 2208 movs r2, #8 + 8001186: 4619 mov r1, r3 + 8001188: 4811 ldr r0, [pc, #68] ; (80011d0 <_ZL12MX_TIM4_Initv+0x138>) + 800118a: f005 fe5d bl 8006e48 + 800118e: 4603 mov r3, r0 + 8001190: 2b00 cmp r3, #0 + 8001192: bf14 ite ne + 8001194: 2301 movne r3, #1 + 8001196: 2300 moveq r3, #0 + 8001198: b2db uxtb r3, r3 + 800119a: 2b00 cmp r3, #0 + 800119c: d001 beq.n 80011a2 <_ZL12MX_TIM4_Initv+0x10a> + Error_Handler(); + 800119e: f000 fb43 bl 8001828 + } + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) { + 80011a2: 463b mov r3, r7 + 80011a4: 220c movs r2, #12 + 80011a6: 4619 mov r1, r3 + 80011a8: 4809 ldr r0, [pc, #36] ; (80011d0 <_ZL12MX_TIM4_Initv+0x138>) + 80011aa: f005 fe4d bl 8006e48 + 80011ae: 4603 mov r3, r0 + 80011b0: 2b00 cmp r3, #0 + 80011b2: bf14 ite ne + 80011b4: 2301 movne r3, #1 + 80011b6: 2300 moveq r3, #0 + 80011b8: b2db uxtb r3, r3 + 80011ba: 2b00 cmp r3, #0 + 80011bc: d001 beq.n 80011c2 <_ZL12MX_TIM4_Initv+0x12a> + Error_Handler(); + 80011be: f000 fb33 bl 8001828 + } + /* USER CODE BEGIN TIM4_Init 2 */ + + /* USER CODE END TIM4_Init 2 */ + HAL_TIM_MspPostInit(&htim4); + 80011c2: 4803 ldr r0, [pc, #12] ; (80011d0 <_ZL12MX_TIM4_Initv+0x138>) + 80011c4: f003 fe86 bl 8004ed4 + +} + 80011c8: bf00 nop + 80011ca: 3738 adds r7, #56 ; 0x38 + 80011cc: 46bd mov sp, r7 + 80011ce: bd80 pop {r7, pc} + 80011d0: 200000ac .word 0x200000ac + 80011d4: 40000800 .word 0x40000800 + +080011d8 <_ZL12MX_TIM5_Initv>: +/** + * @brief TIM5 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM5_Init(void) { + 80011d8: b580 push {r7, lr} + 80011da: b08c sub sp, #48 ; 0x30 + 80011dc: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM5_Init 0 */ + + /* USER CODE END TIM5_Init 0 */ + + TIM_Encoder_InitTypeDef sConfig = { 0 }; + 80011de: f107 030c add.w r3, r7, #12 + 80011e2: 2224 movs r2, #36 ; 0x24 + 80011e4: 2100 movs r1, #0 + 80011e6: 4618 mov r0, r3 + 80011e8: f007 fbe8 bl 80089bc + TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + 80011ec: 463b mov r3, r7 + 80011ee: 2200 movs r2, #0 + 80011f0: 601a str r2, [r3, #0] + 80011f2: 605a str r2, [r3, #4] + 80011f4: 609a str r2, [r3, #8] + + /* USER CODE BEGIN TIM5_Init 1 */ + + /* USER CODE END TIM5_Init 1 */ + htim5.Instance = TIM5; + 80011f6: 4b26 ldr r3, [pc, #152] ; (8001290 <_ZL12MX_TIM5_Initv+0xb8>) + 80011f8: 4a26 ldr r2, [pc, #152] ; (8001294 <_ZL12MX_TIM5_Initv+0xbc>) + 80011fa: 601a str r2, [r3, #0] + htim5.Init.Prescaler = 0; + 80011fc: 4b24 ldr r3, [pc, #144] ; (8001290 <_ZL12MX_TIM5_Initv+0xb8>) + 80011fe: 2200 movs r2, #0 + 8001200: 605a str r2, [r3, #4] + htim5.Init.CounterMode = TIM_COUNTERMODE_UP; + 8001202: 4b23 ldr r3, [pc, #140] ; (8001290 <_ZL12MX_TIM5_Initv+0xb8>) + 8001204: 2200 movs r2, #0 + 8001206: 609a str r2, [r3, #8] + htim5.Init.Period = 4294967295; + 8001208: 4b21 ldr r3, [pc, #132] ; (8001290 <_ZL12MX_TIM5_Initv+0xb8>) + 800120a: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 800120e: 60da str r2, [r3, #12] + htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8001210: 4b1f ldr r3, [pc, #124] ; (8001290 <_ZL12MX_TIM5_Initv+0xb8>) + 8001212: 2200 movs r2, #0 + 8001214: 611a str r2, [r3, #16] + htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 8001216: 4b1e ldr r3, [pc, #120] ; (8001290 <_ZL12MX_TIM5_Initv+0xb8>) + 8001218: 2200 movs r2, #0 + 800121a: 619a str r2, [r3, #24] + sConfig.EncoderMode = TIM_ENCODERMODE_TI12; + 800121c: 2303 movs r3, #3 + 800121e: 60fb str r3, [r7, #12] + sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; + 8001220: 2300 movs r3, #0 + 8001222: 613b str r3, [r7, #16] + sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; + 8001224: 2301 movs r3, #1 + 8001226: 617b str r3, [r7, #20] + sConfig.IC1Prescaler = TIM_ICPSC_DIV1; + 8001228: 2300 movs r3, #0 + 800122a: 61bb str r3, [r7, #24] + sConfig.IC1Filter = 0; + 800122c: 2300 movs r3, #0 + 800122e: 61fb str r3, [r7, #28] + sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; + 8001230: 2300 movs r3, #0 + 8001232: 623b str r3, [r7, #32] + sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; + 8001234: 2301 movs r3, #1 + 8001236: 627b str r3, [r7, #36] ; 0x24 + sConfig.IC2Prescaler = TIM_ICPSC_DIV1; + 8001238: 2300 movs r3, #0 + 800123a: 62bb str r3, [r7, #40] ; 0x28 + sConfig.IC2Filter = 0; + 800123c: 2300 movs r3, #0 + 800123e: 62fb str r3, [r7, #44] ; 0x2c + if (HAL_TIM_Encoder_Init(&htim5, &sConfig) != HAL_OK) { + 8001240: f107 030c add.w r3, r7, #12 + 8001244: 4619 mov r1, r3 + 8001246: 4812 ldr r0, [pc, #72] ; (8001290 <_ZL12MX_TIM5_Initv+0xb8>) + 8001248: f005 fc16 bl 8006a78 + 800124c: 4603 mov r3, r0 + 800124e: 2b00 cmp r3, #0 + 8001250: bf14 ite ne + 8001252: 2301 movne r3, #1 + 8001254: 2300 moveq r3, #0 + 8001256: b2db uxtb r3, r3 + 8001258: 2b00 cmp r3, #0 + 800125a: d001 beq.n 8001260 <_ZL12MX_TIM5_Initv+0x88> + Error_Handler(); + 800125c: f000 fae4 bl 8001828 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8001260: 2300 movs r3, #0 + 8001262: 603b str r3, [r7, #0] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8001264: 2300 movs r3, #0 + 8001266: 60bb str r3, [r7, #8] + if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) { + 8001268: 463b mov r3, r7 + 800126a: 4619 mov r1, r3 + 800126c: 4808 ldr r0, [pc, #32] ; (8001290 <_ZL12MX_TIM5_Initv+0xb8>) + 800126e: f006 fba3 bl 80079b8 + 8001272: 4603 mov r3, r0 + 8001274: 2b00 cmp r3, #0 + 8001276: bf14 ite ne + 8001278: 2301 movne r3, #1 + 800127a: 2300 moveq r3, #0 + 800127c: b2db uxtb r3, r3 + 800127e: 2b00 cmp r3, #0 + 8001280: d001 beq.n 8001286 <_ZL12MX_TIM5_Initv+0xae> + Error_Handler(); + 8001282: f000 fad1 bl 8001828 + } + /* USER CODE BEGIN TIM5_Init 2 */ + + /* USER CODE END TIM5_Init 2 */ + +} + 8001286: bf00 nop + 8001288: 3730 adds r7, #48 ; 0x30 + 800128a: 46bd mov sp, r7 + 800128c: bd80 pop {r7, pc} + 800128e: bf00 nop + 8001290: 200000ec .word 0x200000ec + 8001294: 40000c00 .word 0x40000c00 + +08001298 <_ZL12MX_TIM6_Initv>: +/** + * @brief TIM6 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM6_Init(void) { + 8001298: b580 push {r7, lr} + 800129a: b084 sub sp, #16 + 800129c: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM6_Init 0 */ + + /* USER CODE END TIM6_Init 0 */ + + TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + 800129e: 1d3b adds r3, r7, #4 + 80012a0: 2200 movs r2, #0 + 80012a2: 601a str r2, [r3, #0] + 80012a4: 605a str r2, [r3, #4] + 80012a6: 609a str r2, [r3, #8] + + /* USER CODE BEGIN TIM6_Init 1 */ + + /* USER CODE END TIM6_Init 1 */ + htim6.Instance = TIM6; + 80012a8: 4b1a ldr r3, [pc, #104] ; (8001314 <_ZL12MX_TIM6_Initv+0x7c>) + 80012aa: 4a1b ldr r2, [pc, #108] ; (8001318 <_ZL12MX_TIM6_Initv+0x80>) + 80012ac: 601a str r2, [r3, #0] + htim6.Init.Prescaler = 9999; + 80012ae: 4b19 ldr r3, [pc, #100] ; (8001314 <_ZL12MX_TIM6_Initv+0x7c>) + 80012b0: f242 720f movw r2, #9999 ; 0x270f + 80012b4: 605a str r2, [r3, #4] + htim6.Init.CounterMode = TIM_COUNTERMODE_UP; + 80012b6: 4b17 ldr r3, [pc, #92] ; (8001314 <_ZL12MX_TIM6_Initv+0x7c>) + 80012b8: 2200 movs r2, #0 + 80012ba: 609a str r2, [r3, #8] + htim6.Init.Period = 799; + 80012bc: 4b15 ldr r3, [pc, #84] ; (8001314 <_ZL12MX_TIM6_Initv+0x7c>) + 80012be: f240 321f movw r2, #799 ; 0x31f + 80012c2: 60da str r2, [r3, #12] + htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 80012c4: 4b13 ldr r3, [pc, #76] ; (8001314 <_ZL12MX_TIM6_Initv+0x7c>) + 80012c6: 2200 movs r2, #0 + 80012c8: 619a str r2, [r3, #24] + if (HAL_TIM_Base_Init(&htim6) != HAL_OK) { + 80012ca: 4812 ldr r0, [pc, #72] ; (8001314 <_ZL12MX_TIM6_Initv+0x7c>) + 80012cc: f005 fb04 bl 80068d8 + 80012d0: 4603 mov r3, r0 + 80012d2: 2b00 cmp r3, #0 + 80012d4: bf14 ite ne + 80012d6: 2301 movne r3, #1 + 80012d8: 2300 moveq r3, #0 + 80012da: b2db uxtb r3, r3 + 80012dc: 2b00 cmp r3, #0 + 80012de: d001 beq.n 80012e4 <_ZL12MX_TIM6_Initv+0x4c> + Error_Handler(); + 80012e0: f000 faa2 bl 8001828 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 80012e4: 2300 movs r3, #0 + 80012e6: 607b str r3, [r7, #4] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 80012e8: 2300 movs r3, #0 + 80012ea: 60fb str r3, [r7, #12] + if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) { + 80012ec: 1d3b adds r3, r7, #4 + 80012ee: 4619 mov r1, r3 + 80012f0: 4808 ldr r0, [pc, #32] ; (8001314 <_ZL12MX_TIM6_Initv+0x7c>) + 80012f2: f006 fb61 bl 80079b8 + 80012f6: 4603 mov r3, r0 + 80012f8: 2b00 cmp r3, #0 + 80012fa: bf14 ite ne + 80012fc: 2301 movne r3, #1 + 80012fe: 2300 moveq r3, #0 + 8001300: b2db uxtb r3, r3 + 8001302: 2b00 cmp r3, #0 + 8001304: d001 beq.n 800130a <_ZL12MX_TIM6_Initv+0x72> + Error_Handler(); + 8001306: f000 fa8f bl 8001828 + } + /* USER CODE BEGIN TIM6_Init 2 */ + + /* USER CODE END TIM6_Init 2 */ + +} + 800130a: bf00 nop + 800130c: 3710 adds r7, #16 + 800130e: 46bd mov sp, r7 + 8001310: bd80 pop {r7, pc} + 8001312: bf00 nop + 8001314: 2000012c .word 0x2000012c + 8001318: 40001000 .word 0x40001000 + +0800131c <_ZL19MX_USART6_UART_Initv>: +/** + * @brief USART6 Initialization Function + * @param None + * @retval None + */ +static void MX_USART6_UART_Init(void) { + 800131c: b580 push {r7, lr} + 800131e: af00 add r7, sp, #0 + /* USER CODE END USART6_Init 0 */ + + /* USER CODE BEGIN USART6_Init 1 */ + + /* USER CODE END USART6_Init 1 */ + huart6.Instance = USART6; + 8001320: 4b16 ldr r3, [pc, #88] ; (800137c <_ZL19MX_USART6_UART_Initv+0x60>) + 8001322: 4a17 ldr r2, [pc, #92] ; (8001380 <_ZL19MX_USART6_UART_Initv+0x64>) + 8001324: 601a str r2, [r3, #0] + huart6.Init.BaudRate = 115200; + 8001326: 4b15 ldr r3, [pc, #84] ; (800137c <_ZL19MX_USART6_UART_Initv+0x60>) + 8001328: f44f 32e1 mov.w r2, #115200 ; 0x1c200 + 800132c: 605a str r2, [r3, #4] + huart6.Init.WordLength = UART_WORDLENGTH_8B; + 800132e: 4b13 ldr r3, [pc, #76] ; (800137c <_ZL19MX_USART6_UART_Initv+0x60>) + 8001330: 2200 movs r2, #0 + 8001332: 609a str r2, [r3, #8] + huart6.Init.StopBits = UART_STOPBITS_1; + 8001334: 4b11 ldr r3, [pc, #68] ; (800137c <_ZL19MX_USART6_UART_Initv+0x60>) + 8001336: 2200 movs r2, #0 + 8001338: 60da str r2, [r3, #12] + huart6.Init.Parity = UART_PARITY_NONE; + 800133a: 4b10 ldr r3, [pc, #64] ; (800137c <_ZL19MX_USART6_UART_Initv+0x60>) + 800133c: 2200 movs r2, #0 + 800133e: 611a str r2, [r3, #16] + huart6.Init.Mode = UART_MODE_TX_RX; + 8001340: 4b0e ldr r3, [pc, #56] ; (800137c <_ZL19MX_USART6_UART_Initv+0x60>) + 8001342: 220c movs r2, #12 + 8001344: 615a str r2, [r3, #20] + huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 8001346: 4b0d ldr r3, [pc, #52] ; (800137c <_ZL19MX_USART6_UART_Initv+0x60>) + 8001348: 2200 movs r2, #0 + 800134a: 619a str r2, [r3, #24] + huart6.Init.OverSampling = UART_OVERSAMPLING_16; + 800134c: 4b0b ldr r3, [pc, #44] ; (800137c <_ZL19MX_USART6_UART_Initv+0x60>) + 800134e: 2200 movs r2, #0 + 8001350: 61da str r2, [r3, #28] + huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 8001352: 4b0a ldr r3, [pc, #40] ; (800137c <_ZL19MX_USART6_UART_Initv+0x60>) + 8001354: 2200 movs r2, #0 + 8001356: 621a str r2, [r3, #32] + huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 8001358: 4b08 ldr r3, [pc, #32] ; (800137c <_ZL19MX_USART6_UART_Initv+0x60>) + 800135a: 2200 movs r2, #0 + 800135c: 625a str r2, [r3, #36] ; 0x24 + if (HAL_UART_Init(&huart6) != HAL_OK) { + 800135e: 4807 ldr r0, [pc, #28] ; (800137c <_ZL19MX_USART6_UART_Initv+0x60>) + 8001360: f006 fba4 bl 8007aac + 8001364: 4603 mov r3, r0 + 8001366: 2b00 cmp r3, #0 + 8001368: bf14 ite ne + 800136a: 2301 movne r3, #1 + 800136c: 2300 moveq r3, #0 + 800136e: b2db uxtb r3, r3 + 8001370: 2b00 cmp r3, #0 + 8001372: d001 beq.n 8001378 <_ZL19MX_USART6_UART_Initv+0x5c> + Error_Handler(); + 8001374: f000 fa58 bl 8001828 + } + /* USER CODE BEGIN USART6_Init 2 */ + + /* USER CODE END USART6_Init 2 */ + +} + 8001378: bf00 nop + 800137a: bd80 pop {r7, pc} + 800137c: 2000016c .word 0x2000016c + 8001380: 40011400 .word 0x40011400 + +08001384 <_ZL12MX_GPIO_Initv>: +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) { + 8001384: b580 push {r7, lr} + 8001386: b08c sub sp, #48 ; 0x30 + 8001388: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = { 0 }; + 800138a: f107 031c add.w r3, r7, #28 + 800138e: 2200 movs r2, #0 + 8001390: 601a str r2, [r3, #0] + 8001392: 605a str r2, [r3, #4] + 8001394: 609a str r2, [r3, #8] + 8001396: 60da str r2, [r3, #12] + 8001398: 611a str r2, [r3, #16] + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 800139a: 4b5e ldr r3, [pc, #376] ; (8001514 <_ZL12MX_GPIO_Initv+0x190>) + 800139c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800139e: 4a5d ldr r2, [pc, #372] ; (8001514 <_ZL12MX_GPIO_Initv+0x190>) + 80013a0: f043 0304 orr.w r3, r3, #4 + 80013a4: 6313 str r3, [r2, #48] ; 0x30 + 80013a6: 4b5b ldr r3, [pc, #364] ; (8001514 <_ZL12MX_GPIO_Initv+0x190>) + 80013a8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80013aa: f003 0304 and.w r3, r3, #4 + 80013ae: 61bb str r3, [r7, #24] + 80013b0: 69bb ldr r3, [r7, #24] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80013b2: 4b58 ldr r3, [pc, #352] ; (8001514 <_ZL12MX_GPIO_Initv+0x190>) + 80013b4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80013b6: 4a57 ldr r2, [pc, #348] ; (8001514 <_ZL12MX_GPIO_Initv+0x190>) + 80013b8: f043 0301 orr.w r3, r3, #1 + 80013bc: 6313 str r3, [r2, #48] ; 0x30 + 80013be: 4b55 ldr r3, [pc, #340] ; (8001514 <_ZL12MX_GPIO_Initv+0x190>) + 80013c0: 6b1b ldr r3, [r3, #48] ; 0x30 + 80013c2: f003 0301 and.w r3, r3, #1 + 80013c6: 617b str r3, [r7, #20] + 80013c8: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOF_CLK_ENABLE(); + 80013ca: 4b52 ldr r3, [pc, #328] ; (8001514 <_ZL12MX_GPIO_Initv+0x190>) + 80013cc: 6b1b ldr r3, [r3, #48] ; 0x30 + 80013ce: 4a51 ldr r2, [pc, #324] ; (8001514 <_ZL12MX_GPIO_Initv+0x190>) + 80013d0: f043 0320 orr.w r3, r3, #32 + 80013d4: 6313 str r3, [r2, #48] ; 0x30 + 80013d6: 4b4f ldr r3, [pc, #316] ; (8001514 <_ZL12MX_GPIO_Initv+0x190>) + 80013d8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80013da: f003 0320 and.w r3, r3, #32 + 80013de: 613b str r3, [r7, #16] + 80013e0: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOE_CLK_ENABLE(); + 80013e2: 4b4c ldr r3, [pc, #304] ; (8001514 <_ZL12MX_GPIO_Initv+0x190>) + 80013e4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80013e6: 4a4b ldr r2, [pc, #300] ; (8001514 <_ZL12MX_GPIO_Initv+0x190>) + 80013e8: f043 0310 orr.w r3, r3, #16 + 80013ec: 6313 str r3, [r2, #48] ; 0x30 + 80013ee: 4b49 ldr r3, [pc, #292] ; (8001514 <_ZL12MX_GPIO_Initv+0x190>) + 80013f0: 6b1b ldr r3, [r3, #48] ; 0x30 + 80013f2: f003 0310 and.w r3, r3, #16 + 80013f6: 60fb str r3, [r7, #12] + 80013f8: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOD_CLK_ENABLE(); + 80013fa: 4b46 ldr r3, [pc, #280] ; (8001514 <_ZL12MX_GPIO_Initv+0x190>) + 80013fc: 6b1b ldr r3, [r3, #48] ; 0x30 + 80013fe: 4a45 ldr r2, [pc, #276] ; (8001514 <_ZL12MX_GPIO_Initv+0x190>) + 8001400: f043 0308 orr.w r3, r3, #8 + 8001404: 6313 str r3, [r2, #48] ; 0x30 + 8001406: 4b43 ldr r3, [pc, #268] ; (8001514 <_ZL12MX_GPIO_Initv+0x190>) + 8001408: 6b1b ldr r3, [r3, #48] ; 0x30 + 800140a: f003 0308 and.w r3, r3, #8 + 800140e: 60bb str r3, [r7, #8] + 8001410: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8001412: 4b40 ldr r3, [pc, #256] ; (8001514 <_ZL12MX_GPIO_Initv+0x190>) + 8001414: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001416: 4a3f ldr r2, [pc, #252] ; (8001514 <_ZL12MX_GPIO_Initv+0x190>) + 8001418: f043 0302 orr.w r3, r3, #2 + 800141c: 6313 str r3, [r2, #48] ; 0x30 + 800141e: 4b3d ldr r3, [pc, #244] ; (8001514 <_ZL12MX_GPIO_Initv+0x190>) + 8001420: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001422: f003 0302 and.w r3, r3, #2 + 8001426: 607b str r3, [r7, #4] + 8001428: 687b ldr r3, [r7, #4] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOF, dir2_Pin | dir1_Pin, GPIO_PIN_RESET); + 800142a: 2200 movs r2, #0 + 800142c: f44f 5140 mov.w r1, #12288 ; 0x3000 + 8001430: 4839 ldr r0, [pc, #228] ; (8001518 <_ZL12MX_GPIO_Initv+0x194>) + 8001432: f004 f9b9 bl 80057a8 + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOF, sleep2_Pin | sleep1_Pin, GPIO_PIN_SET); + 8001436: 2201 movs r2, #1 + 8001438: f44f 4140 mov.w r1, #49152 ; 0xc000 + 800143c: 4836 ldr r0, [pc, #216] ; (8001518 <_ZL12MX_GPIO_Initv+0x194>) + 800143e: f004 f9b3 bl 80057a8 + + /*Configure GPIO pin : user_button_Pin */ + GPIO_InitStruct.Pin = user_button_Pin; + 8001442: f44f 5300 mov.w r3, #8192 ; 0x2000 + 8001446: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + 8001448: 4b34 ldr r3, [pc, #208] ; (800151c <_ZL12MX_GPIO_Initv+0x198>) + 800144a: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800144c: 2300 movs r3, #0 + 800144e: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(user_button_GPIO_Port, &GPIO_InitStruct); + 8001450: f107 031c add.w r3, r7, #28 + 8001454: 4619 mov r1, r3 + 8001456: 4832 ldr r0, [pc, #200] ; (8001520 <_ZL12MX_GPIO_Initv+0x19c>) + 8001458: f003 fffc bl 8005454 + + /*Configure GPIO pin : current2_Pin */ + GPIO_InitStruct.Pin = current2_Pin; + 800145c: 2301 movs r3, #1 + 800145e: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 8001460: 2303 movs r3, #3 + 8001462: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001464: 2300 movs r3, #0 + 8001466: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(current2_GPIO_Port, &GPIO_InitStruct); + 8001468: f107 031c add.w r3, r7, #28 + 800146c: 4619 mov r1, r3 + 800146e: 482c ldr r0, [pc, #176] ; (8001520 <_ZL12MX_GPIO_Initv+0x19c>) + 8001470: f003 fff0 bl 8005454 + + /*Configure GPIO pin : current1_Pin */ + GPIO_InitStruct.Pin = current1_Pin; + 8001474: 2308 movs r3, #8 + 8001476: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 8001478: 2303 movs r3, #3 + 800147a: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800147c: 2300 movs r3, #0 + 800147e: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(current1_GPIO_Port, &GPIO_InitStruct); + 8001480: f107 031c add.w r3, r7, #28 + 8001484: 4619 mov r1, r3 + 8001486: 4827 ldr r0, [pc, #156] ; (8001524 <_ZL12MX_GPIO_Initv+0x1a0>) + 8001488: f003 ffe4 bl 8005454 + + /*Configure GPIO pin : fault2_Pin */ + GPIO_InitStruct.Pin = fault2_Pin; + 800148c: 2340 movs r3, #64 ; 0x40 + 800148e: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8001490: 2300 movs r3, #0 + 8001492: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001494: 2300 movs r3, #0 + 8001496: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(fault2_GPIO_Port, &GPIO_InitStruct); + 8001498: f107 031c add.w r3, r7, #28 + 800149c: 4619 mov r1, r3 + 800149e: 4821 ldr r0, [pc, #132] ; (8001524 <_ZL12MX_GPIO_Initv+0x1a0>) + 80014a0: f003 ffd8 bl 8005454 + + /*Configure GPIO pins : dir2_Pin dir1_Pin */ + GPIO_InitStruct.Pin = dir2_Pin | dir1_Pin; + 80014a4: f44f 5340 mov.w r3, #12288 ; 0x3000 + 80014a8: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 80014aa: 2301 movs r3, #1 + 80014ac: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80014ae: 2300 movs r3, #0 + 80014b0: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80014b2: 2300 movs r3, #0 + 80014b4: 62bb str r3, [r7, #40] ; 0x28 + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + 80014b6: f107 031c add.w r3, r7, #28 + 80014ba: 4619 mov r1, r3 + 80014bc: 4816 ldr r0, [pc, #88] ; (8001518 <_ZL12MX_GPIO_Initv+0x194>) + 80014be: f003 ffc9 bl 8005454 + + /*Configure GPIO pins : sleep2_Pin sleep1_Pin */ + GPIO_InitStruct.Pin = sleep2_Pin | sleep1_Pin; + 80014c2: f44f 4340 mov.w r3, #49152 ; 0xc000 + 80014c6: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 80014c8: 2301 movs r3, #1 + 80014ca: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 80014cc: 2301 movs r3, #1 + 80014ce: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80014d0: 2300 movs r3, #0 + 80014d2: 62bb str r3, [r7, #40] ; 0x28 + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + 80014d4: f107 031c add.w r3, r7, #28 + 80014d8: 4619 mov r1, r3 + 80014da: 480f ldr r0, [pc, #60] ; (8001518 <_ZL12MX_GPIO_Initv+0x194>) + 80014dc: f003 ffba bl 8005454 + + /*Configure GPIO pin : fault1_Pin */ + GPIO_InitStruct.Pin = fault1_Pin; + 80014e0: f44f 7300 mov.w r3, #512 ; 0x200 + 80014e4: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 80014e6: 2300 movs r3, #0 + 80014e8: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80014ea: 2300 movs r3, #0 + 80014ec: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(fault1_GPIO_Port, &GPIO_InitStruct); + 80014ee: f107 031c add.w r3, r7, #28 + 80014f2: 4619 mov r1, r3 + 80014f4: 480c ldr r0, [pc, #48] ; (8001528 <_ZL12MX_GPIO_Initv+0x1a4>) + 80014f6: f003 ffad bl 8005454 + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); + 80014fa: 2200 movs r2, #0 + 80014fc: 2100 movs r1, #0 + 80014fe: 2028 movs r0, #40 ; 0x28 + 8001500: f003 ff4f bl 80053a2 + HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); + 8001504: 2028 movs r0, #40 ; 0x28 + 8001506: f003 ff68 bl 80053da + +} + 800150a: bf00 nop + 800150c: 3730 adds r7, #48 ; 0x30 + 800150e: 46bd mov sp, r7 + 8001510: bd80 pop {r7, pc} + 8001512: bf00 nop + 8001514: 40023800 .word 0x40023800 + 8001518: 40021400 .word 0x40021400 + 800151c: 10110000 .word 0x10110000 + 8001520: 40020800 .word 0x40020800 + 8001524: 40020000 .word 0x40020000 + 8001528: 40021000 .word 0x40021000 + +0800152c : + +/* USER CODE BEGIN 4 */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { + 800152c: b5b0 push {r4, r5, r7, lr} + 800152e: ed2d 8b02 vpush {d8} + 8001532: b08a sub sp, #40 ; 0x28 + 8001534: af00 add r7, sp, #0 + 8001536: 61f8 str r0, [r7, #28] + + //TIMER 100Hz PID control + if (htim->Instance == TIM3) { + 8001538: 69fb ldr r3, [r7, #28] + 800153a: 681b ldr r3, [r3, #0] + 800153c: 4a4a ldr r2, [pc, #296] ; (8001668 ) + 800153e: 4293 cmp r3, r2 + 8001540: d14d bne.n 80015de + + left_velocity = left_encoder.GetLinearVelocity(); + 8001542: 484a ldr r0, [pc, #296] ; (800166c ) + 8001544: f7ff f884 bl 8000650 <_ZN7Encoder17GetLinearVelocityEv> + 8001548: eef0 7a40 vmov.f32 s15, s0 + 800154c: 4b48 ldr r3, [pc, #288] ; (8001670 ) + 800154e: edc3 7a00 vstr s15, [r3] + left_dutycycle = left_pid.update(left_velocity); + 8001552: 4b47 ldr r3, [pc, #284] ; (8001670 ) + 8001554: edd3 7a00 vldr s15, [r3] + 8001558: eeb0 0a67 vmov.f32 s0, s15 + 800155c: 4845 ldr r0, [pc, #276] ; (8001674 ) + 800155e: f7ff fb4b bl 8000bf8 <_ZN3Pid6updateEf> + 8001562: 4602 mov r2, r0 + 8001564: 4b44 ldr r3, [pc, #272] ; (8001678 ) + 8001566: 601a str r2, [r3, #0] + left_motor.set_speed(left_dutycycle); + 8001568: 4b43 ldr r3, [pc, #268] ; (8001678 ) + 800156a: 681b ldr r3, [r3, #0] + 800156c: 4619 mov r1, r3 + 800156e: 4843 ldr r0, [pc, #268] ; (800167c ) + 8001570: f7ff f9a0 bl 80008b4 <_ZN15MotorController9set_speedEi> + + right_velocity = right_encoder.GetLinearVelocity(); + 8001574: 4842 ldr r0, [pc, #264] ; (8001680 ) + 8001576: f7ff f86b bl 8000650 <_ZN7Encoder17GetLinearVelocityEv> + 800157a: eef0 7a40 vmov.f32 s15, s0 + 800157e: 4b41 ldr r3, [pc, #260] ; (8001684 ) + 8001580: edc3 7a00 vstr s15, [r3] + right_dutycycle = right_pid.update(right_velocity); + 8001584: 4b3f ldr r3, [pc, #252] ; (8001684 ) + 8001586: edd3 7a00 vldr s15, [r3] + 800158a: eeb0 0a67 vmov.f32 s0, s15 + 800158e: 483e ldr r0, [pc, #248] ; (8001688 ) + 8001590: f7ff fb32 bl 8000bf8 <_ZN3Pid6updateEf> + 8001594: 4602 mov r2, r0 + 8001596: 4b3d ldr r3, [pc, #244] ; (800168c ) + 8001598: 601a str r2, [r3, #0] + right_motor.set_speed(right_dutycycle); + 800159a: 4b3c ldr r3, [pc, #240] ; (800168c ) + 800159c: 681b ldr r3, [r3, #0] + 800159e: 4619 mov r1, r3 + 80015a0: 483b ldr r0, [pc, #236] ; (8001690 ) + 80015a2: f7ff f987 bl 80008b4 <_ZN15MotorController9set_speedEi> + + float difference = left_velocity - right_velocity; + 80015a6: 4b32 ldr r3, [pc, #200] ; (8001670 ) + 80015a8: ed93 7a00 vldr s14, [r3] + 80015ac: 4b35 ldr r3, [pc, #212] ; (8001684 ) + 80015ae: edd3 7a00 vldr s15, [r3] + 80015b2: ee77 7a67 vsub.f32 s15, s14, s15 + 80015b6: edc7 7a09 vstr s15, [r7, #36] ; 0x24 + + int cross_dutycycle = cross_pid.update(difference); + 80015ba: ed97 0a09 vldr s0, [r7, #36] ; 0x24 + 80015be: 4835 ldr r0, [pc, #212] ; (8001694 ) + 80015c0: f7ff fb1a bl 8000bf8 <_ZN3Pid6updateEf> + 80015c4: 6238 str r0, [r7, #32] + + left_dutycycle += cross_dutycycle; + 80015c6: 4b2c ldr r3, [pc, #176] ; (8001678 ) + 80015c8: 681a ldr r2, [r3, #0] + 80015ca: 6a3b ldr r3, [r7, #32] + 80015cc: 4413 add r3, r2 + 80015ce: 4a2a ldr r2, [pc, #168] ; (8001678 ) + 80015d0: 6013 str r3, [r2, #0] + right_dutycycle -= cross_dutycycle; + 80015d2: 4b2e ldr r3, [pc, #184] ; (800168c ) + 80015d4: 681a ldr r2, [r3, #0] + 80015d6: 6a3b ldr r3, [r7, #32] + 80015d8: 1ad3 subs r3, r2, r3 + 80015da: 4a2c ldr r2, [pc, #176] ; (800168c ) + 80015dc: 6013 str r3, [r2, #0] + + } + + //TIMER 2Hz Transmit + if (htim->Instance == TIM6) { + 80015de: 69fb ldr r3, [r7, #28] + 80015e0: 681b ldr r3, [r3, #0] + 80015e2: 4a2d ldr r2, [pc, #180] ; (8001698 ) + 80015e4: 4293 cmp r3, r2 + 80015e6: d138 bne.n 800165a + + odom.UpdateValuesFromWheels(left_encoder.GetLinearVelocity(), + 80015e8: 4820 ldr r0, [pc, #128] ; (800166c ) + 80015ea: f7ff f831 bl 8000650 <_ZN7Encoder17GetLinearVelocityEv> + 80015ee: eeb0 8a40 vmov.f32 s16, s0 + 80015f2: 4823 ldr r0, [pc, #140] ; (8001680 ) + 80015f4: f7ff f82c bl 8000650 <_ZN7Encoder17GetLinearVelocityEv> + 80015f8: eef0 7a40 vmov.f32 s15, s0 + 80015fc: eef0 0a67 vmov.f32 s1, s15 + 8001600: eeb0 0a48 vmov.f32 s0, s16 + 8001604: 4825 ldr r0, [pc, #148] ; (800169c ) + 8001606: f7ff f8b7 bl 8000778 <_ZN8Odometry22UpdateValuesFromWheelsEff> + right_encoder.GetLinearVelocity()); + + vel_output.linear_vel = odom.GetLinearVelocity(); + 800160a: 4824 ldr r0, [pc, #144] ; (800169c ) + 800160c: f7ff f902 bl 8000814 <_ZN8Odometry17GetLinearVelocityEv> + 8001610: eef0 7a40 vmov.f32 s15, s0 + 8001614: 4b22 ldr r3, [pc, #136] ; (80016a0 ) + 8001616: edc3 7a00 vstr s15, [r3] + vel_output.angular_vel = odom.GetAngularVelocity(); + 800161a: 4820 ldr r0, [pc, #128] ; (800169c ) + 800161c: f7ff f909 bl 8000832 <_ZN8Odometry18GetAngularVelocityEv> + 8001620: eef0 7a40 vmov.f32 s15, s0 + 8001624: 4b1e ldr r3, [pc, #120] ; (80016a0 ) + 8001626: edc3 7a01 vstr s15, [r3, #4] + + stream_tx = pb_ostream_from_buffer(buffer_tx, sizeof(buffer_tx)); + 800162a: 4c1e ldr r4, [pc, #120] ; (80016a4 ) + 800162c: 463b mov r3, r7 + 800162e: 220a movs r2, #10 + 8001630: 491d ldr r1, [pc, #116] ; (80016a8 ) + 8001632: 4618 mov r0, r3 + 8001634: f002 faa2 bl 8003b7c + 8001638: 4625 mov r5, r4 + 800163a: 463c mov r4, r7 + 800163c: cc0f ldmia r4!, {r0, r1, r2, r3} + 800163e: c50f stmia r5!, {r0, r1, r2, r3} + 8001640: 6823 ldr r3, [r4, #0] + 8001642: 602b str r3, [r5, #0] + + pb_encode(&stream_tx, Velocities_fields, &vel_output); + 8001644: 4a16 ldr r2, [pc, #88] ; (80016a0 ) + 8001646: 4919 ldr r1, [pc, #100] ; (80016ac ) + 8001648: 4816 ldr r0, [pc, #88] ; (80016a4 ) + 800164a: f002 feaa bl 80043a2 + + HAL_UART_Transmit(&huart6, buffer_tx, 10, 100); + 800164e: 2364 movs r3, #100 ; 0x64 + 8001650: 220a movs r2, #10 + 8001652: 4915 ldr r1, [pc, #84] ; (80016a8 ) + 8001654: 4816 ldr r0, [pc, #88] ; (80016b0 ) + 8001656: f006 fa77 bl 8007b48 + } +} + 800165a: bf00 nop + 800165c: 3728 adds r7, #40 ; 0x28 + 800165e: 46bd mov sp, r7 + 8001660: ecbd 8b02 vpop {d8} + 8001664: bdb0 pop {r4, r5, r7, pc} + 8001666: bf00 nop + 8001668: 40000400 .word 0x40000400 + 800166c: 20000204 .word 0x20000204 + 8001670: 2000022c .word 0x2000022c + 8001674: 20000234 .word 0x20000234 + 8001678: 200002ac .word 0x200002ac + 800167c: 200002cc .word 0x200002cc + 8001680: 200001ec .word 0x200001ec + 8001684: 20000230 .word 0x20000230 + 8001688: 20000258 .word 0x20000258 + 800168c: 200002b0 .word 0x200002b0 + 8001690: 200002b4 .word 0x200002b4 + 8001694: 2000027c .word 0x2000027c + 8001698: 40001000 .word 0x40001000 + 800169c: 2000021c .word 0x2000021c + 80016a0: 20000308 .word 0x20000308 + 80016a4: 2000031c .word 0x2000031c + 80016a8: 20000310 .word 0x20000310 + 80016ac: 08008cd0 .word 0x08008cd0 + 80016b0: 2000016c .word 0x2000016c + +080016b4 : + +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *UartHandle) { + 80016b4: b580 push {r7, lr} + 80016b6: b088 sub sp, #32 + 80016b8: af00 add r7, sp, #0 + 80016ba: 6078 str r0, [r7, #4] + + pb_istream_t stream = pb_istream_from_buffer(buffer_rx, 10); + 80016bc: f107 030c add.w r3, r7, #12 + 80016c0: 220a movs r2, #10 + 80016c2: 492c ldr r1, [pc, #176] ; (8001774 ) + 80016c4: 4618 mov r0, r3 + 80016c6: f000 fc99 bl 8001ffc + + bool status = pb_decode(&stream, Velocities_fields, &vel_input); + 80016ca: f107 030c add.w r3, r7, #12 + 80016ce: 4a2a ldr r2, [pc, #168] ; (8001778 ) + 80016d0: 492a ldr r1, [pc, #168] ; (800177c ) + 80016d2: 4618 mov r0, r3 + 80016d4: f001 fdda bl 800328c + 80016d8: 4603 mov r3, r0 + 80016da: 77fb strb r3, [r7, #31] + + // if decoding went ok + if (status) { + 80016dc: 7ffb ldrb r3, [r7, #31] + 80016de: 2b00 cmp r3, #0 + 80016e0: d03f beq.n 8001762 + + odom.UpdateValuesFromVel(vel_input.linear_vel, vel_input.angular_vel); + 80016e2: 4b25 ldr r3, [pc, #148] ; (8001778 ) + 80016e4: edd3 7a00 vldr s15, [r3] + 80016e8: 4b23 ldr r3, [pc, #140] ; (8001778 ) + 80016ea: ed93 7a01 vldr s14, [r3, #4] + 80016ee: eef0 0a47 vmov.f32 s1, s14 + 80016f2: eeb0 0a67 vmov.f32 s0, s15 + 80016f6: 4822 ldr r0, [pc, #136] ; (8001780 ) + 80016f8: f7fe fffe bl 80006f8 <_ZN8Odometry19UpdateValuesFromVelEff> + + left_setpoint = odom.GetLeftVelocity(); + 80016fc: 4820 ldr r0, [pc, #128] ; (8001780 ) + 80016fe: f7ff f86b bl 80007d8 <_ZN8Odometry15GetLeftVelocityEv> + 8001702: eef0 7a40 vmov.f32 s15, s0 + 8001706: 4b1f ldr r3, [pc, #124] ; (8001784 ) + 8001708: edc3 7a00 vstr s15, [r3] + right_setpoint = odom.GetRightVelocity(); + 800170c: 481c ldr r0, [pc, #112] ; (8001780 ) + 800170e: f7ff f872 bl 80007f6 <_ZN8Odometry16GetRightVelocityEv> + 8001712: eef0 7a40 vmov.f32 s15, s0 + 8001716: 4b1c ldr r3, [pc, #112] ; (8001788 ) + 8001718: edc3 7a00 vstr s15, [r3] + + left_pid.set(left_setpoint); + 800171c: 4b19 ldr r3, [pc, #100] ; (8001784 ) + 800171e: edd3 7a00 vldr s15, [r3] + 8001722: eeb0 0a67 vmov.f32 s0, s15 + 8001726: 4819 ldr r0, [pc, #100] ; (800178c ) + 8001728: f7ff fa57 bl 8000bda <_ZN3Pid3setEf> + right_pid.set(right_setpoint); + 800172c: 4b16 ldr r3, [pc, #88] ; (8001788 ) + 800172e: edd3 7a00 vldr s15, [r3] + 8001732: eeb0 0a67 vmov.f32 s0, s15 + 8001736: 4816 ldr r0, [pc, #88] ; (8001790 ) + 8001738: f7ff fa4f bl 8000bda <_ZN3Pid3setEf> + + cross_setpoint = left_setpoint - right_setpoint; + 800173c: 4b11 ldr r3, [pc, #68] ; (8001784 ) + 800173e: ed93 7a00 vldr s14, [r3] + 8001742: 4b11 ldr r3, [pc, #68] ; (8001788 ) + 8001744: edd3 7a00 vldr s15, [r3] + 8001748: ee77 7a67 vsub.f32 s15, s14, s15 + 800174c: 4b11 ldr r3, [pc, #68] ; (8001794 ) + 800174e: edc3 7a00 vstr s15, [r3] + cross_pid.set(cross_setpoint); + 8001752: 4b10 ldr r3, [pc, #64] ; (8001794 ) + 8001754: edd3 7a00 vldr s15, [r3] + 8001758: eeb0 0a67 vmov.f32 s0, s15 + 800175c: 480e ldr r0, [pc, #56] ; (8001798 ) + 800175e: f7ff fa3c bl 8000bda <_ZN3Pid3setEf> + } + + HAL_UART_Receive_IT(&huart6, buffer_rx, 10); + 8001762: 220a movs r2, #10 + 8001764: 4903 ldr r1, [pc, #12] ; (8001774 ) + 8001766: 480d ldr r0, [pc, #52] ; (800179c ) + 8001768: f006 fa80 bl 8007c6c + +} + 800176c: bf00 nop + 800176e: 3720 adds r7, #32 + 8001770: 46bd mov sp, r7 + 8001772: bd80 pop {r7, pc} + 8001774: 20000338 .word 0x20000338 + 8001778: 20000330 .word 0x20000330 + 800177c: 08008cd0 .word 0x08008cd0 + 8001780: 2000021c .word 0x2000021c + 8001784: 200002a0 .word 0x200002a0 + 8001788: 200002a4 .word 0x200002a4 + 800178c: 20000234 .word 0x20000234 + 8001790: 20000258 .word 0x20000258 + 8001794: 200002a8 .word 0x200002a8 + 8001798: 2000027c .word 0x2000027c + 800179c: 2000016c .word 0x2000016c + +080017a0 : + +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { + 80017a0: b580 push {r7, lr} + 80017a2: b082 sub sp, #8 + 80017a4: af00 add r7, sp, #0 + 80017a6: 4603 mov r3, r0 + 80017a8: 80fb strh r3, [r7, #6] + //Blue user button + if (GPIO_Pin == GPIO_PIN_13) { + 80017aa: 88fb ldrh r3, [r7, #6] + 80017ac: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 80017b0: d12b bne.n 800180a + previous_millis = current_millis; + 80017b2: 4b18 ldr r3, [pc, #96] ; (8001814 ) + 80017b4: 681b ldr r3, [r3, #0] + 80017b6: 4a18 ldr r2, [pc, #96] ; (8001818 ) + 80017b8: 6013 str r3, [r2, #0] + current_millis = HAL_GetTick(); + 80017ba: f003 fd0b bl 80051d4 + 80017be: 4603 mov r3, r0 + 80017c0: 461a mov r2, r3 + 80017c2: 4b14 ldr r3, [pc, #80] ; (8001814 ) + 80017c4: 601a str r2, [r3, #0] + if (current_millis - previous_millis < 500) + 80017c6: 4b13 ldr r3, [pc, #76] ; (8001814 ) + 80017c8: 681a ldr r2, [r3, #0] + 80017ca: 4b13 ldr r3, [pc, #76] ; (8001818 ) + 80017cc: 681b ldr r3, [r3, #0] + 80017ce: 1ad3 subs r3, r2, r3 + 80017d0: f5b3 7ffa cmp.w r3, #500 ; 0x1f4 + 80017d4: da03 bge.n 80017de + debounce = false; + 80017d6: 4b11 ldr r3, [pc, #68] ; (800181c ) + 80017d8: 2200 movs r2, #0 + 80017da: 701a strb r2, [r3, #0] + 80017dc: e002 b.n 80017e4 + else + debounce = true; + 80017de: 4b0f ldr r3, [pc, #60] ; (800181c ) + 80017e0: 2201 movs r2, #1 + 80017e2: 701a strb r2, [r3, #0] + if (mode == 0 && debounce) { + 80017e4: 4b0e ldr r3, [pc, #56] ; (8001820 ) + 80017e6: edd3 7a00 vldr s15, [r3] + 80017ea: eef5 7a40 vcmp.f32 s15, #0.0 + 80017ee: eef1 fa10 vmrs APSR_nzcv, fpscr + 80017f2: d10a bne.n 800180a + 80017f4: 4b09 ldr r3, [pc, #36] ; (800181c ) + 80017f6: 781b ldrb r3, [r3, #0] + 80017f8: 2b00 cmp r3, #0 + 80017fa: d006 beq.n 800180a + mode = 1; + 80017fc: 4b08 ldr r3, [pc, #32] ; (8001820 ) + 80017fe: f04f 527e mov.w r2, #1065353216 ; 0x3f800000 + 8001802: 601a str r2, [r3, #0] + //Enables TIM3 interrupt (used for PID control) + HAL_TIM_Base_Start_IT(&htim3); + 8001804: 4807 ldr r0, [pc, #28] ; (8001824 ) + 8001806: f005 f893 bl 8006930 + } + } +} + 800180a: bf00 nop + 800180c: 3708 adds r7, #8 + 800180e: 46bd mov sp, r7 + 8001810: bd80 pop {r7, pc} + 8001812: bf00 nop + 8001814: 20000300 .word 0x20000300 + 8001818: 200002fc .word 0x200002fc + 800181c: 20000000 .word 0x20000000 + 8001820: 20000304 .word 0x20000304 + 8001824: 2000006c .word 0x2000006c + +08001828 : + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) { + 8001828: b480 push {r7} + 800182a: af00 add r7, sp, #0 + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} + 800182c: bf00 nop + 800182e: 46bd mov sp, r7 + 8001830: f85d 7b04 ldr.w r7, [sp], #4 + 8001834: 4770 bx lr + ... + +08001838 <_Z41__static_initialization_and_destruction_0ii>: + 8001838: b580 push {r7, lr} + 800183a: b086 sub sp, #24 + 800183c: af04 add r7, sp, #16 + 800183e: 6078 str r0, [r7, #4] + 8001840: 6039 str r1, [r7, #0] + 8001842: 687b ldr r3, [r7, #4] + 8001844: 2b01 cmp r3, #1 + 8001846: d148 bne.n 80018da <_Z41__static_initialization_and_destruction_0ii+0xa2> + 8001848: 683b ldr r3, [r7, #0] + 800184a: f64f 72ff movw r2, #65535 ; 0xffff + 800184e: 4293 cmp r3, r2 + 8001850: d143 bne.n 80018da <_Z41__static_initialization_and_destruction_0ii+0xa2> +Encoder right_encoder = Encoder(&htim5, RIGHT_TICKS_PER_METER); + 8001852: 4a24 ldr r2, [pc, #144] ; (80018e4 <_Z41__static_initialization_and_destruction_0ii+0xac>) + 8001854: 4924 ldr r1, [pc, #144] ; (80018e8 <_Z41__static_initialization_and_destruction_0ii+0xb0>) + 8001856: 4825 ldr r0, [pc, #148] ; (80018ec <_Z41__static_initialization_and_destruction_0ii+0xb4>) + 8001858: f7fe fe95 bl 8000586 <_ZN7EncoderC1EP17TIM_HandleTypeDefi> +Encoder left_encoder = Encoder(&htim2, LEFT_TICKS_PER_METER); + 800185c: 4a24 ldr r2, [pc, #144] ; (80018f0 <_Z41__static_initialization_and_destruction_0ii+0xb8>) + 800185e: 4925 ldr r1, [pc, #148] ; (80018f4 <_Z41__static_initialization_and_destruction_0ii+0xbc>) + 8001860: 4825 ldr r0, [pc, #148] ; (80018f8 <_Z41__static_initialization_and_destruction_0ii+0xc0>) + 8001862: f7fe fe90 bl 8000586 <_ZN7EncoderC1EP17TIM_HandleTypeDefi> +Odometry odom = Odometry(); + 8001866: 4825 ldr r0, [pc, #148] ; (80018fc <_Z41__static_initialization_and_destruction_0ii+0xc4>) + 8001868: f7fe ff2a bl 80006c0 <_ZN8OdometryC1Ev> +Pid left_pid(0, 0, 0); + 800186c: ed9f 1a24 vldr s2, [pc, #144] ; 8001900 <_Z41__static_initialization_and_destruction_0ii+0xc8> + 8001870: eddf 0a23 vldr s1, [pc, #140] ; 8001900 <_Z41__static_initialization_and_destruction_0ii+0xc8> + 8001874: ed9f 0a22 vldr s0, [pc, #136] ; 8001900 <_Z41__static_initialization_and_destruction_0ii+0xc8> + 8001878: 4822 ldr r0, [pc, #136] ; (8001904 <_Z41__static_initialization_and_destruction_0ii+0xcc>) + 800187a: f7ff f951 bl 8000b20 <_ZN3PidC1Efff> +Pid right_pid(0, 0, 0); + 800187e: ed9f 1a20 vldr s2, [pc, #128] ; 8001900 <_Z41__static_initialization_and_destruction_0ii+0xc8> + 8001882: eddf 0a1f vldr s1, [pc, #124] ; 8001900 <_Z41__static_initialization_and_destruction_0ii+0xc8> + 8001886: ed9f 0a1e vldr s0, [pc, #120] ; 8001900 <_Z41__static_initialization_and_destruction_0ii+0xc8> + 800188a: 481f ldr r0, [pc, #124] ; (8001908 <_Z41__static_initialization_and_destruction_0ii+0xd0>) + 800188c: f7ff f948 bl 8000b20 <_ZN3PidC1Efff> +Pid cross_pid(0, 0, 0); + 8001890: ed9f 1a1b vldr s2, [pc, #108] ; 8001900 <_Z41__static_initialization_and_destruction_0ii+0xc8> + 8001894: eddf 0a1a vldr s1, [pc, #104] ; 8001900 <_Z41__static_initialization_and_destruction_0ii+0xc8> + 8001898: ed9f 0a19 vldr s0, [pc, #100] ; 8001900 <_Z41__static_initialization_and_destruction_0ii+0xc8> + 800189c: 481b ldr r0, [pc, #108] ; (800190c <_Z41__static_initialization_and_destruction_0ii+0xd4>) + 800189e: f7ff f93f bl 8000b20 <_ZN3PidC1Efff> + TIM_CHANNEL_4); + 80018a2: 230c movs r3, #12 + 80018a4: 9302 str r3, [sp, #8] + 80018a6: 4b1a ldr r3, [pc, #104] ; (8001910 <_Z41__static_initialization_and_destruction_0ii+0xd8>) + 80018a8: 9301 str r3, [sp, #4] + 80018aa: f44f 5300 mov.w r3, #8192 ; 0x2000 + 80018ae: 9300 str r3, [sp, #0] + 80018b0: 4b18 ldr r3, [pc, #96] ; (8001914 <_Z41__static_initialization_and_destruction_0ii+0xdc>) + 80018b2: f44f 4200 mov.w r2, #32768 ; 0x8000 + 80018b6: 4917 ldr r1, [pc, #92] ; (8001914 <_Z41__static_initialization_and_destruction_0ii+0xdc>) + 80018b8: 4817 ldr r0, [pc, #92] ; (8001918 <_Z41__static_initialization_and_destruction_0ii+0xe0>) + 80018ba: f7fe ffc9 bl 8000850 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm> + TIM_CHANNEL_3); + 80018be: 2308 movs r3, #8 + 80018c0: 9302 str r3, [sp, #8] + 80018c2: 4b13 ldr r3, [pc, #76] ; (8001910 <_Z41__static_initialization_and_destruction_0ii+0xd8>) + 80018c4: 9301 str r3, [sp, #4] + 80018c6: f44f 5380 mov.w r3, #4096 ; 0x1000 + 80018ca: 9300 str r3, [sp, #0] + 80018cc: 4b11 ldr r3, [pc, #68] ; (8001914 <_Z41__static_initialization_and_destruction_0ii+0xdc>) + 80018ce: f44f 4280 mov.w r2, #16384 ; 0x4000 + 80018d2: 4910 ldr r1, [pc, #64] ; (8001914 <_Z41__static_initialization_and_destruction_0ii+0xdc>) + 80018d4: 4811 ldr r0, [pc, #68] ; (800191c <_Z41__static_initialization_and_destruction_0ii+0xe4>) + 80018d6: f7fe ffbb bl 8000850 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm> +} + 80018da: bf00 nop + 80018dc: 3708 adds r7, #8 + 80018de: 46bd mov sp, r7 + 80018e0: bd80 pop {r7, pc} + 80018e2: bf00 nop + 80018e4: 000300dd .word 0x000300dd + 80018e8: 200000ec .word 0x200000ec + 80018ec: 200001ec .word 0x200001ec + 80018f0: 0002fccc .word 0x0002fccc + 80018f4: 2000002c .word 0x2000002c + 80018f8: 20000204 .word 0x20000204 + 80018fc: 2000021c .word 0x2000021c + 8001900: 00000000 .word 0x00000000 + 8001904: 20000234 .word 0x20000234 + 8001908: 20000258 .word 0x20000258 + 800190c: 2000027c .word 0x2000027c + 8001910: 200000ac .word 0x200000ac + 8001914: 40021400 .word 0x40021400 + 8001918: 200002b4 .word 0x200002b4 + 800191c: 200002cc .word 0x200002cc + +08001920 <_GLOBAL__sub_I_htim2>: + 8001920: b580 push {r7, lr} + 8001922: af00 add r7, sp, #0 + 8001924: f64f 71ff movw r1, #65535 ; 0xffff + 8001928: 2001 movs r0, #1 + 800192a: f7ff ff85 bl 8001838 <_Z41__static_initialization_and_destruction_0ii> + 800192e: bd80 pop {r7, pc} + +08001930 : + */ + +#include "pb_common.h" + +static bool load_descriptor_values(pb_field_iter_t *iter) +{ + 8001930: b480 push {r7} + 8001932: b08f sub sp, #60 ; 0x3c + 8001934: af00 add r7, sp, #0 + 8001936: 6078 str r0, [r7, #4] + uint32_t word0; + uint32_t data_offset; + uint8_t format; + int8_t size_offset; + + if (iter->index >= iter->descriptor->field_count) + 8001938: 687b ldr r3, [r7, #4] + 800193a: 891a ldrh r2, [r3, #8] + 800193c: 687b ldr r3, [r7, #4] + 800193e: 681b ldr r3, [r3, #0] + 8001940: 881b ldrh r3, [r3, #0] + 8001942: b29b uxth r3, r3 + 8001944: 429a cmp r2, r3 + 8001946: d301 bcc.n 800194c + return false; + 8001948: 2300 movs r3, #0 + 800194a: e14d b.n 8001be8 + + word0 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index]); + 800194c: 687b ldr r3, [r7, #4] + 800194e: 681b ldr r3, [r3, #0] + 8001950: f8d3 2002 ldr.w r2, [r3, #2] + 8001954: 687b ldr r3, [r7, #4] + 8001956: 895b ldrh r3, [r3, #10] + 8001958: 009b lsls r3, r3, #2 + 800195a: 4413 add r3, r2 + 800195c: 681b ldr r3, [r3, #0] + 800195e: 62fb str r3, [r7, #44] ; 0x2c + format = word0 & 3; + 8001960: 6afb ldr r3, [r7, #44] ; 0x2c + 8001962: b2db uxtb r3, r3 + 8001964: f003 0303 and.w r3, r3, #3 + 8001968: f887 302b strb.w r3, [r7, #43] ; 0x2b + iter->tag = (pb_size_t)((word0 >> 2) & 0x3F); + 800196c: 6afb ldr r3, [r7, #44] ; 0x2c + 800196e: 089b lsrs r3, r3, #2 + 8001970: b29b uxth r3, r3 + 8001972: f003 033f and.w r3, r3, #63 ; 0x3f + 8001976: b29a uxth r2, r3 + 8001978: 687b ldr r3, [r7, #4] + 800197a: 821a strh r2, [r3, #16] + iter->type = (pb_type_t)((word0 >> 8) & 0xFF); + 800197c: 6afb ldr r3, [r7, #44] ; 0x2c + 800197e: 0a1b lsrs r3, r3, #8 + 8001980: b2da uxtb r2, r3 + 8001982: 687b ldr r3, [r7, #4] + 8001984: 759a strb r2, [r3, #22] + + if (format == 0) + 8001986: f897 302b ldrb.w r3, [r7, #43] ; 0x2b + 800198a: 2b00 cmp r3, #0 + 800198c: d116 bne.n 80019bc + { + /* 1-word format */ + iter->array_size = 1; + 800198e: 687b ldr r3, [r7, #4] + 8001990: 2201 movs r2, #1 + 8001992: 829a strh r2, [r3, #20] + size_offset = (int8_t)((word0 >> 24) & 0x0F); + 8001994: 6afb ldr r3, [r7, #44] ; 0x2c + 8001996: 0e1b lsrs r3, r3, #24 + 8001998: b25b sxtb r3, r3 + 800199a: f003 030f and.w r3, r3, #15 + 800199e: f887 3033 strb.w r3, [r7, #51] ; 0x33 + data_offset = (word0 >> 16) & 0xFF; + 80019a2: 6afb ldr r3, [r7, #44] ; 0x2c + 80019a4: 0c1b lsrs r3, r3, #16 + 80019a6: b2db uxtb r3, r3 + 80019a8: 637b str r3, [r7, #52] ; 0x34 + iter->data_size = (pb_size_t)((word0 >> 28) & 0x0F); + 80019aa: 6afb ldr r3, [r7, #44] ; 0x2c + 80019ac: 0f1b lsrs r3, r3, #28 + 80019ae: b29b uxth r3, r3 + 80019b0: f003 030f and.w r3, r3, #15 + 80019b4: b29a uxth r2, r3 + 80019b6: 687b ldr r3, [r7, #4] + 80019b8: 825a strh r2, [r3, #18] + 80019ba: e0b7 b.n 8001b2c + } + else if (format == 1) + 80019bc: f897 302b ldrb.w r3, [r7, #43] ; 0x2b + 80019c0: 2b01 cmp r3, #1 + 80019c2: d130 bne.n 8001a26 + { + /* 2-word format */ + uint32_t word1 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 1]); + 80019c4: 687b ldr r3, [r7, #4] + 80019c6: 681b ldr r3, [r3, #0] + 80019c8: f8d3 2002 ldr.w r2, [r3, #2] + 80019cc: 687b ldr r3, [r7, #4] + 80019ce: 895b ldrh r3, [r3, #10] + 80019d0: 3301 adds r3, #1 + 80019d2: 009b lsls r3, r3, #2 + 80019d4: 4413 add r3, r2 + 80019d6: 681b ldr r3, [r3, #0] + 80019d8: 60bb str r3, [r7, #8] + + iter->array_size = (pb_size_t)((word0 >> 16) & 0x0FFF); + 80019da: 6afb ldr r3, [r7, #44] ; 0x2c + 80019dc: 0c1b lsrs r3, r3, #16 + 80019de: b29b uxth r3, r3 + 80019e0: f3c3 030b ubfx r3, r3, #0, #12 + 80019e4: b29a uxth r2, r3 + 80019e6: 687b ldr r3, [r7, #4] + 80019e8: 829a strh r2, [r3, #20] + iter->tag = (pb_size_t)(iter->tag | ((word1 >> 28) << 6)); + 80019ea: 687b ldr r3, [r7, #4] + 80019ec: 8a1a ldrh r2, [r3, #16] + 80019ee: 68bb ldr r3, [r7, #8] + 80019f0: 0f1b lsrs r3, r3, #28 + 80019f2: b29b uxth r3, r3 + 80019f4: 019b lsls r3, r3, #6 + 80019f6: b29b uxth r3, r3 + 80019f8: 4313 orrs r3, r2 + 80019fa: b29a uxth r2, r3 + 80019fc: 687b ldr r3, [r7, #4] + 80019fe: 821a strh r2, [r3, #16] + size_offset = (int8_t)((word0 >> 28) & 0x0F); + 8001a00: 6afb ldr r3, [r7, #44] ; 0x2c + 8001a02: 0f1b lsrs r3, r3, #28 + 8001a04: b25b sxtb r3, r3 + 8001a06: f003 030f and.w r3, r3, #15 + 8001a0a: f887 3033 strb.w r3, [r7, #51] ; 0x33 + data_offset = word1 & 0xFFFF; + 8001a0e: 68bb ldr r3, [r7, #8] + 8001a10: b29b uxth r3, r3 + 8001a12: 637b str r3, [r7, #52] ; 0x34 + iter->data_size = (pb_size_t)((word1 >> 16) & 0x0FFF); + 8001a14: 68bb ldr r3, [r7, #8] + 8001a16: 0c1b lsrs r3, r3, #16 + 8001a18: b29b uxth r3, r3 + 8001a1a: f3c3 030b ubfx r3, r3, #0, #12 + 8001a1e: b29a uxth r2, r3 + 8001a20: 687b ldr r3, [r7, #4] + 8001a22: 825a strh r2, [r3, #18] + 8001a24: e082 b.n 8001b2c + } + else if (format == 2) + 8001a26: f897 302b ldrb.w r3, [r7, #43] ; 0x2b + 8001a2a: 2b02 cmp r3, #2 + 8001a2c: d13a bne.n 8001aa4 + { + /* 4-word format */ + uint32_t word1 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 1]); + 8001a2e: 687b ldr r3, [r7, #4] + 8001a30: 681b ldr r3, [r3, #0] + 8001a32: f8d3 2002 ldr.w r2, [r3, #2] + 8001a36: 687b ldr r3, [r7, #4] + 8001a38: 895b ldrh r3, [r3, #10] + 8001a3a: 3301 adds r3, #1 + 8001a3c: 009b lsls r3, r3, #2 + 8001a3e: 4413 add r3, r2 + 8001a40: 681b ldr r3, [r3, #0] + 8001a42: 617b str r3, [r7, #20] + uint32_t word2 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 2]); + 8001a44: 687b ldr r3, [r7, #4] + 8001a46: 681b ldr r3, [r3, #0] + 8001a48: f8d3 2002 ldr.w r2, [r3, #2] + 8001a4c: 687b ldr r3, [r7, #4] + 8001a4e: 895b ldrh r3, [r3, #10] + 8001a50: 3302 adds r3, #2 + 8001a52: 009b lsls r3, r3, #2 + 8001a54: 4413 add r3, r2 + 8001a56: 681b ldr r3, [r3, #0] + 8001a58: 613b str r3, [r7, #16] + uint32_t word3 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 3]); + 8001a5a: 687b ldr r3, [r7, #4] + 8001a5c: 681b ldr r3, [r3, #0] + 8001a5e: f8d3 2002 ldr.w r2, [r3, #2] + 8001a62: 687b ldr r3, [r7, #4] + 8001a64: 895b ldrh r3, [r3, #10] + 8001a66: 3303 adds r3, #3 + 8001a68: 009b lsls r3, r3, #2 + 8001a6a: 4413 add r3, r2 + 8001a6c: 681b ldr r3, [r3, #0] + 8001a6e: 60fb str r3, [r7, #12] + + iter->array_size = (pb_size_t)(word0 >> 16); + 8001a70: 6afb ldr r3, [r7, #44] ; 0x2c + 8001a72: 0c1b lsrs r3, r3, #16 + 8001a74: b29a uxth r2, r3 + 8001a76: 687b ldr r3, [r7, #4] + 8001a78: 829a strh r2, [r3, #20] + iter->tag = (pb_size_t)(iter->tag | ((word1 >> 8) << 6)); + 8001a7a: 687b ldr r3, [r7, #4] + 8001a7c: 8a1a ldrh r2, [r3, #16] + 8001a7e: 697b ldr r3, [r7, #20] + 8001a80: 0a1b lsrs r3, r3, #8 + 8001a82: b29b uxth r3, r3 + 8001a84: 019b lsls r3, r3, #6 + 8001a86: b29b uxth r3, r3 + 8001a88: 4313 orrs r3, r2 + 8001a8a: b29a uxth r2, r3 + 8001a8c: 687b ldr r3, [r7, #4] + 8001a8e: 821a strh r2, [r3, #16] + size_offset = (int8_t)(word1 & 0xFF); + 8001a90: 697b ldr r3, [r7, #20] + 8001a92: f887 3033 strb.w r3, [r7, #51] ; 0x33 + data_offset = word2; + 8001a96: 693b ldr r3, [r7, #16] + 8001a98: 637b str r3, [r7, #52] ; 0x34 + iter->data_size = (pb_size_t)word3; + 8001a9a: 68fb ldr r3, [r7, #12] + 8001a9c: b29a uxth r2, r3 + 8001a9e: 687b ldr r3, [r7, #4] + 8001aa0: 825a strh r2, [r3, #18] + 8001aa2: e043 b.n 8001b2c + } + else + { + /* 8-word format */ + uint32_t word1 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 1]); + 8001aa4: 687b ldr r3, [r7, #4] + 8001aa6: 681b ldr r3, [r3, #0] + 8001aa8: f8d3 2002 ldr.w r2, [r3, #2] + 8001aac: 687b ldr r3, [r7, #4] + 8001aae: 895b ldrh r3, [r3, #10] + 8001ab0: 3301 adds r3, #1 + 8001ab2: 009b lsls r3, r3, #2 + 8001ab4: 4413 add r3, r2 + 8001ab6: 681b ldr r3, [r3, #0] + 8001ab8: 627b str r3, [r7, #36] ; 0x24 + uint32_t word2 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 2]); + 8001aba: 687b ldr r3, [r7, #4] + 8001abc: 681b ldr r3, [r3, #0] + 8001abe: f8d3 2002 ldr.w r2, [r3, #2] + 8001ac2: 687b ldr r3, [r7, #4] + 8001ac4: 895b ldrh r3, [r3, #10] + 8001ac6: 3302 adds r3, #2 + 8001ac8: 009b lsls r3, r3, #2 + 8001aca: 4413 add r3, r2 + 8001acc: 681b ldr r3, [r3, #0] + 8001ace: 623b str r3, [r7, #32] + uint32_t word3 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 3]); + 8001ad0: 687b ldr r3, [r7, #4] + 8001ad2: 681b ldr r3, [r3, #0] + 8001ad4: f8d3 2002 ldr.w r2, [r3, #2] + 8001ad8: 687b ldr r3, [r7, #4] + 8001ada: 895b ldrh r3, [r3, #10] + 8001adc: 3303 adds r3, #3 + 8001ade: 009b lsls r3, r3, #2 + 8001ae0: 4413 add r3, r2 + 8001ae2: 681b ldr r3, [r3, #0] + 8001ae4: 61fb str r3, [r7, #28] + uint32_t word4 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 4]); + 8001ae6: 687b ldr r3, [r7, #4] + 8001ae8: 681b ldr r3, [r3, #0] + 8001aea: f8d3 2002 ldr.w r2, [r3, #2] + 8001aee: 687b ldr r3, [r7, #4] + 8001af0: 895b ldrh r3, [r3, #10] + 8001af2: 3304 adds r3, #4 + 8001af4: 009b lsls r3, r3, #2 + 8001af6: 4413 add r3, r2 + 8001af8: 681b ldr r3, [r3, #0] + 8001afa: 61bb str r3, [r7, #24] + + iter->array_size = (pb_size_t)word4; + 8001afc: 69bb ldr r3, [r7, #24] + 8001afe: b29a uxth r2, r3 + 8001b00: 687b ldr r3, [r7, #4] + 8001b02: 829a strh r2, [r3, #20] + iter->tag = (pb_size_t)(iter->tag | ((word1 >> 8) << 6)); + 8001b04: 687b ldr r3, [r7, #4] + 8001b06: 8a1a ldrh r2, [r3, #16] + 8001b08: 6a7b ldr r3, [r7, #36] ; 0x24 + 8001b0a: 0a1b lsrs r3, r3, #8 + 8001b0c: b29b uxth r3, r3 + 8001b0e: 019b lsls r3, r3, #6 + 8001b10: b29b uxth r3, r3 + 8001b12: 4313 orrs r3, r2 + 8001b14: b29a uxth r2, r3 + 8001b16: 687b ldr r3, [r7, #4] + 8001b18: 821a strh r2, [r3, #16] + size_offset = (int8_t)(word1 & 0xFF); + 8001b1a: 6a7b ldr r3, [r7, #36] ; 0x24 + 8001b1c: f887 3033 strb.w r3, [r7, #51] ; 0x33 + data_offset = word2; + 8001b20: 6a3b ldr r3, [r7, #32] + 8001b22: 637b str r3, [r7, #52] ; 0x34 + iter->data_size = (pb_size_t)word3; + 8001b24: 69fb ldr r3, [r7, #28] + 8001b26: b29a uxth r2, r3 + 8001b28: 687b ldr r3, [r7, #4] + 8001b2a: 825a strh r2, [r3, #18] + } + + iter->pField = (char*)iter->message + data_offset; + 8001b2c: 687b ldr r3, [r7, #4] + 8001b2e: 685a ldr r2, [r3, #4] + 8001b30: 6b7b ldr r3, [r7, #52] ; 0x34 + 8001b32: 441a add r2, r3 + 8001b34: 687b ldr r3, [r7, #4] + 8001b36: 619a str r2, [r3, #24] + + if (size_offset) + 8001b38: f997 3033 ldrsb.w r3, [r7, #51] ; 0x33 + 8001b3c: 2b00 cmp r3, #0 + 8001b3e: d008 beq.n 8001b52 + { + iter->pSize = (char*)iter->pField - size_offset; + 8001b40: 687b ldr r3, [r7, #4] + 8001b42: 699a ldr r2, [r3, #24] + 8001b44: f997 3033 ldrsb.w r3, [r7, #51] ; 0x33 + 8001b48: 425b negs r3, r3 + 8001b4a: 441a add r2, r3 + 8001b4c: 687b ldr r3, [r7, #4] + 8001b4e: 621a str r2, [r3, #32] + 8001b50: e01a b.n 8001b88 + } + else if (PB_HTYPE(iter->type) == PB_HTYPE_REPEATED && + 8001b52: 687b ldr r3, [r7, #4] + 8001b54: 7d9b ldrb r3, [r3, #22] + 8001b56: f003 0330 and.w r3, r3, #48 ; 0x30 + 8001b5a: 2b20 cmp r3, #32 + 8001b5c: d111 bne.n 8001b82 + (PB_ATYPE(iter->type) == PB_ATYPE_STATIC || + 8001b5e: 687b ldr r3, [r7, #4] + 8001b60: 7d9b ldrb r3, [r3, #22] + 8001b62: f003 03c0 and.w r3, r3, #192 ; 0xc0 + else if (PB_HTYPE(iter->type) == PB_HTYPE_REPEATED && + 8001b66: 2b00 cmp r3, #0 + 8001b68: d005 beq.n 8001b76 + PB_ATYPE(iter->type) == PB_ATYPE_POINTER)) + 8001b6a: 687b ldr r3, [r7, #4] + 8001b6c: 7d9b ldrb r3, [r3, #22] + 8001b6e: f003 03c0 and.w r3, r3, #192 ; 0xc0 + (PB_ATYPE(iter->type) == PB_ATYPE_STATIC || + 8001b72: 2b80 cmp r3, #128 ; 0x80 + 8001b74: d105 bne.n 8001b82 + { + /* Fixed count array */ + iter->pSize = &iter->array_size; + 8001b76: 687b ldr r3, [r7, #4] + 8001b78: f103 0214 add.w r2, r3, #20 + 8001b7c: 687b ldr r3, [r7, #4] + 8001b7e: 621a str r2, [r3, #32] + 8001b80: e002 b.n 8001b88 + } + else + { + iter->pSize = NULL; + 8001b82: 687b ldr r3, [r7, #4] + 8001b84: 2200 movs r2, #0 + 8001b86: 621a str r2, [r3, #32] + } + + if (PB_ATYPE(iter->type) == PB_ATYPE_POINTER && iter->pField != NULL) + 8001b88: 687b ldr r3, [r7, #4] + 8001b8a: 7d9b ldrb r3, [r3, #22] + 8001b8c: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 8001b90: 2b80 cmp r3, #128 ; 0x80 + 8001b92: d109 bne.n 8001ba8 + 8001b94: 687b ldr r3, [r7, #4] + 8001b96: 699b ldr r3, [r3, #24] + 8001b98: 2b00 cmp r3, #0 + 8001b9a: d005 beq.n 8001ba8 + { + iter->pData = *(void**)iter->pField; + 8001b9c: 687b ldr r3, [r7, #4] + 8001b9e: 699b ldr r3, [r3, #24] + 8001ba0: 681a ldr r2, [r3, #0] + 8001ba2: 687b ldr r3, [r7, #4] + 8001ba4: 61da str r2, [r3, #28] + 8001ba6: e003 b.n 8001bb0 + } + else + { + iter->pData = iter->pField; + 8001ba8: 687b ldr r3, [r7, #4] + 8001baa: 699a ldr r2, [r3, #24] + 8001bac: 687b ldr r3, [r7, #4] + 8001bae: 61da str r2, [r3, #28] + } + + if (PB_LTYPE_IS_SUBMSG(iter->type)) + 8001bb0: 687b ldr r3, [r7, #4] + 8001bb2: 7d9b ldrb r3, [r3, #22] + 8001bb4: f003 030f and.w r3, r3, #15 + 8001bb8: 2b08 cmp r3, #8 + 8001bba: d005 beq.n 8001bc8 + 8001bbc: 687b ldr r3, [r7, #4] + 8001bbe: 7d9b ldrb r3, [r3, #22] + 8001bc0: f003 030f and.w r3, r3, #15 + 8001bc4: 2b09 cmp r3, #9 + 8001bc6: d10b bne.n 8001be0 + { + iter->submsg_desc = iter->descriptor->submsg_info[iter->submessage_index]; + 8001bc8: 687b ldr r3, [r7, #4] + 8001bca: 681b ldr r3, [r3, #0] + 8001bcc: f8d3 2006 ldr.w r2, [r3, #6] + 8001bd0: 687b ldr r3, [r7, #4] + 8001bd2: 89db ldrh r3, [r3, #14] + 8001bd4: 009b lsls r3, r3, #2 + 8001bd6: 4413 add r3, r2 + 8001bd8: 681a ldr r2, [r3, #0] + 8001bda: 687b ldr r3, [r7, #4] + 8001bdc: 625a str r2, [r3, #36] ; 0x24 + 8001bde: e002 b.n 8001be6 + } + else + { + iter->submsg_desc = NULL; + 8001be0: 687b ldr r3, [r7, #4] + 8001be2: 2200 movs r2, #0 + 8001be4: 625a str r2, [r3, #36] ; 0x24 + } + + return true; + 8001be6: 2301 movs r3, #1 +} + 8001be8: 4618 mov r0, r3 + 8001bea: 373c adds r7, #60 ; 0x3c + 8001bec: 46bd mov sp, r7 + 8001bee: f85d 7b04 ldr.w r7, [sp], #4 + 8001bf2: 4770 bx lr + +08001bf4 : + +static void advance_iterator(pb_field_iter_t *iter) +{ + 8001bf4: b480 push {r7} + 8001bf6: b085 sub sp, #20 + 8001bf8: af00 add r7, sp, #0 + 8001bfa: 6078 str r0, [r7, #4] + iter->index++; + 8001bfc: 687b ldr r3, [r7, #4] + 8001bfe: 891b ldrh r3, [r3, #8] + 8001c00: 3301 adds r3, #1 + 8001c02: b29a uxth r2, r3 + 8001c04: 687b ldr r3, [r7, #4] + 8001c06: 811a strh r2, [r3, #8] + + if (iter->index >= iter->descriptor->field_count) + 8001c08: 687b ldr r3, [r7, #4] + 8001c0a: 891a ldrh r2, [r3, #8] + 8001c0c: 687b ldr r3, [r7, #4] + 8001c0e: 681b ldr r3, [r3, #0] + 8001c10: 881b ldrh r3, [r3, #0] + 8001c12: b29b uxth r3, r3 + 8001c14: 429a cmp r2, r3 + 8001c16: d30c bcc.n 8001c32 + { + /* Restart */ + iter->index = 0; + 8001c18: 687b ldr r3, [r7, #4] + 8001c1a: 2200 movs r2, #0 + 8001c1c: 811a strh r2, [r3, #8] + iter->field_info_index = 0; + 8001c1e: 687b ldr r3, [r7, #4] + 8001c20: 2200 movs r2, #0 + 8001c22: 815a strh r2, [r3, #10] + iter->submessage_index = 0; + 8001c24: 687b ldr r3, [r7, #4] + 8001c26: 2200 movs r2, #0 + 8001c28: 81da strh r2, [r3, #14] + iter->required_field_index = 0; + 8001c2a: 687b ldr r3, [r7, #4] + 8001c2c: 2200 movs r2, #0 + 8001c2e: 819a strh r2, [r3, #12] + if (PB_LTYPE_IS_SUBMSG(prev_type)) + { + iter->submessage_index++; + } + } +} + 8001c30: e035 b.n 8001c9e + uint32_t prev_descriptor = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index]); + 8001c32: 687b ldr r3, [r7, #4] + 8001c34: 681b ldr r3, [r3, #0] + 8001c36: f8d3 2002 ldr.w r2, [r3, #2] + 8001c3a: 687b ldr r3, [r7, #4] + 8001c3c: 895b ldrh r3, [r3, #10] + 8001c3e: 009b lsls r3, r3, #2 + 8001c40: 4413 add r3, r2 + 8001c42: 681b ldr r3, [r3, #0] + 8001c44: 60fb str r3, [r7, #12] + pb_type_t prev_type = (prev_descriptor >> 8) & 0xFF; + 8001c46: 68fb ldr r3, [r7, #12] + 8001c48: 0a1b lsrs r3, r3, #8 + 8001c4a: 72fb strb r3, [r7, #11] + pb_size_t descriptor_len = (pb_size_t)(1 << (prev_descriptor & 3)); + 8001c4c: 68fb ldr r3, [r7, #12] + 8001c4e: f003 0303 and.w r3, r3, #3 + 8001c52: 2201 movs r2, #1 + 8001c54: fa02 f303 lsl.w r3, r2, r3 + 8001c58: 813b strh r3, [r7, #8] + iter->field_info_index = (pb_size_t)(iter->field_info_index + descriptor_len); + 8001c5a: 687b ldr r3, [r7, #4] + 8001c5c: 895a ldrh r2, [r3, #10] + 8001c5e: 893b ldrh r3, [r7, #8] + 8001c60: 4413 add r3, r2 + 8001c62: b29a uxth r2, r3 + 8001c64: 687b ldr r3, [r7, #4] + 8001c66: 815a strh r2, [r3, #10] + if (PB_HTYPE(prev_type) == PB_HTYPE_REQUIRED) + 8001c68: 7afb ldrb r3, [r7, #11] + 8001c6a: f003 0330 and.w r3, r3, #48 ; 0x30 + 8001c6e: 2b00 cmp r3, #0 + 8001c70: d105 bne.n 8001c7e + iter->required_field_index++; + 8001c72: 687b ldr r3, [r7, #4] + 8001c74: 899b ldrh r3, [r3, #12] + 8001c76: 3301 adds r3, #1 + 8001c78: b29a uxth r2, r3 + 8001c7a: 687b ldr r3, [r7, #4] + 8001c7c: 819a strh r2, [r3, #12] + if (PB_LTYPE_IS_SUBMSG(prev_type)) + 8001c7e: 7afb ldrb r3, [r7, #11] + 8001c80: f003 030f and.w r3, r3, #15 + 8001c84: 2b08 cmp r3, #8 + 8001c86: d004 beq.n 8001c92 + 8001c88: 7afb ldrb r3, [r7, #11] + 8001c8a: f003 030f and.w r3, r3, #15 + 8001c8e: 2b09 cmp r3, #9 + 8001c90: d105 bne.n 8001c9e + iter->submessage_index++; + 8001c92: 687b ldr r3, [r7, #4] + 8001c94: 89db ldrh r3, [r3, #14] + 8001c96: 3301 adds r3, #1 + 8001c98: b29a uxth r2, r3 + 8001c9a: 687b ldr r3, [r7, #4] + 8001c9c: 81da strh r2, [r3, #14] +} + 8001c9e: bf00 nop + 8001ca0: 3714 adds r7, #20 + 8001ca2: 46bd mov sp, r7 + 8001ca4: f85d 7b04 ldr.w r7, [sp], #4 + 8001ca8: 4770 bx lr + +08001caa : + +bool pb_field_iter_begin(pb_field_iter_t *iter, const pb_msgdesc_t *desc, void *message) +{ + 8001caa: b580 push {r7, lr} + 8001cac: b084 sub sp, #16 + 8001cae: af00 add r7, sp, #0 + 8001cb0: 60f8 str r0, [r7, #12] + 8001cb2: 60b9 str r1, [r7, #8] + 8001cb4: 607a str r2, [r7, #4] + memset(iter, 0, sizeof(*iter)); + 8001cb6: 2228 movs r2, #40 ; 0x28 + 8001cb8: 2100 movs r1, #0 + 8001cba: 68f8 ldr r0, [r7, #12] + 8001cbc: f006 fe7e bl 80089bc + + iter->descriptor = desc; + 8001cc0: 68fb ldr r3, [r7, #12] + 8001cc2: 68ba ldr r2, [r7, #8] + 8001cc4: 601a str r2, [r3, #0] + iter->message = message; + 8001cc6: 68fb ldr r3, [r7, #12] + 8001cc8: 687a ldr r2, [r7, #4] + 8001cca: 605a str r2, [r3, #4] + + return load_descriptor_values(iter); + 8001ccc: 68f8 ldr r0, [r7, #12] + 8001cce: f7ff fe2f bl 8001930 + 8001cd2: 4603 mov r3, r0 +} + 8001cd4: 4618 mov r0, r3 + 8001cd6: 3710 adds r7, #16 + 8001cd8: 46bd mov sp, r7 + 8001cda: bd80 pop {r7, pc} + +08001cdc : + +bool pb_field_iter_begin_extension(pb_field_iter_t *iter, pb_extension_t *extension) +{ + 8001cdc: b580 push {r7, lr} + 8001cde: b086 sub sp, #24 + 8001ce0: af00 add r7, sp, #0 + 8001ce2: 6078 str r0, [r7, #4] + 8001ce4: 6039 str r1, [r7, #0] + const pb_msgdesc_t *msg = (const pb_msgdesc_t*)extension->type->arg; + 8001ce6: 683b ldr r3, [r7, #0] + 8001ce8: 681b ldr r3, [r3, #0] + 8001cea: 689b ldr r3, [r3, #8] + 8001cec: 613b str r3, [r7, #16] + bool status; + + uint32_t word0 = PB_PROGMEM_READU32(msg->field_info[0]); + 8001cee: 693b ldr r3, [r7, #16] + 8001cf0: f8d3 3002 ldr.w r3, [r3, #2] + 8001cf4: 681b ldr r3, [r3, #0] + 8001cf6: 60fb str r3, [r7, #12] + if (PB_ATYPE(word0 >> 8) == PB_ATYPE_POINTER) + 8001cf8: 68fb ldr r3, [r7, #12] + 8001cfa: 0a1b lsrs r3, r3, #8 + 8001cfc: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 8001d00: 2b80 cmp r3, #128 ; 0x80 + 8001d02: d109 bne.n 8001d18 + { + /* For pointer extensions, the pointer is stored directly + * in the extension structure. This avoids having an extra + * indirection. */ + status = pb_field_iter_begin(iter, msg, &extension->dest); + 8001d04: 683b ldr r3, [r7, #0] + 8001d06: 3304 adds r3, #4 + 8001d08: 461a mov r2, r3 + 8001d0a: 6939 ldr r1, [r7, #16] + 8001d0c: 6878 ldr r0, [r7, #4] + 8001d0e: f7ff ffcc bl 8001caa + 8001d12: 4603 mov r3, r0 + 8001d14: 75fb strb r3, [r7, #23] + 8001d16: e008 b.n 8001d2a + } + else + { + status = pb_field_iter_begin(iter, msg, extension->dest); + 8001d18: 683b ldr r3, [r7, #0] + 8001d1a: 685b ldr r3, [r3, #4] + 8001d1c: 461a mov r2, r3 + 8001d1e: 6939 ldr r1, [r7, #16] + 8001d20: 6878 ldr r0, [r7, #4] + 8001d22: f7ff ffc2 bl 8001caa + 8001d26: 4603 mov r3, r0 + 8001d28: 75fb strb r3, [r7, #23] + } + + iter->pSize = &extension->found; + 8001d2a: 683b ldr r3, [r7, #0] + 8001d2c: f103 020c add.w r2, r3, #12 + 8001d30: 687b ldr r3, [r7, #4] + 8001d32: 621a str r2, [r3, #32] + return status; + 8001d34: 7dfb ldrb r3, [r7, #23] +} + 8001d36: 4618 mov r0, r3 + 8001d38: 3718 adds r7, #24 + 8001d3a: 46bd mov sp, r7 + 8001d3c: bd80 pop {r7, pc} + +08001d3e : + +bool pb_field_iter_next(pb_field_iter_t *iter) +{ + 8001d3e: b580 push {r7, lr} + 8001d40: b082 sub sp, #8 + 8001d42: af00 add r7, sp, #0 + 8001d44: 6078 str r0, [r7, #4] + advance_iterator(iter); + 8001d46: 6878 ldr r0, [r7, #4] + 8001d48: f7ff ff54 bl 8001bf4 + (void)load_descriptor_values(iter); + 8001d4c: 6878 ldr r0, [r7, #4] + 8001d4e: f7ff fdef bl 8001930 + return iter->index != 0; + 8001d52: 687b ldr r3, [r7, #4] + 8001d54: 891b ldrh r3, [r3, #8] + 8001d56: 2b00 cmp r3, #0 + 8001d58: bf14 ite ne + 8001d5a: 2301 movne r3, #1 + 8001d5c: 2300 moveq r3, #0 + 8001d5e: b2db uxtb r3, r3 +} + 8001d60: 4618 mov r0, r3 + 8001d62: 3708 adds r7, #8 + 8001d64: 46bd mov sp, r7 + 8001d66: bd80 pop {r7, pc} + +08001d68 : + +bool pb_field_iter_find(pb_field_iter_t *iter, uint32_t tag) +{ + 8001d68: b580 push {r7, lr} + 8001d6a: b084 sub sp, #16 + 8001d6c: af00 add r7, sp, #0 + 8001d6e: 6078 str r0, [r7, #4] + 8001d70: 6039 str r1, [r7, #0] + if (iter->tag == tag) + 8001d72: 687b ldr r3, [r7, #4] + 8001d74: 8a1b ldrh r3, [r3, #16] + 8001d76: 461a mov r2, r3 + 8001d78: 683b ldr r3, [r7, #0] + 8001d7a: 4293 cmp r3, r2 + 8001d7c: d101 bne.n 8001d82 + { + return true; /* Nothing to do, correct field already. */ + 8001d7e: 2301 movs r3, #1 + 8001d80: e031 b.n 8001de6 + } + else + { + pb_size_t start = iter->index; + 8001d82: 687b ldr r3, [r7, #4] + 8001d84: 891b ldrh r3, [r3, #8] + 8001d86: 81fb strh r3, [r7, #14] + uint32_t fieldinfo; + + do + { + /* Advance iterator but don't load values yet */ + advance_iterator(iter); + 8001d88: 6878 ldr r0, [r7, #4] + 8001d8a: f7ff ff33 bl 8001bf4 + + /* Do fast check for tag number match */ + fieldinfo = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index]); + 8001d8e: 687b ldr r3, [r7, #4] + 8001d90: 681b ldr r3, [r3, #0] + 8001d92: f8d3 2002 ldr.w r2, [r3, #2] + 8001d96: 687b ldr r3, [r7, #4] + 8001d98: 895b ldrh r3, [r3, #10] + 8001d9a: 009b lsls r3, r3, #2 + 8001d9c: 4413 add r3, r2 + 8001d9e: 681b ldr r3, [r3, #0] + 8001da0: 60bb str r3, [r7, #8] + + if (((fieldinfo >> 2) & 0x3F) == (tag & 0x3F)) + 8001da2: 68bb ldr r3, [r7, #8] + 8001da4: 089a lsrs r2, r3, #2 + 8001da6: 683b ldr r3, [r7, #0] + 8001da8: 4053 eors r3, r2 + 8001daa: f003 033f and.w r3, r3, #63 ; 0x3f + 8001dae: 2b00 cmp r3, #0 + 8001db0: d110 bne.n 8001dd4 + { + /* Good candidate, check further */ + (void)load_descriptor_values(iter); + 8001db2: 6878 ldr r0, [r7, #4] + 8001db4: f7ff fdbc bl 8001930 + + if (iter->tag == tag && + 8001db8: 687b ldr r3, [r7, #4] + 8001dba: 8a1b ldrh r3, [r3, #16] + 8001dbc: 461a mov r2, r3 + 8001dbe: 683b ldr r3, [r7, #0] + 8001dc0: 4293 cmp r3, r2 + 8001dc2: d107 bne.n 8001dd4 + PB_LTYPE(iter->type) != PB_LTYPE_EXTENSION) + 8001dc4: 687b ldr r3, [r7, #4] + 8001dc6: 7d9b ldrb r3, [r3, #22] + 8001dc8: f003 030f and.w r3, r3, #15 + if (iter->tag == tag && + 8001dcc: 2b0a cmp r3, #10 + 8001dce: d001 beq.n 8001dd4 + { + /* Found it */ + return true; + 8001dd0: 2301 movs r3, #1 + 8001dd2: e008 b.n 8001de6 + } + } + } while (iter->index != start); + 8001dd4: 687b ldr r3, [r7, #4] + 8001dd6: 891b ldrh r3, [r3, #8] + 8001dd8: 89fa ldrh r2, [r7, #14] + 8001dda: 429a cmp r2, r3 + 8001ddc: d1d4 bne.n 8001d88 + + /* Searched all the way back to start, and found nothing. */ + (void)load_descriptor_values(iter); + 8001dde: 6878 ldr r0, [r7, #4] + 8001de0: f7ff fda6 bl 8001930 + return false; + 8001de4: 2300 movs r3, #0 + } +} + 8001de6: 4618 mov r0, r3 + 8001de8: 3710 adds r7, #16 + 8001dea: 46bd mov sp, r7 + 8001dec: bd80 pop {r7, pc} + +08001dee : + +static void *pb_const_cast(const void *p) +{ + 8001dee: b480 push {r7} + 8001df0: b085 sub sp, #20 + 8001df2: af00 add r7, sp, #0 + 8001df4: 6078 str r0, [r7, #4] + * to avoid spurious compiler warnings. */ + union { + void *p1; + const void *p2; + } t; + t.p2 = p; + 8001df6: 687b ldr r3, [r7, #4] + 8001df8: 60fb str r3, [r7, #12] + return t.p1; + 8001dfa: 68fb ldr r3, [r7, #12] +} + 8001dfc: 4618 mov r0, r3 + 8001dfe: 3714 adds r7, #20 + 8001e00: 46bd mov sp, r7 + 8001e02: f85d 7b04 ldr.w r7, [sp], #4 + 8001e06: 4770 bx lr + +08001e08 : + +bool pb_field_iter_begin_const(pb_field_iter_t *iter, const pb_msgdesc_t *desc, const void *message) +{ + 8001e08: b580 push {r7, lr} + 8001e0a: b084 sub sp, #16 + 8001e0c: af00 add r7, sp, #0 + 8001e0e: 60f8 str r0, [r7, #12] + 8001e10: 60b9 str r1, [r7, #8] + 8001e12: 607a str r2, [r7, #4] + return pb_field_iter_begin(iter, desc, pb_const_cast(message)); + 8001e14: 6878 ldr r0, [r7, #4] + 8001e16: f7ff ffea bl 8001dee + 8001e1a: 4603 mov r3, r0 + 8001e1c: 461a mov r2, r3 + 8001e1e: 68b9 ldr r1, [r7, #8] + 8001e20: 68f8 ldr r0, [r7, #12] + 8001e22: f7ff ff42 bl 8001caa + 8001e26: 4603 mov r3, r0 +} + 8001e28: 4618 mov r0, r3 + 8001e2a: 3710 adds r7, #16 + 8001e2c: 46bd mov sp, r7 + 8001e2e: bd80 pop {r7, pc} + +08001e30 : + +bool pb_field_iter_begin_extension_const(pb_field_iter_t *iter, const pb_extension_t *extension) +{ + 8001e30: b580 push {r7, lr} + 8001e32: b082 sub sp, #8 + 8001e34: af00 add r7, sp, #0 + 8001e36: 6078 str r0, [r7, #4] + 8001e38: 6039 str r1, [r7, #0] + return pb_field_iter_begin_extension(iter, (pb_extension_t*)pb_const_cast(extension)); + 8001e3a: 6838 ldr r0, [r7, #0] + 8001e3c: f7ff ffd7 bl 8001dee + 8001e40: 4603 mov r3, r0 + 8001e42: 4619 mov r1, r3 + 8001e44: 6878 ldr r0, [r7, #4] + 8001e46: f7ff ff49 bl 8001cdc + 8001e4a: 4603 mov r3, r0 +} + 8001e4c: 4618 mov r0, r3 + 8001e4e: 3708 adds r7, #8 + 8001e50: 46bd mov sp, r7 + 8001e52: bd80 pop {r7, pc} + +08001e54 : +/******************************* + * pb_istream_t implementation * + *******************************/ + +static bool checkreturn buf_read(pb_istream_t *stream, pb_byte_t *buf, size_t count) +{ + 8001e54: b480 push {r7} + 8001e56: b087 sub sp, #28 + 8001e58: af00 add r7, sp, #0 + 8001e5a: 60f8 str r0, [r7, #12] + 8001e5c: 60b9 str r1, [r7, #8] + 8001e5e: 607a str r2, [r7, #4] + size_t i; + const pb_byte_t *source = (const pb_byte_t*)stream->state; + 8001e60: 68fb ldr r3, [r7, #12] + 8001e62: 685b ldr r3, [r3, #4] + 8001e64: 613b str r3, [r7, #16] + stream->state = (pb_byte_t*)stream->state + count; + 8001e66: 68fb ldr r3, [r7, #12] + 8001e68: 685a ldr r2, [r3, #4] + 8001e6a: 687b ldr r3, [r7, #4] + 8001e6c: 441a add r2, r3 + 8001e6e: 68fb ldr r3, [r7, #12] + 8001e70: 605a str r2, [r3, #4] + + if (buf != NULL) + 8001e72: 68bb ldr r3, [r7, #8] + 8001e74: 2b00 cmp r3, #0 + 8001e76: d011 beq.n 8001e9c + { + for (i = 0; i < count; i++) + 8001e78: 2300 movs r3, #0 + 8001e7a: 617b str r3, [r7, #20] + 8001e7c: e00a b.n 8001e94 + buf[i] = source[i]; + 8001e7e: 693a ldr r2, [r7, #16] + 8001e80: 697b ldr r3, [r7, #20] + 8001e82: 441a add r2, r3 + 8001e84: 68b9 ldr r1, [r7, #8] + 8001e86: 697b ldr r3, [r7, #20] + 8001e88: 440b add r3, r1 + 8001e8a: 7812 ldrb r2, [r2, #0] + 8001e8c: 701a strb r2, [r3, #0] + for (i = 0; i < count; i++) + 8001e8e: 697b ldr r3, [r7, #20] + 8001e90: 3301 adds r3, #1 + 8001e92: 617b str r3, [r7, #20] + 8001e94: 697a ldr r2, [r7, #20] + 8001e96: 687b ldr r3, [r7, #4] + 8001e98: 429a cmp r2, r3 + 8001e9a: d3f0 bcc.n 8001e7e + } + + return true; + 8001e9c: 2301 movs r3, #1 +} + 8001e9e: 4618 mov r0, r3 + 8001ea0: 371c adds r7, #28 + 8001ea2: 46bd mov sp, r7 + 8001ea4: f85d 7b04 ldr.w r7, [sp], #4 + 8001ea8: 4770 bx lr + ... + +08001eac : + +bool checkreturn pb_read(pb_istream_t *stream, pb_byte_t *buf, size_t count) +{ + 8001eac: b580 push {r7, lr} + 8001eae: b088 sub sp, #32 + 8001eb0: af00 add r7, sp, #0 + 8001eb2: 60f8 str r0, [r7, #12] + 8001eb4: 60b9 str r1, [r7, #8] + 8001eb6: 607a str r2, [r7, #4] + if (count == 0) + 8001eb8: 687b ldr r3, [r7, #4] + 8001eba: 2b00 cmp r3, #0 + 8001ebc: d101 bne.n 8001ec2 + return true; + 8001ebe: 2301 movs r3, #1 + 8001ec0: e056 b.n 8001f70 + +#ifndef PB_BUFFER_ONLY + if (buf == NULL && stream->callback != buf_read) + 8001ec2: 68bb ldr r3, [r7, #8] + 8001ec4: 2b00 cmp r3, #0 + 8001ec6: d123 bne.n 8001f10 + 8001ec8: 68fb ldr r3, [r7, #12] + 8001eca: 681b ldr r3, [r3, #0] + 8001ecc: 4a2a ldr r2, [pc, #168] ; (8001f78 ) + 8001ece: 4293 cmp r3, r2 + 8001ed0: d01e beq.n 8001f10 + { + /* Skip input bytes */ + pb_byte_t tmp[16]; + while (count > 16) + 8001ed2: e011 b.n 8001ef8 + { + if (!pb_read(stream, tmp, 16)) + 8001ed4: f107 0310 add.w r3, r7, #16 + 8001ed8: 2210 movs r2, #16 + 8001eda: 4619 mov r1, r3 + 8001edc: 68f8 ldr r0, [r7, #12] + 8001ede: f7ff ffe5 bl 8001eac + 8001ee2: 4603 mov r3, r0 + 8001ee4: f083 0301 eor.w r3, r3, #1 + 8001ee8: b2db uxtb r3, r3 + 8001eea: 2b00 cmp r3, #0 + 8001eec: d001 beq.n 8001ef2 + return false; + 8001eee: 2300 movs r3, #0 + 8001ef0: e03e b.n 8001f70 + + count -= 16; + 8001ef2: 687b ldr r3, [r7, #4] + 8001ef4: 3b10 subs r3, #16 + 8001ef6: 607b str r3, [r7, #4] + while (count > 16) + 8001ef8: 687b ldr r3, [r7, #4] + 8001efa: 2b10 cmp r3, #16 + 8001efc: d8ea bhi.n 8001ed4 + } + + return pb_read(stream, tmp, count); + 8001efe: f107 0310 add.w r3, r7, #16 + 8001f02: 687a ldr r2, [r7, #4] + 8001f04: 4619 mov r1, r3 + 8001f06: 68f8 ldr r0, [r7, #12] + 8001f08: f7ff ffd0 bl 8001eac + 8001f0c: 4603 mov r3, r0 + 8001f0e: e02f b.n 8001f70 + } +#endif + + if (stream->bytes_left < count) + 8001f10: 68fb ldr r3, [r7, #12] + 8001f12: 689b ldr r3, [r3, #8] + 8001f14: 687a ldr r2, [r7, #4] + 8001f16: 429a cmp r2, r3 + 8001f18: d90b bls.n 8001f32 + PB_RETURN_ERROR(stream, "end-of-stream"); + 8001f1a: 68fb ldr r3, [r7, #12] + 8001f1c: 68db ldr r3, [r3, #12] + 8001f1e: 2b00 cmp r3, #0 + 8001f20: d002 beq.n 8001f28 + 8001f22: 68fb ldr r3, [r7, #12] + 8001f24: 68db ldr r3, [r3, #12] + 8001f26: e000 b.n 8001f2a + 8001f28: 4b14 ldr r3, [pc, #80] ; (8001f7c ) + 8001f2a: 68fa ldr r2, [r7, #12] + 8001f2c: 60d3 str r3, [r2, #12] + 8001f2e: 2300 movs r3, #0 + 8001f30: e01e b.n 8001f70 + +#ifndef PB_BUFFER_ONLY + if (!stream->callback(stream, buf, count)) + 8001f32: 68fb ldr r3, [r7, #12] + 8001f34: 681b ldr r3, [r3, #0] + 8001f36: 687a ldr r2, [r7, #4] + 8001f38: 68b9 ldr r1, [r7, #8] + 8001f3a: 68f8 ldr r0, [r7, #12] + 8001f3c: 4798 blx r3 + 8001f3e: 4603 mov r3, r0 + 8001f40: f083 0301 eor.w r3, r3, #1 + 8001f44: b2db uxtb r3, r3 + 8001f46: 2b00 cmp r3, #0 + 8001f48: d00b beq.n 8001f62 + PB_RETURN_ERROR(stream, "io error"); + 8001f4a: 68fb ldr r3, [r7, #12] + 8001f4c: 68db ldr r3, [r3, #12] + 8001f4e: 2b00 cmp r3, #0 + 8001f50: d002 beq.n 8001f58 + 8001f52: 68fb ldr r3, [r7, #12] + 8001f54: 68db ldr r3, [r3, #12] + 8001f56: e000 b.n 8001f5a + 8001f58: 4b09 ldr r3, [pc, #36] ; (8001f80 ) + 8001f5a: 68fa ldr r2, [r7, #12] + 8001f5c: 60d3 str r3, [r2, #12] + 8001f5e: 2300 movs r3, #0 + 8001f60: e006 b.n 8001f70 +#else + if (!buf_read(stream, buf, count)) + return false; +#endif + + stream->bytes_left -= count; + 8001f62: 68fb ldr r3, [r7, #12] + 8001f64: 689a ldr r2, [r3, #8] + 8001f66: 687b ldr r3, [r7, #4] + 8001f68: 1ad2 subs r2, r2, r3 + 8001f6a: 68fb ldr r3, [r7, #12] + 8001f6c: 609a str r2, [r3, #8] + return true; + 8001f6e: 2301 movs r3, #1 +} + 8001f70: 4618 mov r0, r3 + 8001f72: 3720 adds r7, #32 + 8001f74: 46bd mov sp, r7 + 8001f76: bd80 pop {r7, pc} + 8001f78: 08001e55 .word 0x08001e55 + 8001f7c: 080089e4 .word 0x080089e4 + 8001f80: 080089f4 .word 0x080089f4 + +08001f84 : + +/* Read a single byte from input stream. buf may not be NULL. + * This is an optimization for the varint decoding. */ +static bool checkreturn pb_readbyte(pb_istream_t *stream, pb_byte_t *buf) +{ + 8001f84: b580 push {r7, lr} + 8001f86: b082 sub sp, #8 + 8001f88: af00 add r7, sp, #0 + 8001f8a: 6078 str r0, [r7, #4] + 8001f8c: 6039 str r1, [r7, #0] + if (stream->bytes_left == 0) + 8001f8e: 687b ldr r3, [r7, #4] + 8001f90: 689b ldr r3, [r3, #8] + 8001f92: 2b00 cmp r3, #0 + 8001f94: d10b bne.n 8001fae + PB_RETURN_ERROR(stream, "end-of-stream"); + 8001f96: 687b ldr r3, [r7, #4] + 8001f98: 68db ldr r3, [r3, #12] + 8001f9a: 2b00 cmp r3, #0 + 8001f9c: d002 beq.n 8001fa4 + 8001f9e: 687b ldr r3, [r7, #4] + 8001fa0: 68db ldr r3, [r3, #12] + 8001fa2: e000 b.n 8001fa6 + 8001fa4: 4b13 ldr r3, [pc, #76] ; (8001ff4 ) + 8001fa6: 687a ldr r2, [r7, #4] + 8001fa8: 60d3 str r3, [r2, #12] + 8001faa: 2300 movs r3, #0 + 8001fac: e01d b.n 8001fea + +#ifndef PB_BUFFER_ONLY + if (!stream->callback(stream, buf, 1)) + 8001fae: 687b ldr r3, [r7, #4] + 8001fb0: 681b ldr r3, [r3, #0] + 8001fb2: 2201 movs r2, #1 + 8001fb4: 6839 ldr r1, [r7, #0] + 8001fb6: 6878 ldr r0, [r7, #4] + 8001fb8: 4798 blx r3 + 8001fba: 4603 mov r3, r0 + 8001fbc: f083 0301 eor.w r3, r3, #1 + 8001fc0: b2db uxtb r3, r3 + 8001fc2: 2b00 cmp r3, #0 + 8001fc4: d00b beq.n 8001fde + PB_RETURN_ERROR(stream, "io error"); + 8001fc6: 687b ldr r3, [r7, #4] + 8001fc8: 68db ldr r3, [r3, #12] + 8001fca: 2b00 cmp r3, #0 + 8001fcc: d002 beq.n 8001fd4 + 8001fce: 687b ldr r3, [r7, #4] + 8001fd0: 68db ldr r3, [r3, #12] + 8001fd2: e000 b.n 8001fd6 + 8001fd4: 4b08 ldr r3, [pc, #32] ; (8001ff8 ) + 8001fd6: 687a ldr r2, [r7, #4] + 8001fd8: 60d3 str r3, [r2, #12] + 8001fda: 2300 movs r3, #0 + 8001fdc: e005 b.n 8001fea +#else + *buf = *(const pb_byte_t*)stream->state; + stream->state = (pb_byte_t*)stream->state + 1; +#endif + + stream->bytes_left--; + 8001fde: 687b ldr r3, [r7, #4] + 8001fe0: 689b ldr r3, [r3, #8] + 8001fe2: 1e5a subs r2, r3, #1 + 8001fe4: 687b ldr r3, [r7, #4] + 8001fe6: 609a str r2, [r3, #8] + + return true; + 8001fe8: 2301 movs r3, #1 +} + 8001fea: 4618 mov r0, r3 + 8001fec: 3708 adds r7, #8 + 8001fee: 46bd mov sp, r7 + 8001ff0: bd80 pop {r7, pc} + 8001ff2: bf00 nop + 8001ff4: 080089e4 .word 0x080089e4 + 8001ff8: 080089f4 .word 0x080089f4 + +08001ffc : + +pb_istream_t pb_istream_from_buffer(const pb_byte_t *buf, size_t bufsize) +{ + 8001ffc: b490 push {r4, r7} + 8001ffe: b08a sub sp, #40 ; 0x28 + 8002000: af00 add r7, sp, #0 + 8002002: 60f8 str r0, [r7, #12] + 8002004: 60b9 str r1, [r7, #8] + 8002006: 607a str r2, [r7, #4] + const void *c_state; + } state; +#ifdef PB_BUFFER_ONLY + stream.callback = NULL; +#else + stream.callback = &buf_read; + 8002008: 4b0a ldr r3, [pc, #40] ; (8002034 ) + 800200a: 61bb str r3, [r7, #24] +#endif + state.c_state = buf; + 800200c: 68bb ldr r3, [r7, #8] + 800200e: 617b str r3, [r7, #20] + stream.state = state.state; + 8002010: 697b ldr r3, [r7, #20] + 8002012: 61fb str r3, [r7, #28] + stream.bytes_left = bufsize; + 8002014: 687b ldr r3, [r7, #4] + 8002016: 623b str r3, [r7, #32] +#ifndef PB_NO_ERRMSG + stream.errmsg = NULL; + 8002018: 2300 movs r3, #0 + 800201a: 627b str r3, [r7, #36] ; 0x24 +#endif + return stream; + 800201c: 68fb ldr r3, [r7, #12] + 800201e: 461c mov r4, r3 + 8002020: f107 0318 add.w r3, r7, #24 + 8002024: cb0f ldmia r3, {r0, r1, r2, r3} + 8002026: e884 000f stmia.w r4, {r0, r1, r2, r3} +} + 800202a: 68f8 ldr r0, [r7, #12] + 800202c: 3728 adds r7, #40 ; 0x28 + 800202e: 46bd mov sp, r7 + 8002030: bc90 pop {r4, r7} + 8002032: 4770 bx lr + 8002034: 08001e55 .word 0x08001e55 + +08002038 : +/******************** + * Helper functions * + ********************/ + +static bool checkreturn pb_decode_varint32_eof(pb_istream_t *stream, uint32_t *dest, bool *eof) +{ + 8002038: b580 push {r7, lr} + 800203a: b088 sub sp, #32 + 800203c: af00 add r7, sp, #0 + 800203e: 60f8 str r0, [r7, #12] + 8002040: 60b9 str r1, [r7, #8] + 8002042: 607a str r2, [r7, #4] + pb_byte_t byte; + uint32_t result; + + if (!pb_readbyte(stream, &byte)) + 8002044: f107 0316 add.w r3, r7, #22 + 8002048: 4619 mov r1, r3 + 800204a: 68f8 ldr r0, [r7, #12] + 800204c: f7ff ff9a bl 8001f84 + 8002050: 4603 mov r3, r0 + 8002052: f083 0301 eor.w r3, r3, #1 + 8002056: b2db uxtb r3, r3 + 8002058: 2b00 cmp r3, #0 + 800205a: d00b beq.n 8002074 + { + if (stream->bytes_left == 0) + 800205c: 68fb ldr r3, [r7, #12] + 800205e: 689b ldr r3, [r3, #8] + 8002060: 2b00 cmp r3, #0 + 8002062: d105 bne.n 8002070 + { + if (eof) + 8002064: 687b ldr r3, [r7, #4] + 8002066: 2b00 cmp r3, #0 + 8002068: d002 beq.n 8002070 + { + *eof = true; + 800206a: 687b ldr r3, [r7, #4] + 800206c: 2201 movs r2, #1 + 800206e: 701a strb r2, [r3, #0] + } + } + + return false; + 8002070: 2300 movs r3, #0 + 8002072: e064 b.n 800213e + } + + if ((byte & 0x80) == 0) + 8002074: 7dbb ldrb r3, [r7, #22] + 8002076: b25b sxtb r3, r3 + 8002078: 2b00 cmp r3, #0 + 800207a: db02 blt.n 8002082 + { + /* Quick case, 1 byte value */ + result = byte; + 800207c: 7dbb ldrb r3, [r7, #22] + 800207e: 61fb str r3, [r7, #28] + 8002080: e059 b.n 8002136 + } + else + { + /* Multibyte case */ + uint_fast8_t bitpos = 7; + 8002082: 2307 movs r3, #7 + 8002084: 61bb str r3, [r7, #24] + result = byte & 0x7F; + 8002086: 7dbb ldrb r3, [r7, #22] + 8002088: f003 037f and.w r3, r3, #127 ; 0x7f + 800208c: 61fb str r3, [r7, #28] + + do + { + if (!pb_readbyte(stream, &byte)) + 800208e: f107 0316 add.w r3, r7, #22 + 8002092: 4619 mov r1, r3 + 8002094: 68f8 ldr r0, [r7, #12] + 8002096: f7ff ff75 bl 8001f84 + 800209a: 4603 mov r3, r0 + 800209c: f083 0301 eor.w r3, r3, #1 + 80020a0: b2db uxtb r3, r3 + 80020a2: 2b00 cmp r3, #0 + 80020a4: d001 beq.n 80020aa + return false; + 80020a6: 2300 movs r3, #0 + 80020a8: e049 b.n 800213e + + if (bitpos >= 32) + 80020aa: 69bb ldr r3, [r7, #24] + 80020ac: 2b1f cmp r3, #31 + 80020ae: d91e bls.n 80020ee + { + /* Note: The varint could have trailing 0x80 bytes, or 0xFF for negative. */ + uint8_t sign_extension = (bitpos < 63) ? 0xFF : 0x01; + 80020b0: 69bb ldr r3, [r7, #24] + 80020b2: 2b3e cmp r3, #62 ; 0x3e + 80020b4: d801 bhi.n 80020ba + 80020b6: 23ff movs r3, #255 ; 0xff + 80020b8: e000 b.n 80020bc + 80020ba: 2301 movs r3, #1 + 80020bc: 75fb strb r3, [r7, #23] + + if ((byte & 0x7F) != 0x00 && ((result >> 31) == 0 || byte != sign_extension)) + 80020be: 7dbb ldrb r3, [r7, #22] + 80020c0: f003 037f and.w r3, r3, #127 ; 0x7f + 80020c4: 2b00 cmp r3, #0 + 80020c6: d01b beq.n 8002100 + 80020c8: 69fb ldr r3, [r7, #28] + 80020ca: 2b00 cmp r3, #0 + 80020cc: da03 bge.n 80020d6 + 80020ce: 7dbb ldrb r3, [r7, #22] + 80020d0: 7dfa ldrb r2, [r7, #23] + 80020d2: 429a cmp r2, r3 + 80020d4: d014 beq.n 8002100 + { + PB_RETURN_ERROR(stream, "varint overflow"); + 80020d6: 68fb ldr r3, [r7, #12] + 80020d8: 68db ldr r3, [r3, #12] + 80020da: 2b00 cmp r3, #0 + 80020dc: d002 beq.n 80020e4 + 80020de: 68fb ldr r3, [r7, #12] + 80020e0: 68db ldr r3, [r3, #12] + 80020e2: e000 b.n 80020e6 + 80020e4: 4b18 ldr r3, [pc, #96] ; (8002148 ) + 80020e6: 68fa ldr r2, [r7, #12] + 80020e8: 60d3 str r3, [r2, #12] + 80020ea: 2300 movs r3, #0 + 80020ec: e027 b.n 800213e + } + } + else + { + result |= (uint32_t)(byte & 0x7F) << bitpos; + 80020ee: 7dbb ldrb r3, [r7, #22] + 80020f0: f003 027f and.w r2, r3, #127 ; 0x7f + 80020f4: 69bb ldr r3, [r7, #24] + 80020f6: fa02 f303 lsl.w r3, r2, r3 + 80020fa: 69fa ldr r2, [r7, #28] + 80020fc: 4313 orrs r3, r2 + 80020fe: 61fb str r3, [r7, #28] + } + bitpos = (uint_fast8_t)(bitpos + 7); + 8002100: 69bb ldr r3, [r7, #24] + 8002102: 3307 adds r3, #7 + 8002104: 61bb str r3, [r7, #24] + } while (byte & 0x80); + 8002106: 7dbb ldrb r3, [r7, #22] + 8002108: b25b sxtb r3, r3 + 800210a: 2b00 cmp r3, #0 + 800210c: dbbf blt.n 800208e + + if (bitpos == 35 && (byte & 0x70) != 0) + 800210e: 69bb ldr r3, [r7, #24] + 8002110: 2b23 cmp r3, #35 ; 0x23 + 8002112: d110 bne.n 8002136 + 8002114: 7dbb ldrb r3, [r7, #22] + 8002116: f003 0370 and.w r3, r3, #112 ; 0x70 + 800211a: 2b00 cmp r3, #0 + 800211c: d00b beq.n 8002136 + { + /* The last byte was at bitpos=28, so only bottom 4 bits fit. */ + PB_RETURN_ERROR(stream, "varint overflow"); + 800211e: 68fb ldr r3, [r7, #12] + 8002120: 68db ldr r3, [r3, #12] + 8002122: 2b00 cmp r3, #0 + 8002124: d002 beq.n 800212c + 8002126: 68fb ldr r3, [r7, #12] + 8002128: 68db ldr r3, [r3, #12] + 800212a: e000 b.n 800212e + 800212c: 4b06 ldr r3, [pc, #24] ; (8002148 ) + 800212e: 68fa ldr r2, [r7, #12] + 8002130: 60d3 str r3, [r2, #12] + 8002132: 2300 movs r3, #0 + 8002134: e003 b.n 800213e + } + } + + *dest = result; + 8002136: 68bb ldr r3, [r7, #8] + 8002138: 69fa ldr r2, [r7, #28] + 800213a: 601a str r2, [r3, #0] + return true; + 800213c: 2301 movs r3, #1 +} + 800213e: 4618 mov r0, r3 + 8002140: 3720 adds r7, #32 + 8002142: 46bd mov sp, r7 + 8002144: bd80 pop {r7, pc} + 8002146: bf00 nop + 8002148: 08008a00 .word 0x08008a00 + +0800214c : + +bool checkreturn pb_decode_varint32(pb_istream_t *stream, uint32_t *dest) +{ + 800214c: b580 push {r7, lr} + 800214e: b082 sub sp, #8 + 8002150: af00 add r7, sp, #0 + 8002152: 6078 str r0, [r7, #4] + 8002154: 6039 str r1, [r7, #0] + return pb_decode_varint32_eof(stream, dest, NULL); + 8002156: 2200 movs r2, #0 + 8002158: 6839 ldr r1, [r7, #0] + 800215a: 6878 ldr r0, [r7, #4] + 800215c: f7ff ff6c bl 8002038 + 8002160: 4603 mov r3, r0 +} + 8002162: 4618 mov r0, r3 + 8002164: 3708 adds r7, #8 + 8002166: 46bd mov sp, r7 + 8002168: bd80 pop {r7, pc} + ... + +0800216c : + +#ifndef PB_WITHOUT_64BIT +bool checkreturn pb_decode_varint(pb_istream_t *stream, uint64_t *dest) +{ + 800216c: e92d 48f0 stmdb sp!, {r4, r5, r6, r7, fp, lr} + 8002170: b088 sub sp, #32 + 8002172: af00 add r7, sp, #0 + 8002174: 6078 str r0, [r7, #4] + 8002176: 6039 str r1, [r7, #0] + pb_byte_t byte; + uint_fast8_t bitpos = 0; + 8002178: 2300 movs r3, #0 + 800217a: 61fb str r3, [r7, #28] + uint64_t result = 0; + 800217c: f04f 0200 mov.w r2, #0 + 8002180: f04f 0300 mov.w r3, #0 + 8002184: e9c7 2304 strd r2, r3, [r7, #16] + + do + { + if (bitpos >= 64) + 8002188: 69fb ldr r3, [r7, #28] + 800218a: 2b3f cmp r3, #63 ; 0x3f + 800218c: d90b bls.n 80021a6 + PB_RETURN_ERROR(stream, "varint overflow"); + 800218e: 687b ldr r3, [r7, #4] + 8002190: 68db ldr r3, [r3, #12] + 8002192: 2b00 cmp r3, #0 + 8002194: d002 beq.n 800219c + 8002196: 687b ldr r3, [r7, #4] + 8002198: 68db ldr r3, [r3, #12] + 800219a: e000 b.n 800219e + 800219c: 4b23 ldr r3, [pc, #140] ; (800222c ) + 800219e: 687a ldr r2, [r7, #4] + 80021a0: 60d3 str r3, [r2, #12] + 80021a2: 2300 movs r3, #0 + 80021a4: e03d b.n 8002222 + + if (!pb_readbyte(stream, &byte)) + 80021a6: f107 030f add.w r3, r7, #15 + 80021aa: 4619 mov r1, r3 + 80021ac: 6878 ldr r0, [r7, #4] + 80021ae: f7ff fee9 bl 8001f84 + 80021b2: 4603 mov r3, r0 + 80021b4: f083 0301 eor.w r3, r3, #1 + 80021b8: b2db uxtb r3, r3 + 80021ba: 2b00 cmp r3, #0 + 80021bc: d001 beq.n 80021c2 + return false; + 80021be: 2300 movs r3, #0 + 80021c0: e02f b.n 8002222 + + result |= (uint64_t)(byte & 0x7F) << bitpos; + 80021c2: 7bfb ldrb r3, [r7, #15] + 80021c4: b2da uxtb r2, r3 + 80021c6: f04f 0300 mov.w r3, #0 + 80021ca: f04f 007f mov.w r0, #127 ; 0x7f + 80021ce: f04f 0100 mov.w r1, #0 + 80021d2: ea02 0b00 and.w fp, r2, r0 + 80021d6: ea03 0c01 and.w ip, r3, r1 + 80021da: 69f9 ldr r1, [r7, #28] + 80021dc: f1a1 0620 sub.w r6, r1, #32 + 80021e0: f1c1 0020 rsb r0, r1, #32 + 80021e4: fa0c f501 lsl.w r5, ip, r1 + 80021e8: fa0b f606 lsl.w r6, fp, r6 + 80021ec: 4335 orrs r5, r6 + 80021ee: fa2b f000 lsr.w r0, fp, r0 + 80021f2: 4305 orrs r5, r0 + 80021f4: fa0b f401 lsl.w r4, fp, r1 + 80021f8: e9d7 2304 ldrd r2, r3, [r7, #16] + 80021fc: ea42 0004 orr.w r0, r2, r4 + 8002200: ea43 0105 orr.w r1, r3, r5 + 8002204: e9c7 0104 strd r0, r1, [r7, #16] + bitpos = (uint_fast8_t)(bitpos + 7); + 8002208: 69fb ldr r3, [r7, #28] + 800220a: 3307 adds r3, #7 + 800220c: 61fb str r3, [r7, #28] + } while (byte & 0x80); + 800220e: 7bfb ldrb r3, [r7, #15] + 8002210: b25b sxtb r3, r3 + 8002212: 2b00 cmp r3, #0 + 8002214: dbb8 blt.n 8002188 + + *dest = result; + 8002216: 683a ldr r2, [r7, #0] + 8002218: e9d7 3404 ldrd r3, r4, [r7, #16] + 800221c: e9c2 3400 strd r3, r4, [r2] + return true; + 8002220: 2301 movs r3, #1 +} + 8002222: 4618 mov r0, r3 + 8002224: 3720 adds r7, #32 + 8002226: 46bd mov sp, r7 + 8002228: e8bd 88f0 ldmia.w sp!, {r4, r5, r6, r7, fp, pc} + 800222c: 08008a00 .word 0x08008a00 + +08002230 : +#endif + +bool checkreturn pb_skip_varint(pb_istream_t *stream) +{ + 8002230: b580 push {r7, lr} + 8002232: b084 sub sp, #16 + 8002234: af00 add r7, sp, #0 + 8002236: 6078 str r0, [r7, #4] + pb_byte_t byte; + do + { + if (!pb_read(stream, &byte, 1)) + 8002238: f107 030f add.w r3, r7, #15 + 800223c: 2201 movs r2, #1 + 800223e: 4619 mov r1, r3 + 8002240: 6878 ldr r0, [r7, #4] + 8002242: f7ff fe33 bl 8001eac + 8002246: 4603 mov r3, r0 + 8002248: f083 0301 eor.w r3, r3, #1 + 800224c: b2db uxtb r3, r3 + 800224e: 2b00 cmp r3, #0 + 8002250: d001 beq.n 8002256 + return false; + 8002252: 2300 movs r3, #0 + 8002254: e004 b.n 8002260 + } while (byte & 0x80); + 8002256: 7bfb ldrb r3, [r7, #15] + 8002258: b25b sxtb r3, r3 + 800225a: 2b00 cmp r3, #0 + 800225c: dbec blt.n 8002238 + return true; + 800225e: 2301 movs r3, #1 +} + 8002260: 4618 mov r0, r3 + 8002262: 3710 adds r7, #16 + 8002264: 46bd mov sp, r7 + 8002266: bd80 pop {r7, pc} + +08002268 : + +bool checkreturn pb_skip_string(pb_istream_t *stream) +{ + 8002268: b580 push {r7, lr} + 800226a: b084 sub sp, #16 + 800226c: af00 add r7, sp, #0 + 800226e: 6078 str r0, [r7, #4] + uint32_t length; + if (!pb_decode_varint32(stream, &length)) + 8002270: f107 030c add.w r3, r7, #12 + 8002274: 4619 mov r1, r3 + 8002276: 6878 ldr r0, [r7, #4] + 8002278: f7ff ff68 bl 800214c + 800227c: 4603 mov r3, r0 + 800227e: f083 0301 eor.w r3, r3, #1 + 8002282: b2db uxtb r3, r3 + 8002284: 2b00 cmp r3, #0 + 8002286: d001 beq.n 800228c + return false; + 8002288: 2300 movs r3, #0 + 800228a: e006 b.n 800229a + if ((size_t)length != length) + { + PB_RETURN_ERROR(stream, "size too large"); + } + + return pb_read(stream, NULL, (size_t)length); + 800228c: 68fb ldr r3, [r7, #12] + 800228e: 461a mov r2, r3 + 8002290: 2100 movs r1, #0 + 8002292: 6878 ldr r0, [r7, #4] + 8002294: f7ff fe0a bl 8001eac + 8002298: 4603 mov r3, r0 +} + 800229a: 4618 mov r0, r3 + 800229c: 3710 adds r7, #16 + 800229e: 46bd mov sp, r7 + 80022a0: bd80 pop {r7, pc} + +080022a2 : + +bool checkreturn pb_decode_tag(pb_istream_t *stream, pb_wire_type_t *wire_type, uint32_t *tag, bool *eof) +{ + 80022a2: b580 push {r7, lr} + 80022a4: b086 sub sp, #24 + 80022a6: af00 add r7, sp, #0 + 80022a8: 60f8 str r0, [r7, #12] + 80022aa: 60b9 str r1, [r7, #8] + 80022ac: 607a str r2, [r7, #4] + 80022ae: 603b str r3, [r7, #0] + uint32_t temp; + *eof = false; + 80022b0: 683b ldr r3, [r7, #0] + 80022b2: 2200 movs r2, #0 + 80022b4: 701a strb r2, [r3, #0] + *wire_type = (pb_wire_type_t) 0; + 80022b6: 68bb ldr r3, [r7, #8] + 80022b8: 2200 movs r2, #0 + 80022ba: 701a strb r2, [r3, #0] + *tag = 0; + 80022bc: 687b ldr r3, [r7, #4] + 80022be: 2200 movs r2, #0 + 80022c0: 601a str r2, [r3, #0] + + if (!pb_decode_varint32_eof(stream, &temp, eof)) + 80022c2: f107 0314 add.w r3, r7, #20 + 80022c6: 683a ldr r2, [r7, #0] + 80022c8: 4619 mov r1, r3 + 80022ca: 68f8 ldr r0, [r7, #12] + 80022cc: f7ff feb4 bl 8002038 + 80022d0: 4603 mov r3, r0 + 80022d2: f083 0301 eor.w r3, r3, #1 + 80022d6: b2db uxtb r3, r3 + 80022d8: 2b00 cmp r3, #0 + 80022da: d001 beq.n 80022e0 + { + return false; + 80022dc: 2300 movs r3, #0 + 80022de: e00b b.n 80022f8 + } + + *tag = temp >> 3; + 80022e0: 697b ldr r3, [r7, #20] + 80022e2: 08da lsrs r2, r3, #3 + 80022e4: 687b ldr r3, [r7, #4] + 80022e6: 601a str r2, [r3, #0] + *wire_type = (pb_wire_type_t)(temp & 7); + 80022e8: 697b ldr r3, [r7, #20] + 80022ea: b2db uxtb r3, r3 + 80022ec: f003 0307 and.w r3, r3, #7 + 80022f0: b2da uxtb r2, r3 + 80022f2: 68bb ldr r3, [r7, #8] + 80022f4: 701a strb r2, [r3, #0] + return true; + 80022f6: 2301 movs r3, #1 +} + 80022f8: 4618 mov r0, r3 + 80022fa: 3718 adds r7, #24 + 80022fc: 46bd mov sp, r7 + 80022fe: bd80 pop {r7, pc} + +08002300 : + +bool checkreturn pb_skip_field(pb_istream_t *stream, pb_wire_type_t wire_type) +{ + 8002300: b580 push {r7, lr} + 8002302: b082 sub sp, #8 + 8002304: af00 add r7, sp, #0 + 8002306: 6078 str r0, [r7, #4] + 8002308: 460b mov r3, r1 + 800230a: 70fb strb r3, [r7, #3] + switch (wire_type) + 800230c: 78fb ldrb r3, [r7, #3] + 800230e: 2b05 cmp r3, #5 + 8002310: d826 bhi.n 8002360 + 8002312: a201 add r2, pc, #4 ; (adr r2, 8002318 ) + 8002314: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8002318: 08002331 .word 0x08002331 + 800231c: 0800233b .word 0x0800233b + 8002320: 08002349 .word 0x08002349 + 8002324: 08002361 .word 0x08002361 + 8002328: 08002361 .word 0x08002361 + 800232c: 08002353 .word 0x08002353 + { + case PB_WT_VARINT: return pb_skip_varint(stream); + 8002330: 6878 ldr r0, [r7, #4] + 8002332: f7ff ff7d bl 8002230 + 8002336: 4603 mov r3, r0 + 8002338: e01d b.n 8002376 + case PB_WT_64BIT: return pb_read(stream, NULL, 8); + 800233a: 2208 movs r2, #8 + 800233c: 2100 movs r1, #0 + 800233e: 6878 ldr r0, [r7, #4] + 8002340: f7ff fdb4 bl 8001eac + 8002344: 4603 mov r3, r0 + 8002346: e016 b.n 8002376 + case PB_WT_STRING: return pb_skip_string(stream); + 8002348: 6878 ldr r0, [r7, #4] + 800234a: f7ff ff8d bl 8002268 + 800234e: 4603 mov r3, r0 + 8002350: e011 b.n 8002376 + case PB_WT_32BIT: return pb_read(stream, NULL, 4); + 8002352: 2204 movs r2, #4 + 8002354: 2100 movs r1, #0 + 8002356: 6878 ldr r0, [r7, #4] + 8002358: f7ff fda8 bl 8001eac + 800235c: 4603 mov r3, r0 + 800235e: e00a b.n 8002376 + default: PB_RETURN_ERROR(stream, "invalid wire_type"); + 8002360: 687b ldr r3, [r7, #4] + 8002362: 68db ldr r3, [r3, #12] + 8002364: 2b00 cmp r3, #0 + 8002366: d002 beq.n 800236e + 8002368: 687b ldr r3, [r7, #4] + 800236a: 68db ldr r3, [r3, #12] + 800236c: e000 b.n 8002370 + 800236e: 4b04 ldr r3, [pc, #16] ; (8002380 ) + 8002370: 687a ldr r2, [r7, #4] + 8002372: 60d3 str r3, [r2, #12] + 8002374: 2300 movs r3, #0 + } +} + 8002376: 4618 mov r0, r3 + 8002378: 3708 adds r7, #8 + 800237a: 46bd mov sp, r7 + 800237c: bd80 pop {r7, pc} + 800237e: bf00 nop + 8002380: 08008a10 .word 0x08008a10 + +08002384 : + +/* Read a raw value to buffer, for the purpose of passing it to callback as + * a substream. Size is maximum size on call, and actual size on return. + */ +static bool checkreturn read_raw_value(pb_istream_t *stream, pb_wire_type_t wire_type, pb_byte_t *buf, size_t *size) +{ + 8002384: b580 push {r7, lr} + 8002386: b086 sub sp, #24 + 8002388: af00 add r7, sp, #0 + 800238a: 60f8 str r0, [r7, #12] + 800238c: 607a str r2, [r7, #4] + 800238e: 603b str r3, [r7, #0] + 8002390: 460b mov r3, r1 + 8002392: 72fb strb r3, [r7, #11] + size_t max_size = *size; + 8002394: 683b ldr r3, [r7, #0] + 8002396: 681b ldr r3, [r3, #0] + 8002398: 617b str r3, [r7, #20] + switch (wire_type) + 800239a: 7afb ldrb r3, [r7, #11] + 800239c: 2b01 cmp r3, #1 + 800239e: d032 beq.n 8002406 + 80023a0: 2b05 cmp r3, #5 + 80023a2: d03a beq.n 800241a + 80023a4: 2b00 cmp r3, #0 + 80023a6: d142 bne.n 800242e + { + case PB_WT_VARINT: + *size = 0; + 80023a8: 683b ldr r3, [r7, #0] + 80023aa: 2200 movs r2, #0 + 80023ac: 601a str r2, [r3, #0] + do + { + (*size)++; + 80023ae: 683b ldr r3, [r7, #0] + 80023b0: 681b ldr r3, [r3, #0] + 80023b2: 1c5a adds r2, r3, #1 + 80023b4: 683b ldr r3, [r7, #0] + 80023b6: 601a str r2, [r3, #0] + if (*size > max_size) + 80023b8: 683b ldr r3, [r7, #0] + 80023ba: 681b ldr r3, [r3, #0] + 80023bc: 697a ldr r2, [r7, #20] + 80023be: 429a cmp r2, r3 + 80023c0: d20b bcs.n 80023da + PB_RETURN_ERROR(stream, "varint overflow"); + 80023c2: 68fb ldr r3, [r7, #12] + 80023c4: 68db ldr r3, [r3, #12] + 80023c6: 2b00 cmp r3, #0 + 80023c8: d002 beq.n 80023d0 + 80023ca: 68fb ldr r3, [r7, #12] + 80023cc: 68db ldr r3, [r3, #12] + 80023ce: e000 b.n 80023d2 + 80023d0: 4b1e ldr r3, [pc, #120] ; (800244c ) + 80023d2: 68fa ldr r2, [r7, #12] + 80023d4: 60d3 str r3, [r2, #12] + 80023d6: 2300 movs r3, #0 + 80023d8: e034 b.n 8002444 + + if (!pb_read(stream, buf, 1)) + 80023da: 2201 movs r2, #1 + 80023dc: 6879 ldr r1, [r7, #4] + 80023de: 68f8 ldr r0, [r7, #12] + 80023e0: f7ff fd64 bl 8001eac + 80023e4: 4603 mov r3, r0 + 80023e6: f083 0301 eor.w r3, r3, #1 + 80023ea: b2db uxtb r3, r3 + 80023ec: 2b00 cmp r3, #0 + 80023ee: d001 beq.n 80023f4 + return false; + 80023f0: 2300 movs r3, #0 + 80023f2: e027 b.n 8002444 + } while (*buf++ & 0x80); + 80023f4: 687b ldr r3, [r7, #4] + 80023f6: 1c5a adds r2, r3, #1 + 80023f8: 607a str r2, [r7, #4] + 80023fa: 781b ldrb r3, [r3, #0] + 80023fc: b25b sxtb r3, r3 + 80023fe: 2b00 cmp r3, #0 + 8002400: dbd5 blt.n 80023ae + return true; + 8002402: 2301 movs r3, #1 + 8002404: e01e b.n 8002444 + + case PB_WT_64BIT: + *size = 8; + 8002406: 683b ldr r3, [r7, #0] + 8002408: 2208 movs r2, #8 + 800240a: 601a str r2, [r3, #0] + return pb_read(stream, buf, 8); + 800240c: 2208 movs r2, #8 + 800240e: 6879 ldr r1, [r7, #4] + 8002410: 68f8 ldr r0, [r7, #12] + 8002412: f7ff fd4b bl 8001eac + 8002416: 4603 mov r3, r0 + 8002418: e014 b.n 8002444 + + case PB_WT_32BIT: + *size = 4; + 800241a: 683b ldr r3, [r7, #0] + 800241c: 2204 movs r2, #4 + 800241e: 601a str r2, [r3, #0] + return pb_read(stream, buf, 4); + 8002420: 2204 movs r2, #4 + 8002422: 6879 ldr r1, [r7, #4] + 8002424: 68f8 ldr r0, [r7, #12] + 8002426: f7ff fd41 bl 8001eac + 800242a: 4603 mov r3, r0 + 800242c: e00a b.n 8002444 + /* Calling read_raw_value with a PB_WT_STRING is an error. + * Explicitly handle this case and fallthrough to default to avoid + * compiler warnings. + */ + + default: PB_RETURN_ERROR(stream, "invalid wire_type"); + 800242e: 68fb ldr r3, [r7, #12] + 8002430: 68db ldr r3, [r3, #12] + 8002432: 2b00 cmp r3, #0 + 8002434: d002 beq.n 800243c + 8002436: 68fb ldr r3, [r7, #12] + 8002438: 68db ldr r3, [r3, #12] + 800243a: e000 b.n 800243e + 800243c: 4b04 ldr r3, [pc, #16] ; (8002450 ) + 800243e: 68fa ldr r2, [r7, #12] + 8002440: 60d3 str r3, [r2, #12] + 8002442: 2300 movs r3, #0 + } +} + 8002444: 4618 mov r0, r3 + 8002446: 3718 adds r7, #24 + 8002448: 46bd mov sp, r7 + 800244a: bd80 pop {r7, pc} + 800244c: 08008a00 .word 0x08008a00 + 8002450: 08008a10 .word 0x08008a10 + +08002454 : + +/* Decode string length from stream and return a substream with limited length. + * Remember to close the substream using pb_close_string_substream(). + */ +bool checkreturn pb_make_string_substream(pb_istream_t *stream, pb_istream_t *substream) +{ + 8002454: b590 push {r4, r7, lr} + 8002456: b085 sub sp, #20 + 8002458: af00 add r7, sp, #0 + 800245a: 6078 str r0, [r7, #4] + 800245c: 6039 str r1, [r7, #0] + uint32_t size; + if (!pb_decode_varint32(stream, &size)) + 800245e: f107 030c add.w r3, r7, #12 + 8002462: 4619 mov r1, r3 + 8002464: 6878 ldr r0, [r7, #4] + 8002466: f7ff fe71 bl 800214c + 800246a: 4603 mov r3, r0 + 800246c: f083 0301 eor.w r3, r3, #1 + 8002470: b2db uxtb r3, r3 + 8002472: 2b00 cmp r3, #0 + 8002474: d001 beq.n 800247a + return false; + 8002476: 2300 movs r3, #0 + 8002478: e020 b.n 80024bc + + *substream = *stream; + 800247a: 683a ldr r2, [r7, #0] + 800247c: 687b ldr r3, [r7, #4] + 800247e: 4614 mov r4, r2 + 8002480: cb0f ldmia r3, {r0, r1, r2, r3} + 8002482: e884 000f stmia.w r4, {r0, r1, r2, r3} + if (substream->bytes_left < size) + 8002486: 683b ldr r3, [r7, #0] + 8002488: 689a ldr r2, [r3, #8] + 800248a: 68fb ldr r3, [r7, #12] + 800248c: 429a cmp r2, r3 + 800248e: d20b bcs.n 80024a8 + PB_RETURN_ERROR(stream, "parent stream too short"); + 8002490: 687b ldr r3, [r7, #4] + 8002492: 68db ldr r3, [r3, #12] + 8002494: 2b00 cmp r3, #0 + 8002496: d002 beq.n 800249e + 8002498: 687b ldr r3, [r7, #4] + 800249a: 68db ldr r3, [r3, #12] + 800249c: e000 b.n 80024a0 + 800249e: 4b09 ldr r3, [pc, #36] ; (80024c4 ) + 80024a0: 687a ldr r2, [r7, #4] + 80024a2: 60d3 str r3, [r2, #12] + 80024a4: 2300 movs r3, #0 + 80024a6: e009 b.n 80024bc + + substream->bytes_left = (size_t)size; + 80024a8: 68fa ldr r2, [r7, #12] + 80024aa: 683b ldr r3, [r7, #0] + 80024ac: 609a str r2, [r3, #8] + stream->bytes_left -= (size_t)size; + 80024ae: 687b ldr r3, [r7, #4] + 80024b0: 689a ldr r2, [r3, #8] + 80024b2: 68fb ldr r3, [r7, #12] + 80024b4: 1ad2 subs r2, r2, r3 + 80024b6: 687b ldr r3, [r7, #4] + 80024b8: 609a str r2, [r3, #8] + return true; + 80024ba: 2301 movs r3, #1 +} + 80024bc: 4618 mov r0, r3 + 80024be: 3714 adds r7, #20 + 80024c0: 46bd mov sp, r7 + 80024c2: bd90 pop {r4, r7, pc} + 80024c4: 08008a24 .word 0x08008a24 + +080024c8 : + +bool checkreturn pb_close_string_substream(pb_istream_t *stream, pb_istream_t *substream) +{ + 80024c8: b580 push {r7, lr} + 80024ca: b082 sub sp, #8 + 80024cc: af00 add r7, sp, #0 + 80024ce: 6078 str r0, [r7, #4] + 80024d0: 6039 str r1, [r7, #0] + if (substream->bytes_left) { + 80024d2: 683b ldr r3, [r7, #0] + 80024d4: 689b ldr r3, [r3, #8] + 80024d6: 2b00 cmp r3, #0 + 80024d8: d00e beq.n 80024f8 + if (!pb_read(substream, NULL, substream->bytes_left)) + 80024da: 683b ldr r3, [r7, #0] + 80024dc: 689b ldr r3, [r3, #8] + 80024de: 461a mov r2, r3 + 80024e0: 2100 movs r1, #0 + 80024e2: 6838 ldr r0, [r7, #0] + 80024e4: f7ff fce2 bl 8001eac + 80024e8: 4603 mov r3, r0 + 80024ea: f083 0301 eor.w r3, r3, #1 + 80024ee: b2db uxtb r3, r3 + 80024f0: 2b00 cmp r3, #0 + 80024f2: d001 beq.n 80024f8 + return false; + 80024f4: 2300 movs r3, #0 + 80024f6: e008 b.n 800250a + } + + stream->state = substream->state; + 80024f8: 683b ldr r3, [r7, #0] + 80024fa: 685a ldr r2, [r3, #4] + 80024fc: 687b ldr r3, [r7, #4] + 80024fe: 605a str r2, [r3, #4] + +#ifndef PB_NO_ERRMSG + stream->errmsg = substream->errmsg; + 8002500: 683b ldr r3, [r7, #0] + 8002502: 68da ldr r2, [r3, #12] + 8002504: 687b ldr r3, [r7, #4] + 8002506: 60da str r2, [r3, #12] +#endif + return true; + 8002508: 2301 movs r3, #1 +} + 800250a: 4618 mov r0, r3 + 800250c: 3708 adds r7, #8 + 800250e: 46bd mov sp, r7 + 8002510: bd80 pop {r7, pc} + ... + +08002514 : +/************************* + * Decode a single field * + *************************/ + +static bool checkreturn check_wire_type(pb_wire_type_t wire_type, pb_field_iter_t *field) +{ + 8002514: b480 push {r7} + 8002516: b083 sub sp, #12 + 8002518: af00 add r7, sp, #0 + 800251a: 4603 mov r3, r0 + 800251c: 6039 str r1, [r7, #0] + 800251e: 71fb strb r3, [r7, #7] + switch (PB_LTYPE(field->type)) + 8002520: 683b ldr r3, [r7, #0] + 8002522: 7d9b ldrb r3, [r3, #22] + 8002524: f003 030f and.w r3, r3, #15 + 8002528: 2b0b cmp r3, #11 + 800252a: d837 bhi.n 800259c + 800252c: a201 add r2, pc, #4 ; (adr r2, 8002534 ) + 800252e: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8002532: bf00 nop + 8002534: 08002565 .word 0x08002565 + 8002538: 08002565 .word 0x08002565 + 800253c: 08002565 .word 0x08002565 + 8002540: 08002565 .word 0x08002565 + 8002544: 08002573 .word 0x08002573 + 8002548: 08002581 .word 0x08002581 + 800254c: 0800258f .word 0x0800258f + 8002550: 0800258f .word 0x0800258f + 8002554: 0800258f .word 0x0800258f + 8002558: 0800258f .word 0x0800258f + 800255c: 0800259d .word 0x0800259d + 8002560: 0800258f .word 0x0800258f + { + case PB_LTYPE_BOOL: + case PB_LTYPE_VARINT: + case PB_LTYPE_UVARINT: + case PB_LTYPE_SVARINT: + return wire_type == PB_WT_VARINT; + 8002564: 79fb ldrb r3, [r7, #7] + 8002566: 2b00 cmp r3, #0 + 8002568: bf0c ite eq + 800256a: 2301 moveq r3, #1 + 800256c: 2300 movne r3, #0 + 800256e: b2db uxtb r3, r3 + 8002570: e015 b.n 800259e + + case PB_LTYPE_FIXED32: + return wire_type == PB_WT_32BIT; + 8002572: 79fb ldrb r3, [r7, #7] + 8002574: 2b05 cmp r3, #5 + 8002576: bf0c ite eq + 8002578: 2301 moveq r3, #1 + 800257a: 2300 movne r3, #0 + 800257c: b2db uxtb r3, r3 + 800257e: e00e b.n 800259e + + case PB_LTYPE_FIXED64: + return wire_type == PB_WT_64BIT; + 8002580: 79fb ldrb r3, [r7, #7] + 8002582: 2b01 cmp r3, #1 + 8002584: bf0c ite eq + 8002586: 2301 moveq r3, #1 + 8002588: 2300 movne r3, #0 + 800258a: b2db uxtb r3, r3 + 800258c: e007 b.n 800259e + case PB_LTYPE_BYTES: + case PB_LTYPE_STRING: + case PB_LTYPE_SUBMESSAGE: + case PB_LTYPE_SUBMSG_W_CB: + case PB_LTYPE_FIXED_LENGTH_BYTES: + return wire_type == PB_WT_STRING; + 800258e: 79fb ldrb r3, [r7, #7] + 8002590: 2b02 cmp r3, #2 + 8002592: bf0c ite eq + 8002594: 2301 moveq r3, #1 + 8002596: 2300 movne r3, #0 + 8002598: b2db uxtb r3, r3 + 800259a: e000 b.n 800259e + + default: + return false; + 800259c: 2300 movs r3, #0 + } +} + 800259e: 4618 mov r0, r3 + 80025a0: 370c adds r7, #12 + 80025a2: 46bd mov sp, r7 + 80025a4: f85d 7b04 ldr.w r7, [sp], #4 + 80025a8: 4770 bx lr + 80025aa: bf00 nop + +080025ac : + +static bool checkreturn decode_basic_field(pb_istream_t *stream, pb_field_iter_t *field) +{ + 80025ac: b580 push {r7, lr} + 80025ae: b082 sub sp, #8 + 80025b0: af00 add r7, sp, #0 + 80025b2: 6078 str r0, [r7, #4] + 80025b4: 6039 str r1, [r7, #0] + switch (PB_LTYPE(field->type)) + 80025b6: 683b ldr r3, [r7, #0] + 80025b8: 7d9b ldrb r3, [r3, #22] + 80025ba: f003 030f and.w r3, r3, #15 + 80025be: 2b0b cmp r3, #11 + 80025c0: d844 bhi.n 800264c + 80025c2: a201 add r2, pc, #4 ; (adr r2, 80025c8 ) + 80025c4: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80025c8: 080025f9 .word 0x080025f9 + 80025cc: 08002605 .word 0x08002605 + 80025d0: 08002605 .word 0x08002605 + 80025d4: 08002605 .word 0x08002605 + 80025d8: 08002611 .word 0x08002611 + 80025dc: 08002611 .word 0x08002611 + 80025e0: 0800261d .word 0x0800261d + 80025e4: 08002629 .word 0x08002629 + 80025e8: 08002635 .word 0x08002635 + 80025ec: 08002635 .word 0x08002635 + 80025f0: 0800264d .word 0x0800264d + 80025f4: 08002641 .word 0x08002641 + { + case PB_LTYPE_BOOL: + return pb_dec_bool(stream, field); + 80025f8: 6839 ldr r1, [r7, #0] + 80025fa: 6878 ldr r0, [r7, #4] + 80025fc: f000 ff5f bl 80034be + 8002600: 4603 mov r3, r0 + 8002602: e02e b.n 8002662 + + case PB_LTYPE_VARINT: + case PB_LTYPE_UVARINT: + case PB_LTYPE_SVARINT: + return pb_dec_varint(stream, field); + 8002604: 6839 ldr r1, [r7, #0] + 8002606: 6878 ldr r0, [r7, #4] + 8002608: f000 ff6a bl 80034e0 + 800260c: 4603 mov r3, r0 + 800260e: e028 b.n 8002662 + + case PB_LTYPE_FIXED32: + case PB_LTYPE_FIXED64: + return pb_dec_fixed(stream, field); + 8002610: 6839 ldr r1, [r7, #0] + 8002612: 6878 ldr r0, [r7, #4] + 8002614: f001 f87e bl 8003714 + 8002618: 4603 mov r3, r0 + 800261a: e022 b.n 8002662 + + case PB_LTYPE_BYTES: + return pb_dec_bytes(stream, field); + 800261c: 6839 ldr r1, [r7, #0] + 800261e: 6878 ldr r0, [r7, #4] + 8002620: f001 f8a6 bl 8003770 + 8002624: 4603 mov r3, r0 + 8002626: e01c b.n 8002662 + + case PB_LTYPE_STRING: + return pb_dec_string(stream, field); + 8002628: 6839 ldr r1, [r7, #0] + 800262a: 6878 ldr r0, [r7, #4] + 800262c: f001 f914 bl 8003858 + 8002630: 4603 mov r3, r0 + 8002632: e016 b.n 8002662 + + case PB_LTYPE_SUBMESSAGE: + case PB_LTYPE_SUBMSG_W_CB: + return pb_dec_submessage(stream, field); + 8002634: 6839 ldr r1, [r7, #0] + 8002636: 6878 ldr r0, [r7, #4] + 8002638: f001 f98a bl 8003950 + 800263c: 4603 mov r3, r0 + 800263e: e010 b.n 8002662 + + case PB_LTYPE_FIXED_LENGTH_BYTES: + return pb_dec_fixed_length_bytes(stream, field); + 8002640: 6839 ldr r1, [r7, #0] + 8002642: 6878 ldr r0, [r7, #4] + 8002644: f001 fa1e bl 8003a84 + 8002648: 4603 mov r3, r0 + 800264a: e00a b.n 8002662 + + default: + PB_RETURN_ERROR(stream, "invalid field type"); + 800264c: 687b ldr r3, [r7, #4] + 800264e: 68db ldr r3, [r3, #12] + 8002650: 2b00 cmp r3, #0 + 8002652: d002 beq.n 800265a + 8002654: 687b ldr r3, [r7, #4] + 8002656: 68db ldr r3, [r3, #12] + 8002658: e000 b.n 800265c + 800265a: 4b04 ldr r3, [pc, #16] ; (800266c ) + 800265c: 687a ldr r2, [r7, #4] + 800265e: 60d3 str r3, [r2, #12] + 8002660: 2300 movs r3, #0 + } +} + 8002662: 4618 mov r0, r3 + 8002664: 3708 adds r7, #8 + 8002666: 46bd mov sp, r7 + 8002668: bd80 pop {r7, pc} + 800266a: bf00 nop + 800266c: 08008a3c .word 0x08008a3c + +08002670 : + +static bool checkreturn decode_static_field(pb_istream_t *stream, pb_wire_type_t wire_type, pb_field_iter_t *field) +{ + 8002670: b580 push {r7, lr} + 8002672: b08c sub sp, #48 ; 0x30 + 8002674: af00 add r7, sp, #0 + 8002676: 60f8 str r0, [r7, #12] + 8002678: 460b mov r3, r1 + 800267a: 607a str r2, [r7, #4] + 800267c: 72fb strb r3, [r7, #11] + switch (PB_HTYPE(field->type)) + 800267e: 687b ldr r3, [r7, #4] + 8002680: 7d9b ldrb r3, [r3, #22] + 8002682: f003 0330 and.w r3, r3, #48 ; 0x30 + 8002686: 2b10 cmp r3, #16 + 8002688: d027 beq.n 80026da + 800268a: 2b10 cmp r3, #16 + 800268c: d802 bhi.n 8002694 + 800268e: 2b00 cmp r3, #0 + 8002690: d006 beq.n 80026a0 + 8002692: e12e b.n 80028f2 + 8002694: 2b20 cmp r3, #32 + 8002696: d045 beq.n 8002724 + 8002698: 2b30 cmp r3, #48 ; 0x30 + 800269a: f000 80f4 beq.w 8002886 + 800269e: e128 b.n 80028f2 + { + case PB_HTYPE_REQUIRED: + if (!check_wire_type(wire_type, field)) + 80026a0: 7afb ldrb r3, [r7, #11] + 80026a2: 6879 ldr r1, [r7, #4] + 80026a4: 4618 mov r0, r3 + 80026a6: f7ff ff35 bl 8002514 + 80026aa: 4603 mov r3, r0 + 80026ac: f083 0301 eor.w r3, r3, #1 + 80026b0: b2db uxtb r3, r3 + 80026b2: 2b00 cmp r3, #0 + 80026b4: d00b beq.n 80026ce + PB_RETURN_ERROR(stream, "wrong wire type"); + 80026b6: 68fb ldr r3, [r7, #12] + 80026b8: 68db ldr r3, [r3, #12] + 80026ba: 2b00 cmp r3, #0 + 80026bc: d002 beq.n 80026c4 + 80026be: 68fb ldr r3, [r7, #12] + 80026c0: 68db ldr r3, [r3, #12] + 80026c2: e000 b.n 80026c6 + 80026c4: 4b92 ldr r3, [pc, #584] ; (8002910 ) + 80026c6: 68fa ldr r2, [r7, #12] + 80026c8: 60d3 str r3, [r2, #12] + 80026ca: 2300 movs r3, #0 + 80026cc: e11c b.n 8002908 + + return decode_basic_field(stream, field); + 80026ce: 6879 ldr r1, [r7, #4] + 80026d0: 68f8 ldr r0, [r7, #12] + 80026d2: f7ff ff6b bl 80025ac + 80026d6: 4603 mov r3, r0 + 80026d8: e116 b.n 8002908 + + case PB_HTYPE_OPTIONAL: + if (!check_wire_type(wire_type, field)) + 80026da: 7afb ldrb r3, [r7, #11] + 80026dc: 6879 ldr r1, [r7, #4] + 80026de: 4618 mov r0, r3 + 80026e0: f7ff ff18 bl 8002514 + 80026e4: 4603 mov r3, r0 + 80026e6: f083 0301 eor.w r3, r3, #1 + 80026ea: b2db uxtb r3, r3 + 80026ec: 2b00 cmp r3, #0 + 80026ee: d00b beq.n 8002708 + PB_RETURN_ERROR(stream, "wrong wire type"); + 80026f0: 68fb ldr r3, [r7, #12] + 80026f2: 68db ldr r3, [r3, #12] + 80026f4: 2b00 cmp r3, #0 + 80026f6: d002 beq.n 80026fe + 80026f8: 68fb ldr r3, [r7, #12] + 80026fa: 68db ldr r3, [r3, #12] + 80026fc: e000 b.n 8002700 + 80026fe: 4b84 ldr r3, [pc, #528] ; (8002910 ) + 8002700: 68fa ldr r2, [r7, #12] + 8002702: 60d3 str r3, [r2, #12] + 8002704: 2300 movs r3, #0 + 8002706: e0ff b.n 8002908 + + if (field->pSize != NULL) + 8002708: 687b ldr r3, [r7, #4] + 800270a: 6a1b ldr r3, [r3, #32] + 800270c: 2b00 cmp r3, #0 + 800270e: d003 beq.n 8002718 + *(bool*)field->pSize = true; + 8002710: 687b ldr r3, [r7, #4] + 8002712: 6a1b ldr r3, [r3, #32] + 8002714: 2201 movs r2, #1 + 8002716: 701a strb r2, [r3, #0] + return decode_basic_field(stream, field); + 8002718: 6879 ldr r1, [r7, #4] + 800271a: 68f8 ldr r0, [r7, #12] + 800271c: f7ff ff46 bl 80025ac + 8002720: 4603 mov r3, r0 + 8002722: e0f1 b.n 8002908 + + case PB_HTYPE_REPEATED: + if (wire_type == PB_WT_STRING + 8002724: 7afb ldrb r3, [r7, #11] + 8002726: 2b02 cmp r3, #2 + 8002728: d16b bne.n 8002802 + && PB_LTYPE(field->type) <= PB_LTYPE_LAST_PACKABLE) + 800272a: 687b ldr r3, [r7, #4] + 800272c: 7d9b ldrb r3, [r3, #22] + 800272e: f003 030f and.w r3, r3, #15 + 8002732: 2b05 cmp r3, #5 + 8002734: d865 bhi.n 8002802 + { + /* Packed array */ + bool status = true; + 8002736: 2301 movs r3, #1 + 8002738: f887 302f strb.w r3, [r7, #47] ; 0x2f + pb_istream_t substream; + pb_size_t *size = (pb_size_t*)field->pSize; + 800273c: 687b ldr r3, [r7, #4] + 800273e: 6a1b ldr r3, [r3, #32] + 8002740: 62bb str r3, [r7, #40] ; 0x28 + field->pData = (char*)field->pField + field->data_size * (*size); + 8002742: 687b ldr r3, [r7, #4] + 8002744: 699b ldr r3, [r3, #24] + 8002746: 687a ldr r2, [r7, #4] + 8002748: 8a52 ldrh r2, [r2, #18] + 800274a: 4611 mov r1, r2 + 800274c: 6aba ldr r2, [r7, #40] ; 0x28 + 800274e: 8812 ldrh r2, [r2, #0] + 8002750: fb02 f201 mul.w r2, r2, r1 + 8002754: 441a add r2, r3 + 8002756: 687b ldr r3, [r7, #4] + 8002758: 61da str r2, [r3, #28] + + if (!pb_make_string_substream(stream, &substream)) + 800275a: f107 0314 add.w r3, r7, #20 + 800275e: 4619 mov r1, r3 + 8002760: 68f8 ldr r0, [r7, #12] + 8002762: f7ff fe77 bl 8002454 + 8002766: 4603 mov r3, r0 + 8002768: f083 0301 eor.w r3, r3, #1 + 800276c: b2db uxtb r3, r3 + 800276e: 2b00 cmp r3, #0 + 8002770: d01e beq.n 80027b0 + return false; + 8002772: 2300 movs r3, #0 + 8002774: e0c8 b.n 8002908 + + while (substream.bytes_left > 0 && *size < field->array_size) + { + if (!decode_basic_field(&substream, field)) + 8002776: f107 0314 add.w r3, r7, #20 + 800277a: 6879 ldr r1, [r7, #4] + 800277c: 4618 mov r0, r3 + 800277e: f7ff ff15 bl 80025ac + 8002782: 4603 mov r3, r0 + 8002784: f083 0301 eor.w r3, r3, #1 + 8002788: b2db uxtb r3, r3 + 800278a: 2b00 cmp r3, #0 + 800278c: d003 beq.n 8002796 + { + status = false; + 800278e: 2300 movs r3, #0 + 8002790: f887 302f strb.w r3, [r7, #47] ; 0x2f + break; + 8002794: e015 b.n 80027c2 + } + (*size)++; + 8002796: 6abb ldr r3, [r7, #40] ; 0x28 + 8002798: 881b ldrh r3, [r3, #0] + 800279a: 3301 adds r3, #1 + 800279c: b29a uxth r2, r3 + 800279e: 6abb ldr r3, [r7, #40] ; 0x28 + 80027a0: 801a strh r2, [r3, #0] + field->pData = (char*)field->pData + field->data_size; + 80027a2: 687b ldr r3, [r7, #4] + 80027a4: 69db ldr r3, [r3, #28] + 80027a6: 687a ldr r2, [r7, #4] + 80027a8: 8a52 ldrh r2, [r2, #18] + 80027aa: 441a add r2, r3 + 80027ac: 687b ldr r3, [r7, #4] + 80027ae: 61da str r2, [r3, #28] + while (substream.bytes_left > 0 && *size < field->array_size) + 80027b0: 69fb ldr r3, [r7, #28] + 80027b2: 2b00 cmp r3, #0 + 80027b4: d005 beq.n 80027c2 + 80027b6: 6abb ldr r3, [r7, #40] ; 0x28 + 80027b8: 881a ldrh r2, [r3, #0] + 80027ba: 687b ldr r3, [r7, #4] + 80027bc: 8a9b ldrh r3, [r3, #20] + 80027be: 429a cmp r2, r3 + 80027c0: d3d9 bcc.n 8002776 + } + + if (substream.bytes_left != 0) + 80027c2: 69fb ldr r3, [r7, #28] + 80027c4: 2b00 cmp r3, #0 + 80027c6: d00b beq.n 80027e0 + PB_RETURN_ERROR(stream, "array overflow"); + 80027c8: 68fb ldr r3, [r7, #12] + 80027ca: 68db ldr r3, [r3, #12] + 80027cc: 2b00 cmp r3, #0 + 80027ce: d002 beq.n 80027d6 + 80027d0: 68fb ldr r3, [r7, #12] + 80027d2: 68db ldr r3, [r3, #12] + 80027d4: e000 b.n 80027d8 + 80027d6: 4b4f ldr r3, [pc, #316] ; (8002914 ) + 80027d8: 68fa ldr r2, [r7, #12] + 80027da: 60d3 str r3, [r2, #12] + 80027dc: 2300 movs r3, #0 + 80027de: e093 b.n 8002908 + if (!pb_close_string_substream(stream, &substream)) + 80027e0: f107 0314 add.w r3, r7, #20 + 80027e4: 4619 mov r1, r3 + 80027e6: 68f8 ldr r0, [r7, #12] + 80027e8: f7ff fe6e bl 80024c8 + 80027ec: 4603 mov r3, r0 + 80027ee: f083 0301 eor.w r3, r3, #1 + 80027f2: b2db uxtb r3, r3 + 80027f4: 2b00 cmp r3, #0 + 80027f6: d001 beq.n 80027fc + return false; + 80027f8: 2300 movs r3, #0 + 80027fa: e085 b.n 8002908 + + return status; + 80027fc: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8002800: e082 b.n 8002908 + } + else + { + /* Repeated field */ + pb_size_t *size = (pb_size_t*)field->pSize; + 8002802: 687b ldr r3, [r7, #4] + 8002804: 6a1b ldr r3, [r3, #32] + 8002806: 627b str r3, [r7, #36] ; 0x24 + field->pData = (char*)field->pField + field->data_size * (*size); + 8002808: 687b ldr r3, [r7, #4] + 800280a: 699b ldr r3, [r3, #24] + 800280c: 687a ldr r2, [r7, #4] + 800280e: 8a52 ldrh r2, [r2, #18] + 8002810: 4611 mov r1, r2 + 8002812: 6a7a ldr r2, [r7, #36] ; 0x24 + 8002814: 8812 ldrh r2, [r2, #0] + 8002816: fb02 f201 mul.w r2, r2, r1 + 800281a: 441a add r2, r3 + 800281c: 687b ldr r3, [r7, #4] + 800281e: 61da str r2, [r3, #28] + + if (!check_wire_type(wire_type, field)) + 8002820: 7afb ldrb r3, [r7, #11] + 8002822: 6879 ldr r1, [r7, #4] + 8002824: 4618 mov r0, r3 + 8002826: f7ff fe75 bl 8002514 + 800282a: 4603 mov r3, r0 + 800282c: f083 0301 eor.w r3, r3, #1 + 8002830: b2db uxtb r3, r3 + 8002832: 2b00 cmp r3, #0 + 8002834: d00b beq.n 800284e + PB_RETURN_ERROR(stream, "wrong wire type"); + 8002836: 68fb ldr r3, [r7, #12] + 8002838: 68db ldr r3, [r3, #12] + 800283a: 2b00 cmp r3, #0 + 800283c: d002 beq.n 8002844 + 800283e: 68fb ldr r3, [r7, #12] + 8002840: 68db ldr r3, [r3, #12] + 8002842: e000 b.n 8002846 + 8002844: 4b32 ldr r3, [pc, #200] ; (8002910 ) + 8002846: 68fa ldr r2, [r7, #12] + 8002848: 60d3 str r3, [r2, #12] + 800284a: 2300 movs r3, #0 + 800284c: e05c b.n 8002908 + + if ((*size)++ >= field->array_size) + 800284e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002850: 881b ldrh r3, [r3, #0] + 8002852: 1c5a adds r2, r3, #1 + 8002854: b291 uxth r1, r2 + 8002856: 6a7a ldr r2, [r7, #36] ; 0x24 + 8002858: 8011 strh r1, [r2, #0] + 800285a: 687a ldr r2, [r7, #4] + 800285c: 8a92 ldrh r2, [r2, #20] + 800285e: 4293 cmp r3, r2 + 8002860: d30b bcc.n 800287a + PB_RETURN_ERROR(stream, "array overflow"); + 8002862: 68fb ldr r3, [r7, #12] + 8002864: 68db ldr r3, [r3, #12] + 8002866: 2b00 cmp r3, #0 + 8002868: d002 beq.n 8002870 + 800286a: 68fb ldr r3, [r7, #12] + 800286c: 68db ldr r3, [r3, #12] + 800286e: e000 b.n 8002872 + 8002870: 4b28 ldr r3, [pc, #160] ; (8002914 ) + 8002872: 68fa ldr r2, [r7, #12] + 8002874: 60d3 str r3, [r2, #12] + 8002876: 2300 movs r3, #0 + 8002878: e046 b.n 8002908 + + return decode_basic_field(stream, field); + 800287a: 6879 ldr r1, [r7, #4] + 800287c: 68f8 ldr r0, [r7, #12] + 800287e: f7ff fe95 bl 80025ac + 8002882: 4603 mov r3, r0 + 8002884: e040 b.n 8002908 + } + + case PB_HTYPE_ONEOF: + *(pb_size_t*)field->pSize = field->tag; + 8002886: 687b ldr r3, [r7, #4] + 8002888: 6a1b ldr r3, [r3, #32] + 800288a: 687a ldr r2, [r7, #4] + 800288c: 8a12 ldrh r2, [r2, #16] + 800288e: 801a strh r2, [r3, #0] + if (PB_LTYPE_IS_SUBMSG(field->type)) + 8002890: 687b ldr r3, [r7, #4] + 8002892: 7d9b ldrb r3, [r3, #22] + 8002894: f003 030f and.w r3, r3, #15 + 8002898: 2b08 cmp r3, #8 + 800289a: d005 beq.n 80028a8 + 800289c: 687b ldr r3, [r7, #4] + 800289e: 7d9b ldrb r3, [r3, #22] + 80028a0: f003 030f and.w r3, r3, #15 + 80028a4: 2b09 cmp r3, #9 + 80028a6: d107 bne.n 80028b8 + * from some other union field. + * If callbacks are needed inside oneof field, use .proto + * option submsg_callback to have a separate callback function + * that can set the fields before submessage is decoded. + * pb_dec_submessage() will set any default values. */ + memset(field->pData, 0, (size_t)field->data_size); + 80028a8: 687b ldr r3, [r7, #4] + 80028aa: 69d8 ldr r0, [r3, #28] + 80028ac: 687b ldr r3, [r7, #4] + 80028ae: 8a5b ldrh r3, [r3, #18] + 80028b0: 461a mov r2, r3 + 80028b2: 2100 movs r1, #0 + 80028b4: f006 f882 bl 80089bc + } + + if (!check_wire_type(wire_type, field)) + 80028b8: 7afb ldrb r3, [r7, #11] + 80028ba: 6879 ldr r1, [r7, #4] + 80028bc: 4618 mov r0, r3 + 80028be: f7ff fe29 bl 8002514 + 80028c2: 4603 mov r3, r0 + 80028c4: f083 0301 eor.w r3, r3, #1 + 80028c8: b2db uxtb r3, r3 + 80028ca: 2b00 cmp r3, #0 + 80028cc: d00b beq.n 80028e6 + PB_RETURN_ERROR(stream, "wrong wire type"); + 80028ce: 68fb ldr r3, [r7, #12] + 80028d0: 68db ldr r3, [r3, #12] + 80028d2: 2b00 cmp r3, #0 + 80028d4: d002 beq.n 80028dc + 80028d6: 68fb ldr r3, [r7, #12] + 80028d8: 68db ldr r3, [r3, #12] + 80028da: e000 b.n 80028de + 80028dc: 4b0c ldr r3, [pc, #48] ; (8002910 ) + 80028de: 68fa ldr r2, [r7, #12] + 80028e0: 60d3 str r3, [r2, #12] + 80028e2: 2300 movs r3, #0 + 80028e4: e010 b.n 8002908 + + return decode_basic_field(stream, field); + 80028e6: 6879 ldr r1, [r7, #4] + 80028e8: 68f8 ldr r0, [r7, #12] + 80028ea: f7ff fe5f bl 80025ac + 80028ee: 4603 mov r3, r0 + 80028f0: e00a b.n 8002908 + + default: + PB_RETURN_ERROR(stream, "invalid field type"); + 80028f2: 68fb ldr r3, [r7, #12] + 80028f4: 68db ldr r3, [r3, #12] + 80028f6: 2b00 cmp r3, #0 + 80028f8: d002 beq.n 8002900 + 80028fa: 68fb ldr r3, [r7, #12] + 80028fc: 68db ldr r3, [r3, #12] + 80028fe: e000 b.n 8002902 + 8002900: 4b05 ldr r3, [pc, #20] ; (8002918 ) + 8002902: 68fa ldr r2, [r7, #12] + 8002904: 60d3 str r3, [r2, #12] + 8002906: 2300 movs r3, #0 + } +} + 8002908: 4618 mov r0, r3 + 800290a: 3730 adds r7, #48 ; 0x30 + 800290c: 46bd mov sp, r7 + 800290e: bd80 pop {r7, pc} + 8002910: 08008a50 .word 0x08008a50 + 8002914: 08008a60 .word 0x08008a60 + 8002918: 08008a3c .word 0x08008a3c + +0800291c : + } +} +#endif + +static bool checkreturn decode_pointer_field(pb_istream_t *stream, pb_wire_type_t wire_type, pb_field_iter_t *field) +{ + 800291c: b480 push {r7} + 800291e: b085 sub sp, #20 + 8002920: af00 add r7, sp, #0 + 8002922: 60f8 str r0, [r7, #12] + 8002924: 460b mov r3, r1 + 8002926: 607a str r2, [r7, #4] + 8002928: 72fb strb r3, [r7, #11] +#ifndef PB_ENABLE_MALLOC + PB_UNUSED(wire_type); + PB_UNUSED(field); + PB_RETURN_ERROR(stream, "no malloc support"); + 800292a: 68fb ldr r3, [r7, #12] + 800292c: 68db ldr r3, [r3, #12] + 800292e: 2b00 cmp r3, #0 + 8002930: d002 beq.n 8002938 + 8002932: 68fb ldr r3, [r7, #12] + 8002934: 68db ldr r3, [r3, #12] + 8002936: e000 b.n 800293a + 8002938: 4b04 ldr r3, [pc, #16] ; (800294c ) + 800293a: 68fa ldr r2, [r7, #12] + 800293c: 60d3 str r3, [r2, #12] + 800293e: 2300 movs r3, #0 + + default: + PB_RETURN_ERROR(stream, "invalid field type"); + } +#endif +} + 8002940: 4618 mov r0, r3 + 8002942: 3714 adds r7, #20 + 8002944: 46bd mov sp, r7 + 8002946: f85d 7b04 ldr.w r7, [sp], #4 + 800294a: 4770 bx lr + 800294c: 08008a70 .word 0x08008a70 + +08002950 : + +static bool checkreturn decode_callback_field(pb_istream_t *stream, pb_wire_type_t wire_type, pb_field_iter_t *field) +{ + 8002950: b590 push {r4, r7, lr} + 8002952: b097 sub sp, #92 ; 0x5c + 8002954: af00 add r7, sp, #0 + 8002956: 61f8 str r0, [r7, #28] + 8002958: 460b mov r3, r1 + 800295a: 617a str r2, [r7, #20] + 800295c: 76fb strb r3, [r7, #27] + if (!field->descriptor->field_callback) + 800295e: 697b ldr r3, [r7, #20] + 8002960: 681b ldr r3, [r3, #0] + 8002962: f8d3 300e ldr.w r3, [r3, #14] + 8002966: 2b00 cmp r3, #0 + 8002968: d106 bne.n 8002978 + return pb_skip_field(stream, wire_type); + 800296a: 7efb ldrb r3, [r7, #27] + 800296c: 4619 mov r1, r3 + 800296e: 69f8 ldr r0, [r7, #28] + 8002970: f7ff fcc6 bl 8002300 + 8002974: 4603 mov r3, r0 + 8002976: e06d b.n 8002a54 + + if (wire_type == PB_WT_STRING) + 8002978: 7efb ldrb r3, [r7, #27] + 800297a: 2b02 cmp r3, #2 + 800297c: d141 bne.n 8002a02 + { + pb_istream_t substream; + size_t prev_bytes_left; + + if (!pb_make_string_substream(stream, &substream)) + 800297e: f107 0344 add.w r3, r7, #68 ; 0x44 + 8002982: 4619 mov r1, r3 + 8002984: 69f8 ldr r0, [r7, #28] + 8002986: f7ff fd65 bl 8002454 + 800298a: 4603 mov r3, r0 + 800298c: f083 0301 eor.w r3, r3, #1 + 8002990: b2db uxtb r3, r3 + 8002992: 2b00 cmp r3, #0 + 8002994: d001 beq.n 800299a + return false; + 8002996: 2300 movs r3, #0 + 8002998: e05c b.n 8002a54 + + do + { + prev_bytes_left = substream.bytes_left; + 800299a: 6cfb ldr r3, [r7, #76] ; 0x4c + 800299c: 657b str r3, [r7, #84] ; 0x54 + if (!field->descriptor->field_callback(&substream, NULL, field)) + 800299e: 697b ldr r3, [r7, #20] + 80029a0: 681b ldr r3, [r3, #0] + 80029a2: f8d3 300e ldr.w r3, [r3, #14] + 80029a6: f107 0044 add.w r0, r7, #68 ; 0x44 + 80029aa: 697a ldr r2, [r7, #20] + 80029ac: 2100 movs r1, #0 + 80029ae: 4798 blx r3 + 80029b0: 4603 mov r3, r0 + 80029b2: f083 0301 eor.w r3, r3, #1 + 80029b6: b2db uxtb r3, r3 + 80029b8: 2b00 cmp r3, #0 + 80029ba: d00b beq.n 80029d4 + PB_RETURN_ERROR(stream, "callback failed"); + 80029bc: 69fb ldr r3, [r7, #28] + 80029be: 68db ldr r3, [r3, #12] + 80029c0: 2b00 cmp r3, #0 + 80029c2: d002 beq.n 80029ca + 80029c4: 69fb ldr r3, [r7, #28] + 80029c6: 68db ldr r3, [r3, #12] + 80029c8: e000 b.n 80029cc + 80029ca: 4b24 ldr r3, [pc, #144] ; (8002a5c ) + 80029cc: 69fa ldr r2, [r7, #28] + 80029ce: 60d3 str r3, [r2, #12] + 80029d0: 2300 movs r3, #0 + 80029d2: e03f b.n 8002a54 + } while (substream.bytes_left > 0 && substream.bytes_left < prev_bytes_left); + 80029d4: 6cfb ldr r3, [r7, #76] ; 0x4c + 80029d6: 2b00 cmp r3, #0 + 80029d8: d003 beq.n 80029e2 + 80029da: 6cfb ldr r3, [r7, #76] ; 0x4c + 80029dc: 6d7a ldr r2, [r7, #84] ; 0x54 + 80029de: 429a cmp r2, r3 + 80029e0: d8db bhi.n 800299a + + if (!pb_close_string_substream(stream, &substream)) + 80029e2: f107 0344 add.w r3, r7, #68 ; 0x44 + 80029e6: 4619 mov r1, r3 + 80029e8: 69f8 ldr r0, [r7, #28] + 80029ea: f7ff fd6d bl 80024c8 + 80029ee: 4603 mov r3, r0 + 80029f0: f083 0301 eor.w r3, r3, #1 + 80029f4: b2db uxtb r3, r3 + 80029f6: 2b00 cmp r3, #0 + 80029f8: d001 beq.n 80029fe + return false; + 80029fa: 2300 movs r3, #0 + 80029fc: e02a b.n 8002a54 + + return true; + 80029fe: 2301 movs r3, #1 + 8002a00: e028 b.n 8002a54 + * This is required so that we can limit the stream length, + * which in turn allows to use same callback for packed and + * not-packed fields. */ + pb_istream_t substream; + pb_byte_t buffer[10]; + size_t size = sizeof(buffer); + 8002a02: 230a movs r3, #10 + 8002a04: 627b str r3, [r7, #36] ; 0x24 + + if (!read_raw_value(stream, wire_type, buffer, &size)) + 8002a06: f107 0324 add.w r3, r7, #36 ; 0x24 + 8002a0a: f107 0228 add.w r2, r7, #40 ; 0x28 + 8002a0e: 7ef9 ldrb r1, [r7, #27] + 8002a10: 69f8 ldr r0, [r7, #28] + 8002a12: f7ff fcb7 bl 8002384 + 8002a16: 4603 mov r3, r0 + 8002a18: f083 0301 eor.w r3, r3, #1 + 8002a1c: b2db uxtb r3, r3 + 8002a1e: 2b00 cmp r3, #0 + 8002a20: d001 beq.n 8002a26 + return false; + 8002a22: 2300 movs r3, #0 + 8002a24: e016 b.n 8002a54 + substream = pb_istream_from_buffer(buffer, size); + 8002a26: 6a7a ldr r2, [r7, #36] ; 0x24 + 8002a28: 463b mov r3, r7 + 8002a2a: f107 0128 add.w r1, r7, #40 ; 0x28 + 8002a2e: 4618 mov r0, r3 + 8002a30: f7ff fae4 bl 8001ffc + 8002a34: f107 0434 add.w r4, r7, #52 ; 0x34 + 8002a38: 463b mov r3, r7 + 8002a3a: cb0f ldmia r3, {r0, r1, r2, r3} + 8002a3c: e884 000f stmia.w r4, {r0, r1, r2, r3} + + return field->descriptor->field_callback(&substream, NULL, field); + 8002a40: 697b ldr r3, [r7, #20] + 8002a42: 681b ldr r3, [r3, #0] + 8002a44: f8d3 300e ldr.w r3, [r3, #14] + 8002a48: f107 0034 add.w r0, r7, #52 ; 0x34 + 8002a4c: 697a ldr r2, [r7, #20] + 8002a4e: 2100 movs r1, #0 + 8002a50: 4798 blx r3 + 8002a52: 4603 mov r3, r0 + } +} + 8002a54: 4618 mov r0, r3 + 8002a56: 375c adds r7, #92 ; 0x5c + 8002a58: 46bd mov sp, r7 + 8002a5a: bd90 pop {r4, r7, pc} + 8002a5c: 08008a84 .word 0x08008a84 + +08002a60 : + +static bool checkreturn decode_field(pb_istream_t *stream, pb_wire_type_t wire_type, pb_field_iter_t *field) +{ + 8002a60: b580 push {r7, lr} + 8002a62: b084 sub sp, #16 + 8002a64: af00 add r7, sp, #0 + 8002a66: 60f8 str r0, [r7, #12] + 8002a68: 460b mov r3, r1 + 8002a6a: 607a str r2, [r7, #4] + 8002a6c: 72fb strb r3, [r7, #11] + if (!pb_release_union_field(stream, field)) + return false; + } +#endif + + switch (PB_ATYPE(field->type)) + 8002a6e: 687b ldr r3, [r7, #4] + 8002a70: 7d9b ldrb r3, [r3, #22] + 8002a72: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 8002a76: 2b40 cmp r3, #64 ; 0x40 + 8002a78: d013 beq.n 8002aa2 + 8002a7a: 2b80 cmp r3, #128 ; 0x80 + 8002a7c: d009 beq.n 8002a92 + 8002a7e: 2b00 cmp r3, #0 + 8002a80: d117 bne.n 8002ab2 + { + case PB_ATYPE_STATIC: + return decode_static_field(stream, wire_type, field); + 8002a82: 7afb ldrb r3, [r7, #11] + 8002a84: 687a ldr r2, [r7, #4] + 8002a86: 4619 mov r1, r3 + 8002a88: 68f8 ldr r0, [r7, #12] + 8002a8a: f7ff fdf1 bl 8002670 + 8002a8e: 4603 mov r3, r0 + 8002a90: e01a b.n 8002ac8 + + case PB_ATYPE_POINTER: + return decode_pointer_field(stream, wire_type, field); + 8002a92: 7afb ldrb r3, [r7, #11] + 8002a94: 687a ldr r2, [r7, #4] + 8002a96: 4619 mov r1, r3 + 8002a98: 68f8 ldr r0, [r7, #12] + 8002a9a: f7ff ff3f bl 800291c + 8002a9e: 4603 mov r3, r0 + 8002aa0: e012 b.n 8002ac8 + + case PB_ATYPE_CALLBACK: + return decode_callback_field(stream, wire_type, field); + 8002aa2: 7afb ldrb r3, [r7, #11] + 8002aa4: 687a ldr r2, [r7, #4] + 8002aa6: 4619 mov r1, r3 + 8002aa8: 68f8 ldr r0, [r7, #12] + 8002aaa: f7ff ff51 bl 8002950 + 8002aae: 4603 mov r3, r0 + 8002ab0: e00a b.n 8002ac8 + + default: + PB_RETURN_ERROR(stream, "invalid field type"); + 8002ab2: 68fb ldr r3, [r7, #12] + 8002ab4: 68db ldr r3, [r3, #12] + 8002ab6: 2b00 cmp r3, #0 + 8002ab8: d002 beq.n 8002ac0 + 8002aba: 68fb ldr r3, [r7, #12] + 8002abc: 68db ldr r3, [r3, #12] + 8002abe: e000 b.n 8002ac2 + 8002ac0: 4b03 ldr r3, [pc, #12] ; (8002ad0 ) + 8002ac2: 68fa ldr r2, [r7, #12] + 8002ac4: 60d3 str r3, [r2, #12] + 8002ac6: 2300 movs r3, #0 + } +} + 8002ac8: 4618 mov r0, r3 + 8002aca: 3710 adds r7, #16 + 8002acc: 46bd mov sp, r7 + 8002ace: bd80 pop {r7, pc} + 8002ad0: 08008a3c .word 0x08008a3c + +08002ad4 : +/* Default handler for extension fields. Expects to have a pb_msgdesc_t + * pointer in the extension->type->arg field, pointing to a message with + * only one field in it. */ +static bool checkreturn default_extension_decoder(pb_istream_t *stream, + pb_extension_t *extension, uint32_t tag, pb_wire_type_t wire_type) +{ + 8002ad4: b580 push {r7, lr} + 8002ad6: b08e sub sp, #56 ; 0x38 + 8002ad8: af00 add r7, sp, #0 + 8002ada: 60f8 str r0, [r7, #12] + 8002adc: 60b9 str r1, [r7, #8] + 8002ade: 607a str r2, [r7, #4] + 8002ae0: 70fb strb r3, [r7, #3] + pb_field_iter_t iter; + + if (!pb_field_iter_begin_extension(&iter, extension)) + 8002ae2: f107 0310 add.w r3, r7, #16 + 8002ae6: 68b9 ldr r1, [r7, #8] + 8002ae8: 4618 mov r0, r3 + 8002aea: f7ff f8f7 bl 8001cdc + 8002aee: 4603 mov r3, r0 + 8002af0: f083 0301 eor.w r3, r3, #1 + 8002af4: b2db uxtb r3, r3 + 8002af6: 2b00 cmp r3, #0 + 8002af8: d00b beq.n 8002b12 + PB_RETURN_ERROR(stream, "invalid extension"); + 8002afa: 68fb ldr r3, [r7, #12] + 8002afc: 68db ldr r3, [r3, #12] + 8002afe: 2b00 cmp r3, #0 + 8002b00: d002 beq.n 8002b08 + 8002b02: 68fb ldr r3, [r7, #12] + 8002b04: 68db ldr r3, [r3, #12] + 8002b06: e000 b.n 8002b0a + 8002b08: 4b0d ldr r3, [pc, #52] ; (8002b40 ) + 8002b0a: 68fa ldr r2, [r7, #12] + 8002b0c: 60d3 str r3, [r2, #12] + 8002b0e: 2300 movs r3, #0 + 8002b10: e011 b.n 8002b36 + + if (iter.tag != tag) + 8002b12: 8c3b ldrh r3, [r7, #32] + 8002b14: 461a mov r2, r3 + 8002b16: 687b ldr r3, [r7, #4] + 8002b18: 4293 cmp r3, r2 + 8002b1a: d001 beq.n 8002b20 + return true; + 8002b1c: 2301 movs r3, #1 + 8002b1e: e00a b.n 8002b36 + + extension->found = true; + 8002b20: 68bb ldr r3, [r7, #8] + 8002b22: 2201 movs r2, #1 + 8002b24: 731a strb r2, [r3, #12] + return decode_field(stream, wire_type, &iter); + 8002b26: f107 0210 add.w r2, r7, #16 + 8002b2a: 78fb ldrb r3, [r7, #3] + 8002b2c: 4619 mov r1, r3 + 8002b2e: 68f8 ldr r0, [r7, #12] + 8002b30: f7ff ff96 bl 8002a60 + 8002b34: 4603 mov r3, r0 +} + 8002b36: 4618 mov r0, r3 + 8002b38: 3738 adds r7, #56 ; 0x38 + 8002b3a: 46bd mov sp, r7 + 8002b3c: bd80 pop {r7, pc} + 8002b3e: bf00 nop + 8002b40: 08008a94 .word 0x08008a94 + +08002b44 : + +/* Try to decode an unknown field as an extension field. Tries each extension + * decoder in turn, until one of them handles the field or loop ends. */ +static bool checkreturn decode_extension(pb_istream_t *stream, + uint32_t tag, pb_wire_type_t wire_type, pb_field_iter_t *iter) +{ + 8002b44: b590 push {r4, r7, lr} + 8002b46: b089 sub sp, #36 ; 0x24 + 8002b48: af00 add r7, sp, #0 + 8002b4a: 60f8 str r0, [r7, #12] + 8002b4c: 60b9 str r1, [r7, #8] + 8002b4e: 603b str r3, [r7, #0] + 8002b50: 4613 mov r3, r2 + 8002b52: 71fb strb r3, [r7, #7] + pb_extension_t *extension = *(pb_extension_t* const *)iter->pData; + 8002b54: 683b ldr r3, [r7, #0] + 8002b56: 69db ldr r3, [r3, #28] + 8002b58: 681b ldr r3, [r3, #0] + 8002b5a: 61fb str r3, [r7, #28] + size_t pos = stream->bytes_left; + 8002b5c: 68fb ldr r3, [r7, #12] + 8002b5e: 689b ldr r3, [r3, #8] + 8002b60: 617b str r3, [r7, #20] + + while (extension != NULL && pos == stream->bytes_left) + 8002b62: e022 b.n 8002baa + { + bool status; + if (extension->type->decode) + 8002b64: 69fb ldr r3, [r7, #28] + 8002b66: 681b ldr r3, [r3, #0] + 8002b68: 681b ldr r3, [r3, #0] + 8002b6a: 2b00 cmp r3, #0 + 8002b6c: d00a beq.n 8002b84 + status = extension->type->decode(stream, extension, tag, wire_type); + 8002b6e: 69fb ldr r3, [r7, #28] + 8002b70: 681b ldr r3, [r3, #0] + 8002b72: 681c ldr r4, [r3, #0] + 8002b74: 79fb ldrb r3, [r7, #7] + 8002b76: 68ba ldr r2, [r7, #8] + 8002b78: 69f9 ldr r1, [r7, #28] + 8002b7a: 68f8 ldr r0, [r7, #12] + 8002b7c: 47a0 blx r4 + 8002b7e: 4603 mov r3, r0 + 8002b80: 76fb strb r3, [r7, #27] + 8002b82: e007 b.n 8002b94 + else + status = default_extension_decoder(stream, extension, tag, wire_type); + 8002b84: 79fb ldrb r3, [r7, #7] + 8002b86: 68ba ldr r2, [r7, #8] + 8002b88: 69f9 ldr r1, [r7, #28] + 8002b8a: 68f8 ldr r0, [r7, #12] + 8002b8c: f7ff ffa2 bl 8002ad4 + 8002b90: 4603 mov r3, r0 + 8002b92: 76fb strb r3, [r7, #27] + + if (!status) + 8002b94: 7efb ldrb r3, [r7, #27] + 8002b96: f083 0301 eor.w r3, r3, #1 + 8002b9a: b2db uxtb r3, r3 + 8002b9c: 2b00 cmp r3, #0 + 8002b9e: d001 beq.n 8002ba4 + return false; + 8002ba0: 2300 movs r3, #0 + 8002ba2: e00b b.n 8002bbc + + extension = extension->next; + 8002ba4: 69fb ldr r3, [r7, #28] + 8002ba6: 689b ldr r3, [r3, #8] + 8002ba8: 61fb str r3, [r7, #28] + while (extension != NULL && pos == stream->bytes_left) + 8002baa: 69fb ldr r3, [r7, #28] + 8002bac: 2b00 cmp r3, #0 + 8002bae: d004 beq.n 8002bba + 8002bb0: 68fb ldr r3, [r7, #12] + 8002bb2: 689b ldr r3, [r3, #8] + 8002bb4: 697a ldr r2, [r7, #20] + 8002bb6: 429a cmp r2, r3 + 8002bb8: d0d4 beq.n 8002b64 + } + + return true; + 8002bba: 2301 movs r3, #1 +} + 8002bbc: 4618 mov r0, r3 + 8002bbe: 3724 adds r7, #36 ; 0x24 + 8002bc0: 46bd mov sp, r7 + 8002bc2: bd90 pop {r4, r7, pc} + +08002bc4 : + +/* Step through the iterator until an extension field is found or until all + * entries have been checked. There can be only one extension field per + * message. Returns false if no extension field is found. */ +static bool checkreturn find_extension_field(pb_field_iter_t *iter) +{ + 8002bc4: b580 push {r7, lr} + 8002bc6: b084 sub sp, #16 + 8002bc8: af00 add r7, sp, #0 + 8002bca: 6078 str r0, [r7, #4] + pb_size_t start = iter->index; + 8002bcc: 687b ldr r3, [r7, #4] + 8002bce: 891b ldrh r3, [r3, #8] + 8002bd0: 81fb strh r3, [r7, #14] + + do { + if (PB_LTYPE(iter->type) == PB_LTYPE_EXTENSION) + 8002bd2: 687b ldr r3, [r7, #4] + 8002bd4: 7d9b ldrb r3, [r3, #22] + 8002bd6: f003 030f and.w r3, r3, #15 + 8002bda: 2b0a cmp r3, #10 + 8002bdc: d101 bne.n 8002be2 + return true; + 8002bde: 2301 movs r3, #1 + 8002be0: e008 b.n 8002bf4 + (void)pb_field_iter_next(iter); + 8002be2: 6878 ldr r0, [r7, #4] + 8002be4: f7ff f8ab bl 8001d3e + } while (iter->index != start); + 8002be8: 687b ldr r3, [r7, #4] + 8002bea: 891b ldrh r3, [r3, #8] + 8002bec: 89fa ldrh r2, [r7, #14] + 8002bee: 429a cmp r2, r3 + 8002bf0: d1ef bne.n 8002bd2 + + return false; + 8002bf2: 2300 movs r3, #0 +} + 8002bf4: 4618 mov r0, r3 + 8002bf6: 3710 adds r7, #16 + 8002bf8: 46bd mov sp, r7 + 8002bfa: bd80 pop {r7, pc} + +08002bfc : + +/* Initialize message fields to default values, recursively */ +static bool pb_field_set_to_default(pb_field_iter_t *field) +{ + 8002bfc: b580 push {r7, lr} + 8002bfe: b08e sub sp, #56 ; 0x38 + 8002c00: af00 add r7, sp, #0 + 8002c02: 6078 str r0, [r7, #4] + pb_type_t type; + type = field->type; + 8002c04: 687b ldr r3, [r7, #4] + 8002c06: 7d9b ldrb r3, [r3, #22] + 8002c08: f887 3032 strb.w r3, [r7, #50] ; 0x32 + + if (PB_LTYPE(type) == PB_LTYPE_EXTENSION) + 8002c0c: f897 3032 ldrb.w r3, [r7, #50] ; 0x32 + 8002c10: f003 030f and.w r3, r3, #15 + 8002c14: 2b0a cmp r3, #10 + 8002c16: d124 bne.n 8002c62 + { + pb_extension_t *ext = *(pb_extension_t* const *)field->pData; + 8002c18: 687b ldr r3, [r7, #4] + 8002c1a: 69db ldr r3, [r3, #28] + 8002c1c: 681b ldr r3, [r3, #0] + 8002c1e: 637b str r3, [r7, #52] ; 0x34 + while (ext != NULL) + 8002c20: e01b b.n 8002c5a + { + pb_field_iter_t ext_iter; + if (pb_field_iter_begin_extension(&ext_iter, ext)) + 8002c22: f107 0308 add.w r3, r7, #8 + 8002c26: 6b79 ldr r1, [r7, #52] ; 0x34 + 8002c28: 4618 mov r0, r3 + 8002c2a: f7ff f857 bl 8001cdc + 8002c2e: 4603 mov r3, r0 + 8002c30: 2b00 cmp r3, #0 + 8002c32: d00f beq.n 8002c54 + { + ext->found = false; + 8002c34: 6b7b ldr r3, [r7, #52] ; 0x34 + 8002c36: 2200 movs r2, #0 + 8002c38: 731a strb r2, [r3, #12] + if (!pb_message_set_to_defaults(&ext_iter)) + 8002c3a: f107 0308 add.w r3, r7, #8 + 8002c3e: 4618 mov r0, r3 + 8002c40: f000 f88d bl 8002d5e + 8002c44: 4603 mov r3, r0 + 8002c46: f083 0301 eor.w r3, r3, #1 + 8002c4a: b2db uxtb r3, r3 + 8002c4c: 2b00 cmp r3, #0 + 8002c4e: d001 beq.n 8002c54 + return false; + 8002c50: 2300 movs r3, #0 + 8002c52: e080 b.n 8002d56 + } + ext = ext->next; + 8002c54: 6b7b ldr r3, [r7, #52] ; 0x34 + 8002c56: 689b ldr r3, [r3, #8] + 8002c58: 637b str r3, [r7, #52] ; 0x34 + while (ext != NULL) + 8002c5a: 6b7b ldr r3, [r7, #52] ; 0x34 + 8002c5c: 2b00 cmp r3, #0 + 8002c5e: d1e0 bne.n 8002c22 + 8002c60: e078 b.n 8002d54 + } + } + else if (PB_ATYPE(type) == PB_ATYPE_STATIC) + 8002c62: f897 3032 ldrb.w r3, [r7, #50] ; 0x32 + 8002c66: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 8002c6a: 2b00 cmp r3, #0 + 8002c6c: d156 bne.n 8002d1c + { + bool init_data = true; + 8002c6e: 2301 movs r3, #1 + 8002c70: f887 3033 strb.w r3, [r7, #51] ; 0x33 + if (PB_HTYPE(type) == PB_HTYPE_OPTIONAL && field->pSize != NULL) + 8002c74: f897 3032 ldrb.w r3, [r7, #50] ; 0x32 + 8002c78: f003 0330 and.w r3, r3, #48 ; 0x30 + 8002c7c: 2b10 cmp r3, #16 + 8002c7e: d108 bne.n 8002c92 + 8002c80: 687b ldr r3, [r7, #4] + 8002c82: 6a1b ldr r3, [r3, #32] + 8002c84: 2b00 cmp r3, #0 + 8002c86: d004 beq.n 8002c92 + { + /* Set has_field to false. Still initialize the optional field + * itself also. */ + *(bool*)field->pSize = false; + 8002c88: 687b ldr r3, [r7, #4] + 8002c8a: 6a1b ldr r3, [r3, #32] + 8002c8c: 2200 movs r2, #0 + 8002c8e: 701a strb r2, [r3, #0] + 8002c90: e012 b.n 8002cb8 + } + else if (PB_HTYPE(type) == PB_HTYPE_REPEATED || + 8002c92: f897 3032 ldrb.w r3, [r7, #50] ; 0x32 + 8002c96: f003 0330 and.w r3, r3, #48 ; 0x30 + 8002c9a: 2b20 cmp r3, #32 + 8002c9c: d005 beq.n 8002caa + PB_HTYPE(type) == PB_HTYPE_ONEOF) + 8002c9e: f897 3032 ldrb.w r3, [r7, #50] ; 0x32 + 8002ca2: f003 0330 and.w r3, r3, #48 ; 0x30 + else if (PB_HTYPE(type) == PB_HTYPE_REPEATED || + 8002ca6: 2b30 cmp r3, #48 ; 0x30 + 8002ca8: d106 bne.n 8002cb8 + { + /* REPEATED: Set array count to 0, no need to initialize contents. + ONEOF: Set which_field to 0. */ + *(pb_size_t*)field->pSize = 0; + 8002caa: 687b ldr r3, [r7, #4] + 8002cac: 6a1b ldr r3, [r3, #32] + 8002cae: 2200 movs r2, #0 + 8002cb0: 801a strh r2, [r3, #0] + init_data = false; + 8002cb2: 2300 movs r3, #0 + 8002cb4: f887 3033 strb.w r3, [r7, #51] ; 0x33 + } + + if (init_data) + 8002cb8: f897 3033 ldrb.w r3, [r7, #51] ; 0x33 + 8002cbc: 2b00 cmp r3, #0 + 8002cbe: d049 beq.n 8002d54 + { + if (PB_LTYPE_IS_SUBMSG(field->type)) + 8002cc0: 687b ldr r3, [r7, #4] + 8002cc2: 7d9b ldrb r3, [r3, #22] + 8002cc4: f003 030f and.w r3, r3, #15 + 8002cc8: 2b08 cmp r3, #8 + 8002cca: d005 beq.n 8002cd8 + 8002ccc: 687b ldr r3, [r7, #4] + 8002cce: 7d9b ldrb r3, [r3, #22] + 8002cd0: f003 030f and.w r3, r3, #15 + 8002cd4: 2b09 cmp r3, #9 + 8002cd6: d118 bne.n 8002d0a + { + /* Initialize submessage to defaults */ + pb_field_iter_t submsg_iter; + if (pb_field_iter_begin(&submsg_iter, field->submsg_desc, field->pData)) + 8002cd8: 687b ldr r3, [r7, #4] + 8002cda: 6a59 ldr r1, [r3, #36] ; 0x24 + 8002cdc: 687b ldr r3, [r7, #4] + 8002cde: 69da ldr r2, [r3, #28] + 8002ce0: f107 0308 add.w r3, r7, #8 + 8002ce4: 4618 mov r0, r3 + 8002ce6: f7fe ffe0 bl 8001caa + 8002cea: 4603 mov r3, r0 + 8002cec: 2b00 cmp r3, #0 + 8002cee: d030 beq.n 8002d52 + { + if (!pb_message_set_to_defaults(&submsg_iter)) + 8002cf0: f107 0308 add.w r3, r7, #8 + 8002cf4: 4618 mov r0, r3 + 8002cf6: f000 f832 bl 8002d5e + 8002cfa: 4603 mov r3, r0 + 8002cfc: f083 0301 eor.w r3, r3, #1 + 8002d00: b2db uxtb r3, r3 + 8002d02: 2b00 cmp r3, #0 + 8002d04: d025 beq.n 8002d52 + return false; + 8002d06: 2300 movs r3, #0 + 8002d08: e025 b.n 8002d56 + } + } + else + { + /* Initialize to zeros */ + memset(field->pData, 0, (size_t)field->data_size); + 8002d0a: 687b ldr r3, [r7, #4] + 8002d0c: 69d8 ldr r0, [r3, #28] + 8002d0e: 687b ldr r3, [r7, #4] + 8002d10: 8a5b ldrh r3, [r3, #18] + 8002d12: 461a mov r2, r3 + 8002d14: 2100 movs r1, #0 + 8002d16: f005 fe51 bl 80089bc + 8002d1a: e01b b.n 8002d54 + } + } + } + else if (PB_ATYPE(type) == PB_ATYPE_POINTER) + 8002d1c: f897 3032 ldrb.w r3, [r7, #50] ; 0x32 + 8002d20: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 8002d24: 2b80 cmp r3, #128 ; 0x80 + 8002d26: d115 bne.n 8002d54 + { + /* Initialize the pointer to NULL. */ + *(void**)field->pField = NULL; + 8002d28: 687b ldr r3, [r7, #4] + 8002d2a: 699b ldr r3, [r3, #24] + 8002d2c: 2200 movs r2, #0 + 8002d2e: 601a str r2, [r3, #0] + + /* Initialize array count to 0. */ + if (PB_HTYPE(type) == PB_HTYPE_REPEATED || + 8002d30: f897 3032 ldrb.w r3, [r7, #50] ; 0x32 + 8002d34: f003 0330 and.w r3, r3, #48 ; 0x30 + 8002d38: 2b20 cmp r3, #32 + 8002d3a: d005 beq.n 8002d48 + PB_HTYPE(type) == PB_HTYPE_ONEOF) + 8002d3c: f897 3032 ldrb.w r3, [r7, #50] ; 0x32 + 8002d40: f003 0330 and.w r3, r3, #48 ; 0x30 + if (PB_HTYPE(type) == PB_HTYPE_REPEATED || + 8002d44: 2b30 cmp r3, #48 ; 0x30 + 8002d46: d105 bne.n 8002d54 + { + *(pb_size_t*)field->pSize = 0; + 8002d48: 687b ldr r3, [r7, #4] + 8002d4a: 6a1b ldr r3, [r3, #32] + 8002d4c: 2200 movs r2, #0 + 8002d4e: 801a strh r2, [r3, #0] + 8002d50: e000 b.n 8002d54 + { + 8002d52: bf00 nop + else if (PB_ATYPE(type) == PB_ATYPE_CALLBACK) + { + /* Don't overwrite callback */ + } + + return true; + 8002d54: 2301 movs r3, #1 +} + 8002d56: 4618 mov r0, r3 + 8002d58: 3738 adds r7, #56 ; 0x38 + 8002d5a: 46bd mov sp, r7 + 8002d5c: bd80 pop {r7, pc} + +08002d5e : + +static bool pb_message_set_to_defaults(pb_field_iter_t *iter) +{ + 8002d5e: b590 push {r4, r7, lr} + 8002d60: b08d sub sp, #52 ; 0x34 + 8002d62: af00 add r7, sp, #0 + 8002d64: 6178 str r0, [r7, #20] + pb_istream_t defstream = PB_ISTREAM_EMPTY; + 8002d66: f107 0320 add.w r3, r7, #32 + 8002d6a: 2200 movs r2, #0 + 8002d6c: 601a str r2, [r3, #0] + 8002d6e: 605a str r2, [r3, #4] + 8002d70: 609a str r2, [r3, #8] + 8002d72: 60da str r2, [r3, #12] + uint32_t tag = 0; + 8002d74: 2300 movs r3, #0 + 8002d76: 61fb str r3, [r7, #28] + pb_wire_type_t wire_type = PB_WT_VARINT; + 8002d78: 2300 movs r3, #0 + 8002d7a: 76fb strb r3, [r7, #27] + bool eof; + + if (iter->descriptor->default_value) + 8002d7c: 697b ldr r3, [r7, #20] + 8002d7e: 681b ldr r3, [r3, #0] + 8002d80: f8d3 300a ldr.w r3, [r3, #10] + 8002d84: 2b00 cmp r3, #0 + 8002d86: d021 beq.n 8002dcc + { + defstream = pb_istream_from_buffer(iter->descriptor->default_value, (size_t)-1); + 8002d88: 697b ldr r3, [r7, #20] + 8002d8a: 681b ldr r3, [r3, #0] + 8002d8c: f8d3 100a ldr.w r1, [r3, #10] + 8002d90: 463b mov r3, r7 + 8002d92: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 8002d96: 4618 mov r0, r3 + 8002d98: f7ff f930 bl 8001ffc + 8002d9c: f107 0420 add.w r4, r7, #32 + 8002da0: 463b mov r3, r7 + 8002da2: cb0f ldmia r3, {r0, r1, r2, r3} + 8002da4: e884 000f stmia.w r4, {r0, r1, r2, r3} + if (!pb_decode_tag(&defstream, &wire_type, &tag, &eof)) + 8002da8: f107 031a add.w r3, r7, #26 + 8002dac: f107 021c add.w r2, r7, #28 + 8002db0: f107 011b add.w r1, r7, #27 + 8002db4: f107 0020 add.w r0, r7, #32 + 8002db8: f7ff fa73 bl 80022a2 + 8002dbc: 4603 mov r3, r0 + 8002dbe: f083 0301 eor.w r3, r3, #1 + 8002dc2: b2db uxtb r3, r3 + 8002dc4: 2b00 cmp r3, #0 + 8002dc6: d001 beq.n 8002dcc + return false; + 8002dc8: 2300 movs r3, #0 + 8002dca: e043 b.n 8002e54 + } + + do + { + if (!pb_field_set_to_default(iter)) + 8002dcc: 6978 ldr r0, [r7, #20] + 8002dce: f7ff ff15 bl 8002bfc + 8002dd2: 4603 mov r3, r0 + 8002dd4: f083 0301 eor.w r3, r3, #1 + 8002dd8: b2db uxtb r3, r3 + 8002dda: 2b00 cmp r3, #0 + 8002ddc: d001 beq.n 8002de2 + return false; + 8002dde: 2300 movs r3, #0 + 8002de0: e038 b.n 8002e54 + + if (tag != 0 && iter->tag == tag) + 8002de2: 69fb ldr r3, [r7, #28] + 8002de4: 2b00 cmp r3, #0 + 8002de6: d02e beq.n 8002e46 + 8002de8: 697b ldr r3, [r7, #20] + 8002dea: 8a1b ldrh r3, [r3, #16] + 8002dec: 461a mov r2, r3 + 8002dee: 69fb ldr r3, [r7, #28] + 8002df0: 429a cmp r2, r3 + 8002df2: d128 bne.n 8002e46 + { + /* We have a default value for this field in the defstream */ + if (!decode_field(&defstream, wire_type, iter)) + 8002df4: 7ef9 ldrb r1, [r7, #27] + 8002df6: f107 0320 add.w r3, r7, #32 + 8002dfa: 697a ldr r2, [r7, #20] + 8002dfc: 4618 mov r0, r3 + 8002dfe: f7ff fe2f bl 8002a60 + 8002e02: 4603 mov r3, r0 + 8002e04: f083 0301 eor.w r3, r3, #1 + 8002e08: b2db uxtb r3, r3 + 8002e0a: 2b00 cmp r3, #0 + 8002e0c: d001 beq.n 8002e12 + return false; + 8002e0e: 2300 movs r3, #0 + 8002e10: e020 b.n 8002e54 + if (!pb_decode_tag(&defstream, &wire_type, &tag, &eof)) + 8002e12: f107 031a add.w r3, r7, #26 + 8002e16: f107 021c add.w r2, r7, #28 + 8002e1a: f107 011b add.w r1, r7, #27 + 8002e1e: f107 0020 add.w r0, r7, #32 + 8002e22: f7ff fa3e bl 80022a2 + 8002e26: 4603 mov r3, r0 + 8002e28: f083 0301 eor.w r3, r3, #1 + 8002e2c: b2db uxtb r3, r3 + 8002e2e: 2b00 cmp r3, #0 + 8002e30: d001 beq.n 8002e36 + return false; + 8002e32: 2300 movs r3, #0 + 8002e34: e00e b.n 8002e54 + + if (iter->pSize) + 8002e36: 697b ldr r3, [r7, #20] + 8002e38: 6a1b ldr r3, [r3, #32] + 8002e3a: 2b00 cmp r3, #0 + 8002e3c: d003 beq.n 8002e46 + *(bool*)iter->pSize = false; + 8002e3e: 697b ldr r3, [r7, #20] + 8002e40: 6a1b ldr r3, [r3, #32] + 8002e42: 2200 movs r2, #0 + 8002e44: 701a strb r2, [r3, #0] + } + } while (pb_field_iter_next(iter)); + 8002e46: 6978 ldr r0, [r7, #20] + 8002e48: f7fe ff79 bl 8001d3e + 8002e4c: 4603 mov r3, r0 + 8002e4e: 2b00 cmp r3, #0 + 8002e50: d1bc bne.n 8002dcc + + return true; + 8002e52: 2301 movs r3, #1 +} + 8002e54: 4618 mov r0, r3 + 8002e56: 3734 adds r7, #52 ; 0x34 + 8002e58: 46bd mov sp, r7 + 8002e5a: bd90 pop {r4, r7, pc} + +08002e5c : +/********************* + * Decode all fields * + *********************/ + +static bool checkreturn pb_decode_inner(pb_istream_t *stream, const pb_msgdesc_t *fields, void *dest_struct, unsigned int flags) +{ + 8002e5c: b580 push {r7, lr} + 8002e5e: b09a sub sp, #104 ; 0x68 + 8002e60: af00 add r7, sp, #0 + 8002e62: 60f8 str r0, [r7, #12] + 8002e64: 60b9 str r1, [r7, #8] + 8002e66: 607a str r2, [r7, #4] + 8002e68: 603b str r3, [r7, #0] + uint32_t extension_range_start = 0; + 8002e6a: 2300 movs r3, #0 + 8002e6c: 667b str r3, [r7, #100] ; 0x64 + + /* 'fixed_count_field' and 'fixed_count_size' track position of a repeated fixed + * count field. This can only handle _one_ repeated fixed count field that + * is unpacked and unordered among other (non repeated fixed count) fields. + */ + pb_size_t fixed_count_field = PB_SIZE_MAX; + 8002e6e: f64f 73ff movw r3, #65535 ; 0xffff + 8002e72: f8a7 3062 strh.w r3, [r7, #98] ; 0x62 + pb_size_t fixed_count_size = 0; + 8002e76: 2300 movs r3, #0 + 8002e78: f8a7 304c strh.w r3, [r7, #76] ; 0x4c + pb_size_t fixed_count_total_size = 0; + 8002e7c: 2300 movs r3, #0 + 8002e7e: f8a7 3060 strh.w r3, [r7, #96] ; 0x60 + + pb_fields_seen_t fields_seen = {{0, 0}}; + 8002e82: 2300 movs r3, #0 + 8002e84: 647b str r3, [r7, #68] ; 0x44 + 8002e86: 2300 movs r3, #0 + 8002e88: 64bb str r3, [r7, #72] ; 0x48 + const uint32_t allbits = ~(uint32_t)0; + 8002e8a: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8002e8e: 65bb str r3, [r7, #88] ; 0x58 + pb_field_iter_t iter; + + /* Return value ignored, as empty message types will be correctly handled by + * pb_field_iter_find() anyway. */ + (void)pb_field_iter_begin(&iter, fields, dest_struct); + 8002e90: f107 031c add.w r3, r7, #28 + 8002e94: 687a ldr r2, [r7, #4] + 8002e96: 68b9 ldr r1, [r7, #8] + 8002e98: 4618 mov r0, r3 + 8002e9a: f7fe ff06 bl 8001caa + + while (stream->bytes_left) + 8002e9e: e0e5 b.n 800306c + { + uint32_t tag; + pb_wire_type_t wire_type; + bool eof; + + if (!pb_decode_tag(stream, &wire_type, &tag, &eof)) + 8002ea0: f107 0316 add.w r3, r7, #22 + 8002ea4: f107 0218 add.w r2, r7, #24 + 8002ea8: f107 0117 add.w r1, r7, #23 + 8002eac: 68f8 ldr r0, [r7, #12] + 8002eae: f7ff f9f8 bl 80022a2 + 8002eb2: 4603 mov r3, r0 + 8002eb4: f083 0301 eor.w r3, r3, #1 + 8002eb8: b2db uxtb r3, r3 + 8002eba: 2b00 cmp r3, #0 + 8002ebc: d005 beq.n 8002eca + { + if (eof) + 8002ebe: 7dbb ldrb r3, [r7, #22] + 8002ec0: 2b00 cmp r3, #0 + 8002ec2: f040 80d9 bne.w 8003078 + break; + else + return false; + 8002ec6: 2300 movs r3, #0 + 8002ec8: e16c b.n 80031a4 + } + + if (tag == 0) + 8002eca: 69bb ldr r3, [r7, #24] + 8002ecc: 2b00 cmp r3, #0 + 8002ece: d111 bne.n 8002ef4 + { + if (flags & PB_DECODE_NULLTERMINATED) + 8002ed0: 683b ldr r3, [r7, #0] + 8002ed2: f003 0304 and.w r3, r3, #4 + 8002ed6: 2b00 cmp r3, #0 + 8002ed8: f040 80d0 bne.w 800307c + { + break; + } + else + { + PB_RETURN_ERROR(stream, "zero tag"); + 8002edc: 68fb ldr r3, [r7, #12] + 8002ede: 68db ldr r3, [r3, #12] + 8002ee0: 2b00 cmp r3, #0 + 8002ee2: d002 beq.n 8002eea + 8002ee4: 68fb ldr r3, [r7, #12] + 8002ee6: 68db ldr r3, [r3, #12] + 8002ee8: e000 b.n 8002eec + 8002eea: 4bb0 ldr r3, [pc, #704] ; (80031ac ) + 8002eec: 68fa ldr r2, [r7, #12] + 8002eee: 60d3 str r3, [r2, #12] + 8002ef0: 2300 movs r3, #0 + 8002ef2: e157 b.n 80031a4 + } + } + + if (!pb_field_iter_find(&iter, tag) || PB_LTYPE(iter.type) == PB_LTYPE_EXTENSION) + 8002ef4: 69ba ldr r2, [r7, #24] + 8002ef6: f107 031c add.w r3, r7, #28 + 8002efa: 4611 mov r1, r2 + 8002efc: 4618 mov r0, r3 + 8002efe: f7fe ff33 bl 8001d68 + 8002f02: 4603 mov r3, r0 + 8002f04: f083 0301 eor.w r3, r3, #1 + 8002f08: b2db uxtb r3, r3 + 8002f0a: 2b00 cmp r3, #0 + 8002f0c: d105 bne.n 8002f1a + 8002f0e: f897 3032 ldrb.w r3, [r7, #50] ; 0x32 + 8002f12: f003 030f and.w r3, r3, #15 + 8002f16: 2b0a cmp r3, #10 + 8002f18: d13c bne.n 8002f94 + { + /* No match found, check if it matches an extension. */ + if (tag >= extension_range_start) + 8002f1a: 69bb ldr r3, [r7, #24] + 8002f1c: 6e7a ldr r2, [r7, #100] ; 0x64 + 8002f1e: 429a cmp r2, r3 + 8002f20: d82b bhi.n 8002f7a + { + if (!find_extension_field(&iter)) + 8002f22: f107 031c add.w r3, r7, #28 + 8002f26: 4618 mov r0, r3 + 8002f28: f7ff fe4c bl 8002bc4 + 8002f2c: 4603 mov r3, r0 + 8002f2e: f083 0301 eor.w r3, r3, #1 + 8002f32: b2db uxtb r3, r3 + 8002f34: 2b00 cmp r3, #0 + 8002f36: d003 beq.n 8002f40 + extension_range_start = (uint32_t)-1; + 8002f38: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8002f3c: 667b str r3, [r7, #100] ; 0x64 + 8002f3e: e001 b.n 8002f44 + else + extension_range_start = iter.tag; + 8002f40: 8dbb ldrh r3, [r7, #44] ; 0x2c + 8002f42: 667b str r3, [r7, #100] ; 0x64 + + if (tag >= extension_range_start) + 8002f44: 69bb ldr r3, [r7, #24] + 8002f46: 6e7a ldr r2, [r7, #100] ; 0x64 + 8002f48: 429a cmp r2, r3 + 8002f4a: d816 bhi.n 8002f7a + { + size_t pos = stream->bytes_left; + 8002f4c: 68fb ldr r3, [r7, #12] + 8002f4e: 689b ldr r3, [r3, #8] + 8002f50: 653b str r3, [r7, #80] ; 0x50 + + if (!decode_extension(stream, tag, wire_type, &iter)) + 8002f52: 69b9 ldr r1, [r7, #24] + 8002f54: 7dfa ldrb r2, [r7, #23] + 8002f56: f107 031c add.w r3, r7, #28 + 8002f5a: 68f8 ldr r0, [r7, #12] + 8002f5c: f7ff fdf2 bl 8002b44 + 8002f60: 4603 mov r3, r0 + 8002f62: f083 0301 eor.w r3, r3, #1 + 8002f66: b2db uxtb r3, r3 + 8002f68: 2b00 cmp r3, #0 + 8002f6a: d001 beq.n 8002f70 + return false; + 8002f6c: 2300 movs r3, #0 + 8002f6e: e119 b.n 80031a4 + + if (pos != stream->bytes_left) + 8002f70: 68fb ldr r3, [r7, #12] + 8002f72: 689b ldr r3, [r3, #8] + 8002f74: 6d3a ldr r2, [r7, #80] ; 0x50 + 8002f76: 429a cmp r2, r3 + 8002f78: d175 bne.n 8003066 + } + } + } + + /* No match found, skip data */ + if (!pb_skip_field(stream, wire_type)) + 8002f7a: 7dfb ldrb r3, [r7, #23] + 8002f7c: 4619 mov r1, r3 + 8002f7e: 68f8 ldr r0, [r7, #12] + 8002f80: f7ff f9be bl 8002300 + 8002f84: 4603 mov r3, r0 + 8002f86: f083 0301 eor.w r3, r3, #1 + 8002f8a: b2db uxtb r3, r3 + 8002f8c: 2b00 cmp r3, #0 + 8002f8e: d06c beq.n 800306a + return false; + 8002f90: 2300 movs r3, #0 + 8002f92: e107 b.n 80031a4 + } + + /* If a repeated fixed count field was found, get size from + * 'fixed_count_field' as there is no counter contained in the struct. + */ + if (PB_HTYPE(iter.type) == PB_HTYPE_REPEATED && iter.pSize == &iter.array_size) + 8002f94: f897 3032 ldrb.w r3, [r7, #50] ; 0x32 + 8002f98: f003 0330 and.w r3, r3, #48 ; 0x30 + 8002f9c: 2b20 cmp r3, #32 + 8002f9e: d12e bne.n 8002ffe + 8002fa0: 6bfa ldr r2, [r7, #60] ; 0x3c + 8002fa2: f107 031c add.w r3, r7, #28 + 8002fa6: 3314 adds r3, #20 + 8002fa8: 429a cmp r2, r3 + 8002faa: d128 bne.n 8002ffe + { + if (fixed_count_field != iter.index) { + 8002fac: 8cbb ldrh r3, [r7, #36] ; 0x24 + 8002fae: f8b7 2062 ldrh.w r2, [r7, #98] ; 0x62 + 8002fb2: 429a cmp r2, r3 + 8002fb4: d020 beq.n 8002ff8 + /* If the new fixed count field does not match the previous one, + * check that the previous one is NULL or that it finished + * receiving all the expected data. + */ + if (fixed_count_field != PB_SIZE_MAX && + 8002fb6: f8b7 3062 ldrh.w r3, [r7, #98] ; 0x62 + 8002fba: f64f 72ff movw r2, #65535 ; 0xffff + 8002fbe: 4293 cmp r3, r2 + 8002fc0: d011 beq.n 8002fe6 + fixed_count_size != fixed_count_total_size) + 8002fc2: f8b7 304c ldrh.w r3, [r7, #76] ; 0x4c + if (fixed_count_field != PB_SIZE_MAX && + 8002fc6: f8b7 2060 ldrh.w r2, [r7, #96] ; 0x60 + 8002fca: 429a cmp r2, r3 + 8002fcc: d00b beq.n 8002fe6 + { + PB_RETURN_ERROR(stream, "wrong size for fixed count field"); + 8002fce: 68fb ldr r3, [r7, #12] + 8002fd0: 68db ldr r3, [r3, #12] + 8002fd2: 2b00 cmp r3, #0 + 8002fd4: d002 beq.n 8002fdc + 8002fd6: 68fb ldr r3, [r7, #12] + 8002fd8: 68db ldr r3, [r3, #12] + 8002fda: e000 b.n 8002fde + 8002fdc: 4b74 ldr r3, [pc, #464] ; (80031b0 ) + 8002fde: 68fa ldr r2, [r7, #12] + 8002fe0: 60d3 str r3, [r2, #12] + 8002fe2: 2300 movs r3, #0 + 8002fe4: e0de b.n 80031a4 + } + + fixed_count_field = iter.index; + 8002fe6: 8cbb ldrh r3, [r7, #36] ; 0x24 + 8002fe8: f8a7 3062 strh.w r3, [r7, #98] ; 0x62 + fixed_count_size = 0; + 8002fec: 2300 movs r3, #0 + 8002fee: f8a7 304c strh.w r3, [r7, #76] ; 0x4c + fixed_count_total_size = iter.array_size; + 8002ff2: 8e3b ldrh r3, [r7, #48] ; 0x30 + 8002ff4: f8a7 3060 strh.w r3, [r7, #96] ; 0x60 + } + + iter.pSize = &fixed_count_size; + 8002ff8: f107 034c add.w r3, r7, #76 ; 0x4c + 8002ffc: 63fb str r3, [r7, #60] ; 0x3c + } + + if (PB_HTYPE(iter.type) == PB_HTYPE_REQUIRED + 8002ffe: f897 3032 ldrb.w r3, [r7, #50] ; 0x32 + 8003002: f003 0330 and.w r3, r3, #48 ; 0x30 + 8003006: 2b00 cmp r3, #0 + 8003008: d11e bne.n 8003048 + && iter.required_field_index < PB_MAX_REQUIRED_FIELDS) + 800300a: 8d3b ldrh r3, [r7, #40] ; 0x28 + 800300c: 2b3f cmp r3, #63 ; 0x3f + 800300e: d81b bhi.n 8003048 + { + uint32_t tmp = ((uint32_t)1 << (iter.required_field_index & 31)); + 8003010: 8d3b ldrh r3, [r7, #40] ; 0x28 + 8003012: f003 031f and.w r3, r3, #31 + 8003016: 2201 movs r2, #1 + 8003018: fa02 f303 lsl.w r3, r2, r3 + 800301c: 657b str r3, [r7, #84] ; 0x54 + fields_seen.bitfield[iter.required_field_index >> 5] |= tmp; + 800301e: 8d3b ldrh r3, [r7, #40] ; 0x28 + 8003020: 095b lsrs r3, r3, #5 + 8003022: b29b uxth r3, r3 + 8003024: 009b lsls r3, r3, #2 + 8003026: f107 0268 add.w r2, r7, #104 ; 0x68 + 800302a: 4413 add r3, r2 + 800302c: f853 2c24 ldr.w r2, [r3, #-36] + 8003030: 8d3b ldrh r3, [r7, #40] ; 0x28 + 8003032: 095b lsrs r3, r3, #5 + 8003034: b29b uxth r3, r3 + 8003036: 4619 mov r1, r3 + 8003038: 6d7b ldr r3, [r7, #84] ; 0x54 + 800303a: 431a orrs r2, r3 + 800303c: 008b lsls r3, r1, #2 + 800303e: f107 0168 add.w r1, r7, #104 ; 0x68 + 8003042: 440b add r3, r1 + 8003044: f843 2c24 str.w r2, [r3, #-36] + } + + if (!decode_field(stream, wire_type, &iter)) + 8003048: 7dfb ldrb r3, [r7, #23] + 800304a: f107 021c add.w r2, r7, #28 + 800304e: 4619 mov r1, r3 + 8003050: 68f8 ldr r0, [r7, #12] + 8003052: f7ff fd05 bl 8002a60 + 8003056: 4603 mov r3, r0 + 8003058: f083 0301 eor.w r3, r3, #1 + 800305c: b2db uxtb r3, r3 + 800305e: 2b00 cmp r3, #0 + 8003060: d004 beq.n 800306c + return false; + 8003062: 2300 movs r3, #0 + 8003064: e09e b.n 80031a4 + continue; + 8003066: bf00 nop + 8003068: e000 b.n 800306c + continue; + 800306a: bf00 nop + while (stream->bytes_left) + 800306c: 68fb ldr r3, [r7, #12] + 800306e: 689b ldr r3, [r3, #8] + 8003070: 2b00 cmp r3, #0 + 8003072: f47f af15 bne.w 8002ea0 + 8003076: e002 b.n 800307e + break; + 8003078: bf00 nop + 800307a: e000 b.n 800307e + break; + 800307c: bf00 nop + } + + /* Check that all elements of the last decoded fixed count field were present. */ + if (fixed_count_field != PB_SIZE_MAX && + 800307e: f8b7 3062 ldrh.w r3, [r7, #98] ; 0x62 + 8003082: f64f 72ff movw r2, #65535 ; 0xffff + 8003086: 4293 cmp r3, r2 + 8003088: d011 beq.n 80030ae + fixed_count_size != fixed_count_total_size) + 800308a: f8b7 304c ldrh.w r3, [r7, #76] ; 0x4c + if (fixed_count_field != PB_SIZE_MAX && + 800308e: f8b7 2060 ldrh.w r2, [r7, #96] ; 0x60 + 8003092: 429a cmp r2, r3 + 8003094: d00b beq.n 80030ae + { + PB_RETURN_ERROR(stream, "wrong size for fixed count field"); + 8003096: 68fb ldr r3, [r7, #12] + 8003098: 68db ldr r3, [r3, #12] + 800309a: 2b00 cmp r3, #0 + 800309c: d002 beq.n 80030a4 + 800309e: 68fb ldr r3, [r7, #12] + 80030a0: 68db ldr r3, [r3, #12] + 80030a2: e000 b.n 80030a6 + 80030a4: 4b42 ldr r3, [pc, #264] ; (80031b0 ) + 80030a6: 68fa ldr r2, [r7, #12] + 80030a8: 60d3 str r3, [r2, #12] + 80030aa: 2300 movs r3, #0 + 80030ac: e07a b.n 80031a4 + */ + pb_size_t req_field_count; + pb_type_t last_type; + pb_size_t i; + do { + req_field_count = iter.required_field_index; + 80030ae: 8d3b ldrh r3, [r7, #40] ; 0x28 + 80030b0: f8a7 305e strh.w r3, [r7, #94] ; 0x5e + last_type = iter.type; + 80030b4: f897 3032 ldrb.w r3, [r7, #50] ; 0x32 + 80030b8: f887 304f strb.w r3, [r7, #79] ; 0x4f + } while (pb_field_iter_next(&iter)); + 80030bc: f107 031c add.w r3, r7, #28 + 80030c0: 4618 mov r0, r3 + 80030c2: f7fe fe3c bl 8001d3e + 80030c6: 4603 mov r3, r0 + 80030c8: 2b00 cmp r3, #0 + 80030ca: d1f0 bne.n 80030ae + + /* Fixup if last field was also required. */ + if (PB_HTYPE(last_type) == PB_HTYPE_REQUIRED && iter.tag != 0) + 80030cc: f897 304f ldrb.w r3, [r7, #79] ; 0x4f + 80030d0: f003 0330 and.w r3, r3, #48 ; 0x30 + 80030d4: 2b00 cmp r3, #0 + 80030d6: d107 bne.n 80030e8 + 80030d8: 8dbb ldrh r3, [r7, #44] ; 0x2c + 80030da: 2b00 cmp r3, #0 + 80030dc: d004 beq.n 80030e8 + req_field_count++; + 80030de: f8b7 305e ldrh.w r3, [r7, #94] ; 0x5e + 80030e2: 3301 adds r3, #1 + 80030e4: f8a7 305e strh.w r3, [r7, #94] ; 0x5e + + if (req_field_count > PB_MAX_REQUIRED_FIELDS) + 80030e8: f8b7 305e ldrh.w r3, [r7, #94] ; 0x5e + 80030ec: 2b40 cmp r3, #64 ; 0x40 + 80030ee: d902 bls.n 80030f6 + req_field_count = PB_MAX_REQUIRED_FIELDS; + 80030f0: 2340 movs r3, #64 ; 0x40 + 80030f2: f8a7 305e strh.w r3, [r7, #94] ; 0x5e + + if (req_field_count > 0) + 80030f6: f8b7 305e ldrh.w r3, [r7, #94] ; 0x5e + 80030fa: 2b00 cmp r3, #0 + 80030fc: d051 beq.n 80031a2 + { + /* Check the whole words */ + for (i = 0; i < (req_field_count >> 5); i++) + 80030fe: 2300 movs r3, #0 + 8003100: f8a7 305c strh.w r3, [r7, #92] ; 0x5c + 8003104: e01b b.n 800313e + { + if (fields_seen.bitfield[i] != allbits) + 8003106: f8b7 305c ldrh.w r3, [r7, #92] ; 0x5c + 800310a: 009b lsls r3, r3, #2 + 800310c: f107 0268 add.w r2, r7, #104 ; 0x68 + 8003110: 4413 add r3, r2 + 8003112: f853 3c24 ldr.w r3, [r3, #-36] + 8003116: 6dba ldr r2, [r7, #88] ; 0x58 + 8003118: 429a cmp r2, r3 + 800311a: d00b beq.n 8003134 + PB_RETURN_ERROR(stream, "missing required field"); + 800311c: 68fb ldr r3, [r7, #12] + 800311e: 68db ldr r3, [r3, #12] + 8003120: 2b00 cmp r3, #0 + 8003122: d002 beq.n 800312a + 8003124: 68fb ldr r3, [r7, #12] + 8003126: 68db ldr r3, [r3, #12] + 8003128: e000 b.n 800312c + 800312a: 4b22 ldr r3, [pc, #136] ; (80031b4 ) + 800312c: 68fa ldr r2, [r7, #12] + 800312e: 60d3 str r3, [r2, #12] + 8003130: 2300 movs r3, #0 + 8003132: e037 b.n 80031a4 + for (i = 0; i < (req_field_count >> 5); i++) + 8003134: f8b7 305c ldrh.w r3, [r7, #92] ; 0x5c + 8003138: 3301 adds r3, #1 + 800313a: f8a7 305c strh.w r3, [r7, #92] ; 0x5c + 800313e: f8b7 305e ldrh.w r3, [r7, #94] ; 0x5e + 8003142: 095b lsrs r3, r3, #5 + 8003144: b29b uxth r3, r3 + 8003146: f8b7 205c ldrh.w r2, [r7, #92] ; 0x5c + 800314a: 429a cmp r2, r3 + 800314c: d3db bcc.n 8003106 + } + + /* Check the remaining bits (if any) */ + if ((req_field_count & 31) != 0) + 800314e: f8b7 305e ldrh.w r3, [r7, #94] ; 0x5e + 8003152: f003 031f and.w r3, r3, #31 + 8003156: 2b00 cmp r3, #0 + 8003158: d023 beq.n 80031a2 + { + if (fields_seen.bitfield[req_field_count >> 5] != + 800315a: f8b7 305e ldrh.w r3, [r7, #94] ; 0x5e + 800315e: 095b lsrs r3, r3, #5 + 8003160: b29b uxth r3, r3 + 8003162: 009b lsls r3, r3, #2 + 8003164: f107 0268 add.w r2, r7, #104 ; 0x68 + 8003168: 4413 add r3, r2 + 800316a: f853 2c24 ldr.w r2, [r3, #-36] + (allbits >> (uint8_t)(32 - (req_field_count & 31)))) + 800316e: f8b7 305e ldrh.w r3, [r7, #94] ; 0x5e + 8003172: b2db uxtb r3, r3 + 8003174: f003 031f and.w r3, r3, #31 + 8003178: b2db uxtb r3, r3 + 800317a: f1c3 0320 rsb r3, r3, #32 + 800317e: b2db uxtb r3, r3 + 8003180: 4619 mov r1, r3 + 8003182: 6dbb ldr r3, [r7, #88] ; 0x58 + 8003184: 40cb lsrs r3, r1 + if (fields_seen.bitfield[req_field_count >> 5] != + 8003186: 429a cmp r2, r3 + 8003188: d00b beq.n 80031a2 + { + PB_RETURN_ERROR(stream, "missing required field"); + 800318a: 68fb ldr r3, [r7, #12] + 800318c: 68db ldr r3, [r3, #12] + 800318e: 2b00 cmp r3, #0 + 8003190: d002 beq.n 8003198 + 8003192: 68fb ldr r3, [r7, #12] + 8003194: 68db ldr r3, [r3, #12] + 8003196: e000 b.n 800319a + 8003198: 4b06 ldr r3, [pc, #24] ; (80031b4 ) + 800319a: 68fa ldr r2, [r7, #12] + 800319c: 60d3 str r3, [r2, #12] + 800319e: 2300 movs r3, #0 + 80031a0: e000 b.n 80031a4 + } + } + } + } + + return true; + 80031a2: 2301 movs r3, #1 +} + 80031a4: 4618 mov r0, r3 + 80031a6: 3768 adds r7, #104 ; 0x68 + 80031a8: 46bd mov sp, r7 + 80031aa: bd80 pop {r7, pc} + 80031ac: 08008aa8 .word 0x08008aa8 + 80031b0: 08008ab4 .word 0x08008ab4 + 80031b4: 08008ad8 .word 0x08008ad8 + +080031b8 : + +bool checkreturn pb_decode_ex(pb_istream_t *stream, const pb_msgdesc_t *fields, void *dest_struct, unsigned int flags) +{ + 80031b8: b580 push {r7, lr} + 80031ba: b094 sub sp, #80 ; 0x50 + 80031bc: af00 add r7, sp, #0 + 80031be: 60f8 str r0, [r7, #12] + 80031c0: 60b9 str r1, [r7, #8] + 80031c2: 607a str r2, [r7, #4] + 80031c4: 603b str r3, [r7, #0] + bool status; + + if ((flags & PB_DECODE_NOINIT) == 0) + 80031c6: 683b ldr r3, [r7, #0] + 80031c8: f003 0301 and.w r3, r3, #1 + 80031cc: 2b00 cmp r3, #0 + 80031ce: d120 bne.n 8003212 + { + pb_field_iter_t iter; + + if (pb_field_iter_begin(&iter, fields, dest_struct)) + 80031d0: f107 0314 add.w r3, r7, #20 + 80031d4: 687a ldr r2, [r7, #4] + 80031d6: 68b9 ldr r1, [r7, #8] + 80031d8: 4618 mov r0, r3 + 80031da: f7fe fd66 bl 8001caa + 80031de: 4603 mov r3, r0 + 80031e0: 2b00 cmp r3, #0 + 80031e2: d016 beq.n 8003212 + { + if (!pb_message_set_to_defaults(&iter)) + 80031e4: f107 0314 add.w r3, r7, #20 + 80031e8: 4618 mov r0, r3 + 80031ea: f7ff fdb8 bl 8002d5e + 80031ee: 4603 mov r3, r0 + 80031f0: f083 0301 eor.w r3, r3, #1 + 80031f4: b2db uxtb r3, r3 + 80031f6: 2b00 cmp r3, #0 + 80031f8: d00b beq.n 8003212 + PB_RETURN_ERROR(stream, "failed to set defaults"); + 80031fa: 68fb ldr r3, [r7, #12] + 80031fc: 68db ldr r3, [r3, #12] + 80031fe: 2b00 cmp r3, #0 + 8003200: d002 beq.n 8003208 + 8003202: 68fb ldr r3, [r7, #12] + 8003204: 68db ldr r3, [r3, #12] + 8003206: e000 b.n 800320a + 8003208: 4b1f ldr r3, [pc, #124] ; (8003288 ) + 800320a: 68fa ldr r2, [r7, #12] + 800320c: 60d3 str r3, [r2, #12] + 800320e: 2300 movs r3, #0 + 8003210: e036 b.n 8003280 + } + } + + if ((flags & PB_DECODE_DELIMITED) == 0) + 8003212: 683b ldr r3, [r7, #0] + 8003214: f003 0302 and.w r3, r3, #2 + 8003218: 2b00 cmp r3, #0 + 800321a: d109 bne.n 8003230 + { + status = pb_decode_inner(stream, fields, dest_struct, flags); + 800321c: 683b ldr r3, [r7, #0] + 800321e: 687a ldr r2, [r7, #4] + 8003220: 68b9 ldr r1, [r7, #8] + 8003222: 68f8 ldr r0, [r7, #12] + 8003224: f7ff fe1a bl 8002e5c + 8003228: 4603 mov r3, r0 + 800322a: f887 304f strb.w r3, [r7, #79] ; 0x4f + 800322e: e025 b.n 800327c + } + else + { + pb_istream_t substream; + if (!pb_make_string_substream(stream, &substream)) + 8003230: f107 033c add.w r3, r7, #60 ; 0x3c + 8003234: 4619 mov r1, r3 + 8003236: 68f8 ldr r0, [r7, #12] + 8003238: f7ff f90c bl 8002454 + 800323c: 4603 mov r3, r0 + 800323e: f083 0301 eor.w r3, r3, #1 + 8003242: b2db uxtb r3, r3 + 8003244: 2b00 cmp r3, #0 + 8003246: d001 beq.n 800324c + return false; + 8003248: 2300 movs r3, #0 + 800324a: e019 b.n 8003280 + + status = pb_decode_inner(&substream, fields, dest_struct, flags); + 800324c: f107 003c add.w r0, r7, #60 ; 0x3c + 8003250: 683b ldr r3, [r7, #0] + 8003252: 687a ldr r2, [r7, #4] + 8003254: 68b9 ldr r1, [r7, #8] + 8003256: f7ff fe01 bl 8002e5c + 800325a: 4603 mov r3, r0 + 800325c: f887 304f strb.w r3, [r7, #79] ; 0x4f + + if (!pb_close_string_substream(stream, &substream)) + 8003260: f107 033c add.w r3, r7, #60 ; 0x3c + 8003264: 4619 mov r1, r3 + 8003266: 68f8 ldr r0, [r7, #12] + 8003268: f7ff f92e bl 80024c8 + 800326c: 4603 mov r3, r0 + 800326e: f083 0301 eor.w r3, r3, #1 + 8003272: b2db uxtb r3, r3 + 8003274: 2b00 cmp r3, #0 + 8003276: d001 beq.n 800327c + return false; + 8003278: 2300 movs r3, #0 + 800327a: e001 b.n 8003280 +#ifdef PB_ENABLE_MALLOC + if (!status) + pb_release(fields, dest_struct); +#endif + + return status; + 800327c: f897 304f ldrb.w r3, [r7, #79] ; 0x4f +} + 8003280: 4618 mov r0, r3 + 8003282: 3750 adds r7, #80 ; 0x50 + 8003284: 46bd mov sp, r7 + 8003286: bd80 pop {r7, pc} + 8003288: 08008af0 .word 0x08008af0 + +0800328c : + +bool checkreturn pb_decode(pb_istream_t *stream, const pb_msgdesc_t *fields, void *dest_struct) +{ + 800328c: b580 push {r7, lr} + 800328e: b084 sub sp, #16 + 8003290: af00 add r7, sp, #0 + 8003292: 60f8 str r0, [r7, #12] + 8003294: 60b9 str r1, [r7, #8] + 8003296: 607a str r2, [r7, #4] + return pb_decode_ex(stream, fields, dest_struct, 0); + 8003298: 2300 movs r3, #0 + 800329a: 687a ldr r2, [r7, #4] + 800329c: 68b9 ldr r1, [r7, #8] + 800329e: 68f8 ldr r0, [r7, #12] + 80032a0: f7ff ff8a bl 80031b8 + 80032a4: 4603 mov r3, r0 +} + 80032a6: 4618 mov r0, r3 + 80032a8: 3710 adds r7, #16 + 80032aa: 46bd mov sp, r7 + 80032ac: bd80 pop {r7, pc} + +080032ae : +#endif + +/* Field decoders */ + +bool pb_decode_bool(pb_istream_t *stream, bool *dest) +{ + 80032ae: b580 push {r7, lr} + 80032b0: b084 sub sp, #16 + 80032b2: af00 add r7, sp, #0 + 80032b4: 6078 str r0, [r7, #4] + 80032b6: 6039 str r1, [r7, #0] + uint32_t value; + if (!pb_decode_varint32(stream, &value)) + 80032b8: f107 030c add.w r3, r7, #12 + 80032bc: 4619 mov r1, r3 + 80032be: 6878 ldr r0, [r7, #4] + 80032c0: f7fe ff44 bl 800214c + 80032c4: 4603 mov r3, r0 + 80032c6: f083 0301 eor.w r3, r3, #1 + 80032ca: b2db uxtb r3, r3 + 80032cc: 2b00 cmp r3, #0 + 80032ce: d001 beq.n 80032d4 + return false; + 80032d0: 2300 movs r3, #0 + 80032d2: e008 b.n 80032e6 + + *(bool*)dest = (value != 0); + 80032d4: 68fb ldr r3, [r7, #12] + 80032d6: 2b00 cmp r3, #0 + 80032d8: bf14 ite ne + 80032da: 2301 movne r3, #1 + 80032dc: 2300 moveq r3, #0 + 80032de: b2da uxtb r2, r3 + 80032e0: 683b ldr r3, [r7, #0] + 80032e2: 701a strb r2, [r3, #0] + return true; + 80032e4: 2301 movs r3, #1 +} + 80032e6: 4618 mov r0, r3 + 80032e8: 3710 adds r7, #16 + 80032ea: 46bd mov sp, r7 + 80032ec: bd80 pop {r7, pc} + +080032ee : + +bool pb_decode_svarint(pb_istream_t *stream, pb_int64_t *dest) +{ + 80032ee: e92d 4890 stmdb sp!, {r4, r7, fp, lr} + 80032f2: b084 sub sp, #16 + 80032f4: af00 add r7, sp, #0 + 80032f6: 6078 str r0, [r7, #4] + 80032f8: 6039 str r1, [r7, #0] + pb_uint64_t value; + if (!pb_decode_varint(stream, &value)) + 80032fa: f107 0308 add.w r3, r7, #8 + 80032fe: 4619 mov r1, r3 + 8003300: 6878 ldr r0, [r7, #4] + 8003302: f7fe ff33 bl 800216c + 8003306: 4603 mov r3, r0 + 8003308: f083 0301 eor.w r3, r3, #1 + 800330c: b2db uxtb r3, r3 + 800330e: 2b00 cmp r3, #0 + 8003310: d001 beq.n 8003316 + return false; + 8003312: 2300 movs r3, #0 + 8003314: e021 b.n 800335a + + if (value & 1) + 8003316: e9d7 bc02 ldrd fp, ip, [r7, #8] + 800331a: f04f 0101 mov.w r1, #1 + 800331e: f04f 0200 mov.w r2, #0 + 8003322: ea0b 0301 and.w r3, fp, r1 + 8003326: ea0c 0402 and.w r4, ip, r2 + 800332a: 4323 orrs r3, r4 + 800332c: d00c beq.n 8003348 + *dest = (pb_int64_t)(~(value >> 1)); + 800332e: e9d7 3402 ldrd r3, r4, [r7, #8] + 8003332: 0862 lsrs r2, r4, #1 + 8003334: ea4f 0133 mov.w r1, r3, rrx + 8003338: ea6f 0301 mvn.w r3, r1 + 800333c: ea6f 0402 mvn.w r4, r2 + 8003340: 683a ldr r2, [r7, #0] + 8003342: e9c2 3400 strd r3, r4, [r2] + 8003346: e007 b.n 8003358 + else + *dest = (pb_int64_t)(value >> 1); + 8003348: e9d7 3402 ldrd r3, r4, [r7, #8] + 800334c: 0864 lsrs r4, r4, #1 + 800334e: ea4f 0333 mov.w r3, r3, rrx + 8003352: 683a ldr r2, [r7, #0] + 8003354: e9c2 3400 strd r3, r4, [r2] + + return true; + 8003358: 2301 movs r3, #1 +} + 800335a: 4618 mov r0, r3 + 800335c: 3710 adds r7, #16 + 800335e: 46bd mov sp, r7 + 8003360: e8bd 8890 ldmia.w sp!, {r4, r7, fp, pc} + +08003364 : + +bool pb_decode_fixed32(pb_istream_t *stream, void *dest) +{ + 8003364: b580 push {r7, lr} + 8003366: b084 sub sp, #16 + 8003368: af00 add r7, sp, #0 + 800336a: 6078 str r0, [r7, #4] + 800336c: 6039 str r1, [r7, #0] + union { + uint32_t fixed32; + pb_byte_t bytes[4]; + } u; + + if (!pb_read(stream, u.bytes, 4)) + 800336e: f107 030c add.w r3, r7, #12 + 8003372: 2204 movs r2, #4 + 8003374: 4619 mov r1, r3 + 8003376: 6878 ldr r0, [r7, #4] + 8003378: f7fe fd98 bl 8001eac + 800337c: 4603 mov r3, r0 + 800337e: f083 0301 eor.w r3, r3, #1 + 8003382: b2db uxtb r3, r3 + 8003384: 2b00 cmp r3, #0 + 8003386: d001 beq.n 800338c + return false; + 8003388: 2300 movs r3, #0 + 800338a: e00d b.n 80033a8 + +#if defined(__BYTE_ORDER) && __BYTE_ORDER == __LITTLE_ENDIAN && CHAR_BIT == 8 + /* fast path - if we know that we're on little endian, assign directly */ + *(uint32_t*)dest = u.fixed32; +#else + *(uint32_t*)dest = ((uint32_t)u.bytes[0] << 0) | + 800338c: 7b3b ldrb r3, [r7, #12] + 800338e: 461a mov r2, r3 + ((uint32_t)u.bytes[1] << 8) | + 8003390: 7b7b ldrb r3, [r7, #13] + 8003392: 021b lsls r3, r3, #8 + *(uint32_t*)dest = ((uint32_t)u.bytes[0] << 0) | + 8003394: 431a orrs r2, r3 + ((uint32_t)u.bytes[2] << 16) | + 8003396: 7bbb ldrb r3, [r7, #14] + 8003398: 041b lsls r3, r3, #16 + ((uint32_t)u.bytes[1] << 8) | + 800339a: 431a orrs r2, r3 + ((uint32_t)u.bytes[3] << 24); + 800339c: 7bfb ldrb r3, [r7, #15] + 800339e: 061b lsls r3, r3, #24 + ((uint32_t)u.bytes[2] << 16) | + 80033a0: 431a orrs r2, r3 + *(uint32_t*)dest = ((uint32_t)u.bytes[0] << 0) | + 80033a2: 683b ldr r3, [r7, #0] + 80033a4: 601a str r2, [r3, #0] +#endif + return true; + 80033a6: 2301 movs r3, #1 +} + 80033a8: 4618 mov r0, r3 + 80033aa: 3710 adds r7, #16 + 80033ac: 46bd mov sp, r7 + 80033ae: bd80 pop {r7, pc} + +080033b0 : + +#ifndef PB_WITHOUT_64BIT +bool pb_decode_fixed64(pb_istream_t *stream, void *dest) +{ + 80033b0: e92d 4bf0 stmdb sp!, {r4, r5, r6, r7, r8, r9, fp, lr} + 80033b4: b084 sub sp, #16 + 80033b6: af00 add r7, sp, #0 + 80033b8: 6078 str r0, [r7, #4] + 80033ba: 6039 str r1, [r7, #0] + union { + uint64_t fixed64; + pb_byte_t bytes[8]; + } u; + + if (!pb_read(stream, u.bytes, 8)) + 80033bc: f107 0308 add.w r3, r7, #8 + 80033c0: 2208 movs r2, #8 + 80033c2: 4619 mov r1, r3 + 80033c4: 6878 ldr r0, [r7, #4] + 80033c6: f7fe fd71 bl 8001eac + 80033ca: 4603 mov r3, r0 + 80033cc: f083 0301 eor.w r3, r3, #1 + 80033d0: b2db uxtb r3, r3 + 80033d2: 2b00 cmp r3, #0 + 80033d4: d001 beq.n 80033da + return false; + 80033d6: 2300 movs r3, #0 + 80033d8: e06c b.n 80034b4 + +#if defined(__BYTE_ORDER) && __BYTE_ORDER == __LITTLE_ENDIAN && CHAR_BIT == 8 + /* fast path - if we know that we're on little endian, assign directly */ + *(uint64_t*)dest = u.fixed64; +#else + *(uint64_t*)dest = ((uint64_t)u.bytes[0] << 0) | + 80033da: 7a3b ldrb r3, [r7, #8] + 80033dc: fa5f fb83 uxtb.w fp, r3 + 80033e0: f04f 0c00 mov.w ip, #0 + ((uint64_t)u.bytes[1] << 8) | + 80033e4: 7a7b ldrb r3, [r7, #9] + 80033e6: b2d9 uxtb r1, r3 + 80033e8: f04f 0200 mov.w r2, #0 + 80033ec: f04f 0300 mov.w r3, #0 + 80033f0: f04f 0400 mov.w r4, #0 + 80033f4: 0214 lsls r4, r2, #8 + 80033f6: ea44 6411 orr.w r4, r4, r1, lsr #24 + 80033fa: 020b lsls r3, r1, #8 + *(uint64_t*)dest = ((uint64_t)u.bytes[0] << 0) | + 80033fc: ea4b 0803 orr.w r8, fp, r3 + 8003400: ea4c 0904 orr.w r9, ip, r4 + ((uint64_t)u.bytes[2] << 16) | + 8003404: 7abb ldrb r3, [r7, #10] + 8003406: b2d9 uxtb r1, r3 + 8003408: f04f 0200 mov.w r2, #0 + 800340c: f04f 0300 mov.w r3, #0 + 8003410: f04f 0400 mov.w r4, #0 + 8003414: 0414 lsls r4, r2, #16 + 8003416: ea44 4411 orr.w r4, r4, r1, lsr #16 + 800341a: 040b lsls r3, r1, #16 + ((uint64_t)u.bytes[1] << 8) | + 800341c: ea48 0103 orr.w r1, r8, r3 + 8003420: ea49 0204 orr.w r2, r9, r4 + ((uint64_t)u.bytes[3] << 24) | + 8003424: 7afb ldrb r3, [r7, #11] + 8003426: b2db uxtb r3, r3 + 8003428: f04f 0400 mov.w r4, #0 + 800342c: 0a1e lsrs r6, r3, #8 + 800342e: 061d lsls r5, r3, #24 + ((uint64_t)u.bytes[2] << 16) | + 8003430: ea41 0805 orr.w r8, r1, r5 + 8003434: ea42 0906 orr.w r9, r2, r6 + ((uint64_t)u.bytes[4] << 32) | + 8003438: 7b3b ldrb r3, [r7, #12] + 800343a: b2dd uxtb r5, r3 + 800343c: f04f 0600 mov.w r6, #0 + 8003440: f04f 0300 mov.w r3, #0 + 8003444: f04f 0400 mov.w r4, #0 + 8003448: 002c movs r4, r5 + 800344a: 2300 movs r3, #0 + ((uint64_t)u.bytes[3] << 24) | + 800344c: ea48 0103 orr.w r1, r8, r3 + 8003450: ea49 0204 orr.w r2, r9, r4 + ((uint64_t)u.bytes[5] << 40) | + 8003454: 7b7b ldrb r3, [r7, #13] + 8003456: b2dd uxtb r5, r3 + 8003458: f04f 0600 mov.w r6, #0 + 800345c: f04f 0300 mov.w r3, #0 + 8003460: f04f 0400 mov.w r4, #0 + 8003464: 022c lsls r4, r5, #8 + 8003466: 2300 movs r3, #0 + ((uint64_t)u.bytes[4] << 32) | + 8003468: ea41 0803 orr.w r8, r1, r3 + 800346c: ea42 0904 orr.w r9, r2, r4 + ((uint64_t)u.bytes[6] << 48) | + 8003470: 7bbb ldrb r3, [r7, #14] + 8003472: b2dd uxtb r5, r3 + 8003474: f04f 0600 mov.w r6, #0 + 8003478: f04f 0300 mov.w r3, #0 + 800347c: f04f 0400 mov.w r4, #0 + 8003480: 042c lsls r4, r5, #16 + 8003482: 2300 movs r3, #0 + ((uint64_t)u.bytes[5] << 40) | + 8003484: ea48 0103 orr.w r1, r8, r3 + 8003488: ea49 0204 orr.w r2, r9, r4 + ((uint64_t)u.bytes[7] << 56); + 800348c: 7bfb ldrb r3, [r7, #15] + 800348e: b2dd uxtb r5, r3 + 8003490: f04f 0600 mov.w r6, #0 + 8003494: f04f 0800 mov.w r8, #0 + 8003498: f04f 0900 mov.w r9, #0 + 800349c: ea4f 6905 mov.w r9, r5, lsl #24 + 80034a0: f04f 0800 mov.w r8, #0 + ((uint64_t)u.bytes[6] << 48) | + 80034a4: ea48 0301 orr.w r3, r8, r1 + 80034a8: ea49 0402 orr.w r4, r9, r2 + *(uint64_t*)dest = ((uint64_t)u.bytes[0] << 0) | + 80034ac: 683a ldr r2, [r7, #0] + 80034ae: e9c2 3400 strd r3, r4, [r2] +#endif + return true; + 80034b2: 2301 movs r3, #1 +} + 80034b4: 4618 mov r0, r3 + 80034b6: 3710 adds r7, #16 + 80034b8: 46bd mov sp, r7 + 80034ba: e8bd 8bf0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, fp, pc} + +080034be : +#endif + +static bool checkreturn pb_dec_bool(pb_istream_t *stream, const pb_field_iter_t *field) +{ + 80034be: b580 push {r7, lr} + 80034c0: b082 sub sp, #8 + 80034c2: af00 add r7, sp, #0 + 80034c4: 6078 str r0, [r7, #4] + 80034c6: 6039 str r1, [r7, #0] + return pb_decode_bool(stream, (bool*)field->pData); + 80034c8: 683b ldr r3, [r7, #0] + 80034ca: 69db ldr r3, [r3, #28] + 80034cc: 4619 mov r1, r3 + 80034ce: 6878 ldr r0, [r7, #4] + 80034d0: f7ff feed bl 80032ae + 80034d4: 4603 mov r3, r0 +} + 80034d6: 4618 mov r0, r3 + 80034d8: 3708 adds r7, #8 + 80034da: 46bd mov sp, r7 + 80034dc: bd80 pop {r7, pc} + ... + +080034e0 : + +static bool checkreturn pb_dec_varint(pb_istream_t *stream, const pb_field_iter_t *field) +{ + 80034e0: b590 push {r4, r7, lr} + 80034e2: b08d sub sp, #52 ; 0x34 + 80034e4: af00 add r7, sp, #0 + 80034e6: 6078 str r0, [r7, #4] + 80034e8: 6039 str r1, [r7, #0] + if (PB_LTYPE(field->type) == PB_LTYPE_UVARINT) + 80034ea: 683b ldr r3, [r7, #0] + 80034ec: 7d9b ldrb r3, [r3, #22] + 80034ee: f003 030f and.w r3, r3, #15 + 80034f2: 2b02 cmp r3, #2 + 80034f4: d170 bne.n 80035d8 + { + pb_uint64_t value, clamped; + if (!pb_decode_varint(stream, &value)) + 80034f6: f107 0318 add.w r3, r7, #24 + 80034fa: 4619 mov r1, r3 + 80034fc: 6878 ldr r0, [r7, #4] + 80034fe: f7fe fe35 bl 800216c + 8003502: 4603 mov r3, r0 + 8003504: f083 0301 eor.w r3, r3, #1 + 8003508: b2db uxtb r3, r3 + 800350a: 2b00 cmp r3, #0 + 800350c: d001 beq.n 8003512 + return false; + 800350e: 2300 movs r3, #0 + 8003510: e0f7 b.n 8003702 + + /* Cast to the proper field size, while checking for overflows */ + if (field->data_size == sizeof(pb_uint64_t)) + 8003512: 683b ldr r3, [r7, #0] + 8003514: 8a5b ldrh r3, [r3, #18] + 8003516: 2b08 cmp r3, #8 + 8003518: d10a bne.n 8003530 + clamped = *(pb_uint64_t*)field->pData = value; + 800351a: 683b ldr r3, [r7, #0] + 800351c: 69da ldr r2, [r3, #28] + 800351e: e9d7 3406 ldrd r3, r4, [r7, #24] + 8003522: e9c2 3400 strd r3, r4, [r2] + 8003526: e9d2 3400 ldrd r3, r4, [r2] + 800352a: e9c7 340a strd r3, r4, [r7, #40] ; 0x28 + 800352e: e03d b.n 80035ac + else if (field->data_size == sizeof(uint32_t)) + 8003530: 683b ldr r3, [r7, #0] + 8003532: 8a5b ldrh r3, [r3, #18] + 8003534: 2b04 cmp r3, #4 + 8003536: d10b bne.n 8003550 + clamped = *(uint32_t*)field->pData = (uint32_t)value; + 8003538: e9d7 1206 ldrd r1, r2, [r7, #24] + 800353c: 683b ldr r3, [r7, #0] + 800353e: 69db ldr r3, [r3, #28] + 8003540: 460a mov r2, r1 + 8003542: 601a str r2, [r3, #0] + 8003544: 681b ldr r3, [r3, #0] + 8003546: f04f 0400 mov.w r4, #0 + 800354a: e9c7 340a strd r3, r4, [r7, #40] ; 0x28 + 800354e: e02d b.n 80035ac + else if (field->data_size == sizeof(uint_least16_t)) + 8003550: 683b ldr r3, [r7, #0] + 8003552: 8a5b ldrh r3, [r3, #18] + 8003554: 2b02 cmp r3, #2 + 8003556: d10c bne.n 8003572 + clamped = *(uint_least16_t*)field->pData = (uint_least16_t)value; + 8003558: e9d7 1206 ldrd r1, r2, [r7, #24] + 800355c: 683b ldr r3, [r7, #0] + 800355e: 69db ldr r3, [r3, #28] + 8003560: b28a uxth r2, r1 + 8003562: 801a strh r2, [r3, #0] + 8003564: 881b ldrh r3, [r3, #0] + 8003566: b29b uxth r3, r3 + 8003568: f04f 0400 mov.w r4, #0 + 800356c: e9c7 340a strd r3, r4, [r7, #40] ; 0x28 + 8003570: e01c b.n 80035ac + else if (field->data_size == sizeof(uint_least8_t)) + 8003572: 683b ldr r3, [r7, #0] + 8003574: 8a5b ldrh r3, [r3, #18] + 8003576: 2b01 cmp r3, #1 + 8003578: d10c bne.n 8003594 + clamped = *(uint_least8_t*)field->pData = (uint_least8_t)value; + 800357a: e9d7 1206 ldrd r1, r2, [r7, #24] + 800357e: 683b ldr r3, [r7, #0] + 8003580: 69db ldr r3, [r3, #28] + 8003582: b2ca uxtb r2, r1 + 8003584: 701a strb r2, [r3, #0] + 8003586: 781b ldrb r3, [r3, #0] + 8003588: b2db uxtb r3, r3 + 800358a: f04f 0400 mov.w r4, #0 + 800358e: e9c7 340a strd r3, r4, [r7, #40] ; 0x28 + 8003592: e00b b.n 80035ac + else + PB_RETURN_ERROR(stream, "invalid data_size"); + 8003594: 687b ldr r3, [r7, #4] + 8003596: 68db ldr r3, [r3, #12] + 8003598: 2b00 cmp r3, #0 + 800359a: d002 beq.n 80035a2 + 800359c: 687b ldr r3, [r7, #4] + 800359e: 68db ldr r3, [r3, #12] + 80035a0: e000 b.n 80035a4 + 80035a2: 4b5a ldr r3, [pc, #360] ; (800370c ) + 80035a4: 687a ldr r2, [r7, #4] + 80035a6: 60d3 str r3, [r2, #12] + 80035a8: 2300 movs r3, #0 + 80035aa: e0aa b.n 8003702 + + if (clamped != value) + 80035ac: e9d7 3406 ldrd r3, r4, [r7, #24] + 80035b0: e9d7 120a ldrd r1, r2, [r7, #40] ; 0x28 + 80035b4: 42a2 cmp r2, r4 + 80035b6: bf08 it eq + 80035b8: 4299 cmpeq r1, r3 + 80035ba: d00b beq.n 80035d4 + PB_RETURN_ERROR(stream, "integer too large"); + 80035bc: 687b ldr r3, [r7, #4] + 80035be: 68db ldr r3, [r3, #12] + 80035c0: 2b00 cmp r3, #0 + 80035c2: d002 beq.n 80035ca + 80035c4: 687b ldr r3, [r7, #4] + 80035c6: 68db ldr r3, [r3, #12] + 80035c8: e000 b.n 80035cc + 80035ca: 4b51 ldr r3, [pc, #324] ; (8003710 ) + 80035cc: 687a ldr r2, [r7, #4] + 80035ce: 60d3 str r3, [r2, #12] + 80035d0: 2300 movs r3, #0 + 80035d2: e096 b.n 8003702 + + return true; + 80035d4: 2301 movs r3, #1 + 80035d6: e094 b.n 8003702 + { + pb_uint64_t value; + pb_int64_t svalue; + pb_int64_t clamped; + + if (PB_LTYPE(field->type) == PB_LTYPE_SVARINT) + 80035d8: 683b ldr r3, [r7, #0] + 80035da: 7d9b ldrb r3, [r3, #22] + 80035dc: f003 030f and.w r3, r3, #15 + 80035e0: 2b03 cmp r3, #3 + 80035e2: d10d bne.n 8003600 + { + if (!pb_decode_svarint(stream, &svalue)) + 80035e4: f107 0308 add.w r3, r7, #8 + 80035e8: 4619 mov r1, r3 + 80035ea: 6878 ldr r0, [r7, #4] + 80035ec: f7ff fe7f bl 80032ee + 80035f0: 4603 mov r3, r0 + 80035f2: f083 0301 eor.w r3, r3, #1 + 80035f6: b2db uxtb r3, r3 + 80035f8: 2b00 cmp r3, #0 + 80035fa: d01e beq.n 800363a + return false; + 80035fc: 2300 movs r3, #0 + 80035fe: e080 b.n 8003702 + } + else + { + if (!pb_decode_varint(stream, &value)) + 8003600: f107 0310 add.w r3, r7, #16 + 8003604: 4619 mov r1, r3 + 8003606: 6878 ldr r0, [r7, #4] + 8003608: f7fe fdb0 bl 800216c + 800360c: 4603 mov r3, r0 + 800360e: f083 0301 eor.w r3, r3, #1 + 8003612: b2db uxtb r3, r3 + 8003614: 2b00 cmp r3, #0 + 8003616: d001 beq.n 800361c + return false; + 8003618: 2300 movs r3, #0 + 800361a: e072 b.n 8003702 + * be cast as int32_t, instead of the int64_t that should be used when + * encoding. Previous nanopb versions had a bug in encoding. In order to + * not break decoding of such messages, we cast <=32 bit fields to + * int32_t first to get the sign correct. + */ + if (field->data_size == sizeof(pb_int64_t)) + 800361c: 683b ldr r3, [r7, #0] + 800361e: 8a5b ldrh r3, [r3, #18] + 8003620: 2b08 cmp r3, #8 + 8003622: d104 bne.n 800362e + svalue = (pb_int64_t)value; + 8003624: e9d7 3404 ldrd r3, r4, [r7, #16] + 8003628: e9c7 3402 strd r3, r4, [r7, #8] + 800362c: e005 b.n 800363a + else + svalue = (int32_t)value; + 800362e: e9d7 3404 ldrd r3, r4, [r7, #16] + 8003632: ea4f 74e3 mov.w r4, r3, asr #31 + 8003636: e9c7 3402 strd r3, r4, [r7, #8] + } + + /* Cast to the proper field size, while checking for overflows */ + if (field->data_size == sizeof(pb_int64_t)) + 800363a: 683b ldr r3, [r7, #0] + 800363c: 8a5b ldrh r3, [r3, #18] + 800363e: 2b08 cmp r3, #8 + 8003640: d10a bne.n 8003658 + clamped = *(pb_int64_t*)field->pData = svalue; + 8003642: 683b ldr r3, [r7, #0] + 8003644: 69da ldr r2, [r3, #28] + 8003646: e9d7 3402 ldrd r3, r4, [r7, #8] + 800364a: e9c2 3400 strd r3, r4, [r2] + 800364e: e9d2 3400 ldrd r3, r4, [r2] + 8003652: e9c7 3408 strd r3, r4, [r7, #32] + 8003656: e03f b.n 80036d8 + else if (field->data_size == sizeof(int32_t)) + 8003658: 683b ldr r3, [r7, #0] + 800365a: 8a5b ldrh r3, [r3, #18] + 800365c: 2b04 cmp r3, #4 + 800365e: d10b bne.n 8003678 + clamped = *(int32_t*)field->pData = (int32_t)svalue; + 8003660: e9d7 1202 ldrd r1, r2, [r7, #8] + 8003664: 683b ldr r3, [r7, #0] + 8003666: 69db ldr r3, [r3, #28] + 8003668: 460a mov r2, r1 + 800366a: 601a str r2, [r3, #0] + 800366c: 681b ldr r3, [r3, #0] + 800366e: ea4f 74e3 mov.w r4, r3, asr #31 + 8003672: e9c7 3408 strd r3, r4, [r7, #32] + 8003676: e02f b.n 80036d8 + else if (field->data_size == sizeof(int_least16_t)) + 8003678: 683b ldr r3, [r7, #0] + 800367a: 8a5b ldrh r3, [r3, #18] + 800367c: 2b02 cmp r3, #2 + 800367e: d10d bne.n 800369c + clamped = *(int_least16_t*)field->pData = (int_least16_t)svalue; + 8003680: e9d7 1202 ldrd r1, r2, [r7, #8] + 8003684: 683b ldr r3, [r7, #0] + 8003686: 69db ldr r3, [r3, #28] + 8003688: b20a sxth r2, r1 + 800368a: 801a strh r2, [r3, #0] + 800368c: f9b3 3000 ldrsh.w r3, [r3] + 8003690: b21b sxth r3, r3 + 8003692: ea4f 74e3 mov.w r4, r3, asr #31 + 8003696: e9c7 3408 strd r3, r4, [r7, #32] + 800369a: e01d b.n 80036d8 + else if (field->data_size == sizeof(int_least8_t)) + 800369c: 683b ldr r3, [r7, #0] + 800369e: 8a5b ldrh r3, [r3, #18] + 80036a0: 2b01 cmp r3, #1 + 80036a2: d10d bne.n 80036c0 + clamped = *(int_least8_t*)field->pData = (int_least8_t)svalue; + 80036a4: e9d7 1202 ldrd r1, r2, [r7, #8] + 80036a8: 683b ldr r3, [r7, #0] + 80036aa: 69db ldr r3, [r3, #28] + 80036ac: b24a sxtb r2, r1 + 80036ae: 701a strb r2, [r3, #0] + 80036b0: f993 3000 ldrsb.w r3, [r3] + 80036b4: b25b sxtb r3, r3 + 80036b6: ea4f 74e3 mov.w r4, r3, asr #31 + 80036ba: e9c7 3408 strd r3, r4, [r7, #32] + 80036be: e00b b.n 80036d8 + else + PB_RETURN_ERROR(stream, "invalid data_size"); + 80036c0: 687b ldr r3, [r7, #4] + 80036c2: 68db ldr r3, [r3, #12] + 80036c4: 2b00 cmp r3, #0 + 80036c6: d002 beq.n 80036ce + 80036c8: 687b ldr r3, [r7, #4] + 80036ca: 68db ldr r3, [r3, #12] + 80036cc: e000 b.n 80036d0 + 80036ce: 4b0f ldr r3, [pc, #60] ; (800370c ) + 80036d0: 687a ldr r2, [r7, #4] + 80036d2: 60d3 str r3, [r2, #12] + 80036d4: 2300 movs r3, #0 + 80036d6: e014 b.n 8003702 + + if (clamped != svalue) + 80036d8: e9d7 3402 ldrd r3, r4, [r7, #8] + 80036dc: e9d7 1208 ldrd r1, r2, [r7, #32] + 80036e0: 42a2 cmp r2, r4 + 80036e2: bf08 it eq + 80036e4: 4299 cmpeq r1, r3 + 80036e6: d00b beq.n 8003700 + PB_RETURN_ERROR(stream, "integer too large"); + 80036e8: 687b ldr r3, [r7, #4] + 80036ea: 68db ldr r3, [r3, #12] + 80036ec: 2b00 cmp r3, #0 + 80036ee: d002 beq.n 80036f6 + 80036f0: 687b ldr r3, [r7, #4] + 80036f2: 68db ldr r3, [r3, #12] + 80036f4: e000 b.n 80036f8 + 80036f6: 4b06 ldr r3, [pc, #24] ; (8003710 ) + 80036f8: 687a ldr r2, [r7, #4] + 80036fa: 60d3 str r3, [r2, #12] + 80036fc: 2300 movs r3, #0 + 80036fe: e000 b.n 8003702 + + return true; + 8003700: 2301 movs r3, #1 + } +} + 8003702: 4618 mov r0, r3 + 8003704: 3734 adds r7, #52 ; 0x34 + 8003706: 46bd mov sp, r7 + 8003708: bd90 pop {r4, r7, pc} + 800370a: bf00 nop + 800370c: 08008b08 .word 0x08008b08 + 8003710: 08008b1c .word 0x08008b1c + +08003714 : + +static bool checkreturn pb_dec_fixed(pb_istream_t *stream, const pb_field_iter_t *field) +{ + 8003714: b580 push {r7, lr} + 8003716: b082 sub sp, #8 + 8003718: af00 add r7, sp, #0 + 800371a: 6078 str r0, [r7, #4] + 800371c: 6039 str r1, [r7, #0] + { + return pb_decode_double_as_float(stream, (float*)field->pData); + } +#endif + + if (field->data_size == sizeof(uint32_t)) + 800371e: 683b ldr r3, [r7, #0] + 8003720: 8a5b ldrh r3, [r3, #18] + 8003722: 2b04 cmp r3, #4 + 8003724: d107 bne.n 8003736 + { + return pb_decode_fixed32(stream, field->pData); + 8003726: 683b ldr r3, [r7, #0] + 8003728: 69db ldr r3, [r3, #28] + 800372a: 4619 mov r1, r3 + 800372c: 6878 ldr r0, [r7, #4] + 800372e: f7ff fe19 bl 8003364 + 8003732: 4603 mov r3, r0 + 8003734: e016 b.n 8003764 + } +#ifndef PB_WITHOUT_64BIT + else if (field->data_size == sizeof(uint64_t)) + 8003736: 683b ldr r3, [r7, #0] + 8003738: 8a5b ldrh r3, [r3, #18] + 800373a: 2b08 cmp r3, #8 + 800373c: d107 bne.n 800374e + { + return pb_decode_fixed64(stream, field->pData); + 800373e: 683b ldr r3, [r7, #0] + 8003740: 69db ldr r3, [r3, #28] + 8003742: 4619 mov r1, r3 + 8003744: 6878 ldr r0, [r7, #4] + 8003746: f7ff fe33 bl 80033b0 + 800374a: 4603 mov r3, r0 + 800374c: e00a b.n 8003764 + } +#endif + else + { + PB_RETURN_ERROR(stream, "invalid data_size"); + 800374e: 687b ldr r3, [r7, #4] + 8003750: 68db ldr r3, [r3, #12] + 8003752: 2b00 cmp r3, #0 + 8003754: d002 beq.n 800375c + 8003756: 687b ldr r3, [r7, #4] + 8003758: 68db ldr r3, [r3, #12] + 800375a: e000 b.n 800375e + 800375c: 4b03 ldr r3, [pc, #12] ; (800376c ) + 800375e: 687a ldr r2, [r7, #4] + 8003760: 60d3 str r3, [r2, #12] + 8003762: 2300 movs r3, #0 + } +} + 8003764: 4618 mov r0, r3 + 8003766: 3708 adds r7, #8 + 8003768: 46bd mov sp, r7 + 800376a: bd80 pop {r7, pc} + 800376c: 08008b08 .word 0x08008b08 + +08003770 : + +static bool checkreturn pb_dec_bytes(pb_istream_t *stream, const pb_field_iter_t *field) +{ + 8003770: b580 push {r7, lr} + 8003772: b086 sub sp, #24 + 8003774: af00 add r7, sp, #0 + 8003776: 6078 str r0, [r7, #4] + 8003778: 6039 str r1, [r7, #0] + uint32_t size; + size_t alloc_size; + pb_bytes_array_t *dest; + + if (!pb_decode_varint32(stream, &size)) + 800377a: f107 030c add.w r3, r7, #12 + 800377e: 4619 mov r1, r3 + 8003780: 6878 ldr r0, [r7, #4] + 8003782: f7fe fce3 bl 800214c + 8003786: 4603 mov r3, r0 + 8003788: f083 0301 eor.w r3, r3, #1 + 800378c: b2db uxtb r3, r3 + 800378e: 2b00 cmp r3, #0 + 8003790: d001 beq.n 8003796 + return false; + 8003792: 2300 movs r3, #0 + 8003794: e055 b.n 8003842 + + if (size > PB_SIZE_MAX) + 8003796: 68fb ldr r3, [r7, #12] + 8003798: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800379c: d30b bcc.n 80037b6 + PB_RETURN_ERROR(stream, "bytes overflow"); + 800379e: 687b ldr r3, [r7, #4] + 80037a0: 68db ldr r3, [r3, #12] + 80037a2: 2b00 cmp r3, #0 + 80037a4: d002 beq.n 80037ac + 80037a6: 687b ldr r3, [r7, #4] + 80037a8: 68db ldr r3, [r3, #12] + 80037aa: e000 b.n 80037ae + 80037ac: 4b27 ldr r3, [pc, #156] ; (800384c ) + 80037ae: 687a ldr r2, [r7, #4] + 80037b0: 60d3 str r3, [r2, #12] + 80037b2: 2300 movs r3, #0 + 80037b4: e045 b.n 8003842 + + alloc_size = PB_BYTES_ARRAY_T_ALLOCSIZE(size); + 80037b6: 68fb ldr r3, [r7, #12] + 80037b8: 3302 adds r3, #2 + 80037ba: 617b str r3, [r7, #20] + if (size > alloc_size) + 80037bc: 68fb ldr r3, [r7, #12] + 80037be: 697a ldr r2, [r7, #20] + 80037c0: 429a cmp r2, r3 + 80037c2: d20b bcs.n 80037dc + PB_RETURN_ERROR(stream, "size too large"); + 80037c4: 687b ldr r3, [r7, #4] + 80037c6: 68db ldr r3, [r3, #12] + 80037c8: 2b00 cmp r3, #0 + 80037ca: d002 beq.n 80037d2 + 80037cc: 687b ldr r3, [r7, #4] + 80037ce: 68db ldr r3, [r3, #12] + 80037d0: e000 b.n 80037d4 + 80037d2: 4b1f ldr r3, [pc, #124] ; (8003850 ) + 80037d4: 687a ldr r2, [r7, #4] + 80037d6: 60d3 str r3, [r2, #12] + 80037d8: 2300 movs r3, #0 + 80037da: e032 b.n 8003842 + + if (PB_ATYPE(field->type) == PB_ATYPE_POINTER) + 80037dc: 683b ldr r3, [r7, #0] + 80037de: 7d9b ldrb r3, [r3, #22] + 80037e0: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 80037e4: 2b80 cmp r3, #128 ; 0x80 + 80037e6: d10b bne.n 8003800 + { +#ifndef PB_ENABLE_MALLOC + PB_RETURN_ERROR(stream, "no malloc support"); + 80037e8: 687b ldr r3, [r7, #4] + 80037ea: 68db ldr r3, [r3, #12] + 80037ec: 2b00 cmp r3, #0 + 80037ee: d002 beq.n 80037f6 + 80037f0: 687b ldr r3, [r7, #4] + 80037f2: 68db ldr r3, [r3, #12] + 80037f4: e000 b.n 80037f8 + 80037f6: 4b17 ldr r3, [pc, #92] ; (8003854 ) + 80037f8: 687a ldr r2, [r7, #4] + 80037fa: 60d3 str r3, [r2, #12] + 80037fc: 2300 movs r3, #0 + 80037fe: e020 b.n 8003842 + dest = *(pb_bytes_array_t**)field->pData; +#endif + } + else + { + if (alloc_size > field->data_size) + 8003800: 683b ldr r3, [r7, #0] + 8003802: 8a5b ldrh r3, [r3, #18] + 8003804: 461a mov r2, r3 + 8003806: 697b ldr r3, [r7, #20] + 8003808: 4293 cmp r3, r2 + 800380a: d90b bls.n 8003824 + PB_RETURN_ERROR(stream, "bytes overflow"); + 800380c: 687b ldr r3, [r7, #4] + 800380e: 68db ldr r3, [r3, #12] + 8003810: 2b00 cmp r3, #0 + 8003812: d002 beq.n 800381a + 8003814: 687b ldr r3, [r7, #4] + 8003816: 68db ldr r3, [r3, #12] + 8003818: e000 b.n 800381c + 800381a: 4b0c ldr r3, [pc, #48] ; (800384c ) + 800381c: 687a ldr r2, [r7, #4] + 800381e: 60d3 str r3, [r2, #12] + 8003820: 2300 movs r3, #0 + 8003822: e00e b.n 8003842 + dest = (pb_bytes_array_t*)field->pData; + 8003824: 683b ldr r3, [r7, #0] + 8003826: 69db ldr r3, [r3, #28] + 8003828: 613b str r3, [r7, #16] + } + + dest->size = (pb_size_t)size; + 800382a: 68fb ldr r3, [r7, #12] + 800382c: b29a uxth r2, r3 + 800382e: 693b ldr r3, [r7, #16] + 8003830: 801a strh r2, [r3, #0] + return pb_read(stream, dest->bytes, (size_t)size); + 8003832: 693b ldr r3, [r7, #16] + 8003834: 3302 adds r3, #2 + 8003836: 68fa ldr r2, [r7, #12] + 8003838: 4619 mov r1, r3 + 800383a: 6878 ldr r0, [r7, #4] + 800383c: f7fe fb36 bl 8001eac + 8003840: 4603 mov r3, r0 +} + 8003842: 4618 mov r0, r3 + 8003844: 3718 adds r7, #24 + 8003846: 46bd mov sp, r7 + 8003848: bd80 pop {r7, pc} + 800384a: bf00 nop + 800384c: 08008b30 .word 0x08008b30 + 8003850: 08008b40 .word 0x08008b40 + 8003854: 08008a70 .word 0x08008a70 + +08003858 : + +static bool checkreturn pb_dec_string(pb_istream_t *stream, const pb_field_iter_t *field) +{ + 8003858: b580 push {r7, lr} + 800385a: b086 sub sp, #24 + 800385c: af00 add r7, sp, #0 + 800385e: 6078 str r0, [r7, #4] + 8003860: 6039 str r1, [r7, #0] + uint32_t size; + size_t alloc_size; + pb_byte_t *dest = (pb_byte_t*)field->pData; + 8003862: 683b ldr r3, [r7, #0] + 8003864: 69db ldr r3, [r3, #28] + 8003866: 617b str r3, [r7, #20] + + if (!pb_decode_varint32(stream, &size)) + 8003868: f107 030c add.w r3, r7, #12 + 800386c: 4619 mov r1, r3 + 800386e: 6878 ldr r0, [r7, #4] + 8003870: f7fe fc6c bl 800214c + 8003874: 4603 mov r3, r0 + 8003876: f083 0301 eor.w r3, r3, #1 + 800387a: b2db uxtb r3, r3 + 800387c: 2b00 cmp r3, #0 + 800387e: d001 beq.n 8003884 + return false; + 8003880: 2300 movs r3, #0 + 8003882: e05a b.n 800393a + + if (size == (uint32_t)-1) + 8003884: 68fb ldr r3, [r7, #12] + 8003886: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800388a: d10b bne.n 80038a4 + PB_RETURN_ERROR(stream, "size too large"); + 800388c: 687b ldr r3, [r7, #4] + 800388e: 68db ldr r3, [r3, #12] + 8003890: 2b00 cmp r3, #0 + 8003892: d002 beq.n 800389a + 8003894: 687b ldr r3, [r7, #4] + 8003896: 68db ldr r3, [r3, #12] + 8003898: e000 b.n 800389c + 800389a: 4b2a ldr r3, [pc, #168] ; (8003944 ) + 800389c: 687a ldr r2, [r7, #4] + 800389e: 60d3 str r3, [r2, #12] + 80038a0: 2300 movs r3, #0 + 80038a2: e04a b.n 800393a + + /* Space for null terminator */ + alloc_size = (size_t)(size + 1); + 80038a4: 68fb ldr r3, [r7, #12] + 80038a6: 3301 adds r3, #1 + 80038a8: 613b str r3, [r7, #16] + + if (alloc_size < size) + 80038aa: 68fb ldr r3, [r7, #12] + 80038ac: 693a ldr r2, [r7, #16] + 80038ae: 429a cmp r2, r3 + 80038b0: d20b bcs.n 80038ca + PB_RETURN_ERROR(stream, "size too large"); + 80038b2: 687b ldr r3, [r7, #4] + 80038b4: 68db ldr r3, [r3, #12] + 80038b6: 2b00 cmp r3, #0 + 80038b8: d002 beq.n 80038c0 + 80038ba: 687b ldr r3, [r7, #4] + 80038bc: 68db ldr r3, [r3, #12] + 80038be: e000 b.n 80038c2 + 80038c0: 4b20 ldr r3, [pc, #128] ; (8003944 ) + 80038c2: 687a ldr r2, [r7, #4] + 80038c4: 60d3 str r3, [r2, #12] + 80038c6: 2300 movs r3, #0 + 80038c8: e037 b.n 800393a + + if (PB_ATYPE(field->type) == PB_ATYPE_POINTER) + 80038ca: 683b ldr r3, [r7, #0] + 80038cc: 7d9b ldrb r3, [r3, #22] + 80038ce: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 80038d2: 2b80 cmp r3, #128 ; 0x80 + 80038d4: d10b bne.n 80038ee + { +#ifndef PB_ENABLE_MALLOC + PB_RETURN_ERROR(stream, "no malloc support"); + 80038d6: 687b ldr r3, [r7, #4] + 80038d8: 68db ldr r3, [r3, #12] + 80038da: 2b00 cmp r3, #0 + 80038dc: d002 beq.n 80038e4 + 80038de: 687b ldr r3, [r7, #4] + 80038e0: 68db ldr r3, [r3, #12] + 80038e2: e000 b.n 80038e6 + 80038e4: 4b18 ldr r3, [pc, #96] ; (8003948 ) + 80038e6: 687a ldr r2, [r7, #4] + 80038e8: 60d3 str r3, [r2, #12] + 80038ea: 2300 movs r3, #0 + 80038ec: e025 b.n 800393a + dest = *(pb_byte_t**)field->pData; +#endif + } + else + { + if (alloc_size > field->data_size) + 80038ee: 683b ldr r3, [r7, #0] + 80038f0: 8a5b ldrh r3, [r3, #18] + 80038f2: 461a mov r2, r3 + 80038f4: 693b ldr r3, [r7, #16] + 80038f6: 4293 cmp r3, r2 + 80038f8: d90b bls.n 8003912 + PB_RETURN_ERROR(stream, "string overflow"); + 80038fa: 687b ldr r3, [r7, #4] + 80038fc: 68db ldr r3, [r3, #12] + 80038fe: 2b00 cmp r3, #0 + 8003900: d002 beq.n 8003908 + 8003902: 687b ldr r3, [r7, #4] + 8003904: 68db ldr r3, [r3, #12] + 8003906: e000 b.n 800390a + 8003908: 4b10 ldr r3, [pc, #64] ; (800394c ) + 800390a: 687a ldr r2, [r7, #4] + 800390c: 60d3 str r3, [r2, #12] + 800390e: 2300 movs r3, #0 + 8003910: e013 b.n 800393a + } + + dest[size] = 0; + 8003912: 68fb ldr r3, [r7, #12] + 8003914: 697a ldr r2, [r7, #20] + 8003916: 4413 add r3, r2 + 8003918: 2200 movs r2, #0 + 800391a: 701a strb r2, [r3, #0] + + if (!pb_read(stream, dest, (size_t)size)) + 800391c: 68fb ldr r3, [r7, #12] + 800391e: 461a mov r2, r3 + 8003920: 6979 ldr r1, [r7, #20] + 8003922: 6878 ldr r0, [r7, #4] + 8003924: f7fe fac2 bl 8001eac + 8003928: 4603 mov r3, r0 + 800392a: f083 0301 eor.w r3, r3, #1 + 800392e: b2db uxtb r3, r3 + 8003930: 2b00 cmp r3, #0 + 8003932: d001 beq.n 8003938 + return false; + 8003934: 2300 movs r3, #0 + 8003936: e000 b.n 800393a +#ifdef PB_VALIDATE_UTF8 + if (!pb_validate_utf8((const char*)dest)) + PB_RETURN_ERROR(stream, "invalid utf8"); +#endif + + return true; + 8003938: 2301 movs r3, #1 +} + 800393a: 4618 mov r0, r3 + 800393c: 3718 adds r7, #24 + 800393e: 46bd mov sp, r7 + 8003940: bd80 pop {r7, pc} + 8003942: bf00 nop + 8003944: 08008b40 .word 0x08008b40 + 8003948: 08008a70 .word 0x08008a70 + 800394c: 08008b50 .word 0x08008b50 + +08003950 : + +static bool checkreturn pb_dec_submessage(pb_istream_t *stream, const pb_field_iter_t *field) +{ + 8003950: b580 push {r7, lr} + 8003952: b092 sub sp, #72 ; 0x48 + 8003954: af00 add r7, sp, #0 + 8003956: 6078 str r0, [r7, #4] + 8003958: 6039 str r1, [r7, #0] + bool status = true; + 800395a: 2301 movs r3, #1 + 800395c: f887 3047 strb.w r3, [r7, #71] ; 0x47 + pb_istream_t substream; + + if (!pb_make_string_substream(stream, &substream)) + 8003960: f107 0330 add.w r3, r7, #48 ; 0x30 + 8003964: 4619 mov r1, r3 + 8003966: 6878 ldr r0, [r7, #4] + 8003968: f7fe fd74 bl 8002454 + 800396c: 4603 mov r3, r0 + 800396e: f083 0301 eor.w r3, r3, #1 + 8003972: b2db uxtb r3, r3 + 8003974: 2b00 cmp r3, #0 + 8003976: d001 beq.n 800397c + return false; + 8003978: 2300 movs r3, #0 + 800397a: e07b b.n 8003a74 + + if (field->submsg_desc == NULL) + 800397c: 683b ldr r3, [r7, #0] + 800397e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003980: 2b00 cmp r3, #0 + 8003982: d10b bne.n 800399c + PB_RETURN_ERROR(stream, "invalid field descriptor"); + 8003984: 687b ldr r3, [r7, #4] + 8003986: 68db ldr r3, [r3, #12] + 8003988: 2b00 cmp r3, #0 + 800398a: d002 beq.n 8003992 + 800398c: 687b ldr r3, [r7, #4] + 800398e: 68db ldr r3, [r3, #12] + 8003990: e000 b.n 8003994 + 8003992: 4b3a ldr r3, [pc, #232] ; (8003a7c ) + 8003994: 687a ldr r2, [r7, #4] + 8003996: 60d3 str r3, [r2, #12] + 8003998: 2300 movs r3, #0 + 800399a: e06b b.n 8003a74 + + /* New array entries need to be initialized, while required and optional + * submessages have already been initialized in the top-level pb_decode. */ + if (PB_HTYPE(field->type) == PB_HTYPE_REPEATED || + 800399c: 683b ldr r3, [r7, #0] + 800399e: 7d9b ldrb r3, [r3, #22] + 80039a0: f003 0330 and.w r3, r3, #48 ; 0x30 + 80039a4: 2b20 cmp r3, #32 + 80039a6: d005 beq.n 80039b4 + PB_HTYPE(field->type) == PB_HTYPE_ONEOF) + 80039a8: 683b ldr r3, [r7, #0] + 80039aa: 7d9b ldrb r3, [r3, #22] + 80039ac: f003 0330 and.w r3, r3, #48 ; 0x30 + if (PB_HTYPE(field->type) == PB_HTYPE_REPEATED || + 80039b0: 2b30 cmp r3, #48 ; 0x30 + 80039b2: d122 bne.n 80039fa + { + pb_field_iter_t submsg_iter; + if (pb_field_iter_begin(&submsg_iter, field->submsg_desc, field->pData)) + 80039b4: 683b ldr r3, [r7, #0] + 80039b6: 6a59 ldr r1, [r3, #36] ; 0x24 + 80039b8: 683b ldr r3, [r7, #0] + 80039ba: 69da ldr r2, [r3, #28] + 80039bc: f107 0308 add.w r3, r7, #8 + 80039c0: 4618 mov r0, r3 + 80039c2: f7fe f972 bl 8001caa + 80039c6: 4603 mov r3, r0 + 80039c8: 2b00 cmp r3, #0 + 80039ca: d016 beq.n 80039fa + { + if (!pb_message_set_to_defaults(&submsg_iter)) + 80039cc: f107 0308 add.w r3, r7, #8 + 80039d0: 4618 mov r0, r3 + 80039d2: f7ff f9c4 bl 8002d5e + 80039d6: 4603 mov r3, r0 + 80039d8: f083 0301 eor.w r3, r3, #1 + 80039dc: b2db uxtb r3, r3 + 80039de: 2b00 cmp r3, #0 + 80039e0: d00b beq.n 80039fa + PB_RETURN_ERROR(stream, "failed to set defaults"); + 80039e2: 687b ldr r3, [r7, #4] + 80039e4: 68db ldr r3, [r3, #12] + 80039e6: 2b00 cmp r3, #0 + 80039e8: d002 beq.n 80039f0 + 80039ea: 687b ldr r3, [r7, #4] + 80039ec: 68db ldr r3, [r3, #12] + 80039ee: e000 b.n 80039f2 + 80039f0: 4b23 ldr r3, [pc, #140] ; (8003a80 ) + 80039f2: 687a ldr r2, [r7, #4] + 80039f4: 60d3 str r3, [r2, #12] + 80039f6: 2300 movs r3, #0 + 80039f8: e03c b.n 8003a74 + } + + /* Submessages can have a separate message-level callback that is called + * before decoding the message. Typically it is used to set callback fields + * inside oneofs. */ + if (PB_LTYPE(field->type) == PB_LTYPE_SUBMSG_W_CB && field->pSize != NULL) + 80039fa: 683b ldr r3, [r7, #0] + 80039fc: 7d9b ldrb r3, [r3, #22] + 80039fe: f003 030f and.w r3, r3, #15 + 8003a02: 2b09 cmp r3, #9 + 8003a04: d116 bne.n 8003a34 + 8003a06: 683b ldr r3, [r7, #0] + 8003a08: 6a1b ldr r3, [r3, #32] + 8003a0a: 2b00 cmp r3, #0 + 8003a0c: d012 beq.n 8003a34 + { + /* Message callback is stored right before pSize. */ + pb_callback_t *callback = (pb_callback_t*)field->pSize - 1; + 8003a0e: 683b ldr r3, [r7, #0] + 8003a10: 6a1b ldr r3, [r3, #32] + 8003a12: 3b08 subs r3, #8 + 8003a14: 643b str r3, [r7, #64] ; 0x40 + if (callback->funcs.decode) + 8003a16: 6c3b ldr r3, [r7, #64] ; 0x40 + 8003a18: 681b ldr r3, [r3, #0] + 8003a1a: 2b00 cmp r3, #0 + 8003a1c: d00a beq.n 8003a34 + { + status = callback->funcs.decode(&substream, field, &callback->arg); + 8003a1e: 6c3b ldr r3, [r7, #64] ; 0x40 + 8003a20: 681b ldr r3, [r3, #0] + 8003a22: 6c3a ldr r2, [r7, #64] ; 0x40 + 8003a24: 3204 adds r2, #4 + 8003a26: f107 0030 add.w r0, r7, #48 ; 0x30 + 8003a2a: 6839 ldr r1, [r7, #0] + 8003a2c: 4798 blx r3 + 8003a2e: 4603 mov r3, r0 + 8003a30: f887 3047 strb.w r3, [r7, #71] ; 0x47 + } + } + + /* Now decode the submessage contents */ + if (status) + 8003a34: f897 3047 ldrb.w r3, [r7, #71] ; 0x47 + 8003a38: 2b00 cmp r3, #0 + 8003a3a: d00b beq.n 8003a54 + { + status = pb_decode_noinit(&substream, field->submsg_desc, field->pData); + 8003a3c: 683b ldr r3, [r7, #0] + 8003a3e: 6a59 ldr r1, [r3, #36] ; 0x24 + 8003a40: 683b ldr r3, [r7, #0] + 8003a42: 69da ldr r2, [r3, #28] + 8003a44: f107 0030 add.w r0, r7, #48 ; 0x30 + 8003a48: 2301 movs r3, #1 + 8003a4a: f7ff fbb5 bl 80031b8 + 8003a4e: 4603 mov r3, r0 + 8003a50: f887 3047 strb.w r3, [r7, #71] ; 0x47 + } + + if (!pb_close_string_substream(stream, &substream)) + 8003a54: f107 0330 add.w r3, r7, #48 ; 0x30 + 8003a58: 4619 mov r1, r3 + 8003a5a: 6878 ldr r0, [r7, #4] + 8003a5c: f7fe fd34 bl 80024c8 + 8003a60: 4603 mov r3, r0 + 8003a62: f083 0301 eor.w r3, r3, #1 + 8003a66: b2db uxtb r3, r3 + 8003a68: 2b00 cmp r3, #0 + 8003a6a: d001 beq.n 8003a70 + return false; + 8003a6c: 2300 movs r3, #0 + 8003a6e: e001 b.n 8003a74 + + return status; + 8003a70: f897 3047 ldrb.w r3, [r7, #71] ; 0x47 +} + 8003a74: 4618 mov r0, r3 + 8003a76: 3748 adds r7, #72 ; 0x48 + 8003a78: 46bd mov sp, r7 + 8003a7a: bd80 pop {r7, pc} + 8003a7c: 08008b60 .word 0x08008b60 + 8003a80: 08008af0 .word 0x08008af0 + +08003a84 : + +static bool checkreturn pb_dec_fixed_length_bytes(pb_istream_t *stream, const pb_field_iter_t *field) +{ + 8003a84: b580 push {r7, lr} + 8003a86: b084 sub sp, #16 + 8003a88: af00 add r7, sp, #0 + 8003a8a: 6078 str r0, [r7, #4] + 8003a8c: 6039 str r1, [r7, #0] + uint32_t size; + + if (!pb_decode_varint32(stream, &size)) + 8003a8e: f107 030c add.w r3, r7, #12 + 8003a92: 4619 mov r1, r3 + 8003a94: 6878 ldr r0, [r7, #4] + 8003a96: f7fe fb59 bl 800214c + 8003a9a: 4603 mov r3, r0 + 8003a9c: f083 0301 eor.w r3, r3, #1 + 8003aa0: b2db uxtb r3, r3 + 8003aa2: 2b00 cmp r3, #0 + 8003aa4: d001 beq.n 8003aaa + return false; + 8003aa6: 2300 movs r3, #0 + 8003aa8: e037 b.n 8003b1a + + if (size > PB_SIZE_MAX) + 8003aaa: 68fb ldr r3, [r7, #12] + 8003aac: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8003ab0: d30b bcc.n 8003aca + PB_RETURN_ERROR(stream, "bytes overflow"); + 8003ab2: 687b ldr r3, [r7, #4] + 8003ab4: 68db ldr r3, [r3, #12] + 8003ab6: 2b00 cmp r3, #0 + 8003ab8: d002 beq.n 8003ac0 + 8003aba: 687b ldr r3, [r7, #4] + 8003abc: 68db ldr r3, [r3, #12] + 8003abe: e000 b.n 8003ac2 + 8003ac0: 4b18 ldr r3, [pc, #96] ; (8003b24 ) + 8003ac2: 687a ldr r2, [r7, #4] + 8003ac4: 60d3 str r3, [r2, #12] + 8003ac6: 2300 movs r3, #0 + 8003ac8: e027 b.n 8003b1a + + if (size == 0) + 8003aca: 68fb ldr r3, [r7, #12] + 8003acc: 2b00 cmp r3, #0 + 8003ace: d109 bne.n 8003ae4 + { + /* As a special case, treat empty bytes string as all zeros for fixed_length_bytes. */ + memset(field->pData, 0, (size_t)field->data_size); + 8003ad0: 683b ldr r3, [r7, #0] + 8003ad2: 69d8 ldr r0, [r3, #28] + 8003ad4: 683b ldr r3, [r7, #0] + 8003ad6: 8a5b ldrh r3, [r3, #18] + 8003ad8: 461a mov r2, r3 + 8003ada: 2100 movs r1, #0 + 8003adc: f004 ff6e bl 80089bc + return true; + 8003ae0: 2301 movs r3, #1 + 8003ae2: e01a b.n 8003b1a + } + + if (size != field->data_size) + 8003ae4: 683b ldr r3, [r7, #0] + 8003ae6: 8a5b ldrh r3, [r3, #18] + 8003ae8: 461a mov r2, r3 + 8003aea: 68fb ldr r3, [r7, #12] + 8003aec: 429a cmp r2, r3 + 8003aee: d00b beq.n 8003b08 + PB_RETURN_ERROR(stream, "incorrect fixed length bytes size"); + 8003af0: 687b ldr r3, [r7, #4] + 8003af2: 68db ldr r3, [r3, #12] + 8003af4: 2b00 cmp r3, #0 + 8003af6: d002 beq.n 8003afe + 8003af8: 687b ldr r3, [r7, #4] + 8003afa: 68db ldr r3, [r3, #12] + 8003afc: e000 b.n 8003b00 + 8003afe: 4b0a ldr r3, [pc, #40] ; (8003b28 ) + 8003b00: 687a ldr r2, [r7, #4] + 8003b02: 60d3 str r3, [r2, #12] + 8003b04: 2300 movs r3, #0 + 8003b06: e008 b.n 8003b1a + + return pb_read(stream, (pb_byte_t*)field->pData, (size_t)field->data_size); + 8003b08: 683b ldr r3, [r7, #0] + 8003b0a: 69d9 ldr r1, [r3, #28] + 8003b0c: 683b ldr r3, [r7, #0] + 8003b0e: 8a5b ldrh r3, [r3, #18] + 8003b10: 461a mov r2, r3 + 8003b12: 6878 ldr r0, [r7, #4] + 8003b14: f7fe f9ca bl 8001eac + 8003b18: 4603 mov r3, r0 +} + 8003b1a: 4618 mov r0, r3 + 8003b1c: 3710 adds r7, #16 + 8003b1e: 46bd mov sp, r7 + 8003b20: bd80 pop {r7, pc} + 8003b22: bf00 nop + 8003b24: 08008b30 .word 0x08008b30 + 8003b28: 08008b7c .word 0x08008b7c + +08003b2c : +/******************************* + * pb_ostream_t implementation * + *******************************/ + +static bool checkreturn buf_write(pb_ostream_t *stream, const pb_byte_t *buf, size_t count) +{ + 8003b2c: b480 push {r7} + 8003b2e: b087 sub sp, #28 + 8003b30: af00 add r7, sp, #0 + 8003b32: 60f8 str r0, [r7, #12] + 8003b34: 60b9 str r1, [r7, #8] + 8003b36: 607a str r2, [r7, #4] + size_t i; + pb_byte_t *dest = (pb_byte_t*)stream->state; + 8003b38: 68fb ldr r3, [r7, #12] + 8003b3a: 685b ldr r3, [r3, #4] + 8003b3c: 613b str r3, [r7, #16] + stream->state = dest + count; + 8003b3e: 693a ldr r2, [r7, #16] + 8003b40: 687b ldr r3, [r7, #4] + 8003b42: 441a add r2, r3 + 8003b44: 68fb ldr r3, [r7, #12] + 8003b46: 605a str r2, [r3, #4] + + for (i = 0; i < count; i++) + 8003b48: 2300 movs r3, #0 + 8003b4a: 617b str r3, [r7, #20] + 8003b4c: e00a b.n 8003b64 + dest[i] = buf[i]; + 8003b4e: 68ba ldr r2, [r7, #8] + 8003b50: 697b ldr r3, [r7, #20] + 8003b52: 441a add r2, r3 + 8003b54: 6939 ldr r1, [r7, #16] + 8003b56: 697b ldr r3, [r7, #20] + 8003b58: 440b add r3, r1 + 8003b5a: 7812 ldrb r2, [r2, #0] + 8003b5c: 701a strb r2, [r3, #0] + for (i = 0; i < count; i++) + 8003b5e: 697b ldr r3, [r7, #20] + 8003b60: 3301 adds r3, #1 + 8003b62: 617b str r3, [r7, #20] + 8003b64: 697a ldr r2, [r7, #20] + 8003b66: 687b ldr r3, [r7, #4] + 8003b68: 429a cmp r2, r3 + 8003b6a: d3f0 bcc.n 8003b4e + + return true; + 8003b6c: 2301 movs r3, #1 +} + 8003b6e: 4618 mov r0, r3 + 8003b70: 371c adds r7, #28 + 8003b72: 46bd mov sp, r7 + 8003b74: f85d 7b04 ldr.w r7, [sp], #4 + 8003b78: 4770 bx lr + ... + +08003b7c : + +pb_ostream_t pb_ostream_from_buffer(pb_byte_t *buf, size_t bufsize) +{ + 8003b7c: b4b0 push {r4, r5, r7} + 8003b7e: b08b sub sp, #44 ; 0x2c + 8003b80: af00 add r7, sp, #0 + 8003b82: 60f8 str r0, [r7, #12] + 8003b84: 60b9 str r1, [r7, #8] + 8003b86: 607a str r2, [r7, #4] + pb_ostream_t stream; +#ifdef PB_BUFFER_ONLY + stream.callback = (void*)1; /* Just a marker value */ +#else + stream.callback = &buf_write; + 8003b88: 4b0b ldr r3, [pc, #44] ; (8003bb8 ) + 8003b8a: 617b str r3, [r7, #20] +#endif + stream.state = buf; + 8003b8c: 68bb ldr r3, [r7, #8] + 8003b8e: 61bb str r3, [r7, #24] + stream.max_size = bufsize; + 8003b90: 687b ldr r3, [r7, #4] + 8003b92: 61fb str r3, [r7, #28] + stream.bytes_written = 0; + 8003b94: 2300 movs r3, #0 + 8003b96: 623b str r3, [r7, #32] +#ifndef PB_NO_ERRMSG + stream.errmsg = NULL; + 8003b98: 2300 movs r3, #0 + 8003b9a: 627b str r3, [r7, #36] ; 0x24 +#endif + return stream; + 8003b9c: 68fb ldr r3, [r7, #12] + 8003b9e: 461d mov r5, r3 + 8003ba0: f107 0414 add.w r4, r7, #20 + 8003ba4: cc0f ldmia r4!, {r0, r1, r2, r3} + 8003ba6: c50f stmia r5!, {r0, r1, r2, r3} + 8003ba8: 6823 ldr r3, [r4, #0] + 8003baa: 602b str r3, [r5, #0] +} + 8003bac: 68f8 ldr r0, [r7, #12] + 8003bae: 372c adds r7, #44 ; 0x2c + 8003bb0: 46bd mov sp, r7 + 8003bb2: bcb0 pop {r4, r5, r7} + 8003bb4: 4770 bx lr + 8003bb6: bf00 nop + 8003bb8: 08003b2d .word 0x08003b2d + +08003bbc : + +bool checkreturn pb_write(pb_ostream_t *stream, const pb_byte_t *buf, size_t count) +{ + 8003bbc: b580 push {r7, lr} + 8003bbe: b084 sub sp, #16 + 8003bc0: af00 add r7, sp, #0 + 8003bc2: 60f8 str r0, [r7, #12] + 8003bc4: 60b9 str r1, [r7, #8] + 8003bc6: 607a str r2, [r7, #4] + if (count > 0 && stream->callback != NULL) + 8003bc8: 687b ldr r3, [r7, #4] + 8003bca: 2b00 cmp r3, #0 + 8003bcc: d02f beq.n 8003c2e + 8003bce: 68fb ldr r3, [r7, #12] + 8003bd0: 681b ldr r3, [r3, #0] + 8003bd2: 2b00 cmp r3, #0 + 8003bd4: d02b beq.n 8003c2e + { + if (stream->bytes_written + count > stream->max_size) + 8003bd6: 68fb ldr r3, [r7, #12] + 8003bd8: 68da ldr r2, [r3, #12] + 8003bda: 687b ldr r3, [r7, #4] + 8003bdc: 441a add r2, r3 + 8003bde: 68fb ldr r3, [r7, #12] + 8003be0: 689b ldr r3, [r3, #8] + 8003be2: 429a cmp r2, r3 + 8003be4: d90b bls.n 8003bfe + PB_RETURN_ERROR(stream, "stream full"); + 8003be6: 68fb ldr r3, [r7, #12] + 8003be8: 691b ldr r3, [r3, #16] + 8003bea: 2b00 cmp r3, #0 + 8003bec: d002 beq.n 8003bf4 + 8003bee: 68fb ldr r3, [r7, #12] + 8003bf0: 691b ldr r3, [r3, #16] + 8003bf2: e000 b.n 8003bf6 + 8003bf4: 4b13 ldr r3, [pc, #76] ; (8003c44 ) + 8003bf6: 68fa ldr r2, [r7, #12] + 8003bf8: 6113 str r3, [r2, #16] + 8003bfa: 2300 movs r3, #0 + 8003bfc: e01e b.n 8003c3c + +#ifdef PB_BUFFER_ONLY + if (!buf_write(stream, buf, count)) + PB_RETURN_ERROR(stream, "io error"); +#else + if (!stream->callback(stream, buf, count)) + 8003bfe: 68fb ldr r3, [r7, #12] + 8003c00: 681b ldr r3, [r3, #0] + 8003c02: 687a ldr r2, [r7, #4] + 8003c04: 68b9 ldr r1, [r7, #8] + 8003c06: 68f8 ldr r0, [r7, #12] + 8003c08: 4798 blx r3 + 8003c0a: 4603 mov r3, r0 + 8003c0c: f083 0301 eor.w r3, r3, #1 + 8003c10: b2db uxtb r3, r3 + 8003c12: 2b00 cmp r3, #0 + 8003c14: d00b beq.n 8003c2e + PB_RETURN_ERROR(stream, "io error"); + 8003c16: 68fb ldr r3, [r7, #12] + 8003c18: 691b ldr r3, [r3, #16] + 8003c1a: 2b00 cmp r3, #0 + 8003c1c: d002 beq.n 8003c24 + 8003c1e: 68fb ldr r3, [r7, #12] + 8003c20: 691b ldr r3, [r3, #16] + 8003c22: e000 b.n 8003c26 + 8003c24: 4b08 ldr r3, [pc, #32] ; (8003c48 ) + 8003c26: 68fa ldr r2, [r7, #12] + 8003c28: 6113 str r3, [r2, #16] + 8003c2a: 2300 movs r3, #0 + 8003c2c: e006 b.n 8003c3c +#endif + } + + stream->bytes_written += count; + 8003c2e: 68fb ldr r3, [r7, #12] + 8003c30: 68da ldr r2, [r3, #12] + 8003c32: 687b ldr r3, [r7, #4] + 8003c34: 441a add r2, r3 + 8003c36: 68fb ldr r3, [r7, #12] + 8003c38: 60da str r2, [r3, #12] + return true; + 8003c3a: 2301 movs r3, #1 +} + 8003c3c: 4618 mov r0, r3 + 8003c3e: 3710 adds r7, #16 + 8003c40: 46bd mov sp, r7 + 8003c42: bd80 pop {r7, pc} + 8003c44: 08008ba0 .word 0x08008ba0 + 8003c48: 08008bac .word 0x08008bac + +08003c4c : +/* Read a bool value without causing undefined behavior even if the value + * is invalid. See issue #434 and + * https://stackoverflow.com/questions/27661768/weird-results-for-conditional + */ +static bool safe_read_bool(const void *pSize) +{ + 8003c4c: b480 push {r7} + 8003c4e: b085 sub sp, #20 + 8003c50: af00 add r7, sp, #0 + 8003c52: 6078 str r0, [r7, #4] + const char *p = (const char *)pSize; + 8003c54: 687b ldr r3, [r7, #4] + 8003c56: 60bb str r3, [r7, #8] + size_t i; + for (i = 0; i < sizeof(bool); i++) + 8003c58: 2300 movs r3, #0 + 8003c5a: 60fb str r3, [r7, #12] + 8003c5c: e00a b.n 8003c74 + { + if (p[i] != 0) + 8003c5e: 68ba ldr r2, [r7, #8] + 8003c60: 68fb ldr r3, [r7, #12] + 8003c62: 4413 add r3, r2 + 8003c64: 781b ldrb r3, [r3, #0] + 8003c66: 2b00 cmp r3, #0 + 8003c68: d001 beq.n 8003c6e + return true; + 8003c6a: 2301 movs r3, #1 + 8003c6c: e006 b.n 8003c7c + for (i = 0; i < sizeof(bool); i++) + 8003c6e: 68fb ldr r3, [r7, #12] + 8003c70: 3301 adds r3, #1 + 8003c72: 60fb str r3, [r7, #12] + 8003c74: 68fb ldr r3, [r7, #12] + 8003c76: 2b00 cmp r3, #0 + 8003c78: d0f1 beq.n 8003c5e + } + return false; + 8003c7a: 2300 movs r3, #0 +} + 8003c7c: 4618 mov r0, r3 + 8003c7e: 3714 adds r7, #20 + 8003c80: 46bd mov sp, r7 + 8003c82: f85d 7b04 ldr.w r7, [sp], #4 + 8003c86: 4770 bx lr + +08003c88 : + +/* Encode a static array. Handles the size calculations and possible packing. */ +static bool checkreturn encode_array(pb_ostream_t *stream, pb_field_iter_t *field) +{ + 8003c88: b590 push {r4, r7, lr} + 8003c8a: b08d sub sp, #52 ; 0x34 + 8003c8c: af00 add r7, sp, #0 + 8003c8e: 6078 str r0, [r7, #4] + 8003c90: 6039 str r1, [r7, #0] + pb_size_t count; +#ifndef PB_ENCODE_ARRAYS_UNPACKED + size_t size; +#endif + + count = *(pb_size_t*)field->pSize; + 8003c92: 683b ldr r3, [r7, #0] + 8003c94: 6a1b ldr r3, [r3, #32] + 8003c96: 881b ldrh r3, [r3, #0] + 8003c98: 84bb strh r3, [r7, #36] ; 0x24 + + if (count == 0) + 8003c9a: 8cbb ldrh r3, [r7, #36] ; 0x24 + 8003c9c: 2b00 cmp r3, #0 + 8003c9e: d101 bne.n 8003ca4 + return true; + 8003ca0: 2301 movs r3, #1 + 8003ca2: e13c b.n 8003f1e + + if (PB_ATYPE(field->type) != PB_ATYPE_POINTER && count > field->array_size) + 8003ca4: 683b ldr r3, [r7, #0] + 8003ca6: 7d9b ldrb r3, [r3, #22] + 8003ca8: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 8003cac: 2b80 cmp r3, #128 ; 0x80 + 8003cae: d010 beq.n 8003cd2 + 8003cb0: 683b ldr r3, [r7, #0] + 8003cb2: 8a9b ldrh r3, [r3, #20] + 8003cb4: 8cba ldrh r2, [r7, #36] ; 0x24 + 8003cb6: 429a cmp r2, r3 + 8003cb8: d90b bls.n 8003cd2 + PB_RETURN_ERROR(stream, "array max size exceeded"); + 8003cba: 687b ldr r3, [r7, #4] + 8003cbc: 691b ldr r3, [r3, #16] + 8003cbe: 2b00 cmp r3, #0 + 8003cc0: d002 beq.n 8003cc8 + 8003cc2: 687b ldr r3, [r7, #4] + 8003cc4: 691b ldr r3, [r3, #16] + 8003cc6: e000 b.n 8003cca + 8003cc8: 4b97 ldr r3, [pc, #604] ; (8003f28 ) + 8003cca: 687a ldr r2, [r7, #4] + 8003ccc: 6113 str r3, [r2, #16] + 8003cce: 2300 movs r3, #0 + 8003cd0: e125 b.n 8003f1e + +#ifndef PB_ENCODE_ARRAYS_UNPACKED + /* We always pack arrays if the datatype allows it. */ + if (PB_LTYPE(field->type) <= PB_LTYPE_LAST_PACKABLE) + 8003cd2: 683b ldr r3, [r7, #0] + 8003cd4: 7d9b ldrb r3, [r3, #22] + 8003cd6: f003 030f and.w r3, r3, #15 + 8003cda: 2b05 cmp r3, #5 + 8003cdc: f200 80b2 bhi.w 8003e44 + { + if (!pb_encode_tag(stream, PB_WT_STRING, field->tag)) + 8003ce0: 683b ldr r3, [r7, #0] + 8003ce2: 8a1b ldrh r3, [r3, #16] + 8003ce4: 461a mov r2, r3 + 8003ce6: 2102 movs r1, #2 + 8003ce8: 6878 ldr r0, [r7, #4] + 8003cea: f000 fce7 bl 80046bc + 8003cee: 4603 mov r3, r0 + 8003cf0: f083 0301 eor.w r3, r3, #1 + 8003cf4: b2db uxtb r3, r3 + 8003cf6: 2b00 cmp r3, #0 + 8003cf8: d001 beq.n 8003cfe + return false; + 8003cfa: 2300 movs r3, #0 + 8003cfc: e10f b.n 8003f1e + + /* Determine the total size of packed array. */ + if (PB_LTYPE(field->type) == PB_LTYPE_FIXED32) + 8003cfe: 683b ldr r3, [r7, #0] + 8003d00: 7d9b ldrb r3, [r3, #22] + 8003d02: f003 030f and.w r3, r3, #15 + 8003d06: 2b04 cmp r3, #4 + 8003d08: d103 bne.n 8003d12 + { + size = 4 * (size_t)count; + 8003d0a: 8cbb ldrh r3, [r7, #36] ; 0x24 + 8003d0c: 009b lsls r3, r3, #2 + 8003d0e: 62bb str r3, [r7, #40] ; 0x28 + 8003d10: e047 b.n 8003da2 + } + else if (PB_LTYPE(field->type) == PB_LTYPE_FIXED64) + 8003d12: 683b ldr r3, [r7, #0] + 8003d14: 7d9b ldrb r3, [r3, #22] + 8003d16: f003 030f and.w r3, r3, #15 + 8003d1a: 2b05 cmp r3, #5 + 8003d1c: d103 bne.n 8003d26 + { + size = 8 * (size_t)count; + 8003d1e: 8cbb ldrh r3, [r7, #36] ; 0x24 + 8003d20: 00db lsls r3, r3, #3 + 8003d22: 62bb str r3, [r7, #40] ; 0x28 + 8003d24: e03d b.n 8003da2 + } + else + { + pb_ostream_t sizestream = PB_OSTREAM_SIZING; + 8003d26: f107 0308 add.w r3, r7, #8 + 8003d2a: 2200 movs r2, #0 + 8003d2c: 601a str r2, [r3, #0] + 8003d2e: 605a str r2, [r3, #4] + 8003d30: 609a str r2, [r3, #8] + 8003d32: 60da str r2, [r3, #12] + 8003d34: 611a str r2, [r3, #16] + void *pData_orig = field->pData; + 8003d36: 683b ldr r3, [r7, #0] + 8003d38: 69db ldr r3, [r3, #28] + 8003d3a: 61fb str r3, [r7, #28] + for (i = 0; i < count; i++) + 8003d3c: 2300 movs r3, #0 + 8003d3e: 85fb strh r3, [r7, #46] ; 0x2e + 8003d40: e026 b.n 8003d90 + { + if (!pb_enc_varint(&sizestream, field)) + 8003d42: f107 0308 add.w r3, r7, #8 + 8003d46: 6839 ldr r1, [r7, #0] + 8003d48: 4618 mov r0, r3 + 8003d4a: f000 fdf1 bl 8004930 + 8003d4e: 4603 mov r3, r0 + 8003d50: f083 0301 eor.w r3, r3, #1 + 8003d54: b2db uxtb r3, r3 + 8003d56: 2b00 cmp r3, #0 + 8003d58: d010 beq.n 8003d7c + PB_RETURN_ERROR(stream, PB_GET_ERROR(&sizestream)); + 8003d5a: 687b ldr r3, [r7, #4] + 8003d5c: 691b ldr r3, [r3, #16] + 8003d5e: 2b00 cmp r3, #0 + 8003d60: d002 beq.n 8003d68 + 8003d62: 687b ldr r3, [r7, #4] + 8003d64: 691b ldr r3, [r3, #16] + 8003d66: e005 b.n 8003d74 + 8003d68: 69bb ldr r3, [r7, #24] + 8003d6a: 2b00 cmp r3, #0 + 8003d6c: d001 beq.n 8003d72 + 8003d6e: 69bb ldr r3, [r7, #24] + 8003d70: e000 b.n 8003d74 + 8003d72: 4b6e ldr r3, [pc, #440] ; (8003f2c ) + 8003d74: 687a ldr r2, [r7, #4] + 8003d76: 6113 str r3, [r2, #16] + 8003d78: 2300 movs r3, #0 + 8003d7a: e0d0 b.n 8003f1e + field->pData = (char*)field->pData + field->data_size; + 8003d7c: 683b ldr r3, [r7, #0] + 8003d7e: 69db ldr r3, [r3, #28] + 8003d80: 683a ldr r2, [r7, #0] + 8003d82: 8a52 ldrh r2, [r2, #18] + 8003d84: 441a add r2, r3 + 8003d86: 683b ldr r3, [r7, #0] + 8003d88: 61da str r2, [r3, #28] + for (i = 0; i < count; i++) + 8003d8a: 8dfb ldrh r3, [r7, #46] ; 0x2e + 8003d8c: 3301 adds r3, #1 + 8003d8e: 85fb strh r3, [r7, #46] ; 0x2e + 8003d90: 8dfa ldrh r2, [r7, #46] ; 0x2e + 8003d92: 8cbb ldrh r3, [r7, #36] ; 0x24 + 8003d94: 429a cmp r2, r3 + 8003d96: d3d4 bcc.n 8003d42 + } + field->pData = pData_orig; + 8003d98: 683b ldr r3, [r7, #0] + 8003d9a: 69fa ldr r2, [r7, #28] + 8003d9c: 61da str r2, [r3, #28] + size = sizestream.bytes_written; + 8003d9e: 697b ldr r3, [r7, #20] + 8003da0: 62bb str r3, [r7, #40] ; 0x28 + } + + if (!pb_encode_varint(stream, (pb_uint64_t)size)) + 8003da2: 6abb ldr r3, [r7, #40] ; 0x28 + 8003da4: f04f 0400 mov.w r4, #0 + 8003da8: 461a mov r2, r3 + 8003daa: 4623 mov r3, r4 + 8003dac: 6878 ldr r0, [r7, #4] + 8003dae: f000 fba9 bl 8004504 + 8003db2: 4603 mov r3, r0 + 8003db4: f083 0301 eor.w r3, r3, #1 + 8003db8: b2db uxtb r3, r3 + 8003dba: 2b00 cmp r3, #0 + 8003dbc: d001 beq.n 8003dc2 + return false; + 8003dbe: 2300 movs r3, #0 + 8003dc0: e0ad b.n 8003f1e + + if (stream->callback == NULL) + 8003dc2: 687b ldr r3, [r7, #4] + 8003dc4: 681b ldr r3, [r3, #0] + 8003dc6: 2b00 cmp r3, #0 + 8003dc8: d106 bne.n 8003dd8 + return pb_write(stream, NULL, size); /* Just sizing.. */ + 8003dca: 6aba ldr r2, [r7, #40] ; 0x28 + 8003dcc: 2100 movs r1, #0 + 8003dce: 6878 ldr r0, [r7, #4] + 8003dd0: f7ff fef4 bl 8003bbc + 8003dd4: 4603 mov r3, r0 + 8003dd6: e0a2 b.n 8003f1e + + /* Write the data */ + for (i = 0; i < count; i++) + 8003dd8: 2300 movs r3, #0 + 8003dda: 85fb strh r3, [r7, #46] ; 0x2e + 8003ddc: e02d b.n 8003e3a + { + if (PB_LTYPE(field->type) == PB_LTYPE_FIXED32 || PB_LTYPE(field->type) == PB_LTYPE_FIXED64) + 8003dde: 683b ldr r3, [r7, #0] + 8003de0: 7d9b ldrb r3, [r3, #22] + 8003de2: f003 030f and.w r3, r3, #15 + 8003de6: 2b04 cmp r3, #4 + 8003de8: d005 beq.n 8003df6 + 8003dea: 683b ldr r3, [r7, #0] + 8003dec: 7d9b ldrb r3, [r3, #22] + 8003dee: f003 030f and.w r3, r3, #15 + 8003df2: 2b05 cmp r3, #5 + 8003df4: d10b bne.n 8003e0e + { + if (!pb_enc_fixed(stream, field)) + 8003df6: 6839 ldr r1, [r7, #0] + 8003df8: 6878 ldr r0, [r7, #4] + 8003dfa: f000 fe4f bl 8004a9c + 8003dfe: 4603 mov r3, r0 + 8003e00: f083 0301 eor.w r3, r3, #1 + 8003e04: b2db uxtb r3, r3 + 8003e06: 2b00 cmp r3, #0 + 8003e08: d00d beq.n 8003e26 + return false; + 8003e0a: 2300 movs r3, #0 + 8003e0c: e087 b.n 8003f1e + } + else + { + if (!pb_enc_varint(stream, field)) + 8003e0e: 6839 ldr r1, [r7, #0] + 8003e10: 6878 ldr r0, [r7, #4] + 8003e12: f000 fd8d bl 8004930 + 8003e16: 4603 mov r3, r0 + 8003e18: f083 0301 eor.w r3, r3, #1 + 8003e1c: b2db uxtb r3, r3 + 8003e1e: 2b00 cmp r3, #0 + 8003e20: d001 beq.n 8003e26 + return false; + 8003e22: 2300 movs r3, #0 + 8003e24: e07b b.n 8003f1e + } + + field->pData = (char*)field->pData + field->data_size; + 8003e26: 683b ldr r3, [r7, #0] + 8003e28: 69db ldr r3, [r3, #28] + 8003e2a: 683a ldr r2, [r7, #0] + 8003e2c: 8a52 ldrh r2, [r2, #18] + 8003e2e: 441a add r2, r3 + 8003e30: 683b ldr r3, [r7, #0] + 8003e32: 61da str r2, [r3, #28] + for (i = 0; i < count; i++) + 8003e34: 8dfb ldrh r3, [r7, #46] ; 0x2e + 8003e36: 3301 adds r3, #1 + 8003e38: 85fb strh r3, [r7, #46] ; 0x2e + 8003e3a: 8dfa ldrh r2, [r7, #46] ; 0x2e + 8003e3c: 8cbb ldrh r3, [r7, #36] ; 0x24 + 8003e3e: 429a cmp r2, r3 + 8003e40: d3cd bcc.n 8003dde + 8003e42: e06b b.n 8003f1c + } + } + else /* Unpacked fields */ +#endif + { + for (i = 0; i < count; i++) + 8003e44: 2300 movs r3, #0 + 8003e46: 85fb strh r3, [r7, #46] ; 0x2e + 8003e48: e064 b.n 8003f14 + { + /* Normally the data is stored directly in the array entries, but + * for pointer-type string and bytes fields, the array entries are + * actually pointers themselves also. So we have to dereference once + * more to get to the actual data. */ + if (PB_ATYPE(field->type) == PB_ATYPE_POINTER && + 8003e4a: 683b ldr r3, [r7, #0] + 8003e4c: 7d9b ldrb r3, [r3, #22] + 8003e4e: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 8003e52: 2b80 cmp r3, #128 ; 0x80 + 8003e54: d147 bne.n 8003ee6 + (PB_LTYPE(field->type) == PB_LTYPE_STRING || + 8003e56: 683b ldr r3, [r7, #0] + 8003e58: 7d9b ldrb r3, [r3, #22] + 8003e5a: f003 030f and.w r3, r3, #15 + if (PB_ATYPE(field->type) == PB_ATYPE_POINTER && + 8003e5e: 2b07 cmp r3, #7 + 8003e60: d005 beq.n 8003e6e + PB_LTYPE(field->type) == PB_LTYPE_BYTES)) + 8003e62: 683b ldr r3, [r7, #0] + 8003e64: 7d9b ldrb r3, [r3, #22] + 8003e66: f003 030f and.w r3, r3, #15 + (PB_LTYPE(field->type) == PB_LTYPE_STRING || + 8003e6a: 2b06 cmp r3, #6 + 8003e6c: d13b bne.n 8003ee6 + { + bool status; + void *pData_orig = field->pData; + 8003e6e: 683b ldr r3, [r7, #0] + 8003e70: 69db ldr r3, [r3, #28] + 8003e72: 623b str r3, [r7, #32] + field->pData = *(void* const*)field->pData; + 8003e74: 683b ldr r3, [r7, #0] + 8003e76: 69db ldr r3, [r3, #28] + 8003e78: 681a ldr r2, [r3, #0] + 8003e7a: 683b ldr r3, [r7, #0] + 8003e7c: 61da str r2, [r3, #28] + + if (!field->pData) + 8003e7e: 683b ldr r3, [r7, #0] + 8003e80: 69db ldr r3, [r3, #28] + 8003e82: 2b00 cmp r3, #0 + 8003e84: d11c bne.n 8003ec0 + { + /* Null pointer in array is treated as empty string / bytes */ + status = pb_encode_tag_for_field(stream, field) && + 8003e86: 6839 ldr r1, [r7, #0] + 8003e88: 6878 ldr r0, [r7, #4] + 8003e8a: f000 fc3b bl 8004704 + 8003e8e: 4603 mov r3, r0 + 8003e90: 2b00 cmp r3, #0 + 8003e92: d00b beq.n 8003eac + pb_encode_varint(stream, 0); + 8003e94: f04f 0200 mov.w r2, #0 + 8003e98: f04f 0300 mov.w r3, #0 + 8003e9c: 6878 ldr r0, [r7, #4] + 8003e9e: f000 fb31 bl 8004504 + 8003ea2: 4603 mov r3, r0 + status = pb_encode_tag_for_field(stream, field) && + 8003ea4: 2b00 cmp r3, #0 + 8003ea6: d001 beq.n 8003eac + 8003ea8: 2301 movs r3, #1 + 8003eaa: e000 b.n 8003eae + 8003eac: 2300 movs r3, #0 + 8003eae: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8003eb2: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8003eb6: f003 0301 and.w r3, r3, #1 + 8003eba: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8003ebe: e006 b.n 8003ece + } + else + { + status = encode_basic_field(stream, field); + 8003ec0: 6839 ldr r1, [r7, #0] + 8003ec2: 6878 ldr r0, [r7, #4] + 8003ec4: f000 f8fe bl 80040c4 + 8003ec8: 4603 mov r3, r0 + 8003eca: f887 3027 strb.w r3, [r7, #39] ; 0x27 + } + + field->pData = pData_orig; + 8003ece: 683b ldr r3, [r7, #0] + 8003ed0: 6a3a ldr r2, [r7, #32] + 8003ed2: 61da str r2, [r3, #28] + + if (!status) + 8003ed4: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8003ed8: f083 0301 eor.w r3, r3, #1 + 8003edc: b2db uxtb r3, r3 + 8003ede: 2b00 cmp r3, #0 + 8003ee0: d00d beq.n 8003efe + return false; + 8003ee2: 2300 movs r3, #0 + 8003ee4: e01b b.n 8003f1e + } + else + { + if (!encode_basic_field(stream, field)) + 8003ee6: 6839 ldr r1, [r7, #0] + 8003ee8: 6878 ldr r0, [r7, #4] + 8003eea: f000 f8eb bl 80040c4 + 8003eee: 4603 mov r3, r0 + 8003ef0: f083 0301 eor.w r3, r3, #1 + 8003ef4: b2db uxtb r3, r3 + 8003ef6: 2b00 cmp r3, #0 + 8003ef8: d002 beq.n 8003f00 + return false; + 8003efa: 2300 movs r3, #0 + 8003efc: e00f b.n 8003f1e + { + 8003efe: bf00 nop + } + field->pData = (char*)field->pData + field->data_size; + 8003f00: 683b ldr r3, [r7, #0] + 8003f02: 69db ldr r3, [r3, #28] + 8003f04: 683a ldr r2, [r7, #0] + 8003f06: 8a52 ldrh r2, [r2, #18] + 8003f08: 441a add r2, r3 + 8003f0a: 683b ldr r3, [r7, #0] + 8003f0c: 61da str r2, [r3, #28] + for (i = 0; i < count; i++) + 8003f0e: 8dfb ldrh r3, [r7, #46] ; 0x2e + 8003f10: 3301 adds r3, #1 + 8003f12: 85fb strh r3, [r7, #46] ; 0x2e + 8003f14: 8dfa ldrh r2, [r7, #46] ; 0x2e + 8003f16: 8cbb ldrh r3, [r7, #36] ; 0x24 + 8003f18: 429a cmp r2, r3 + 8003f1a: d396 bcc.n 8003e4a + } + } + + return true; + 8003f1c: 2301 movs r3, #1 +} + 8003f1e: 4618 mov r0, r3 + 8003f20: 3734 adds r7, #52 ; 0x34 + 8003f22: 46bd mov sp, r7 + 8003f24: bd90 pop {r4, r7, pc} + 8003f26: bf00 nop + 8003f28: 08008bb8 .word 0x08008bb8 + 8003f2c: 08008bd0 .word 0x08008bd0 + +08003f30 : + +/* In proto3, all fields are optional and are only encoded if their value is "non-zero". + * This function implements the check for the zero value. */ +static bool checkreturn pb_check_proto3_default_value(const pb_field_iter_t *field) +{ + 8003f30: b580 push {r7, lr} + 8003f32: b090 sub sp, #64 ; 0x40 + 8003f34: af00 add r7, sp, #0 + 8003f36: 6078 str r0, [r7, #4] + pb_type_t type = field->type; + 8003f38: 687b ldr r3, [r7, #4] + 8003f3a: 7d9b ldrb r3, [r3, #22] + 8003f3c: f887 303d strb.w r3, [r7, #61] ; 0x3d + + if (PB_ATYPE(type) == PB_ATYPE_STATIC) + 8003f40: f897 303d ldrb.w r3, [r7, #61] ; 0x3d + 8003f44: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 8003f48: 2b00 cmp r3, #0 + 8003f4a: f040 809f bne.w 800408c + { + if (PB_HTYPE(type) == PB_HTYPE_REQUIRED) + 8003f4e: f897 303d ldrb.w r3, [r7, #61] ; 0x3d + 8003f52: f003 0330 and.w r3, r3, #48 ; 0x30 + 8003f56: 2b00 cmp r3, #0 + 8003f58: d101 bne.n 8003f5e + { + /* Required proto2 fields inside proto3 submessage, pretty rare case */ + return false; + 8003f5a: 2300 movs r3, #0 + 8003f5c: e0ad b.n 80040ba + } + else if (PB_HTYPE(type) == PB_HTYPE_REPEATED) + 8003f5e: f897 303d ldrb.w r3, [r7, #61] ; 0x3d + 8003f62: f003 0330 and.w r3, r3, #48 ; 0x30 + 8003f66: 2b20 cmp r3, #32 + 8003f68: d108 bne.n 8003f7c + { + /* Repeated fields inside proto3 submessage: present if count != 0 */ + return *(const pb_size_t*)field->pSize == 0; + 8003f6a: 687b ldr r3, [r7, #4] + 8003f6c: 6a1b ldr r3, [r3, #32] + 8003f6e: 881b ldrh r3, [r3, #0] + 8003f70: 2b00 cmp r3, #0 + 8003f72: bf0c ite eq + 8003f74: 2301 moveq r3, #1 + 8003f76: 2300 movne r3, #0 + 8003f78: b2db uxtb r3, r3 + 8003f7a: e09e b.n 80040ba + } + else if (PB_HTYPE(type) == PB_HTYPE_ONEOF) + 8003f7c: f897 303d ldrb.w r3, [r7, #61] ; 0x3d + 8003f80: f003 0330 and.w r3, r3, #48 ; 0x30 + 8003f84: 2b30 cmp r3, #48 ; 0x30 + 8003f86: d108 bne.n 8003f9a + { + /* Oneof fields */ + return *(const pb_size_t*)field->pSize == 0; + 8003f88: 687b ldr r3, [r7, #4] + 8003f8a: 6a1b ldr r3, [r3, #32] + 8003f8c: 881b ldrh r3, [r3, #0] + 8003f8e: 2b00 cmp r3, #0 + 8003f90: bf0c ite eq + 8003f92: 2301 moveq r3, #1 + 8003f94: 2300 movne r3, #0 + 8003f96: b2db uxtb r3, r3 + 8003f98: e08f b.n 80040ba + } + else if (PB_HTYPE(type) == PB_HTYPE_OPTIONAL && field->pSize != NULL) + 8003f9a: f897 303d ldrb.w r3, [r7, #61] ; 0x3d + 8003f9e: f003 0330 and.w r3, r3, #48 ; 0x30 + 8003fa2: 2b10 cmp r3, #16 + 8003fa4: d115 bne.n 8003fd2 + 8003fa6: 687b ldr r3, [r7, #4] + 8003fa8: 6a1b ldr r3, [r3, #32] + 8003faa: 2b00 cmp r3, #0 + 8003fac: d011 beq.n 8003fd2 + { + /* Proto2 optional fields inside proto3 message, or proto3 + * submessage fields. */ + return safe_read_bool(field->pSize) == false; + 8003fae: 687b ldr r3, [r7, #4] + 8003fb0: 6a1b ldr r3, [r3, #32] + 8003fb2: 4618 mov r0, r3 + 8003fb4: f7ff fe4a bl 8003c4c + 8003fb8: 4603 mov r3, r0 + 8003fba: 2b00 cmp r3, #0 + 8003fbc: bf14 ite ne + 8003fbe: 2301 movne r3, #1 + 8003fc0: 2300 moveq r3, #0 + 8003fc2: b2db uxtb r3, r3 + 8003fc4: f083 0301 eor.w r3, r3, #1 + 8003fc8: b2db uxtb r3, r3 + 8003fca: f003 0301 and.w r3, r3, #1 + 8003fce: b2db uxtb r3, r3 + 8003fd0: e073 b.n 80040ba + } + + /* Rest is proto3 singular fields */ + if (PB_LTYPE(type) == PB_LTYPE_BYTES) + 8003fd2: f897 303d ldrb.w r3, [r7, #61] ; 0x3d + 8003fd6: f003 030f and.w r3, r3, #15 + 8003fda: 2b06 cmp r3, #6 + 8003fdc: d10a bne.n 8003ff4 + { + const pb_bytes_array_t *bytes = (const pb_bytes_array_t*)field->pData; + 8003fde: 687b ldr r3, [r7, #4] + 8003fe0: 69db ldr r3, [r3, #28] + 8003fe2: 63bb str r3, [r7, #56] ; 0x38 + return bytes->size == 0; + 8003fe4: 6bbb ldr r3, [r7, #56] ; 0x38 + 8003fe6: 881b ldrh r3, [r3, #0] + 8003fe8: 2b00 cmp r3, #0 + 8003fea: bf0c ite eq + 8003fec: 2301 moveq r3, #1 + 8003fee: 2300 movne r3, #0 + 8003ff0: b2db uxtb r3, r3 + 8003ff2: e062 b.n 80040ba + } + else if (PB_LTYPE(type) == PB_LTYPE_STRING) + 8003ff4: f897 303d ldrb.w r3, [r7, #61] ; 0x3d + 8003ff8: f003 030f and.w r3, r3, #15 + 8003ffc: 2b07 cmp r3, #7 + 8003ffe: d108 bne.n 8004012 + { + return *(const char*)field->pData == '\0'; + 8004000: 687b ldr r3, [r7, #4] + 8004002: 69db ldr r3, [r3, #28] + 8004004: 781b ldrb r3, [r3, #0] + 8004006: 2b00 cmp r3, #0 + 8004008: bf0c ite eq + 800400a: 2301 moveq r3, #1 + 800400c: 2300 movne r3, #0 + 800400e: b2db uxtb r3, r3 + 8004010: e053 b.n 80040ba + } + else if (PB_LTYPE(type) == PB_LTYPE_FIXED_LENGTH_BYTES) + 8004012: f897 303d ldrb.w r3, [r7, #61] ; 0x3d + 8004016: f003 030f and.w r3, r3, #15 + 800401a: 2b0b cmp r3, #11 + 800401c: d107 bne.n 800402e + { + /* Fixed length bytes is only empty if its length is fixed + * as 0. Which would be pretty strange, but we can check + * it anyway. */ + return field->data_size == 0; + 800401e: 687b ldr r3, [r7, #4] + 8004020: 8a5b ldrh r3, [r3, #18] + 8004022: 2b00 cmp r3, #0 + 8004024: bf0c ite eq + 8004026: 2301 moveq r3, #1 + 8004028: 2300 movne r3, #0 + 800402a: b2db uxtb r3, r3 + 800402c: e045 b.n 80040ba + } + else if (PB_LTYPE_IS_SUBMSG(type)) + 800402e: f897 303d ldrb.w r3, [r7, #61] ; 0x3d + 8004032: f003 030f and.w r3, r3, #15 + 8004036: 2b08 cmp r3, #8 + 8004038: d005 beq.n 8004046 + 800403a: f897 303d ldrb.w r3, [r7, #61] ; 0x3d + 800403e: f003 030f and.w r3, r3, #15 + 8004042: 2b09 cmp r3, #9 + 8004044: d122 bne.n 800408c + * because the C struct may contain padding bytes that must + * be skipped. Note that usually proto3 submessages have + * a separate has_field that is checked earlier in this if. + */ + pb_field_iter_t iter; + if (pb_field_iter_begin(&iter, field->submsg_desc, field->pData)) + 8004046: 687b ldr r3, [r7, #4] + 8004048: 6a59 ldr r1, [r3, #36] ; 0x24 + 800404a: 687b ldr r3, [r7, #4] + 800404c: 69da ldr r2, [r3, #28] + 800404e: f107 030c add.w r3, r7, #12 + 8004052: 4618 mov r0, r3 + 8004054: f7fd fe29 bl 8001caa + 8004058: 4603 mov r3, r0 + 800405a: 2b00 cmp r3, #0 + 800405c: d014 beq.n 8004088 + { + do + { + if (!pb_check_proto3_default_value(&iter)) + 800405e: f107 030c add.w r3, r7, #12 + 8004062: 4618 mov r0, r3 + 8004064: f7ff ff64 bl 8003f30 + 8004068: 4603 mov r3, r0 + 800406a: f083 0301 eor.w r3, r3, #1 + 800406e: b2db uxtb r3, r3 + 8004070: 2b00 cmp r3, #0 + 8004072: d001 beq.n 8004078 + { + return false; + 8004074: 2300 movs r3, #0 + 8004076: e020 b.n 80040ba + } + } while (pb_field_iter_next(&iter)); + 8004078: f107 030c add.w r3, r7, #12 + 800407c: 4618 mov r0, r3 + 800407e: f7fd fe5e bl 8001d3e + 8004082: 4603 mov r3, r0 + 8004084: 2b00 cmp r3, #0 + 8004086: d1ea bne.n 800405e + } + return true; + 8004088: 2301 movs r3, #1 + 800408a: e016 b.n 80040ba + * UVARINT, SVARINT, FIXED32, FIXED64, EXTENSION fields, and also + * callback fields. These all have integer or pointer value which + * can be compared with 0. + */ + pb_size_t i; + const char *p = (const char*)field->pData; + 800408c: 687b ldr r3, [r7, #4] + 800408e: 69db ldr r3, [r3, #28] + 8004090: 637b str r3, [r7, #52] ; 0x34 + for (i = 0; i < field->data_size; i++) + 8004092: 2300 movs r3, #0 + 8004094: 87fb strh r3, [r7, #62] ; 0x3e + 8004096: e00a b.n 80040ae + { + if (p[i] != 0) + 8004098: 8ffb ldrh r3, [r7, #62] ; 0x3e + 800409a: 6b7a ldr r2, [r7, #52] ; 0x34 + 800409c: 4413 add r3, r2 + 800409e: 781b ldrb r3, [r3, #0] + 80040a0: 2b00 cmp r3, #0 + 80040a2: d001 beq.n 80040a8 + { + return false; + 80040a4: 2300 movs r3, #0 + 80040a6: e008 b.n 80040ba + for (i = 0; i < field->data_size; i++) + 80040a8: 8ffb ldrh r3, [r7, #62] ; 0x3e + 80040aa: 3301 adds r3, #1 + 80040ac: 87fb strh r3, [r7, #62] ; 0x3e + 80040ae: 687b ldr r3, [r7, #4] + 80040b0: 8a5b ldrh r3, [r3, #18] + 80040b2: 8ffa ldrh r2, [r7, #62] ; 0x3e + 80040b4: 429a cmp r2, r3 + 80040b6: d3ef bcc.n 8004098 + } + } + + return true; + 80040b8: 2301 movs r3, #1 + } +} + 80040ba: 4618 mov r0, r3 + 80040bc: 3740 adds r7, #64 ; 0x40 + 80040be: 46bd mov sp, r7 + 80040c0: bd80 pop {r7, pc} + ... + +080040c4 : + +/* Encode a field with static or pointer allocation, i.e. one whose data + * is available to the encoder directly. */ +static bool checkreturn encode_basic_field(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + 80040c4: b580 push {r7, lr} + 80040c6: b082 sub sp, #8 + 80040c8: af00 add r7, sp, #0 + 80040ca: 6078 str r0, [r7, #4] + 80040cc: 6039 str r1, [r7, #0] + if (!field->pData) + 80040ce: 683b ldr r3, [r7, #0] + 80040d0: 69db ldr r3, [r3, #28] + 80040d2: 2b00 cmp r3, #0 + 80040d4: d101 bne.n 80040da + { + /* Missing pointer field */ + return true; + 80040d6: 2301 movs r3, #1 + 80040d8: e061 b.n 800419e + } + + if (!pb_encode_tag_for_field(stream, field)) + 80040da: 6839 ldr r1, [r7, #0] + 80040dc: 6878 ldr r0, [r7, #4] + 80040de: f000 fb11 bl 8004704 + 80040e2: 4603 mov r3, r0 + 80040e4: f083 0301 eor.w r3, r3, #1 + 80040e8: b2db uxtb r3, r3 + 80040ea: 2b00 cmp r3, #0 + 80040ec: d001 beq.n 80040f2 + return false; + 80040ee: 2300 movs r3, #0 + 80040f0: e055 b.n 800419e + + switch (PB_LTYPE(field->type)) + 80040f2: 683b ldr r3, [r7, #0] + 80040f4: 7d9b ldrb r3, [r3, #22] + 80040f6: f003 030f and.w r3, r3, #15 + 80040fa: 2b0b cmp r3, #11 + 80040fc: d844 bhi.n 8004188 + 80040fe: a201 add r2, pc, #4 ; (adr r2, 8004104 ) + 8004100: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8004104: 08004135 .word 0x08004135 + 8004108: 08004141 .word 0x08004141 + 800410c: 08004141 .word 0x08004141 + 8004110: 08004141 .word 0x08004141 + 8004114: 0800414d .word 0x0800414d + 8004118: 0800414d .word 0x0800414d + 800411c: 08004159 .word 0x08004159 + 8004120: 08004165 .word 0x08004165 + 8004124: 08004171 .word 0x08004171 + 8004128: 08004171 .word 0x08004171 + 800412c: 08004189 .word 0x08004189 + 8004130: 0800417d .word 0x0800417d + { + case PB_LTYPE_BOOL: + return pb_enc_bool(stream, field); + 8004134: 6839 ldr r1, [r7, #0] + 8004136: 6878 ldr r0, [r7, #4] + 8004138: f000 fbe0 bl 80048fc + 800413c: 4603 mov r3, r0 + 800413e: e02e b.n 800419e + + case PB_LTYPE_VARINT: + case PB_LTYPE_UVARINT: + case PB_LTYPE_SVARINT: + return pb_enc_varint(stream, field); + 8004140: 6839 ldr r1, [r7, #0] + 8004142: 6878 ldr r0, [r7, #4] + 8004144: f000 fbf4 bl 8004930 + 8004148: 4603 mov r3, r0 + 800414a: e028 b.n 800419e + + case PB_LTYPE_FIXED32: + case PB_LTYPE_FIXED64: + return pb_enc_fixed(stream, field); + 800414c: 6839 ldr r1, [r7, #0] + 800414e: 6878 ldr r0, [r7, #4] + 8004150: f000 fca4 bl 8004a9c + 8004154: 4603 mov r3, r0 + 8004156: e022 b.n 800419e + + case PB_LTYPE_BYTES: + return pb_enc_bytes(stream, field); + 8004158: 6839 ldr r1, [r7, #0] + 800415a: 6878 ldr r0, [r7, #4] + 800415c: f000 fccc bl 8004af8 + 8004160: 4603 mov r3, r0 + 8004162: e01c b.n 800419e + + case PB_LTYPE_STRING: + return pb_enc_string(stream, field); + 8004164: 6839 ldr r1, [r7, #0] + 8004166: 6878 ldr r0, [r7, #4] + 8004168: f000 fd02 bl 8004b70 + 800416c: 4603 mov r3, r0 + 800416e: e016 b.n 800419e + + case PB_LTYPE_SUBMESSAGE: + case PB_LTYPE_SUBMSG_W_CB: + return pb_enc_submessage(stream, field); + 8004170: 6839 ldr r1, [r7, #0] + 8004172: 6878 ldr r0, [r7, #4] + 8004174: f000 fd5a bl 8004c2c + 8004178: 4603 mov r3, r0 + 800417a: e010 b.n 800419e + + case PB_LTYPE_FIXED_LENGTH_BYTES: + return pb_enc_fixed_length_bytes(stream, field); + 800417c: 6839 ldr r1, [r7, #0] + 800417e: 6878 ldr r0, [r7, #4] + 8004180: f000 fd9a bl 8004cb8 + 8004184: 4603 mov r3, r0 + 8004186: e00a b.n 800419e + + default: + PB_RETURN_ERROR(stream, "invalid field type"); + 8004188: 687b ldr r3, [r7, #4] + 800418a: 691b ldr r3, [r3, #16] + 800418c: 2b00 cmp r3, #0 + 800418e: d002 beq.n 8004196 + 8004190: 687b ldr r3, [r7, #4] + 8004192: 691b ldr r3, [r3, #16] + 8004194: e000 b.n 8004198 + 8004196: 4b04 ldr r3, [pc, #16] ; (80041a8 ) + 8004198: 687a ldr r2, [r7, #4] + 800419a: 6113 str r3, [r2, #16] + 800419c: 2300 movs r3, #0 + } +} + 800419e: 4618 mov r0, r3 + 80041a0: 3708 adds r7, #8 + 80041a2: 46bd mov sp, r7 + 80041a4: bd80 pop {r7, pc} + 80041a6: bf00 nop + 80041a8: 08008bd8 .word 0x08008bd8 + +080041ac : + +/* Encode a field with callback semantics. This means that a user function is + * called to provide and encode the actual data. */ +static bool checkreturn encode_callback_field(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + 80041ac: b580 push {r7, lr} + 80041ae: b082 sub sp, #8 + 80041b0: af00 add r7, sp, #0 + 80041b2: 6078 str r0, [r7, #4] + 80041b4: 6039 str r1, [r7, #0] + if (field->descriptor->field_callback != NULL) + 80041b6: 683b ldr r3, [r7, #0] + 80041b8: 681b ldr r3, [r3, #0] + 80041ba: f8d3 300e ldr.w r3, [r3, #14] + 80041be: 2b00 cmp r3, #0 + 80041c0: d019 beq.n 80041f6 + { + if (!field->descriptor->field_callback(NULL, stream, field)) + 80041c2: 683b ldr r3, [r7, #0] + 80041c4: 681b ldr r3, [r3, #0] + 80041c6: f8d3 300e ldr.w r3, [r3, #14] + 80041ca: 683a ldr r2, [r7, #0] + 80041cc: 6879 ldr r1, [r7, #4] + 80041ce: 2000 movs r0, #0 + 80041d0: 4798 blx r3 + 80041d2: 4603 mov r3, r0 + 80041d4: f083 0301 eor.w r3, r3, #1 + 80041d8: b2db uxtb r3, r3 + 80041da: 2b00 cmp r3, #0 + 80041dc: d00b beq.n 80041f6 + PB_RETURN_ERROR(stream, "callback error"); + 80041de: 687b ldr r3, [r7, #4] + 80041e0: 691b ldr r3, [r3, #16] + 80041e2: 2b00 cmp r3, #0 + 80041e4: d002 beq.n 80041ec + 80041e6: 687b ldr r3, [r7, #4] + 80041e8: 691b ldr r3, [r3, #16] + 80041ea: e000 b.n 80041ee + 80041ec: 4b04 ldr r3, [pc, #16] ; (8004200 ) + 80041ee: 687a ldr r2, [r7, #4] + 80041f0: 6113 str r3, [r2, #16] + 80041f2: 2300 movs r3, #0 + 80041f4: e000 b.n 80041f8 + } + return true; + 80041f6: 2301 movs r3, #1 +} + 80041f8: 4618 mov r0, r3 + 80041fa: 3708 adds r7, #8 + 80041fc: 46bd mov sp, r7 + 80041fe: bd80 pop {r7, pc} + 8004200: 08008bec .word 0x08008bec + +08004204 : + +/* Encode a single field of any callback, pointer or static type. */ +static bool checkreturn encode_field(pb_ostream_t *stream, pb_field_iter_t *field) +{ + 8004204: b580 push {r7, lr} + 8004206: b082 sub sp, #8 + 8004208: af00 add r7, sp, #0 + 800420a: 6078 str r0, [r7, #4] + 800420c: 6039 str r1, [r7, #0] + /* Check field presence */ + if (PB_HTYPE(field->type) == PB_HTYPE_ONEOF) + 800420e: 683b ldr r3, [r7, #0] + 8004210: 7d9b ldrb r3, [r3, #22] + 8004212: f003 0330 and.w r3, r3, #48 ; 0x30 + 8004216: 2b30 cmp r3, #48 ; 0x30 + 8004218: d108 bne.n 800422c + { + if (*(const pb_size_t*)field->pSize != field->tag) + 800421a: 683b ldr r3, [r7, #0] + 800421c: 6a1b ldr r3, [r3, #32] + 800421e: 881a ldrh r2, [r3, #0] + 8004220: 683b ldr r3, [r7, #0] + 8004222: 8a1b ldrh r3, [r3, #16] + 8004224: 429a cmp r2, r3 + 8004226: d026 beq.n 8004276 + { + /* Different type oneof field */ + return true; + 8004228: 2301 movs r3, #1 + 800422a: e059 b.n 80042e0 + } + } + else if (PB_HTYPE(field->type) == PB_HTYPE_OPTIONAL) + 800422c: 683b ldr r3, [r7, #0] + 800422e: 7d9b ldrb r3, [r3, #22] + 8004230: f003 0330 and.w r3, r3, #48 ; 0x30 + 8004234: 2b10 cmp r3, #16 + 8004236: d11e bne.n 8004276 + { + if (field->pSize) + 8004238: 683b ldr r3, [r7, #0] + 800423a: 6a1b ldr r3, [r3, #32] + 800423c: 2b00 cmp r3, #0 + 800423e: d00c beq.n 800425a + { + if (safe_read_bool(field->pSize) == false) + 8004240: 683b ldr r3, [r7, #0] + 8004242: 6a1b ldr r3, [r3, #32] + 8004244: 4618 mov r0, r3 + 8004246: f7ff fd01 bl 8003c4c + 800424a: 4603 mov r3, r0 + 800424c: f083 0301 eor.w r3, r3, #1 + 8004250: b2db uxtb r3, r3 + 8004252: 2b00 cmp r3, #0 + 8004254: d00f beq.n 8004276 + { + /* Missing optional field */ + return true; + 8004256: 2301 movs r3, #1 + 8004258: e042 b.n 80042e0 + } + } + else if (PB_ATYPE(field->type) == PB_ATYPE_STATIC) + 800425a: 683b ldr r3, [r7, #0] + 800425c: 7d9b ldrb r3, [r3, #22] + 800425e: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 8004262: 2b00 cmp r3, #0 + 8004264: d107 bne.n 8004276 + { + /* Proto3 singular field */ + if (pb_check_proto3_default_value(field)) + 8004266: 6838 ldr r0, [r7, #0] + 8004268: f7ff fe62 bl 8003f30 + 800426c: 4603 mov r3, r0 + 800426e: 2b00 cmp r3, #0 + 8004270: d001 beq.n 8004276 + return true; + 8004272: 2301 movs r3, #1 + 8004274: e034 b.n 80042e0 + } + } + + if (!field->pData) + 8004276: 683b ldr r3, [r7, #0] + 8004278: 69db ldr r3, [r3, #28] + 800427a: 2b00 cmp r3, #0 + 800427c: d113 bne.n 80042a6 + { + if (PB_HTYPE(field->type) == PB_HTYPE_REQUIRED) + 800427e: 683b ldr r3, [r7, #0] + 8004280: 7d9b ldrb r3, [r3, #22] + 8004282: f003 0330 and.w r3, r3, #48 ; 0x30 + 8004286: 2b00 cmp r3, #0 + 8004288: d10b bne.n 80042a2 + PB_RETURN_ERROR(stream, "missing required field"); + 800428a: 687b ldr r3, [r7, #4] + 800428c: 691b ldr r3, [r3, #16] + 800428e: 2b00 cmp r3, #0 + 8004290: d002 beq.n 8004298 + 8004292: 687b ldr r3, [r7, #4] + 8004294: 691b ldr r3, [r3, #16] + 8004296: e000 b.n 800429a + 8004298: 4b13 ldr r3, [pc, #76] ; (80042e8 ) + 800429a: 687a ldr r2, [r7, #4] + 800429c: 6113 str r3, [r2, #16] + 800429e: 2300 movs r3, #0 + 80042a0: e01e b.n 80042e0 + + /* Pointer field set to NULL */ + return true; + 80042a2: 2301 movs r3, #1 + 80042a4: e01c b.n 80042e0 + } + + /* Then encode field contents */ + if (PB_ATYPE(field->type) == PB_ATYPE_CALLBACK) + 80042a6: 683b ldr r3, [r7, #0] + 80042a8: 7d9b ldrb r3, [r3, #22] + 80042aa: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 80042ae: 2b40 cmp r3, #64 ; 0x40 + 80042b0: d105 bne.n 80042be + { + return encode_callback_field(stream, field); + 80042b2: 6839 ldr r1, [r7, #0] + 80042b4: 6878 ldr r0, [r7, #4] + 80042b6: f7ff ff79 bl 80041ac + 80042ba: 4603 mov r3, r0 + 80042bc: e010 b.n 80042e0 + } + else if (PB_HTYPE(field->type) == PB_HTYPE_REPEATED) + 80042be: 683b ldr r3, [r7, #0] + 80042c0: 7d9b ldrb r3, [r3, #22] + 80042c2: f003 0330 and.w r3, r3, #48 ; 0x30 + 80042c6: 2b20 cmp r3, #32 + 80042c8: d105 bne.n 80042d6 + { + return encode_array(stream, field); + 80042ca: 6839 ldr r1, [r7, #0] + 80042cc: 6878 ldr r0, [r7, #4] + 80042ce: f7ff fcdb bl 8003c88 + 80042d2: 4603 mov r3, r0 + 80042d4: e004 b.n 80042e0 + } + else + { + return encode_basic_field(stream, field); + 80042d6: 6839 ldr r1, [r7, #0] + 80042d8: 6878 ldr r0, [r7, #4] + 80042da: f7ff fef3 bl 80040c4 + 80042de: 4603 mov r3, r0 + } +} + 80042e0: 4618 mov r0, r3 + 80042e2: 3708 adds r7, #8 + 80042e4: 46bd mov sp, r7 + 80042e6: bd80 pop {r7, pc} + 80042e8: 08008bfc .word 0x08008bfc + +080042ec : + +/* Default handler for extension fields. Expects to have a pb_msgdesc_t + * pointer in the extension->type->arg field, pointing to a message with + * only one field in it. */ +static bool checkreturn default_extension_encoder(pb_ostream_t *stream, const pb_extension_t *extension) +{ + 80042ec: b580 push {r7, lr} + 80042ee: b08c sub sp, #48 ; 0x30 + 80042f0: af00 add r7, sp, #0 + 80042f2: 6078 str r0, [r7, #4] + 80042f4: 6039 str r1, [r7, #0] + pb_field_iter_t iter; + + if (!pb_field_iter_begin_extension_const(&iter, extension)) + 80042f6: f107 0308 add.w r3, r7, #8 + 80042fa: 6839 ldr r1, [r7, #0] + 80042fc: 4618 mov r0, r3 + 80042fe: f7fd fd97 bl 8001e30 + 8004302: 4603 mov r3, r0 + 8004304: f083 0301 eor.w r3, r3, #1 + 8004308: b2db uxtb r3, r3 + 800430a: 2b00 cmp r3, #0 + 800430c: d00b beq.n 8004326 + PB_RETURN_ERROR(stream, "invalid extension"); + 800430e: 687b ldr r3, [r7, #4] + 8004310: 691b ldr r3, [r3, #16] + 8004312: 2b00 cmp r3, #0 + 8004314: d002 beq.n 800431c + 8004316: 687b ldr r3, [r7, #4] + 8004318: 691b ldr r3, [r3, #16] + 800431a: e000 b.n 800431e + 800431c: 4b07 ldr r3, [pc, #28] ; (800433c ) + 800431e: 687a ldr r2, [r7, #4] + 8004320: 6113 str r3, [r2, #16] + 8004322: 2300 movs r3, #0 + 8004324: e006 b.n 8004334 + + return encode_field(stream, &iter); + 8004326: f107 0308 add.w r3, r7, #8 + 800432a: 4619 mov r1, r3 + 800432c: 6878 ldr r0, [r7, #4] + 800432e: f7ff ff69 bl 8004204 + 8004332: 4603 mov r3, r0 +} + 8004334: 4618 mov r0, r3 + 8004336: 3730 adds r7, #48 ; 0x30 + 8004338: 46bd mov sp, r7 + 800433a: bd80 pop {r7, pc} + 800433c: 08008c14 .word 0x08008c14 + +08004340 : + + +/* Walk through all the registered extensions and give them a chance + * to encode themselves. */ +static bool checkreturn encode_extension_field(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + 8004340: b580 push {r7, lr} + 8004342: b084 sub sp, #16 + 8004344: af00 add r7, sp, #0 + 8004346: 6078 str r0, [r7, #4] + 8004348: 6039 str r1, [r7, #0] + const pb_extension_t *extension = *(const pb_extension_t* const *)field->pData; + 800434a: 683b ldr r3, [r7, #0] + 800434c: 69db ldr r3, [r3, #28] + 800434e: 681b ldr r3, [r3, #0] + 8004350: 60fb str r3, [r7, #12] + + while (extension) + 8004352: e01e b.n 8004392 + { + bool status; + if (extension->type->encode) + 8004354: 68fb ldr r3, [r7, #12] + 8004356: 681b ldr r3, [r3, #0] + 8004358: 685b ldr r3, [r3, #4] + 800435a: 2b00 cmp r3, #0 + 800435c: d008 beq.n 8004370 + status = extension->type->encode(stream, extension); + 800435e: 68fb ldr r3, [r7, #12] + 8004360: 681b ldr r3, [r3, #0] + 8004362: 685b ldr r3, [r3, #4] + 8004364: 68f9 ldr r1, [r7, #12] + 8004366: 6878 ldr r0, [r7, #4] + 8004368: 4798 blx r3 + 800436a: 4603 mov r3, r0 + 800436c: 72fb strb r3, [r7, #11] + 800436e: e005 b.n 800437c + else + status = default_extension_encoder(stream, extension); + 8004370: 68f9 ldr r1, [r7, #12] + 8004372: 6878 ldr r0, [r7, #4] + 8004374: f7ff ffba bl 80042ec + 8004378: 4603 mov r3, r0 + 800437a: 72fb strb r3, [r7, #11] + + if (!status) + 800437c: 7afb ldrb r3, [r7, #11] + 800437e: f083 0301 eor.w r3, r3, #1 + 8004382: b2db uxtb r3, r3 + 8004384: 2b00 cmp r3, #0 + 8004386: d001 beq.n 800438c + return false; + 8004388: 2300 movs r3, #0 + 800438a: e006 b.n 800439a + + extension = extension->next; + 800438c: 68fb ldr r3, [r7, #12] + 800438e: 689b ldr r3, [r3, #8] + 8004390: 60fb str r3, [r7, #12] + while (extension) + 8004392: 68fb ldr r3, [r7, #12] + 8004394: 2b00 cmp r3, #0 + 8004396: d1dd bne.n 8004354 + } + + return true; + 8004398: 2301 movs r3, #1 +} + 800439a: 4618 mov r0, r3 + 800439c: 3710 adds r7, #16 + 800439e: 46bd mov sp, r7 + 80043a0: bd80 pop {r7, pc} + +080043a2 : +/********************* + * Encode all fields * + *********************/ + +bool checkreturn pb_encode(pb_ostream_t *stream, const pb_msgdesc_t *fields, const void *src_struct) +{ + 80043a2: b580 push {r7, lr} + 80043a4: b08e sub sp, #56 ; 0x38 + 80043a6: af00 add r7, sp, #0 + 80043a8: 60f8 str r0, [r7, #12] + 80043aa: 60b9 str r1, [r7, #8] + 80043ac: 607a str r2, [r7, #4] + pb_field_iter_t iter; + if (!pb_field_iter_begin_const(&iter, fields, src_struct)) + 80043ae: f107 0310 add.w r3, r7, #16 + 80043b2: 687a ldr r2, [r7, #4] + 80043b4: 68b9 ldr r1, [r7, #8] + 80043b6: 4618 mov r0, r3 + 80043b8: f7fd fd26 bl 8001e08 + 80043bc: 4603 mov r3, r0 + 80043be: f083 0301 eor.w r3, r3, #1 + 80043c2: b2db uxtb r3, r3 + 80043c4: 2b00 cmp r3, #0 + 80043c6: d001 beq.n 80043cc + return true; /* Empty message type */ + 80043c8: 2301 movs r3, #1 + 80043ca: e02a b.n 8004422 + + do { + if (PB_LTYPE(iter.type) == PB_LTYPE_EXTENSION) + 80043cc: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 80043d0: f003 030f and.w r3, r3, #15 + 80043d4: 2b0a cmp r3, #10 + 80043d6: d10d bne.n 80043f4 + { + /* Special case for the extension field placeholder */ + if (!encode_extension_field(stream, &iter)) + 80043d8: f107 0310 add.w r3, r7, #16 + 80043dc: 4619 mov r1, r3 + 80043de: 68f8 ldr r0, [r7, #12] + 80043e0: f7ff ffae bl 8004340 + 80043e4: 4603 mov r3, r0 + 80043e6: f083 0301 eor.w r3, r3, #1 + 80043ea: b2db uxtb r3, r3 + 80043ec: 2b00 cmp r3, #0 + 80043ee: d00f beq.n 8004410 + return false; + 80043f0: 2300 movs r3, #0 + 80043f2: e016 b.n 8004422 + } + else + { + /* Regular field */ + if (!encode_field(stream, &iter)) + 80043f4: f107 0310 add.w r3, r7, #16 + 80043f8: 4619 mov r1, r3 + 80043fa: 68f8 ldr r0, [r7, #12] + 80043fc: f7ff ff02 bl 8004204 + 8004400: 4603 mov r3, r0 + 8004402: f083 0301 eor.w r3, r3, #1 + 8004406: b2db uxtb r3, r3 + 8004408: 2b00 cmp r3, #0 + 800440a: d001 beq.n 8004410 + return false; + 800440c: 2300 movs r3, #0 + 800440e: e008 b.n 8004422 + } + } while (pb_field_iter_next(&iter)); + 8004410: f107 0310 add.w r3, r7, #16 + 8004414: 4618 mov r0, r3 + 8004416: f7fd fc92 bl 8001d3e + 800441a: 4603 mov r3, r0 + 800441c: 2b00 cmp r3, #0 + 800441e: d1d5 bne.n 80043cc + + return true; + 8004420: 2301 movs r3, #1 +} + 8004422: 4618 mov r0, r3 + 8004424: 3738 adds r7, #56 ; 0x38 + 8004426: 46bd mov sp, r7 + 8004428: bd80 pop {r7, pc} + +0800442a : + * Helper functions * + ********************/ + +/* This function avoids 64-bit shifts as they are quite slow on many platforms. */ +static bool checkreturn pb_encode_varint_32(pb_ostream_t *stream, uint32_t low, uint32_t high) +{ + 800442a: b580 push {r7, lr} + 800442c: b088 sub sp, #32 + 800442e: af00 add r7, sp, #0 + 8004430: 60f8 str r0, [r7, #12] + 8004432: 60b9 str r1, [r7, #8] + 8004434: 607a str r2, [r7, #4] + size_t i = 0; + 8004436: 2300 movs r3, #0 + 8004438: 61fb str r3, [r7, #28] + pb_byte_t buffer[10]; + pb_byte_t byte = (pb_byte_t)(low & 0x7F); + 800443a: 68bb ldr r3, [r7, #8] + 800443c: b2db uxtb r3, r3 + 800443e: f003 037f and.w r3, r3, #127 ; 0x7f + 8004442: 76fb strb r3, [r7, #27] + low >>= 7; + 8004444: 68bb ldr r3, [r7, #8] + 8004446: 09db lsrs r3, r3, #7 + 8004448: 60bb str r3, [r7, #8] + + while (i < 4 && (low != 0 || high != 0)) + 800444a: e014 b.n 8004476 + { + byte |= 0x80; + 800444c: 7efb ldrb r3, [r7, #27] + 800444e: f063 037f orn r3, r3, #127 ; 0x7f + 8004452: 76fb strb r3, [r7, #27] + buffer[i++] = byte; + 8004454: 69fb ldr r3, [r7, #28] + 8004456: 1c5a adds r2, r3, #1 + 8004458: 61fa str r2, [r7, #28] + 800445a: f107 0220 add.w r2, r7, #32 + 800445e: 4413 add r3, r2 + 8004460: 7efa ldrb r2, [r7, #27] + 8004462: f803 2c10 strb.w r2, [r3, #-16] + byte = (pb_byte_t)(low & 0x7F); + 8004466: 68bb ldr r3, [r7, #8] + 8004468: b2db uxtb r3, r3 + 800446a: f003 037f and.w r3, r3, #127 ; 0x7f + 800446e: 76fb strb r3, [r7, #27] + low >>= 7; + 8004470: 68bb ldr r3, [r7, #8] + 8004472: 09db lsrs r3, r3, #7 + 8004474: 60bb str r3, [r7, #8] + while (i < 4 && (low != 0 || high != 0)) + 8004476: 69fb ldr r3, [r7, #28] + 8004478: 2b03 cmp r3, #3 + 800447a: d805 bhi.n 8004488 + 800447c: 68bb ldr r3, [r7, #8] + 800447e: 2b00 cmp r3, #0 + 8004480: d1e4 bne.n 800444c + 8004482: 687b ldr r3, [r7, #4] + 8004484: 2b00 cmp r3, #0 + 8004486: d1e1 bne.n 800444c + } + + if (high) + 8004488: 687b ldr r3, [r7, #4] + 800448a: 2b00 cmp r3, #0 + 800448c: d025 beq.n 80044da + { + byte = (pb_byte_t)(byte | ((high & 0x07) << 4)); + 800448e: 687b ldr r3, [r7, #4] + 8004490: b2db uxtb r3, r3 + 8004492: 011b lsls r3, r3, #4 + 8004494: b2db uxtb r3, r3 + 8004496: f003 0370 and.w r3, r3, #112 ; 0x70 + 800449a: b2da uxtb r2, r3 + 800449c: 7efb ldrb r3, [r7, #27] + 800449e: 4313 orrs r3, r2 + 80044a0: 76fb strb r3, [r7, #27] + high >>= 3; + 80044a2: 687b ldr r3, [r7, #4] + 80044a4: 08db lsrs r3, r3, #3 + 80044a6: 607b str r3, [r7, #4] + + while (high) + 80044a8: e014 b.n 80044d4 + { + byte |= 0x80; + 80044aa: 7efb ldrb r3, [r7, #27] + 80044ac: f063 037f orn r3, r3, #127 ; 0x7f + 80044b0: 76fb strb r3, [r7, #27] + buffer[i++] = byte; + 80044b2: 69fb ldr r3, [r7, #28] + 80044b4: 1c5a adds r2, r3, #1 + 80044b6: 61fa str r2, [r7, #28] + 80044b8: f107 0220 add.w r2, r7, #32 + 80044bc: 4413 add r3, r2 + 80044be: 7efa ldrb r2, [r7, #27] + 80044c0: f803 2c10 strb.w r2, [r3, #-16] + byte = (pb_byte_t)(high & 0x7F); + 80044c4: 687b ldr r3, [r7, #4] + 80044c6: b2db uxtb r3, r3 + 80044c8: f003 037f and.w r3, r3, #127 ; 0x7f + 80044cc: 76fb strb r3, [r7, #27] + high >>= 7; + 80044ce: 687b ldr r3, [r7, #4] + 80044d0: 09db lsrs r3, r3, #7 + 80044d2: 607b str r3, [r7, #4] + while (high) + 80044d4: 687b ldr r3, [r7, #4] + 80044d6: 2b00 cmp r3, #0 + 80044d8: d1e7 bne.n 80044aa + } + } + + buffer[i++] = byte; + 80044da: 69fb ldr r3, [r7, #28] + 80044dc: 1c5a adds r2, r3, #1 + 80044de: 61fa str r2, [r7, #28] + 80044e0: f107 0220 add.w r2, r7, #32 + 80044e4: 4413 add r3, r2 + 80044e6: 7efa ldrb r2, [r7, #27] + 80044e8: f803 2c10 strb.w r2, [r3, #-16] + + return pb_write(stream, buffer, i); + 80044ec: f107 0310 add.w r3, r7, #16 + 80044f0: 69fa ldr r2, [r7, #28] + 80044f2: 4619 mov r1, r3 + 80044f4: 68f8 ldr r0, [r7, #12] + 80044f6: f7ff fb61 bl 8003bbc + 80044fa: 4603 mov r3, r0 +} + 80044fc: 4618 mov r0, r3 + 80044fe: 3720 adds r7, #32 + 8004500: 46bd mov sp, r7 + 8004502: bd80 pop {r7, pc} + +08004504 : + +bool checkreturn pb_encode_varint(pb_ostream_t *stream, pb_uint64_t value) +{ + 8004504: b590 push {r4, r7, lr} + 8004506: b087 sub sp, #28 + 8004508: af00 add r7, sp, #0 + 800450a: 60f8 str r0, [r7, #12] + 800450c: e9c7 2300 strd r2, r3, [r7] + if (value <= 0x7F) + 8004510: e9d7 3400 ldrd r3, r4, [r7] + 8004514: 2c00 cmp r4, #0 + 8004516: bf08 it eq + 8004518: 2b80 cmpeq r3, #128 ; 0x80 + 800451a: d20a bcs.n 8004532 + { + /* Fast path: single byte */ + pb_byte_t byte = (pb_byte_t)value; + 800451c: 783b ldrb r3, [r7, #0] + 800451e: 75fb strb r3, [r7, #23] + return pb_write(stream, &byte, 1); + 8004520: f107 0317 add.w r3, r7, #23 + 8004524: 2201 movs r2, #1 + 8004526: 4619 mov r1, r3 + 8004528: 68f8 ldr r0, [r7, #12] + 800452a: f7ff fb47 bl 8003bbc + 800452e: 4603 mov r3, r0 + 8004530: e00e b.n 8004550 + else + { +#ifdef PB_WITHOUT_64BIT + return pb_encode_varint_32(stream, value, 0); +#else + return pb_encode_varint_32(stream, (uint32_t)value, (uint32_t)(value >> 32)); + 8004532: 6838 ldr r0, [r7, #0] + 8004534: e9d7 1200 ldrd r1, r2, [r7] + 8004538: f04f 0300 mov.w r3, #0 + 800453c: f04f 0400 mov.w r4, #0 + 8004540: 0013 movs r3, r2 + 8004542: 2400 movs r4, #0 + 8004544: 461a mov r2, r3 + 8004546: 4601 mov r1, r0 + 8004548: 68f8 ldr r0, [r7, #12] + 800454a: f7ff ff6e bl 800442a + 800454e: 4603 mov r3, r0 +#endif + } +} + 8004550: 4618 mov r0, r3 + 8004552: 371c adds r7, #28 + 8004554: 46bd mov sp, r7 + 8004556: bd90 pop {r4, r7, pc} + +08004558 : + +bool checkreturn pb_encode_svarint(pb_ostream_t *stream, pb_int64_t value) +{ + 8004558: b590 push {r4, r7, lr} + 800455a: b087 sub sp, #28 + 800455c: af00 add r7, sp, #0 + 800455e: 60f8 str r0, [r7, #12] + 8004560: e9c7 2300 strd r2, r3, [r7] + pb_uint64_t zigzagged; + if (value < 0) + 8004564: e9d7 3400 ldrd r3, r4, [r7] + 8004568: 2b00 cmp r3, #0 + 800456a: f174 0300 sbcs.w r3, r4, #0 + 800456e: da0d bge.n 800458c + zigzagged = ~((pb_uint64_t)value << 1); + 8004570: e9d7 1200 ldrd r1, r2, [r7] + 8004574: 184b adds r3, r1, r1 + 8004576: eb42 0402 adc.w r4, r2, r2 + 800457a: 4619 mov r1, r3 + 800457c: 4622 mov r2, r4 + 800457e: ea6f 0301 mvn.w r3, r1 + 8004582: ea6f 0402 mvn.w r4, r2 + 8004586: e9c7 3404 strd r3, r4, [r7, #16] + 800458a: e006 b.n 800459a + else + zigzagged = (pb_uint64_t)value << 1; + 800458c: e9d7 1200 ldrd r1, r2, [r7] + 8004590: 184b adds r3, r1, r1 + 8004592: eb42 0402 adc.w r4, r2, r2 + 8004596: e9c7 3404 strd r3, r4, [r7, #16] + + return pb_encode_varint(stream, zigzagged); + 800459a: e9d7 2304 ldrd r2, r3, [r7, #16] + 800459e: 68f8 ldr r0, [r7, #12] + 80045a0: f7ff ffb0 bl 8004504 + 80045a4: 4603 mov r3, r0 +} + 80045a6: 4618 mov r0, r3 + 80045a8: 371c adds r7, #28 + 80045aa: 46bd mov sp, r7 + 80045ac: bd90 pop {r4, r7, pc} + +080045ae : + +bool checkreturn pb_encode_fixed32(pb_ostream_t *stream, const void *value) +{ + 80045ae: b580 push {r7, lr} + 80045b0: b084 sub sp, #16 + 80045b2: af00 add r7, sp, #0 + 80045b4: 6078 str r0, [r7, #4] + 80045b6: 6039 str r1, [r7, #0] + uint32_t val = *(const uint32_t*)value; + 80045b8: 683b ldr r3, [r7, #0] + 80045ba: 681b ldr r3, [r3, #0] + 80045bc: 60fb str r3, [r7, #12] + pb_byte_t bytes[4]; + bytes[0] = (pb_byte_t)(val & 0xFF); + 80045be: 68fb ldr r3, [r7, #12] + 80045c0: b2db uxtb r3, r3 + 80045c2: 723b strb r3, [r7, #8] + bytes[1] = (pb_byte_t)((val >> 8) & 0xFF); + 80045c4: 68fb ldr r3, [r7, #12] + 80045c6: 0a1b lsrs r3, r3, #8 + 80045c8: b2db uxtb r3, r3 + 80045ca: 727b strb r3, [r7, #9] + bytes[2] = (pb_byte_t)((val >> 16) & 0xFF); + 80045cc: 68fb ldr r3, [r7, #12] + 80045ce: 0c1b lsrs r3, r3, #16 + 80045d0: b2db uxtb r3, r3 + 80045d2: 72bb strb r3, [r7, #10] + bytes[3] = (pb_byte_t)((val >> 24) & 0xFF); + 80045d4: 68fb ldr r3, [r7, #12] + 80045d6: 0e1b lsrs r3, r3, #24 + 80045d8: b2db uxtb r3, r3 + 80045da: 72fb strb r3, [r7, #11] + return pb_write(stream, bytes, 4); + 80045dc: f107 0308 add.w r3, r7, #8 + 80045e0: 2204 movs r2, #4 + 80045e2: 4619 mov r1, r3 + 80045e4: 6878 ldr r0, [r7, #4] + 80045e6: f7ff fae9 bl 8003bbc + 80045ea: 4603 mov r3, r0 +} + 80045ec: 4618 mov r0, r3 + 80045ee: 3710 adds r7, #16 + 80045f0: 46bd mov sp, r7 + 80045f2: bd80 pop {r7, pc} + +080045f4 : + +#ifndef PB_WITHOUT_64BIT +bool checkreturn pb_encode_fixed64(pb_ostream_t *stream, const void *value) +{ + 80045f4: b590 push {r4, r7, lr} + 80045f6: b087 sub sp, #28 + 80045f8: af00 add r7, sp, #0 + 80045fa: 6078 str r0, [r7, #4] + 80045fc: 6039 str r1, [r7, #0] + uint64_t val = *(const uint64_t*)value; + 80045fe: 683b ldr r3, [r7, #0] + 8004600: e9d3 3400 ldrd r3, r4, [r3] + 8004604: e9c7 3404 strd r3, r4, [r7, #16] + pb_byte_t bytes[8]; + bytes[0] = (pb_byte_t)(val & 0xFF); + 8004608: 7c3b ldrb r3, [r7, #16] + 800460a: 723b strb r3, [r7, #8] + bytes[1] = (pb_byte_t)((val >> 8) & 0xFF); + 800460c: e9d7 1204 ldrd r1, r2, [r7, #16] + 8004610: f04f 0300 mov.w r3, #0 + 8004614: f04f 0400 mov.w r4, #0 + 8004618: 0a0b lsrs r3, r1, #8 + 800461a: ea43 6302 orr.w r3, r3, r2, lsl #24 + 800461e: 0a14 lsrs r4, r2, #8 + 8004620: b2db uxtb r3, r3 + 8004622: 727b strb r3, [r7, #9] + bytes[2] = (pb_byte_t)((val >> 16) & 0xFF); + 8004624: e9d7 1204 ldrd r1, r2, [r7, #16] + 8004628: f04f 0300 mov.w r3, #0 + 800462c: f04f 0400 mov.w r4, #0 + 8004630: 0c0b lsrs r3, r1, #16 + 8004632: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8004636: 0c14 lsrs r4, r2, #16 + 8004638: b2db uxtb r3, r3 + 800463a: 72bb strb r3, [r7, #10] + bytes[3] = (pb_byte_t)((val >> 24) & 0xFF); + 800463c: e9d7 1204 ldrd r1, r2, [r7, #16] + 8004640: f04f 0300 mov.w r3, #0 + 8004644: f04f 0400 mov.w r4, #0 + 8004648: 0e0b lsrs r3, r1, #24 + 800464a: ea43 2302 orr.w r3, r3, r2, lsl #8 + 800464e: 0e14 lsrs r4, r2, #24 + 8004650: b2db uxtb r3, r3 + 8004652: 72fb strb r3, [r7, #11] + bytes[4] = (pb_byte_t)((val >> 32) & 0xFF); + 8004654: e9d7 1204 ldrd r1, r2, [r7, #16] + 8004658: f04f 0300 mov.w r3, #0 + 800465c: f04f 0400 mov.w r4, #0 + 8004660: 0013 movs r3, r2 + 8004662: 2400 movs r4, #0 + 8004664: b2db uxtb r3, r3 + 8004666: 733b strb r3, [r7, #12] + bytes[5] = (pb_byte_t)((val >> 40) & 0xFF); + 8004668: e9d7 1204 ldrd r1, r2, [r7, #16] + 800466c: f04f 0300 mov.w r3, #0 + 8004670: f04f 0400 mov.w r4, #0 + 8004674: 0a13 lsrs r3, r2, #8 + 8004676: 2400 movs r4, #0 + 8004678: b2db uxtb r3, r3 + 800467a: 737b strb r3, [r7, #13] + bytes[6] = (pb_byte_t)((val >> 48) & 0xFF); + 800467c: e9d7 1204 ldrd r1, r2, [r7, #16] + 8004680: f04f 0300 mov.w r3, #0 + 8004684: f04f 0400 mov.w r4, #0 + 8004688: 0c13 lsrs r3, r2, #16 + 800468a: 2400 movs r4, #0 + 800468c: b2db uxtb r3, r3 + 800468e: 73bb strb r3, [r7, #14] + bytes[7] = (pb_byte_t)((val >> 56) & 0xFF); + 8004690: e9d7 1204 ldrd r1, r2, [r7, #16] + 8004694: f04f 0300 mov.w r3, #0 + 8004698: f04f 0400 mov.w r4, #0 + 800469c: 0e13 lsrs r3, r2, #24 + 800469e: 2400 movs r4, #0 + 80046a0: b2db uxtb r3, r3 + 80046a2: 73fb strb r3, [r7, #15] + return pb_write(stream, bytes, 8); + 80046a4: f107 0308 add.w r3, r7, #8 + 80046a8: 2208 movs r2, #8 + 80046aa: 4619 mov r1, r3 + 80046ac: 6878 ldr r0, [r7, #4] + 80046ae: f7ff fa85 bl 8003bbc + 80046b2: 4603 mov r3, r0 +} + 80046b4: 4618 mov r0, r3 + 80046b6: 371c adds r7, #28 + 80046b8: 46bd mov sp, r7 + 80046ba: bd90 pop {r4, r7, pc} + +080046bc : +#endif + +bool checkreturn pb_encode_tag(pb_ostream_t *stream, pb_wire_type_t wiretype, uint32_t field_number) +{ + 80046bc: e92d 4890 stmdb sp!, {r4, r7, fp, lr} + 80046c0: b086 sub sp, #24 + 80046c2: af00 add r7, sp, #0 + 80046c4: 60f8 str r0, [r7, #12] + 80046c6: 607a str r2, [r7, #4] + 80046c8: 460a mov r2, r1 + 80046ca: 72fa strb r2, [r7, #11] + pb_uint64_t tag = ((pb_uint64_t)field_number << 3) | wiretype; + 80046cc: 687a ldr r2, [r7, #4] + 80046ce: 4611 mov r1, r2 + 80046d0: f04f 0200 mov.w r2, #0 + 80046d4: ea4f 7c51 mov.w ip, r1, lsr #29 + 80046d8: ea4f 0bc1 mov.w fp, r1, lsl #3 + 80046dc: 7af9 ldrb r1, [r7, #11] + 80046de: f04f 0200 mov.w r2, #0 + 80046e2: ea4b 0301 orr.w r3, fp, r1 + 80046e6: ea4c 0402 orr.w r4, ip, r2 + 80046ea: e9c7 3404 strd r3, r4, [r7, #16] + return pb_encode_varint(stream, tag); + 80046ee: e9d7 2304 ldrd r2, r3, [r7, #16] + 80046f2: 68f8 ldr r0, [r7, #12] + 80046f4: f7ff ff06 bl 8004504 + 80046f8: 4603 mov r3, r0 +} + 80046fa: 4618 mov r0, r3 + 80046fc: 3718 adds r7, #24 + 80046fe: 46bd mov sp, r7 + 8004700: e8bd 8890 ldmia.w sp!, {r4, r7, fp, pc} + +08004704 : + +bool pb_encode_tag_for_field ( pb_ostream_t* stream, const pb_field_iter_t* field ) +{ + 8004704: b580 push {r7, lr} + 8004706: b084 sub sp, #16 + 8004708: af00 add r7, sp, #0 + 800470a: 6078 str r0, [r7, #4] + 800470c: 6039 str r1, [r7, #0] + pb_wire_type_t wiretype; + switch (PB_LTYPE(field->type)) + 800470e: 683b ldr r3, [r7, #0] + 8004710: 7d9b ldrb r3, [r3, #22] + 8004712: f003 030f and.w r3, r3, #15 + 8004716: 2b0b cmp r3, #11 + 8004718: d826 bhi.n 8004768 + 800471a: a201 add r2, pc, #4 ; (adr r2, 8004720 ) + 800471c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8004720: 08004751 .word 0x08004751 + 8004724: 08004751 .word 0x08004751 + 8004728: 08004751 .word 0x08004751 + 800472c: 08004751 .word 0x08004751 + 8004730: 08004757 .word 0x08004757 + 8004734: 0800475d .word 0x0800475d + 8004738: 08004763 .word 0x08004763 + 800473c: 08004763 .word 0x08004763 + 8004740: 08004763 .word 0x08004763 + 8004744: 08004763 .word 0x08004763 + 8004748: 08004769 .word 0x08004769 + 800474c: 08004763 .word 0x08004763 + { + case PB_LTYPE_BOOL: + case PB_LTYPE_VARINT: + case PB_LTYPE_UVARINT: + case PB_LTYPE_SVARINT: + wiretype = PB_WT_VARINT; + 8004750: 2300 movs r3, #0 + 8004752: 73fb strb r3, [r7, #15] + break; + 8004754: e014 b.n 8004780 + + case PB_LTYPE_FIXED32: + wiretype = PB_WT_32BIT; + 8004756: 2305 movs r3, #5 + 8004758: 73fb strb r3, [r7, #15] + break; + 800475a: e011 b.n 8004780 + + case PB_LTYPE_FIXED64: + wiretype = PB_WT_64BIT; + 800475c: 2301 movs r3, #1 + 800475e: 73fb strb r3, [r7, #15] + break; + 8004760: e00e b.n 8004780 + case PB_LTYPE_BYTES: + case PB_LTYPE_STRING: + case PB_LTYPE_SUBMESSAGE: + case PB_LTYPE_SUBMSG_W_CB: + case PB_LTYPE_FIXED_LENGTH_BYTES: + wiretype = PB_WT_STRING; + 8004762: 2302 movs r3, #2 + 8004764: 73fb strb r3, [r7, #15] + break; + 8004766: e00b b.n 8004780 + + default: + PB_RETURN_ERROR(stream, "invalid field type"); + 8004768: 687b ldr r3, [r7, #4] + 800476a: 691b ldr r3, [r3, #16] + 800476c: 2b00 cmp r3, #0 + 800476e: d002 beq.n 8004776 + 8004770: 687b ldr r3, [r7, #4] + 8004772: 691b ldr r3, [r3, #16] + 8004774: e000 b.n 8004778 + 8004776: 4b09 ldr r3, [pc, #36] ; (800479c ) + 8004778: 687a ldr r2, [r7, #4] + 800477a: 6113 str r3, [r2, #16] + 800477c: 2300 movs r3, #0 + 800477e: e008 b.n 8004792 + } + + return pb_encode_tag(stream, wiretype, field->tag); + 8004780: 683b ldr r3, [r7, #0] + 8004782: 8a1b ldrh r3, [r3, #16] + 8004784: 461a mov r2, r3 + 8004786: 7bfb ldrb r3, [r7, #15] + 8004788: 4619 mov r1, r3 + 800478a: 6878 ldr r0, [r7, #4] + 800478c: f7ff ff96 bl 80046bc + 8004790: 4603 mov r3, r0 +} + 8004792: 4618 mov r0, r3 + 8004794: 3710 adds r7, #16 + 8004796: 46bd mov sp, r7 + 8004798: bd80 pop {r7, pc} + 800479a: bf00 nop + 800479c: 08008bd8 .word 0x08008bd8 + +080047a0 : + +bool checkreturn pb_encode_string(pb_ostream_t *stream, const pb_byte_t *buffer, size_t size) +{ + 80047a0: b590 push {r4, r7, lr} + 80047a2: b085 sub sp, #20 + 80047a4: af00 add r7, sp, #0 + 80047a6: 60f8 str r0, [r7, #12] + 80047a8: 60b9 str r1, [r7, #8] + 80047aa: 607a str r2, [r7, #4] + if (!pb_encode_varint(stream, (pb_uint64_t)size)) + 80047ac: 687b ldr r3, [r7, #4] + 80047ae: f04f 0400 mov.w r4, #0 + 80047b2: 461a mov r2, r3 + 80047b4: 4623 mov r3, r4 + 80047b6: 68f8 ldr r0, [r7, #12] + 80047b8: f7ff fea4 bl 8004504 + 80047bc: 4603 mov r3, r0 + 80047be: f083 0301 eor.w r3, r3, #1 + 80047c2: b2db uxtb r3, r3 + 80047c4: 2b00 cmp r3, #0 + 80047c6: d001 beq.n 80047cc + return false; + 80047c8: 2300 movs r3, #0 + 80047ca: e005 b.n 80047d8 + + return pb_write(stream, buffer, size); + 80047cc: 687a ldr r2, [r7, #4] + 80047ce: 68b9 ldr r1, [r7, #8] + 80047d0: 68f8 ldr r0, [r7, #12] + 80047d2: f7ff f9f3 bl 8003bbc + 80047d6: 4603 mov r3, r0 +} + 80047d8: 4618 mov r0, r3 + 80047da: 3714 adds r7, #20 + 80047dc: 46bd mov sp, r7 + 80047de: bd90 pop {r4, r7, pc} + +080047e0 : + +bool checkreturn pb_encode_submessage(pb_ostream_t *stream, const pb_msgdesc_t *fields, const void *src_struct) +{ + 80047e0: b590 push {r4, r7, lr} + 80047e2: b08d sub sp, #52 ; 0x34 + 80047e4: af00 add r7, sp, #0 + 80047e6: 60f8 str r0, [r7, #12] + 80047e8: 60b9 str r1, [r7, #8] + 80047ea: 607a str r2, [r7, #4] + /* First calculate the message size using a non-writing substream. */ + pb_ostream_t substream = PB_OSTREAM_SIZING; + 80047ec: f107 0314 add.w r3, r7, #20 + 80047f0: 2200 movs r2, #0 + 80047f2: 601a str r2, [r3, #0] + 80047f4: 605a str r2, [r3, #4] + 80047f6: 609a str r2, [r3, #8] + 80047f8: 60da str r2, [r3, #12] + 80047fa: 611a str r2, [r3, #16] + size_t size; + bool status; + + if (!pb_encode(&substream, fields, src_struct)) + 80047fc: f107 0314 add.w r3, r7, #20 + 8004800: 687a ldr r2, [r7, #4] + 8004802: 68b9 ldr r1, [r7, #8] + 8004804: 4618 mov r0, r3 + 8004806: f7ff fdcc bl 80043a2 + 800480a: 4603 mov r3, r0 + 800480c: f083 0301 eor.w r3, r3, #1 + 8004810: b2db uxtb r3, r3 + 8004812: 2b00 cmp r3, #0 + 8004814: d004 beq.n 8004820 + { +#ifndef PB_NO_ERRMSG + stream->errmsg = substream.errmsg; + 8004816: 6a7a ldr r2, [r7, #36] ; 0x24 + 8004818: 68fb ldr r3, [r7, #12] + 800481a: 611a str r2, [r3, #16] +#endif + return false; + 800481c: 2300 movs r3, #0 + 800481e: e064 b.n 80048ea + } + + size = substream.bytes_written; + 8004820: 6a3b ldr r3, [r7, #32] + 8004822: 62fb str r3, [r7, #44] ; 0x2c + + if (!pb_encode_varint(stream, (pb_uint64_t)size)) + 8004824: 6afb ldr r3, [r7, #44] ; 0x2c + 8004826: f04f 0400 mov.w r4, #0 + 800482a: 461a mov r2, r3 + 800482c: 4623 mov r3, r4 + 800482e: 68f8 ldr r0, [r7, #12] + 8004830: f7ff fe68 bl 8004504 + 8004834: 4603 mov r3, r0 + 8004836: f083 0301 eor.w r3, r3, #1 + 800483a: b2db uxtb r3, r3 + 800483c: 2b00 cmp r3, #0 + 800483e: d001 beq.n 8004844 + return false; + 8004840: 2300 movs r3, #0 + 8004842: e052 b.n 80048ea + + if (stream->callback == NULL) + 8004844: 68fb ldr r3, [r7, #12] + 8004846: 681b ldr r3, [r3, #0] + 8004848: 2b00 cmp r3, #0 + 800484a: d106 bne.n 800485a + return pb_write(stream, NULL, size); /* Just sizing */ + 800484c: 6afa ldr r2, [r7, #44] ; 0x2c + 800484e: 2100 movs r1, #0 + 8004850: 68f8 ldr r0, [r7, #12] + 8004852: f7ff f9b3 bl 8003bbc + 8004856: 4603 mov r3, r0 + 8004858: e047 b.n 80048ea + + if (stream->bytes_written + size > stream->max_size) + 800485a: 68fb ldr r3, [r7, #12] + 800485c: 68da ldr r2, [r3, #12] + 800485e: 6afb ldr r3, [r7, #44] ; 0x2c + 8004860: 441a add r2, r3 + 8004862: 68fb ldr r3, [r7, #12] + 8004864: 689b ldr r3, [r3, #8] + 8004866: 429a cmp r2, r3 + 8004868: d90b bls.n 8004882 + PB_RETURN_ERROR(stream, "stream full"); + 800486a: 68fb ldr r3, [r7, #12] + 800486c: 691b ldr r3, [r3, #16] + 800486e: 2b00 cmp r3, #0 + 8004870: d002 beq.n 8004878 + 8004872: 68fb ldr r3, [r7, #12] + 8004874: 691b ldr r3, [r3, #16] + 8004876: e000 b.n 800487a + 8004878: 4b1e ldr r3, [pc, #120] ; (80048f4 ) + 800487a: 68fa ldr r2, [r7, #12] + 800487c: 6113 str r3, [r2, #16] + 800487e: 2300 movs r3, #0 + 8004880: e033 b.n 80048ea + + /* Use a substream to verify that a callback doesn't write more than + * what it did the first time. */ + substream.callback = stream->callback; + 8004882: 68fb ldr r3, [r7, #12] + 8004884: 681b ldr r3, [r3, #0] + 8004886: 617b str r3, [r7, #20] + substream.state = stream->state; + 8004888: 68fb ldr r3, [r7, #12] + 800488a: 685b ldr r3, [r3, #4] + 800488c: 61bb str r3, [r7, #24] + substream.max_size = size; + 800488e: 6afb ldr r3, [r7, #44] ; 0x2c + 8004890: 61fb str r3, [r7, #28] + substream.bytes_written = 0; + 8004892: 2300 movs r3, #0 + 8004894: 623b str r3, [r7, #32] +#ifndef PB_NO_ERRMSG + substream.errmsg = NULL; + 8004896: 2300 movs r3, #0 + 8004898: 627b str r3, [r7, #36] ; 0x24 +#endif + + status = pb_encode(&substream, fields, src_struct); + 800489a: f107 0314 add.w r3, r7, #20 + 800489e: 687a ldr r2, [r7, #4] + 80048a0: 68b9 ldr r1, [r7, #8] + 80048a2: 4618 mov r0, r3 + 80048a4: f7ff fd7d bl 80043a2 + 80048a8: 4603 mov r3, r0 + 80048aa: f887 302b strb.w r3, [r7, #43] ; 0x2b + + stream->bytes_written += substream.bytes_written; + 80048ae: 68fb ldr r3, [r7, #12] + 80048b0: 68da ldr r2, [r3, #12] + 80048b2: 6a3b ldr r3, [r7, #32] + 80048b4: 441a add r2, r3 + 80048b6: 68fb ldr r3, [r7, #12] + 80048b8: 60da str r2, [r3, #12] + stream->state = substream.state; + 80048ba: 69ba ldr r2, [r7, #24] + 80048bc: 68fb ldr r3, [r7, #12] + 80048be: 605a str r2, [r3, #4] +#ifndef PB_NO_ERRMSG + stream->errmsg = substream.errmsg; + 80048c0: 6a7a ldr r2, [r7, #36] ; 0x24 + 80048c2: 68fb ldr r3, [r7, #12] + 80048c4: 611a str r2, [r3, #16] +#endif + + if (substream.bytes_written != size) + 80048c6: 6a3b ldr r3, [r7, #32] + 80048c8: 6afa ldr r2, [r7, #44] ; 0x2c + 80048ca: 429a cmp r2, r3 + 80048cc: d00b beq.n 80048e6 + PB_RETURN_ERROR(stream, "submsg size changed"); + 80048ce: 68fb ldr r3, [r7, #12] + 80048d0: 691b ldr r3, [r3, #16] + 80048d2: 2b00 cmp r3, #0 + 80048d4: d002 beq.n 80048dc + 80048d6: 68fb ldr r3, [r7, #12] + 80048d8: 691b ldr r3, [r3, #16] + 80048da: e000 b.n 80048de + 80048dc: 4b06 ldr r3, [pc, #24] ; (80048f8 ) + 80048de: 68fa ldr r2, [r7, #12] + 80048e0: 6113 str r3, [r2, #16] + 80048e2: 2300 movs r3, #0 + 80048e4: e001 b.n 80048ea + + return status; + 80048e6: f897 302b ldrb.w r3, [r7, #43] ; 0x2b +} + 80048ea: 4618 mov r0, r3 + 80048ec: 3734 adds r7, #52 ; 0x34 + 80048ee: 46bd mov sp, r7 + 80048f0: bd90 pop {r4, r7, pc} + 80048f2: bf00 nop + 80048f4: 08008ba0 .word 0x08008ba0 + 80048f8: 08008c28 .word 0x08008c28 + +080048fc : + +/* Field encoders */ + +static bool checkreturn pb_enc_bool(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + 80048fc: b590 push {r4, r7, lr} + 80048fe: b085 sub sp, #20 + 8004900: af00 add r7, sp, #0 + 8004902: 6078 str r0, [r7, #4] + 8004904: 6039 str r1, [r7, #0] + uint32_t value = safe_read_bool(field->pData) ? 1 : 0; + 8004906: 683b ldr r3, [r7, #0] + 8004908: 69db ldr r3, [r3, #28] + 800490a: 4618 mov r0, r3 + 800490c: f7ff f99e bl 8003c4c + 8004910: 4603 mov r3, r0 + 8004912: 60fb str r3, [r7, #12] + PB_UNUSED(field); + return pb_encode_varint(stream, value); + 8004914: 68fb ldr r3, [r7, #12] + 8004916: f04f 0400 mov.w r4, #0 + 800491a: 461a mov r2, r3 + 800491c: 4623 mov r3, r4 + 800491e: 6878 ldr r0, [r7, #4] + 8004920: f7ff fdf0 bl 8004504 + 8004924: 4603 mov r3, r0 +} + 8004926: 4618 mov r0, r3 + 8004928: 3714 adds r7, #20 + 800492a: 46bd mov sp, r7 + 800492c: bd90 pop {r4, r7, pc} + ... + +08004930 : + +static bool checkreturn pb_enc_varint(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + 8004930: b590 push {r4, r7, lr} + 8004932: b087 sub sp, #28 + 8004934: af00 add r7, sp, #0 + 8004936: 6078 str r0, [r7, #4] + 8004938: 6039 str r1, [r7, #0] + if (PB_LTYPE(field->type) == PB_LTYPE_UVARINT) + 800493a: 683b ldr r3, [r7, #0] + 800493c: 7d9b ldrb r3, [r3, #22] + 800493e: f003 030f and.w r3, r3, #15 + 8004942: 2b02 cmp r3, #2 + 8004944: d149 bne.n 80049da + { + /* Perform unsigned integer extension */ + pb_uint64_t value = 0; + 8004946: f04f 0300 mov.w r3, #0 + 800494a: f04f 0400 mov.w r4, #0 + 800494e: e9c7 3404 strd r3, r4, [r7, #16] + + if (field->data_size == sizeof(uint_least8_t)) + 8004952: 683b ldr r3, [r7, #0] + 8004954: 8a5b ldrh r3, [r3, #18] + 8004956: 2b01 cmp r3, #1 + 8004958: d108 bne.n 800496c + value = *(const uint_least8_t*)field->pData; + 800495a: 683b ldr r3, [r7, #0] + 800495c: 69db ldr r3, [r3, #28] + 800495e: 781b ldrb r3, [r3, #0] + 8004960: b2db uxtb r3, r3 + 8004962: f04f 0400 mov.w r4, #0 + 8004966: e9c7 3404 strd r3, r4, [r7, #16] + 800496a: e02f b.n 80049cc + else if (field->data_size == sizeof(uint_least16_t)) + 800496c: 683b ldr r3, [r7, #0] + 800496e: 8a5b ldrh r3, [r3, #18] + 8004970: 2b02 cmp r3, #2 + 8004972: d108 bne.n 8004986 + value = *(const uint_least16_t*)field->pData; + 8004974: 683b ldr r3, [r7, #0] + 8004976: 69db ldr r3, [r3, #28] + 8004978: 881b ldrh r3, [r3, #0] + 800497a: b29b uxth r3, r3 + 800497c: f04f 0400 mov.w r4, #0 + 8004980: e9c7 3404 strd r3, r4, [r7, #16] + 8004984: e022 b.n 80049cc + else if (field->data_size == sizeof(uint32_t)) + 8004986: 683b ldr r3, [r7, #0] + 8004988: 8a5b ldrh r3, [r3, #18] + 800498a: 2b04 cmp r3, #4 + 800498c: d107 bne.n 800499e + value = *(const uint32_t*)field->pData; + 800498e: 683b ldr r3, [r7, #0] + 8004990: 69db ldr r3, [r3, #28] + 8004992: 681b ldr r3, [r3, #0] + 8004994: f04f 0400 mov.w r4, #0 + 8004998: e9c7 3404 strd r3, r4, [r7, #16] + 800499c: e016 b.n 80049cc + else if (field->data_size == sizeof(pb_uint64_t)) + 800499e: 683b ldr r3, [r7, #0] + 80049a0: 8a5b ldrh r3, [r3, #18] + 80049a2: 2b08 cmp r3, #8 + 80049a4: d106 bne.n 80049b4 + value = *(const pb_uint64_t*)field->pData; + 80049a6: 683b ldr r3, [r7, #0] + 80049a8: 69db ldr r3, [r3, #28] + 80049aa: e9d3 3400 ldrd r3, r4, [r3] + 80049ae: e9c7 3404 strd r3, r4, [r7, #16] + 80049b2: e00b b.n 80049cc + else + PB_RETURN_ERROR(stream, "invalid data_size"); + 80049b4: 687b ldr r3, [r7, #4] + 80049b6: 691b ldr r3, [r3, #16] + 80049b8: 2b00 cmp r3, #0 + 80049ba: d002 beq.n 80049c2 + 80049bc: 687b ldr r3, [r7, #4] + 80049be: 691b ldr r3, [r3, #16] + 80049c0: e000 b.n 80049c4 + 80049c2: 4b35 ldr r3, [pc, #212] ; (8004a98 ) + 80049c4: 687a ldr r2, [r7, #4] + 80049c6: 6113 str r3, [r2, #16] + 80049c8: 2300 movs r3, #0 + 80049ca: e060 b.n 8004a8e + + return pb_encode_varint(stream, value); + 80049cc: e9d7 2304 ldrd r2, r3, [r7, #16] + 80049d0: 6878 ldr r0, [r7, #4] + 80049d2: f7ff fd97 bl 8004504 + 80049d6: 4603 mov r3, r0 + 80049d8: e059 b.n 8004a8e + } + else + { + /* Perform signed integer extension */ + pb_int64_t value = 0; + 80049da: f04f 0300 mov.w r3, #0 + 80049de: f04f 0400 mov.w r4, #0 + 80049e2: e9c7 3402 strd r3, r4, [r7, #8] + + if (field->data_size == sizeof(int_least8_t)) + 80049e6: 683b ldr r3, [r7, #0] + 80049e8: 8a5b ldrh r3, [r3, #18] + 80049ea: 2b01 cmp r3, #1 + 80049ec: d109 bne.n 8004a02 + value = *(const int_least8_t*)field->pData; + 80049ee: 683b ldr r3, [r7, #0] + 80049f0: 69db ldr r3, [r3, #28] + 80049f2: f993 3000 ldrsb.w r3, [r3] + 80049f6: b25b sxtb r3, r3 + 80049f8: ea4f 74e3 mov.w r4, r3, asr #31 + 80049fc: e9c7 3402 strd r3, r4, [r7, #8] + 8004a00: e030 b.n 8004a64 + else if (field->data_size == sizeof(int_least16_t)) + 8004a02: 683b ldr r3, [r7, #0] + 8004a04: 8a5b ldrh r3, [r3, #18] + 8004a06: 2b02 cmp r3, #2 + 8004a08: d109 bne.n 8004a1e + value = *(const int_least16_t*)field->pData; + 8004a0a: 683b ldr r3, [r7, #0] + 8004a0c: 69db ldr r3, [r3, #28] + 8004a0e: f9b3 3000 ldrsh.w r3, [r3] + 8004a12: b21b sxth r3, r3 + 8004a14: ea4f 74e3 mov.w r4, r3, asr #31 + 8004a18: e9c7 3402 strd r3, r4, [r7, #8] + 8004a1c: e022 b.n 8004a64 + else if (field->data_size == sizeof(int32_t)) + 8004a1e: 683b ldr r3, [r7, #0] + 8004a20: 8a5b ldrh r3, [r3, #18] + 8004a22: 2b04 cmp r3, #4 + 8004a24: d107 bne.n 8004a36 + value = *(const int32_t*)field->pData; + 8004a26: 683b ldr r3, [r7, #0] + 8004a28: 69db ldr r3, [r3, #28] + 8004a2a: 681b ldr r3, [r3, #0] + 8004a2c: ea4f 74e3 mov.w r4, r3, asr #31 + 8004a30: e9c7 3402 strd r3, r4, [r7, #8] + 8004a34: e016 b.n 8004a64 + else if (field->data_size == sizeof(pb_int64_t)) + 8004a36: 683b ldr r3, [r7, #0] + 8004a38: 8a5b ldrh r3, [r3, #18] + 8004a3a: 2b08 cmp r3, #8 + 8004a3c: d106 bne.n 8004a4c + value = *(const pb_int64_t*)field->pData; + 8004a3e: 683b ldr r3, [r7, #0] + 8004a40: 69db ldr r3, [r3, #28] + 8004a42: e9d3 3400 ldrd r3, r4, [r3] + 8004a46: e9c7 3402 strd r3, r4, [r7, #8] + 8004a4a: e00b b.n 8004a64 + else + PB_RETURN_ERROR(stream, "invalid data_size"); + 8004a4c: 687b ldr r3, [r7, #4] + 8004a4e: 691b ldr r3, [r3, #16] + 8004a50: 2b00 cmp r3, #0 + 8004a52: d002 beq.n 8004a5a + 8004a54: 687b ldr r3, [r7, #4] + 8004a56: 691b ldr r3, [r3, #16] + 8004a58: e000 b.n 8004a5c + 8004a5a: 4b0f ldr r3, [pc, #60] ; (8004a98 ) + 8004a5c: 687a ldr r2, [r7, #4] + 8004a5e: 6113 str r3, [r2, #16] + 8004a60: 2300 movs r3, #0 + 8004a62: e014 b.n 8004a8e + + if (PB_LTYPE(field->type) == PB_LTYPE_SVARINT) + 8004a64: 683b ldr r3, [r7, #0] + 8004a66: 7d9b ldrb r3, [r3, #22] + 8004a68: f003 030f and.w r3, r3, #15 + 8004a6c: 2b03 cmp r3, #3 + 8004a6e: d106 bne.n 8004a7e + return pb_encode_svarint(stream, value); + 8004a70: e9d7 2302 ldrd r2, r3, [r7, #8] + 8004a74: 6878 ldr r0, [r7, #4] + 8004a76: f7ff fd6f bl 8004558 + 8004a7a: 4603 mov r3, r0 + 8004a7c: e007 b.n 8004a8e +#ifdef PB_WITHOUT_64BIT + else if (value < 0) + return pb_encode_varint_32(stream, (uint32_t)value, (uint32_t)-1); +#endif + else + return pb_encode_varint(stream, (pb_uint64_t)value); + 8004a7e: e9d7 3402 ldrd r3, r4, [r7, #8] + 8004a82: 461a mov r2, r3 + 8004a84: 4623 mov r3, r4 + 8004a86: 6878 ldr r0, [r7, #4] + 8004a88: f7ff fd3c bl 8004504 + 8004a8c: 4603 mov r3, r0 + + } +} + 8004a8e: 4618 mov r0, r3 + 8004a90: 371c adds r7, #28 + 8004a92: 46bd mov sp, r7 + 8004a94: bd90 pop {r4, r7, pc} + 8004a96: bf00 nop + 8004a98: 08008c3c .word 0x08008c3c + +08004a9c : + +static bool checkreturn pb_enc_fixed(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + 8004a9c: b580 push {r7, lr} + 8004a9e: b082 sub sp, #8 + 8004aa0: af00 add r7, sp, #0 + 8004aa2: 6078 str r0, [r7, #4] + 8004aa4: 6039 str r1, [r7, #0] + { + return pb_encode_float_as_double(stream, *(float*)field->pData); + } +#endif + + if (field->data_size == sizeof(uint32_t)) + 8004aa6: 683b ldr r3, [r7, #0] + 8004aa8: 8a5b ldrh r3, [r3, #18] + 8004aaa: 2b04 cmp r3, #4 + 8004aac: d107 bne.n 8004abe + { + return pb_encode_fixed32(stream, field->pData); + 8004aae: 683b ldr r3, [r7, #0] + 8004ab0: 69db ldr r3, [r3, #28] + 8004ab2: 4619 mov r1, r3 + 8004ab4: 6878 ldr r0, [r7, #4] + 8004ab6: f7ff fd7a bl 80045ae + 8004aba: 4603 mov r3, r0 + 8004abc: e016 b.n 8004aec + } +#ifndef PB_WITHOUT_64BIT + else if (field->data_size == sizeof(uint64_t)) + 8004abe: 683b ldr r3, [r7, #0] + 8004ac0: 8a5b ldrh r3, [r3, #18] + 8004ac2: 2b08 cmp r3, #8 + 8004ac4: d107 bne.n 8004ad6 + { + return pb_encode_fixed64(stream, field->pData); + 8004ac6: 683b ldr r3, [r7, #0] + 8004ac8: 69db ldr r3, [r3, #28] + 8004aca: 4619 mov r1, r3 + 8004acc: 6878 ldr r0, [r7, #4] + 8004ace: f7ff fd91 bl 80045f4 + 8004ad2: 4603 mov r3, r0 + 8004ad4: e00a b.n 8004aec + } +#endif + else + { + PB_RETURN_ERROR(stream, "invalid data_size"); + 8004ad6: 687b ldr r3, [r7, #4] + 8004ad8: 691b ldr r3, [r3, #16] + 8004ada: 2b00 cmp r3, #0 + 8004adc: d002 beq.n 8004ae4 + 8004ade: 687b ldr r3, [r7, #4] + 8004ae0: 691b ldr r3, [r3, #16] + 8004ae2: e000 b.n 8004ae6 + 8004ae4: 4b03 ldr r3, [pc, #12] ; (8004af4 ) + 8004ae6: 687a ldr r2, [r7, #4] + 8004ae8: 6113 str r3, [r2, #16] + 8004aea: 2300 movs r3, #0 + } +} + 8004aec: 4618 mov r0, r3 + 8004aee: 3708 adds r7, #8 + 8004af0: 46bd mov sp, r7 + 8004af2: bd80 pop {r7, pc} + 8004af4: 08008c3c .word 0x08008c3c + +08004af8 : + +static bool checkreturn pb_enc_bytes(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + 8004af8: b580 push {r7, lr} + 8004afa: b084 sub sp, #16 + 8004afc: af00 add r7, sp, #0 + 8004afe: 6078 str r0, [r7, #4] + 8004b00: 6039 str r1, [r7, #0] + const pb_bytes_array_t *bytes = NULL; + 8004b02: 2300 movs r3, #0 + 8004b04: 60fb str r3, [r7, #12] + + bytes = (const pb_bytes_array_t*)field->pData; + 8004b06: 683b ldr r3, [r7, #0] + 8004b08: 69db ldr r3, [r3, #28] + 8004b0a: 60fb str r3, [r7, #12] + + if (bytes == NULL) + 8004b0c: 68fb ldr r3, [r7, #12] + 8004b0e: 2b00 cmp r3, #0 + 8004b10: d106 bne.n 8004b20 + { + /* Treat null pointer as an empty bytes field */ + return pb_encode_string(stream, NULL, 0); + 8004b12: 2200 movs r2, #0 + 8004b14: 2100 movs r1, #0 + 8004b16: 6878 ldr r0, [r7, #4] + 8004b18: f7ff fe42 bl 80047a0 + 8004b1c: 4603 mov r3, r0 + 8004b1e: e021 b.n 8004b64 + } + + if (PB_ATYPE(field->type) == PB_ATYPE_STATIC && + 8004b20: 683b ldr r3, [r7, #0] + 8004b22: 7d9b ldrb r3, [r3, #22] + 8004b24: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 8004b28: 2b00 cmp r3, #0 + 8004b2a: d112 bne.n 8004b52 + PB_BYTES_ARRAY_T_ALLOCSIZE(bytes->size) > field->data_size) + 8004b2c: 68fb ldr r3, [r7, #12] + 8004b2e: 881b ldrh r3, [r3, #0] + 8004b30: 3302 adds r3, #2 + 8004b32: 683a ldr r2, [r7, #0] + 8004b34: 8a52 ldrh r2, [r2, #18] + if (PB_ATYPE(field->type) == PB_ATYPE_STATIC && + 8004b36: 4293 cmp r3, r2 + 8004b38: d90b bls.n 8004b52 + { + PB_RETURN_ERROR(stream, "bytes size exceeded"); + 8004b3a: 687b ldr r3, [r7, #4] + 8004b3c: 691b ldr r3, [r3, #16] + 8004b3e: 2b00 cmp r3, #0 + 8004b40: d002 beq.n 8004b48 + 8004b42: 687b ldr r3, [r7, #4] + 8004b44: 691b ldr r3, [r3, #16] + 8004b46: e000 b.n 8004b4a + 8004b48: 4b08 ldr r3, [pc, #32] ; (8004b6c ) + 8004b4a: 687a ldr r2, [r7, #4] + 8004b4c: 6113 str r3, [r2, #16] + 8004b4e: 2300 movs r3, #0 + 8004b50: e008 b.n 8004b64 + } + + return pb_encode_string(stream, bytes->bytes, (size_t)bytes->size); + 8004b52: 68fb ldr r3, [r7, #12] + 8004b54: 1c99 adds r1, r3, #2 + 8004b56: 68fb ldr r3, [r7, #12] + 8004b58: 881b ldrh r3, [r3, #0] + 8004b5a: 461a mov r2, r3 + 8004b5c: 6878 ldr r0, [r7, #4] + 8004b5e: f7ff fe1f bl 80047a0 + 8004b62: 4603 mov r3, r0 +} + 8004b64: 4618 mov r0, r3 + 8004b66: 3710 adds r7, #16 + 8004b68: 46bd mov sp, r7 + 8004b6a: bd80 pop {r7, pc} + 8004b6c: 08008c50 .word 0x08008c50 + +08004b70 : + +static bool checkreturn pb_enc_string(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + 8004b70: b580 push {r7, lr} + 8004b72: b086 sub sp, #24 + 8004b74: af00 add r7, sp, #0 + 8004b76: 6078 str r0, [r7, #4] + 8004b78: 6039 str r1, [r7, #0] + size_t size = 0; + 8004b7a: 2300 movs r3, #0 + 8004b7c: 617b str r3, [r7, #20] + size_t max_size = (size_t)field->data_size; + 8004b7e: 683b ldr r3, [r7, #0] + 8004b80: 8a5b ldrh r3, [r3, #18] + 8004b82: 613b str r3, [r7, #16] + const char *str = (const char*)field->pData; + 8004b84: 683b ldr r3, [r7, #0] + 8004b86: 69db ldr r3, [r3, #28] + 8004b88: 60bb str r3, [r7, #8] + + if (PB_ATYPE(field->type) == PB_ATYPE_POINTER) + 8004b8a: 683b ldr r3, [r7, #0] + 8004b8c: 7d9b ldrb r3, [r3, #22] + 8004b8e: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 8004b92: 2b80 cmp r3, #128 ; 0x80 + 8004b94: d103 bne.n 8004b9e + { + max_size = (size_t)-1; + 8004b96: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8004b9a: 613b str r3, [r7, #16] + 8004b9c: e011 b.n 8004bc2 + /* pb_dec_string() assumes string fields end with a null + * terminator when the type isn't PB_ATYPE_POINTER, so we + * shouldn't allow more than max-1 bytes to be written to + * allow space for the null terminator. + */ + if (max_size == 0) + 8004b9e: 693b ldr r3, [r7, #16] + 8004ba0: 2b00 cmp r3, #0 + 8004ba2: d10b bne.n 8004bbc + PB_RETURN_ERROR(stream, "zero-length string"); + 8004ba4: 687b ldr r3, [r7, #4] + 8004ba6: 691b ldr r3, [r3, #16] + 8004ba8: 2b00 cmp r3, #0 + 8004baa: d002 beq.n 8004bb2 + 8004bac: 687b ldr r3, [r7, #4] + 8004bae: 691b ldr r3, [r3, #16] + 8004bb0: e000 b.n 8004bb4 + 8004bb2: 4b1c ldr r3, [pc, #112] ; (8004c24 ) + 8004bb4: 687a ldr r2, [r7, #4] + 8004bb6: 6113 str r3, [r2, #16] + 8004bb8: 2300 movs r3, #0 + 8004bba: e02f b.n 8004c1c + + max_size -= 1; + 8004bbc: 693b ldr r3, [r7, #16] + 8004bbe: 3b01 subs r3, #1 + 8004bc0: 613b str r3, [r7, #16] + } + + + if (str == NULL) + 8004bc2: 68bb ldr r3, [r7, #8] + 8004bc4: 2b00 cmp r3, #0 + 8004bc6: d102 bne.n 8004bce + { + size = 0; /* Treat null pointer as an empty string */ + 8004bc8: 2300 movs r3, #0 + 8004bca: 617b str r3, [r7, #20] + 8004bcc: e020 b.n 8004c10 + } + else + { + const char *p = str; + 8004bce: 68bb ldr r3, [r7, #8] + 8004bd0: 60fb str r3, [r7, #12] + + /* strnlen() is not always available, so just use a loop */ + while (size < max_size && *p != '\0') + 8004bd2: e005 b.n 8004be0 + { + size++; + 8004bd4: 697b ldr r3, [r7, #20] + 8004bd6: 3301 adds r3, #1 + 8004bd8: 617b str r3, [r7, #20] + p++; + 8004bda: 68fb ldr r3, [r7, #12] + 8004bdc: 3301 adds r3, #1 + 8004bde: 60fb str r3, [r7, #12] + while (size < max_size && *p != '\0') + 8004be0: 697a ldr r2, [r7, #20] + 8004be2: 693b ldr r3, [r7, #16] + 8004be4: 429a cmp r2, r3 + 8004be6: d203 bcs.n 8004bf0 + 8004be8: 68fb ldr r3, [r7, #12] + 8004bea: 781b ldrb r3, [r3, #0] + 8004bec: 2b00 cmp r3, #0 + 8004bee: d1f1 bne.n 8004bd4 + } + + if (*p != '\0') + 8004bf0: 68fb ldr r3, [r7, #12] + 8004bf2: 781b ldrb r3, [r3, #0] + 8004bf4: 2b00 cmp r3, #0 + 8004bf6: d00b beq.n 8004c10 + { + PB_RETURN_ERROR(stream, "unterminated string"); + 8004bf8: 687b ldr r3, [r7, #4] + 8004bfa: 691b ldr r3, [r3, #16] + 8004bfc: 2b00 cmp r3, #0 + 8004bfe: d002 beq.n 8004c06 + 8004c00: 687b ldr r3, [r7, #4] + 8004c02: 691b ldr r3, [r3, #16] + 8004c04: e000 b.n 8004c08 + 8004c06: 4b08 ldr r3, [pc, #32] ; (8004c28 ) + 8004c08: 687a ldr r2, [r7, #4] + 8004c0a: 6113 str r3, [r2, #16] + 8004c0c: 2300 movs r3, #0 + 8004c0e: e005 b.n 8004c1c +#ifdef PB_VALIDATE_UTF8 + if (!pb_validate_utf8(str)) + PB_RETURN_ERROR(stream, "invalid utf8"); +#endif + + return pb_encode_string(stream, (const pb_byte_t*)str, size); + 8004c10: 697a ldr r2, [r7, #20] + 8004c12: 68b9 ldr r1, [r7, #8] + 8004c14: 6878 ldr r0, [r7, #4] + 8004c16: f7ff fdc3 bl 80047a0 + 8004c1a: 4603 mov r3, r0 +} + 8004c1c: 4618 mov r0, r3 + 8004c1e: 3718 adds r7, #24 + 8004c20: 46bd mov sp, r7 + 8004c22: bd80 pop {r7, pc} + 8004c24: 08008c64 .word 0x08008c64 + 8004c28: 08008c78 .word 0x08008c78 + +08004c2c : + +static bool checkreturn pb_enc_submessage(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + 8004c2c: b580 push {r7, lr} + 8004c2e: b084 sub sp, #16 + 8004c30: af00 add r7, sp, #0 + 8004c32: 6078 str r0, [r7, #4] + 8004c34: 6039 str r1, [r7, #0] + if (field->submsg_desc == NULL) + 8004c36: 683b ldr r3, [r7, #0] + 8004c38: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004c3a: 2b00 cmp r3, #0 + 8004c3c: d10b bne.n 8004c56 + PB_RETURN_ERROR(stream, "invalid field descriptor"); + 8004c3e: 687b ldr r3, [r7, #4] + 8004c40: 691b ldr r3, [r3, #16] + 8004c42: 2b00 cmp r3, #0 + 8004c44: d002 beq.n 8004c4c + 8004c46: 687b ldr r3, [r7, #4] + 8004c48: 691b ldr r3, [r3, #16] + 8004c4a: e000 b.n 8004c4e + 8004c4c: 4b19 ldr r3, [pc, #100] ; (8004cb4 ) + 8004c4e: 687a ldr r2, [r7, #4] + 8004c50: 6113 str r3, [r2, #16] + 8004c52: 2300 movs r3, #0 + 8004c54: e029 b.n 8004caa + + if (PB_LTYPE(field->type) == PB_LTYPE_SUBMSG_W_CB && field->pSize != NULL) + 8004c56: 683b ldr r3, [r7, #0] + 8004c58: 7d9b ldrb r3, [r3, #22] + 8004c5a: f003 030f and.w r3, r3, #15 + 8004c5e: 2b09 cmp r3, #9 + 8004c60: d11a bne.n 8004c98 + 8004c62: 683b ldr r3, [r7, #0] + 8004c64: 6a1b ldr r3, [r3, #32] + 8004c66: 2b00 cmp r3, #0 + 8004c68: d016 beq.n 8004c98 + { + /* Message callback is stored right before pSize. */ + pb_callback_t *callback = (pb_callback_t*)field->pSize - 1; + 8004c6a: 683b ldr r3, [r7, #0] + 8004c6c: 6a1b ldr r3, [r3, #32] + 8004c6e: 3b08 subs r3, #8 + 8004c70: 60fb str r3, [r7, #12] + if (callback->funcs.encode) + 8004c72: 68fb ldr r3, [r7, #12] + 8004c74: 681b ldr r3, [r3, #0] + 8004c76: 2b00 cmp r3, #0 + 8004c78: d00e beq.n 8004c98 + { + if (!callback->funcs.encode(stream, field, &callback->arg)) + 8004c7a: 68fb ldr r3, [r7, #12] + 8004c7c: 681b ldr r3, [r3, #0] + 8004c7e: 68fa ldr r2, [r7, #12] + 8004c80: 3204 adds r2, #4 + 8004c82: 6839 ldr r1, [r7, #0] + 8004c84: 6878 ldr r0, [r7, #4] + 8004c86: 4798 blx r3 + 8004c88: 4603 mov r3, r0 + 8004c8a: f083 0301 eor.w r3, r3, #1 + 8004c8e: b2db uxtb r3, r3 + 8004c90: 2b00 cmp r3, #0 + 8004c92: d001 beq.n 8004c98 + return false; + 8004c94: 2300 movs r3, #0 + 8004c96: e008 b.n 8004caa + } + } + + return pb_encode_submessage(stream, field->submsg_desc, field->pData); + 8004c98: 683b ldr r3, [r7, #0] + 8004c9a: 6a59 ldr r1, [r3, #36] ; 0x24 + 8004c9c: 683b ldr r3, [r7, #0] + 8004c9e: 69db ldr r3, [r3, #28] + 8004ca0: 461a mov r2, r3 + 8004ca2: 6878 ldr r0, [r7, #4] + 8004ca4: f7ff fd9c bl 80047e0 + 8004ca8: 4603 mov r3, r0 +} + 8004caa: 4618 mov r0, r3 + 8004cac: 3710 adds r7, #16 + 8004cae: 46bd mov sp, r7 + 8004cb0: bd80 pop {r7, pc} + 8004cb2: bf00 nop + 8004cb4: 08008c8c .word 0x08008c8c + +08004cb8 : + +static bool checkreturn pb_enc_fixed_length_bytes(pb_ostream_t *stream, const pb_field_iter_t *field) +{ + 8004cb8: b580 push {r7, lr} + 8004cba: b082 sub sp, #8 + 8004cbc: af00 add r7, sp, #0 + 8004cbe: 6078 str r0, [r7, #4] + 8004cc0: 6039 str r1, [r7, #0] + return pb_encode_string(stream, (const pb_byte_t*)field->pData, (size_t)field->data_size); + 8004cc2: 683b ldr r3, [r7, #0] + 8004cc4: 69d9 ldr r1, [r3, #28] + 8004cc6: 683b ldr r3, [r7, #0] + 8004cc8: 8a5b ldrh r3, [r3, #18] + 8004cca: 461a mov r2, r3 + 8004ccc: 6878 ldr r0, [r7, #4] + 8004cce: f7ff fd67 bl 80047a0 + 8004cd2: 4603 mov r3, r0 +} + 8004cd4: 4618 mov r0, r3 + 8004cd6: 3708 adds r7, #8 + 8004cd8: 46bd mov sp, r7 + 8004cda: bd80 pop {r7, pc} + +08004cdc : +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 8004cdc: b480 push {r7} + 8004cde: b083 sub sp, #12 + 8004ce0: af00 add r7, sp, #0 + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_PWR_CLK_ENABLE(); + 8004ce2: 4b0f ldr r3, [pc, #60] ; (8004d20 ) + 8004ce4: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004ce6: 4a0e ldr r2, [pc, #56] ; (8004d20 ) + 8004ce8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8004cec: 6413 str r3, [r2, #64] ; 0x40 + 8004cee: 4b0c ldr r3, [pc, #48] ; (8004d20 ) + 8004cf0: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004cf2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8004cf6: 607b str r3, [r7, #4] + 8004cf8: 687b ldr r3, [r7, #4] + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8004cfa: 4b09 ldr r3, [pc, #36] ; (8004d20 ) + 8004cfc: 6c5b ldr r3, [r3, #68] ; 0x44 + 8004cfe: 4a08 ldr r2, [pc, #32] ; (8004d20 ) + 8004d00: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8004d04: 6453 str r3, [r2, #68] ; 0x44 + 8004d06: 4b06 ldr r3, [pc, #24] ; (8004d20 ) + 8004d08: 6c5b ldr r3, [r3, #68] ; 0x44 + 8004d0a: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8004d0e: 603b str r3, [r7, #0] + 8004d10: 683b ldr r3, [r7, #0] + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8004d12: bf00 nop + 8004d14: 370c adds r7, #12 + 8004d16: 46bd mov sp, r7 + 8004d18: f85d 7b04 ldr.w r7, [sp], #4 + 8004d1c: 4770 bx lr + 8004d1e: bf00 nop + 8004d20: 40023800 .word 0x40023800 + +08004d24 : +* This function configures the hardware resources used in this example +* @param htim_encoder: TIM_Encoder handle pointer +* @retval None +*/ +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder) +{ + 8004d24: b580 push {r7, lr} + 8004d26: b08c sub sp, #48 ; 0x30 + 8004d28: af00 add r7, sp, #0 + 8004d2a: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8004d2c: f107 031c add.w r3, r7, #28 + 8004d30: 2200 movs r2, #0 + 8004d32: 601a str r2, [r3, #0] + 8004d34: 605a str r2, [r3, #4] + 8004d36: 609a str r2, [r3, #8] + 8004d38: 60da str r2, [r3, #12] + 8004d3a: 611a str r2, [r3, #16] + if(htim_encoder->Instance==TIM2) + 8004d3c: 687b ldr r3, [r7, #4] + 8004d3e: 681b ldr r3, [r3, #0] + 8004d40: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 8004d44: d144 bne.n 8004dd0 + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + 8004d46: 4b3b ldr r3, [pc, #236] ; (8004e34 ) + 8004d48: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004d4a: 4a3a ldr r2, [pc, #232] ; (8004e34 ) + 8004d4c: f043 0301 orr.w r3, r3, #1 + 8004d50: 6413 str r3, [r2, #64] ; 0x40 + 8004d52: 4b38 ldr r3, [pc, #224] ; (8004e34 ) + 8004d54: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004d56: f003 0301 and.w r3, r3, #1 + 8004d5a: 61bb str r3, [r7, #24] + 8004d5c: 69bb ldr r3, [r7, #24] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8004d5e: 4b35 ldr r3, [pc, #212] ; (8004e34 ) + 8004d60: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004d62: 4a34 ldr r2, [pc, #208] ; (8004e34 ) + 8004d64: f043 0301 orr.w r3, r3, #1 + 8004d68: 6313 str r3, [r2, #48] ; 0x30 + 8004d6a: 4b32 ldr r3, [pc, #200] ; (8004e34 ) + 8004d6c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004d6e: f003 0301 and.w r3, r3, #1 + 8004d72: 617b str r3, [r7, #20] + 8004d74: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8004d76: 4b2f ldr r3, [pc, #188] ; (8004e34 ) + 8004d78: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004d7a: 4a2e ldr r2, [pc, #184] ; (8004e34 ) + 8004d7c: f043 0302 orr.w r3, r3, #2 + 8004d80: 6313 str r3, [r2, #48] ; 0x30 + 8004d82: 4b2c ldr r3, [pc, #176] ; (8004e34 ) + 8004d84: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004d86: f003 0302 and.w r3, r3, #2 + 8004d8a: 613b str r3, [r7, #16] + 8004d8c: 693b ldr r3, [r7, #16] + /**TIM2 GPIO Configuration + PA5 ------> TIM2_CH1 + PB3 ------> TIM2_CH2 + */ + GPIO_InitStruct.Pin = encoder_sx1_Pin; + 8004d8e: 2320 movs r3, #32 + 8004d90: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8004d92: 2302 movs r3, #2 + 8004d94: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8004d96: 2300 movs r3, #0 + 8004d98: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8004d9a: 2300 movs r3, #0 + 8004d9c: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; + 8004d9e: 2301 movs r3, #1 + 8004da0: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(encoder_sx1_GPIO_Port, &GPIO_InitStruct); + 8004da2: f107 031c add.w r3, r7, #28 + 8004da6: 4619 mov r1, r3 + 8004da8: 4823 ldr r0, [pc, #140] ; (8004e38 ) + 8004daa: f000 fb53 bl 8005454 + + GPIO_InitStruct.Pin = encoder_sx2_Pin; + 8004dae: 2308 movs r3, #8 + 8004db0: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8004db2: 2302 movs r3, #2 + 8004db4: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8004db6: 2300 movs r3, #0 + 8004db8: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8004dba: 2300 movs r3, #0 + 8004dbc: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; + 8004dbe: 2301 movs r3, #1 + 8004dc0: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(encoder_sx2_GPIO_Port, &GPIO_InitStruct); + 8004dc2: f107 031c add.w r3, r7, #28 + 8004dc6: 4619 mov r1, r3 + 8004dc8: 481c ldr r0, [pc, #112] ; (8004e3c ) + 8004dca: f000 fb43 bl 8005454 + /* USER CODE BEGIN TIM5_MspInit 1 */ + + /* USER CODE END TIM5_MspInit 1 */ + } + +} + 8004dce: e02c b.n 8004e2a + else if(htim_encoder->Instance==TIM5) + 8004dd0: 687b ldr r3, [r7, #4] + 8004dd2: 681b ldr r3, [r3, #0] + 8004dd4: 4a1a ldr r2, [pc, #104] ; (8004e40 ) + 8004dd6: 4293 cmp r3, r2 + 8004dd8: d127 bne.n 8004e2a + __HAL_RCC_TIM5_CLK_ENABLE(); + 8004dda: 4b16 ldr r3, [pc, #88] ; (8004e34 ) + 8004ddc: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004dde: 4a15 ldr r2, [pc, #84] ; (8004e34 ) + 8004de0: f043 0308 orr.w r3, r3, #8 + 8004de4: 6413 str r3, [r2, #64] ; 0x40 + 8004de6: 4b13 ldr r3, [pc, #76] ; (8004e34 ) + 8004de8: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004dea: f003 0308 and.w r3, r3, #8 + 8004dee: 60fb str r3, [r7, #12] + 8004df0: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8004df2: 4b10 ldr r3, [pc, #64] ; (8004e34 ) + 8004df4: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004df6: 4a0f ldr r2, [pc, #60] ; (8004e34 ) + 8004df8: f043 0301 orr.w r3, r3, #1 + 8004dfc: 6313 str r3, [r2, #48] ; 0x30 + 8004dfe: 4b0d ldr r3, [pc, #52] ; (8004e34 ) + 8004e00: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004e02: f003 0301 and.w r3, r3, #1 + 8004e06: 60bb str r3, [r7, #8] + 8004e08: 68bb ldr r3, [r7, #8] + GPIO_InitStruct.Pin = encoder_dx1_Pin|encoder_dx2_Pin; + 8004e0a: 2303 movs r3, #3 + 8004e0c: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8004e0e: 2302 movs r3, #2 + 8004e10: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8004e12: 2300 movs r3, #0 + 8004e14: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8004e16: 2300 movs r3, #0 + 8004e18: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Alternate = GPIO_AF2_TIM5; + 8004e1a: 2302 movs r3, #2 + 8004e1c: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8004e1e: f107 031c add.w r3, r7, #28 + 8004e22: 4619 mov r1, r3 + 8004e24: 4804 ldr r0, [pc, #16] ; (8004e38 ) + 8004e26: f000 fb15 bl 8005454 +} + 8004e2a: bf00 nop + 8004e2c: 3730 adds r7, #48 ; 0x30 + 8004e2e: 46bd mov sp, r7 + 8004e30: bd80 pop {r7, pc} + 8004e32: bf00 nop + 8004e34: 40023800 .word 0x40023800 + 8004e38: 40020000 .word 0x40020000 + 8004e3c: 40020400 .word 0x40020400 + 8004e40: 40000c00 .word 0x40000c00 + +08004e44 : +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + 8004e44: b480 push {r7} + 8004e46: b087 sub sp, #28 + 8004e48: af00 add r7, sp, #0 + 8004e4a: 6078 str r0, [r7, #4] + if(htim_base->Instance==TIM3) + 8004e4c: 687b ldr r3, [r7, #4] + 8004e4e: 681b ldr r3, [r3, #0] + 8004e50: 4a1c ldr r2, [pc, #112] ; (8004ec4 ) + 8004e52: 4293 cmp r3, r2 + 8004e54: d10c bne.n 8004e70 + { + /* USER CODE BEGIN TIM3_MspInit 0 */ + + /* USER CODE END TIM3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM3_CLK_ENABLE(); + 8004e56: 4b1c ldr r3, [pc, #112] ; (8004ec8 ) + 8004e58: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004e5a: 4a1b ldr r2, [pc, #108] ; (8004ec8 ) + 8004e5c: f043 0302 orr.w r3, r3, #2 + 8004e60: 6413 str r3, [r2, #64] ; 0x40 + 8004e62: 4b19 ldr r3, [pc, #100] ; (8004ec8 ) + 8004e64: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004e66: f003 0302 and.w r3, r3, #2 + 8004e6a: 617b str r3, [r7, #20] + 8004e6c: 697b ldr r3, [r7, #20] + /* USER CODE BEGIN TIM6_MspInit 1 */ + + /* USER CODE END TIM6_MspInit 1 */ + } + +} + 8004e6e: e022 b.n 8004eb6 + else if(htim_base->Instance==TIM4) + 8004e70: 687b ldr r3, [r7, #4] + 8004e72: 681b ldr r3, [r3, #0] + 8004e74: 4a15 ldr r2, [pc, #84] ; (8004ecc ) + 8004e76: 4293 cmp r3, r2 + 8004e78: d10c bne.n 8004e94 + __HAL_RCC_TIM4_CLK_ENABLE(); + 8004e7a: 4b13 ldr r3, [pc, #76] ; (8004ec8 ) + 8004e7c: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004e7e: 4a12 ldr r2, [pc, #72] ; (8004ec8 ) + 8004e80: f043 0304 orr.w r3, r3, #4 + 8004e84: 6413 str r3, [r2, #64] ; 0x40 + 8004e86: 4b10 ldr r3, [pc, #64] ; (8004ec8 ) + 8004e88: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004e8a: f003 0304 and.w r3, r3, #4 + 8004e8e: 613b str r3, [r7, #16] + 8004e90: 693b ldr r3, [r7, #16] +} + 8004e92: e010 b.n 8004eb6 + else if(htim_base->Instance==TIM6) + 8004e94: 687b ldr r3, [r7, #4] + 8004e96: 681b ldr r3, [r3, #0] + 8004e98: 4a0d ldr r2, [pc, #52] ; (8004ed0 ) + 8004e9a: 4293 cmp r3, r2 + 8004e9c: d10b bne.n 8004eb6 + __HAL_RCC_TIM6_CLK_ENABLE(); + 8004e9e: 4b0a ldr r3, [pc, #40] ; (8004ec8 ) + 8004ea0: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004ea2: 4a09 ldr r2, [pc, #36] ; (8004ec8 ) + 8004ea4: f043 0310 orr.w r3, r3, #16 + 8004ea8: 6413 str r3, [r2, #64] ; 0x40 + 8004eaa: 4b07 ldr r3, [pc, #28] ; (8004ec8 ) + 8004eac: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004eae: f003 0310 and.w r3, r3, #16 + 8004eb2: 60fb str r3, [r7, #12] + 8004eb4: 68fb ldr r3, [r7, #12] +} + 8004eb6: bf00 nop + 8004eb8: 371c adds r7, #28 + 8004eba: 46bd mov sp, r7 + 8004ebc: f85d 7b04 ldr.w r7, [sp], #4 + 8004ec0: 4770 bx lr + 8004ec2: bf00 nop + 8004ec4: 40000400 .word 0x40000400 + 8004ec8: 40023800 .word 0x40023800 + 8004ecc: 40000800 .word 0x40000800 + 8004ed0: 40001000 .word 0x40001000 + +08004ed4 : + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + 8004ed4: b580 push {r7, lr} + 8004ed6: b088 sub sp, #32 + 8004ed8: af00 add r7, sp, #0 + 8004eda: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8004edc: f107 030c add.w r3, r7, #12 + 8004ee0: 2200 movs r2, #0 + 8004ee2: 601a str r2, [r3, #0] + 8004ee4: 605a str r2, [r3, #4] + 8004ee6: 609a str r2, [r3, #8] + 8004ee8: 60da str r2, [r3, #12] + 8004eea: 611a str r2, [r3, #16] + if(htim->Instance==TIM4) + 8004eec: 687b ldr r3, [r7, #4] + 8004eee: 681b ldr r3, [r3, #0] + 8004ef0: 4a11 ldr r2, [pc, #68] ; (8004f38 ) + 8004ef2: 4293 cmp r3, r2 + 8004ef4: d11c bne.n 8004f30 + { + /* USER CODE BEGIN TIM4_MspPostInit 0 */ + + /* USER CODE END TIM4_MspPostInit 0 */ + + __HAL_RCC_GPIOD_CLK_ENABLE(); + 8004ef6: 4b11 ldr r3, [pc, #68] ; (8004f3c ) + 8004ef8: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004efa: 4a10 ldr r2, [pc, #64] ; (8004f3c ) + 8004efc: f043 0308 orr.w r3, r3, #8 + 8004f00: 6313 str r3, [r2, #48] ; 0x30 + 8004f02: 4b0e ldr r3, [pc, #56] ; (8004f3c ) + 8004f04: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004f06: f003 0308 and.w r3, r3, #8 + 8004f0a: 60bb str r3, [r7, #8] + 8004f0c: 68bb ldr r3, [r7, #8] + /**TIM4 GPIO Configuration + PD14 ------> TIM4_CH3 + PD15 ------> TIM4_CH4 + */ + GPIO_InitStruct.Pin = pwm2_Pin|pwm1_Pin; + 8004f0e: f44f 4340 mov.w r3, #49152 ; 0xc000 + 8004f12: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8004f14: 2302 movs r3, #2 + 8004f16: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8004f18: 2300 movs r3, #0 + 8004f1a: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8004f1c: 2300 movs r3, #0 + 8004f1e: 61bb str r3, [r7, #24] + GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; + 8004f20: 2302 movs r3, #2 + 8004f22: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 8004f24: f107 030c add.w r3, r7, #12 + 8004f28: 4619 mov r1, r3 + 8004f2a: 4805 ldr r0, [pc, #20] ; (8004f40 ) + 8004f2c: f000 fa92 bl 8005454 + /* USER CODE BEGIN TIM4_MspPostInit 1 */ + + /* USER CODE END TIM4_MspPostInit 1 */ + } + +} + 8004f30: bf00 nop + 8004f32: 3720 adds r7, #32 + 8004f34: 46bd mov sp, r7 + 8004f36: bd80 pop {r7, pc} + 8004f38: 40000800 .word 0x40000800 + 8004f3c: 40023800 .word 0x40023800 + 8004f40: 40020c00 .word 0x40020c00 + +08004f44 : +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + 8004f44: b580 push {r7, lr} + 8004f46: b08a sub sp, #40 ; 0x28 + 8004f48: af00 add r7, sp, #0 + 8004f4a: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8004f4c: f107 0314 add.w r3, r7, #20 + 8004f50: 2200 movs r2, #0 + 8004f52: 601a str r2, [r3, #0] + 8004f54: 605a str r2, [r3, #4] + 8004f56: 609a str r2, [r3, #8] + 8004f58: 60da str r2, [r3, #12] + 8004f5a: 611a str r2, [r3, #16] + if(huart->Instance==USART6) + 8004f5c: 687b ldr r3, [r7, #4] + 8004f5e: 681b ldr r3, [r3, #0] + 8004f60: 4a17 ldr r2, [pc, #92] ; (8004fc0 ) + 8004f62: 4293 cmp r3, r2 + 8004f64: d127 bne.n 8004fb6 + { + /* USER CODE BEGIN USART6_MspInit 0 */ + + /* USER CODE END USART6_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART6_CLK_ENABLE(); + 8004f66: 4b17 ldr r3, [pc, #92] ; (8004fc4 ) + 8004f68: 6c5b ldr r3, [r3, #68] ; 0x44 + 8004f6a: 4a16 ldr r2, [pc, #88] ; (8004fc4 ) + 8004f6c: f043 0320 orr.w r3, r3, #32 + 8004f70: 6453 str r3, [r2, #68] ; 0x44 + 8004f72: 4b14 ldr r3, [pc, #80] ; (8004fc4 ) + 8004f74: 6c5b ldr r3, [r3, #68] ; 0x44 + 8004f76: f003 0320 and.w r3, r3, #32 + 8004f7a: 613b str r3, [r7, #16] + 8004f7c: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8004f7e: 4b11 ldr r3, [pc, #68] ; (8004fc4 ) + 8004f80: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004f82: 4a10 ldr r2, [pc, #64] ; (8004fc4 ) + 8004f84: f043 0304 orr.w r3, r3, #4 + 8004f88: 6313 str r3, [r2, #48] ; 0x30 + 8004f8a: 4b0e ldr r3, [pc, #56] ; (8004fc4 ) + 8004f8c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004f8e: f003 0304 and.w r3, r3, #4 + 8004f92: 60fb str r3, [r7, #12] + 8004f94: 68fb ldr r3, [r7, #12] + /**USART6 GPIO Configuration + PC6 ------> USART6_TX + PC7 ------> USART6_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + 8004f96: 23c0 movs r3, #192 ; 0xc0 + 8004f98: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8004f9a: 2302 movs r3, #2 + 8004f9c: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8004f9e: 2300 movs r3, #0 + 8004fa0: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8004fa2: 2303 movs r3, #3 + 8004fa4: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF8_USART6; + 8004fa6: 2308 movs r3, #8 + 8004fa8: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 8004faa: f107 0314 add.w r3, r7, #20 + 8004fae: 4619 mov r1, r3 + 8004fb0: 4805 ldr r0, [pc, #20] ; (8004fc8 ) + 8004fb2: f000 fa4f bl 8005454 + /* USER CODE BEGIN USART6_MspInit 1 */ + + /* USER CODE END USART6_MspInit 1 */ + } + +} + 8004fb6: bf00 nop + 8004fb8: 3728 adds r7, #40 ; 0x28 + 8004fba: 46bd mov sp, r7 + 8004fbc: bd80 pop {r7, pc} + 8004fbe: bf00 nop + 8004fc0: 40011400 .word 0x40011400 + 8004fc4: 40023800 .word 0x40023800 + 8004fc8: 40020800 .word 0x40020800 + +08004fcc : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 8004fcc: b480 push {r7} + 8004fce: af00 add r7, sp, #0 + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + 8004fd0: bf00 nop + 8004fd2: 46bd mov sp, r7 + 8004fd4: f85d 7b04 ldr.w r7, [sp], #4 + 8004fd8: 4770 bx lr + +08004fda : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 8004fda: b480 push {r7} + 8004fdc: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8004fde: e7fe b.n 8004fde + +08004fe0 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 8004fe0: b480 push {r7} + 8004fe2: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 8004fe4: e7fe b.n 8004fe4 + +08004fe6 : + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 8004fe6: b480 push {r7} + 8004fe8: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 8004fea: e7fe b.n 8004fea + +08004fec : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 8004fec: b480 push {r7} + 8004fee: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8004ff0: e7fe b.n 8004ff0 + +08004ff2 : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 8004ff2: b480 push {r7} + 8004ff4: af00 add r7, sp, #0 + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + 8004ff6: bf00 nop + 8004ff8: 46bd mov sp, r7 + 8004ffa: f85d 7b04 ldr.w r7, [sp], #4 + 8004ffe: 4770 bx lr + +08005000 : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 8005000: b480 push {r7} + 8005002: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 8005004: bf00 nop + 8005006: 46bd mov sp, r7 + 8005008: f85d 7b04 ldr.w r7, [sp], #4 + 800500c: 4770 bx lr + +0800500e : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 800500e: b480 push {r7} + 8005010: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8005012: bf00 nop + 8005014: 46bd mov sp, r7 + 8005016: f85d 7b04 ldr.w r7, [sp], #4 + 800501a: 4770 bx lr + +0800501c : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 800501c: b580 push {r7, lr} + 800501e: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 8005020: f000 f8c4 bl 80051ac + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8005024: bf00 nop + 8005026: bd80 pop {r7, pc} + +08005028 : + +/** + * @brief This function handles TIM3 global interrupt. + */ +void TIM3_IRQHandler(void) +{ + 8005028: b580 push {r7, lr} + 800502a: af00 add r7, sp, #0 + /* USER CODE BEGIN TIM3_IRQn 0 */ + + /* USER CODE END TIM3_IRQn 0 */ + HAL_TIM_IRQHandler(&htim3); + 800502c: 4802 ldr r0, [pc, #8] ; (8005038 ) + 800502e: f001 fdec bl 8006c0a + /* USER CODE BEGIN TIM3_IRQn 1 */ + + /* USER CODE END TIM3_IRQn 1 */ +} + 8005032: bf00 nop + 8005034: bd80 pop {r7, pc} + 8005036: bf00 nop + 8005038: 2000006c .word 0x2000006c + +0800503c : + +/** + * @brief This function handles EXTI line[15:10] interrupts. + */ +void EXTI15_10_IRQHandler(void) +{ + 800503c: b580 push {r7, lr} + 800503e: af00 add r7, sp, #0 + /* USER CODE BEGIN EXTI15_10_IRQn 0 */ + + /* USER CODE END EXTI15_10_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13); + 8005040: f44f 5000 mov.w r0, #8192 ; 0x2000 + 8005044: f000 fbca bl 80057dc + /* USER CODE BEGIN EXTI15_10_IRQn 1 */ + + /* USER CODE END EXTI15_10_IRQn 1 */ +} + 8005048: bf00 nop + 800504a: bd80 pop {r7, pc} + +0800504c : + +/** + * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts. + */ +void TIM6_DAC_IRQHandler(void) +{ + 800504c: b580 push {r7, lr} + 800504e: af00 add r7, sp, #0 + /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ + + /* USER CODE END TIM6_DAC_IRQn 0 */ + HAL_TIM_IRQHandler(&htim6); + 8005050: 4802 ldr r0, [pc, #8] ; (800505c ) + 8005052: f001 fdda bl 8006c0a + /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ + + /* USER CODE END TIM6_DAC_IRQn 1 */ +} + 8005056: bf00 nop + 8005058: bd80 pop {r7, pc} + 800505a: bf00 nop + 800505c: 2000012c .word 0x2000012c + +08005060 : + +/** + * @brief This function handles USART6 global interrupt. + */ +void USART6_IRQHandler(void) +{ + 8005060: b580 push {r7, lr} + 8005062: af00 add r7, sp, #0 + /* USER CODE BEGIN USART6_IRQn 0 */ + + /* USER CODE END USART6_IRQn 0 */ + HAL_UART_IRQHandler(&huart6); + 8005064: 4802 ldr r0, [pc, #8] ; (8005070 ) + 8005066: f002 fea3 bl 8007db0 + /* USER CODE BEGIN USART6_IRQn 1 */ + + /* USER CODE END USART6_IRQn 1 */ +} + 800506a: bf00 nop + 800506c: bd80 pop {r7, pc} + 800506e: bf00 nop + 8005070: 2000016c .word 0x2000016c + +08005074 : + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + 8005074: b480 push {r7} + 8005076: af00 add r7, sp, #0 + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + 8005078: 4b15 ldr r3, [pc, #84] ; (80050d0 ) + 800507a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800507e: 4a14 ldr r2, [pc, #80] ; (80050d0 ) + 8005080: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 + 8005084: f8c2 3088 str.w r3, [r2, #136] ; 0x88 + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + 8005088: 4b12 ldr r3, [pc, #72] ; (80050d4 ) + 800508a: 681b ldr r3, [r3, #0] + 800508c: 4a11 ldr r2, [pc, #68] ; (80050d4 ) + 800508e: f043 0301 orr.w r3, r3, #1 + 8005092: 6013 str r3, [r2, #0] + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + 8005094: 4b0f ldr r3, [pc, #60] ; (80050d4 ) + 8005096: 2200 movs r2, #0 + 8005098: 609a str r2, [r3, #8] + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + 800509a: 4b0e ldr r3, [pc, #56] ; (80050d4 ) + 800509c: 681a ldr r2, [r3, #0] + 800509e: 490d ldr r1, [pc, #52] ; (80050d4 ) + 80050a0: 4b0d ldr r3, [pc, #52] ; (80050d8 ) + 80050a2: 4013 ands r3, r2 + 80050a4: 600b str r3, [r1, #0] + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + 80050a6: 4b0b ldr r3, [pc, #44] ; (80050d4 ) + 80050a8: 4a0c ldr r2, [pc, #48] ; (80050dc ) + 80050aa: 605a str r2, [r3, #4] + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + 80050ac: 4b09 ldr r3, [pc, #36] ; (80050d4 ) + 80050ae: 681b ldr r3, [r3, #0] + 80050b0: 4a08 ldr r2, [pc, #32] ; (80050d4 ) + 80050b2: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 80050b6: 6013 str r3, [r2, #0] + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + 80050b8: 4b06 ldr r3, [pc, #24] ; (80050d4 ) + 80050ba: 2200 movs r2, #0 + 80050bc: 60da str r2, [r3, #12] + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + 80050be: 4b04 ldr r3, [pc, #16] ; (80050d0 ) + 80050c0: f04f 6200 mov.w r2, #134217728 ; 0x8000000 + 80050c4: 609a str r2, [r3, #8] +#endif +} + 80050c6: bf00 nop + 80050c8: 46bd mov sp, r7 + 80050ca: f85d 7b04 ldr.w r7, [sp], #4 + 80050ce: 4770 bx lr + 80050d0: e000ed00 .word 0xe000ed00 + 80050d4: 40023800 .word 0x40023800 + 80050d8: fef6ffff .word 0xfef6ffff + 80050dc: 24003010 .word 0x24003010 + +080050e0 : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + 80050e0: f8df d034 ldr.w sp, [pc, #52] ; 8005118 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + 80050e4: 2100 movs r1, #0 + b LoopCopyDataInit + 80050e6: e003 b.n 80050f0 + +080050e8 : + +CopyDataInit: + ldr r3, =_sidata + 80050e8: 4b0c ldr r3, [pc, #48] ; (800511c ) + ldr r3, [r3, r1] + 80050ea: 585b ldr r3, [r3, r1] + str r3, [r0, r1] + 80050ec: 5043 str r3, [r0, r1] + adds r1, r1, #4 + 80050ee: 3104 adds r1, #4 + +080050f0 : + +LoopCopyDataInit: + ldr r0, =_sdata + 80050f0: 480b ldr r0, [pc, #44] ; (8005120 ) + ldr r3, =_edata + 80050f2: 4b0c ldr r3, [pc, #48] ; (8005124 ) + adds r2, r0, r1 + 80050f4: 1842 adds r2, r0, r1 + cmp r2, r3 + 80050f6: 429a cmp r2, r3 + bcc CopyDataInit + 80050f8: d3f6 bcc.n 80050e8 + ldr r2, =_sbss + 80050fa: 4a0b ldr r2, [pc, #44] ; (8005128 ) + b LoopFillZerobss + 80050fc: e002 b.n 8005104 + +080050fe : +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + 80050fe: 2300 movs r3, #0 + str r3, [r2], #4 + 8005100: f842 3b04 str.w r3, [r2], #4 + +08005104 : + +LoopFillZerobss: + ldr r3, = _ebss + 8005104: 4b09 ldr r3, [pc, #36] ; (800512c ) + cmp r2, r3 + 8005106: 429a cmp r2, r3 + bcc FillZerobss + 8005108: d3f9 bcc.n 80050fe + +/* Call the clock system initialization function.*/ + bl SystemInit + 800510a: f7ff ffb3 bl 8005074 +/* Call static constructors */ + bl __libc_init_array + 800510e: f003 fc31 bl 8008974 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 8005112: f7fb fdc9 bl 8000ca8
+ bx lr + 8005116: 4770 bx lr + ldr sp, =_estack /* set stack pointer */ + 8005118: 20080000 .word 0x20080000 + ldr r3, =_sidata + 800511c: 08008cf8 .word 0x08008cf8 + ldr r0, =_sdata + 8005120: 20000000 .word 0x20000000 + ldr r3, =_edata + 8005124: 20000010 .word 0x20000010 + ldr r2, =_sbss + 8005128: 20000010 .word 0x20000010 + ldr r3, = _ebss + 800512c: 20000348 .word 0x20000348 + +08005130 : + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8005130: e7fe b.n 8005130 + +08005132 : + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8005132: b580 push {r7, lr} + 8005134: af00 add r7, sp, #0 +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8005136: 2003 movs r0, #3 + 8005138: f000 f928 bl 800538c + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + 800513c: 2000 movs r0, #0 + 800513e: f000 f805 bl 800514c + + /* Init the low level hardware */ + HAL_MspInit(); + 8005142: f7ff fdcb bl 8004cdc + + /* Return function status */ + return HAL_OK; + 8005146: 2300 movs r3, #0 +} + 8005148: 4618 mov r0, r3 + 800514a: bd80 pop {r7, pc} + +0800514c : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 800514c: b580 push {r7, lr} + 800514e: b082 sub sp, #8 + 8005150: af00 add r7, sp, #0 + 8005152: 6078 str r0, [r7, #4] + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + 8005154: 4b12 ldr r3, [pc, #72] ; (80051a0 ) + 8005156: 681a ldr r2, [r3, #0] + 8005158: 4b12 ldr r3, [pc, #72] ; (80051a4 ) + 800515a: 781b ldrb r3, [r3, #0] + 800515c: 4619 mov r1, r3 + 800515e: f44f 737a mov.w r3, #1000 ; 0x3e8 + 8005162: fbb3 f3f1 udiv r3, r3, r1 + 8005166: fbb2 f3f3 udiv r3, r2, r3 + 800516a: 4618 mov r0, r3 + 800516c: f000 f943 bl 80053f6 + 8005170: 4603 mov r3, r0 + 8005172: 2b00 cmp r3, #0 + 8005174: d001 beq.n 800517a + { + return HAL_ERROR; + 8005176: 2301 movs r3, #1 + 8005178: e00e b.n 8005198 + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 800517a: 687b ldr r3, [r7, #4] + 800517c: 2b0f cmp r3, #15 + 800517e: d80a bhi.n 8005196 + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8005180: 2200 movs r2, #0 + 8005182: 6879 ldr r1, [r7, #4] + 8005184: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8005188: f000 f90b bl 80053a2 + uwTickPrio = TickPriority; + 800518c: 4a06 ldr r2, [pc, #24] ; (80051a8 ) + 800518e: 687b ldr r3, [r7, #4] + 8005190: 6013 str r3, [r2, #0] + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; + 8005192: 2300 movs r3, #0 + 8005194: e000 b.n 8005198 + return HAL_ERROR; + 8005196: 2301 movs r3, #1 +} + 8005198: 4618 mov r0, r3 + 800519a: 3708 adds r7, #8 + 800519c: 46bd mov sp, r7 + 800519e: bd80 pop {r7, pc} + 80051a0: 20000004 .word 0x20000004 + 80051a4: 2000000c .word 0x2000000c + 80051a8: 20000008 .word 0x20000008 + +080051ac : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 80051ac: b480 push {r7} + 80051ae: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 80051b0: 4b06 ldr r3, [pc, #24] ; (80051cc ) + 80051b2: 781b ldrb r3, [r3, #0] + 80051b4: 461a mov r2, r3 + 80051b6: 4b06 ldr r3, [pc, #24] ; (80051d0 ) + 80051b8: 681b ldr r3, [r3, #0] + 80051ba: 4413 add r3, r2 + 80051bc: 4a04 ldr r2, [pc, #16] ; (80051d0 ) + 80051be: 6013 str r3, [r2, #0] +} + 80051c0: bf00 nop + 80051c2: 46bd mov sp, r7 + 80051c4: f85d 7b04 ldr.w r7, [sp], #4 + 80051c8: 4770 bx lr + 80051ca: bf00 nop + 80051cc: 2000000c .word 0x2000000c + 80051d0: 20000344 .word 0x20000344 + +080051d4 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 80051d4: b480 push {r7} + 80051d6: af00 add r7, sp, #0 + return uwTick; + 80051d8: 4b03 ldr r3, [pc, #12] ; (80051e8 ) + 80051da: 681b ldr r3, [r3, #0] +} + 80051dc: 4618 mov r0, r3 + 80051de: 46bd mov sp, r7 + 80051e0: f85d 7b04 ldr.w r7, [sp], #4 + 80051e4: 4770 bx lr + 80051e6: bf00 nop + 80051e8: 20000344 .word 0x20000344 + +080051ec <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 80051ec: b480 push {r7} + 80051ee: b085 sub sp, #20 + 80051f0: af00 add r7, sp, #0 + 80051f2: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 80051f4: 687b ldr r3, [r7, #4] + 80051f6: f003 0307 and.w r3, r3, #7 + 80051fa: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 80051fc: 4b0b ldr r3, [pc, #44] ; (800522c <__NVIC_SetPriorityGrouping+0x40>) + 80051fe: 68db ldr r3, [r3, #12] + 8005200: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8005202: 68ba ldr r2, [r7, #8] + 8005204: f64f 03ff movw r3, #63743 ; 0xf8ff + 8005208: 4013 ands r3, r2 + 800520a: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 800520c: 68fb ldr r3, [r7, #12] + 800520e: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8005210: 68bb ldr r3, [r7, #8] + 8005212: 431a orrs r2, r3 + reg_value = (reg_value | + 8005214: 4b06 ldr r3, [pc, #24] ; (8005230 <__NVIC_SetPriorityGrouping+0x44>) + 8005216: 4313 orrs r3, r2 + 8005218: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 800521a: 4a04 ldr r2, [pc, #16] ; (800522c <__NVIC_SetPriorityGrouping+0x40>) + 800521c: 68bb ldr r3, [r7, #8] + 800521e: 60d3 str r3, [r2, #12] +} + 8005220: bf00 nop + 8005222: 3714 adds r7, #20 + 8005224: 46bd mov sp, r7 + 8005226: f85d 7b04 ldr.w r7, [sp], #4 + 800522a: 4770 bx lr + 800522c: e000ed00 .word 0xe000ed00 + 8005230: 05fa0000 .word 0x05fa0000 + +08005234 <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 8005234: b480 push {r7} + 8005236: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8005238: 4b04 ldr r3, [pc, #16] ; (800524c <__NVIC_GetPriorityGrouping+0x18>) + 800523a: 68db ldr r3, [r3, #12] + 800523c: 0a1b lsrs r3, r3, #8 + 800523e: f003 0307 and.w r3, r3, #7 +} + 8005242: 4618 mov r0, r3 + 8005244: 46bd mov sp, r7 + 8005246: f85d 7b04 ldr.w r7, [sp], #4 + 800524a: 4770 bx lr + 800524c: e000ed00 .word 0xe000ed00 + +08005250 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8005250: b480 push {r7} + 8005252: b083 sub sp, #12 + 8005254: af00 add r7, sp, #0 + 8005256: 4603 mov r3, r0 + 8005258: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 800525a: f997 3007 ldrsb.w r3, [r7, #7] + 800525e: 2b00 cmp r3, #0 + 8005260: db0b blt.n 800527a <__NVIC_EnableIRQ+0x2a> + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8005262: 79fb ldrb r3, [r7, #7] + 8005264: f003 021f and.w r2, r3, #31 + 8005268: 4907 ldr r1, [pc, #28] ; (8005288 <__NVIC_EnableIRQ+0x38>) + 800526a: f997 3007 ldrsb.w r3, [r7, #7] + 800526e: 095b lsrs r3, r3, #5 + 8005270: 2001 movs r0, #1 + 8005272: fa00 f202 lsl.w r2, r0, r2 + 8005276: f841 2023 str.w r2, [r1, r3, lsl #2] + } +} + 800527a: bf00 nop + 800527c: 370c adds r7, #12 + 800527e: 46bd mov sp, r7 + 8005280: f85d 7b04 ldr.w r7, [sp], #4 + 8005284: 4770 bx lr + 8005286: bf00 nop + 8005288: e000e100 .word 0xe000e100 + +0800528c <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 800528c: b480 push {r7} + 800528e: b083 sub sp, #12 + 8005290: af00 add r7, sp, #0 + 8005292: 4603 mov r3, r0 + 8005294: 6039 str r1, [r7, #0] + 8005296: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8005298: f997 3007 ldrsb.w r3, [r7, #7] + 800529c: 2b00 cmp r3, #0 + 800529e: db0a blt.n 80052b6 <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 80052a0: 683b ldr r3, [r7, #0] + 80052a2: b2da uxtb r2, r3 + 80052a4: 490c ldr r1, [pc, #48] ; (80052d8 <__NVIC_SetPriority+0x4c>) + 80052a6: f997 3007 ldrsb.w r3, [r7, #7] + 80052aa: 0112 lsls r2, r2, #4 + 80052ac: b2d2 uxtb r2, r2 + 80052ae: 440b add r3, r1 + 80052b0: f883 2300 strb.w r2, [r3, #768] ; 0x300 + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 80052b4: e00a b.n 80052cc <__NVIC_SetPriority+0x40> + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 80052b6: 683b ldr r3, [r7, #0] + 80052b8: b2da uxtb r2, r3 + 80052ba: 4908 ldr r1, [pc, #32] ; (80052dc <__NVIC_SetPriority+0x50>) + 80052bc: 79fb ldrb r3, [r7, #7] + 80052be: f003 030f and.w r3, r3, #15 + 80052c2: 3b04 subs r3, #4 + 80052c4: 0112 lsls r2, r2, #4 + 80052c6: b2d2 uxtb r2, r2 + 80052c8: 440b add r3, r1 + 80052ca: 761a strb r2, [r3, #24] +} + 80052cc: bf00 nop + 80052ce: 370c adds r7, #12 + 80052d0: 46bd mov sp, r7 + 80052d2: f85d 7b04 ldr.w r7, [sp], #4 + 80052d6: 4770 bx lr + 80052d8: e000e100 .word 0xe000e100 + 80052dc: e000ed00 .word 0xe000ed00 + +080052e0 : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 80052e0: b480 push {r7} + 80052e2: b089 sub sp, #36 ; 0x24 + 80052e4: af00 add r7, sp, #0 + 80052e6: 60f8 str r0, [r7, #12] + 80052e8: 60b9 str r1, [r7, #8] + 80052ea: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 80052ec: 68fb ldr r3, [r7, #12] + 80052ee: f003 0307 and.w r3, r3, #7 + 80052f2: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 80052f4: 69fb ldr r3, [r7, #28] + 80052f6: f1c3 0307 rsb r3, r3, #7 + 80052fa: 2b04 cmp r3, #4 + 80052fc: bf28 it cs + 80052fe: 2304 movcs r3, #4 + 8005300: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8005302: 69fb ldr r3, [r7, #28] + 8005304: 3304 adds r3, #4 + 8005306: 2b06 cmp r3, #6 + 8005308: d902 bls.n 8005310 + 800530a: 69fb ldr r3, [r7, #28] + 800530c: 3b03 subs r3, #3 + 800530e: e000 b.n 8005312 + 8005310: 2300 movs r3, #0 + 8005312: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8005314: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 8005318: 69bb ldr r3, [r7, #24] + 800531a: fa02 f303 lsl.w r3, r2, r3 + 800531e: 43da mvns r2, r3 + 8005320: 68bb ldr r3, [r7, #8] + 8005322: 401a ands r2, r3 + 8005324: 697b ldr r3, [r7, #20] + 8005326: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8005328: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff + 800532c: 697b ldr r3, [r7, #20] + 800532e: fa01 f303 lsl.w r3, r1, r3 + 8005332: 43d9 mvns r1, r3 + 8005334: 687b ldr r3, [r7, #4] + 8005336: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8005338: 4313 orrs r3, r2 + ); +} + 800533a: 4618 mov r0, r3 + 800533c: 3724 adds r7, #36 ; 0x24 + 800533e: 46bd mov sp, r7 + 8005340: f85d 7b04 ldr.w r7, [sp], #4 + 8005344: 4770 bx lr + ... + +08005348 : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8005348: b580 push {r7, lr} + 800534a: b082 sub sp, #8 + 800534c: af00 add r7, sp, #0 + 800534e: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8005350: 687b ldr r3, [r7, #4] + 8005352: 3b01 subs r3, #1 + 8005354: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 + 8005358: d301 bcc.n 800535e + { + return (1UL); /* Reload value impossible */ + 800535a: 2301 movs r3, #1 + 800535c: e00f b.n 800537e + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 800535e: 4a0a ldr r2, [pc, #40] ; (8005388 ) + 8005360: 687b ldr r3, [r7, #4] + 8005362: 3b01 subs r3, #1 + 8005364: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 8005366: 210f movs r1, #15 + 8005368: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 800536c: f7ff ff8e bl 800528c <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8005370: 4b05 ldr r3, [pc, #20] ; (8005388 ) + 8005372: 2200 movs r2, #0 + 8005374: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8005376: 4b04 ldr r3, [pc, #16] ; (8005388 ) + 8005378: 2207 movs r2, #7 + 800537a: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 800537c: 2300 movs r3, #0 +} + 800537e: 4618 mov r0, r3 + 8005380: 3708 adds r7, #8 + 8005382: 46bd mov sp, r7 + 8005384: bd80 pop {r7, pc} + 8005386: bf00 nop + 8005388: e000e010 .word 0xe000e010 + +0800538c : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 800538c: b580 push {r7, lr} + 800538e: b082 sub sp, #8 + 8005390: af00 add r7, sp, #0 + 8005392: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8005394: 6878 ldr r0, [r7, #4] + 8005396: f7ff ff29 bl 80051ec <__NVIC_SetPriorityGrouping> +} + 800539a: bf00 nop + 800539c: 3708 adds r7, #8 + 800539e: 46bd mov sp, r7 + 80053a0: bd80 pop {r7, pc} + +080053a2 : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 80053a2: b580 push {r7, lr} + 80053a4: b086 sub sp, #24 + 80053a6: af00 add r7, sp, #0 + 80053a8: 4603 mov r3, r0 + 80053aa: 60b9 str r1, [r7, #8] + 80053ac: 607a str r2, [r7, #4] + 80053ae: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00; + 80053b0: 2300 movs r3, #0 + 80053b2: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 80053b4: f7ff ff3e bl 8005234 <__NVIC_GetPriorityGrouping> + 80053b8: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 80053ba: 687a ldr r2, [r7, #4] + 80053bc: 68b9 ldr r1, [r7, #8] + 80053be: 6978 ldr r0, [r7, #20] + 80053c0: f7ff ff8e bl 80052e0 + 80053c4: 4602 mov r2, r0 + 80053c6: f997 300f ldrsb.w r3, [r7, #15] + 80053ca: 4611 mov r1, r2 + 80053cc: 4618 mov r0, r3 + 80053ce: f7ff ff5d bl 800528c <__NVIC_SetPriority> +} + 80053d2: bf00 nop + 80053d4: 3718 adds r7, #24 + 80053d6: 46bd mov sp, r7 + 80053d8: bd80 pop {r7, pc} + +080053da : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 80053da: b580 push {r7, lr} + 80053dc: b082 sub sp, #8 + 80053de: af00 add r7, sp, #0 + 80053e0: 4603 mov r3, r0 + 80053e2: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 80053e4: f997 3007 ldrsb.w r3, [r7, #7] + 80053e8: 4618 mov r0, r3 + 80053ea: f7ff ff31 bl 8005250 <__NVIC_EnableIRQ> +} + 80053ee: bf00 nop + 80053f0: 3708 adds r7, #8 + 80053f2: 46bd mov sp, r7 + 80053f4: bd80 pop {r7, pc} + +080053f6 : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 80053f6: b580 push {r7, lr} + 80053f8: b082 sub sp, #8 + 80053fa: af00 add r7, sp, #0 + 80053fc: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 80053fe: 6878 ldr r0, [r7, #4] + 8005400: f7ff ffa2 bl 8005348 + 8005404: 4603 mov r3, r0 +} + 8005406: 4618 mov r0, r3 + 8005408: 3708 adds r7, #8 + 800540a: 46bd mov sp, r7 + 800540c: bd80 pop {r7, pc} + +0800540e : + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + 800540e: b480 push {r7} + 8005410: b083 sub sp, #12 + 8005412: af00 add r7, sp, #0 + 8005414: 6078 str r0, [r7, #4] + if(hdma->State != HAL_DMA_STATE_BUSY) + 8005416: 687b ldr r3, [r7, #4] + 8005418: f893 3035 ldrb.w r3, [r3, #53] ; 0x35 + 800541c: b2db uxtb r3, r3 + 800541e: 2b02 cmp r3, #2 + 8005420: d004 beq.n 800542c + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 8005422: 687b ldr r3, [r7, #4] + 8005424: 2280 movs r2, #128 ; 0x80 + 8005426: 655a str r2, [r3, #84] ; 0x54 + return HAL_ERROR; + 8005428: 2301 movs r3, #1 + 800542a: e00c b.n 8005446 + } + else + { + /* Set Abort State */ + hdma->State = HAL_DMA_STATE_ABORT; + 800542c: 687b ldr r3, [r7, #4] + 800542e: 2205 movs r2, #5 + 8005430: f883 2035 strb.w r2, [r3, #53] ; 0x35 + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + 8005434: 687b ldr r3, [r7, #4] + 8005436: 681b ldr r3, [r3, #0] + 8005438: 681a ldr r2, [r3, #0] + 800543a: 687b ldr r3, [r7, #4] + 800543c: 681b ldr r3, [r3, #0] + 800543e: f022 0201 bic.w r2, r2, #1 + 8005442: 601a str r2, [r3, #0] + } + + return HAL_OK; + 8005444: 2300 movs r3, #0 +} + 8005446: 4618 mov r0, r3 + 8005448: 370c adds r7, #12 + 800544a: 46bd mov sp, r7 + 800544c: f85d 7b04 ldr.w r7, [sp], #4 + 8005450: 4770 bx lr + ... + +08005454 : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8005454: b480 push {r7} + 8005456: b089 sub sp, #36 ; 0x24 + 8005458: af00 add r7, sp, #0 + 800545a: 6078 str r0, [r7, #4] + 800545c: 6039 str r1, [r7, #0] + uint32_t position = 0x00; + 800545e: 2300 movs r3, #0 + 8005460: 61fb str r3, [r7, #28] + uint32_t ioposition = 0x00; + 8005462: 2300 movs r3, #0 + 8005464: 617b str r3, [r7, #20] + uint32_t iocurrent = 0x00; + 8005466: 2300 movs r3, #0 + 8005468: 613b str r3, [r7, #16] + uint32_t temp = 0x00; + 800546a: 2300 movs r3, #0 + 800546c: 61bb str r3, [r7, #24] + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + for(position = 0; position < GPIO_NUMBER; position++) + 800546e: 2300 movs r3, #0 + 8005470: 61fb str r3, [r7, #28] + 8005472: e175 b.n 8005760 + { + /* Get the IO position */ + ioposition = ((uint32_t)0x01) << position; + 8005474: 2201 movs r2, #1 + 8005476: 69fb ldr r3, [r7, #28] + 8005478: fa02 f303 lsl.w r3, r2, r3 + 800547c: 617b str r3, [r7, #20] + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + 800547e: 683b ldr r3, [r7, #0] + 8005480: 681b ldr r3, [r3, #0] + 8005482: 697a ldr r2, [r7, #20] + 8005484: 4013 ands r3, r2 + 8005486: 613b str r3, [r7, #16] + + if(iocurrent == ioposition) + 8005488: 693a ldr r2, [r7, #16] + 800548a: 697b ldr r3, [r7, #20] + 800548c: 429a cmp r2, r3 + 800548e: f040 8164 bne.w 800575a + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 8005492: 683b ldr r3, [r7, #0] + 8005494: 685b ldr r3, [r3, #4] + 8005496: 2b02 cmp r3, #2 + 8005498: d003 beq.n 80054a2 + 800549a: 683b ldr r3, [r7, #0] + 800549c: 685b ldr r3, [r3, #4] + 800549e: 2b12 cmp r3, #18 + 80054a0: d123 bne.n 80054ea + { + /* Check the Alternate function parameter */ + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3]; + 80054a2: 69fb ldr r3, [r7, #28] + 80054a4: 08da lsrs r2, r3, #3 + 80054a6: 687b ldr r3, [r7, #4] + 80054a8: 3208 adds r2, #8 + 80054aa: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80054ae: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + 80054b0: 69fb ldr r3, [r7, #28] + 80054b2: f003 0307 and.w r3, r3, #7 + 80054b6: 009b lsls r3, r3, #2 + 80054b8: 220f movs r2, #15 + 80054ba: fa02 f303 lsl.w r3, r2, r3 + 80054be: 43db mvns r3, r3 + 80054c0: 69ba ldr r2, [r7, #24] + 80054c2: 4013 ands r3, r2 + 80054c4: 61bb str r3, [r7, #24] + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); + 80054c6: 683b ldr r3, [r7, #0] + 80054c8: 691a ldr r2, [r3, #16] + 80054ca: 69fb ldr r3, [r7, #28] + 80054cc: f003 0307 and.w r3, r3, #7 + 80054d0: 009b lsls r3, r3, #2 + 80054d2: fa02 f303 lsl.w r3, r2, r3 + 80054d6: 69ba ldr r2, [r7, #24] + 80054d8: 4313 orrs r3, r2 + 80054da: 61bb str r3, [r7, #24] + GPIOx->AFR[position >> 3] = temp; + 80054dc: 69fb ldr r3, [r7, #28] + 80054de: 08da lsrs r2, r3, #3 + 80054e0: 687b ldr r3, [r7, #4] + 80054e2: 3208 adds r2, #8 + 80054e4: 69b9 ldr r1, [r7, #24] + 80054e6: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 80054ea: 687b ldr r3, [r7, #4] + 80054ec: 681b ldr r3, [r3, #0] + 80054ee: 61bb str r3, [r7, #24] + temp &= ~(GPIO_MODER_MODER0 << (position * 2)); + 80054f0: 69fb ldr r3, [r7, #28] + 80054f2: 005b lsls r3, r3, #1 + 80054f4: 2203 movs r2, #3 + 80054f6: fa02 f303 lsl.w r3, r2, r3 + 80054fa: 43db mvns r3, r3 + 80054fc: 69ba ldr r2, [r7, #24] + 80054fe: 4013 ands r3, r2 + 8005500: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 8005502: 683b ldr r3, [r7, #0] + 8005504: 685b ldr r3, [r3, #4] + 8005506: f003 0203 and.w r2, r3, #3 + 800550a: 69fb ldr r3, [r7, #28] + 800550c: 005b lsls r3, r3, #1 + 800550e: fa02 f303 lsl.w r3, r2, r3 + 8005512: 69ba ldr r2, [r7, #24] + 8005514: 4313 orrs r3, r2 + 8005516: 61bb str r3, [r7, #24] + GPIOx->MODER = temp; + 8005518: 687b ldr r3, [r7, #4] + 800551a: 69ba ldr r2, [r7, #24] + 800551c: 601a str r2, [r3, #0] + + /* In case of Output or Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 800551e: 683b ldr r3, [r7, #0] + 8005520: 685b ldr r3, [r3, #4] + 8005522: 2b01 cmp r3, #1 + 8005524: d00b beq.n 800553e + 8005526: 683b ldr r3, [r7, #0] + 8005528: 685b ldr r3, [r3, #4] + 800552a: 2b02 cmp r3, #2 + 800552c: d007 beq.n 800553e + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 800552e: 683b ldr r3, [r7, #0] + 8005530: 685b ldr r3, [r3, #4] + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 8005532: 2b11 cmp r3, #17 + 8005534: d003 beq.n 800553e + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 8005536: 683b ldr r3, [r7, #0] + 8005538: 685b ldr r3, [r3, #4] + 800553a: 2b12 cmp r3, #18 + 800553c: d130 bne.n 80055a0 + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 800553e: 687b ldr r3, [r7, #4] + 8005540: 689b ldr r3, [r3, #8] + 8005542: 61bb str r3, [r7, #24] + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + 8005544: 69fb ldr r3, [r7, #28] + 8005546: 005b lsls r3, r3, #1 + 8005548: 2203 movs r2, #3 + 800554a: fa02 f303 lsl.w r3, r2, r3 + 800554e: 43db mvns r3, r3 + 8005550: 69ba ldr r2, [r7, #24] + 8005552: 4013 ands r3, r2 + 8005554: 61bb str r3, [r7, #24] + temp |= (GPIO_Init->Speed << (position * 2)); + 8005556: 683b ldr r3, [r7, #0] + 8005558: 68da ldr r2, [r3, #12] + 800555a: 69fb ldr r3, [r7, #28] + 800555c: 005b lsls r3, r3, #1 + 800555e: fa02 f303 lsl.w r3, r2, r3 + 8005562: 69ba ldr r2, [r7, #24] + 8005564: 4313 orrs r3, r2 + 8005566: 61bb str r3, [r7, #24] + GPIOx->OSPEEDR = temp; + 8005568: 687b ldr r3, [r7, #4] + 800556a: 69ba ldr r2, [r7, #24] + 800556c: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 800556e: 687b ldr r3, [r7, #4] + 8005570: 685b ldr r3, [r3, #4] + 8005572: 61bb str r3, [r7, #24] + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + 8005574: 2201 movs r2, #1 + 8005576: 69fb ldr r3, [r7, #28] + 8005578: fa02 f303 lsl.w r3, r2, r3 + 800557c: 43db mvns r3, r3 + 800557e: 69ba ldr r2, [r7, #24] + 8005580: 4013 ands r3, r2 + 8005582: 61bb str r3, [r7, #24] + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); + 8005584: 683b ldr r3, [r7, #0] + 8005586: 685b ldr r3, [r3, #4] + 8005588: 091b lsrs r3, r3, #4 + 800558a: f003 0201 and.w r2, r3, #1 + 800558e: 69fb ldr r3, [r7, #28] + 8005590: fa02 f303 lsl.w r3, r2, r3 + 8005594: 69ba ldr r2, [r7, #24] + 8005596: 4313 orrs r3, r2 + 8005598: 61bb str r3, [r7, #24] + GPIOx->OTYPER = temp; + 800559a: 687b ldr r3, [r7, #4] + 800559c: 69ba ldr r2, [r7, #24] + 800559e: 605a str r2, [r3, #4] + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 80055a0: 687b ldr r3, [r7, #4] + 80055a2: 68db ldr r3, [r3, #12] + 80055a4: 61bb str r3, [r7, #24] + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + 80055a6: 69fb ldr r3, [r7, #28] + 80055a8: 005b lsls r3, r3, #1 + 80055aa: 2203 movs r2, #3 + 80055ac: fa02 f303 lsl.w r3, r2, r3 + 80055b0: 43db mvns r3, r3 + 80055b2: 69ba ldr r2, [r7, #24] + 80055b4: 4013 ands r3, r2 + 80055b6: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Pull) << (position * 2)); + 80055b8: 683b ldr r3, [r7, #0] + 80055ba: 689a ldr r2, [r3, #8] + 80055bc: 69fb ldr r3, [r7, #28] + 80055be: 005b lsls r3, r3, #1 + 80055c0: fa02 f303 lsl.w r3, r2, r3 + 80055c4: 69ba ldr r2, [r7, #24] + 80055c6: 4313 orrs r3, r2 + 80055c8: 61bb str r3, [r7, #24] + GPIOx->PUPDR = temp; + 80055ca: 687b ldr r3, [r7, #4] + 80055cc: 69ba ldr r2, [r7, #24] + 80055ce: 60da str r2, [r3, #12] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + 80055d0: 683b ldr r3, [r7, #0] + 80055d2: 685b ldr r3, [r3, #4] + 80055d4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 80055d8: 2b00 cmp r3, #0 + 80055da: f000 80be beq.w 800575a + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 80055de: 4b65 ldr r3, [pc, #404] ; (8005774 ) + 80055e0: 6c5b ldr r3, [r3, #68] ; 0x44 + 80055e2: 4a64 ldr r2, [pc, #400] ; (8005774 ) + 80055e4: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 80055e8: 6453 str r3, [r2, #68] ; 0x44 + 80055ea: 4b62 ldr r3, [pc, #392] ; (8005774 ) + 80055ec: 6c5b ldr r3, [r3, #68] ; 0x44 + 80055ee: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 80055f2: 60fb str r3, [r7, #12] + 80055f4: 68fb ldr r3, [r7, #12] + + temp = SYSCFG->EXTICR[position >> 2]; + 80055f6: 4a60 ldr r2, [pc, #384] ; (8005778 ) + 80055f8: 69fb ldr r3, [r7, #28] + 80055fa: 089b lsrs r3, r3, #2 + 80055fc: 3302 adds r3, #2 + 80055fe: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8005602: 61bb str r3, [r7, #24] + temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); + 8005604: 69fb ldr r3, [r7, #28] + 8005606: f003 0303 and.w r3, r3, #3 + 800560a: 009b lsls r3, r3, #2 + 800560c: 220f movs r2, #15 + 800560e: fa02 f303 lsl.w r3, r2, r3 + 8005612: 43db mvns r3, r3 + 8005614: 69ba ldr r2, [r7, #24] + 8005616: 4013 ands r3, r2 + 8005618: 61bb str r3, [r7, #24] + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 800561a: 687b ldr r3, [r7, #4] + 800561c: 4a57 ldr r2, [pc, #348] ; (800577c ) + 800561e: 4293 cmp r3, r2 + 8005620: d037 beq.n 8005692 + 8005622: 687b ldr r3, [r7, #4] + 8005624: 4a56 ldr r2, [pc, #344] ; (8005780 ) + 8005626: 4293 cmp r3, r2 + 8005628: d031 beq.n 800568e + 800562a: 687b ldr r3, [r7, #4] + 800562c: 4a55 ldr r2, [pc, #340] ; (8005784 ) + 800562e: 4293 cmp r3, r2 + 8005630: d02b beq.n 800568a + 8005632: 687b ldr r3, [r7, #4] + 8005634: 4a54 ldr r2, [pc, #336] ; (8005788 ) + 8005636: 4293 cmp r3, r2 + 8005638: d025 beq.n 8005686 + 800563a: 687b ldr r3, [r7, #4] + 800563c: 4a53 ldr r2, [pc, #332] ; (800578c ) + 800563e: 4293 cmp r3, r2 + 8005640: d01f beq.n 8005682 + 8005642: 687b ldr r3, [r7, #4] + 8005644: 4a52 ldr r2, [pc, #328] ; (8005790 ) + 8005646: 4293 cmp r3, r2 + 8005648: d019 beq.n 800567e + 800564a: 687b ldr r3, [r7, #4] + 800564c: 4a51 ldr r2, [pc, #324] ; (8005794 ) + 800564e: 4293 cmp r3, r2 + 8005650: d013 beq.n 800567a + 8005652: 687b ldr r3, [r7, #4] + 8005654: 4a50 ldr r2, [pc, #320] ; (8005798 ) + 8005656: 4293 cmp r3, r2 + 8005658: d00d beq.n 8005676 + 800565a: 687b ldr r3, [r7, #4] + 800565c: 4a4f ldr r2, [pc, #316] ; (800579c ) + 800565e: 4293 cmp r3, r2 + 8005660: d007 beq.n 8005672 + 8005662: 687b ldr r3, [r7, #4] + 8005664: 4a4e ldr r2, [pc, #312] ; (80057a0 ) + 8005666: 4293 cmp r3, r2 + 8005668: d101 bne.n 800566e + 800566a: 2309 movs r3, #9 + 800566c: e012 b.n 8005694 + 800566e: 230a movs r3, #10 + 8005670: e010 b.n 8005694 + 8005672: 2308 movs r3, #8 + 8005674: e00e b.n 8005694 + 8005676: 2307 movs r3, #7 + 8005678: e00c b.n 8005694 + 800567a: 2306 movs r3, #6 + 800567c: e00a b.n 8005694 + 800567e: 2305 movs r3, #5 + 8005680: e008 b.n 8005694 + 8005682: 2304 movs r3, #4 + 8005684: e006 b.n 8005694 + 8005686: 2303 movs r3, #3 + 8005688: e004 b.n 8005694 + 800568a: 2302 movs r3, #2 + 800568c: e002 b.n 8005694 + 800568e: 2301 movs r3, #1 + 8005690: e000 b.n 8005694 + 8005692: 2300 movs r3, #0 + 8005694: 69fa ldr r2, [r7, #28] + 8005696: f002 0203 and.w r2, r2, #3 + 800569a: 0092 lsls r2, r2, #2 + 800569c: 4093 lsls r3, r2 + 800569e: 69ba ldr r2, [r7, #24] + 80056a0: 4313 orrs r3, r2 + 80056a2: 61bb str r3, [r7, #24] + SYSCFG->EXTICR[position >> 2] = temp; + 80056a4: 4934 ldr r1, [pc, #208] ; (8005778 ) + 80056a6: 69fb ldr r3, [r7, #28] + 80056a8: 089b lsrs r3, r3, #2 + 80056aa: 3302 adds r3, #2 + 80056ac: 69ba ldr r2, [r7, #24] + 80056ae: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 80056b2: 4b3c ldr r3, [pc, #240] ; (80057a4 ) + 80056b4: 681b ldr r3, [r3, #0] + 80056b6: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 80056b8: 693b ldr r3, [r7, #16] + 80056ba: 43db mvns r3, r3 + 80056bc: 69ba ldr r2, [r7, #24] + 80056be: 4013 ands r3, r2 + 80056c0: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + 80056c2: 683b ldr r3, [r7, #0] + 80056c4: 685b ldr r3, [r3, #4] + 80056c6: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 80056ca: 2b00 cmp r3, #0 + 80056cc: d003 beq.n 80056d6 + { + temp |= iocurrent; + 80056ce: 69ba ldr r2, [r7, #24] + 80056d0: 693b ldr r3, [r7, #16] + 80056d2: 4313 orrs r3, r2 + 80056d4: 61bb str r3, [r7, #24] + } + EXTI->IMR = temp; + 80056d6: 4a33 ldr r2, [pc, #204] ; (80057a4 ) + 80056d8: 69bb ldr r3, [r7, #24] + 80056da: 6013 str r3, [r2, #0] + + temp = EXTI->EMR; + 80056dc: 4b31 ldr r3, [pc, #196] ; (80057a4 ) + 80056de: 685b ldr r3, [r3, #4] + 80056e0: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 80056e2: 693b ldr r3, [r7, #16] + 80056e4: 43db mvns r3, r3 + 80056e6: 69ba ldr r2, [r7, #24] + 80056e8: 4013 ands r3, r2 + 80056ea: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + 80056ec: 683b ldr r3, [r7, #0] + 80056ee: 685b ldr r3, [r3, #4] + 80056f0: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80056f4: 2b00 cmp r3, #0 + 80056f6: d003 beq.n 8005700 + { + temp |= iocurrent; + 80056f8: 69ba ldr r2, [r7, #24] + 80056fa: 693b ldr r3, [r7, #16] + 80056fc: 4313 orrs r3, r2 + 80056fe: 61bb str r3, [r7, #24] + } + EXTI->EMR = temp; + 8005700: 4a28 ldr r2, [pc, #160] ; (80057a4 ) + 8005702: 69bb ldr r3, [r7, #24] + 8005704: 6053 str r3, [r2, #4] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 8005706: 4b27 ldr r3, [pc, #156] ; (80057a4 ) + 8005708: 689b ldr r3, [r3, #8] + 800570a: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 800570c: 693b ldr r3, [r7, #16] + 800570e: 43db mvns r3, r3 + 8005710: 69ba ldr r2, [r7, #24] + 8005712: 4013 ands r3, r2 + 8005714: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + 8005716: 683b ldr r3, [r7, #0] + 8005718: 685b ldr r3, [r3, #4] + 800571a: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 800571e: 2b00 cmp r3, #0 + 8005720: d003 beq.n 800572a + { + temp |= iocurrent; + 8005722: 69ba ldr r2, [r7, #24] + 8005724: 693b ldr r3, [r7, #16] + 8005726: 4313 orrs r3, r2 + 8005728: 61bb str r3, [r7, #24] + } + EXTI->RTSR = temp; + 800572a: 4a1e ldr r2, [pc, #120] ; (80057a4 ) + 800572c: 69bb ldr r3, [r7, #24] + 800572e: 6093 str r3, [r2, #8] + + temp = EXTI->FTSR; + 8005730: 4b1c ldr r3, [pc, #112] ; (80057a4 ) + 8005732: 68db ldr r3, [r3, #12] + 8005734: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 8005736: 693b ldr r3, [r7, #16] + 8005738: 43db mvns r3, r3 + 800573a: 69ba ldr r2, [r7, #24] + 800573c: 4013 ands r3, r2 + 800573e: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + 8005740: 683b ldr r3, [r7, #0] + 8005742: 685b ldr r3, [r3, #4] + 8005744: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8005748: 2b00 cmp r3, #0 + 800574a: d003 beq.n 8005754 + { + temp |= iocurrent; + 800574c: 69ba ldr r2, [r7, #24] + 800574e: 693b ldr r3, [r7, #16] + 8005750: 4313 orrs r3, r2 + 8005752: 61bb str r3, [r7, #24] + } + EXTI->FTSR = temp; + 8005754: 4a13 ldr r2, [pc, #76] ; (80057a4 ) + 8005756: 69bb ldr r3, [r7, #24] + 8005758: 60d3 str r3, [r2, #12] + for(position = 0; position < GPIO_NUMBER; position++) + 800575a: 69fb ldr r3, [r7, #28] + 800575c: 3301 adds r3, #1 + 800575e: 61fb str r3, [r7, #28] + 8005760: 69fb ldr r3, [r7, #28] + 8005762: 2b0f cmp r3, #15 + 8005764: f67f ae86 bls.w 8005474 + } + } + } +} + 8005768: bf00 nop + 800576a: 3724 adds r7, #36 ; 0x24 + 800576c: 46bd mov sp, r7 + 800576e: f85d 7b04 ldr.w r7, [sp], #4 + 8005772: 4770 bx lr + 8005774: 40023800 .word 0x40023800 + 8005778: 40013800 .word 0x40013800 + 800577c: 40020000 .word 0x40020000 + 8005780: 40020400 .word 0x40020400 + 8005784: 40020800 .word 0x40020800 + 8005788: 40020c00 .word 0x40020c00 + 800578c: 40021000 .word 0x40021000 + 8005790: 40021400 .word 0x40021400 + 8005794: 40021800 .word 0x40021800 + 8005798: 40021c00 .word 0x40021c00 + 800579c: 40022000 .word 0x40022000 + 80057a0: 40022400 .word 0x40022400 + 80057a4: 40013c00 .word 0x40013c00 + +080057a8 : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 80057a8: b480 push {r7} + 80057aa: b083 sub sp, #12 + 80057ac: af00 add r7, sp, #0 + 80057ae: 6078 str r0, [r7, #4] + 80057b0: 460b mov r3, r1 + 80057b2: 807b strh r3, [r7, #2] + 80057b4: 4613 mov r3, r2 + 80057b6: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if(PinState != GPIO_PIN_RESET) + 80057b8: 787b ldrb r3, [r7, #1] + 80057ba: 2b00 cmp r3, #0 + 80057bc: d003 beq.n 80057c6 + { + GPIOx->BSRR = GPIO_Pin; + 80057be: 887a ldrh r2, [r7, #2] + 80057c0: 687b ldr r3, [r7, #4] + 80057c2: 619a str r2, [r3, #24] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; + } +} + 80057c4: e003 b.n 80057ce + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; + 80057c6: 887b ldrh r3, [r7, #2] + 80057c8: 041a lsls r2, r3, #16 + 80057ca: 687b ldr r3, [r7, #4] + 80057cc: 619a str r2, [r3, #24] +} + 80057ce: bf00 nop + 80057d0: 370c adds r7, #12 + 80057d2: 46bd mov sp, r7 + 80057d4: f85d 7b04 ldr.w r7, [sp], #4 + 80057d8: 4770 bx lr + ... + +080057dc : + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin Specifies the pins connected EXTI line + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + 80057dc: b580 push {r7, lr} + 80057de: b082 sub sp, #8 + 80057e0: af00 add r7, sp, #0 + 80057e2: 4603 mov r3, r0 + 80057e4: 80fb strh r3, [r7, #6] + /* EXTI line interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + 80057e6: 4b08 ldr r3, [pc, #32] ; (8005808 ) + 80057e8: 695a ldr r2, [r3, #20] + 80057ea: 88fb ldrh r3, [r7, #6] + 80057ec: 4013 ands r3, r2 + 80057ee: 2b00 cmp r3, #0 + 80057f0: d006 beq.n 8005800 + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + 80057f2: 4a05 ldr r2, [pc, #20] ; (8005808 ) + 80057f4: 88fb ldrh r3, [r7, #6] + 80057f6: 6153 str r3, [r2, #20] + HAL_GPIO_EXTI_Callback(GPIO_Pin); + 80057f8: 88fb ldrh r3, [r7, #6] + 80057fa: 4618 mov r0, r3 + 80057fc: f7fb ffd0 bl 80017a0 + } +} + 8005800: bf00 nop + 8005802: 3708 adds r7, #8 + 8005804: 46bd mov sp, r7 + 8005806: bd80 pop {r7, pc} + 8005808: 40013c00 .word 0x40013c00 + +0800580c : + * supported by this function. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 800580c: b580 push {r7, lr} + 800580e: b086 sub sp, #24 + 8005810: af00 add r7, sp, #0 + 8005812: 6078 str r0, [r7, #4] + uint32_t tickstart; + FlagStatus pwrclkchanged = RESET; + 8005814: 2300 movs r3, #0 + 8005816: 75fb strb r3, [r7, #23] + + /* Check Null pointer */ + if(RCC_OscInitStruct == NULL) + 8005818: 687b ldr r3, [r7, #4] + 800581a: 2b00 cmp r3, #0 + 800581c: d101 bne.n 8005822 + { + return HAL_ERROR; + 800581e: 2301 movs r3, #1 + 8005820: e25e b.n 8005ce0 + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 8005822: 687b ldr r3, [r7, #4] + 8005824: 681b ldr r3, [r3, #0] + 8005826: f003 0301 and.w r3, r3, #1 + 800582a: 2b00 cmp r3, #0 + 800582c: f000 8087 beq.w 800593e + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + 8005830: 4b96 ldr r3, [pc, #600] ; (8005a8c ) + 8005832: 689b ldr r3, [r3, #8] + 8005834: f003 030c and.w r3, r3, #12 + 8005838: 2b04 cmp r3, #4 + 800583a: d00c beq.n 8005856 + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + 800583c: 4b93 ldr r3, [pc, #588] ; (8005a8c ) + 800583e: 689b ldr r3, [r3, #8] + 8005840: f003 030c and.w r3, r3, #12 + 8005844: 2b08 cmp r3, #8 + 8005846: d112 bne.n 800586e + 8005848: 4b90 ldr r3, [pc, #576] ; (8005a8c ) + 800584a: 685b ldr r3, [r3, #4] + 800584c: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8005850: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 8005854: d10b bne.n 800586e + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8005856: 4b8d ldr r3, [pc, #564] ; (8005a8c ) + 8005858: 681b ldr r3, [r3, #0] + 800585a: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800585e: 2b00 cmp r3, #0 + 8005860: d06c beq.n 800593c + 8005862: 687b ldr r3, [r7, #4] + 8005864: 685b ldr r3, [r3, #4] + 8005866: 2b00 cmp r3, #0 + 8005868: d168 bne.n 800593c + { + return HAL_ERROR; + 800586a: 2301 movs r3, #1 + 800586c: e238 b.n 8005ce0 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 800586e: 687b ldr r3, [r7, #4] + 8005870: 685b ldr r3, [r3, #4] + 8005872: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8005876: d106 bne.n 8005886 + 8005878: 4b84 ldr r3, [pc, #528] ; (8005a8c ) + 800587a: 681b ldr r3, [r3, #0] + 800587c: 4a83 ldr r2, [pc, #524] ; (8005a8c ) + 800587e: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8005882: 6013 str r3, [r2, #0] + 8005884: e02e b.n 80058e4 + 8005886: 687b ldr r3, [r7, #4] + 8005888: 685b ldr r3, [r3, #4] + 800588a: 2b00 cmp r3, #0 + 800588c: d10c bne.n 80058a8 + 800588e: 4b7f ldr r3, [pc, #508] ; (8005a8c ) + 8005890: 681b ldr r3, [r3, #0] + 8005892: 4a7e ldr r2, [pc, #504] ; (8005a8c ) + 8005894: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8005898: 6013 str r3, [r2, #0] + 800589a: 4b7c ldr r3, [pc, #496] ; (8005a8c ) + 800589c: 681b ldr r3, [r3, #0] + 800589e: 4a7b ldr r2, [pc, #492] ; (8005a8c ) + 80058a0: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 80058a4: 6013 str r3, [r2, #0] + 80058a6: e01d b.n 80058e4 + 80058a8: 687b ldr r3, [r7, #4] + 80058aa: 685b ldr r3, [r3, #4] + 80058ac: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 + 80058b0: d10c bne.n 80058cc + 80058b2: 4b76 ldr r3, [pc, #472] ; (8005a8c ) + 80058b4: 681b ldr r3, [r3, #0] + 80058b6: 4a75 ldr r2, [pc, #468] ; (8005a8c ) + 80058b8: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 80058bc: 6013 str r3, [r2, #0] + 80058be: 4b73 ldr r3, [pc, #460] ; (8005a8c ) + 80058c0: 681b ldr r3, [r3, #0] + 80058c2: 4a72 ldr r2, [pc, #456] ; (8005a8c ) + 80058c4: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80058c8: 6013 str r3, [r2, #0] + 80058ca: e00b b.n 80058e4 + 80058cc: 4b6f ldr r3, [pc, #444] ; (8005a8c ) + 80058ce: 681b ldr r3, [r3, #0] + 80058d0: 4a6e ldr r2, [pc, #440] ; (8005a8c ) + 80058d2: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 80058d6: 6013 str r3, [r2, #0] + 80058d8: 4b6c ldr r3, [pc, #432] ; (8005a8c ) + 80058da: 681b ldr r3, [r3, #0] + 80058dc: 4a6b ldr r2, [pc, #428] ; (8005a8c ) + 80058de: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 80058e2: 6013 str r3, [r2, #0] + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 80058e4: 687b ldr r3, [r7, #4] + 80058e6: 685b ldr r3, [r3, #4] + 80058e8: 2b00 cmp r3, #0 + 80058ea: d013 beq.n 8005914 + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80058ec: f7ff fc72 bl 80051d4 + 80058f0: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 80058f2: e008 b.n 8005906 + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 80058f4: f7ff fc6e bl 80051d4 + 80058f8: 4602 mov r2, r0 + 80058fa: 693b ldr r3, [r7, #16] + 80058fc: 1ad3 subs r3, r2, r3 + 80058fe: 2b64 cmp r3, #100 ; 0x64 + 8005900: d901 bls.n 8005906 + { + return HAL_TIMEOUT; + 8005902: 2303 movs r3, #3 + 8005904: e1ec b.n 8005ce0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8005906: 4b61 ldr r3, [pc, #388] ; (8005a8c ) + 8005908: 681b ldr r3, [r3, #0] + 800590a: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800590e: 2b00 cmp r3, #0 + 8005910: d0f0 beq.n 80058f4 + 8005912: e014 b.n 800593e + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8005914: f7ff fc5e bl 80051d4 + 8005918: 6138 str r0, [r7, #16] + + /* Wait till HSE is bypassed or disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 800591a: e008 b.n 800592e + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 800591c: f7ff fc5a bl 80051d4 + 8005920: 4602 mov r2, r0 + 8005922: 693b ldr r3, [r7, #16] + 8005924: 1ad3 subs r3, r2, r3 + 8005926: 2b64 cmp r3, #100 ; 0x64 + 8005928: d901 bls.n 800592e + { + return HAL_TIMEOUT; + 800592a: 2303 movs r3, #3 + 800592c: e1d8 b.n 8005ce0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 800592e: 4b57 ldr r3, [pc, #348] ; (8005a8c ) + 8005930: 681b ldr r3, [r3, #0] + 8005932: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8005936: 2b00 cmp r3, #0 + 8005938: d1f0 bne.n 800591c + 800593a: e000 b.n 800593e + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 800593c: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 800593e: 687b ldr r3, [r7, #4] + 8005940: 681b ldr r3, [r3, #0] + 8005942: f003 0302 and.w r3, r3, #2 + 8005946: 2b00 cmp r3, #0 + 8005948: d069 beq.n 8005a1e + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + 800594a: 4b50 ldr r3, [pc, #320] ; (8005a8c ) + 800594c: 689b ldr r3, [r3, #8] + 800594e: f003 030c and.w r3, r3, #12 + 8005952: 2b00 cmp r3, #0 + 8005954: d00b beq.n 800596e + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + 8005956: 4b4d ldr r3, [pc, #308] ; (8005a8c ) + 8005958: 689b ldr r3, [r3, #8] + 800595a: f003 030c and.w r3, r3, #12 + 800595e: 2b08 cmp r3, #8 + 8005960: d11c bne.n 800599c + 8005962: 4b4a ldr r3, [pc, #296] ; (8005a8c ) + 8005964: 685b ldr r3, [r3, #4] + 8005966: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 800596a: 2b00 cmp r3, #0 + 800596c: d116 bne.n 800599c + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 800596e: 4b47 ldr r3, [pc, #284] ; (8005a8c ) + 8005970: 681b ldr r3, [r3, #0] + 8005972: f003 0302 and.w r3, r3, #2 + 8005976: 2b00 cmp r3, #0 + 8005978: d005 beq.n 8005986 + 800597a: 687b ldr r3, [r7, #4] + 800597c: 68db ldr r3, [r3, #12] + 800597e: 2b01 cmp r3, #1 + 8005980: d001 beq.n 8005986 + { + return HAL_ERROR; + 8005982: 2301 movs r3, #1 + 8005984: e1ac b.n 8005ce0 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8005986: 4b41 ldr r3, [pc, #260] ; (8005a8c ) + 8005988: 681b ldr r3, [r3, #0] + 800598a: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 800598e: 687b ldr r3, [r7, #4] + 8005990: 691b ldr r3, [r3, #16] + 8005992: 00db lsls r3, r3, #3 + 8005994: 493d ldr r1, [pc, #244] ; (8005a8c ) + 8005996: 4313 orrs r3, r2 + 8005998: 600b str r3, [r1, #0] + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 800599a: e040 b.n 8005a1e + } + } + else + { + /* Check the HSI State */ + if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) + 800599c: 687b ldr r3, [r7, #4] + 800599e: 68db ldr r3, [r3, #12] + 80059a0: 2b00 cmp r3, #0 + 80059a2: d023 beq.n 80059ec + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 80059a4: 4b39 ldr r3, [pc, #228] ; (8005a8c ) + 80059a6: 681b ldr r3, [r3, #0] + 80059a8: 4a38 ldr r2, [pc, #224] ; (8005a8c ) + 80059aa: f043 0301 orr.w r3, r3, #1 + 80059ae: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80059b0: f7ff fc10 bl 80051d4 + 80059b4: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 80059b6: e008 b.n 80059ca + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 80059b8: f7ff fc0c bl 80051d4 + 80059bc: 4602 mov r2, r0 + 80059be: 693b ldr r3, [r7, #16] + 80059c0: 1ad3 subs r3, r2, r3 + 80059c2: 2b02 cmp r3, #2 + 80059c4: d901 bls.n 80059ca + { + return HAL_TIMEOUT; + 80059c6: 2303 movs r3, #3 + 80059c8: e18a b.n 8005ce0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 80059ca: 4b30 ldr r3, [pc, #192] ; (8005a8c ) + 80059cc: 681b ldr r3, [r3, #0] + 80059ce: f003 0302 and.w r3, r3, #2 + 80059d2: 2b00 cmp r3, #0 + 80059d4: d0f0 beq.n 80059b8 + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 80059d6: 4b2d ldr r3, [pc, #180] ; (8005a8c ) + 80059d8: 681b ldr r3, [r3, #0] + 80059da: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 80059de: 687b ldr r3, [r7, #4] + 80059e0: 691b ldr r3, [r3, #16] + 80059e2: 00db lsls r3, r3, #3 + 80059e4: 4929 ldr r1, [pc, #164] ; (8005a8c ) + 80059e6: 4313 orrs r3, r2 + 80059e8: 600b str r3, [r1, #0] + 80059ea: e018 b.n 8005a1e + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 80059ec: 4b27 ldr r3, [pc, #156] ; (8005a8c ) + 80059ee: 681b ldr r3, [r3, #0] + 80059f0: 4a26 ldr r2, [pc, #152] ; (8005a8c ) + 80059f2: f023 0301 bic.w r3, r3, #1 + 80059f6: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80059f8: f7ff fbec bl 80051d4 + 80059fc: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 80059fe: e008 b.n 8005a12 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8005a00: f7ff fbe8 bl 80051d4 + 8005a04: 4602 mov r2, r0 + 8005a06: 693b ldr r3, [r7, #16] + 8005a08: 1ad3 subs r3, r2, r3 + 8005a0a: 2b02 cmp r3, #2 + 8005a0c: d901 bls.n 8005a12 + { + return HAL_TIMEOUT; + 8005a0e: 2303 movs r3, #3 + 8005a10: e166 b.n 8005ce0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 8005a12: 4b1e ldr r3, [pc, #120] ; (8005a8c ) + 8005a14: 681b ldr r3, [r3, #0] + 8005a16: f003 0302 and.w r3, r3, #2 + 8005a1a: 2b00 cmp r3, #0 + 8005a1c: d1f0 bne.n 8005a00 + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8005a1e: 687b ldr r3, [r7, #4] + 8005a20: 681b ldr r3, [r3, #0] + 8005a22: f003 0308 and.w r3, r3, #8 + 8005a26: 2b00 cmp r3, #0 + 8005a28: d038 beq.n 8005a9c + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) + 8005a2a: 687b ldr r3, [r7, #4] + 8005a2c: 695b ldr r3, [r3, #20] + 8005a2e: 2b00 cmp r3, #0 + 8005a30: d019 beq.n 8005a66 + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 8005a32: 4b16 ldr r3, [pc, #88] ; (8005a8c ) + 8005a34: 6f5b ldr r3, [r3, #116] ; 0x74 + 8005a36: 4a15 ldr r2, [pc, #84] ; (8005a8c ) + 8005a38: f043 0301 orr.w r3, r3, #1 + 8005a3c: 6753 str r3, [r2, #116] ; 0x74 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8005a3e: f7ff fbc9 bl 80051d4 + 8005a42: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8005a44: e008 b.n 8005a58 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8005a46: f7ff fbc5 bl 80051d4 + 8005a4a: 4602 mov r2, r0 + 8005a4c: 693b ldr r3, [r7, #16] + 8005a4e: 1ad3 subs r3, r2, r3 + 8005a50: 2b02 cmp r3, #2 + 8005a52: d901 bls.n 8005a58 + { + return HAL_TIMEOUT; + 8005a54: 2303 movs r3, #3 + 8005a56: e143 b.n 8005ce0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8005a58: 4b0c ldr r3, [pc, #48] ; (8005a8c ) + 8005a5a: 6f5b ldr r3, [r3, #116] ; 0x74 + 8005a5c: f003 0302 and.w r3, r3, #2 + 8005a60: 2b00 cmp r3, #0 + 8005a62: d0f0 beq.n 8005a46 + 8005a64: e01a b.n 8005a9c + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8005a66: 4b09 ldr r3, [pc, #36] ; (8005a8c ) + 8005a68: 6f5b ldr r3, [r3, #116] ; 0x74 + 8005a6a: 4a08 ldr r2, [pc, #32] ; (8005a8c ) + 8005a6c: f023 0301 bic.w r3, r3, #1 + 8005a70: 6753 str r3, [r2, #116] ; 0x74 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8005a72: f7ff fbaf bl 80051d4 + 8005a76: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8005a78: e00a b.n 8005a90 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8005a7a: f7ff fbab bl 80051d4 + 8005a7e: 4602 mov r2, r0 + 8005a80: 693b ldr r3, [r7, #16] + 8005a82: 1ad3 subs r3, r2, r3 + 8005a84: 2b02 cmp r3, #2 + 8005a86: d903 bls.n 8005a90 + { + return HAL_TIMEOUT; + 8005a88: 2303 movs r3, #3 + 8005a8a: e129 b.n 8005ce0 + 8005a8c: 40023800 .word 0x40023800 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8005a90: 4b95 ldr r3, [pc, #596] ; (8005ce8 ) + 8005a92: 6f5b ldr r3, [r3, #116] ; 0x74 + 8005a94: f003 0302 and.w r3, r3, #2 + 8005a98: 2b00 cmp r3, #0 + 8005a9a: d1ee bne.n 8005a7a + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8005a9c: 687b ldr r3, [r7, #4] + 8005a9e: 681b ldr r3, [r3, #0] + 8005aa0: f003 0304 and.w r3, r3, #4 + 8005aa4: 2b00 cmp r3, #0 + 8005aa6: f000 80a4 beq.w 8005bf2 + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8005aaa: 4b8f ldr r3, [pc, #572] ; (8005ce8 ) + 8005aac: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005aae: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8005ab2: 2b00 cmp r3, #0 + 8005ab4: d10d bne.n 8005ad2 + { + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + 8005ab6: 4b8c ldr r3, [pc, #560] ; (8005ce8 ) + 8005ab8: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005aba: 4a8b ldr r2, [pc, #556] ; (8005ce8 ) + 8005abc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8005ac0: 6413 str r3, [r2, #64] ; 0x40 + 8005ac2: 4b89 ldr r3, [pc, #548] ; (8005ce8 ) + 8005ac4: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005ac6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8005aca: 60fb str r3, [r7, #12] + 8005acc: 68fb ldr r3, [r7, #12] + pwrclkchanged = SET; + 8005ace: 2301 movs r3, #1 + 8005ad0: 75fb strb r3, [r7, #23] + } + + if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 8005ad2: 4b86 ldr r3, [pc, #536] ; (8005cec ) + 8005ad4: 681b ldr r3, [r3, #0] + 8005ad6: f403 7380 and.w r3, r3, #256 ; 0x100 + 8005ada: 2b00 cmp r3, #0 + 8005adc: d118 bne.n 8005b10 + { + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + 8005ade: 4b83 ldr r3, [pc, #524] ; (8005cec ) + 8005ae0: 681b ldr r3, [r3, #0] + 8005ae2: 4a82 ldr r2, [pc, #520] ; (8005cec ) + 8005ae4: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8005ae8: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8005aea: f7ff fb73 bl 80051d4 + 8005aee: 6138 str r0, [r7, #16] + + while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 8005af0: e008 b.n 8005b04 + { + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + 8005af2: f7ff fb6f bl 80051d4 + 8005af6: 4602 mov r2, r0 + 8005af8: 693b ldr r3, [r7, #16] + 8005afa: 1ad3 subs r3, r2, r3 + 8005afc: 2b64 cmp r3, #100 ; 0x64 + 8005afe: d901 bls.n 8005b04 + { + return HAL_TIMEOUT; + 8005b00: 2303 movs r3, #3 + 8005b02: e0ed b.n 8005ce0 + while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 8005b04: 4b79 ldr r3, [pc, #484] ; (8005cec ) + 8005b06: 681b ldr r3, [r3, #0] + 8005b08: f403 7380 and.w r3, r3, #256 ; 0x100 + 8005b0c: 2b00 cmp r3, #0 + 8005b0e: d0f0 beq.n 8005af2 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8005b10: 687b ldr r3, [r7, #4] + 8005b12: 689b ldr r3, [r3, #8] + 8005b14: 2b01 cmp r3, #1 + 8005b16: d106 bne.n 8005b26 + 8005b18: 4b73 ldr r3, [pc, #460] ; (8005ce8 ) + 8005b1a: 6f1b ldr r3, [r3, #112] ; 0x70 + 8005b1c: 4a72 ldr r2, [pc, #456] ; (8005ce8 ) + 8005b1e: f043 0301 orr.w r3, r3, #1 + 8005b22: 6713 str r3, [r2, #112] ; 0x70 + 8005b24: e02d b.n 8005b82 + 8005b26: 687b ldr r3, [r7, #4] + 8005b28: 689b ldr r3, [r3, #8] + 8005b2a: 2b00 cmp r3, #0 + 8005b2c: d10c bne.n 8005b48 + 8005b2e: 4b6e ldr r3, [pc, #440] ; (8005ce8 ) + 8005b30: 6f1b ldr r3, [r3, #112] ; 0x70 + 8005b32: 4a6d ldr r2, [pc, #436] ; (8005ce8 ) + 8005b34: f023 0301 bic.w r3, r3, #1 + 8005b38: 6713 str r3, [r2, #112] ; 0x70 + 8005b3a: 4b6b ldr r3, [pc, #428] ; (8005ce8 ) + 8005b3c: 6f1b ldr r3, [r3, #112] ; 0x70 + 8005b3e: 4a6a ldr r2, [pc, #424] ; (8005ce8 ) + 8005b40: f023 0304 bic.w r3, r3, #4 + 8005b44: 6713 str r3, [r2, #112] ; 0x70 + 8005b46: e01c b.n 8005b82 + 8005b48: 687b ldr r3, [r7, #4] + 8005b4a: 689b ldr r3, [r3, #8] + 8005b4c: 2b05 cmp r3, #5 + 8005b4e: d10c bne.n 8005b6a + 8005b50: 4b65 ldr r3, [pc, #404] ; (8005ce8 ) + 8005b52: 6f1b ldr r3, [r3, #112] ; 0x70 + 8005b54: 4a64 ldr r2, [pc, #400] ; (8005ce8 ) + 8005b56: f043 0304 orr.w r3, r3, #4 + 8005b5a: 6713 str r3, [r2, #112] ; 0x70 + 8005b5c: 4b62 ldr r3, [pc, #392] ; (8005ce8 ) + 8005b5e: 6f1b ldr r3, [r3, #112] ; 0x70 + 8005b60: 4a61 ldr r2, [pc, #388] ; (8005ce8 ) + 8005b62: f043 0301 orr.w r3, r3, #1 + 8005b66: 6713 str r3, [r2, #112] ; 0x70 + 8005b68: e00b b.n 8005b82 + 8005b6a: 4b5f ldr r3, [pc, #380] ; (8005ce8 ) + 8005b6c: 6f1b ldr r3, [r3, #112] ; 0x70 + 8005b6e: 4a5e ldr r2, [pc, #376] ; (8005ce8 ) + 8005b70: f023 0301 bic.w r3, r3, #1 + 8005b74: 6713 str r3, [r2, #112] ; 0x70 + 8005b76: 4b5c ldr r3, [pc, #368] ; (8005ce8 ) + 8005b78: 6f1b ldr r3, [r3, #112] ; 0x70 + 8005b7a: 4a5b ldr r2, [pc, #364] ; (8005ce8 ) + 8005b7c: f023 0304 bic.w r3, r3, #4 + 8005b80: 6713 str r3, [r2, #112] ; 0x70 + /* Check the LSE State */ + if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + 8005b82: 687b ldr r3, [r7, #4] + 8005b84: 689b ldr r3, [r3, #8] + 8005b86: 2b00 cmp r3, #0 + 8005b88: d015 beq.n 8005bb6 + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8005b8a: f7ff fb23 bl 80051d4 + 8005b8e: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8005b90: e00a b.n 8005ba8 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8005b92: f7ff fb1f bl 80051d4 + 8005b96: 4602 mov r2, r0 + 8005b98: 693b ldr r3, [r7, #16] + 8005b9a: 1ad3 subs r3, r2, r3 + 8005b9c: f241 3288 movw r2, #5000 ; 0x1388 + 8005ba0: 4293 cmp r3, r2 + 8005ba2: d901 bls.n 8005ba8 + { + return HAL_TIMEOUT; + 8005ba4: 2303 movs r3, #3 + 8005ba6: e09b b.n 8005ce0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8005ba8: 4b4f ldr r3, [pc, #316] ; (8005ce8 ) + 8005baa: 6f1b ldr r3, [r3, #112] ; 0x70 + 8005bac: f003 0302 and.w r3, r3, #2 + 8005bb0: 2b00 cmp r3, #0 + 8005bb2: d0ee beq.n 8005b92 + 8005bb4: e014 b.n 8005be0 + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8005bb6: f7ff fb0d bl 80051d4 + 8005bba: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8005bbc: e00a b.n 8005bd4 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8005bbe: f7ff fb09 bl 80051d4 + 8005bc2: 4602 mov r2, r0 + 8005bc4: 693b ldr r3, [r7, #16] + 8005bc6: 1ad3 subs r3, r2, r3 + 8005bc8: f241 3288 movw r2, #5000 ; 0x1388 + 8005bcc: 4293 cmp r3, r2 + 8005bce: d901 bls.n 8005bd4 + { + return HAL_TIMEOUT; + 8005bd0: 2303 movs r3, #3 + 8005bd2: e085 b.n 8005ce0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8005bd4: 4b44 ldr r3, [pc, #272] ; (8005ce8 ) + 8005bd6: 6f1b ldr r3, [r3, #112] ; 0x70 + 8005bd8: f003 0302 and.w r3, r3, #2 + 8005bdc: 2b00 cmp r3, #0 + 8005bde: d1ee bne.n 8005bbe + } + } + } + + /* Restore clock configuration if changed */ + if(pwrclkchanged == SET) + 8005be0: 7dfb ldrb r3, [r7, #23] + 8005be2: 2b01 cmp r3, #1 + 8005be4: d105 bne.n 8005bf2 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8005be6: 4b40 ldr r3, [pc, #256] ; (8005ce8 ) + 8005be8: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005bea: 4a3f ldr r2, [pc, #252] ; (8005ce8 ) + 8005bec: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 8005bf0: 6413 str r3, [r2, #64] ; 0x40 + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 8005bf2: 687b ldr r3, [r7, #4] + 8005bf4: 699b ldr r3, [r3, #24] + 8005bf6: 2b00 cmp r3, #0 + 8005bf8: d071 beq.n 8005cde + { + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8005bfa: 4b3b ldr r3, [pc, #236] ; (8005ce8 ) + 8005bfc: 689b ldr r3, [r3, #8] + 8005bfe: f003 030c and.w r3, r3, #12 + 8005c02: 2b08 cmp r3, #8 + 8005c04: d069 beq.n 8005cda + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 8005c06: 687b ldr r3, [r7, #4] + 8005c08: 699b ldr r3, [r3, #24] + 8005c0a: 2b02 cmp r3, #2 + 8005c0c: d14b bne.n 8005ca6 +#if defined (RCC_PLLCFGR_PLLR) + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); +#endif + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8005c0e: 4b36 ldr r3, [pc, #216] ; (8005ce8 ) + 8005c10: 681b ldr r3, [r3, #0] + 8005c12: 4a35 ldr r2, [pc, #212] ; (8005ce8 ) + 8005c14: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 8005c18: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8005c1a: f7ff fadb bl 80051d4 + 8005c1e: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8005c20: e008 b.n 8005c34 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8005c22: f7ff fad7 bl 80051d4 + 8005c26: 4602 mov r2, r0 + 8005c28: 693b ldr r3, [r7, #16] + 8005c2a: 1ad3 subs r3, r2, r3 + 8005c2c: 2b02 cmp r3, #2 + 8005c2e: d901 bls.n 8005c34 + { + return HAL_TIMEOUT; + 8005c30: 2303 movs r3, #3 + 8005c32: e055 b.n 8005ce0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8005c34: 4b2c ldr r3, [pc, #176] ; (8005ce8 ) + 8005c36: 681b ldr r3, [r3, #0] + 8005c38: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8005c3c: 2b00 cmp r3, #0 + 8005c3e: d1f0 bne.n 8005c22 + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ +#if defined (RCC_PLLCFGR_PLLR) + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8005c40: 687b ldr r3, [r7, #4] + 8005c42: 69da ldr r2, [r3, #28] + 8005c44: 687b ldr r3, [r7, #4] + 8005c46: 6a1b ldr r3, [r3, #32] + 8005c48: 431a orrs r2, r3 + 8005c4a: 687b ldr r3, [r7, #4] + 8005c4c: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005c4e: 019b lsls r3, r3, #6 + 8005c50: 431a orrs r2, r3 + 8005c52: 687b ldr r3, [r7, #4] + 8005c54: 6a9b ldr r3, [r3, #40] ; 0x28 + 8005c56: 085b lsrs r3, r3, #1 + 8005c58: 3b01 subs r3, #1 + 8005c5a: 041b lsls r3, r3, #16 + 8005c5c: 431a orrs r2, r3 + 8005c5e: 687b ldr r3, [r7, #4] + 8005c60: 6adb ldr r3, [r3, #44] ; 0x2c + 8005c62: 061b lsls r3, r3, #24 + 8005c64: 431a orrs r2, r3 + 8005c66: 687b ldr r3, [r7, #4] + 8005c68: 6b1b ldr r3, [r3, #48] ; 0x30 + 8005c6a: 071b lsls r3, r3, #28 + 8005c6c: 491e ldr r1, [pc, #120] ; (8005ce8 ) + 8005c6e: 4313 orrs r3, r2 + 8005c70: 604b str r3, [r1, #4] + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ); +#endif + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8005c72: 4b1d ldr r3, [pc, #116] ; (8005ce8 ) + 8005c74: 681b ldr r3, [r3, #0] + 8005c76: 4a1c ldr r2, [pc, #112] ; (8005ce8 ) + 8005c78: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 8005c7c: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8005c7e: f7ff faa9 bl 80051d4 + 8005c82: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8005c84: e008 b.n 8005c98 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8005c86: f7ff faa5 bl 80051d4 + 8005c8a: 4602 mov r2, r0 + 8005c8c: 693b ldr r3, [r7, #16] + 8005c8e: 1ad3 subs r3, r2, r3 + 8005c90: 2b02 cmp r3, #2 + 8005c92: d901 bls.n 8005c98 + { + return HAL_TIMEOUT; + 8005c94: 2303 movs r3, #3 + 8005c96: e023 b.n 8005ce0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8005c98: 4b13 ldr r3, [pc, #76] ; (8005ce8 ) + 8005c9a: 681b ldr r3, [r3, #0] + 8005c9c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8005ca0: 2b00 cmp r3, #0 + 8005ca2: d0f0 beq.n 8005c86 + 8005ca4: e01b b.n 8005cde + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8005ca6: 4b10 ldr r3, [pc, #64] ; (8005ce8 ) + 8005ca8: 681b ldr r3, [r3, #0] + 8005caa: 4a0f ldr r2, [pc, #60] ; (8005ce8 ) + 8005cac: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 8005cb0: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8005cb2: f7ff fa8f bl 80051d4 + 8005cb6: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8005cb8: e008 b.n 8005ccc + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8005cba: f7ff fa8b bl 80051d4 + 8005cbe: 4602 mov r2, r0 + 8005cc0: 693b ldr r3, [r7, #16] + 8005cc2: 1ad3 subs r3, r2, r3 + 8005cc4: 2b02 cmp r3, #2 + 8005cc6: d901 bls.n 8005ccc + { + return HAL_TIMEOUT; + 8005cc8: 2303 movs r3, #3 + 8005cca: e009 b.n 8005ce0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8005ccc: 4b06 ldr r3, [pc, #24] ; (8005ce8 ) + 8005cce: 681b ldr r3, [r3, #0] + 8005cd0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8005cd4: 2b00 cmp r3, #0 + 8005cd6: d1f0 bne.n 8005cba + 8005cd8: e001 b.n 8005cde + } + } + } + else + { + return HAL_ERROR; + 8005cda: 2301 movs r3, #1 + 8005cdc: e000 b.n 8005ce0 + } + } + return HAL_OK; + 8005cde: 2300 movs r3, #0 +} + 8005ce0: 4618 mov r0, r3 + 8005ce2: 3718 adds r7, #24 + 8005ce4: 46bd mov sp, r7 + 8005ce6: bd80 pop {r7, pc} + 8005ce8: 40023800 .word 0x40023800 + 8005cec: 40007000 .word 0x40007000 + +08005cf0 : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8005cf0: b580 push {r7, lr} + 8005cf2: b084 sub sp, #16 + 8005cf4: af00 add r7, sp, #0 + 8005cf6: 6078 str r0, [r7, #4] + 8005cf8: 6039 str r1, [r7, #0] + uint32_t tickstart = 0; + 8005cfa: 2300 movs r3, #0 + 8005cfc: 60fb str r3, [r7, #12] + + /* Check Null pointer */ + if(RCC_ClkInitStruct == NULL) + 8005cfe: 687b ldr r3, [r7, #4] + 8005d00: 2b00 cmp r3, #0 + 8005d02: d101 bne.n 8005d08 + { + return HAL_ERROR; + 8005d04: 2301 movs r3, #1 + 8005d06: e0ce b.n 8005ea6 + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 8005d08: 4b69 ldr r3, [pc, #420] ; (8005eb0 ) + 8005d0a: 681b ldr r3, [r3, #0] + 8005d0c: f003 030f and.w r3, r3, #15 + 8005d10: 683a ldr r2, [r7, #0] + 8005d12: 429a cmp r2, r3 + 8005d14: d910 bls.n 8005d38 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8005d16: 4b66 ldr r3, [pc, #408] ; (8005eb0 ) + 8005d18: 681b ldr r3, [r3, #0] + 8005d1a: f023 020f bic.w r2, r3, #15 + 8005d1e: 4964 ldr r1, [pc, #400] ; (8005eb0 ) + 8005d20: 683b ldr r3, [r7, #0] + 8005d22: 4313 orrs r3, r2 + 8005d24: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8005d26: 4b62 ldr r3, [pc, #392] ; (8005eb0 ) + 8005d28: 681b ldr r3, [r3, #0] + 8005d2a: f003 030f and.w r3, r3, #15 + 8005d2e: 683a ldr r2, [r7, #0] + 8005d30: 429a cmp r2, r3 + 8005d32: d001 beq.n 8005d38 + { + return HAL_ERROR; + 8005d34: 2301 movs r3, #1 + 8005d36: e0b6 b.n 8005ea6 + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8005d38: 687b ldr r3, [r7, #4] + 8005d3a: 681b ldr r3, [r3, #0] + 8005d3c: f003 0302 and.w r3, r3, #2 + 8005d40: 2b00 cmp r3, #0 + 8005d42: d020 beq.n 8005d86 + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8005d44: 687b ldr r3, [r7, #4] + 8005d46: 681b ldr r3, [r3, #0] + 8005d48: f003 0304 and.w r3, r3, #4 + 8005d4c: 2b00 cmp r3, #0 + 8005d4e: d005 beq.n 8005d5c + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + 8005d50: 4b58 ldr r3, [pc, #352] ; (8005eb4 ) + 8005d52: 689b ldr r3, [r3, #8] + 8005d54: 4a57 ldr r2, [pc, #348] ; (8005eb4 ) + 8005d56: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00 + 8005d5a: 6093 str r3, [r2, #8] + } + + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8005d5c: 687b ldr r3, [r7, #4] + 8005d5e: 681b ldr r3, [r3, #0] + 8005d60: f003 0308 and.w r3, r3, #8 + 8005d64: 2b00 cmp r3, #0 + 8005d66: d005 beq.n 8005d74 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + 8005d68: 4b52 ldr r3, [pc, #328] ; (8005eb4 ) + 8005d6a: 689b ldr r3, [r3, #8] + 8005d6c: 4a51 ldr r2, [pc, #324] ; (8005eb4 ) + 8005d6e: f443 4360 orr.w r3, r3, #57344 ; 0xe000 + 8005d72: 6093 str r3, [r2, #8] + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8005d74: 4b4f ldr r3, [pc, #316] ; (8005eb4 ) + 8005d76: 689b ldr r3, [r3, #8] + 8005d78: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 8005d7c: 687b ldr r3, [r7, #4] + 8005d7e: 689b ldr r3, [r3, #8] + 8005d80: 494c ldr r1, [pc, #304] ; (8005eb4 ) + 8005d82: 4313 orrs r3, r2 + 8005d84: 608b str r3, [r1, #8] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8005d86: 687b ldr r3, [r7, #4] + 8005d88: 681b ldr r3, [r3, #0] + 8005d8a: f003 0301 and.w r3, r3, #1 + 8005d8e: 2b00 cmp r3, #0 + 8005d90: d040 beq.n 8005e14 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8005d92: 687b ldr r3, [r7, #4] + 8005d94: 685b ldr r3, [r3, #4] + 8005d96: 2b01 cmp r3, #1 + 8005d98: d107 bne.n 8005daa + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8005d9a: 4b46 ldr r3, [pc, #280] ; (8005eb4 ) + 8005d9c: 681b ldr r3, [r3, #0] + 8005d9e: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8005da2: 2b00 cmp r3, #0 + 8005da4: d115 bne.n 8005dd2 + { + return HAL_ERROR; + 8005da6: 2301 movs r3, #1 + 8005da8: e07d b.n 8005ea6 + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8005daa: 687b ldr r3, [r7, #4] + 8005dac: 685b ldr r3, [r3, #4] + 8005dae: 2b02 cmp r3, #2 + 8005db0: d107 bne.n 8005dc2 + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8005db2: 4b40 ldr r3, [pc, #256] ; (8005eb4 ) + 8005db4: 681b ldr r3, [r3, #0] + 8005db6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8005dba: 2b00 cmp r3, #0 + 8005dbc: d109 bne.n 8005dd2 + { + return HAL_ERROR; + 8005dbe: 2301 movs r3, #1 + 8005dc0: e071 b.n 8005ea6 + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8005dc2: 4b3c ldr r3, [pc, #240] ; (8005eb4 ) + 8005dc4: 681b ldr r3, [r3, #0] + 8005dc6: f003 0302 and.w r3, r3, #2 + 8005dca: 2b00 cmp r3, #0 + 8005dcc: d101 bne.n 8005dd2 + { + return HAL_ERROR; + 8005dce: 2301 movs r3, #1 + 8005dd0: e069 b.n 8005ea6 + } + } + + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 8005dd2: 4b38 ldr r3, [pc, #224] ; (8005eb4 ) + 8005dd4: 689b ldr r3, [r3, #8] + 8005dd6: f023 0203 bic.w r2, r3, #3 + 8005dda: 687b ldr r3, [r7, #4] + 8005ddc: 685b ldr r3, [r3, #4] + 8005dde: 4935 ldr r1, [pc, #212] ; (8005eb4 ) + 8005de0: 4313 orrs r3, r2 + 8005de2: 608b str r3, [r1, #8] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8005de4: f7ff f9f6 bl 80051d4 + 8005de8: 60f8 str r0, [r7, #12] + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8005dea: e00a b.n 8005e02 + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 8005dec: f7ff f9f2 bl 80051d4 + 8005df0: 4602 mov r2, r0 + 8005df2: 68fb ldr r3, [r7, #12] + 8005df4: 1ad3 subs r3, r2, r3 + 8005df6: f241 3288 movw r2, #5000 ; 0x1388 + 8005dfa: 4293 cmp r3, r2 + 8005dfc: d901 bls.n 8005e02 + { + return HAL_TIMEOUT; + 8005dfe: 2303 movs r3, #3 + 8005e00: e051 b.n 8005ea6 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8005e02: 4b2c ldr r3, [pc, #176] ; (8005eb4 ) + 8005e04: 689b ldr r3, [r3, #8] + 8005e06: f003 020c and.w r2, r3, #12 + 8005e0a: 687b ldr r3, [r7, #4] + 8005e0c: 685b ldr r3, [r3, #4] + 8005e0e: 009b lsls r3, r3, #2 + 8005e10: 429a cmp r2, r3 + 8005e12: d1eb bne.n 8005dec + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 8005e14: 4b26 ldr r3, [pc, #152] ; (8005eb0 ) + 8005e16: 681b ldr r3, [r3, #0] + 8005e18: f003 030f and.w r3, r3, #15 + 8005e1c: 683a ldr r2, [r7, #0] + 8005e1e: 429a cmp r2, r3 + 8005e20: d210 bcs.n 8005e44 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8005e22: 4b23 ldr r3, [pc, #140] ; (8005eb0 ) + 8005e24: 681b ldr r3, [r3, #0] + 8005e26: f023 020f bic.w r2, r3, #15 + 8005e2a: 4921 ldr r1, [pc, #132] ; (8005eb0 ) + 8005e2c: 683b ldr r3, [r7, #0] + 8005e2e: 4313 orrs r3, r2 + 8005e30: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8005e32: 4b1f ldr r3, [pc, #124] ; (8005eb0 ) + 8005e34: 681b ldr r3, [r3, #0] + 8005e36: f003 030f and.w r3, r3, #15 + 8005e3a: 683a ldr r2, [r7, #0] + 8005e3c: 429a cmp r2, r3 + 8005e3e: d001 beq.n 8005e44 + { + return HAL_ERROR; + 8005e40: 2301 movs r3, #1 + 8005e42: e030 b.n 8005ea6 + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8005e44: 687b ldr r3, [r7, #4] + 8005e46: 681b ldr r3, [r3, #0] + 8005e48: f003 0304 and.w r3, r3, #4 + 8005e4c: 2b00 cmp r3, #0 + 8005e4e: d008 beq.n 8005e62 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 8005e50: 4b18 ldr r3, [pc, #96] ; (8005eb4 ) + 8005e52: 689b ldr r3, [r3, #8] + 8005e54: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 + 8005e58: 687b ldr r3, [r7, #4] + 8005e5a: 68db ldr r3, [r3, #12] + 8005e5c: 4915 ldr r1, [pc, #84] ; (8005eb4 ) + 8005e5e: 4313 orrs r3, r2 + 8005e60: 608b str r3, [r1, #8] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8005e62: 687b ldr r3, [r7, #4] + 8005e64: 681b ldr r3, [r3, #0] + 8005e66: f003 0308 and.w r3, r3, #8 + 8005e6a: 2b00 cmp r3, #0 + 8005e6c: d009 beq.n 8005e82 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + 8005e6e: 4b11 ldr r3, [pc, #68] ; (8005eb4 ) + 8005e70: 689b ldr r3, [r3, #8] + 8005e72: f423 4260 bic.w r2, r3, #57344 ; 0xe000 + 8005e76: 687b ldr r3, [r7, #4] + 8005e78: 691b ldr r3, [r3, #16] + 8005e7a: 00db lsls r3, r3, #3 + 8005e7c: 490d ldr r1, [pc, #52] ; (8005eb4 ) + 8005e7e: 4313 orrs r3, r2 + 8005e80: 608b str r3, [r1, #8] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + 8005e82: f000 f81d bl 8005ec0 + 8005e86: 4601 mov r1, r0 + 8005e88: 4b0a ldr r3, [pc, #40] ; (8005eb4 ) + 8005e8a: 689b ldr r3, [r3, #8] + 8005e8c: 091b lsrs r3, r3, #4 + 8005e8e: f003 030f and.w r3, r3, #15 + 8005e92: 4a09 ldr r2, [pc, #36] ; (8005eb8 ) + 8005e94: 5cd3 ldrb r3, [r2, r3] + 8005e96: fa21 f303 lsr.w r3, r1, r3 + 8005e9a: 4a08 ldr r2, [pc, #32] ; (8005ebc ) + 8005e9c: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick (TICK_INT_PRIORITY); + 8005e9e: 2000 movs r0, #0 + 8005ea0: f7ff f954 bl 800514c + + return HAL_OK; + 8005ea4: 2300 movs r3, #0 +} + 8005ea6: 4618 mov r0, r3 + 8005ea8: 3710 adds r7, #16 + 8005eaa: 46bd mov sp, r7 + 8005eac: bd80 pop {r7, pc} + 8005eae: bf00 nop + 8005eb0: 40023c00 .word 0x40023c00 + 8005eb4: 40023800 .word 0x40023800 + 8005eb8: 08008ca8 .word 0x08008ca8 + 8005ebc: 20000004 .word 0x20000004 + +08005ec0 : + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8005ec0: b5f0 push {r4, r5, r6, r7, lr} + 8005ec2: b085 sub sp, #20 + 8005ec4: af00 add r7, sp, #0 + uint32_t pllm = 0, pllvco = 0, pllp = 0; + 8005ec6: 2300 movs r3, #0 + 8005ec8: 607b str r3, [r7, #4] + 8005eca: 2300 movs r3, #0 + 8005ecc: 60fb str r3, [r7, #12] + 8005ece: 2300 movs r3, #0 + 8005ed0: 603b str r3, [r7, #0] + uint32_t sysclockfreq = 0; + 8005ed2: 2300 movs r3, #0 + 8005ed4: 60bb str r3, [r7, #8] + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + 8005ed6: 4b50 ldr r3, [pc, #320] ; (8006018 ) + 8005ed8: 689b ldr r3, [r3, #8] + 8005eda: f003 030c and.w r3, r3, #12 + 8005ede: 2b04 cmp r3, #4 + 8005ee0: d007 beq.n 8005ef2 + 8005ee2: 2b08 cmp r3, #8 + 8005ee4: d008 beq.n 8005ef8 + 8005ee6: 2b00 cmp r3, #0 + 8005ee8: f040 808d bne.w 8006006 + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + 8005eec: 4b4b ldr r3, [pc, #300] ; (800601c ) + 8005eee: 60bb str r3, [r7, #8] + break; + 8005ef0: e08c b.n 800600c + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + { + sysclockfreq = HSE_VALUE; + 8005ef2: 4b4b ldr r3, [pc, #300] ; (8006020 ) + 8005ef4: 60bb str r3, [r7, #8] + break; + 8005ef6: e089 b.n 800600c + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + 8005ef8: 4b47 ldr r3, [pc, #284] ; (8006018 ) + 8005efa: 685b ldr r3, [r3, #4] + 8005efc: f003 033f and.w r3, r3, #63 ; 0x3f + 8005f00: 607b str r3, [r7, #4] + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) + 8005f02: 4b45 ldr r3, [pc, #276] ; (8006018 ) + 8005f04: 685b ldr r3, [r3, #4] + 8005f06: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8005f0a: 2b00 cmp r3, #0 + 8005f0c: d023 beq.n 8005f56 + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 8005f0e: 4b42 ldr r3, [pc, #264] ; (8006018 ) + 8005f10: 685b ldr r3, [r3, #4] + 8005f12: 099b lsrs r3, r3, #6 + 8005f14: f04f 0400 mov.w r4, #0 + 8005f18: f240 11ff movw r1, #511 ; 0x1ff + 8005f1c: f04f 0200 mov.w r2, #0 + 8005f20: ea03 0501 and.w r5, r3, r1 + 8005f24: ea04 0602 and.w r6, r4, r2 + 8005f28: 4a3d ldr r2, [pc, #244] ; (8006020 ) + 8005f2a: fb02 f106 mul.w r1, r2, r6 + 8005f2e: 2200 movs r2, #0 + 8005f30: fb02 f205 mul.w r2, r2, r5 + 8005f34: 440a add r2, r1 + 8005f36: 493a ldr r1, [pc, #232] ; (8006020 ) + 8005f38: fba5 0101 umull r0, r1, r5, r1 + 8005f3c: 1853 adds r3, r2, r1 + 8005f3e: 4619 mov r1, r3 + 8005f40: 687b ldr r3, [r7, #4] + 8005f42: f04f 0400 mov.w r4, #0 + 8005f46: 461a mov r2, r3 + 8005f48: 4623 mov r3, r4 + 8005f4a: f7fa f975 bl 8000238 <__aeabi_uldivmod> + 8005f4e: 4603 mov r3, r0 + 8005f50: 460c mov r4, r1 + 8005f52: 60fb str r3, [r7, #12] + 8005f54: e049 b.n 8005fea + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 8005f56: 4b30 ldr r3, [pc, #192] ; (8006018 ) + 8005f58: 685b ldr r3, [r3, #4] + 8005f5a: 099b lsrs r3, r3, #6 + 8005f5c: f04f 0400 mov.w r4, #0 + 8005f60: f240 11ff movw r1, #511 ; 0x1ff + 8005f64: f04f 0200 mov.w r2, #0 + 8005f68: ea03 0501 and.w r5, r3, r1 + 8005f6c: ea04 0602 and.w r6, r4, r2 + 8005f70: 4629 mov r1, r5 + 8005f72: 4632 mov r2, r6 + 8005f74: f04f 0300 mov.w r3, #0 + 8005f78: f04f 0400 mov.w r4, #0 + 8005f7c: 0154 lsls r4, r2, #5 + 8005f7e: ea44 64d1 orr.w r4, r4, r1, lsr #27 + 8005f82: 014b lsls r3, r1, #5 + 8005f84: 4619 mov r1, r3 + 8005f86: 4622 mov r2, r4 + 8005f88: 1b49 subs r1, r1, r5 + 8005f8a: eb62 0206 sbc.w r2, r2, r6 + 8005f8e: f04f 0300 mov.w r3, #0 + 8005f92: f04f 0400 mov.w r4, #0 + 8005f96: 0194 lsls r4, r2, #6 + 8005f98: ea44 6491 orr.w r4, r4, r1, lsr #26 + 8005f9c: 018b lsls r3, r1, #6 + 8005f9e: 1a5b subs r3, r3, r1 + 8005fa0: eb64 0402 sbc.w r4, r4, r2 + 8005fa4: f04f 0100 mov.w r1, #0 + 8005fa8: f04f 0200 mov.w r2, #0 + 8005fac: 00e2 lsls r2, r4, #3 + 8005fae: ea42 7253 orr.w r2, r2, r3, lsr #29 + 8005fb2: 00d9 lsls r1, r3, #3 + 8005fb4: 460b mov r3, r1 + 8005fb6: 4614 mov r4, r2 + 8005fb8: 195b adds r3, r3, r5 + 8005fba: eb44 0406 adc.w r4, r4, r6 + 8005fbe: f04f 0100 mov.w r1, #0 + 8005fc2: f04f 0200 mov.w r2, #0 + 8005fc6: 02a2 lsls r2, r4, #10 + 8005fc8: ea42 5293 orr.w r2, r2, r3, lsr #22 + 8005fcc: 0299 lsls r1, r3, #10 + 8005fce: 460b mov r3, r1 + 8005fd0: 4614 mov r4, r2 + 8005fd2: 4618 mov r0, r3 + 8005fd4: 4621 mov r1, r4 + 8005fd6: 687b ldr r3, [r7, #4] + 8005fd8: f04f 0400 mov.w r4, #0 + 8005fdc: 461a mov r2, r3 + 8005fde: 4623 mov r3, r4 + 8005fe0: f7fa f92a bl 8000238 <__aeabi_uldivmod> + 8005fe4: 4603 mov r3, r0 + 8005fe6: 460c mov r4, r1 + 8005fe8: 60fb str r3, [r7, #12] + } + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2); + 8005fea: 4b0b ldr r3, [pc, #44] ; (8006018 ) + 8005fec: 685b ldr r3, [r3, #4] + 8005fee: 0c1b lsrs r3, r3, #16 + 8005ff0: f003 0303 and.w r3, r3, #3 + 8005ff4: 3301 adds r3, #1 + 8005ff6: 005b lsls r3, r3, #1 + 8005ff8: 603b str r3, [r7, #0] + + sysclockfreq = pllvco/pllp; + 8005ffa: 68fa ldr r2, [r7, #12] + 8005ffc: 683b ldr r3, [r7, #0] + 8005ffe: fbb2 f3f3 udiv r3, r2, r3 + 8006002: 60bb str r3, [r7, #8] + break; + 8006004: e002 b.n 800600c + } + default: + { + sysclockfreq = HSI_VALUE; + 8006006: 4b05 ldr r3, [pc, #20] ; (800601c ) + 8006008: 60bb str r3, [r7, #8] + break; + 800600a: bf00 nop + } + } + return sysclockfreq; + 800600c: 68bb ldr r3, [r7, #8] +} + 800600e: 4618 mov r0, r3 + 8006010: 3714 adds r7, #20 + 8006012: 46bd mov sp, r7 + 8006014: bdf0 pop {r4, r5, r6, r7, pc} + 8006016: bf00 nop + 8006018: 40023800 .word 0x40023800 + 800601c: 00f42400 .word 0x00f42400 + 8006020: 017d7840 .word 0x017d7840 + +08006024 : + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + 8006024: b480 push {r7} + 8006026: af00 add r7, sp, #0 + return SystemCoreClock; + 8006028: 4b03 ldr r3, [pc, #12] ; (8006038 ) + 800602a: 681b ldr r3, [r3, #0] +} + 800602c: 4618 mov r0, r3 + 800602e: 46bd mov sp, r7 + 8006030: f85d 7b04 ldr.w r7, [sp], #4 + 8006034: 4770 bx lr + 8006036: bf00 nop + 8006038: 20000004 .word 0x20000004 + +0800603c : + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + 800603c: b580 push {r7, lr} + 800603e: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]); + 8006040: f7ff fff0 bl 8006024 + 8006044: 4601 mov r1, r0 + 8006046: 4b05 ldr r3, [pc, #20] ; (800605c ) + 8006048: 689b ldr r3, [r3, #8] + 800604a: 0a9b lsrs r3, r3, #10 + 800604c: f003 0307 and.w r3, r3, #7 + 8006050: 4a03 ldr r2, [pc, #12] ; (8006060 ) + 8006052: 5cd3 ldrb r3, [r2, r3] + 8006054: fa21 f303 lsr.w r3, r1, r3 +} + 8006058: 4618 mov r0, r3 + 800605a: bd80 pop {r7, pc} + 800605c: 40023800 .word 0x40023800 + 8006060: 08008cb8 .word 0x08008cb8 + +08006064 : + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + 8006064: b580 push {r7, lr} + 8006066: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]); + 8006068: f7ff ffdc bl 8006024 + 800606c: 4601 mov r1, r0 + 800606e: 4b05 ldr r3, [pc, #20] ; (8006084 ) + 8006070: 689b ldr r3, [r3, #8] + 8006072: 0b5b lsrs r3, r3, #13 + 8006074: f003 0307 and.w r3, r3, #7 + 8006078: 4a03 ldr r2, [pc, #12] ; (8006088 ) + 800607a: 5cd3 ldrb r3, [r2, r3] + 800607c: fa21 f303 lsr.w r3, r1, r3 +} + 8006080: 4618 mov r0, r3 + 8006082: bd80 pop {r7, pc} + 8006084: 40023800 .word 0x40023800 + 8006088: 08008cb8 .word 0x08008cb8 + +0800608c : + * the backup registers) are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + 800608c: b580 push {r7, lr} + 800608e: b088 sub sp, #32 + 8006090: af00 add r7, sp, #0 + 8006092: 6078 str r0, [r7, #4] + uint32_t tickstart = 0; + 8006094: 2300 movs r3, #0 + 8006096: 617b str r3, [r7, #20] + uint32_t tmpreg0 = 0; + 8006098: 2300 movs r3, #0 + 800609a: 613b str r3, [r7, #16] + uint32_t tmpreg1 = 0; + 800609c: 2300 movs r3, #0 + 800609e: 60fb str r3, [r7, #12] + uint32_t plli2sused = 0; + 80060a0: 2300 movs r3, #0 + 80060a2: 61fb str r3, [r7, #28] + uint32_t pllsaiused = 0; + 80060a4: 2300 movs r3, #0 + 80060a6: 61bb str r3, [r7, #24] + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*----------------------------------- I2S configuration ----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + 80060a8: 687b ldr r3, [r7, #4] + 80060aa: 681b ldr r3, [r3, #0] + 80060ac: f003 0301 and.w r3, r3, #1 + 80060b0: 2b00 cmp r3, #0 + 80060b2: d012 beq.n 80060da + { + /* Check the parameters */ + assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + 80060b4: 4b69 ldr r3, [pc, #420] ; (800625c ) + 80060b6: 689b ldr r3, [r3, #8] + 80060b8: 4a68 ldr r2, [pc, #416] ; (800625c ) + 80060ba: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 + 80060be: 6093 str r3, [r2, #8] + 80060c0: 4b66 ldr r3, [pc, #408] ; (800625c ) + 80060c2: 689a ldr r2, [r3, #8] + 80060c4: 687b ldr r3, [r7, #4] + 80060c6: 6b5b ldr r3, [r3, #52] ; 0x34 + 80060c8: 4964 ldr r1, [pc, #400] ; (800625c ) + 80060ca: 4313 orrs r3, r2 + 80060cc: 608b str r3, [r1, #8] + + /* Enable the PLLI2S when it's used as clock source for I2S */ + if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) + 80060ce: 687b ldr r3, [r7, #4] + 80060d0: 6b5b ldr r3, [r3, #52] ; 0x34 + 80060d2: 2b00 cmp r3, #0 + 80060d4: d101 bne.n 80060da + { + plli2sused = 1; + 80060d6: 2301 movs r3, #1 + 80060d8: 61fb str r3, [r7, #28] + } + } + + /*------------------------------------ SAI1 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) + 80060da: 687b ldr r3, [r7, #4] + 80060dc: 681b ldr r3, [r3, #0] + 80060de: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 80060e2: 2b00 cmp r3, #0 + 80060e4: d017 beq.n 8006116 + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + 80060e6: 4b5d ldr r3, [pc, #372] ; (800625c ) + 80060e8: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 80060ec: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 + 80060f0: 687b ldr r3, [r7, #4] + 80060f2: 6bdb ldr r3, [r3, #60] ; 0x3c + 80060f4: 4959 ldr r1, [pc, #356] ; (800625c ) + 80060f6: 4313 orrs r3, r2 + 80060f8: f8c1 308c str.w r3, [r1, #140] ; 0x8c + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) + 80060fc: 687b ldr r3, [r7, #4] + 80060fe: 6bdb ldr r3, [r3, #60] ; 0x3c + 8006100: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 8006104: d101 bne.n 800610a + { + plli2sused = 1; + 8006106: 2301 movs r3, #1 + 8006108: 61fb str r3, [r7, #28] + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) + 800610a: 687b ldr r3, [r7, #4] + 800610c: 6bdb ldr r3, [r3, #60] ; 0x3c + 800610e: 2b00 cmp r3, #0 + 8006110: d101 bne.n 8006116 + { + pllsaiused = 1; + 8006112: 2301 movs r3, #1 + 8006114: 61bb str r3, [r7, #24] + } + } + + /*------------------------------------ SAI2 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) + 8006116: 687b ldr r3, [r7, #4] + 8006118: 681b ldr r3, [r3, #0] + 800611a: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 800611e: 2b00 cmp r3, #0 + 8006120: d017 beq.n 8006152 + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + + /* Configure SAI2 Clock source */ + __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + 8006122: 4b4e ldr r3, [pc, #312] ; (800625c ) + 8006124: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8006128: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 + 800612c: 687b ldr r3, [r7, #4] + 800612e: 6c1b ldr r3, [r3, #64] ; 0x40 + 8006130: 494a ldr r1, [pc, #296] ; (800625c ) + 8006132: 4313 orrs r3, r2 + 8006134: f8c1 308c str.w r3, [r1, #140] ; 0x8c + + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) + 8006138: 687b ldr r3, [r7, #4] + 800613a: 6c1b ldr r3, [r3, #64] ; 0x40 + 800613c: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 8006140: d101 bne.n 8006146 + { + plli2sused = 1; + 8006142: 2301 movs r3, #1 + 8006144: 61fb str r3, [r7, #28] + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) + 8006146: 687b ldr r3, [r7, #4] + 8006148: 6c1b ldr r3, [r3, #64] ; 0x40 + 800614a: 2b00 cmp r3, #0 + 800614c: d101 bne.n 8006152 + { + pllsaiused = 1; + 800614e: 2301 movs r3, #1 + 8006150: 61bb str r3, [r7, #24] + } + } + + /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + 8006152: 687b ldr r3, [r7, #4] + 8006154: 681b ldr r3, [r3, #0] + 8006156: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 800615a: 2b00 cmp r3, #0 + 800615c: d001 beq.n 8006162 + { + plli2sused = 1; + 800615e: 2301 movs r3, #1 + 8006160: 61fb str r3, [r7, #28] + } + + /*------------------------------------ RTC configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + 8006162: 687b ldr r3, [r7, #4] + 8006164: 681b ldr r3, [r3, #0] + 8006166: f003 0320 and.w r3, r3, #32 + 800616a: 2b00 cmp r3, #0 + 800616c: f000 808b beq.w 8006286 + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + 8006170: 4b3a ldr r3, [pc, #232] ; (800625c ) + 8006172: 6c1b ldr r3, [r3, #64] ; 0x40 + 8006174: 4a39 ldr r2, [pc, #228] ; (800625c ) + 8006176: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 800617a: 6413 str r3, [r2, #64] ; 0x40 + 800617c: 4b37 ldr r3, [pc, #220] ; (800625c ) + 800617e: 6c1b ldr r3, [r3, #64] ; 0x40 + 8006180: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8006184: 60bb str r3, [r7, #8] + 8006186: 68bb ldr r3, [r7, #8] + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + 8006188: 4b35 ldr r3, [pc, #212] ; (8006260 ) + 800618a: 681b ldr r3, [r3, #0] + 800618c: 4a34 ldr r2, [pc, #208] ; (8006260 ) + 800618e: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8006192: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8006194: f7ff f81e bl 80051d4 + 8006198: 6178 str r0, [r7, #20] + + /* Wait for Backup domain Write protection disable */ + while((PWR->CR1 & PWR_CR1_DBP) == RESET) + 800619a: e008 b.n 80061ae + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 800619c: f7ff f81a bl 80051d4 + 80061a0: 4602 mov r2, r0 + 80061a2: 697b ldr r3, [r7, #20] + 80061a4: 1ad3 subs r3, r2, r3 + 80061a6: 2b64 cmp r3, #100 ; 0x64 + 80061a8: d901 bls.n 80061ae + { + return HAL_TIMEOUT; + 80061aa: 2303 movs r3, #3 + 80061ac: e38d b.n 80068ca + while((PWR->CR1 & PWR_CR1_DBP) == RESET) + 80061ae: 4b2c ldr r3, [pc, #176] ; (8006260 ) + 80061b0: 681b ldr r3, [r3, #0] + 80061b2: f403 7380 and.w r3, r3, #256 ; 0x100 + 80061b6: 2b00 cmp r3, #0 + 80061b8: d0f0 beq.n 800619c + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); + 80061ba: 4b28 ldr r3, [pc, #160] ; (800625c ) + 80061bc: 6f1b ldr r3, [r3, #112] ; 0x70 + 80061be: f403 7340 and.w r3, r3, #768 ; 0x300 + 80061c2: 613b str r3, [r7, #16] + + if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + 80061c4: 693b ldr r3, [r7, #16] + 80061c6: 2b00 cmp r3, #0 + 80061c8: d035 beq.n 8006236 + 80061ca: 687b ldr r3, [r7, #4] + 80061cc: 6b1b ldr r3, [r3, #48] ; 0x30 + 80061ce: f403 7340 and.w r3, r3, #768 ; 0x300 + 80061d2: 693a ldr r2, [r7, #16] + 80061d4: 429a cmp r2, r3 + 80061d6: d02e beq.n 8006236 + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + 80061d8: 4b20 ldr r3, [pc, #128] ; (800625c ) + 80061da: 6f1b ldr r3, [r3, #112] ; 0x70 + 80061dc: f423 7340 bic.w r3, r3, #768 ; 0x300 + 80061e0: 613b str r3, [r7, #16] + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + 80061e2: 4b1e ldr r3, [pc, #120] ; (800625c ) + 80061e4: 6f1b ldr r3, [r3, #112] ; 0x70 + 80061e6: 4a1d ldr r2, [pc, #116] ; (800625c ) + 80061e8: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80061ec: 6713 str r3, [r2, #112] ; 0x70 + __HAL_RCC_BACKUPRESET_RELEASE(); + 80061ee: 4b1b ldr r3, [pc, #108] ; (800625c ) + 80061f0: 6f1b ldr r3, [r3, #112] ; 0x70 + 80061f2: 4a1a ldr r2, [pc, #104] ; (800625c ) + 80061f4: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 80061f8: 6713 str r3, [r2, #112] ; 0x70 + + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg0; + 80061fa: 4a18 ldr r2, [pc, #96] ; (800625c ) + 80061fc: 693b ldr r3, [r7, #16] + 80061fe: 6713 str r3, [r2, #112] ; 0x70 + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + 8006200: 4b16 ldr r3, [pc, #88] ; (800625c ) + 8006202: 6f1b ldr r3, [r3, #112] ; 0x70 + 8006204: f003 0301 and.w r3, r3, #1 + 8006208: 2b01 cmp r3, #1 + 800620a: d114 bne.n 8006236 + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800620c: f7fe ffe2 bl 80051d4 + 8006210: 6178 str r0, [r7, #20] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8006212: e00a b.n 800622a + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8006214: f7fe ffde bl 80051d4 + 8006218: 4602 mov r2, r0 + 800621a: 697b ldr r3, [r7, #20] + 800621c: 1ad3 subs r3, r2, r3 + 800621e: f241 3288 movw r2, #5000 ; 0x1388 + 8006222: 4293 cmp r3, r2 + 8006224: d901 bls.n 800622a + { + return HAL_TIMEOUT; + 8006226: 2303 movs r3, #3 + 8006228: e34f b.n 80068ca + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 800622a: 4b0c ldr r3, [pc, #48] ; (800625c ) + 800622c: 6f1b ldr r3, [r3, #112] ; 0x70 + 800622e: f003 0302 and.w r3, r3, #2 + 8006232: 2b00 cmp r3, #0 + 8006234: d0ee beq.n 8006214 + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 8006236: 687b ldr r3, [r7, #4] + 8006238: 6b1b ldr r3, [r3, #48] ; 0x30 + 800623a: f403 7340 and.w r3, r3, #768 ; 0x300 + 800623e: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 8006242: d111 bne.n 8006268 + 8006244: 4b05 ldr r3, [pc, #20] ; (800625c ) + 8006246: 689b ldr r3, [r3, #8] + 8006248: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000 + 800624c: 687b ldr r3, [r7, #4] + 800624e: 6b19 ldr r1, [r3, #48] ; 0x30 + 8006250: 4b04 ldr r3, [pc, #16] ; (8006264 ) + 8006252: 400b ands r3, r1 + 8006254: 4901 ldr r1, [pc, #4] ; (800625c ) + 8006256: 4313 orrs r3, r2 + 8006258: 608b str r3, [r1, #8] + 800625a: e00b b.n 8006274 + 800625c: 40023800 .word 0x40023800 + 8006260: 40007000 .word 0x40007000 + 8006264: 0ffffcff .word 0x0ffffcff + 8006268: 4bb3 ldr r3, [pc, #716] ; (8006538 ) + 800626a: 689b ldr r3, [r3, #8] + 800626c: 4ab2 ldr r2, [pc, #712] ; (8006538 ) + 800626e: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000 + 8006272: 6093 str r3, [r2, #8] + 8006274: 4bb0 ldr r3, [pc, #704] ; (8006538 ) + 8006276: 6f1a ldr r2, [r3, #112] ; 0x70 + 8006278: 687b ldr r3, [r7, #4] + 800627a: 6b1b ldr r3, [r3, #48] ; 0x30 + 800627c: f3c3 030b ubfx r3, r3, #0, #12 + 8006280: 49ad ldr r1, [pc, #692] ; (8006538 ) + 8006282: 4313 orrs r3, r2 + 8006284: 670b str r3, [r1, #112] ; 0x70 + } + + /*------------------------------------ TIM configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + 8006286: 687b ldr r3, [r7, #4] + 8006288: 681b ldr r3, [r3, #0] + 800628a: f003 0310 and.w r3, r3, #16 + 800628e: 2b00 cmp r3, #0 + 8006290: d010 beq.n 80062b4 + { + /* Check the parameters */ + assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + 8006292: 4ba9 ldr r3, [pc, #676] ; (8006538 ) + 8006294: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8006298: 4aa7 ldr r2, [pc, #668] ; (8006538 ) + 800629a: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 800629e: f8c2 308c str.w r3, [r2, #140] ; 0x8c + 80062a2: 4ba5 ldr r3, [pc, #660] ; (8006538 ) + 80062a4: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c + 80062a8: 687b ldr r3, [r7, #4] + 80062aa: 6b9b ldr r3, [r3, #56] ; 0x38 + 80062ac: 49a2 ldr r1, [pc, #648] ; (8006538 ) + 80062ae: 4313 orrs r3, r2 + 80062b0: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } + + /*-------------------------------------- I2C1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 80062b4: 687b ldr r3, [r7, #4] + 80062b6: 681b ldr r3, [r3, #0] + 80062b8: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 80062bc: 2b00 cmp r3, #0 + 80062be: d00a beq.n 80062d6 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 80062c0: 4b9d ldr r3, [pc, #628] ; (8006538 ) + 80062c2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80062c6: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 80062ca: 687b ldr r3, [r7, #4] + 80062cc: 6e5b ldr r3, [r3, #100] ; 0x64 + 80062ce: 499a ldr r1, [pc, #616] ; (8006538 ) + 80062d0: 4313 orrs r3, r2 + 80062d2: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- I2C2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + 80062d6: 687b ldr r3, [r7, #4] + 80062d8: 681b ldr r3, [r3, #0] + 80062da: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 80062de: 2b00 cmp r3, #0 + 80062e0: d00a beq.n 80062f8 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + 80062e2: 4b95 ldr r3, [pc, #596] ; (8006538 ) + 80062e4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80062e8: f423 2240 bic.w r2, r3, #786432 ; 0xc0000 + 80062ec: 687b ldr r3, [r7, #4] + 80062ee: 6e9b ldr r3, [r3, #104] ; 0x68 + 80062f0: 4991 ldr r1, [pc, #580] ; (8006538 ) + 80062f2: 4313 orrs r3, r2 + 80062f4: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- I2C3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + 80062f8: 687b ldr r3, [r7, #4] + 80062fa: 681b ldr r3, [r3, #0] + 80062fc: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8006300: 2b00 cmp r3, #0 + 8006302: d00a beq.n 800631a + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + 8006304: 4b8c ldr r3, [pc, #560] ; (8006538 ) + 8006306: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800630a: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 + 800630e: 687b ldr r3, [r7, #4] + 8006310: 6edb ldr r3, [r3, #108] ; 0x6c + 8006312: 4989 ldr r1, [pc, #548] ; (8006538 ) + 8006314: 4313 orrs r3, r2 + 8006316: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- I2C4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) + 800631a: 687b ldr r3, [r7, #4] + 800631c: 681b ldr r3, [r3, #0] + 800631e: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8006322: 2b00 cmp r3, #0 + 8006324: d00a beq.n 800633c + { + /* Check the parameters */ + assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); + + /* Configure the I2C4 clock source */ + __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); + 8006326: 4b84 ldr r3, [pc, #528] ; (8006538 ) + 8006328: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800632c: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 + 8006330: 687b ldr r3, [r7, #4] + 8006332: 6f1b ldr r3, [r3, #112] ; 0x70 + 8006334: 4980 ldr r1, [pc, #512] ; (8006538 ) + 8006336: 4313 orrs r3, r2 + 8006338: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 800633c: 687b ldr r3, [r7, #4] + 800633e: 681b ldr r3, [r3, #0] + 8006340: f003 0340 and.w r3, r3, #64 ; 0x40 + 8006344: 2b00 cmp r3, #0 + 8006346: d00a beq.n 800635e + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 8006348: 4b7b ldr r3, [pc, #492] ; (8006538 ) + 800634a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800634e: f023 0203 bic.w r2, r3, #3 + 8006352: 687b ldr r3, [r7, #4] + 8006354: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006356: 4978 ldr r1, [pc, #480] ; (8006538 ) + 8006358: 4313 orrs r3, r2 + 800635a: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 800635e: 687b ldr r3, [r7, #4] + 8006360: 681b ldr r3, [r3, #0] + 8006362: f003 0380 and.w r3, r3, #128 ; 0x80 + 8006366: 2b00 cmp r3, #0 + 8006368: d00a beq.n 8006380 + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 800636a: 4b73 ldr r3, [pc, #460] ; (8006538 ) + 800636c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8006370: f023 020c bic.w r2, r3, #12 + 8006374: 687b ldr r3, [r7, #4] + 8006376: 6c9b ldr r3, [r3, #72] ; 0x48 + 8006378: 496f ldr r1, [pc, #444] ; (8006538 ) + 800637a: 4313 orrs r3, r2 + 800637c: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + 8006380: 687b ldr r3, [r7, #4] + 8006382: 681b ldr r3, [r3, #0] + 8006384: f403 7380 and.w r3, r3, #256 ; 0x100 + 8006388: 2b00 cmp r3, #0 + 800638a: d00a beq.n 80063a2 + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + 800638c: 4b6a ldr r3, [pc, #424] ; (8006538 ) + 800638e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8006392: f023 0230 bic.w r2, r3, #48 ; 0x30 + 8006396: 687b ldr r3, [r7, #4] + 8006398: 6cdb ldr r3, [r3, #76] ; 0x4c + 800639a: 4967 ldr r1, [pc, #412] ; (8006538 ) + 800639c: 4313 orrs r3, r2 + 800639e: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + 80063a2: 687b ldr r3, [r7, #4] + 80063a4: 681b ldr r3, [r3, #0] + 80063a6: f403 7300 and.w r3, r3, #512 ; 0x200 + 80063aa: 2b00 cmp r3, #0 + 80063ac: d00a beq.n 80063c4 + { + /* Check the parameters */ + assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); + + /* Configure the UART4 clock source */ + __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); + 80063ae: 4b62 ldr r3, [pc, #392] ; (8006538 ) + 80063b0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80063b4: f023 02c0 bic.w r2, r3, #192 ; 0xc0 + 80063b8: 687b ldr r3, [r7, #4] + 80063ba: 6d1b ldr r3, [r3, #80] ; 0x50 + 80063bc: 495e ldr r1, [pc, #376] ; (8006538 ) + 80063be: 4313 orrs r3, r2 + 80063c0: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART5 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + 80063c4: 687b ldr r3, [r7, #4] + 80063c6: 681b ldr r3, [r3, #0] + 80063c8: f403 6380 and.w r3, r3, #1024 ; 0x400 + 80063cc: 2b00 cmp r3, #0 + 80063ce: d00a beq.n 80063e6 + { + /* Check the parameters */ + assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); + + /* Configure the UART5 clock source */ + __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); + 80063d0: 4b59 ldr r3, [pc, #356] ; (8006538 ) + 80063d2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80063d6: f423 7240 bic.w r2, r3, #768 ; 0x300 + 80063da: 687b ldr r3, [r7, #4] + 80063dc: 6d5b ldr r3, [r3, #84] ; 0x54 + 80063de: 4956 ldr r1, [pc, #344] ; (8006538 ) + 80063e0: 4313 orrs r3, r2 + 80063e2: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART6 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) + 80063e6: 687b ldr r3, [r7, #4] + 80063e8: 681b ldr r3, [r3, #0] + 80063ea: f403 6300 and.w r3, r3, #2048 ; 0x800 + 80063ee: 2b00 cmp r3, #0 + 80063f0: d00a beq.n 8006408 + { + /* Check the parameters */ + assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); + + /* Configure the USART6 clock source */ + __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); + 80063f2: 4b51 ldr r3, [pc, #324] ; (8006538 ) + 80063f4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80063f8: f423 6240 bic.w r2, r3, #3072 ; 0xc00 + 80063fc: 687b ldr r3, [r7, #4] + 80063fe: 6d9b ldr r3, [r3, #88] ; 0x58 + 8006400: 494d ldr r1, [pc, #308] ; (8006538 ) + 8006402: 4313 orrs r3, r2 + 8006404: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART7 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) + 8006408: 687b ldr r3, [r7, #4] + 800640a: 681b ldr r3, [r3, #0] + 800640c: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8006410: 2b00 cmp r3, #0 + 8006412: d00a beq.n 800642a + { + /* Check the parameters */ + assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); + + /* Configure the UART7 clock source */ + __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); + 8006414: 4b48 ldr r3, [pc, #288] ; (8006538 ) + 8006416: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800641a: f423 5240 bic.w r2, r3, #12288 ; 0x3000 + 800641e: 687b ldr r3, [r7, #4] + 8006420: 6ddb ldr r3, [r3, #92] ; 0x5c + 8006422: 4945 ldr r1, [pc, #276] ; (8006538 ) + 8006424: 4313 orrs r3, r2 + 8006426: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART8 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) + 800642a: 687b ldr r3, [r7, #4] + 800642c: 681b ldr r3, [r3, #0] + 800642e: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8006432: 2b00 cmp r3, #0 + 8006434: d00a beq.n 800644c + { + /* Check the parameters */ + assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); + + /* Configure the UART8 clock source */ + __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); + 8006436: 4b40 ldr r3, [pc, #256] ; (8006538 ) + 8006438: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800643c: f423 4240 bic.w r2, r3, #49152 ; 0xc000 + 8006440: 687b ldr r3, [r7, #4] + 8006442: 6e1b ldr r3, [r3, #96] ; 0x60 + 8006444: 493c ldr r1, [pc, #240] ; (8006538 ) + 8006446: 4313 orrs r3, r2 + 8006448: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*--------------------------------------- CEC Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + 800644c: 687b ldr r3, [r7, #4] + 800644e: 681b ldr r3, [r3, #0] + 8006450: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8006454: 2b00 cmp r3, #0 + 8006456: d00a beq.n 800646e + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + 8006458: 4b37 ldr r3, [pc, #220] ; (8006538 ) + 800645a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800645e: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 + 8006462: 687b ldr r3, [r7, #4] + 8006464: 6f9b ldr r3, [r3, #120] ; 0x78 + 8006466: 4934 ldr r1, [pc, #208] ; (8006538 ) + 8006468: 4313 orrs r3, r2 + 800646a: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- CK48 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + 800646e: 687b ldr r3, [r7, #4] + 8006470: 681b ldr r3, [r3, #0] + 8006472: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8006476: 2b00 cmp r3, #0 + 8006478: d011 beq.n 800649e + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + 800647a: 4b2f ldr r3, [pc, #188] ; (8006538 ) + 800647c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8006480: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000 + 8006484: 687b ldr r3, [r7, #4] + 8006486: 6fdb ldr r3, [r3, #124] ; 0x7c + 8006488: 492b ldr r1, [pc, #172] ; (8006538 ) + 800648a: 4313 orrs r3, r2 + 800648c: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + + /* Enable the PLLSAI when it's used as clock source for CK48 */ + if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) + 8006490: 687b ldr r3, [r7, #4] + 8006492: 6fdb ldr r3, [r3, #124] ; 0x7c + 8006494: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 + 8006498: d101 bne.n 800649e + { + pllsaiused = 1; + 800649a: 2301 movs r3, #1 + 800649c: 61bb str r3, [r7, #24] + } + } + + /*-------------------------------------- LTDC Configuration -----------------------------------*/ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + 800649e: 687b ldr r3, [r7, #4] + 80064a0: 681b ldr r3, [r3, #0] + 80064a2: f003 0308 and.w r3, r3, #8 + 80064a6: 2b00 cmp r3, #0 + 80064a8: d001 beq.n 80064ae + { + pllsaiused = 1; + 80064aa: 2301 movs r3, #1 + 80064ac: 61bb str r3, [r7, #24] + } +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + 80064ae: 687b ldr r3, [r7, #4] + 80064b0: 681b ldr r3, [r3, #0] + 80064b2: f403 2380 and.w r3, r3, #262144 ; 0x40000 + 80064b6: 2b00 cmp r3, #0 + 80064b8: d00a beq.n 80064d0 + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LTPIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + 80064ba: 4b1f ldr r3, [pc, #124] ; (8006538 ) + 80064bc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80064c0: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000 + 80064c4: 687b ldr r3, [r7, #4] + 80064c6: 6f5b ldr r3, [r3, #116] ; 0x74 + 80064c8: 491b ldr r1, [pc, #108] ; (8006538 ) + 80064ca: 4313 orrs r3, r2 + 80064cc: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) + 80064d0: 687b ldr r3, [r7, #4] + 80064d2: 681b ldr r3, [r3, #0] + 80064d4: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 80064d8: 2b00 cmp r3, #0 + 80064da: d00b beq.n 80064f4 + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); + + /* Configure the SDMMC1 clock source */ + __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); + 80064dc: 4b16 ldr r3, [pc, #88] ; (8006538 ) + 80064de: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80064e2: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000 + 80064e6: 687b ldr r3, [r7, #4] + 80064e8: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 80064ec: 4912 ldr r1, [pc, #72] ; (8006538 ) + 80064ee: 4313 orrs r3, r2 + 80064f0: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) + 80064f4: 687b ldr r3, [r7, #4] + 80064f6: 681b ldr r3, [r3, #0] + 80064f8: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 80064fc: 2b00 cmp r3, #0 + 80064fe: d00b beq.n 8006518 + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); + + /* Configure the SDMMC2 clock source */ + __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); + 8006500: 4b0d ldr r3, [pc, #52] ; (8006538 ) + 8006502: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8006506: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000 + 800650a: 687b ldr r3, [r7, #4] + 800650c: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8006510: 4909 ldr r1, [pc, #36] ; (8006538 ) + 8006512: 4313 orrs r3, r2 + 8006514: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*------------------------------------- DFSDM1 Configuration -------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) + 8006518: 687b ldr r3, [r7, #4] + 800651a: 681b ldr r3, [r3, #0] + 800651c: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 8006520: 2b00 cmp r3, #0 + 8006522: d00f beq.n 8006544 + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); + + /* Configure the DFSDM1 interface clock source */ + __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); + 8006524: 4b04 ldr r3, [pc, #16] ; (8006538 ) + 8006526: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 800652a: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000 + 800652e: 687b ldr r3, [r7, #4] + 8006530: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8006534: e002 b.n 800653c + 8006536: bf00 nop + 8006538: 40023800 .word 0x40023800 + 800653c: 4985 ldr r1, [pc, #532] ; (8006754 ) + 800653e: 4313 orrs r3, r2 + 8006540: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } + + /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) + 8006544: 687b ldr r3, [r7, #4] + 8006546: 681b ldr r3, [r3, #0] + 8006548: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 800654c: 2b00 cmp r3, #0 + 800654e: d00b beq.n 8006568 + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); + + /* Configure the DFSDM interface clock source */ + __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); + 8006550: 4b80 ldr r3, [pc, #512] ; (8006754 ) + 8006552: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8006556: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 + 800655a: 687b ldr r3, [r7, #4] + 800655c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8006560: 497c ldr r1, [pc, #496] ; (8006754 ) + 8006562: 4313 orrs r3, r2 + 8006564: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + + /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ + /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ + if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) + 8006568: 69fb ldr r3, [r7, #28] + 800656a: 2b01 cmp r3, #1 + 800656c: d005 beq.n 800657a + 800656e: 687b ldr r3, [r7, #4] + 8006570: 681b ldr r3, [r3, #0] + 8006572: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 + 8006576: f040 80d6 bne.w 8006726 + { + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + 800657a: 4b76 ldr r3, [pc, #472] ; (8006754 ) + 800657c: 681b ldr r3, [r3, #0] + 800657e: 4a75 ldr r2, [pc, #468] ; (8006754 ) + 8006580: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 + 8006584: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8006586: f7fe fe25 bl 80051d4 + 800658a: 6178 str r0, [r7, #20] + + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + 800658c: e008 b.n 80065a0 + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + 800658e: f7fe fe21 bl 80051d4 + 8006592: 4602 mov r2, r0 + 8006594: 697b ldr r3, [r7, #20] + 8006596: 1ad3 subs r3, r2, r3 + 8006598: 2b64 cmp r3, #100 ; 0x64 + 800659a: d901 bls.n 80065a0 + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 800659c: 2303 movs r3, #3 + 800659e: e194 b.n 80068ca + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + 80065a0: 4b6c ldr r3, [pc, #432] ; (8006754 ) + 80065a2: 681b ldr r3, [r3, #0] + 80065a4: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 80065a8: 2b00 cmp r3, #0 + 80065aa: d1f0 bne.n 800658e + + /* check for common PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) + 80065ac: 687b ldr r3, [r7, #4] + 80065ae: 681b ldr r3, [r3, #0] + 80065b0: f003 0301 and.w r3, r3, #1 + 80065b4: 2b00 cmp r3, #0 + 80065b6: d021 beq.n 80065fc + 80065b8: 687b ldr r3, [r7, #4] + 80065ba: 6b5b ldr r3, [r3, #52] ; 0x34 + 80065bc: 2b00 cmp r3, #0 + 80065be: d11d bne.n 80065fc + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + 80065c0: 4b64 ldr r3, [pc, #400] ; (8006754 ) + 80065c2: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 80065c6: 0c1b lsrs r3, r3, #16 + 80065c8: f003 0303 and.w r3, r3, #3 + 80065cc: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + 80065ce: 4b61 ldr r3, [pc, #388] ; (8006754 ) + 80065d0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 80065d4: 0e1b lsrs r3, r3, #24 + 80065d6: f003 030f and.w r3, r3, #15 + 80065da: 60fb str r3, [r7, #12] + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR); + 80065dc: 687b ldr r3, [r7, #4] + 80065de: 685b ldr r3, [r3, #4] + 80065e0: 019a lsls r2, r3, #6 + 80065e2: 693b ldr r3, [r7, #16] + 80065e4: 041b lsls r3, r3, #16 + 80065e6: 431a orrs r2, r3 + 80065e8: 68fb ldr r3, [r7, #12] + 80065ea: 061b lsls r3, r3, #24 + 80065ec: 431a orrs r2, r3 + 80065ee: 687b ldr r3, [r7, #4] + 80065f0: 689b ldr r3, [r3, #8] + 80065f2: 071b lsls r3, r3, #28 + 80065f4: 4957 ldr r1, [pc, #348] ; (8006754 ) + 80065f6: 4313 orrs r3, r2 + 80065f8: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + } + + /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + 80065fc: 687b ldr r3, [r7, #4] + 80065fe: 681b ldr r3, [r3, #0] + 8006600: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 8006604: 2b00 cmp r3, #0 + 8006606: d004 beq.n 8006612 + 8006608: 687b ldr r3, [r7, #4] + 800660a: 6bdb ldr r3, [r3, #60] ; 0x3c + 800660c: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 8006610: d00a beq.n 8006628 + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + 8006612: 687b ldr r3, [r7, #4] + 8006614: 681b ldr r3, [r3, #0] + 8006616: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + 800661a: 2b00 cmp r3, #0 + 800661c: d02e beq.n 800667c + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + 800661e: 687b ldr r3, [r7, #4] + 8006620: 6c1b ldr r3, [r3, #64] ; 0x40 + 8006622: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 8006626: d129 bne.n 800667c + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + /* Check for PLLI2S/DIVQ parameters */ + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + 8006628: 4b4a ldr r3, [pc, #296] ; (8006754 ) + 800662a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800662e: 0c1b lsrs r3, r3, #16 + 8006630: f003 0303 and.w r3, r3, #3 + 8006634: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + 8006636: 4b47 ldr r3, [pc, #284] ; (8006754 ) + 8006638: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800663c: 0f1b lsrs r3, r3, #28 + 800663e: f003 0307 and.w r3, r3, #7 + 8006642: 60fb str r3, [r7, #12] + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); + 8006644: 687b ldr r3, [r7, #4] + 8006646: 685b ldr r3, [r3, #4] + 8006648: 019a lsls r2, r3, #6 + 800664a: 693b ldr r3, [r7, #16] + 800664c: 041b lsls r3, r3, #16 + 800664e: 431a orrs r2, r3 + 8006650: 687b ldr r3, [r7, #4] + 8006652: 68db ldr r3, [r3, #12] + 8006654: 061b lsls r3, r3, #24 + 8006656: 431a orrs r2, r3 + 8006658: 68fb ldr r3, [r7, #12] + 800665a: 071b lsls r3, r3, #28 + 800665c: 493d ldr r1, [pc, #244] ; (8006754 ) + 800665e: 4313 orrs r3, r2 + 8006660: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + 8006664: 4b3b ldr r3, [pc, #236] ; (8006754 ) + 8006666: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 800666a: f023 021f bic.w r2, r3, #31 + 800666e: 687b ldr r3, [r7, #4] + 8006670: 6a5b ldr r3, [r3, #36] ; 0x24 + 8006672: 3b01 subs r3, #1 + 8006674: 4937 ldr r1, [pc, #220] ; (8006754 ) + 8006676: 4313 orrs r3, r2 + 8006678: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } + + /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + 800667c: 687b ldr r3, [r7, #4] + 800667e: 681b ldr r3, [r3, #0] + 8006680: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 8006684: 2b00 cmp r3, #0 + 8006686: d01d beq.n 80066c4 + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + 8006688: 4b32 ldr r3, [pc, #200] ; (8006754 ) + 800668a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800668e: 0e1b lsrs r3, r3, #24 + 8006690: f003 030f and.w r3, r3, #15 + 8006694: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + 8006696: 4b2f ldr r3, [pc, #188] ; (8006754 ) + 8006698: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800669c: 0f1b lsrs r3, r3, #28 + 800669e: f003 0307 and.w r3, r3, #7 + 80066a2: 60fb str r3, [r7, #12] + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1); + 80066a4: 687b ldr r3, [r7, #4] + 80066a6: 685b ldr r3, [r3, #4] + 80066a8: 019a lsls r2, r3, #6 + 80066aa: 687b ldr r3, [r7, #4] + 80066ac: 691b ldr r3, [r3, #16] + 80066ae: 041b lsls r3, r3, #16 + 80066b0: 431a orrs r2, r3 + 80066b2: 693b ldr r3, [r7, #16] + 80066b4: 061b lsls r3, r3, #24 + 80066b6: 431a orrs r2, r3 + 80066b8: 68fb ldr r3, [r7, #12] + 80066ba: 071b lsls r3, r3, #28 + 80066bc: 4925 ldr r1, [pc, #148] ; (8006754 ) + 80066be: 4313 orrs r3, r2 + 80066c0: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + 80066c4: 687b ldr r3, [r7, #4] + 80066c6: 681b ldr r3, [r3, #0] + 80066c8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 80066cc: 2b00 cmp r3, #0 + 80066ce: d011 beq.n 80066f4 + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ + /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + 80066d0: 687b ldr r3, [r7, #4] + 80066d2: 685b ldr r3, [r3, #4] + 80066d4: 019a lsls r2, r3, #6 + 80066d6: 687b ldr r3, [r7, #4] + 80066d8: 691b ldr r3, [r3, #16] + 80066da: 041b lsls r3, r3, #16 + 80066dc: 431a orrs r2, r3 + 80066de: 687b ldr r3, [r7, #4] + 80066e0: 68db ldr r3, [r3, #12] + 80066e2: 061b lsls r3, r3, #24 + 80066e4: 431a orrs r2, r3 + 80066e6: 687b ldr r3, [r7, #4] + 80066e8: 689b ldr r3, [r3, #8] + 80066ea: 071b lsls r3, r3, #28 + 80066ec: 4919 ldr r1, [pc, #100] ; (8006754 ) + 80066ee: 4313 orrs r3, r2 + 80066f0: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + 80066f4: 4b17 ldr r3, [pc, #92] ; (8006754 ) + 80066f6: 681b ldr r3, [r3, #0] + 80066f8: 4a16 ldr r2, [pc, #88] ; (8006754 ) + 80066fa: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 + 80066fe: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8006700: f7fe fd68 bl 80051d4 + 8006704: 6178 str r0, [r7, #20] + + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 8006706: e008 b.n 800671a + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + 8006708: f7fe fd64 bl 80051d4 + 800670c: 4602 mov r2, r0 + 800670e: 697b ldr r3, [r7, #20] + 8006710: 1ad3 subs r3, r2, r3 + 8006712: 2b64 cmp r3, #100 ; 0x64 + 8006714: d901 bls.n 800671a + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 8006716: 2303 movs r3, #3 + 8006718: e0d7 b.n 80068ca + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 800671a: 4b0e ldr r3, [pc, #56] ; (8006754 ) + 800671c: 681b ldr r3, [r3, #0] + 800671e: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 8006722: 2b00 cmp r3, #0 + 8006724: d0f0 beq.n 8006708 + } + } + + /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ + /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ + if(pllsaiused == 1) + 8006726: 69bb ldr r3, [r7, #24] + 8006728: 2b01 cmp r3, #1 + 800672a: f040 80cd bne.w 80068c8 + { + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + 800672e: 4b09 ldr r3, [pc, #36] ; (8006754 ) + 8006730: 681b ldr r3, [r3, #0] + 8006732: 4a08 ldr r2, [pc, #32] ; (8006754 ) + 8006734: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 8006738: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800673a: f7fe fd4b bl 80051d4 + 800673e: 6178 str r0, [r7, #20] + + /* Wait till PLLSAI is disabled */ + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + 8006740: e00a b.n 8006758 + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + 8006742: f7fe fd47 bl 80051d4 + 8006746: 4602 mov r2, r0 + 8006748: 697b ldr r3, [r7, #20] + 800674a: 1ad3 subs r3, r2, r3 + 800674c: 2b64 cmp r3, #100 ; 0x64 + 800674e: d903 bls.n 8006758 + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 8006750: 2303 movs r3, #3 + 8006752: e0ba b.n 80068ca + 8006754: 40023800 .word 0x40023800 + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + 8006758: 4b5e ldr r3, [pc, #376] ; (80068d4 ) + 800675a: 681b ldr r3, [r3, #0] + 800675c: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 8006760: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 8006764: d0ed beq.n 8006742 + + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ + 8006766: 687b ldr r3, [r7, #4] + 8006768: 681b ldr r3, [r3, #0] + 800676a: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 800676e: 2b00 cmp r3, #0 + 8006770: d003 beq.n 800677a + 8006772: 687b ldr r3, [r7, #4] + 8006774: 6bdb ldr r3, [r3, #60] ; 0x3c + 8006776: 2b00 cmp r3, #0 + 8006778: d009 beq.n 800678e + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + 800677a: 687b ldr r3, [r7, #4] + 800677c: 681b ldr r3, [r3, #0] + 800677e: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ + 8006782: 2b00 cmp r3, #0 + 8006784: d02e beq.n 80067e4 + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + 8006786: 687b ldr r3, [r7, #4] + 8006788: 6c1b ldr r3, [r3, #64] ; 0x40 + 800678a: 2b00 cmp r3, #0 + 800678c: d12a bne.n 80067e4 + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + /* check for PLLSAI/DIVQ Parameter */ + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + 800678e: 4b51 ldr r3, [pc, #324] ; (80068d4 ) + 8006790: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8006794: 0c1b lsrs r3, r3, #16 + 8006796: f003 0303 and.w r3, r3, #3 + 800679a: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + 800679c: 4b4d ldr r3, [pc, #308] ; (80068d4 ) + 800679e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 80067a2: 0f1b lsrs r3, r3, #28 + 80067a4: f003 0307 and.w r3, r3, #7 + 80067a8: 60fb str r3, [r7, #12] + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); + 80067aa: 687b ldr r3, [r7, #4] + 80067ac: 695b ldr r3, [r3, #20] + 80067ae: 019a lsls r2, r3, #6 + 80067b0: 693b ldr r3, [r7, #16] + 80067b2: 041b lsls r3, r3, #16 + 80067b4: 431a orrs r2, r3 + 80067b6: 687b ldr r3, [r7, #4] + 80067b8: 699b ldr r3, [r3, #24] + 80067ba: 061b lsls r3, r3, #24 + 80067bc: 431a orrs r2, r3 + 80067be: 68fb ldr r3, [r7, #12] + 80067c0: 071b lsls r3, r3, #28 + 80067c2: 4944 ldr r1, [pc, #272] ; (80068d4 ) + 80067c4: 4313 orrs r3, r2 + 80067c6: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + 80067ca: 4b42 ldr r3, [pc, #264] ; (80068d4 ) + 80067cc: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 80067d0: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00 + 80067d4: 687b ldr r3, [r7, #4] + 80067d6: 6a9b ldr r3, [r3, #40] ; 0x28 + 80067d8: 3b01 subs r3, #1 + 80067da: 021b lsls r3, r3, #8 + 80067dc: 493d ldr r1, [pc, #244] ; (80068d4 ) + 80067de: 4313 orrs r3, r2 + 80067e0: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } + + /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ + /* In Case of PLLI2S is selected as source clock for CK48 */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) + 80067e4: 687b ldr r3, [r7, #4] + 80067e6: 681b ldr r3, [r3, #0] + 80067e8: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 80067ec: 2b00 cmp r3, #0 + 80067ee: d022 beq.n 8006836 + 80067f0: 687b ldr r3, [r7, #4] + 80067f2: 6fdb ldr r3, [r3, #124] ; 0x7c + 80067f4: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 + 80067f8: d11d bne.n 8006836 + { + /* check for Parameters */ + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + 80067fa: 4b36 ldr r3, [pc, #216] ; (80068d4 ) + 80067fc: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8006800: 0e1b lsrs r3, r3, #24 + 8006802: f003 030f and.w r3, r3, #15 + 8006806: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + 8006808: 4b32 ldr r3, [pc, #200] ; (80068d4 ) + 800680a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800680e: 0f1b lsrs r3, r3, #28 + 8006810: f003 0307 and.w r3, r3, #7 + 8006814: 60fb str r3, [r7, #12] + + /* Configure the PLLSAI division factors */ + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ + /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); + 8006816: 687b ldr r3, [r7, #4] + 8006818: 695b ldr r3, [r3, #20] + 800681a: 019a lsls r2, r3, #6 + 800681c: 687b ldr r3, [r7, #4] + 800681e: 6a1b ldr r3, [r3, #32] + 8006820: 041b lsls r3, r3, #16 + 8006822: 431a orrs r2, r3 + 8006824: 693b ldr r3, [r7, #16] + 8006826: 061b lsls r3, r3, #24 + 8006828: 431a orrs r2, r3 + 800682a: 68fb ldr r3, [r7, #12] + 800682c: 071b lsls r3, r3, #28 + 800682e: 4929 ldr r1, [pc, #164] ; (80068d4 ) + 8006830: 4313 orrs r3, r2 + 8006832: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + } + +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + /*---------------------------- LTDC configuration -------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) + 8006836: 687b ldr r3, [r7, #4] + 8006838: 681b ldr r3, [r3, #0] + 800683a: f003 0308 and.w r3, r3, #8 + 800683e: 2b00 cmp r3, #0 + 8006840: d028 beq.n 8006894 + { + assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); + assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); + + /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + 8006842: 4b24 ldr r3, [pc, #144] ; (80068d4 ) + 8006844: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8006848: 0e1b lsrs r3, r3, #24 + 800684a: f003 030f and.w r3, r3, #15 + 800684e: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + 8006850: 4b20 ldr r3, [pc, #128] ; (80068d4 ) + 8006852: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8006856: 0c1b lsrs r3, r3, #16 + 8006858: f003 0303 and.w r3, r3, #3 + 800685c: 60fb str r3, [r7, #12] + + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR); + 800685e: 687b ldr r3, [r7, #4] + 8006860: 695b ldr r3, [r3, #20] + 8006862: 019a lsls r2, r3, #6 + 8006864: 68fb ldr r3, [r7, #12] + 8006866: 041b lsls r3, r3, #16 + 8006868: 431a orrs r2, r3 + 800686a: 693b ldr r3, [r7, #16] + 800686c: 061b lsls r3, r3, #24 + 800686e: 431a orrs r2, r3 + 8006870: 687b ldr r3, [r7, #4] + 8006872: 69db ldr r3, [r3, #28] + 8006874: 071b lsls r3, r3, #28 + 8006876: 4917 ldr r1, [pc, #92] ; (80068d4 ) + 8006878: 4313 orrs r3, r2 + 800687a: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); + 800687e: 4b15 ldr r3, [pc, #84] ; (80068d4 ) + 8006880: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8006884: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 8006888: 687b ldr r3, [r7, #4] + 800688a: 6adb ldr r3, [r3, #44] ; 0x2c + 800688c: 4911 ldr r1, [pc, #68] ; (80068d4 ) + 800688e: 4313 orrs r3, r2 + 8006890: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + 8006894: 4b0f ldr r3, [pc, #60] ; (80068d4 ) + 8006896: 681b ldr r3, [r3, #0] + 8006898: 4a0e ldr r2, [pc, #56] ; (80068d4 ) + 800689a: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 800689e: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80068a0: f7fe fc98 bl 80051d4 + 80068a4: 6178 str r0, [r7, #20] + + /* Wait till PLLSAI is ready */ + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + 80068a6: e008 b.n 80068ba + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + 80068a8: f7fe fc94 bl 80051d4 + 80068ac: 4602 mov r2, r0 + 80068ae: 697b ldr r3, [r7, #20] + 80068b0: 1ad3 subs r3, r2, r3 + 80068b2: 2b64 cmp r3, #100 ; 0x64 + 80068b4: d901 bls.n 80068ba + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 80068b6: 2303 movs r3, #3 + 80068b8: e007 b.n 80068ca + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + 80068ba: 4b06 ldr r3, [pc, #24] ; (80068d4 ) + 80068bc: 681b ldr r3, [r3, #0] + 80068be: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 80068c2: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 80068c6: d1ef bne.n 80068a8 + } + } + } + return HAL_OK; + 80068c8: 2300 movs r3, #0 +} + 80068ca: 4618 mov r0, r3 + 80068cc: 3720 adds r7, #32 + 80068ce: 46bd mov sp, r7 + 80068d0: bd80 pop {r7, pc} + 80068d2: bf00 nop + 80068d4: 40023800 .word 0x40023800 + +080068d8 : + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + 80068d8: b580 push {r7, lr} + 80068da: b082 sub sp, #8 + 80068dc: af00 add r7, sp, #0 + 80068de: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 80068e0: 687b ldr r3, [r7, #4] + 80068e2: 2b00 cmp r3, #0 + 80068e4: d101 bne.n 80068ea + { + return HAL_ERROR; + 80068e6: 2301 movs r3, #1 + 80068e8: e01d b.n 8006926 + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 80068ea: 687b ldr r3, [r7, #4] + 80068ec: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 80068f0: b2db uxtb r3, r3 + 80068f2: 2b00 cmp r3, #0 + 80068f4: d106 bne.n 8006904 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 80068f6: 687b ldr r3, [r7, #4] + 80068f8: 2200 movs r2, #0 + 80068fa: f883 203c strb.w r2, [r3, #60] ; 0x3c + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); + 80068fe: 6878 ldr r0, [r7, #4] + 8006900: f7fe faa0 bl 8004e44 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8006904: 687b ldr r3, [r7, #4] + 8006906: 2202 movs r2, #2 + 8006908: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 800690c: 687b ldr r3, [r7, #4] + 800690e: 681a ldr r2, [r3, #0] + 8006910: 687b ldr r3, [r7, #4] + 8006912: 3304 adds r3, #4 + 8006914: 4619 mov r1, r3 + 8006916: 4610 mov r0, r2 + 8006918: f000 fc90 bl 800723c + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 800691c: 687b ldr r3, [r7, #4] + 800691e: 2201 movs r2, #1 + 8006920: f883 203d strb.w r2, [r3, #61] ; 0x3d + + return HAL_OK; + 8006924: 2300 movs r3, #0 +} + 8006926: 4618 mov r0, r3 + 8006928: 3708 adds r7, #8 + 800692a: 46bd mov sp, r7 + 800692c: bd80 pop {r7, pc} + ... + +08006930 : + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + 8006930: b480 push {r7} + 8006932: b085 sub sp, #20 + 8006934: af00 add r7, sp, #0 + 8006936: 6078 str r0, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + 8006938: 687b ldr r3, [r7, #4] + 800693a: 681b ldr r3, [r3, #0] + 800693c: 68da ldr r2, [r3, #12] + 800693e: 687b ldr r3, [r7, #4] + 8006940: 681b ldr r3, [r3, #0] + 8006942: f042 0201 orr.w r2, r2, #1 + 8006946: 60da str r2, [r3, #12] + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 8006948: 687b ldr r3, [r7, #4] + 800694a: 681b ldr r3, [r3, #0] + 800694c: 689a ldr r2, [r3, #8] + 800694e: 4b0c ldr r3, [pc, #48] ; (8006980 ) + 8006950: 4013 ands r3, r2 + 8006952: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8006954: 68fb ldr r3, [r7, #12] + 8006956: 2b06 cmp r3, #6 + 8006958: d00b beq.n 8006972 + 800695a: 68fb ldr r3, [r7, #12] + 800695c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8006960: d007 beq.n 8006972 + { + __HAL_TIM_ENABLE(htim); + 8006962: 687b ldr r3, [r7, #4] + 8006964: 681b ldr r3, [r3, #0] + 8006966: 681a ldr r2, [r3, #0] + 8006968: 687b ldr r3, [r7, #4] + 800696a: 681b ldr r3, [r3, #0] + 800696c: f042 0201 orr.w r2, r2, #1 + 8006970: 601a str r2, [r3, #0] + } + + /* Return function status */ + return HAL_OK; + 8006972: 2300 movs r3, #0 +} + 8006974: 4618 mov r0, r3 + 8006976: 3714 adds r7, #20 + 8006978: 46bd mov sp, r7 + 800697a: f85d 7b04 ldr.w r7, [sp], #4 + 800697e: 4770 bx lr + 8006980: 00010007 .word 0x00010007 + +08006984 : + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + 8006984: b580 push {r7, lr} + 8006986: b082 sub sp, #8 + 8006988: af00 add r7, sp, #0 + 800698a: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 800698c: 687b ldr r3, [r7, #4] + 800698e: 2b00 cmp r3, #0 + 8006990: d101 bne.n 8006996 + { + return HAL_ERROR; + 8006992: 2301 movs r3, #1 + 8006994: e01d b.n 80069d2 + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 8006996: 687b ldr r3, [r7, #4] + 8006998: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 800699c: b2db uxtb r3, r3 + 800699e: 2b00 cmp r3, #0 + 80069a0: d106 bne.n 80069b0 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 80069a2: 687b ldr r3, [r7, #4] + 80069a4: 2200 movs r2, #0 + 80069a6: f883 203c strb.w r2, [r3, #60] ; 0x3c + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); + 80069aa: 6878 ldr r0, [r7, #4] + 80069ac: f000 f815 bl 80069da +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 80069b0: 687b ldr r3, [r7, #4] + 80069b2: 2202 movs r2, #2 + 80069b4: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 80069b8: 687b ldr r3, [r7, #4] + 80069ba: 681a ldr r2, [r3, #0] + 80069bc: 687b ldr r3, [r7, #4] + 80069be: 3304 adds r3, #4 + 80069c0: 4619 mov r1, r3 + 80069c2: 4610 mov r0, r2 + 80069c4: f000 fc3a bl 800723c + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 80069c8: 687b ldr r3, [r7, #4] + 80069ca: 2201 movs r2, #1 + 80069cc: f883 203d strb.w r2, [r3, #61] ; 0x3d + + return HAL_OK; + 80069d0: 2300 movs r3, #0 +} + 80069d2: 4618 mov r0, r3 + 80069d4: 3708 adds r7, #8 + 80069d6: 46bd mov sp, r7 + 80069d8: bd80 pop {r7, pc} + +080069da : + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + 80069da: b480 push {r7} + 80069dc: b083 sub sp, #12 + 80069de: af00 add r7, sp, #0 + 80069e0: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + 80069e2: bf00 nop + 80069e4: 370c adds r7, #12 + 80069e6: 46bd mov sp, r7 + 80069e8: f85d 7b04 ldr.w r7, [sp], #4 + 80069ec: 4770 bx lr + ... + +080069f0 : + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + 80069f0: b580 push {r7, lr} + 80069f2: b084 sub sp, #16 + 80069f4: af00 add r7, sp, #0 + 80069f6: 6078 str r0, [r7, #4] + 80069f8: 6039 str r1, [r7, #0] + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 80069fa: 687b ldr r3, [r7, #4] + 80069fc: 681b ldr r3, [r3, #0] + 80069fe: 2201 movs r2, #1 + 8006a00: 6839 ldr r1, [r7, #0] + 8006a02: 4618 mov r0, r3 + 8006a04: f000 ffb2 bl 800796c + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 8006a08: 687b ldr r3, [r7, #4] + 8006a0a: 681b ldr r3, [r3, #0] + 8006a0c: 4a17 ldr r2, [pc, #92] ; (8006a6c ) + 8006a0e: 4293 cmp r3, r2 + 8006a10: d004 beq.n 8006a1c + 8006a12: 687b ldr r3, [r7, #4] + 8006a14: 681b ldr r3, [r3, #0] + 8006a16: 4a16 ldr r2, [pc, #88] ; (8006a70 ) + 8006a18: 4293 cmp r3, r2 + 8006a1a: d101 bne.n 8006a20 + 8006a1c: 2301 movs r3, #1 + 8006a1e: e000 b.n 8006a22 + 8006a20: 2300 movs r3, #0 + 8006a22: 2b00 cmp r3, #0 + 8006a24: d007 beq.n 8006a36 + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + 8006a26: 687b ldr r3, [r7, #4] + 8006a28: 681b ldr r3, [r3, #0] + 8006a2a: 6c5a ldr r2, [r3, #68] ; 0x44 + 8006a2c: 687b ldr r3, [r7, #4] + 8006a2e: 681b ldr r3, [r3, #0] + 8006a30: f442 4200 orr.w r2, r2, #32768 ; 0x8000 + 8006a34: 645a str r2, [r3, #68] ; 0x44 + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 8006a36: 687b ldr r3, [r7, #4] + 8006a38: 681b ldr r3, [r3, #0] + 8006a3a: 689a ldr r2, [r3, #8] + 8006a3c: 4b0d ldr r3, [pc, #52] ; (8006a74 ) + 8006a3e: 4013 ands r3, r2 + 8006a40: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8006a42: 68fb ldr r3, [r7, #12] + 8006a44: 2b06 cmp r3, #6 + 8006a46: d00b beq.n 8006a60 + 8006a48: 68fb ldr r3, [r7, #12] + 8006a4a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8006a4e: d007 beq.n 8006a60 + { + __HAL_TIM_ENABLE(htim); + 8006a50: 687b ldr r3, [r7, #4] + 8006a52: 681b ldr r3, [r3, #0] + 8006a54: 681a ldr r2, [r3, #0] + 8006a56: 687b ldr r3, [r7, #4] + 8006a58: 681b ldr r3, [r3, #0] + 8006a5a: f042 0201 orr.w r2, r2, #1 + 8006a5e: 601a str r2, [r3, #0] + } + + /* Return function status */ + return HAL_OK; + 8006a60: 2300 movs r3, #0 +} + 8006a62: 4618 mov r0, r3 + 8006a64: 3710 adds r7, #16 + 8006a66: 46bd mov sp, r7 + 8006a68: bd80 pop {r7, pc} + 8006a6a: bf00 nop + 8006a6c: 40010000 .word 0x40010000 + 8006a70: 40010400 .word 0x40010400 + 8006a74: 00010007 .word 0x00010007 + +08006a78 : + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +{ + 8006a78: b580 push {r7, lr} + 8006a7a: b086 sub sp, #24 + 8006a7c: af00 add r7, sp, #0 + 8006a7e: 6078 str r0, [r7, #4] + 8006a80: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + 8006a82: 687b ldr r3, [r7, #4] + 8006a84: 2b00 cmp r3, #0 + 8006a86: d101 bne.n 8006a8c + { + return HAL_ERROR; + 8006a88: 2301 movs r3, #1 + 8006a8a: e07b b.n 8006b84 + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + 8006a8c: 687b ldr r3, [r7, #4] + 8006a8e: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 8006a92: b2db uxtb r3, r3 + 8006a94: 2b00 cmp r3, #0 + 8006a96: d106 bne.n 8006aa6 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 8006a98: 687b ldr r3, [r7, #4] + 8006a9a: 2200 movs r2, #0 + 8006a9c: f883 203c strb.w r2, [r3, #60] ; 0x3c + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); + 8006aa0: 6878 ldr r0, [r7, #4] + 8006aa2: f7fe f93f bl 8004d24 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8006aa6: 687b ldr r3, [r7, #4] + 8006aa8: 2202 movs r2, #2 + 8006aaa: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + 8006aae: 687b ldr r3, [r7, #4] + 8006ab0: 681b ldr r3, [r3, #0] + 8006ab2: 6899 ldr r1, [r3, #8] + 8006ab4: 687b ldr r3, [r7, #4] + 8006ab6: 681a ldr r2, [r3, #0] + 8006ab8: 4b34 ldr r3, [pc, #208] ; (8006b8c ) + 8006aba: 400b ands r3, r1 + 8006abc: 6093 str r3, [r2, #8] + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8006abe: 687b ldr r3, [r7, #4] + 8006ac0: 681a ldr r2, [r3, #0] + 8006ac2: 687b ldr r3, [r7, #4] + 8006ac4: 3304 adds r3, #4 + 8006ac6: 4619 mov r1, r3 + 8006ac8: 4610 mov r0, r2 + 8006aca: f000 fbb7 bl 800723c + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 8006ace: 687b ldr r3, [r7, #4] + 8006ad0: 681b ldr r3, [r3, #0] + 8006ad2: 689b ldr r3, [r3, #8] + 8006ad4: 617b str r3, [r7, #20] + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + 8006ad6: 687b ldr r3, [r7, #4] + 8006ad8: 681b ldr r3, [r3, #0] + 8006ada: 699b ldr r3, [r3, #24] + 8006adc: 613b str r3, [r7, #16] + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + 8006ade: 687b ldr r3, [r7, #4] + 8006ae0: 681b ldr r3, [r3, #0] + 8006ae2: 6a1b ldr r3, [r3, #32] + 8006ae4: 60fb str r3, [r7, #12] + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + 8006ae6: 683b ldr r3, [r7, #0] + 8006ae8: 681b ldr r3, [r3, #0] + 8006aea: 697a ldr r2, [r7, #20] + 8006aec: 4313 orrs r3, r2 + 8006aee: 617b str r3, [r7, #20] + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + 8006af0: 693a ldr r2, [r7, #16] + 8006af2: 4b27 ldr r3, [pc, #156] ; (8006b90 ) + 8006af4: 4013 ands r3, r2 + 8006af6: 613b str r3, [r7, #16] + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + 8006af8: 683b ldr r3, [r7, #0] + 8006afa: 689a ldr r2, [r3, #8] + 8006afc: 683b ldr r3, [r7, #0] + 8006afe: 699b ldr r3, [r3, #24] + 8006b00: 021b lsls r3, r3, #8 + 8006b02: 4313 orrs r3, r2 + 8006b04: 693a ldr r2, [r7, #16] + 8006b06: 4313 orrs r3, r2 + 8006b08: 613b str r3, [r7, #16] + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + 8006b0a: 693a ldr r2, [r7, #16] + 8006b0c: 4b21 ldr r3, [pc, #132] ; (8006b94 ) + 8006b0e: 4013 ands r3, r2 + 8006b10: 613b str r3, [r7, #16] + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + 8006b12: 693a ldr r2, [r7, #16] + 8006b14: 4b20 ldr r3, [pc, #128] ; (8006b98 ) + 8006b16: 4013 ands r3, r2 + 8006b18: 613b str r3, [r7, #16] + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + 8006b1a: 683b ldr r3, [r7, #0] + 8006b1c: 68da ldr r2, [r3, #12] + 8006b1e: 683b ldr r3, [r7, #0] + 8006b20: 69db ldr r3, [r3, #28] + 8006b22: 021b lsls r3, r3, #8 + 8006b24: 4313 orrs r3, r2 + 8006b26: 693a ldr r2, [r7, #16] + 8006b28: 4313 orrs r3, r2 + 8006b2a: 613b str r3, [r7, #16] + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + 8006b2c: 683b ldr r3, [r7, #0] + 8006b2e: 691b ldr r3, [r3, #16] + 8006b30: 011a lsls r2, r3, #4 + 8006b32: 683b ldr r3, [r7, #0] + 8006b34: 6a1b ldr r3, [r3, #32] + 8006b36: 031b lsls r3, r3, #12 + 8006b38: 4313 orrs r3, r2 + 8006b3a: 693a ldr r2, [r7, #16] + 8006b3c: 4313 orrs r3, r2 + 8006b3e: 613b str r3, [r7, #16] + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + 8006b40: 68fb ldr r3, [r7, #12] + 8006b42: f023 0322 bic.w r3, r3, #34 ; 0x22 + 8006b46: 60fb str r3, [r7, #12] + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + 8006b48: 68fb ldr r3, [r7, #12] + 8006b4a: f023 0388 bic.w r3, r3, #136 ; 0x88 + 8006b4e: 60fb str r3, [r7, #12] + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + 8006b50: 683b ldr r3, [r7, #0] + 8006b52: 685a ldr r2, [r3, #4] + 8006b54: 683b ldr r3, [r7, #0] + 8006b56: 695b ldr r3, [r3, #20] + 8006b58: 011b lsls r3, r3, #4 + 8006b5a: 4313 orrs r3, r2 + 8006b5c: 68fa ldr r2, [r7, #12] + 8006b5e: 4313 orrs r3, r2 + 8006b60: 60fb str r3, [r7, #12] + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8006b62: 687b ldr r3, [r7, #4] + 8006b64: 681b ldr r3, [r3, #0] + 8006b66: 697a ldr r2, [r7, #20] + 8006b68: 609a str r2, [r3, #8] + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + 8006b6a: 687b ldr r3, [r7, #4] + 8006b6c: 681b ldr r3, [r3, #0] + 8006b6e: 693a ldr r2, [r7, #16] + 8006b70: 619a str r2, [r3, #24] + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + 8006b72: 687b ldr r3, [r7, #4] + 8006b74: 681b ldr r3, [r3, #0] + 8006b76: 68fa ldr r2, [r7, #12] + 8006b78: 621a str r2, [r3, #32] + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 8006b7a: 687b ldr r3, [r7, #4] + 8006b7c: 2201 movs r2, #1 + 8006b7e: f883 203d strb.w r2, [r3, #61] ; 0x3d + + return HAL_OK; + 8006b82: 2300 movs r3, #0 +} + 8006b84: 4618 mov r0, r3 + 8006b86: 3718 adds r7, #24 + 8006b88: 46bd mov sp, r7 + 8006b8a: bd80 pop {r7, pc} + 8006b8c: fffebff8 .word 0xfffebff8 + 8006b90: fffffcfc .word 0xfffffcfc + 8006b94: fffff3f3 .word 0xfffff3f3 + 8006b98: ffff0f0f .word 0xffff0f0f + +08006b9c : + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + 8006b9c: b580 push {r7, lr} + 8006b9e: b082 sub sp, #8 + 8006ba0: af00 add r7, sp, #0 + 8006ba2: 6078 str r0, [r7, #4] + 8006ba4: 6039 str r1, [r7, #0] + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + switch (Channel) + 8006ba6: 683b ldr r3, [r7, #0] + 8006ba8: 2b00 cmp r3, #0 + 8006baa: d002 beq.n 8006bb2 + 8006bac: 2b04 cmp r3, #4 + 8006bae: d008 beq.n 8006bc2 + 8006bb0: e00f b.n 8006bd2 + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 8006bb2: 687b ldr r3, [r7, #4] + 8006bb4: 681b ldr r3, [r3, #0] + 8006bb6: 2201 movs r2, #1 + 8006bb8: 2100 movs r1, #0 + 8006bba: 4618 mov r0, r3 + 8006bbc: f000 fed6 bl 800796c + break; + 8006bc0: e016 b.n 8006bf0 + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 8006bc2: 687b ldr r3, [r7, #4] + 8006bc4: 681b ldr r3, [r3, #0] + 8006bc6: 2201 movs r2, #1 + 8006bc8: 2104 movs r1, #4 + 8006bca: 4618 mov r0, r3 + 8006bcc: f000 fece bl 800796c + break; + 8006bd0: e00e b.n 8006bf0 + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 8006bd2: 687b ldr r3, [r7, #4] + 8006bd4: 681b ldr r3, [r3, #0] + 8006bd6: 2201 movs r2, #1 + 8006bd8: 2100 movs r1, #0 + 8006bda: 4618 mov r0, r3 + 8006bdc: f000 fec6 bl 800796c + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 8006be0: 687b ldr r3, [r7, #4] + 8006be2: 681b ldr r3, [r3, #0] + 8006be4: 2201 movs r2, #1 + 8006be6: 2104 movs r1, #4 + 8006be8: 4618 mov r0, r3 + 8006bea: f000 febf bl 800796c + break; + 8006bee: bf00 nop + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + 8006bf0: 687b ldr r3, [r7, #4] + 8006bf2: 681b ldr r3, [r3, #0] + 8006bf4: 681a ldr r2, [r3, #0] + 8006bf6: 687b ldr r3, [r7, #4] + 8006bf8: 681b ldr r3, [r3, #0] + 8006bfa: f042 0201 orr.w r2, r2, #1 + 8006bfe: 601a str r2, [r3, #0] + + /* Return function status */ + return HAL_OK; + 8006c00: 2300 movs r3, #0 +} + 8006c02: 4618 mov r0, r3 + 8006c04: 3708 adds r7, #8 + 8006c06: 46bd mov sp, r7 + 8006c08: bd80 pop {r7, pc} + +08006c0a : + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + 8006c0a: b580 push {r7, lr} + 8006c0c: b082 sub sp, #8 + 8006c0e: af00 add r7, sp, #0 + 8006c10: 6078 str r0, [r7, #4] + /* Capture compare 1 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + 8006c12: 687b ldr r3, [r7, #4] + 8006c14: 681b ldr r3, [r3, #0] + 8006c16: 691b ldr r3, [r3, #16] + 8006c18: f003 0302 and.w r3, r3, #2 + 8006c1c: 2b02 cmp r3, #2 + 8006c1e: d122 bne.n 8006c66 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + 8006c20: 687b ldr r3, [r7, #4] + 8006c22: 681b ldr r3, [r3, #0] + 8006c24: 68db ldr r3, [r3, #12] + 8006c26: f003 0302 and.w r3, r3, #2 + 8006c2a: 2b02 cmp r3, #2 + 8006c2c: d11b bne.n 8006c66 + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + 8006c2e: 687b ldr r3, [r7, #4] + 8006c30: 681b ldr r3, [r3, #0] + 8006c32: f06f 0202 mvn.w r2, #2 + 8006c36: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 8006c38: 687b ldr r3, [r7, #4] + 8006c3a: 2201 movs r2, #1 + 8006c3c: 771a strb r2, [r3, #28] + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + 8006c3e: 687b ldr r3, [r7, #4] + 8006c40: 681b ldr r3, [r3, #0] + 8006c42: 699b ldr r3, [r3, #24] + 8006c44: f003 0303 and.w r3, r3, #3 + 8006c48: 2b00 cmp r3, #0 + 8006c4a: d003 beq.n 8006c54 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8006c4c: 6878 ldr r0, [r7, #4] + 8006c4e: f000 fad7 bl 8007200 + 8006c52: e005 b.n 8006c60 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8006c54: 6878 ldr r0, [r7, #4] + 8006c56: f000 fac9 bl 80071ec + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8006c5a: 6878 ldr r0, [r7, #4] + 8006c5c: f000 fada bl 8007214 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8006c60: 687b ldr r3, [r7, #4] + 8006c62: 2200 movs r2, #0 + 8006c64: 771a strb r2, [r3, #28] + } + } + } + /* Capture compare 2 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + 8006c66: 687b ldr r3, [r7, #4] + 8006c68: 681b ldr r3, [r3, #0] + 8006c6a: 691b ldr r3, [r3, #16] + 8006c6c: f003 0304 and.w r3, r3, #4 + 8006c70: 2b04 cmp r3, #4 + 8006c72: d122 bne.n 8006cba + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + 8006c74: 687b ldr r3, [r7, #4] + 8006c76: 681b ldr r3, [r3, #0] + 8006c78: 68db ldr r3, [r3, #12] + 8006c7a: f003 0304 and.w r3, r3, #4 + 8006c7e: 2b04 cmp r3, #4 + 8006c80: d11b bne.n 8006cba + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + 8006c82: 687b ldr r3, [r7, #4] + 8006c84: 681b ldr r3, [r3, #0] + 8006c86: f06f 0204 mvn.w r2, #4 + 8006c8a: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 8006c8c: 687b ldr r3, [r7, #4] + 8006c8e: 2202 movs r2, #2 + 8006c90: 771a strb r2, [r3, #28] + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + 8006c92: 687b ldr r3, [r7, #4] + 8006c94: 681b ldr r3, [r3, #0] + 8006c96: 699b ldr r3, [r3, #24] + 8006c98: f403 7340 and.w r3, r3, #768 ; 0x300 + 8006c9c: 2b00 cmp r3, #0 + 8006c9e: d003 beq.n 8006ca8 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8006ca0: 6878 ldr r0, [r7, #4] + 8006ca2: f000 faad bl 8007200 + 8006ca6: e005 b.n 8006cb4 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8006ca8: 6878 ldr r0, [r7, #4] + 8006caa: f000 fa9f bl 80071ec + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8006cae: 6878 ldr r0, [r7, #4] + 8006cb0: f000 fab0 bl 8007214 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8006cb4: 687b ldr r3, [r7, #4] + 8006cb6: 2200 movs r2, #0 + 8006cb8: 771a strb r2, [r3, #28] + } + } + /* Capture compare 3 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + 8006cba: 687b ldr r3, [r7, #4] + 8006cbc: 681b ldr r3, [r3, #0] + 8006cbe: 691b ldr r3, [r3, #16] + 8006cc0: f003 0308 and.w r3, r3, #8 + 8006cc4: 2b08 cmp r3, #8 + 8006cc6: d122 bne.n 8006d0e + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + 8006cc8: 687b ldr r3, [r7, #4] + 8006cca: 681b ldr r3, [r3, #0] + 8006ccc: 68db ldr r3, [r3, #12] + 8006cce: f003 0308 and.w r3, r3, #8 + 8006cd2: 2b08 cmp r3, #8 + 8006cd4: d11b bne.n 8006d0e + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + 8006cd6: 687b ldr r3, [r7, #4] + 8006cd8: 681b ldr r3, [r3, #0] + 8006cda: f06f 0208 mvn.w r2, #8 + 8006cde: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 8006ce0: 687b ldr r3, [r7, #4] + 8006ce2: 2204 movs r2, #4 + 8006ce4: 771a strb r2, [r3, #28] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + 8006ce6: 687b ldr r3, [r7, #4] + 8006ce8: 681b ldr r3, [r3, #0] + 8006cea: 69db ldr r3, [r3, #28] + 8006cec: f003 0303 and.w r3, r3, #3 + 8006cf0: 2b00 cmp r3, #0 + 8006cf2: d003 beq.n 8006cfc + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8006cf4: 6878 ldr r0, [r7, #4] + 8006cf6: f000 fa83 bl 8007200 + 8006cfa: e005 b.n 8006d08 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8006cfc: 6878 ldr r0, [r7, #4] + 8006cfe: f000 fa75 bl 80071ec + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8006d02: 6878 ldr r0, [r7, #4] + 8006d04: f000 fa86 bl 8007214 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8006d08: 687b ldr r3, [r7, #4] + 8006d0a: 2200 movs r2, #0 + 8006d0c: 771a strb r2, [r3, #28] + } + } + /* Capture compare 4 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + 8006d0e: 687b ldr r3, [r7, #4] + 8006d10: 681b ldr r3, [r3, #0] + 8006d12: 691b ldr r3, [r3, #16] + 8006d14: f003 0310 and.w r3, r3, #16 + 8006d18: 2b10 cmp r3, #16 + 8006d1a: d122 bne.n 8006d62 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + 8006d1c: 687b ldr r3, [r7, #4] + 8006d1e: 681b ldr r3, [r3, #0] + 8006d20: 68db ldr r3, [r3, #12] + 8006d22: f003 0310 and.w r3, r3, #16 + 8006d26: 2b10 cmp r3, #16 + 8006d28: d11b bne.n 8006d62 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + 8006d2a: 687b ldr r3, [r7, #4] + 8006d2c: 681b ldr r3, [r3, #0] + 8006d2e: f06f 0210 mvn.w r2, #16 + 8006d32: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 8006d34: 687b ldr r3, [r7, #4] + 8006d36: 2208 movs r2, #8 + 8006d38: 771a strb r2, [r3, #28] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + 8006d3a: 687b ldr r3, [r7, #4] + 8006d3c: 681b ldr r3, [r3, #0] + 8006d3e: 69db ldr r3, [r3, #28] + 8006d40: f403 7340 and.w r3, r3, #768 ; 0x300 + 8006d44: 2b00 cmp r3, #0 + 8006d46: d003 beq.n 8006d50 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8006d48: 6878 ldr r0, [r7, #4] + 8006d4a: f000 fa59 bl 8007200 + 8006d4e: e005 b.n 8006d5c + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8006d50: 6878 ldr r0, [r7, #4] + 8006d52: f000 fa4b bl 80071ec + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8006d56: 6878 ldr r0, [r7, #4] + 8006d58: f000 fa5c bl 8007214 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8006d5c: 687b ldr r3, [r7, #4] + 8006d5e: 2200 movs r2, #0 + 8006d60: 771a strb r2, [r3, #28] + } + } + /* TIM Update event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + 8006d62: 687b ldr r3, [r7, #4] + 8006d64: 681b ldr r3, [r3, #0] + 8006d66: 691b ldr r3, [r3, #16] + 8006d68: f003 0301 and.w r3, r3, #1 + 8006d6c: 2b01 cmp r3, #1 + 8006d6e: d10e bne.n 8006d8e + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + 8006d70: 687b ldr r3, [r7, #4] + 8006d72: 681b ldr r3, [r3, #0] + 8006d74: 68db ldr r3, [r3, #12] + 8006d76: f003 0301 and.w r3, r3, #1 + 8006d7a: 2b01 cmp r3, #1 + 8006d7c: d107 bne.n 8006d8e + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + 8006d7e: 687b ldr r3, [r7, #4] + 8006d80: 681b ldr r3, [r3, #0] + 8006d82: f06f 0201 mvn.w r2, #1 + 8006d86: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); + 8006d88: 6878 ldr r0, [r7, #4] + 8006d8a: f7fa fbcf bl 800152c +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + 8006d8e: 687b ldr r3, [r7, #4] + 8006d90: 681b ldr r3, [r3, #0] + 8006d92: 691b ldr r3, [r3, #16] + 8006d94: f003 0380 and.w r3, r3, #128 ; 0x80 + 8006d98: 2b80 cmp r3, #128 ; 0x80 + 8006d9a: d10e bne.n 8006dba + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + 8006d9c: 687b ldr r3, [r7, #4] + 8006d9e: 681b ldr r3, [r3, #0] + 8006da0: 68db ldr r3, [r3, #12] + 8006da2: f003 0380 and.w r3, r3, #128 ; 0x80 + 8006da6: 2b80 cmp r3, #128 ; 0x80 + 8006da8: d107 bne.n 8006dba + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + 8006daa: 687b ldr r3, [r7, #4] + 8006dac: 681b ldr r3, [r3, #0] + 8006dae: f06f 0280 mvn.w r2, #128 ; 0x80 + 8006db2: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); + 8006db4: 6878 ldr r0, [r7, #4] + 8006db6: f000 fe65 bl 8007a84 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break2 input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + 8006dba: 687b ldr r3, [r7, #4] + 8006dbc: 681b ldr r3, [r3, #0] + 8006dbe: 691b ldr r3, [r3, #16] + 8006dc0: f403 7380 and.w r3, r3, #256 ; 0x100 + 8006dc4: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8006dc8: d10e bne.n 8006de8 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + 8006dca: 687b ldr r3, [r7, #4] + 8006dcc: 681b ldr r3, [r3, #0] + 8006dce: 68db ldr r3, [r3, #12] + 8006dd0: f003 0380 and.w r3, r3, #128 ; 0x80 + 8006dd4: 2b80 cmp r3, #128 ; 0x80 + 8006dd6: d107 bne.n 8006de8 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); + 8006dd8: 687b ldr r3, [r7, #4] + 8006dda: 681b ldr r3, [r3, #0] + 8006ddc: f46f 7280 mvn.w r2, #256 ; 0x100 + 8006de0: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); + 8006de2: 6878 ldr r0, [r7, #4] + 8006de4: f000 fe58 bl 8007a98 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + 8006de8: 687b ldr r3, [r7, #4] + 8006dea: 681b ldr r3, [r3, #0] + 8006dec: 691b ldr r3, [r3, #16] + 8006dee: f003 0340 and.w r3, r3, #64 ; 0x40 + 8006df2: 2b40 cmp r3, #64 ; 0x40 + 8006df4: d10e bne.n 8006e14 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + 8006df6: 687b ldr r3, [r7, #4] + 8006df8: 681b ldr r3, [r3, #0] + 8006dfa: 68db ldr r3, [r3, #12] + 8006dfc: f003 0340 and.w r3, r3, #64 ; 0x40 + 8006e00: 2b40 cmp r3, #64 ; 0x40 + 8006e02: d107 bne.n 8006e14 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + 8006e04: 687b ldr r3, [r7, #4] + 8006e06: 681b ldr r3, [r3, #0] + 8006e08: f06f 0240 mvn.w r2, #64 ; 0x40 + 8006e0c: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); + 8006e0e: 6878 ldr r0, [r7, #4] + 8006e10: f000 fa0a bl 8007228 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + 8006e14: 687b ldr r3, [r7, #4] + 8006e16: 681b ldr r3, [r3, #0] + 8006e18: 691b ldr r3, [r3, #16] + 8006e1a: f003 0320 and.w r3, r3, #32 + 8006e1e: 2b20 cmp r3, #32 + 8006e20: d10e bne.n 8006e40 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + 8006e22: 687b ldr r3, [r7, #4] + 8006e24: 681b ldr r3, [r3, #0] + 8006e26: 68db ldr r3, [r3, #12] + 8006e28: f003 0320 and.w r3, r3, #32 + 8006e2c: 2b20 cmp r3, #32 + 8006e2e: d107 bne.n 8006e40 + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + 8006e30: 687b ldr r3, [r7, #4] + 8006e32: 681b ldr r3, [r3, #0] + 8006e34: f06f 0220 mvn.w r2, #32 + 8006e38: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); + 8006e3a: 6878 ldr r0, [r7, #4] + 8006e3c: f000 fe18 bl 8007a70 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + 8006e40: bf00 nop + 8006e42: 3708 adds r7, #8 + 8006e44: 46bd mov sp, r7 + 8006e46: bd80 pop {r7, pc} + +08006e48 : + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + 8006e48: b580 push {r7, lr} + 8006e4a: b084 sub sp, #16 + 8006e4c: af00 add r7, sp, #0 + 8006e4e: 60f8 str r0, [r7, #12] + 8006e50: 60b9 str r1, [r7, #8] + 8006e52: 607a str r2, [r7, #4] + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + 8006e54: 68fb ldr r3, [r7, #12] + 8006e56: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 8006e5a: 2b01 cmp r3, #1 + 8006e5c: d101 bne.n 8006e62 + 8006e5e: 2302 movs r3, #2 + 8006e60: e105 b.n 800706e + 8006e62: 68fb ldr r3, [r7, #12] + 8006e64: 2201 movs r2, #1 + 8006e66: f883 203c strb.w r2, [r3, #60] ; 0x3c + + htim->State = HAL_TIM_STATE_BUSY; + 8006e6a: 68fb ldr r3, [r7, #12] + 8006e6c: 2202 movs r2, #2 + 8006e6e: f883 203d strb.w r2, [r3, #61] ; 0x3d + + switch (Channel) + 8006e72: 687b ldr r3, [r7, #4] + 8006e74: 2b14 cmp r3, #20 + 8006e76: f200 80f0 bhi.w 800705a + 8006e7a: a201 add r2, pc, #4 ; (adr r2, 8006e80 ) + 8006e7c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8006e80: 08006ed5 .word 0x08006ed5 + 8006e84: 0800705b .word 0x0800705b + 8006e88: 0800705b .word 0x0800705b + 8006e8c: 0800705b .word 0x0800705b + 8006e90: 08006f15 .word 0x08006f15 + 8006e94: 0800705b .word 0x0800705b + 8006e98: 0800705b .word 0x0800705b + 8006e9c: 0800705b .word 0x0800705b + 8006ea0: 08006f57 .word 0x08006f57 + 8006ea4: 0800705b .word 0x0800705b + 8006ea8: 0800705b .word 0x0800705b + 8006eac: 0800705b .word 0x0800705b + 8006eb0: 08006f97 .word 0x08006f97 + 8006eb4: 0800705b .word 0x0800705b + 8006eb8: 0800705b .word 0x0800705b + 8006ebc: 0800705b .word 0x0800705b + 8006ec0: 08006fd9 .word 0x08006fd9 + 8006ec4: 0800705b .word 0x0800705b + 8006ec8: 0800705b .word 0x0800705b + 8006ecc: 0800705b .word 0x0800705b + 8006ed0: 08007019 .word 0x08007019 + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + 8006ed4: 68fb ldr r3, [r7, #12] + 8006ed6: 681b ldr r3, [r3, #0] + 8006ed8: 68b9 ldr r1, [r7, #8] + 8006eda: 4618 mov r0, r3 + 8006edc: f000 fa4e bl 800737c + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + 8006ee0: 68fb ldr r3, [r7, #12] + 8006ee2: 681b ldr r3, [r3, #0] + 8006ee4: 699a ldr r2, [r3, #24] + 8006ee6: 68fb ldr r3, [r7, #12] + 8006ee8: 681b ldr r3, [r3, #0] + 8006eea: f042 0208 orr.w r2, r2, #8 + 8006eee: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + 8006ef0: 68fb ldr r3, [r7, #12] + 8006ef2: 681b ldr r3, [r3, #0] + 8006ef4: 699a ldr r2, [r3, #24] + 8006ef6: 68fb ldr r3, [r7, #12] + 8006ef8: 681b ldr r3, [r3, #0] + 8006efa: f022 0204 bic.w r2, r2, #4 + 8006efe: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode; + 8006f00: 68fb ldr r3, [r7, #12] + 8006f02: 681b ldr r3, [r3, #0] + 8006f04: 6999 ldr r1, [r3, #24] + 8006f06: 68bb ldr r3, [r7, #8] + 8006f08: 691a ldr r2, [r3, #16] + 8006f0a: 68fb ldr r3, [r7, #12] + 8006f0c: 681b ldr r3, [r3, #0] + 8006f0e: 430a orrs r2, r1 + 8006f10: 619a str r2, [r3, #24] + break; + 8006f12: e0a3 b.n 800705c + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + 8006f14: 68fb ldr r3, [r7, #12] + 8006f16: 681b ldr r3, [r3, #0] + 8006f18: 68b9 ldr r1, [r7, #8] + 8006f1a: 4618 mov r0, r3 + 8006f1c: f000 faa0 bl 8007460 + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + 8006f20: 68fb ldr r3, [r7, #12] + 8006f22: 681b ldr r3, [r3, #0] + 8006f24: 699a ldr r2, [r3, #24] + 8006f26: 68fb ldr r3, [r7, #12] + 8006f28: 681b ldr r3, [r3, #0] + 8006f2a: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 8006f2e: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + 8006f30: 68fb ldr r3, [r7, #12] + 8006f32: 681b ldr r3, [r3, #0] + 8006f34: 699a ldr r2, [r3, #24] + 8006f36: 68fb ldr r3, [r7, #12] + 8006f38: 681b ldr r3, [r3, #0] + 8006f3a: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 8006f3e: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + 8006f40: 68fb ldr r3, [r7, #12] + 8006f42: 681b ldr r3, [r3, #0] + 8006f44: 6999 ldr r1, [r3, #24] + 8006f46: 68bb ldr r3, [r7, #8] + 8006f48: 691b ldr r3, [r3, #16] + 8006f4a: 021a lsls r2, r3, #8 + 8006f4c: 68fb ldr r3, [r7, #12] + 8006f4e: 681b ldr r3, [r3, #0] + 8006f50: 430a orrs r2, r1 + 8006f52: 619a str r2, [r3, #24] + break; + 8006f54: e082 b.n 800705c + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + 8006f56: 68fb ldr r3, [r7, #12] + 8006f58: 681b ldr r3, [r3, #0] + 8006f5a: 68b9 ldr r1, [r7, #8] + 8006f5c: 4618 mov r0, r3 + 8006f5e: f000 faf7 bl 8007550 + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + 8006f62: 68fb ldr r3, [r7, #12] + 8006f64: 681b ldr r3, [r3, #0] + 8006f66: 69da ldr r2, [r3, #28] + 8006f68: 68fb ldr r3, [r7, #12] + 8006f6a: 681b ldr r3, [r3, #0] + 8006f6c: f042 0208 orr.w r2, r2, #8 + 8006f70: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + 8006f72: 68fb ldr r3, [r7, #12] + 8006f74: 681b ldr r3, [r3, #0] + 8006f76: 69da ldr r2, [r3, #28] + 8006f78: 68fb ldr r3, [r7, #12] + 8006f7a: 681b ldr r3, [r3, #0] + 8006f7c: f022 0204 bic.w r2, r2, #4 + 8006f80: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode; + 8006f82: 68fb ldr r3, [r7, #12] + 8006f84: 681b ldr r3, [r3, #0] + 8006f86: 69d9 ldr r1, [r3, #28] + 8006f88: 68bb ldr r3, [r7, #8] + 8006f8a: 691a ldr r2, [r3, #16] + 8006f8c: 68fb ldr r3, [r7, #12] + 8006f8e: 681b ldr r3, [r3, #0] + 8006f90: 430a orrs r2, r1 + 8006f92: 61da str r2, [r3, #28] + break; + 8006f94: e062 b.n 800705c + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + 8006f96: 68fb ldr r3, [r7, #12] + 8006f98: 681b ldr r3, [r3, #0] + 8006f9a: 68b9 ldr r1, [r7, #8] + 8006f9c: 4618 mov r0, r3 + 8006f9e: f000 fb4d bl 800763c + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + 8006fa2: 68fb ldr r3, [r7, #12] + 8006fa4: 681b ldr r3, [r3, #0] + 8006fa6: 69da ldr r2, [r3, #28] + 8006fa8: 68fb ldr r3, [r7, #12] + 8006faa: 681b ldr r3, [r3, #0] + 8006fac: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 8006fb0: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + 8006fb2: 68fb ldr r3, [r7, #12] + 8006fb4: 681b ldr r3, [r3, #0] + 8006fb6: 69da ldr r2, [r3, #28] + 8006fb8: 68fb ldr r3, [r7, #12] + 8006fba: 681b ldr r3, [r3, #0] + 8006fbc: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 8006fc0: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + 8006fc2: 68fb ldr r3, [r7, #12] + 8006fc4: 681b ldr r3, [r3, #0] + 8006fc6: 69d9 ldr r1, [r3, #28] + 8006fc8: 68bb ldr r3, [r7, #8] + 8006fca: 691b ldr r3, [r3, #16] + 8006fcc: 021a lsls r2, r3, #8 + 8006fce: 68fb ldr r3, [r7, #12] + 8006fd0: 681b ldr r3, [r3, #0] + 8006fd2: 430a orrs r2, r1 + 8006fd4: 61da str r2, [r3, #28] + break; + 8006fd6: e041 b.n 800705c + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the Channel 5 in PWM mode */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + 8006fd8: 68fb ldr r3, [r7, #12] + 8006fda: 681b ldr r3, [r3, #0] + 8006fdc: 68b9 ldr r1, [r7, #8] + 8006fde: 4618 mov r0, r3 + 8006fe0: f000 fb84 bl 80076ec + + /* Set the Preload enable bit for channel5*/ + htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; + 8006fe4: 68fb ldr r3, [r7, #12] + 8006fe6: 681b ldr r3, [r3, #0] + 8006fe8: 6d5a ldr r2, [r3, #84] ; 0x54 + 8006fea: 68fb ldr r3, [r7, #12] + 8006fec: 681b ldr r3, [r3, #0] + 8006fee: f042 0208 orr.w r2, r2, #8 + 8006ff2: 655a str r2, [r3, #84] ; 0x54 + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; + 8006ff4: 68fb ldr r3, [r7, #12] + 8006ff6: 681b ldr r3, [r3, #0] + 8006ff8: 6d5a ldr r2, [r3, #84] ; 0x54 + 8006ffa: 68fb ldr r3, [r7, #12] + 8006ffc: 681b ldr r3, [r3, #0] + 8006ffe: f022 0204 bic.w r2, r2, #4 + 8007002: 655a str r2, [r3, #84] ; 0x54 + htim->Instance->CCMR3 |= sConfig->OCFastMode; + 8007004: 68fb ldr r3, [r7, #12] + 8007006: 681b ldr r3, [r3, #0] + 8007008: 6d59 ldr r1, [r3, #84] ; 0x54 + 800700a: 68bb ldr r3, [r7, #8] + 800700c: 691a ldr r2, [r3, #16] + 800700e: 68fb ldr r3, [r7, #12] + 8007010: 681b ldr r3, [r3, #0] + 8007012: 430a orrs r2, r1 + 8007014: 655a str r2, [r3, #84] ; 0x54 + break; + 8007016: e021 b.n 800705c + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the Channel 6 in PWM mode */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + 8007018: 68fb ldr r3, [r7, #12] + 800701a: 681b ldr r3, [r3, #0] + 800701c: 68b9 ldr r1, [r7, #8] + 800701e: 4618 mov r0, r3 + 8007020: f000 fbb6 bl 8007790 + + /* Set the Preload enable bit for channel6 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; + 8007024: 68fb ldr r3, [r7, #12] + 8007026: 681b ldr r3, [r3, #0] + 8007028: 6d5a ldr r2, [r3, #84] ; 0x54 + 800702a: 68fb ldr r3, [r7, #12] + 800702c: 681b ldr r3, [r3, #0] + 800702e: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 8007032: 655a str r2, [r3, #84] ; 0x54 + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; + 8007034: 68fb ldr r3, [r7, #12] + 8007036: 681b ldr r3, [r3, #0] + 8007038: 6d5a ldr r2, [r3, #84] ; 0x54 + 800703a: 68fb ldr r3, [r7, #12] + 800703c: 681b ldr r3, [r3, #0] + 800703e: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 8007042: 655a str r2, [r3, #84] ; 0x54 + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + 8007044: 68fb ldr r3, [r7, #12] + 8007046: 681b ldr r3, [r3, #0] + 8007048: 6d59 ldr r1, [r3, #84] ; 0x54 + 800704a: 68bb ldr r3, [r7, #8] + 800704c: 691b ldr r3, [r3, #16] + 800704e: 021a lsls r2, r3, #8 + 8007050: 68fb ldr r3, [r7, #12] + 8007052: 681b ldr r3, [r3, #0] + 8007054: 430a orrs r2, r1 + 8007056: 655a str r2, [r3, #84] ; 0x54 + break; + 8007058: e000 b.n 800705c + } + + default: + break; + 800705a: bf00 nop + } + + htim->State = HAL_TIM_STATE_READY; + 800705c: 68fb ldr r3, [r7, #12] + 800705e: 2201 movs r2, #1 + 8007060: f883 203d strb.w r2, [r3, #61] ; 0x3d + + __HAL_UNLOCK(htim); + 8007064: 68fb ldr r3, [r7, #12] + 8007066: 2200 movs r2, #0 + 8007068: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_OK; + 800706c: 2300 movs r3, #0 +} + 800706e: 4618 mov r0, r3 + 8007070: 3710 adds r7, #16 + 8007072: 46bd mov sp, r7 + 8007074: bd80 pop {r7, pc} + 8007076: bf00 nop + +08007078 : + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + 8007078: b580 push {r7, lr} + 800707a: b084 sub sp, #16 + 800707c: af00 add r7, sp, #0 + 800707e: 6078 str r0, [r7, #4] + 8007080: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + 8007082: 687b ldr r3, [r7, #4] + 8007084: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 8007088: 2b01 cmp r3, #1 + 800708a: d101 bne.n 8007090 + 800708c: 2302 movs r3, #2 + 800708e: e0a6 b.n 80071de + 8007090: 687b ldr r3, [r7, #4] + 8007092: 2201 movs r2, #1 + 8007094: f883 203c strb.w r2, [r3, #60] ; 0x3c + + htim->State = HAL_TIM_STATE_BUSY; + 8007098: 687b ldr r3, [r7, #4] + 800709a: 2202 movs r2, #2 + 800709c: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + 80070a0: 687b ldr r3, [r7, #4] + 80070a2: 681b ldr r3, [r3, #0] + 80070a4: 689b ldr r3, [r3, #8] + 80070a6: 60fb str r3, [r7, #12] + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + 80070a8: 68fa ldr r2, [r7, #12] + 80070aa: 4b4f ldr r3, [pc, #316] ; (80071e8 ) + 80070ac: 4013 ands r3, r2 + 80070ae: 60fb str r3, [r7, #12] + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 80070b0: 68fb ldr r3, [r7, #12] + 80070b2: f423 437f bic.w r3, r3, #65280 ; 0xff00 + 80070b6: 60fb str r3, [r7, #12] + htim->Instance->SMCR = tmpsmcr; + 80070b8: 687b ldr r3, [r7, #4] + 80070ba: 681b ldr r3, [r3, #0] + 80070bc: 68fa ldr r2, [r7, #12] + 80070be: 609a str r2, [r3, #8] + + switch (sClockSourceConfig->ClockSource) + 80070c0: 683b ldr r3, [r7, #0] + 80070c2: 681b ldr r3, [r3, #0] + 80070c4: 2b40 cmp r3, #64 ; 0x40 + 80070c6: d067 beq.n 8007198 + 80070c8: 2b40 cmp r3, #64 ; 0x40 + 80070ca: d80b bhi.n 80070e4 + 80070cc: 2b10 cmp r3, #16 + 80070ce: d073 beq.n 80071b8 + 80070d0: 2b10 cmp r3, #16 + 80070d2: d802 bhi.n 80070da + 80070d4: 2b00 cmp r3, #0 + 80070d6: d06f beq.n 80071b8 + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + break; + 80070d8: e078 b.n 80071cc + switch (sClockSourceConfig->ClockSource) + 80070da: 2b20 cmp r3, #32 + 80070dc: d06c beq.n 80071b8 + 80070de: 2b30 cmp r3, #48 ; 0x30 + 80070e0: d06a beq.n 80071b8 + break; + 80070e2: e073 b.n 80071cc + switch (sClockSourceConfig->ClockSource) + 80070e4: 2b70 cmp r3, #112 ; 0x70 + 80070e6: d00d beq.n 8007104 + 80070e8: 2b70 cmp r3, #112 ; 0x70 + 80070ea: d804 bhi.n 80070f6 + 80070ec: 2b50 cmp r3, #80 ; 0x50 + 80070ee: d033 beq.n 8007158 + 80070f0: 2b60 cmp r3, #96 ; 0x60 + 80070f2: d041 beq.n 8007178 + break; + 80070f4: e06a b.n 80071cc + switch (sClockSourceConfig->ClockSource) + 80070f6: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 80070fa: d066 beq.n 80071ca + 80070fc: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 8007100: d017 beq.n 8007132 + break; + 8007102: e063 b.n 80071cc + TIM_ETR_SetConfig(htim->Instance, + 8007104: 687b ldr r3, [r7, #4] + 8007106: 6818 ldr r0, [r3, #0] + 8007108: 683b ldr r3, [r7, #0] + 800710a: 6899 ldr r1, [r3, #8] + 800710c: 683b ldr r3, [r7, #0] + 800710e: 685a ldr r2, [r3, #4] + 8007110: 683b ldr r3, [r7, #0] + 8007112: 68db ldr r3, [r3, #12] + 8007114: f000 fc0a bl 800792c + tmpsmcr = htim->Instance->SMCR; + 8007118: 687b ldr r3, [r7, #4] + 800711a: 681b ldr r3, [r3, #0] + 800711c: 689b ldr r3, [r3, #8] + 800711e: 60fb str r3, [r7, #12] + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + 8007120: 68fb ldr r3, [r7, #12] + 8007122: f043 0377 orr.w r3, r3, #119 ; 0x77 + 8007126: 60fb str r3, [r7, #12] + htim->Instance->SMCR = tmpsmcr; + 8007128: 687b ldr r3, [r7, #4] + 800712a: 681b ldr r3, [r3, #0] + 800712c: 68fa ldr r2, [r7, #12] + 800712e: 609a str r2, [r3, #8] + break; + 8007130: e04c b.n 80071cc + TIM_ETR_SetConfig(htim->Instance, + 8007132: 687b ldr r3, [r7, #4] + 8007134: 6818 ldr r0, [r3, #0] + 8007136: 683b ldr r3, [r7, #0] + 8007138: 6899 ldr r1, [r3, #8] + 800713a: 683b ldr r3, [r7, #0] + 800713c: 685a ldr r2, [r3, #4] + 800713e: 683b ldr r3, [r7, #0] + 8007140: 68db ldr r3, [r3, #12] + 8007142: f000 fbf3 bl 800792c + htim->Instance->SMCR |= TIM_SMCR_ECE; + 8007146: 687b ldr r3, [r7, #4] + 8007148: 681b ldr r3, [r3, #0] + 800714a: 689a ldr r2, [r3, #8] + 800714c: 687b ldr r3, [r7, #4] + 800714e: 681b ldr r3, [r3, #0] + 8007150: f442 4280 orr.w r2, r2, #16384 ; 0x4000 + 8007154: 609a str r2, [r3, #8] + break; + 8007156: e039 b.n 80071cc + TIM_TI1_ConfigInputStage(htim->Instance, + 8007158: 687b ldr r3, [r7, #4] + 800715a: 6818 ldr r0, [r3, #0] + 800715c: 683b ldr r3, [r7, #0] + 800715e: 6859 ldr r1, [r3, #4] + 8007160: 683b ldr r3, [r7, #0] + 8007162: 68db ldr r3, [r3, #12] + 8007164: 461a mov r2, r3 + 8007166: f000 fb67 bl 8007838 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + 800716a: 687b ldr r3, [r7, #4] + 800716c: 681b ldr r3, [r3, #0] + 800716e: 2150 movs r1, #80 ; 0x50 + 8007170: 4618 mov r0, r3 + 8007172: f000 fbc0 bl 80078f6 + break; + 8007176: e029 b.n 80071cc + TIM_TI2_ConfigInputStage(htim->Instance, + 8007178: 687b ldr r3, [r7, #4] + 800717a: 6818 ldr r0, [r3, #0] + 800717c: 683b ldr r3, [r7, #0] + 800717e: 6859 ldr r1, [r3, #4] + 8007180: 683b ldr r3, [r7, #0] + 8007182: 68db ldr r3, [r3, #12] + 8007184: 461a mov r2, r3 + 8007186: f000 fb86 bl 8007896 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + 800718a: 687b ldr r3, [r7, #4] + 800718c: 681b ldr r3, [r3, #0] + 800718e: 2160 movs r1, #96 ; 0x60 + 8007190: 4618 mov r0, r3 + 8007192: f000 fbb0 bl 80078f6 + break; + 8007196: e019 b.n 80071cc + TIM_TI1_ConfigInputStage(htim->Instance, + 8007198: 687b ldr r3, [r7, #4] + 800719a: 6818 ldr r0, [r3, #0] + 800719c: 683b ldr r3, [r7, #0] + 800719e: 6859 ldr r1, [r3, #4] + 80071a0: 683b ldr r3, [r7, #0] + 80071a2: 68db ldr r3, [r3, #12] + 80071a4: 461a mov r2, r3 + 80071a6: f000 fb47 bl 8007838 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + 80071aa: 687b ldr r3, [r7, #4] + 80071ac: 681b ldr r3, [r3, #0] + 80071ae: 2140 movs r1, #64 ; 0x40 + 80071b0: 4618 mov r0, r3 + 80071b2: f000 fba0 bl 80078f6 + break; + 80071b6: e009 b.n 80071cc + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + 80071b8: 687b ldr r3, [r7, #4] + 80071ba: 681a ldr r2, [r3, #0] + 80071bc: 683b ldr r3, [r7, #0] + 80071be: 681b ldr r3, [r3, #0] + 80071c0: 4619 mov r1, r3 + 80071c2: 4610 mov r0, r2 + 80071c4: f000 fb97 bl 80078f6 + break; + 80071c8: e000 b.n 80071cc + break; + 80071ca: bf00 nop + } + htim->State = HAL_TIM_STATE_READY; + 80071cc: 687b ldr r3, [r7, #4] + 80071ce: 2201 movs r2, #1 + 80071d0: f883 203d strb.w r2, [r3, #61] ; 0x3d + + __HAL_UNLOCK(htim); + 80071d4: 687b ldr r3, [r7, #4] + 80071d6: 2200 movs r2, #0 + 80071d8: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_OK; + 80071dc: 2300 movs r3, #0 +} + 80071de: 4618 mov r0, r3 + 80071e0: 3710 adds r7, #16 + 80071e2: 46bd mov sp, r7 + 80071e4: bd80 pop {r7, pc} + 80071e6: bf00 nop + 80071e8: fffeff88 .word 0xfffeff88 + +080071ec : + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + 80071ec: b480 push {r7} + 80071ee: b083 sub sp, #12 + 80071f0: af00 add r7, sp, #0 + 80071f2: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + 80071f4: bf00 nop + 80071f6: 370c adds r7, #12 + 80071f8: 46bd mov sp, r7 + 80071fa: f85d 7b04 ldr.w r7, [sp], #4 + 80071fe: 4770 bx lr + +08007200 : + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + 8007200: b480 push {r7} + 8007202: b083 sub sp, #12 + 8007204: af00 add r7, sp, #0 + 8007206: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + 8007208: bf00 nop + 800720a: 370c adds r7, #12 + 800720c: 46bd mov sp, r7 + 800720e: f85d 7b04 ldr.w r7, [sp], #4 + 8007212: 4770 bx lr + +08007214 : + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + 8007214: b480 push {r7} + 8007216: b083 sub sp, #12 + 8007218: af00 add r7, sp, #0 + 800721a: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + 800721c: bf00 nop + 800721e: 370c adds r7, #12 + 8007220: 46bd mov sp, r7 + 8007222: f85d 7b04 ldr.w r7, [sp], #4 + 8007226: 4770 bx lr + +08007228 : + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + 8007228: b480 push {r7} + 800722a: b083 sub sp, #12 + 800722c: af00 add r7, sp, #0 + 800722e: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + 8007230: bf00 nop + 8007232: 370c adds r7, #12 + 8007234: 46bd mov sp, r7 + 8007236: f85d 7b04 ldr.w r7, [sp], #4 + 800723a: 4770 bx lr + +0800723c : + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + 800723c: b480 push {r7} + 800723e: b085 sub sp, #20 + 8007240: af00 add r7, sp, #0 + 8007242: 6078 str r0, [r7, #4] + 8007244: 6039 str r1, [r7, #0] + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + 8007246: 687b ldr r3, [r7, #4] + 8007248: 681b ldr r3, [r3, #0] + 800724a: 60fb str r3, [r7, #12] + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + 800724c: 687b ldr r3, [r7, #4] + 800724e: 4a40 ldr r2, [pc, #256] ; (8007350 ) + 8007250: 4293 cmp r3, r2 + 8007252: d013 beq.n 800727c + 8007254: 687b ldr r3, [r7, #4] + 8007256: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 800725a: d00f beq.n 800727c + 800725c: 687b ldr r3, [r7, #4] + 800725e: 4a3d ldr r2, [pc, #244] ; (8007354 ) + 8007260: 4293 cmp r3, r2 + 8007262: d00b beq.n 800727c + 8007264: 687b ldr r3, [r7, #4] + 8007266: 4a3c ldr r2, [pc, #240] ; (8007358 ) + 8007268: 4293 cmp r3, r2 + 800726a: d007 beq.n 800727c + 800726c: 687b ldr r3, [r7, #4] + 800726e: 4a3b ldr r2, [pc, #236] ; (800735c ) + 8007270: 4293 cmp r3, r2 + 8007272: d003 beq.n 800727c + 8007274: 687b ldr r3, [r7, #4] + 8007276: 4a3a ldr r2, [pc, #232] ; (8007360 ) + 8007278: 4293 cmp r3, r2 + 800727a: d108 bne.n 800728e + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + 800727c: 68fb ldr r3, [r7, #12] + 800727e: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8007282: 60fb str r3, [r7, #12] + tmpcr1 |= Structure->CounterMode; + 8007284: 683b ldr r3, [r7, #0] + 8007286: 685b ldr r3, [r3, #4] + 8007288: 68fa ldr r2, [r7, #12] + 800728a: 4313 orrs r3, r2 + 800728c: 60fb str r3, [r7, #12] + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + 800728e: 687b ldr r3, [r7, #4] + 8007290: 4a2f ldr r2, [pc, #188] ; (8007350 ) + 8007292: 4293 cmp r3, r2 + 8007294: d02b beq.n 80072ee + 8007296: 687b ldr r3, [r7, #4] + 8007298: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 800729c: d027 beq.n 80072ee + 800729e: 687b ldr r3, [r7, #4] + 80072a0: 4a2c ldr r2, [pc, #176] ; (8007354 ) + 80072a2: 4293 cmp r3, r2 + 80072a4: d023 beq.n 80072ee + 80072a6: 687b ldr r3, [r7, #4] + 80072a8: 4a2b ldr r2, [pc, #172] ; (8007358 ) + 80072aa: 4293 cmp r3, r2 + 80072ac: d01f beq.n 80072ee + 80072ae: 687b ldr r3, [r7, #4] + 80072b0: 4a2a ldr r2, [pc, #168] ; (800735c ) + 80072b2: 4293 cmp r3, r2 + 80072b4: d01b beq.n 80072ee + 80072b6: 687b ldr r3, [r7, #4] + 80072b8: 4a29 ldr r2, [pc, #164] ; (8007360 ) + 80072ba: 4293 cmp r3, r2 + 80072bc: d017 beq.n 80072ee + 80072be: 687b ldr r3, [r7, #4] + 80072c0: 4a28 ldr r2, [pc, #160] ; (8007364 ) + 80072c2: 4293 cmp r3, r2 + 80072c4: d013 beq.n 80072ee + 80072c6: 687b ldr r3, [r7, #4] + 80072c8: 4a27 ldr r2, [pc, #156] ; (8007368 ) + 80072ca: 4293 cmp r3, r2 + 80072cc: d00f beq.n 80072ee + 80072ce: 687b ldr r3, [r7, #4] + 80072d0: 4a26 ldr r2, [pc, #152] ; (800736c ) + 80072d2: 4293 cmp r3, r2 + 80072d4: d00b beq.n 80072ee + 80072d6: 687b ldr r3, [r7, #4] + 80072d8: 4a25 ldr r2, [pc, #148] ; (8007370 ) + 80072da: 4293 cmp r3, r2 + 80072dc: d007 beq.n 80072ee + 80072de: 687b ldr r3, [r7, #4] + 80072e0: 4a24 ldr r2, [pc, #144] ; (8007374 ) + 80072e2: 4293 cmp r3, r2 + 80072e4: d003 beq.n 80072ee + 80072e6: 687b ldr r3, [r7, #4] + 80072e8: 4a23 ldr r2, [pc, #140] ; (8007378 ) + 80072ea: 4293 cmp r3, r2 + 80072ec: d108 bne.n 8007300 + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + 80072ee: 68fb ldr r3, [r7, #12] + 80072f0: f423 7340 bic.w r3, r3, #768 ; 0x300 + 80072f4: 60fb str r3, [r7, #12] + tmpcr1 |= (uint32_t)Structure->ClockDivision; + 80072f6: 683b ldr r3, [r7, #0] + 80072f8: 68db ldr r3, [r3, #12] + 80072fa: 68fa ldr r2, [r7, #12] + 80072fc: 4313 orrs r3, r2 + 80072fe: 60fb str r3, [r7, #12] + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + 8007300: 68fb ldr r3, [r7, #12] + 8007302: f023 0280 bic.w r2, r3, #128 ; 0x80 + 8007306: 683b ldr r3, [r7, #0] + 8007308: 695b ldr r3, [r3, #20] + 800730a: 4313 orrs r3, r2 + 800730c: 60fb str r3, [r7, #12] + + TIMx->CR1 = tmpcr1; + 800730e: 687b ldr r3, [r7, #4] + 8007310: 68fa ldr r2, [r7, #12] + 8007312: 601a str r2, [r3, #0] + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + 8007314: 683b ldr r3, [r7, #0] + 8007316: 689a ldr r2, [r3, #8] + 8007318: 687b ldr r3, [r7, #4] + 800731a: 62da str r2, [r3, #44] ; 0x2c + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + 800731c: 683b ldr r3, [r7, #0] + 800731e: 681a ldr r2, [r3, #0] + 8007320: 687b ldr r3, [r7, #4] + 8007322: 629a str r2, [r3, #40] ; 0x28 + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + 8007324: 687b ldr r3, [r7, #4] + 8007326: 4a0a ldr r2, [pc, #40] ; (8007350 ) + 8007328: 4293 cmp r3, r2 + 800732a: d003 beq.n 8007334 + 800732c: 687b ldr r3, [r7, #4] + 800732e: 4a0c ldr r2, [pc, #48] ; (8007360 ) + 8007330: 4293 cmp r3, r2 + 8007332: d103 bne.n 800733c + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + 8007334: 683b ldr r3, [r7, #0] + 8007336: 691a ldr r2, [r3, #16] + 8007338: 687b ldr r3, [r7, #4] + 800733a: 631a str r2, [r3, #48] ; 0x30 + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + 800733c: 687b ldr r3, [r7, #4] + 800733e: 2201 movs r2, #1 + 8007340: 615a str r2, [r3, #20] +} + 8007342: bf00 nop + 8007344: 3714 adds r7, #20 + 8007346: 46bd mov sp, r7 + 8007348: f85d 7b04 ldr.w r7, [sp], #4 + 800734c: 4770 bx lr + 800734e: bf00 nop + 8007350: 40010000 .word 0x40010000 + 8007354: 40000400 .word 0x40000400 + 8007358: 40000800 .word 0x40000800 + 800735c: 40000c00 .word 0x40000c00 + 8007360: 40010400 .word 0x40010400 + 8007364: 40014000 .word 0x40014000 + 8007368: 40014400 .word 0x40014400 + 800736c: 40014800 .word 0x40014800 + 8007370: 40001800 .word 0x40001800 + 8007374: 40001c00 .word 0x40001c00 + 8007378: 40002000 .word 0x40002000 + +0800737c : + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 800737c: b480 push {r7} + 800737e: b087 sub sp, #28 + 8007380: af00 add r7, sp, #0 + 8007382: 6078 str r0, [r7, #4] + 8007384: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + 8007386: 687b ldr r3, [r7, #4] + 8007388: 6a1b ldr r3, [r3, #32] + 800738a: f023 0201 bic.w r2, r3, #1 + 800738e: 687b ldr r3, [r7, #4] + 8007390: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8007392: 687b ldr r3, [r7, #4] + 8007394: 6a1b ldr r3, [r3, #32] + 8007396: 617b str r3, [r7, #20] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8007398: 687b ldr r3, [r7, #4] + 800739a: 685b ldr r3, [r3, #4] + 800739c: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 800739e: 687b ldr r3, [r7, #4] + 80073a0: 699b ldr r3, [r3, #24] + 80073a2: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + 80073a4: 68fa ldr r2, [r7, #12] + 80073a6: 4b2b ldr r3, [pc, #172] ; (8007454 ) + 80073a8: 4013 ands r3, r2 + 80073aa: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC1S; + 80073ac: 68fb ldr r3, [r7, #12] + 80073ae: f023 0303 bic.w r3, r3, #3 + 80073b2: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 80073b4: 683b ldr r3, [r7, #0] + 80073b6: 681b ldr r3, [r3, #0] + 80073b8: 68fa ldr r2, [r7, #12] + 80073ba: 4313 orrs r3, r2 + 80073bc: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + 80073be: 697b ldr r3, [r7, #20] + 80073c0: f023 0302 bic.w r3, r3, #2 + 80073c4: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + 80073c6: 683b ldr r3, [r7, #0] + 80073c8: 689b ldr r3, [r3, #8] + 80073ca: 697a ldr r2, [r7, #20] + 80073cc: 4313 orrs r3, r2 + 80073ce: 617b str r3, [r7, #20] + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + 80073d0: 687b ldr r3, [r7, #4] + 80073d2: 4a21 ldr r2, [pc, #132] ; (8007458 ) + 80073d4: 4293 cmp r3, r2 + 80073d6: d003 beq.n 80073e0 + 80073d8: 687b ldr r3, [r7, #4] + 80073da: 4a20 ldr r2, [pc, #128] ; (800745c ) + 80073dc: 4293 cmp r3, r2 + 80073de: d10c bne.n 80073fa + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + 80073e0: 697b ldr r3, [r7, #20] + 80073e2: f023 0308 bic.w r3, r3, #8 + 80073e6: 617b str r3, [r7, #20] + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + 80073e8: 683b ldr r3, [r7, #0] + 80073ea: 68db ldr r3, [r3, #12] + 80073ec: 697a ldr r2, [r7, #20] + 80073ee: 4313 orrs r3, r2 + 80073f0: 617b str r3, [r7, #20] + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + 80073f2: 697b ldr r3, [r7, #20] + 80073f4: f023 0304 bic.w r3, r3, #4 + 80073f8: 617b str r3, [r7, #20] + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 80073fa: 687b ldr r3, [r7, #4] + 80073fc: 4a16 ldr r2, [pc, #88] ; (8007458 ) + 80073fe: 4293 cmp r3, r2 + 8007400: d003 beq.n 800740a + 8007402: 687b ldr r3, [r7, #4] + 8007404: 4a15 ldr r2, [pc, #84] ; (800745c ) + 8007406: 4293 cmp r3, r2 + 8007408: d111 bne.n 800742e + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + 800740a: 693b ldr r3, [r7, #16] + 800740c: f423 7380 bic.w r3, r3, #256 ; 0x100 + 8007410: 613b str r3, [r7, #16] + tmpcr2 &= ~TIM_CR2_OIS1N; + 8007412: 693b ldr r3, [r7, #16] + 8007414: f423 7300 bic.w r3, r3, #512 ; 0x200 + 8007418: 613b str r3, [r7, #16] + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + 800741a: 683b ldr r3, [r7, #0] + 800741c: 695b ldr r3, [r3, #20] + 800741e: 693a ldr r2, [r7, #16] + 8007420: 4313 orrs r3, r2 + 8007422: 613b str r3, [r7, #16] + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + 8007424: 683b ldr r3, [r7, #0] + 8007426: 699b ldr r3, [r3, #24] + 8007428: 693a ldr r2, [r7, #16] + 800742a: 4313 orrs r3, r2 + 800742c: 613b str r3, [r7, #16] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 800742e: 687b ldr r3, [r7, #4] + 8007430: 693a ldr r2, [r7, #16] + 8007432: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8007434: 687b ldr r3, [r7, #4] + 8007436: 68fa ldr r2, [r7, #12] + 8007438: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + 800743a: 683b ldr r3, [r7, #0] + 800743c: 685a ldr r2, [r3, #4] + 800743e: 687b ldr r3, [r7, #4] + 8007440: 635a str r2, [r3, #52] ; 0x34 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8007442: 687b ldr r3, [r7, #4] + 8007444: 697a ldr r2, [r7, #20] + 8007446: 621a str r2, [r3, #32] +} + 8007448: bf00 nop + 800744a: 371c adds r7, #28 + 800744c: 46bd mov sp, r7 + 800744e: f85d 7b04 ldr.w r7, [sp], #4 + 8007452: 4770 bx lr + 8007454: fffeff8f .word 0xfffeff8f + 8007458: 40010000 .word 0x40010000 + 800745c: 40010400 .word 0x40010400 + +08007460 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 8007460: b480 push {r7} + 8007462: b087 sub sp, #28 + 8007464: af00 add r7, sp, #0 + 8007466: 6078 str r0, [r7, #4] + 8007468: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + 800746a: 687b ldr r3, [r7, #4] + 800746c: 6a1b ldr r3, [r3, #32] + 800746e: f023 0210 bic.w r2, r3, #16 + 8007472: 687b ldr r3, [r7, #4] + 8007474: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8007476: 687b ldr r3, [r7, #4] + 8007478: 6a1b ldr r3, [r3, #32] + 800747a: 617b str r3, [r7, #20] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 800747c: 687b ldr r3, [r7, #4] + 800747e: 685b ldr r3, [r3, #4] + 8007480: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 8007482: 687b ldr r3, [r7, #4] + 8007484: 699b ldr r3, [r3, #24] + 8007486: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + 8007488: 68fa ldr r2, [r7, #12] + 800748a: 4b2e ldr r3, [pc, #184] ; (8007544 ) + 800748c: 4013 ands r3, r2 + 800748e: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC2S; + 8007490: 68fb ldr r3, [r7, #12] + 8007492: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8007496: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 8007498: 683b ldr r3, [r7, #0] + 800749a: 681b ldr r3, [r3, #0] + 800749c: 021b lsls r3, r3, #8 + 800749e: 68fa ldr r2, [r7, #12] + 80074a0: 4313 orrs r3, r2 + 80074a2: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + 80074a4: 697b ldr r3, [r7, #20] + 80074a6: f023 0320 bic.w r3, r3, #32 + 80074aa: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + 80074ac: 683b ldr r3, [r7, #0] + 80074ae: 689b ldr r3, [r3, #8] + 80074b0: 011b lsls r3, r3, #4 + 80074b2: 697a ldr r2, [r7, #20] + 80074b4: 4313 orrs r3, r2 + 80074b6: 617b str r3, [r7, #20] + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + 80074b8: 687b ldr r3, [r7, #4] + 80074ba: 4a23 ldr r2, [pc, #140] ; (8007548 ) + 80074bc: 4293 cmp r3, r2 + 80074be: d003 beq.n 80074c8 + 80074c0: 687b ldr r3, [r7, #4] + 80074c2: 4a22 ldr r2, [pc, #136] ; (800754c ) + 80074c4: 4293 cmp r3, r2 + 80074c6: d10d bne.n 80074e4 + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + 80074c8: 697b ldr r3, [r7, #20] + 80074ca: f023 0380 bic.w r3, r3, #128 ; 0x80 + 80074ce: 617b str r3, [r7, #20] + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + 80074d0: 683b ldr r3, [r7, #0] + 80074d2: 68db ldr r3, [r3, #12] + 80074d4: 011b lsls r3, r3, #4 + 80074d6: 697a ldr r2, [r7, #20] + 80074d8: 4313 orrs r3, r2 + 80074da: 617b str r3, [r7, #20] + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + 80074dc: 697b ldr r3, [r7, #20] + 80074de: f023 0340 bic.w r3, r3, #64 ; 0x40 + 80074e2: 617b str r3, [r7, #20] + + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 80074e4: 687b ldr r3, [r7, #4] + 80074e6: 4a18 ldr r2, [pc, #96] ; (8007548 ) + 80074e8: 4293 cmp r3, r2 + 80074ea: d003 beq.n 80074f4 + 80074ec: 687b ldr r3, [r7, #4] + 80074ee: 4a17 ldr r2, [pc, #92] ; (800754c ) + 80074f0: 4293 cmp r3, r2 + 80074f2: d113 bne.n 800751c + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + 80074f4: 693b ldr r3, [r7, #16] + 80074f6: f423 6380 bic.w r3, r3, #1024 ; 0x400 + 80074fa: 613b str r3, [r7, #16] + tmpcr2 &= ~TIM_CR2_OIS2N; + 80074fc: 693b ldr r3, [r7, #16] + 80074fe: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 8007502: 613b str r3, [r7, #16] + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + 8007504: 683b ldr r3, [r7, #0] + 8007506: 695b ldr r3, [r3, #20] + 8007508: 009b lsls r3, r3, #2 + 800750a: 693a ldr r2, [r7, #16] + 800750c: 4313 orrs r3, r2 + 800750e: 613b str r3, [r7, #16] + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + 8007510: 683b ldr r3, [r7, #0] + 8007512: 699b ldr r3, [r3, #24] + 8007514: 009b lsls r3, r3, #2 + 8007516: 693a ldr r2, [r7, #16] + 8007518: 4313 orrs r3, r2 + 800751a: 613b str r3, [r7, #16] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 800751c: 687b ldr r3, [r7, #4] + 800751e: 693a ldr r2, [r7, #16] + 8007520: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8007522: 687b ldr r3, [r7, #4] + 8007524: 68fa ldr r2, [r7, #12] + 8007526: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + 8007528: 683b ldr r3, [r7, #0] + 800752a: 685a ldr r2, [r3, #4] + 800752c: 687b ldr r3, [r7, #4] + 800752e: 639a str r2, [r3, #56] ; 0x38 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8007530: 687b ldr r3, [r7, #4] + 8007532: 697a ldr r2, [r7, #20] + 8007534: 621a str r2, [r3, #32] +} + 8007536: bf00 nop + 8007538: 371c adds r7, #28 + 800753a: 46bd mov sp, r7 + 800753c: f85d 7b04 ldr.w r7, [sp], #4 + 8007540: 4770 bx lr + 8007542: bf00 nop + 8007544: feff8fff .word 0xfeff8fff + 8007548: 40010000 .word 0x40010000 + 800754c: 40010400 .word 0x40010400 + +08007550 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 8007550: b480 push {r7} + 8007552: b087 sub sp, #28 + 8007554: af00 add r7, sp, #0 + 8007556: 6078 str r0, [r7, #4] + 8007558: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + 800755a: 687b ldr r3, [r7, #4] + 800755c: 6a1b ldr r3, [r3, #32] + 800755e: f423 7280 bic.w r2, r3, #256 ; 0x100 + 8007562: 687b ldr r3, [r7, #4] + 8007564: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8007566: 687b ldr r3, [r7, #4] + 8007568: 6a1b ldr r3, [r3, #32] + 800756a: 617b str r3, [r7, #20] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 800756c: 687b ldr r3, [r7, #4] + 800756e: 685b ldr r3, [r3, #4] + 8007570: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 8007572: 687b ldr r3, [r7, #4] + 8007574: 69db ldr r3, [r3, #28] + 8007576: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + 8007578: 68fa ldr r2, [r7, #12] + 800757a: 4b2d ldr r3, [pc, #180] ; (8007630 ) + 800757c: 4013 ands r3, r2 + 800757e: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC3S; + 8007580: 68fb ldr r3, [r7, #12] + 8007582: f023 0303 bic.w r3, r3, #3 + 8007586: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 8007588: 683b ldr r3, [r7, #0] + 800758a: 681b ldr r3, [r3, #0] + 800758c: 68fa ldr r2, [r7, #12] + 800758e: 4313 orrs r3, r2 + 8007590: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + 8007592: 697b ldr r3, [r7, #20] + 8007594: f423 7300 bic.w r3, r3, #512 ; 0x200 + 8007598: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + 800759a: 683b ldr r3, [r7, #0] + 800759c: 689b ldr r3, [r3, #8] + 800759e: 021b lsls r3, r3, #8 + 80075a0: 697a ldr r2, [r7, #20] + 80075a2: 4313 orrs r3, r2 + 80075a4: 617b str r3, [r7, #20] + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + 80075a6: 687b ldr r3, [r7, #4] + 80075a8: 4a22 ldr r2, [pc, #136] ; (8007634 ) + 80075aa: 4293 cmp r3, r2 + 80075ac: d003 beq.n 80075b6 + 80075ae: 687b ldr r3, [r7, #4] + 80075b0: 4a21 ldr r2, [pc, #132] ; (8007638 ) + 80075b2: 4293 cmp r3, r2 + 80075b4: d10d bne.n 80075d2 + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + 80075b6: 697b ldr r3, [r7, #20] + 80075b8: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 80075bc: 617b str r3, [r7, #20] + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + 80075be: 683b ldr r3, [r7, #0] + 80075c0: 68db ldr r3, [r3, #12] + 80075c2: 021b lsls r3, r3, #8 + 80075c4: 697a ldr r2, [r7, #20] + 80075c6: 4313 orrs r3, r2 + 80075c8: 617b str r3, [r7, #20] + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + 80075ca: 697b ldr r3, [r7, #20] + 80075cc: f423 6380 bic.w r3, r3, #1024 ; 0x400 + 80075d0: 617b str r3, [r7, #20] + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 80075d2: 687b ldr r3, [r7, #4] + 80075d4: 4a17 ldr r2, [pc, #92] ; (8007634 ) + 80075d6: 4293 cmp r3, r2 + 80075d8: d003 beq.n 80075e2 + 80075da: 687b ldr r3, [r7, #4] + 80075dc: 4a16 ldr r2, [pc, #88] ; (8007638 ) + 80075de: 4293 cmp r3, r2 + 80075e0: d113 bne.n 800760a + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + 80075e2: 693b ldr r3, [r7, #16] + 80075e4: f423 5380 bic.w r3, r3, #4096 ; 0x1000 + 80075e8: 613b str r3, [r7, #16] + tmpcr2 &= ~TIM_CR2_OIS3N; + 80075ea: 693b ldr r3, [r7, #16] + 80075ec: f423 5300 bic.w r3, r3, #8192 ; 0x2000 + 80075f0: 613b str r3, [r7, #16] + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + 80075f2: 683b ldr r3, [r7, #0] + 80075f4: 695b ldr r3, [r3, #20] + 80075f6: 011b lsls r3, r3, #4 + 80075f8: 693a ldr r2, [r7, #16] + 80075fa: 4313 orrs r3, r2 + 80075fc: 613b str r3, [r7, #16] + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + 80075fe: 683b ldr r3, [r7, #0] + 8007600: 699b ldr r3, [r3, #24] + 8007602: 011b lsls r3, r3, #4 + 8007604: 693a ldr r2, [r7, #16] + 8007606: 4313 orrs r3, r2 + 8007608: 613b str r3, [r7, #16] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 800760a: 687b ldr r3, [r7, #4] + 800760c: 693a ldr r2, [r7, #16] + 800760e: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 8007610: 687b ldr r3, [r7, #4] + 8007612: 68fa ldr r2, [r7, #12] + 8007614: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + 8007616: 683b ldr r3, [r7, #0] + 8007618: 685a ldr r2, [r3, #4] + 800761a: 687b ldr r3, [r7, #4] + 800761c: 63da str r2, [r3, #60] ; 0x3c + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 800761e: 687b ldr r3, [r7, #4] + 8007620: 697a ldr r2, [r7, #20] + 8007622: 621a str r2, [r3, #32] +} + 8007624: bf00 nop + 8007626: 371c adds r7, #28 + 8007628: 46bd mov sp, r7 + 800762a: f85d 7b04 ldr.w r7, [sp], #4 + 800762e: 4770 bx lr + 8007630: fffeff8f .word 0xfffeff8f + 8007634: 40010000 .word 0x40010000 + 8007638: 40010400 .word 0x40010400 + +0800763c : + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 800763c: b480 push {r7} + 800763e: b087 sub sp, #28 + 8007640: af00 add r7, sp, #0 + 8007642: 6078 str r0, [r7, #4] + 8007644: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + 8007646: 687b ldr r3, [r7, #4] + 8007648: 6a1b ldr r3, [r3, #32] + 800764a: f423 5280 bic.w r2, r3, #4096 ; 0x1000 + 800764e: 687b ldr r3, [r7, #4] + 8007650: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8007652: 687b ldr r3, [r7, #4] + 8007654: 6a1b ldr r3, [r3, #32] + 8007656: 613b str r3, [r7, #16] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8007658: 687b ldr r3, [r7, #4] + 800765a: 685b ldr r3, [r3, #4] + 800765c: 617b str r3, [r7, #20] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 800765e: 687b ldr r3, [r7, #4] + 8007660: 69db ldr r3, [r3, #28] + 8007662: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + 8007664: 68fa ldr r2, [r7, #12] + 8007666: 4b1e ldr r3, [pc, #120] ; (80076e0 ) + 8007668: 4013 ands r3, r2 + 800766a: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC4S; + 800766c: 68fb ldr r3, [r7, #12] + 800766e: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8007672: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 8007674: 683b ldr r3, [r7, #0] + 8007676: 681b ldr r3, [r3, #0] + 8007678: 021b lsls r3, r3, #8 + 800767a: 68fa ldr r2, [r7, #12] + 800767c: 4313 orrs r3, r2 + 800767e: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + 8007680: 693b ldr r3, [r7, #16] + 8007682: f423 5300 bic.w r3, r3, #8192 ; 0x2000 + 8007686: 613b str r3, [r7, #16] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + 8007688: 683b ldr r3, [r7, #0] + 800768a: 689b ldr r3, [r3, #8] + 800768c: 031b lsls r3, r3, #12 + 800768e: 693a ldr r2, [r7, #16] + 8007690: 4313 orrs r3, r2 + 8007692: 613b str r3, [r7, #16] + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 8007694: 687b ldr r3, [r7, #4] + 8007696: 4a13 ldr r2, [pc, #76] ; (80076e4 ) + 8007698: 4293 cmp r3, r2 + 800769a: d003 beq.n 80076a4 + 800769c: 687b ldr r3, [r7, #4] + 800769e: 4a12 ldr r2, [pc, #72] ; (80076e8 ) + 80076a0: 4293 cmp r3, r2 + 80076a2: d109 bne.n 80076b8 + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + 80076a4: 697b ldr r3, [r7, #20] + 80076a6: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 80076aa: 617b str r3, [r7, #20] + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + 80076ac: 683b ldr r3, [r7, #0] + 80076ae: 695b ldr r3, [r3, #20] + 80076b0: 019b lsls r3, r3, #6 + 80076b2: 697a ldr r2, [r7, #20] + 80076b4: 4313 orrs r3, r2 + 80076b6: 617b str r3, [r7, #20] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 80076b8: 687b ldr r3, [r7, #4] + 80076ba: 697a ldr r2, [r7, #20] + 80076bc: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 80076be: 687b ldr r3, [r7, #4] + 80076c0: 68fa ldr r2, [r7, #12] + 80076c2: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + 80076c4: 683b ldr r3, [r7, #0] + 80076c6: 685a ldr r2, [r3, #4] + 80076c8: 687b ldr r3, [r7, #4] + 80076ca: 641a str r2, [r3, #64] ; 0x40 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 80076cc: 687b ldr r3, [r7, #4] + 80076ce: 693a ldr r2, [r7, #16] + 80076d0: 621a str r2, [r3, #32] +} + 80076d2: bf00 nop + 80076d4: 371c adds r7, #28 + 80076d6: 46bd mov sp, r7 + 80076d8: f85d 7b04 ldr.w r7, [sp], #4 + 80076dc: 4770 bx lr + 80076de: bf00 nop + 80076e0: feff8fff .word 0xfeff8fff + 80076e4: 40010000 .word 0x40010000 + 80076e8: 40010400 .word 0x40010400 + +080076ec : + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, + TIM_OC_InitTypeDef *OC_Config) +{ + 80076ec: b480 push {r7} + 80076ee: b087 sub sp, #28 + 80076f0: af00 add r7, sp, #0 + 80076f2: 6078 str r0, [r7, #4] + 80076f4: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC5E; + 80076f6: 687b ldr r3, [r7, #4] + 80076f8: 6a1b ldr r3, [r3, #32] + 80076fa: f423 3280 bic.w r2, r3, #65536 ; 0x10000 + 80076fe: 687b ldr r3, [r7, #4] + 8007700: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8007702: 687b ldr r3, [r7, #4] + 8007704: 6a1b ldr r3, [r3, #32] + 8007706: 613b str r3, [r7, #16] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8007708: 687b ldr r3, [r7, #4] + 800770a: 685b ldr r3, [r3, #4] + 800770c: 617b str r3, [r7, #20] + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + 800770e: 687b ldr r3, [r7, #4] + 8007710: 6d5b ldr r3, [r3, #84] ; 0x54 + 8007712: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC5M); + 8007714: 68fa ldr r2, [r7, #12] + 8007716: 4b1b ldr r3, [pc, #108] ; (8007784 ) + 8007718: 4013 ands r3, r2 + 800771a: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 800771c: 683b ldr r3, [r7, #0] + 800771e: 681b ldr r3, [r3, #0] + 8007720: 68fa ldr r2, [r7, #12] + 8007722: 4313 orrs r3, r2 + 8007724: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC5P; + 8007726: 693b ldr r3, [r7, #16] + 8007728: f423 3300 bic.w r3, r3, #131072 ; 0x20000 + 800772c: 613b str r3, [r7, #16] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 16U); + 800772e: 683b ldr r3, [r7, #0] + 8007730: 689b ldr r3, [r3, #8] + 8007732: 041b lsls r3, r3, #16 + 8007734: 693a ldr r2, [r7, #16] + 8007736: 4313 orrs r3, r2 + 8007738: 613b str r3, [r7, #16] + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 800773a: 687b ldr r3, [r7, #4] + 800773c: 4a12 ldr r2, [pc, #72] ; (8007788 ) + 800773e: 4293 cmp r3, r2 + 8007740: d003 beq.n 800774a + 8007742: 687b ldr r3, [r7, #4] + 8007744: 4a11 ldr r2, [pc, #68] ; (800778c ) + 8007746: 4293 cmp r3, r2 + 8007748: d109 bne.n 800775e + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS5; + 800774a: 697b ldr r3, [r7, #20] + 800774c: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8007750: 617b str r3, [r7, #20] + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 8U); + 8007752: 683b ldr r3, [r7, #0] + 8007754: 695b ldr r3, [r3, #20] + 8007756: 021b lsls r3, r3, #8 + 8007758: 697a ldr r2, [r7, #20] + 800775a: 4313 orrs r3, r2 + 800775c: 617b str r3, [r7, #20] + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 800775e: 687b ldr r3, [r7, #4] + 8007760: 697a ldr r2, [r7, #20] + 8007762: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + 8007764: 687b ldr r3, [r7, #4] + 8007766: 68fa ldr r2, [r7, #12] + 8007768: 655a str r2, [r3, #84] ; 0x54 + + /* Set the Capture Compare Register value */ + TIMx->CCR5 = OC_Config->Pulse; + 800776a: 683b ldr r3, [r7, #0] + 800776c: 685a ldr r2, [r3, #4] + 800776e: 687b ldr r3, [r7, #4] + 8007770: 659a str r2, [r3, #88] ; 0x58 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8007772: 687b ldr r3, [r7, #4] + 8007774: 693a ldr r2, [r7, #16] + 8007776: 621a str r2, [r3, #32] +} + 8007778: bf00 nop + 800777a: 371c adds r7, #28 + 800777c: 46bd mov sp, r7 + 800777e: f85d 7b04 ldr.w r7, [sp], #4 + 8007782: 4770 bx lr + 8007784: fffeff8f .word 0xfffeff8f + 8007788: 40010000 .word 0x40010000 + 800778c: 40010400 .word 0x40010400 + +08007790 : + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, + TIM_OC_InitTypeDef *OC_Config) +{ + 8007790: b480 push {r7} + 8007792: b087 sub sp, #28 + 8007794: af00 add r7, sp, #0 + 8007796: 6078 str r0, [r7, #4] + 8007798: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC6E; + 800779a: 687b ldr r3, [r7, #4] + 800779c: 6a1b ldr r3, [r3, #32] + 800779e: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 + 80077a2: 687b ldr r3, [r7, #4] + 80077a4: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 80077a6: 687b ldr r3, [r7, #4] + 80077a8: 6a1b ldr r3, [r3, #32] + 80077aa: 613b str r3, [r7, #16] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 80077ac: 687b ldr r3, [r7, #4] + 80077ae: 685b ldr r3, [r3, #4] + 80077b0: 617b str r3, [r7, #20] + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + 80077b2: 687b ldr r3, [r7, #4] + 80077b4: 6d5b ldr r3, [r3, #84] ; 0x54 + 80077b6: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC6M); + 80077b8: 68fa ldr r2, [r7, #12] + 80077ba: 4b1c ldr r3, [pc, #112] ; (800782c ) + 80077bc: 4013 ands r3, r2 + 80077be: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 80077c0: 683b ldr r3, [r7, #0] + 80077c2: 681b ldr r3, [r3, #0] + 80077c4: 021b lsls r3, r3, #8 + 80077c6: 68fa ldr r2, [r7, #12] + 80077c8: 4313 orrs r3, r2 + 80077ca: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)~TIM_CCER_CC6P; + 80077cc: 693b ldr r3, [r7, #16] + 80077ce: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 + 80077d2: 613b str r3, [r7, #16] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 20U); + 80077d4: 683b ldr r3, [r7, #0] + 80077d6: 689b ldr r3, [r3, #8] + 80077d8: 051b lsls r3, r3, #20 + 80077da: 693a ldr r2, [r7, #16] + 80077dc: 4313 orrs r3, r2 + 80077de: 613b str r3, [r7, #16] + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 80077e0: 687b ldr r3, [r7, #4] + 80077e2: 4a13 ldr r2, [pc, #76] ; (8007830 ) + 80077e4: 4293 cmp r3, r2 + 80077e6: d003 beq.n 80077f0 + 80077e8: 687b ldr r3, [r7, #4] + 80077ea: 4a12 ldr r2, [pc, #72] ; (8007834 ) + 80077ec: 4293 cmp r3, r2 + 80077ee: d109 bne.n 8007804 + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS6; + 80077f0: 697b ldr r3, [r7, #20] + 80077f2: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 80077f6: 617b str r3, [r7, #20] + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 10U); + 80077f8: 683b ldr r3, [r7, #0] + 80077fa: 695b ldr r3, [r3, #20] + 80077fc: 029b lsls r3, r3, #10 + 80077fe: 697a ldr r2, [r7, #20] + 8007800: 4313 orrs r3, r2 + 8007802: 617b str r3, [r7, #20] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8007804: 687b ldr r3, [r7, #4] + 8007806: 697a ldr r2, [r7, #20] + 8007808: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + 800780a: 687b ldr r3, [r7, #4] + 800780c: 68fa ldr r2, [r7, #12] + 800780e: 655a str r2, [r3, #84] ; 0x54 + + /* Set the Capture Compare Register value */ + TIMx->CCR6 = OC_Config->Pulse; + 8007810: 683b ldr r3, [r7, #0] + 8007812: 685a ldr r2, [r3, #4] + 8007814: 687b ldr r3, [r7, #4] + 8007816: 65da str r2, [r3, #92] ; 0x5c + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8007818: 687b ldr r3, [r7, #4] + 800781a: 693a ldr r2, [r7, #16] + 800781c: 621a str r2, [r3, #32] +} + 800781e: bf00 nop + 8007820: 371c adds r7, #28 + 8007822: 46bd mov sp, r7 + 8007824: f85d 7b04 ldr.w r7, [sp], #4 + 8007828: 4770 bx lr + 800782a: bf00 nop + 800782c: feff8fff .word 0xfeff8fff + 8007830: 40010000 .word 0x40010000 + 8007834: 40010400 .word 0x40010400 + +08007838 : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 8007838: b480 push {r7} + 800783a: b087 sub sp, #28 + 800783c: af00 add r7, sp, #0 + 800783e: 60f8 str r0, [r7, #12] + 8007840: 60b9 str r1, [r7, #8] + 8007842: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + 8007844: 68fb ldr r3, [r7, #12] + 8007846: 6a1b ldr r3, [r3, #32] + 8007848: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC1E; + 800784a: 68fb ldr r3, [r7, #12] + 800784c: 6a1b ldr r3, [r3, #32] + 800784e: f023 0201 bic.w r2, r3, #1 + 8007852: 68fb ldr r3, [r7, #12] + 8007854: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 8007856: 68fb ldr r3, [r7, #12] + 8007858: 699b ldr r3, [r3, #24] + 800785a: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + 800785c: 693b ldr r3, [r7, #16] + 800785e: f023 03f0 bic.w r3, r3, #240 ; 0xf0 + 8007862: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 4U); + 8007864: 687b ldr r3, [r7, #4] + 8007866: 011b lsls r3, r3, #4 + 8007868: 693a ldr r2, [r7, #16] + 800786a: 4313 orrs r3, r2 + 800786c: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + 800786e: 697b ldr r3, [r7, #20] + 8007870: f023 030a bic.w r3, r3, #10 + 8007874: 617b str r3, [r7, #20] + tmpccer |= TIM_ICPolarity; + 8007876: 697a ldr r2, [r7, #20] + 8007878: 68bb ldr r3, [r7, #8] + 800787a: 4313 orrs r3, r2 + 800787c: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + 800787e: 68fb ldr r3, [r7, #12] + 8007880: 693a ldr r2, [r7, #16] + 8007882: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 8007884: 68fb ldr r3, [r7, #12] + 8007886: 697a ldr r2, [r7, #20] + 8007888: 621a str r2, [r3, #32] +} + 800788a: bf00 nop + 800788c: 371c adds r7, #28 + 800788e: 46bd mov sp, r7 + 8007890: f85d 7b04 ldr.w r7, [sp], #4 + 8007894: 4770 bx lr + +08007896 : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 8007896: b480 push {r7} + 8007898: b087 sub sp, #28 + 800789a: af00 add r7, sp, #0 + 800789c: 60f8 str r0, [r7, #12] + 800789e: 60b9 str r1, [r7, #8] + 80078a0: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + 80078a2: 68fb ldr r3, [r7, #12] + 80078a4: 6a1b ldr r3, [r3, #32] + 80078a6: f023 0210 bic.w r2, r3, #16 + 80078aa: 68fb ldr r3, [r7, #12] + 80078ac: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 80078ae: 68fb ldr r3, [r7, #12] + 80078b0: 699b ldr r3, [r3, #24] + 80078b2: 617b str r3, [r7, #20] + tmpccer = TIMx->CCER; + 80078b4: 68fb ldr r3, [r7, #12] + 80078b6: 6a1b ldr r3, [r3, #32] + 80078b8: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + 80078ba: 697b ldr r3, [r7, #20] + 80078bc: f423 4370 bic.w r3, r3, #61440 ; 0xf000 + 80078c0: 617b str r3, [r7, #20] + tmpccmr1 |= (TIM_ICFilter << 12U); + 80078c2: 687b ldr r3, [r7, #4] + 80078c4: 031b lsls r3, r3, #12 + 80078c6: 697a ldr r2, [r7, #20] + 80078c8: 4313 orrs r3, r2 + 80078ca: 617b str r3, [r7, #20] + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + 80078cc: 693b ldr r3, [r7, #16] + 80078ce: f023 03a0 bic.w r3, r3, #160 ; 0xa0 + 80078d2: 613b str r3, [r7, #16] + tmpccer |= (TIM_ICPolarity << 4U); + 80078d4: 68bb ldr r3, [r7, #8] + 80078d6: 011b lsls r3, r3, #4 + 80078d8: 693a ldr r2, [r7, #16] + 80078da: 4313 orrs r3, r2 + 80078dc: 613b str r3, [r7, #16] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + 80078de: 68fb ldr r3, [r7, #12] + 80078e0: 697a ldr r2, [r7, #20] + 80078e2: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 80078e4: 68fb ldr r3, [r7, #12] + 80078e6: 693a ldr r2, [r7, #16] + 80078e8: 621a str r2, [r3, #32] +} + 80078ea: bf00 nop + 80078ec: 371c adds r7, #28 + 80078ee: 46bd mov sp, r7 + 80078f0: f85d 7b04 ldr.w r7, [sp], #4 + 80078f4: 4770 bx lr + +080078f6 : + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + 80078f6: b480 push {r7} + 80078f8: b085 sub sp, #20 + 80078fa: af00 add r7, sp, #0 + 80078fc: 6078 str r0, [r7, #4] + 80078fe: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + 8007900: 687b ldr r3, [r7, #4] + 8007902: 689b ldr r3, [r3, #8] + 8007904: 60fb str r3, [r7, #12] + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + 8007906: 68fb ldr r3, [r7, #12] + 8007908: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800790c: 60fb str r3, [r7, #12] + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + 800790e: 683a ldr r2, [r7, #0] + 8007910: 68fb ldr r3, [r7, #12] + 8007912: 4313 orrs r3, r2 + 8007914: f043 0307 orr.w r3, r3, #7 + 8007918: 60fb str r3, [r7, #12] + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 800791a: 687b ldr r3, [r7, #4] + 800791c: 68fa ldr r2, [r7, #12] + 800791e: 609a str r2, [r3, #8] +} + 8007920: bf00 nop + 8007922: 3714 adds r7, #20 + 8007924: 46bd mov sp, r7 + 8007926: f85d 7b04 ldr.w r7, [sp], #4 + 800792a: 4770 bx lr + +0800792c : + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + 800792c: b480 push {r7} + 800792e: b087 sub sp, #28 + 8007930: af00 add r7, sp, #0 + 8007932: 60f8 str r0, [r7, #12] + 8007934: 60b9 str r1, [r7, #8] + 8007936: 607a str r2, [r7, #4] + 8007938: 603b str r3, [r7, #0] + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + 800793a: 68fb ldr r3, [r7, #12] + 800793c: 689b ldr r3, [r3, #8] + 800793e: 617b str r3, [r7, #20] + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 8007940: 697b ldr r3, [r7, #20] + 8007942: f423 437f bic.w r3, r3, #65280 ; 0xff00 + 8007946: 617b str r3, [r7, #20] + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + 8007948: 683b ldr r3, [r7, #0] + 800794a: 021a lsls r2, r3, #8 + 800794c: 687b ldr r3, [r7, #4] + 800794e: 431a orrs r2, r3 + 8007950: 68bb ldr r3, [r7, #8] + 8007952: 4313 orrs r3, r2 + 8007954: 697a ldr r2, [r7, #20] + 8007956: 4313 orrs r3, r2 + 8007958: 617b str r3, [r7, #20] + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 800795a: 68fb ldr r3, [r7, #12] + 800795c: 697a ldr r2, [r7, #20] + 800795e: 609a str r2, [r3, #8] +} + 8007960: bf00 nop + 8007962: 371c adds r7, #28 + 8007964: 46bd mov sp, r7 + 8007966: f85d 7b04 ldr.w r7, [sp], #4 + 800796a: 4770 bx lr + +0800796c : + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + 800796c: b480 push {r7} + 800796e: b087 sub sp, #28 + 8007970: af00 add r7, sp, #0 + 8007972: 60f8 str r0, [r7, #12] + 8007974: 60b9 str r1, [r7, #8] + 8007976: 607a str r2, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + 8007978: 68bb ldr r3, [r7, #8] + 800797a: f003 031f and.w r3, r3, #31 + 800797e: 2201 movs r2, #1 + 8007980: fa02 f303 lsl.w r3, r2, r3 + 8007984: 617b str r3, [r7, #20] + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + 8007986: 68fb ldr r3, [r7, #12] + 8007988: 6a1a ldr r2, [r3, #32] + 800798a: 697b ldr r3, [r7, #20] + 800798c: 43db mvns r3, r3 + 800798e: 401a ands r2, r3 + 8007990: 68fb ldr r3, [r7, #12] + 8007992: 621a str r2, [r3, #32] + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + 8007994: 68fb ldr r3, [r7, #12] + 8007996: 6a1a ldr r2, [r3, #32] + 8007998: 68bb ldr r3, [r7, #8] + 800799a: f003 031f and.w r3, r3, #31 + 800799e: 6879 ldr r1, [r7, #4] + 80079a0: fa01 f303 lsl.w r3, r1, r3 + 80079a4: 431a orrs r2, r3 + 80079a6: 68fb ldr r3, [r7, #12] + 80079a8: 621a str r2, [r3, #32] +} + 80079aa: bf00 nop + 80079ac: 371c adds r7, #28 + 80079ae: 46bd mov sp, r7 + 80079b0: f85d 7b04 ldr.w r7, [sp], #4 + 80079b4: 4770 bx lr + ... + +080079b8 : + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig) +{ + 80079b8: b480 push {r7} + 80079ba: b085 sub sp, #20 + 80079bc: af00 add r7, sp, #0 + 80079be: 6078 str r0, [r7, #4] + 80079c0: 6039 str r1, [r7, #0] + assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + 80079c2: 687b ldr r3, [r7, #4] + 80079c4: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 80079c8: 2b01 cmp r3, #1 + 80079ca: d101 bne.n 80079d0 + 80079cc: 2302 movs r3, #2 + 80079ce: e045 b.n 8007a5c + 80079d0: 687b ldr r3, [r7, #4] + 80079d2: 2201 movs r2, #1 + 80079d4: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + 80079d8: 687b ldr r3, [r7, #4] + 80079da: 2202 movs r2, #2 + 80079dc: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + 80079e0: 687b ldr r3, [r7, #4] + 80079e2: 681b ldr r3, [r3, #0] + 80079e4: 685b ldr r3, [r3, #4] + 80079e6: 60fb str r3, [r7, #12] + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 80079e8: 687b ldr r3, [r7, #4] + 80079ea: 681b ldr r3, [r3, #0] + 80079ec: 689b ldr r3, [r3, #8] + 80079ee: 60bb str r3, [r7, #8] + + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) + 80079f0: 687b ldr r3, [r7, #4] + 80079f2: 681b ldr r3, [r3, #0] + 80079f4: 4a1c ldr r2, [pc, #112] ; (8007a68 ) + 80079f6: 4293 cmp r3, r2 + 80079f8: d004 beq.n 8007a04 + 80079fa: 687b ldr r3, [r7, #4] + 80079fc: 681b ldr r3, [r3, #0] + 80079fe: 4a1b ldr r2, [pc, #108] ; (8007a6c ) + 8007a00: 4293 cmp r3, r2 + 8007a02: d108 bne.n 8007a16 + { + /* Check the parameters */ + assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); + + /* Clear the MMS2 bits */ + tmpcr2 &= ~TIM_CR2_MMS2; + 8007a04: 68fb ldr r3, [r7, #12] + 8007a06: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000 + 8007a0a: 60fb str r3, [r7, #12] + /* Select the TRGO2 source*/ + tmpcr2 |= sMasterConfig->MasterOutputTrigger2; + 8007a0c: 683b ldr r3, [r7, #0] + 8007a0e: 685b ldr r3, [r3, #4] + 8007a10: 68fa ldr r2, [r7, #12] + 8007a12: 4313 orrs r3, r2 + 8007a14: 60fb str r3, [r7, #12] + } + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + 8007a16: 68fb ldr r3, [r7, #12] + 8007a18: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8007a1c: 60fb str r3, [r7, #12] + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + 8007a1e: 683b ldr r3, [r7, #0] + 8007a20: 681b ldr r3, [r3, #0] + 8007a22: 68fa ldr r2, [r7, #12] + 8007a24: 4313 orrs r3, r2 + 8007a26: 60fb str r3, [r7, #12] + + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + 8007a28: 68bb ldr r3, [r7, #8] + 8007a2a: f023 0380 bic.w r3, r3, #128 ; 0x80 + 8007a2e: 60bb str r3, [r7, #8] + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + 8007a30: 683b ldr r3, [r7, #0] + 8007a32: 689b ldr r3, [r3, #8] + 8007a34: 68ba ldr r2, [r7, #8] + 8007a36: 4313 orrs r3, r2 + 8007a38: 60bb str r3, [r7, #8] + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + 8007a3a: 687b ldr r3, [r7, #4] + 8007a3c: 681b ldr r3, [r3, #0] + 8007a3e: 68fa ldr r2, [r7, #12] + 8007a40: 605a str r2, [r3, #4] + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8007a42: 687b ldr r3, [r7, #4] + 8007a44: 681b ldr r3, [r3, #0] + 8007a46: 68ba ldr r2, [r7, #8] + 8007a48: 609a str r2, [r3, #8] + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + 8007a4a: 687b ldr r3, [r7, #4] + 8007a4c: 2201 movs r2, #1 + 8007a4e: f883 203d strb.w r2, [r3, #61] ; 0x3d + + __HAL_UNLOCK(htim); + 8007a52: 687b ldr r3, [r7, #4] + 8007a54: 2200 movs r2, #0 + 8007a56: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_OK; + 8007a5a: 2300 movs r3, #0 +} + 8007a5c: 4618 mov r0, r3 + 8007a5e: 3714 adds r7, #20 + 8007a60: 46bd mov sp, r7 + 8007a62: f85d 7b04 ldr.w r7, [sp], #4 + 8007a66: 4770 bx lr + 8007a68: 40010000 .word 0x40010000 + 8007a6c: 40010400 .word 0x40010400 + +08007a70 : + * @brief Hall commutation changed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + 8007a70: b480 push {r7} + 8007a72: b083 sub sp, #12 + 8007a74: af00 add r7, sp, #0 + 8007a76: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} + 8007a78: bf00 nop + 8007a7a: 370c adds r7, #12 + 8007a7c: 46bd mov sp, r7 + 8007a7e: f85d 7b04 ldr.w r7, [sp], #4 + 8007a82: 4770 bx lr + +08007a84 : + * @brief Hall Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + 8007a84: b480 push {r7} + 8007a86: b083 sub sp, #12 + 8007a88: af00 add r7, sp, #0 + 8007a8a: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + 8007a8c: bf00 nop + 8007a8e: 370c adds r7, #12 + 8007a90: 46bd mov sp, r7 + 8007a92: f85d 7b04 ldr.w r7, [sp], #4 + 8007a96: 4770 bx lr + +08007a98 : + * @brief Hall Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + 8007a98: b480 push {r7} + 8007a9a: b083 sub sp, #12 + 8007a9c: af00 add r7, sp, #0 + 8007a9e: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} + 8007aa0: bf00 nop + 8007aa2: 370c adds r7, #12 + 8007aa4: 46bd mov sp, r7 + 8007aa6: f85d 7b04 ldr.w r7, [sp], #4 + 8007aaa: 4770 bx lr + +08007aac : + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + 8007aac: b580 push {r7, lr} + 8007aae: b082 sub sp, #8 + 8007ab0: af00 add r7, sp, #0 + 8007ab2: 6078 str r0, [r7, #4] + /* Check the UART handle allocation */ + if (huart == NULL) + 8007ab4: 687b ldr r3, [r7, #4] + 8007ab6: 2b00 cmp r3, #0 + 8007ab8: d101 bne.n 8007abe + { + return HAL_ERROR; + 8007aba: 2301 movs r3, #1 + 8007abc: e040 b.n 8007b40 + { + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + + if (huart->gState == HAL_UART_STATE_RESET) + 8007abe: 687b ldr r3, [r7, #4] + 8007ac0: 6f5b ldr r3, [r3, #116] ; 0x74 + 8007ac2: 2b00 cmp r3, #0 + 8007ac4: d106 bne.n 8007ad4 + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + 8007ac6: 687b ldr r3, [r7, #4] + 8007ac8: 2200 movs r2, #0 + 8007aca: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); + 8007ace: 6878 ldr r0, [r7, #4] + 8007ad0: f7fd fa38 bl 8004f44 +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + 8007ad4: 687b ldr r3, [r7, #4] + 8007ad6: 2224 movs r2, #36 ; 0x24 + 8007ad8: 675a str r2, [r3, #116] ; 0x74 + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + 8007ada: 687b ldr r3, [r7, #4] + 8007adc: 681b ldr r3, [r3, #0] + 8007ade: 681a ldr r2, [r3, #0] + 8007ae0: 687b ldr r3, [r7, #4] + 8007ae2: 681b ldr r3, [r3, #0] + 8007ae4: f022 0201 bic.w r2, r2, #1 + 8007ae8: 601a str r2, [r3, #0] + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + 8007aea: 6878 ldr r0, [r7, #4] + 8007aec: f000 fa90 bl 8008010 + 8007af0: 4603 mov r3, r0 + 8007af2: 2b01 cmp r3, #1 + 8007af4: d101 bne.n 8007afa + { + return HAL_ERROR; + 8007af6: 2301 movs r3, #1 + 8007af8: e022 b.n 8007b40 + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 8007afa: 687b ldr r3, [r7, #4] + 8007afc: 6a5b ldr r3, [r3, #36] ; 0x24 + 8007afe: 2b00 cmp r3, #0 + 8007b00: d002 beq.n 8007b08 + { + UART_AdvFeatureConfig(huart); + 8007b02: 6878 ldr r0, [r7, #4] + 8007b04: f000 fd28 bl 8008558 + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 8007b08: 687b ldr r3, [r7, #4] + 8007b0a: 681b ldr r3, [r3, #0] + 8007b0c: 685a ldr r2, [r3, #4] + 8007b0e: 687b ldr r3, [r7, #4] + 8007b10: 681b ldr r3, [r3, #0] + 8007b12: f422 4290 bic.w r2, r2, #18432 ; 0x4800 + 8007b16: 605a str r2, [r3, #4] + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 8007b18: 687b ldr r3, [r7, #4] + 8007b1a: 681b ldr r3, [r3, #0] + 8007b1c: 689a ldr r2, [r3, #8] + 8007b1e: 687b ldr r3, [r7, #4] + 8007b20: 681b ldr r3, [r3, #0] + 8007b22: f022 022a bic.w r2, r2, #42 ; 0x2a + 8007b26: 609a str r2, [r3, #8] + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + 8007b28: 687b ldr r3, [r7, #4] + 8007b2a: 681b ldr r3, [r3, #0] + 8007b2c: 681a ldr r2, [r3, #0] + 8007b2e: 687b ldr r3, [r7, #4] + 8007b30: 681b ldr r3, [r3, #0] + 8007b32: f042 0201 orr.w r2, r2, #1 + 8007b36: 601a str r2, [r3, #0] + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); + 8007b38: 6878 ldr r0, [r7, #4] + 8007b3a: f000 fdaf bl 800869c + 8007b3e: 4603 mov r3, r0 +} + 8007b40: 4618 mov r0, r3 + 8007b42: 3708 adds r7, #8 + 8007b44: 46bd mov sp, r7 + 8007b46: bd80 pop {r7, pc} + +08007b48 : + * @param Size Amount of data to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8007b48: b580 push {r7, lr} + 8007b4a: b08a sub sp, #40 ; 0x28 + 8007b4c: af02 add r7, sp, #8 + 8007b4e: 60f8 str r0, [r7, #12] + 8007b50: 60b9 str r1, [r7, #8] + 8007b52: 603b str r3, [r7, #0] + 8007b54: 4613 mov r3, r2 + 8007b56: 80fb strh r3, [r7, #6] + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + 8007b58: 68fb ldr r3, [r7, #12] + 8007b5a: 6f5b ldr r3, [r3, #116] ; 0x74 + 8007b5c: 2b20 cmp r3, #32 + 8007b5e: d17f bne.n 8007c60 + { + if ((pData == NULL) || (Size == 0U)) + 8007b60: 68bb ldr r3, [r7, #8] + 8007b62: 2b00 cmp r3, #0 + 8007b64: d002 beq.n 8007b6c + 8007b66: 88fb ldrh r3, [r7, #6] + 8007b68: 2b00 cmp r3, #0 + 8007b6a: d101 bne.n 8007b70 + { + return HAL_ERROR; + 8007b6c: 2301 movs r3, #1 + 8007b6e: e078 b.n 8007c62 + } + + /* Process Locked */ + __HAL_LOCK(huart); + 8007b70: 68fb ldr r3, [r7, #12] + 8007b72: f893 3070 ldrb.w r3, [r3, #112] ; 0x70 + 8007b76: 2b01 cmp r3, #1 + 8007b78: d101 bne.n 8007b7e + 8007b7a: 2302 movs r3, #2 + 8007b7c: e071 b.n 8007c62 + 8007b7e: 68fb ldr r3, [r7, #12] + 8007b80: 2201 movs r2, #1 + 8007b82: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8007b86: 68fb ldr r3, [r7, #12] + 8007b88: 2200 movs r2, #0 + 8007b8a: 67da str r2, [r3, #124] ; 0x7c + huart->gState = HAL_UART_STATE_BUSY_TX; + 8007b8c: 68fb ldr r3, [r7, #12] + 8007b8e: 2221 movs r2, #33 ; 0x21 + 8007b90: 675a str r2, [r3, #116] ; 0x74 + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + 8007b92: f7fd fb1f bl 80051d4 + 8007b96: 6178 str r0, [r7, #20] + + huart->TxXferSize = Size; + 8007b98: 68fb ldr r3, [r7, #12] + 8007b9a: 88fa ldrh r2, [r7, #6] + 8007b9c: f8a3 2050 strh.w r2, [r3, #80] ; 0x50 + huart->TxXferCount = Size; + 8007ba0: 68fb ldr r3, [r7, #12] + 8007ba2: 88fa ldrh r2, [r7, #6] + 8007ba4: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 8007ba8: 68fb ldr r3, [r7, #12] + 8007baa: 689b ldr r3, [r3, #8] + 8007bac: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8007bb0: d108 bne.n 8007bc4 + 8007bb2: 68fb ldr r3, [r7, #12] + 8007bb4: 691b ldr r3, [r3, #16] + 8007bb6: 2b00 cmp r3, #0 + 8007bb8: d104 bne.n 8007bc4 + { + pdata8bits = NULL; + 8007bba: 2300 movs r3, #0 + 8007bbc: 61fb str r3, [r7, #28] + pdata16bits = (uint16_t *) pData; + 8007bbe: 68bb ldr r3, [r7, #8] + 8007bc0: 61bb str r3, [r7, #24] + 8007bc2: e003 b.n 8007bcc + } + else + { + pdata8bits = pData; + 8007bc4: 68bb ldr r3, [r7, #8] + 8007bc6: 61fb str r3, [r7, #28] + pdata16bits = NULL; + 8007bc8: 2300 movs r3, #0 + 8007bca: 61bb str r3, [r7, #24] + } + + while (huart->TxXferCount > 0U) + 8007bcc: e02c b.n 8007c28 + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + 8007bce: 683b ldr r3, [r7, #0] + 8007bd0: 9300 str r3, [sp, #0] + 8007bd2: 697b ldr r3, [r7, #20] + 8007bd4: 2200 movs r2, #0 + 8007bd6: 2180 movs r1, #128 ; 0x80 + 8007bd8: 68f8 ldr r0, [r7, #12] + 8007bda: f000 fd8e bl 80086fa + 8007bde: 4603 mov r3, r0 + 8007be0: 2b00 cmp r3, #0 + 8007be2: d001 beq.n 8007be8 + { + return HAL_TIMEOUT; + 8007be4: 2303 movs r3, #3 + 8007be6: e03c b.n 8007c62 + } + if (pdata8bits == NULL) + 8007be8: 69fb ldr r3, [r7, #28] + 8007bea: 2b00 cmp r3, #0 + 8007bec: d10b bne.n 8007c06 + { + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + 8007bee: 69bb ldr r3, [r7, #24] + 8007bf0: 881b ldrh r3, [r3, #0] + 8007bf2: 461a mov r2, r3 + 8007bf4: 68fb ldr r3, [r7, #12] + 8007bf6: 681b ldr r3, [r3, #0] + 8007bf8: f3c2 0208 ubfx r2, r2, #0, #9 + 8007bfc: 629a str r2, [r3, #40] ; 0x28 + pdata16bits++; + 8007bfe: 69bb ldr r3, [r7, #24] + 8007c00: 3302 adds r3, #2 + 8007c02: 61bb str r3, [r7, #24] + 8007c04: e007 b.n 8007c16 + } + else + { + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + 8007c06: 69fb ldr r3, [r7, #28] + 8007c08: 781a ldrb r2, [r3, #0] + 8007c0a: 68fb ldr r3, [r7, #12] + 8007c0c: 681b ldr r3, [r3, #0] + 8007c0e: 629a str r2, [r3, #40] ; 0x28 + pdata8bits++; + 8007c10: 69fb ldr r3, [r7, #28] + 8007c12: 3301 adds r3, #1 + 8007c14: 61fb str r3, [r7, #28] + } + huart->TxXferCount--; + 8007c16: 68fb ldr r3, [r7, #12] + 8007c18: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 + 8007c1c: b29b uxth r3, r3 + 8007c1e: 3b01 subs r3, #1 + 8007c20: b29a uxth r2, r3 + 8007c22: 68fb ldr r3, [r7, #12] + 8007c24: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 + while (huart->TxXferCount > 0U) + 8007c28: 68fb ldr r3, [r7, #12] + 8007c2a: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 + 8007c2e: b29b uxth r3, r3 + 8007c30: 2b00 cmp r3, #0 + 8007c32: d1cc bne.n 8007bce + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + 8007c34: 683b ldr r3, [r7, #0] + 8007c36: 9300 str r3, [sp, #0] + 8007c38: 697b ldr r3, [r7, #20] + 8007c3a: 2200 movs r2, #0 + 8007c3c: 2140 movs r1, #64 ; 0x40 + 8007c3e: 68f8 ldr r0, [r7, #12] + 8007c40: f000 fd5b bl 80086fa + 8007c44: 4603 mov r3, r0 + 8007c46: 2b00 cmp r3, #0 + 8007c48: d001 beq.n 8007c4e + { + return HAL_TIMEOUT; + 8007c4a: 2303 movs r3, #3 + 8007c4c: e009 b.n 8007c62 + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 8007c4e: 68fb ldr r3, [r7, #12] + 8007c50: 2220 movs r2, #32 + 8007c52: 675a str r2, [r3, #116] ; 0x74 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8007c54: 68fb ldr r3, [r7, #12] + 8007c56: 2200 movs r2, #0 + 8007c58: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + return HAL_OK; + 8007c5c: 2300 movs r3, #0 + 8007c5e: e000 b.n 8007c62 + } + else + { + return HAL_BUSY; + 8007c60: 2302 movs r3, #2 + } +} + 8007c62: 4618 mov r0, r3 + 8007c64: 3720 adds r7, #32 + 8007c66: 46bd mov sp, r7 + 8007c68: bd80 pop {r7, pc} + ... + +08007c6c : + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + 8007c6c: b480 push {r7} + 8007c6e: b085 sub sp, #20 + 8007c70: af00 add r7, sp, #0 + 8007c72: 60f8 str r0, [r7, #12] + 8007c74: 60b9 str r1, [r7, #8] + 8007c76: 4613 mov r3, r2 + 8007c78: 80fb strh r3, [r7, #6] + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + 8007c7a: 68fb ldr r3, [r7, #12] + 8007c7c: 6f9b ldr r3, [r3, #120] ; 0x78 + 8007c7e: 2b20 cmp r3, #32 + 8007c80: f040 808a bne.w 8007d98 + { + if ((pData == NULL) || (Size == 0U)) + 8007c84: 68bb ldr r3, [r7, #8] + 8007c86: 2b00 cmp r3, #0 + 8007c88: d002 beq.n 8007c90 + 8007c8a: 88fb ldrh r3, [r7, #6] + 8007c8c: 2b00 cmp r3, #0 + 8007c8e: d101 bne.n 8007c94 + { + return HAL_ERROR; + 8007c90: 2301 movs r3, #1 + 8007c92: e082 b.n 8007d9a + } + + /* Process Locked */ + __HAL_LOCK(huart); + 8007c94: 68fb ldr r3, [r7, #12] + 8007c96: f893 3070 ldrb.w r3, [r3, #112] ; 0x70 + 8007c9a: 2b01 cmp r3, #1 + 8007c9c: d101 bne.n 8007ca2 + 8007c9e: 2302 movs r3, #2 + 8007ca0: e07b b.n 8007d9a + 8007ca2: 68fb ldr r3, [r7, #12] + 8007ca4: 2201 movs r2, #1 + 8007ca6: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + huart->pRxBuffPtr = pData; + 8007caa: 68fb ldr r3, [r7, #12] + 8007cac: 68ba ldr r2, [r7, #8] + 8007cae: 655a str r2, [r3, #84] ; 0x54 + huart->RxXferSize = Size; + 8007cb0: 68fb ldr r3, [r7, #12] + 8007cb2: 88fa ldrh r2, [r7, #6] + 8007cb4: f8a3 2058 strh.w r2, [r3, #88] ; 0x58 + huart->RxXferCount = Size; + 8007cb8: 68fb ldr r3, [r7, #12] + 8007cba: 88fa ldrh r2, [r7, #6] + 8007cbc: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + huart->RxISR = NULL; + 8007cc0: 68fb ldr r3, [r7, #12] + 8007cc2: 2200 movs r2, #0 + 8007cc4: 661a str r2, [r3, #96] ; 0x60 + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + 8007cc6: 68fb ldr r3, [r7, #12] + 8007cc8: 689b ldr r3, [r3, #8] + 8007cca: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8007cce: d10e bne.n 8007cee + 8007cd0: 68fb ldr r3, [r7, #12] + 8007cd2: 691b ldr r3, [r3, #16] + 8007cd4: 2b00 cmp r3, #0 + 8007cd6: d105 bne.n 8007ce4 + 8007cd8: 68fb ldr r3, [r7, #12] + 8007cda: f240 12ff movw r2, #511 ; 0x1ff + 8007cde: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8007ce2: e02d b.n 8007d40 + 8007ce4: 68fb ldr r3, [r7, #12] + 8007ce6: 22ff movs r2, #255 ; 0xff + 8007ce8: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8007cec: e028 b.n 8007d40 + 8007cee: 68fb ldr r3, [r7, #12] + 8007cf0: 689b ldr r3, [r3, #8] + 8007cf2: 2b00 cmp r3, #0 + 8007cf4: d10d bne.n 8007d12 + 8007cf6: 68fb ldr r3, [r7, #12] + 8007cf8: 691b ldr r3, [r3, #16] + 8007cfa: 2b00 cmp r3, #0 + 8007cfc: d104 bne.n 8007d08 + 8007cfe: 68fb ldr r3, [r7, #12] + 8007d00: 22ff movs r2, #255 ; 0xff + 8007d02: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8007d06: e01b b.n 8007d40 + 8007d08: 68fb ldr r3, [r7, #12] + 8007d0a: 227f movs r2, #127 ; 0x7f + 8007d0c: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8007d10: e016 b.n 8007d40 + 8007d12: 68fb ldr r3, [r7, #12] + 8007d14: 689b ldr r3, [r3, #8] + 8007d16: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 + 8007d1a: d10d bne.n 8007d38 + 8007d1c: 68fb ldr r3, [r7, #12] + 8007d1e: 691b ldr r3, [r3, #16] + 8007d20: 2b00 cmp r3, #0 + 8007d22: d104 bne.n 8007d2e + 8007d24: 68fb ldr r3, [r7, #12] + 8007d26: 227f movs r2, #127 ; 0x7f + 8007d28: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8007d2c: e008 b.n 8007d40 + 8007d2e: 68fb ldr r3, [r7, #12] + 8007d30: 223f movs r2, #63 ; 0x3f + 8007d32: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8007d36: e003 b.n 8007d40 + 8007d38: 68fb ldr r3, [r7, #12] + 8007d3a: 2200 movs r2, #0 + 8007d3c: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8007d40: 68fb ldr r3, [r7, #12] + 8007d42: 2200 movs r2, #0 + 8007d44: 67da str r2, [r3, #124] ; 0x7c + huart->RxState = HAL_UART_STATE_BUSY_RX; + 8007d46: 68fb ldr r3, [r7, #12] + 8007d48: 2222 movs r2, #34 ; 0x22 + 8007d4a: 679a str r2, [r3, #120] ; 0x78 + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8007d4c: 68fb ldr r3, [r7, #12] + 8007d4e: 681b ldr r3, [r3, #0] + 8007d50: 689a ldr r2, [r3, #8] + 8007d52: 68fb ldr r3, [r7, #12] + 8007d54: 681b ldr r3, [r3, #0] + 8007d56: f042 0201 orr.w r2, r2, #1 + 8007d5a: 609a str r2, [r3, #8] + + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 8007d5c: 68fb ldr r3, [r7, #12] + 8007d5e: 689b ldr r3, [r3, #8] + 8007d60: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8007d64: d107 bne.n 8007d76 + 8007d66: 68fb ldr r3, [r7, #12] + 8007d68: 691b ldr r3, [r3, #16] + 8007d6a: 2b00 cmp r3, #0 + 8007d6c: d103 bne.n 8007d76 + { + huart->RxISR = UART_RxISR_16BIT; + 8007d6e: 68fb ldr r3, [r7, #12] + 8007d70: 4a0d ldr r2, [pc, #52] ; (8007da8 ) + 8007d72: 661a str r2, [r3, #96] ; 0x60 + 8007d74: e002 b.n 8007d7c + } + else + { + huart->RxISR = UART_RxISR_8BIT; + 8007d76: 68fb ldr r3, [r7, #12] + 8007d78: 4a0c ldr r2, [pc, #48] ; (8007dac ) + 8007d7a: 661a str r2, [r3, #96] ; 0x60 + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8007d7c: 68fb ldr r3, [r7, #12] + 8007d7e: 2200 movs r2, #0 + 8007d80: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + 8007d84: 68fb ldr r3, [r7, #12] + 8007d86: 681b ldr r3, [r3, #0] + 8007d88: 681a ldr r2, [r3, #0] + 8007d8a: 68fb ldr r3, [r7, #12] + 8007d8c: 681b ldr r3, [r3, #0] + 8007d8e: f442 7290 orr.w r2, r2, #288 ; 0x120 + 8007d92: 601a str r2, [r3, #0] + + return HAL_OK; + 8007d94: 2300 movs r3, #0 + 8007d96: e000 b.n 8007d9a + } + else + { + return HAL_BUSY; + 8007d98: 2302 movs r3, #2 + } +} + 8007d9a: 4618 mov r0, r3 + 8007d9c: 3714 adds r7, #20 + 8007d9e: 46bd mov sp, r7 + 8007da0: f85d 7b04 ldr.w r7, [sp], #4 + 8007da4: 4770 bx lr + 8007da6: bf00 nop + 8007da8: 080088cf .word 0x080088cf + 8007dac: 08008829 .word 0x08008829 + +08007db0 : + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + 8007db0: b580 push {r7, lr} + 8007db2: b088 sub sp, #32 + 8007db4: af00 add r7, sp, #0 + 8007db6: 6078 str r0, [r7, #4] + uint32_t isrflags = READ_REG(huart->Instance->ISR); + 8007db8: 687b ldr r3, [r7, #4] + 8007dba: 681b ldr r3, [r3, #0] + 8007dbc: 69db ldr r3, [r3, #28] + 8007dbe: 61fb str r3, [r7, #28] + uint32_t cr1its = READ_REG(huart->Instance->CR1); + 8007dc0: 687b ldr r3, [r7, #4] + 8007dc2: 681b ldr r3, [r3, #0] + 8007dc4: 681b ldr r3, [r3, #0] + 8007dc6: 61bb str r3, [r7, #24] + uint32_t cr3its = READ_REG(huart->Instance->CR3); + 8007dc8: 687b ldr r3, [r7, #4] + 8007dca: 681b ldr r3, [r3, #0] + 8007dcc: 689b ldr r3, [r3, #8] + 8007dce: 617b str r3, [r7, #20] + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + 8007dd0: 69fb ldr r3, [r7, #28] + 8007dd2: f003 030f and.w r3, r3, #15 + 8007dd6: 613b str r3, [r7, #16] + if (errorflags == 0U) + 8007dd8: 693b ldr r3, [r7, #16] + 8007dda: 2b00 cmp r3, #0 + 8007ddc: d113 bne.n 8007e06 + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE) != 0U) + 8007dde: 69fb ldr r3, [r7, #28] + 8007de0: f003 0320 and.w r3, r3, #32 + 8007de4: 2b00 cmp r3, #0 + 8007de6: d00e beq.n 8007e06 + && ((cr1its & USART_CR1_RXNEIE) != 0U)) + 8007de8: 69bb ldr r3, [r7, #24] + 8007dea: f003 0320 and.w r3, r3, #32 + 8007dee: 2b00 cmp r3, #0 + 8007df0: d009 beq.n 8007e06 + { + if (huart->RxISR != NULL) + 8007df2: 687b ldr r3, [r7, #4] + 8007df4: 6e1b ldr r3, [r3, #96] ; 0x60 + 8007df6: 2b00 cmp r3, #0 + 8007df8: f000 80eb beq.w 8007fd2 + { + huart->RxISR(huart); + 8007dfc: 687b ldr r3, [r7, #4] + 8007dfe: 6e1b ldr r3, [r3, #96] ; 0x60 + 8007e00: 6878 ldr r0, [r7, #4] + 8007e02: 4798 blx r3 + } + return; + 8007e04: e0e5 b.n 8007fd2 + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + 8007e06: 693b ldr r3, [r7, #16] + 8007e08: 2b00 cmp r3, #0 + 8007e0a: f000 80c0 beq.w 8007f8e + && (((cr3its & USART_CR3_EIE) != 0U) + 8007e0e: 697b ldr r3, [r7, #20] + 8007e10: f003 0301 and.w r3, r3, #1 + 8007e14: 2b00 cmp r3, #0 + 8007e16: d105 bne.n 8007e24 + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U))) + 8007e18: 69bb ldr r3, [r7, #24] + 8007e1a: f403 7390 and.w r3, r3, #288 ; 0x120 + 8007e1e: 2b00 cmp r3, #0 + 8007e20: f000 80b5 beq.w 8007f8e + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + 8007e24: 69fb ldr r3, [r7, #28] + 8007e26: f003 0301 and.w r3, r3, #1 + 8007e2a: 2b00 cmp r3, #0 + 8007e2c: d00e beq.n 8007e4c + 8007e2e: 69bb ldr r3, [r7, #24] + 8007e30: f403 7380 and.w r3, r3, #256 ; 0x100 + 8007e34: 2b00 cmp r3, #0 + 8007e36: d009 beq.n 8007e4c + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + 8007e38: 687b ldr r3, [r7, #4] + 8007e3a: 681b ldr r3, [r3, #0] + 8007e3c: 2201 movs r2, #1 + 8007e3e: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_PE; + 8007e40: 687b ldr r3, [r7, #4] + 8007e42: 6fdb ldr r3, [r3, #124] ; 0x7c + 8007e44: f043 0201 orr.w r2, r3, #1 + 8007e48: 687b ldr r3, [r7, #4] + 8007e4a: 67da str r2, [r3, #124] ; 0x7c + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8007e4c: 69fb ldr r3, [r7, #28] + 8007e4e: f003 0302 and.w r3, r3, #2 + 8007e52: 2b00 cmp r3, #0 + 8007e54: d00e beq.n 8007e74 + 8007e56: 697b ldr r3, [r7, #20] + 8007e58: f003 0301 and.w r3, r3, #1 + 8007e5c: 2b00 cmp r3, #0 + 8007e5e: d009 beq.n 8007e74 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + 8007e60: 687b ldr r3, [r7, #4] + 8007e62: 681b ldr r3, [r3, #0] + 8007e64: 2202 movs r2, #2 + 8007e66: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_FE; + 8007e68: 687b ldr r3, [r7, #4] + 8007e6a: 6fdb ldr r3, [r3, #124] ; 0x7c + 8007e6c: f043 0204 orr.w r2, r3, #4 + 8007e70: 687b ldr r3, [r7, #4] + 8007e72: 67da str r2, [r3, #124] ; 0x7c + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8007e74: 69fb ldr r3, [r7, #28] + 8007e76: f003 0304 and.w r3, r3, #4 + 8007e7a: 2b00 cmp r3, #0 + 8007e7c: d00e beq.n 8007e9c + 8007e7e: 697b ldr r3, [r7, #20] + 8007e80: f003 0301 and.w r3, r3, #1 + 8007e84: 2b00 cmp r3, #0 + 8007e86: d009 beq.n 8007e9c + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + 8007e88: 687b ldr r3, [r7, #4] + 8007e8a: 681b ldr r3, [r3, #0] + 8007e8c: 2204 movs r2, #4 + 8007e8e: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_NE; + 8007e90: 687b ldr r3, [r7, #4] + 8007e92: 6fdb ldr r3, [r3, #124] ; 0x7c + 8007e94: f043 0202 orr.w r2, r3, #2 + 8007e98: 687b ldr r3, [r7, #4] + 8007e9a: 67da str r2, [r3, #124] ; 0x7c + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + 8007e9c: 69fb ldr r3, [r7, #28] + 8007e9e: f003 0308 and.w r3, r3, #8 + 8007ea2: 2b00 cmp r3, #0 + 8007ea4: d013 beq.n 8007ece + && (((cr1its & USART_CR1_RXNEIE) != 0U) || + 8007ea6: 69bb ldr r3, [r7, #24] + 8007ea8: f003 0320 and.w r3, r3, #32 + 8007eac: 2b00 cmp r3, #0 + 8007eae: d104 bne.n 8007eba + ((cr3its & USART_CR3_EIE) != 0U))) + 8007eb0: 697b ldr r3, [r7, #20] + 8007eb2: f003 0301 and.w r3, r3, #1 + && (((cr1its & USART_CR1_RXNEIE) != 0U) || + 8007eb6: 2b00 cmp r3, #0 + 8007eb8: d009 beq.n 8007ece + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + 8007eba: 687b ldr r3, [r7, #4] + 8007ebc: 681b ldr r3, [r3, #0] + 8007ebe: 2208 movs r2, #8 + 8007ec0: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + 8007ec2: 687b ldr r3, [r7, #4] + 8007ec4: 6fdb ldr r3, [r3, #124] ; 0x7c + 8007ec6: f043 0208 orr.w r2, r3, #8 + 8007eca: 687b ldr r3, [r7, #4] + 8007ecc: 67da str r2, [r3, #124] ; 0x7c + } + + /* Call UART Error Call back function if need be --------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + 8007ece: 687b ldr r3, [r7, #4] + 8007ed0: 6fdb ldr r3, [r3, #124] ; 0x7c + 8007ed2: 2b00 cmp r3, #0 + 8007ed4: d07f beq.n 8007fd6 + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE) != 0U) + 8007ed6: 69fb ldr r3, [r7, #28] + 8007ed8: f003 0320 and.w r3, r3, #32 + 8007edc: 2b00 cmp r3, #0 + 8007ede: d00c beq.n 8007efa + && ((cr1its & USART_CR1_RXNEIE) != 0U)) + 8007ee0: 69bb ldr r3, [r7, #24] + 8007ee2: f003 0320 and.w r3, r3, #32 + 8007ee6: 2b00 cmp r3, #0 + 8007ee8: d007 beq.n 8007efa + { + if (huart->RxISR != NULL) + 8007eea: 687b ldr r3, [r7, #4] + 8007eec: 6e1b ldr r3, [r3, #96] ; 0x60 + 8007eee: 2b00 cmp r3, #0 + 8007ef0: d003 beq.n 8007efa + { + huart->RxISR(huart); + 8007ef2: 687b ldr r3, [r7, #4] + 8007ef4: 6e1b ldr r3, [r3, #96] ; 0x60 + 8007ef6: 6878 ldr r0, [r7, #4] + 8007ef8: 4798 blx r3 + } + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + errorcode = huart->ErrorCode; + 8007efa: 687b ldr r3, [r7, #4] + 8007efc: 6fdb ldr r3, [r3, #124] ; 0x7c + 8007efe: 60fb str r3, [r7, #12] + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + 8007f00: 687b ldr r3, [r7, #4] + 8007f02: 681b ldr r3, [r3, #0] + 8007f04: 689b ldr r3, [r3, #8] + 8007f06: f003 0340 and.w r3, r3, #64 ; 0x40 + 8007f0a: 2b40 cmp r3, #64 ; 0x40 + 8007f0c: d004 beq.n 8007f18 + ((errorcode & HAL_UART_ERROR_ORE) != 0U)) + 8007f0e: 68fb ldr r3, [r7, #12] + 8007f10: f003 0308 and.w r3, r3, #8 + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + 8007f14: 2b00 cmp r3, #0 + 8007f16: d031 beq.n 8007f7c + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + 8007f18: 6878 ldr r0, [r7, #4] + 8007f1a: f000 fc36 bl 800878a + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8007f1e: 687b ldr r3, [r7, #4] + 8007f20: 681b ldr r3, [r3, #0] + 8007f22: 689b ldr r3, [r3, #8] + 8007f24: f003 0340 and.w r3, r3, #64 ; 0x40 + 8007f28: 2b40 cmp r3, #64 ; 0x40 + 8007f2a: d123 bne.n 8007f74 + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 8007f2c: 687b ldr r3, [r7, #4] + 8007f2e: 681b ldr r3, [r3, #0] + 8007f30: 689a ldr r2, [r3, #8] + 8007f32: 687b ldr r3, [r7, #4] + 8007f34: 681b ldr r3, [r3, #0] + 8007f36: f022 0240 bic.w r2, r2, #64 ; 0x40 + 8007f3a: 609a str r2, [r3, #8] + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + 8007f3c: 687b ldr r3, [r7, #4] + 8007f3e: 6edb ldr r3, [r3, #108] ; 0x6c + 8007f40: 2b00 cmp r3, #0 + 8007f42: d013 beq.n 8007f6c + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + 8007f44: 687b ldr r3, [r7, #4] + 8007f46: 6edb ldr r3, [r3, #108] ; 0x6c + 8007f48: 4a26 ldr r2, [pc, #152] ; (8007fe4 ) + 8007f4a: 651a str r2, [r3, #80] ; 0x50 + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + 8007f4c: 687b ldr r3, [r7, #4] + 8007f4e: 6edb ldr r3, [r3, #108] ; 0x6c + 8007f50: 4618 mov r0, r3 + 8007f52: f7fd fa5c bl 800540e + 8007f56: 4603 mov r3, r0 + 8007f58: 2b00 cmp r3, #0 + 8007f5a: d016 beq.n 8007f8a + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + 8007f5c: 687b ldr r3, [r7, #4] + 8007f5e: 6edb ldr r3, [r3, #108] ; 0x6c + 8007f60: 6d1b ldr r3, [r3, #80] ; 0x50 + 8007f62: 687a ldr r2, [r7, #4] + 8007f64: 6ed2 ldr r2, [r2, #108] ; 0x6c + 8007f66: 4610 mov r0, r2 + 8007f68: 4798 blx r3 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8007f6a: e00e b.n 8007f8a +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8007f6c: 6878 ldr r0, [r7, #4] + 8007f6e: f000 f845 bl 8007ffc + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8007f72: e00a b.n 8007f8a +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8007f74: 6878 ldr r0, [r7, #4] + 8007f76: f000 f841 bl 8007ffc + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8007f7a: e006 b.n 8007f8a +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8007f7c: 6878 ldr r0, [r7, #4] + 8007f7e: f000 f83d bl 8007ffc +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8007f82: 687b ldr r3, [r7, #4] + 8007f84: 2200 movs r2, #0 + 8007f86: 67da str r2, [r3, #124] ; 0x7c + } + } + return; + 8007f88: e025 b.n 8007fd6 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8007f8a: bf00 nop + return; + 8007f8c: e023 b.n 8007fd6 + + } /* End if some error occurs */ + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE) != 0U) + 8007f8e: 69fb ldr r3, [r7, #28] + 8007f90: f003 0380 and.w r3, r3, #128 ; 0x80 + 8007f94: 2b00 cmp r3, #0 + 8007f96: d00d beq.n 8007fb4 + && ((cr1its & USART_CR1_TXEIE) != 0U)) + 8007f98: 69bb ldr r3, [r7, #24] + 8007f9a: f003 0380 and.w r3, r3, #128 ; 0x80 + 8007f9e: 2b00 cmp r3, #0 + 8007fa0: d008 beq.n 8007fb4 + { + if (huart->TxISR != NULL) + 8007fa2: 687b ldr r3, [r7, #4] + 8007fa4: 6e5b ldr r3, [r3, #100] ; 0x64 + 8007fa6: 2b00 cmp r3, #0 + 8007fa8: d017 beq.n 8007fda + { + huart->TxISR(huart); + 8007faa: 687b ldr r3, [r7, #4] + 8007fac: 6e5b ldr r3, [r3, #100] ; 0x64 + 8007fae: 6878 ldr r0, [r7, #4] + 8007fb0: 4798 blx r3 + } + return; + 8007fb2: e012 b.n 8007fda + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + 8007fb4: 69fb ldr r3, [r7, #28] + 8007fb6: f003 0340 and.w r3, r3, #64 ; 0x40 + 8007fba: 2b00 cmp r3, #0 + 8007fbc: d00e beq.n 8007fdc + 8007fbe: 69bb ldr r3, [r7, #24] + 8007fc0: f003 0340 and.w r3, r3, #64 ; 0x40 + 8007fc4: 2b00 cmp r3, #0 + 8007fc6: d009 beq.n 8007fdc + { + UART_EndTransmit_IT(huart); + 8007fc8: 6878 ldr r0, [r7, #4] + 8007fca: f000 fc14 bl 80087f6 + return; + 8007fce: bf00 nop + 8007fd0: e004 b.n 8007fdc + return; + 8007fd2: bf00 nop + 8007fd4: e002 b.n 8007fdc + return; + 8007fd6: bf00 nop + 8007fd8: e000 b.n 8007fdc + return; + 8007fda: bf00 nop + } + +} + 8007fdc: 3720 adds r7, #32 + 8007fde: 46bd mov sp, r7 + 8007fe0: bd80 pop {r7, pc} + 8007fe2: bf00 nop + 8007fe4: 080087cb .word 0x080087cb + +08007fe8 : + * @brief Tx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + 8007fe8: b480 push {r7} + 8007fea: b083 sub sp, #12 + 8007fec: af00 add r7, sp, #0 + 8007fee: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file. + */ +} + 8007ff0: bf00 nop + 8007ff2: 370c adds r7, #12 + 8007ff4: 46bd mov sp, r7 + 8007ff6: f85d 7b04 ldr.w r7, [sp], #4 + 8007ffa: 4770 bx lr + +08007ffc : + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + 8007ffc: b480 push {r7} + 8007ffe: b083 sub sp, #12 + 8008000: af00 add r7, sp, #0 + 8008002: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + 8008004: bf00 nop + 8008006: 370c adds r7, #12 + 8008008: 46bd mov sp, r7 + 800800a: f85d 7b04 ldr.w r7, [sp], #4 + 800800e: 4770 bx lr + +08008010 : + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + 8008010: b580 push {r7, lr} + 8008012: b088 sub sp, #32 + 8008014: af00 add r7, sp, #0 + 8008016: 6078 str r0, [r7, #4] + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv = 0x00000000U; + 8008018: 2300 movs r3, #0 + 800801a: 61bb str r3, [r7, #24] + HAL_StatusTypeDef ret = HAL_OK; + 800801c: 2300 movs r3, #0 + 800801e: 75fb strb r3, [r7, #23] + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + 8008020: 687b ldr r3, [r7, #4] + 8008022: 689a ldr r2, [r3, #8] + 8008024: 687b ldr r3, [r7, #4] + 8008026: 691b ldr r3, [r3, #16] + 8008028: 431a orrs r2, r3 + 800802a: 687b ldr r3, [r7, #4] + 800802c: 695b ldr r3, [r3, #20] + 800802e: 431a orrs r2, r3 + 8008030: 687b ldr r3, [r7, #4] + 8008032: 69db ldr r3, [r3, #28] + 8008034: 4313 orrs r3, r2 + 8008036: 613b str r3, [r7, #16] + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 8008038: 687b ldr r3, [r7, #4] + 800803a: 681b ldr r3, [r3, #0] + 800803c: 681a ldr r2, [r3, #0] + 800803e: 4bb1 ldr r3, [pc, #708] ; (8008304 ) + 8008040: 4013 ands r3, r2 + 8008042: 687a ldr r2, [r7, #4] + 8008044: 6812 ldr r2, [r2, #0] + 8008046: 6939 ldr r1, [r7, #16] + 8008048: 430b orrs r3, r1 + 800804a: 6013 str r3, [r2, #0] + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + 800804c: 687b ldr r3, [r7, #4] + 800804e: 681b ldr r3, [r3, #0] + 8008050: 685b ldr r3, [r3, #4] + 8008052: f423 5140 bic.w r1, r3, #12288 ; 0x3000 + 8008056: 687b ldr r3, [r7, #4] + 8008058: 68da ldr r2, [r3, #12] + 800805a: 687b ldr r3, [r7, #4] + 800805c: 681b ldr r3, [r3, #0] + 800805e: 430a orrs r2, r1 + 8008060: 605a str r2, [r3, #4] + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + 8008062: 687b ldr r3, [r7, #4] + 8008064: 699b ldr r3, [r3, #24] + 8008066: 613b str r3, [r7, #16] + + tmpreg |= huart->Init.OneBitSampling; + 8008068: 687b ldr r3, [r7, #4] + 800806a: 6a1b ldr r3, [r3, #32] + 800806c: 693a ldr r2, [r7, #16] + 800806e: 4313 orrs r3, r2 + 8008070: 613b str r3, [r7, #16] + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + 8008072: 687b ldr r3, [r7, #4] + 8008074: 681b ldr r3, [r3, #0] + 8008076: 689b ldr r3, [r3, #8] + 8008078: f423 6130 bic.w r1, r3, #2816 ; 0xb00 + 800807c: 687b ldr r3, [r7, #4] + 800807e: 681b ldr r3, [r3, #0] + 8008080: 693a ldr r2, [r7, #16] + 8008082: 430a orrs r2, r1 + 8008084: 609a str r2, [r3, #8] + + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + 8008086: 687b ldr r3, [r7, #4] + 8008088: 681b ldr r3, [r3, #0] + 800808a: 4a9f ldr r2, [pc, #636] ; (8008308 ) + 800808c: 4293 cmp r3, r2 + 800808e: d121 bne.n 80080d4 + 8008090: 4b9e ldr r3, [pc, #632] ; (800830c ) + 8008092: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8008096: f003 0303 and.w r3, r3, #3 + 800809a: 2b03 cmp r3, #3 + 800809c: d816 bhi.n 80080cc + 800809e: a201 add r2, pc, #4 ; (adr r2, 80080a4 ) + 80080a0: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80080a4: 080080b5 .word 0x080080b5 + 80080a8: 080080c1 .word 0x080080c1 + 80080ac: 080080bb .word 0x080080bb + 80080b0: 080080c7 .word 0x080080c7 + 80080b4: 2301 movs r3, #1 + 80080b6: 77fb strb r3, [r7, #31] + 80080b8: e151 b.n 800835e + 80080ba: 2302 movs r3, #2 + 80080bc: 77fb strb r3, [r7, #31] + 80080be: e14e b.n 800835e + 80080c0: 2304 movs r3, #4 + 80080c2: 77fb strb r3, [r7, #31] + 80080c4: e14b b.n 800835e + 80080c6: 2308 movs r3, #8 + 80080c8: 77fb strb r3, [r7, #31] + 80080ca: e148 b.n 800835e + 80080cc: 2310 movs r3, #16 + 80080ce: 77fb strb r3, [r7, #31] + 80080d0: bf00 nop + 80080d2: e144 b.n 800835e + 80080d4: 687b ldr r3, [r7, #4] + 80080d6: 681b ldr r3, [r3, #0] + 80080d8: 4a8d ldr r2, [pc, #564] ; (8008310 ) + 80080da: 4293 cmp r3, r2 + 80080dc: d134 bne.n 8008148 + 80080de: 4b8b ldr r3, [pc, #556] ; (800830c ) + 80080e0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80080e4: f003 030c and.w r3, r3, #12 + 80080e8: 2b0c cmp r3, #12 + 80080ea: d829 bhi.n 8008140 + 80080ec: a201 add r2, pc, #4 ; (adr r2, 80080f4 ) + 80080ee: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80080f2: bf00 nop + 80080f4: 08008129 .word 0x08008129 + 80080f8: 08008141 .word 0x08008141 + 80080fc: 08008141 .word 0x08008141 + 8008100: 08008141 .word 0x08008141 + 8008104: 08008135 .word 0x08008135 + 8008108: 08008141 .word 0x08008141 + 800810c: 08008141 .word 0x08008141 + 8008110: 08008141 .word 0x08008141 + 8008114: 0800812f .word 0x0800812f + 8008118: 08008141 .word 0x08008141 + 800811c: 08008141 .word 0x08008141 + 8008120: 08008141 .word 0x08008141 + 8008124: 0800813b .word 0x0800813b + 8008128: 2300 movs r3, #0 + 800812a: 77fb strb r3, [r7, #31] + 800812c: e117 b.n 800835e + 800812e: 2302 movs r3, #2 + 8008130: 77fb strb r3, [r7, #31] + 8008132: e114 b.n 800835e + 8008134: 2304 movs r3, #4 + 8008136: 77fb strb r3, [r7, #31] + 8008138: e111 b.n 800835e + 800813a: 2308 movs r3, #8 + 800813c: 77fb strb r3, [r7, #31] + 800813e: e10e b.n 800835e + 8008140: 2310 movs r3, #16 + 8008142: 77fb strb r3, [r7, #31] + 8008144: bf00 nop + 8008146: e10a b.n 800835e + 8008148: 687b ldr r3, [r7, #4] + 800814a: 681b ldr r3, [r3, #0] + 800814c: 4a71 ldr r2, [pc, #452] ; (8008314 ) + 800814e: 4293 cmp r3, r2 + 8008150: d120 bne.n 8008194 + 8008152: 4b6e ldr r3, [pc, #440] ; (800830c ) + 8008154: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8008158: f003 0330 and.w r3, r3, #48 ; 0x30 + 800815c: 2b10 cmp r3, #16 + 800815e: d00f beq.n 8008180 + 8008160: 2b10 cmp r3, #16 + 8008162: d802 bhi.n 800816a + 8008164: 2b00 cmp r3, #0 + 8008166: d005 beq.n 8008174 + 8008168: e010 b.n 800818c + 800816a: 2b20 cmp r3, #32 + 800816c: d005 beq.n 800817a + 800816e: 2b30 cmp r3, #48 ; 0x30 + 8008170: d009 beq.n 8008186 + 8008172: e00b b.n 800818c + 8008174: 2300 movs r3, #0 + 8008176: 77fb strb r3, [r7, #31] + 8008178: e0f1 b.n 800835e + 800817a: 2302 movs r3, #2 + 800817c: 77fb strb r3, [r7, #31] + 800817e: e0ee b.n 800835e + 8008180: 2304 movs r3, #4 + 8008182: 77fb strb r3, [r7, #31] + 8008184: e0eb b.n 800835e + 8008186: 2308 movs r3, #8 + 8008188: 77fb strb r3, [r7, #31] + 800818a: e0e8 b.n 800835e + 800818c: 2310 movs r3, #16 + 800818e: 77fb strb r3, [r7, #31] + 8008190: bf00 nop + 8008192: e0e4 b.n 800835e + 8008194: 687b ldr r3, [r7, #4] + 8008196: 681b ldr r3, [r3, #0] + 8008198: 4a5f ldr r2, [pc, #380] ; (8008318 ) + 800819a: 4293 cmp r3, r2 + 800819c: d120 bne.n 80081e0 + 800819e: 4b5b ldr r3, [pc, #364] ; (800830c ) + 80081a0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80081a4: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 80081a8: 2b40 cmp r3, #64 ; 0x40 + 80081aa: d00f beq.n 80081cc + 80081ac: 2b40 cmp r3, #64 ; 0x40 + 80081ae: d802 bhi.n 80081b6 + 80081b0: 2b00 cmp r3, #0 + 80081b2: d005 beq.n 80081c0 + 80081b4: e010 b.n 80081d8 + 80081b6: 2b80 cmp r3, #128 ; 0x80 + 80081b8: d005 beq.n 80081c6 + 80081ba: 2bc0 cmp r3, #192 ; 0xc0 + 80081bc: d009 beq.n 80081d2 + 80081be: e00b b.n 80081d8 + 80081c0: 2300 movs r3, #0 + 80081c2: 77fb strb r3, [r7, #31] + 80081c4: e0cb b.n 800835e + 80081c6: 2302 movs r3, #2 + 80081c8: 77fb strb r3, [r7, #31] + 80081ca: e0c8 b.n 800835e + 80081cc: 2304 movs r3, #4 + 80081ce: 77fb strb r3, [r7, #31] + 80081d0: e0c5 b.n 800835e + 80081d2: 2308 movs r3, #8 + 80081d4: 77fb strb r3, [r7, #31] + 80081d6: e0c2 b.n 800835e + 80081d8: 2310 movs r3, #16 + 80081da: 77fb strb r3, [r7, #31] + 80081dc: bf00 nop + 80081de: e0be b.n 800835e + 80081e0: 687b ldr r3, [r7, #4] + 80081e2: 681b ldr r3, [r3, #0] + 80081e4: 4a4d ldr r2, [pc, #308] ; (800831c ) + 80081e6: 4293 cmp r3, r2 + 80081e8: d124 bne.n 8008234 + 80081ea: 4b48 ldr r3, [pc, #288] ; (800830c ) + 80081ec: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80081f0: f403 7340 and.w r3, r3, #768 ; 0x300 + 80081f4: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 80081f8: d012 beq.n 8008220 + 80081fa: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 80081fe: d802 bhi.n 8008206 + 8008200: 2b00 cmp r3, #0 + 8008202: d007 beq.n 8008214 + 8008204: e012 b.n 800822c + 8008206: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 800820a: d006 beq.n 800821a + 800820c: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 8008210: d009 beq.n 8008226 + 8008212: e00b b.n 800822c + 8008214: 2300 movs r3, #0 + 8008216: 77fb strb r3, [r7, #31] + 8008218: e0a1 b.n 800835e + 800821a: 2302 movs r3, #2 + 800821c: 77fb strb r3, [r7, #31] + 800821e: e09e b.n 800835e + 8008220: 2304 movs r3, #4 + 8008222: 77fb strb r3, [r7, #31] + 8008224: e09b b.n 800835e + 8008226: 2308 movs r3, #8 + 8008228: 77fb strb r3, [r7, #31] + 800822a: e098 b.n 800835e + 800822c: 2310 movs r3, #16 + 800822e: 77fb strb r3, [r7, #31] + 8008230: bf00 nop + 8008232: e094 b.n 800835e + 8008234: 687b ldr r3, [r7, #4] + 8008236: 681b ldr r3, [r3, #0] + 8008238: 4a39 ldr r2, [pc, #228] ; (8008320 ) + 800823a: 4293 cmp r3, r2 + 800823c: d124 bne.n 8008288 + 800823e: 4b33 ldr r3, [pc, #204] ; (800830c ) + 8008240: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8008244: f403 6340 and.w r3, r3, #3072 ; 0xc00 + 8008248: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 800824c: d012 beq.n 8008274 + 800824e: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8008252: d802 bhi.n 800825a + 8008254: 2b00 cmp r3, #0 + 8008256: d007 beq.n 8008268 + 8008258: e012 b.n 8008280 + 800825a: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 800825e: d006 beq.n 800826e + 8008260: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 + 8008264: d009 beq.n 800827a + 8008266: e00b b.n 8008280 + 8008268: 2301 movs r3, #1 + 800826a: 77fb strb r3, [r7, #31] + 800826c: e077 b.n 800835e + 800826e: 2302 movs r3, #2 + 8008270: 77fb strb r3, [r7, #31] + 8008272: e074 b.n 800835e + 8008274: 2304 movs r3, #4 + 8008276: 77fb strb r3, [r7, #31] + 8008278: e071 b.n 800835e + 800827a: 2308 movs r3, #8 + 800827c: 77fb strb r3, [r7, #31] + 800827e: e06e b.n 800835e + 8008280: 2310 movs r3, #16 + 8008282: 77fb strb r3, [r7, #31] + 8008284: bf00 nop + 8008286: e06a b.n 800835e + 8008288: 687b ldr r3, [r7, #4] + 800828a: 681b ldr r3, [r3, #0] + 800828c: 4a25 ldr r2, [pc, #148] ; (8008324 ) + 800828e: 4293 cmp r3, r2 + 8008290: d124 bne.n 80082dc + 8008292: 4b1e ldr r3, [pc, #120] ; (800830c ) + 8008294: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8008298: f403 5340 and.w r3, r3, #12288 ; 0x3000 + 800829c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 80082a0: d012 beq.n 80082c8 + 80082a2: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 80082a6: d802 bhi.n 80082ae + 80082a8: 2b00 cmp r3, #0 + 80082aa: d007 beq.n 80082bc + 80082ac: e012 b.n 80082d4 + 80082ae: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 80082b2: d006 beq.n 80082c2 + 80082b4: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 + 80082b8: d009 beq.n 80082ce + 80082ba: e00b b.n 80082d4 + 80082bc: 2300 movs r3, #0 + 80082be: 77fb strb r3, [r7, #31] + 80082c0: e04d b.n 800835e + 80082c2: 2302 movs r3, #2 + 80082c4: 77fb strb r3, [r7, #31] + 80082c6: e04a b.n 800835e + 80082c8: 2304 movs r3, #4 + 80082ca: 77fb strb r3, [r7, #31] + 80082cc: e047 b.n 800835e + 80082ce: 2308 movs r3, #8 + 80082d0: 77fb strb r3, [r7, #31] + 80082d2: e044 b.n 800835e + 80082d4: 2310 movs r3, #16 + 80082d6: 77fb strb r3, [r7, #31] + 80082d8: bf00 nop + 80082da: e040 b.n 800835e + 80082dc: 687b ldr r3, [r7, #4] + 80082de: 681b ldr r3, [r3, #0] + 80082e0: 4a11 ldr r2, [pc, #68] ; (8008328 ) + 80082e2: 4293 cmp r3, r2 + 80082e4: d139 bne.n 800835a + 80082e6: 4b09 ldr r3, [pc, #36] ; (800830c ) + 80082e8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80082ec: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 80082f0: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 80082f4: d027 beq.n 8008346 + 80082f6: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 80082fa: d817 bhi.n 800832c + 80082fc: 2b00 cmp r3, #0 + 80082fe: d01c beq.n 800833a + 8008300: e027 b.n 8008352 + 8008302: bf00 nop + 8008304: efff69f3 .word 0xefff69f3 + 8008308: 40011000 .word 0x40011000 + 800830c: 40023800 .word 0x40023800 + 8008310: 40004400 .word 0x40004400 + 8008314: 40004800 .word 0x40004800 + 8008318: 40004c00 .word 0x40004c00 + 800831c: 40005000 .word 0x40005000 + 8008320: 40011400 .word 0x40011400 + 8008324: 40007800 .word 0x40007800 + 8008328: 40007c00 .word 0x40007c00 + 800832c: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8008330: d006 beq.n 8008340 + 8008332: f5b3 4f40 cmp.w r3, #49152 ; 0xc000 + 8008336: d009 beq.n 800834c + 8008338: e00b b.n 8008352 + 800833a: 2300 movs r3, #0 + 800833c: 77fb strb r3, [r7, #31] + 800833e: e00e b.n 800835e + 8008340: 2302 movs r3, #2 + 8008342: 77fb strb r3, [r7, #31] + 8008344: e00b b.n 800835e + 8008346: 2304 movs r3, #4 + 8008348: 77fb strb r3, [r7, #31] + 800834a: e008 b.n 800835e + 800834c: 2308 movs r3, #8 + 800834e: 77fb strb r3, [r7, #31] + 8008350: e005 b.n 800835e + 8008352: 2310 movs r3, #16 + 8008354: 77fb strb r3, [r7, #31] + 8008356: bf00 nop + 8008358: e001 b.n 800835e + 800835a: 2310 movs r3, #16 + 800835c: 77fb strb r3, [r7, #31] + + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + 800835e: 687b ldr r3, [r7, #4] + 8008360: 69db ldr r3, [r3, #28] + 8008362: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8008366: d17c bne.n 8008462 + { + switch (clocksource) + 8008368: 7ffb ldrb r3, [r7, #31] + 800836a: 2b08 cmp r3, #8 + 800836c: d859 bhi.n 8008422 + 800836e: a201 add r2, pc, #4 ; (adr r2, 8008374 ) + 8008370: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8008374: 08008399 .word 0x08008399 + 8008378: 080083b7 .word 0x080083b7 + 800837c: 080083d5 .word 0x080083d5 + 8008380: 08008423 .word 0x08008423 + 8008384: 080083ed .word 0x080083ed + 8008388: 08008423 .word 0x08008423 + 800838c: 08008423 .word 0x08008423 + 8008390: 08008423 .word 0x08008423 + 8008394: 0800840b .word 0x0800840b + { + case UART_CLOCKSOURCE_PCLK1: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + 8008398: f7fd fe50 bl 800603c + 800839c: 4603 mov r3, r0 + 800839e: 005a lsls r2, r3, #1 + 80083a0: 687b ldr r3, [r7, #4] + 80083a2: 685b ldr r3, [r3, #4] + 80083a4: 085b lsrs r3, r3, #1 + 80083a6: 441a add r2, r3 + 80083a8: 687b ldr r3, [r7, #4] + 80083aa: 685b ldr r3, [r3, #4] + 80083ac: fbb2 f3f3 udiv r3, r2, r3 + 80083b0: b29b uxth r3, r3 + 80083b2: 61bb str r3, [r7, #24] + break; + 80083b4: e038 b.n 8008428 + case UART_CLOCKSOURCE_PCLK2: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); + 80083b6: f7fd fe55 bl 8006064 + 80083ba: 4603 mov r3, r0 + 80083bc: 005a lsls r2, r3, #1 + 80083be: 687b ldr r3, [r7, #4] + 80083c0: 685b ldr r3, [r3, #4] + 80083c2: 085b lsrs r3, r3, #1 + 80083c4: 441a add r2, r3 + 80083c6: 687b ldr r3, [r7, #4] + 80083c8: 685b ldr r3, [r3, #4] + 80083ca: fbb2 f3f3 udiv r3, r2, r3 + 80083ce: b29b uxth r3, r3 + 80083d0: 61bb str r3, [r7, #24] + break; + 80083d2: e029 b.n 8008428 + case UART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); + 80083d4: 687b ldr r3, [r7, #4] + 80083d6: 685b ldr r3, [r3, #4] + 80083d8: 085a lsrs r2, r3, #1 + 80083da: 4b5d ldr r3, [pc, #372] ; (8008550 ) + 80083dc: 4413 add r3, r2 + 80083de: 687a ldr r2, [r7, #4] + 80083e0: 6852 ldr r2, [r2, #4] + 80083e2: fbb3 f3f2 udiv r3, r3, r2 + 80083e6: b29b uxth r3, r3 + 80083e8: 61bb str r3, [r7, #24] + break; + 80083ea: e01d b.n 8008428 + case UART_CLOCKSOURCE_SYSCLK: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + 80083ec: f7fd fd68 bl 8005ec0 + 80083f0: 4603 mov r3, r0 + 80083f2: 005a lsls r2, r3, #1 + 80083f4: 687b ldr r3, [r7, #4] + 80083f6: 685b ldr r3, [r3, #4] + 80083f8: 085b lsrs r3, r3, #1 + 80083fa: 441a add r2, r3 + 80083fc: 687b ldr r3, [r7, #4] + 80083fe: 685b ldr r3, [r3, #4] + 8008400: fbb2 f3f3 udiv r3, r2, r3 + 8008404: b29b uxth r3, r3 + 8008406: 61bb str r3, [r7, #24] + break; + 8008408: e00e b.n 8008428 + case UART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); + 800840a: 687b ldr r3, [r7, #4] + 800840c: 685b ldr r3, [r3, #4] + 800840e: 085b lsrs r3, r3, #1 + 8008410: f503 3280 add.w r2, r3, #65536 ; 0x10000 + 8008414: 687b ldr r3, [r7, #4] + 8008416: 685b ldr r3, [r3, #4] + 8008418: fbb2 f3f3 udiv r3, r2, r3 + 800841c: b29b uxth r3, r3 + 800841e: 61bb str r3, [r7, #24] + break; + 8008420: e002 b.n 8008428 + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + 8008422: 2301 movs r3, #1 + 8008424: 75fb strb r3, [r7, #23] + break; + 8008426: bf00 nop + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 8008428: 69bb ldr r3, [r7, #24] + 800842a: 2b0f cmp r3, #15 + 800842c: d916 bls.n 800845c + 800842e: 69bb ldr r3, [r7, #24] + 8008430: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8008434: d212 bcs.n 800845c + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + 8008436: 69bb ldr r3, [r7, #24] + 8008438: b29b uxth r3, r3 + 800843a: f023 030f bic.w r3, r3, #15 + 800843e: 81fb strh r3, [r7, #14] + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + 8008440: 69bb ldr r3, [r7, #24] + 8008442: 085b lsrs r3, r3, #1 + 8008444: b29b uxth r3, r3 + 8008446: f003 0307 and.w r3, r3, #7 + 800844a: b29a uxth r2, r3 + 800844c: 89fb ldrh r3, [r7, #14] + 800844e: 4313 orrs r3, r2 + 8008450: 81fb strh r3, [r7, #14] + huart->Instance->BRR = brrtemp; + 8008452: 687b ldr r3, [r7, #4] + 8008454: 681b ldr r3, [r3, #0] + 8008456: 89fa ldrh r2, [r7, #14] + 8008458: 60da str r2, [r3, #12] + 800845a: e06e b.n 800853a + } + else + { + ret = HAL_ERROR; + 800845c: 2301 movs r3, #1 + 800845e: 75fb strb r3, [r7, #23] + 8008460: e06b b.n 800853a + } + } + else + { + switch (clocksource) + 8008462: 7ffb ldrb r3, [r7, #31] + 8008464: 2b08 cmp r3, #8 + 8008466: d857 bhi.n 8008518 + 8008468: a201 add r2, pc, #4 ; (adr r2, 8008470 ) + 800846a: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800846e: bf00 nop + 8008470: 08008495 .word 0x08008495 + 8008474: 080084b1 .word 0x080084b1 + 8008478: 080084cd .word 0x080084cd + 800847c: 08008519 .word 0x08008519 + 8008480: 080084e5 .word 0x080084e5 + 8008484: 08008519 .word 0x08008519 + 8008488: 08008519 .word 0x08008519 + 800848c: 08008519 .word 0x08008519 + 8008490: 08008501 .word 0x08008501 + { + case UART_CLOCKSOURCE_PCLK1: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + 8008494: f7fd fdd2 bl 800603c + 8008498: 4602 mov r2, r0 + 800849a: 687b ldr r3, [r7, #4] + 800849c: 685b ldr r3, [r3, #4] + 800849e: 085b lsrs r3, r3, #1 + 80084a0: 441a add r2, r3 + 80084a2: 687b ldr r3, [r7, #4] + 80084a4: 685b ldr r3, [r3, #4] + 80084a6: fbb2 f3f3 udiv r3, r2, r3 + 80084aa: b29b uxth r3, r3 + 80084ac: 61bb str r3, [r7, #24] + break; + 80084ae: e036 b.n 800851e + case UART_CLOCKSOURCE_PCLK2: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); + 80084b0: f7fd fdd8 bl 8006064 + 80084b4: 4602 mov r2, r0 + 80084b6: 687b ldr r3, [r7, #4] + 80084b8: 685b ldr r3, [r3, #4] + 80084ba: 085b lsrs r3, r3, #1 + 80084bc: 441a add r2, r3 + 80084be: 687b ldr r3, [r7, #4] + 80084c0: 685b ldr r3, [r3, #4] + 80084c2: fbb2 f3f3 udiv r3, r2, r3 + 80084c6: b29b uxth r3, r3 + 80084c8: 61bb str r3, [r7, #24] + break; + 80084ca: e028 b.n 800851e + case UART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); + 80084cc: 687b ldr r3, [r7, #4] + 80084ce: 685b ldr r3, [r3, #4] + 80084d0: 085a lsrs r2, r3, #1 + 80084d2: 4b20 ldr r3, [pc, #128] ; (8008554 ) + 80084d4: 4413 add r3, r2 + 80084d6: 687a ldr r2, [r7, #4] + 80084d8: 6852 ldr r2, [r2, #4] + 80084da: fbb3 f3f2 udiv r3, r3, r2 + 80084de: b29b uxth r3, r3 + 80084e0: 61bb str r3, [r7, #24] + break; + 80084e2: e01c b.n 800851e + case UART_CLOCKSOURCE_SYSCLK: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + 80084e4: f7fd fcec bl 8005ec0 + 80084e8: 4602 mov r2, r0 + 80084ea: 687b ldr r3, [r7, #4] + 80084ec: 685b ldr r3, [r3, #4] + 80084ee: 085b lsrs r3, r3, #1 + 80084f0: 441a add r2, r3 + 80084f2: 687b ldr r3, [r7, #4] + 80084f4: 685b ldr r3, [r3, #4] + 80084f6: fbb2 f3f3 udiv r3, r2, r3 + 80084fa: b29b uxth r3, r3 + 80084fc: 61bb str r3, [r7, #24] + break; + 80084fe: e00e b.n 800851e + case UART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); + 8008500: 687b ldr r3, [r7, #4] + 8008502: 685b ldr r3, [r3, #4] + 8008504: 085b lsrs r3, r3, #1 + 8008506: f503 4200 add.w r2, r3, #32768 ; 0x8000 + 800850a: 687b ldr r3, [r7, #4] + 800850c: 685b ldr r3, [r3, #4] + 800850e: fbb2 f3f3 udiv r3, r2, r3 + 8008512: b29b uxth r3, r3 + 8008514: 61bb str r3, [r7, #24] + break; + 8008516: e002 b.n 800851e + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + 8008518: 2301 movs r3, #1 + 800851a: 75fb strb r3, [r7, #23] + break; + 800851c: bf00 nop + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 800851e: 69bb ldr r3, [r7, #24] + 8008520: 2b0f cmp r3, #15 + 8008522: d908 bls.n 8008536 + 8008524: 69bb ldr r3, [r7, #24] + 8008526: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800852a: d204 bcs.n 8008536 + { + huart->Instance->BRR = usartdiv; + 800852c: 687b ldr r3, [r7, #4] + 800852e: 681b ldr r3, [r3, #0] + 8008530: 69ba ldr r2, [r7, #24] + 8008532: 60da str r2, [r3, #12] + 8008534: e001 b.n 800853a + } + else + { + ret = HAL_ERROR; + 8008536: 2301 movs r3, #1 + 8008538: 75fb strb r3, [r7, #23] + } + } + + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + 800853a: 687b ldr r3, [r7, #4] + 800853c: 2200 movs r2, #0 + 800853e: 661a str r2, [r3, #96] ; 0x60 + huart->TxISR = NULL; + 8008540: 687b ldr r3, [r7, #4] + 8008542: 2200 movs r2, #0 + 8008544: 665a str r2, [r3, #100] ; 0x64 + + return ret; + 8008546: 7dfb ldrb r3, [r7, #23] +} + 8008548: 4618 mov r0, r3 + 800854a: 3720 adds r7, #32 + 800854c: 46bd mov sp, r7 + 800854e: bd80 pop {r7, pc} + 8008550: 01e84800 .word 0x01e84800 + 8008554: 00f42400 .word 0x00f42400 + +08008558 : + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + 8008558: b480 push {r7} + 800855a: b083 sub sp, #12 + 800855c: af00 add r7, sp, #0 + 800855e: 6078 str r0, [r7, #4] + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + 8008560: 687b ldr r3, [r7, #4] + 8008562: 6a5b ldr r3, [r3, #36] ; 0x24 + 8008564: f003 0301 and.w r3, r3, #1 + 8008568: 2b00 cmp r3, #0 + 800856a: d00a beq.n 8008582 + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + 800856c: 687b ldr r3, [r7, #4] + 800856e: 681b ldr r3, [r3, #0] + 8008570: 685b ldr r3, [r3, #4] + 8008572: f423 3100 bic.w r1, r3, #131072 ; 0x20000 + 8008576: 687b ldr r3, [r7, #4] + 8008578: 6a9a ldr r2, [r3, #40] ; 0x28 + 800857a: 687b ldr r3, [r7, #4] + 800857c: 681b ldr r3, [r3, #0] + 800857e: 430a orrs r2, r1 + 8008580: 605a str r2, [r3, #4] + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + 8008582: 687b ldr r3, [r7, #4] + 8008584: 6a5b ldr r3, [r3, #36] ; 0x24 + 8008586: f003 0302 and.w r3, r3, #2 + 800858a: 2b00 cmp r3, #0 + 800858c: d00a beq.n 80085a4 + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + 800858e: 687b ldr r3, [r7, #4] + 8008590: 681b ldr r3, [r3, #0] + 8008592: 685b ldr r3, [r3, #4] + 8008594: f423 3180 bic.w r1, r3, #65536 ; 0x10000 + 8008598: 687b ldr r3, [r7, #4] + 800859a: 6ada ldr r2, [r3, #44] ; 0x2c + 800859c: 687b ldr r3, [r7, #4] + 800859e: 681b ldr r3, [r3, #0] + 80085a0: 430a orrs r2, r1 + 80085a2: 605a str r2, [r3, #4] + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + 80085a4: 687b ldr r3, [r7, #4] + 80085a6: 6a5b ldr r3, [r3, #36] ; 0x24 + 80085a8: f003 0304 and.w r3, r3, #4 + 80085ac: 2b00 cmp r3, #0 + 80085ae: d00a beq.n 80085c6 + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + 80085b0: 687b ldr r3, [r7, #4] + 80085b2: 681b ldr r3, [r3, #0] + 80085b4: 685b ldr r3, [r3, #4] + 80085b6: f423 2180 bic.w r1, r3, #262144 ; 0x40000 + 80085ba: 687b ldr r3, [r7, #4] + 80085bc: 6b1a ldr r2, [r3, #48] ; 0x30 + 80085be: 687b ldr r3, [r7, #4] + 80085c0: 681b ldr r3, [r3, #0] + 80085c2: 430a orrs r2, r1 + 80085c4: 605a str r2, [r3, #4] + } + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + 80085c6: 687b ldr r3, [r7, #4] + 80085c8: 6a5b ldr r3, [r3, #36] ; 0x24 + 80085ca: f003 0308 and.w r3, r3, #8 + 80085ce: 2b00 cmp r3, #0 + 80085d0: d00a beq.n 80085e8 + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + 80085d2: 687b ldr r3, [r7, #4] + 80085d4: 681b ldr r3, [r3, #0] + 80085d6: 685b ldr r3, [r3, #4] + 80085d8: f423 4100 bic.w r1, r3, #32768 ; 0x8000 + 80085dc: 687b ldr r3, [r7, #4] + 80085de: 6b5a ldr r2, [r3, #52] ; 0x34 + 80085e0: 687b ldr r3, [r7, #4] + 80085e2: 681b ldr r3, [r3, #0] + 80085e4: 430a orrs r2, r1 + 80085e6: 605a str r2, [r3, #4] + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + 80085e8: 687b ldr r3, [r7, #4] + 80085ea: 6a5b ldr r3, [r3, #36] ; 0x24 + 80085ec: f003 0310 and.w r3, r3, #16 + 80085f0: 2b00 cmp r3, #0 + 80085f2: d00a beq.n 800860a + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + 80085f4: 687b ldr r3, [r7, #4] + 80085f6: 681b ldr r3, [r3, #0] + 80085f8: 689b ldr r3, [r3, #8] + 80085fa: f423 5180 bic.w r1, r3, #4096 ; 0x1000 + 80085fe: 687b ldr r3, [r7, #4] + 8008600: 6b9a ldr r2, [r3, #56] ; 0x38 + 8008602: 687b ldr r3, [r7, #4] + 8008604: 681b ldr r3, [r3, #0] + 8008606: 430a orrs r2, r1 + 8008608: 609a str r2, [r3, #8] + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + 800860a: 687b ldr r3, [r7, #4] + 800860c: 6a5b ldr r3, [r3, #36] ; 0x24 + 800860e: f003 0320 and.w r3, r3, #32 + 8008612: 2b00 cmp r3, #0 + 8008614: d00a beq.n 800862c + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + 8008616: 687b ldr r3, [r7, #4] + 8008618: 681b ldr r3, [r3, #0] + 800861a: 689b ldr r3, [r3, #8] + 800861c: f423 5100 bic.w r1, r3, #8192 ; 0x2000 + 8008620: 687b ldr r3, [r7, #4] + 8008622: 6bda ldr r2, [r3, #60] ; 0x3c + 8008624: 687b ldr r3, [r7, #4] + 8008626: 681b ldr r3, [r3, #0] + 8008628: 430a orrs r2, r1 + 800862a: 609a str r2, [r3, #8] + } + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + 800862c: 687b ldr r3, [r7, #4] + 800862e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8008630: f003 0340 and.w r3, r3, #64 ; 0x40 + 8008634: 2b00 cmp r3, #0 + 8008636: d01a beq.n 800866e + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + 8008638: 687b ldr r3, [r7, #4] + 800863a: 681b ldr r3, [r3, #0] + 800863c: 685b ldr r3, [r3, #4] + 800863e: f423 1180 bic.w r1, r3, #1048576 ; 0x100000 + 8008642: 687b ldr r3, [r7, #4] + 8008644: 6c1a ldr r2, [r3, #64] ; 0x40 + 8008646: 687b ldr r3, [r7, #4] + 8008648: 681b ldr r3, [r3, #0] + 800864a: 430a orrs r2, r1 + 800864c: 605a str r2, [r3, #4] + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + 800864e: 687b ldr r3, [r7, #4] + 8008650: 6c1b ldr r3, [r3, #64] ; 0x40 + 8008652: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 8008656: d10a bne.n 800866e + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + 8008658: 687b ldr r3, [r7, #4] + 800865a: 681b ldr r3, [r3, #0] + 800865c: 685b ldr r3, [r3, #4] + 800865e: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000 + 8008662: 687b ldr r3, [r7, #4] + 8008664: 6c5a ldr r2, [r3, #68] ; 0x44 + 8008666: 687b ldr r3, [r7, #4] + 8008668: 681b ldr r3, [r3, #0] + 800866a: 430a orrs r2, r1 + 800866c: 605a str r2, [r3, #4] + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + 800866e: 687b ldr r3, [r7, #4] + 8008670: 6a5b ldr r3, [r3, #36] ; 0x24 + 8008672: f003 0380 and.w r3, r3, #128 ; 0x80 + 8008676: 2b00 cmp r3, #0 + 8008678: d00a beq.n 8008690 + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + 800867a: 687b ldr r3, [r7, #4] + 800867c: 681b ldr r3, [r3, #0] + 800867e: 685b ldr r3, [r3, #4] + 8008680: f423 2100 bic.w r1, r3, #524288 ; 0x80000 + 8008684: 687b ldr r3, [r7, #4] + 8008686: 6c9a ldr r2, [r3, #72] ; 0x48 + 8008688: 687b ldr r3, [r7, #4] + 800868a: 681b ldr r3, [r3, #0] + 800868c: 430a orrs r2, r1 + 800868e: 605a str r2, [r3, #4] + } +} + 8008690: bf00 nop + 8008692: 370c adds r7, #12 + 8008694: 46bd mov sp, r7 + 8008696: f85d 7b04 ldr.w r7, [sp], #4 + 800869a: 4770 bx lr + +0800869c : + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + 800869c: b580 push {r7, lr} + 800869e: b086 sub sp, #24 + 80086a0: af02 add r7, sp, #8 + 80086a2: 6078 str r0, [r7, #4] + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 80086a4: 687b ldr r3, [r7, #4] + 80086a6: 2200 movs r2, #0 + 80086a8: 67da str r2, [r3, #124] ; 0x7c + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + 80086aa: f7fc fd93 bl 80051d4 + 80086ae: 60f8 str r0, [r7, #12] + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + 80086b0: 687b ldr r3, [r7, #4] + 80086b2: 681b ldr r3, [r3, #0] + 80086b4: 681b ldr r3, [r3, #0] + 80086b6: f003 0308 and.w r3, r3, #8 + 80086ba: 2b08 cmp r3, #8 + 80086bc: d10e bne.n 80086dc + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + 80086be: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 + 80086c2: 9300 str r3, [sp, #0] + 80086c4: 68fb ldr r3, [r7, #12] + 80086c6: 2200 movs r2, #0 + 80086c8: f44f 1100 mov.w r1, #2097152 ; 0x200000 + 80086cc: 6878 ldr r0, [r7, #4] + 80086ce: f000 f814 bl 80086fa + 80086d2: 4603 mov r3, r0 + 80086d4: 2b00 cmp r3, #0 + 80086d6: d001 beq.n 80086dc + { + /* Timeout occurred */ + return HAL_TIMEOUT; + 80086d8: 2303 movs r3, #3 + 80086da: e00a b.n 80086f2 + } + } + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + 80086dc: 687b ldr r3, [r7, #4] + 80086de: 2220 movs r2, #32 + 80086e0: 675a str r2, [r3, #116] ; 0x74 + huart->RxState = HAL_UART_STATE_READY; + 80086e2: 687b ldr r3, [r7, #4] + 80086e4: 2220 movs r2, #32 + 80086e6: 679a str r2, [r3, #120] ; 0x78 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 80086e8: 687b ldr r3, [r7, #4] + 80086ea: 2200 movs r2, #0 + 80086ec: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + return HAL_OK; + 80086f0: 2300 movs r3, #0 +} + 80086f2: 4618 mov r0, r3 + 80086f4: 3710 adds r7, #16 + 80086f6: 46bd mov sp, r7 + 80086f8: bd80 pop {r7, pc} + +080086fa : + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +{ + 80086fa: b580 push {r7, lr} + 80086fc: b084 sub sp, #16 + 80086fe: af00 add r7, sp, #0 + 8008700: 60f8 str r0, [r7, #12] + 8008702: 60b9 str r1, [r7, #8] + 8008704: 603b str r3, [r7, #0] + 8008706: 4613 mov r3, r2 + 8008708: 71fb strb r3, [r7, #7] + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 800870a: e02a b.n 8008762 + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 800870c: 69bb ldr r3, [r7, #24] + 800870e: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8008712: d026 beq.n 8008762 + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 8008714: f7fc fd5e bl 80051d4 + 8008718: 4602 mov r2, r0 + 800871a: 683b ldr r3, [r7, #0] + 800871c: 1ad3 subs r3, r2, r3 + 800871e: 69ba ldr r2, [r7, #24] + 8008720: 429a cmp r2, r3 + 8008722: d302 bcc.n 800872a + 8008724: 69bb ldr r3, [r7, #24] + 8008726: 2b00 cmp r3, #0 + 8008728: d11b bne.n 8008762 + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + 800872a: 68fb ldr r3, [r7, #12] + 800872c: 681b ldr r3, [r3, #0] + 800872e: 681a ldr r2, [r3, #0] + 8008730: 68fb ldr r3, [r7, #12] + 8008732: 681b ldr r3, [r3, #0] + 8008734: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 + 8008738: 601a str r2, [r3, #0] + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 800873a: 68fb ldr r3, [r7, #12] + 800873c: 681b ldr r3, [r3, #0] + 800873e: 689a ldr r2, [r3, #8] + 8008740: 68fb ldr r3, [r7, #12] + 8008742: 681b ldr r3, [r3, #0] + 8008744: f022 0201 bic.w r2, r2, #1 + 8008748: 609a str r2, [r3, #8] + + huart->gState = HAL_UART_STATE_READY; + 800874a: 68fb ldr r3, [r7, #12] + 800874c: 2220 movs r2, #32 + 800874e: 675a str r2, [r3, #116] ; 0x74 + huart->RxState = HAL_UART_STATE_READY; + 8008750: 68fb ldr r3, [r7, #12] + 8008752: 2220 movs r2, #32 + 8008754: 679a str r2, [r3, #120] ; 0x78 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8008756: 68fb ldr r3, [r7, #12] + 8008758: 2200 movs r2, #0 + 800875a: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + return HAL_TIMEOUT; + 800875e: 2303 movs r3, #3 + 8008760: e00f b.n 8008782 + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 8008762: 68fb ldr r3, [r7, #12] + 8008764: 681b ldr r3, [r3, #0] + 8008766: 69da ldr r2, [r3, #28] + 8008768: 68bb ldr r3, [r7, #8] + 800876a: 4013 ands r3, r2 + 800876c: 68ba ldr r2, [r7, #8] + 800876e: 429a cmp r2, r3 + 8008770: bf0c ite eq + 8008772: 2301 moveq r3, #1 + 8008774: 2300 movne r3, #0 + 8008776: b2db uxtb r3, r3 + 8008778: 461a mov r2, r3 + 800877a: 79fb ldrb r3, [r7, #7] + 800877c: 429a cmp r2, r3 + 800877e: d0c5 beq.n 800870c + } + } + } + return HAL_OK; + 8008780: 2300 movs r3, #0 +} + 8008782: 4618 mov r0, r3 + 8008784: 3710 adds r7, #16 + 8008786: 46bd mov sp, r7 + 8008788: bd80 pop {r7, pc} + +0800878a : + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + 800878a: b480 push {r7} + 800878c: b083 sub sp, #12 + 800878e: af00 add r7, sp, #0 + 8008790: 6078 str r0, [r7, #4] + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + 8008792: 687b ldr r3, [r7, #4] + 8008794: 681b ldr r3, [r3, #0] + 8008796: 681a ldr r2, [r3, #0] + 8008798: 687b ldr r3, [r7, #4] + 800879a: 681b ldr r3, [r3, #0] + 800879c: f422 7290 bic.w r2, r2, #288 ; 0x120 + 80087a0: 601a str r2, [r3, #0] + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 80087a2: 687b ldr r3, [r7, #4] + 80087a4: 681b ldr r3, [r3, #0] + 80087a6: 689a ldr r2, [r3, #8] + 80087a8: 687b ldr r3, [r7, #4] + 80087aa: 681b ldr r3, [r3, #0] + 80087ac: f022 0201 bic.w r2, r2, #1 + 80087b0: 609a str r2, [r3, #8] + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 80087b2: 687b ldr r3, [r7, #4] + 80087b4: 2220 movs r2, #32 + 80087b6: 679a str r2, [r3, #120] ; 0x78 + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; + 80087b8: 687b ldr r3, [r7, #4] + 80087ba: 2200 movs r2, #0 + 80087bc: 661a str r2, [r3, #96] ; 0x60 +} + 80087be: bf00 nop + 80087c0: 370c adds r7, #12 + 80087c2: 46bd mov sp, r7 + 80087c4: f85d 7b04 ldr.w r7, [sp], #4 + 80087c8: 4770 bx lr + +080087ca : + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + 80087ca: b580 push {r7, lr} + 80087cc: b084 sub sp, #16 + 80087ce: af00 add r7, sp, #0 + 80087d0: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 80087d2: 687b ldr r3, [r7, #4] + 80087d4: 6b9b ldr r3, [r3, #56] ; 0x38 + 80087d6: 60fb str r3, [r7, #12] + huart->RxXferCount = 0U; + 80087d8: 68fb ldr r3, [r7, #12] + 80087da: 2200 movs r2, #0 + 80087dc: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + huart->TxXferCount = 0U; + 80087e0: 68fb ldr r3, [r7, #12] + 80087e2: 2200 movs r2, #0 + 80087e4: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 80087e8: 68f8 ldr r0, [r7, #12] + 80087ea: f7ff fc07 bl 8007ffc +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 80087ee: bf00 nop + 80087f0: 3710 adds r7, #16 + 80087f2: 46bd mov sp, r7 + 80087f4: bd80 pop {r7, pc} + +080087f6 : + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + 80087f6: b580 push {r7, lr} + 80087f8: b082 sub sp, #8 + 80087fa: af00 add r7, sp, #0 + 80087fc: 6078 str r0, [r7, #4] + /* Disable the UART Transmit Complete Interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + 80087fe: 687b ldr r3, [r7, #4] + 8008800: 681b ldr r3, [r3, #0] + 8008802: 681a ldr r2, [r3, #0] + 8008804: 687b ldr r3, [r7, #4] + 8008806: 681b ldr r3, [r3, #0] + 8008808: f022 0240 bic.w r2, r2, #64 ; 0x40 + 800880c: 601a str r2, [r3, #0] + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 800880e: 687b ldr r3, [r7, #4] + 8008810: 2220 movs r2, #32 + 8008812: 675a str r2, [r3, #116] ; 0x74 + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + 8008814: 687b ldr r3, [r7, #4] + 8008816: 2200 movs r2, #0 + 8008818: 665a str r2, [r3, #100] ; 0x64 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); + 800881a: 6878 ldr r0, [r7, #4] + 800881c: f7ff fbe4 bl 8007fe8 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 8008820: bf00 nop + 8008822: 3708 adds r7, #8 + 8008824: 46bd mov sp, r7 + 8008826: bd80 pop {r7, pc} + +08008828 : + * @brief RX interrrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + 8008828: b580 push {r7, lr} + 800882a: b084 sub sp, #16 + 800882c: af00 add r7, sp, #0 + 800882e: 6078 str r0, [r7, #4] + uint16_t uhMask = huart->Mask; + 8008830: 687b ldr r3, [r7, #4] + 8008832: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c + 8008836: 81fb strh r3, [r7, #14] + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 8008838: 687b ldr r3, [r7, #4] + 800883a: 6f9b ldr r3, [r3, #120] ; 0x78 + 800883c: 2b22 cmp r3, #34 ; 0x22 + 800883e: d13a bne.n 80088b6 + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 8008840: 687b ldr r3, [r7, #4] + 8008842: 681b ldr r3, [r3, #0] + 8008844: 6a5b ldr r3, [r3, #36] ; 0x24 + 8008846: 81bb strh r3, [r7, #12] + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + 8008848: 89bb ldrh r3, [r7, #12] + 800884a: b2d9 uxtb r1, r3 + 800884c: 89fb ldrh r3, [r7, #14] + 800884e: b2da uxtb r2, r3 + 8008850: 687b ldr r3, [r7, #4] + 8008852: 6d5b ldr r3, [r3, #84] ; 0x54 + 8008854: 400a ands r2, r1 + 8008856: b2d2 uxtb r2, r2 + 8008858: 701a strb r2, [r3, #0] + huart->pRxBuffPtr++; + 800885a: 687b ldr r3, [r7, #4] + 800885c: 6d5b ldr r3, [r3, #84] ; 0x54 + 800885e: 1c5a adds r2, r3, #1 + 8008860: 687b ldr r3, [r7, #4] + 8008862: 655a str r2, [r3, #84] ; 0x54 + huart->RxXferCount--; + 8008864: 687b ldr r3, [r7, #4] + 8008866: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 800886a: b29b uxth r3, r3 + 800886c: 3b01 subs r3, #1 + 800886e: b29a uxth r2, r3 + 8008870: 687b ldr r3, [r7, #4] + 8008872: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + + if (huart->RxXferCount == 0U) + 8008876: 687b ldr r3, [r7, #4] + 8008878: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 800887c: b29b uxth r3, r3 + 800887e: 2b00 cmp r3, #0 + 8008880: d121 bne.n 80088c6 + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + 8008882: 687b ldr r3, [r7, #4] + 8008884: 681b ldr r3, [r3, #0] + 8008886: 681a ldr r2, [r3, #0] + 8008888: 687b ldr r3, [r7, #4] + 800888a: 681b ldr r3, [r3, #0] + 800888c: f422 7290 bic.w r2, r2, #288 ; 0x120 + 8008890: 601a str r2, [r3, #0] + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8008892: 687b ldr r3, [r7, #4] + 8008894: 681b ldr r3, [r3, #0] + 8008896: 689a ldr r2, [r3, #8] + 8008898: 687b ldr r3, [r7, #4] + 800889a: 681b ldr r3, [r3, #0] + 800889c: f022 0201 bic.w r2, r2, #1 + 80088a0: 609a str r2, [r3, #8] + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 80088a2: 687b ldr r3, [r7, #4] + 80088a4: 2220 movs r2, #32 + 80088a6: 679a str r2, [r3, #120] ; 0x78 + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 80088a8: 687b ldr r3, [r7, #4] + 80088aa: 2200 movs r2, #0 + 80088ac: 661a str r2, [r3, #96] ; 0x60 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); + 80088ae: 6878 ldr r0, [r7, #4] + 80088b0: f7f8 ff00 bl 80016b4 + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + 80088b4: e007 b.n 80088c6 + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 80088b6: 687b ldr r3, [r7, #4] + 80088b8: 681b ldr r3, [r3, #0] + 80088ba: 699a ldr r2, [r3, #24] + 80088bc: 687b ldr r3, [r7, #4] + 80088be: 681b ldr r3, [r3, #0] + 80088c0: f042 0208 orr.w r2, r2, #8 + 80088c4: 619a str r2, [r3, #24] +} + 80088c6: bf00 nop + 80088c8: 3710 adds r7, #16 + 80088ca: 46bd mov sp, r7 + 80088cc: bd80 pop {r7, pc} + +080088ce : + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + 80088ce: b580 push {r7, lr} + 80088d0: b084 sub sp, #16 + 80088d2: af00 add r7, sp, #0 + 80088d4: 6078 str r0, [r7, #4] + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + 80088d6: 687b ldr r3, [r7, #4] + 80088d8: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c + 80088dc: 81fb strh r3, [r7, #14] + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 80088de: 687b ldr r3, [r7, #4] + 80088e0: 6f9b ldr r3, [r3, #120] ; 0x78 + 80088e2: 2b22 cmp r3, #34 ; 0x22 + 80088e4: d13a bne.n 800895c + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 80088e6: 687b ldr r3, [r7, #4] + 80088e8: 681b ldr r3, [r3, #0] + 80088ea: 6a5b ldr r3, [r3, #36] ; 0x24 + 80088ec: 81bb strh r3, [r7, #12] + tmp = (uint16_t *) huart->pRxBuffPtr ; + 80088ee: 687b ldr r3, [r7, #4] + 80088f0: 6d5b ldr r3, [r3, #84] ; 0x54 + 80088f2: 60bb str r3, [r7, #8] + *tmp = (uint16_t)(uhdata & uhMask); + 80088f4: 89ba ldrh r2, [r7, #12] + 80088f6: 89fb ldrh r3, [r7, #14] + 80088f8: 4013 ands r3, r2 + 80088fa: b29a uxth r2, r3 + 80088fc: 68bb ldr r3, [r7, #8] + 80088fe: 801a strh r2, [r3, #0] + huart->pRxBuffPtr += 2U; + 8008900: 687b ldr r3, [r7, #4] + 8008902: 6d5b ldr r3, [r3, #84] ; 0x54 + 8008904: 1c9a adds r2, r3, #2 + 8008906: 687b ldr r3, [r7, #4] + 8008908: 655a str r2, [r3, #84] ; 0x54 + huart->RxXferCount--; + 800890a: 687b ldr r3, [r7, #4] + 800890c: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 8008910: b29b uxth r3, r3 + 8008912: 3b01 subs r3, #1 + 8008914: b29a uxth r2, r3 + 8008916: 687b ldr r3, [r7, #4] + 8008918: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + + if (huart->RxXferCount == 0U) + 800891c: 687b ldr r3, [r7, #4] + 800891e: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 8008922: b29b uxth r3, r3 + 8008924: 2b00 cmp r3, #0 + 8008926: d121 bne.n 800896c + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + 8008928: 687b ldr r3, [r7, #4] + 800892a: 681b ldr r3, [r3, #0] + 800892c: 681a ldr r2, [r3, #0] + 800892e: 687b ldr r3, [r7, #4] + 8008930: 681b ldr r3, [r3, #0] + 8008932: f422 7290 bic.w r2, r2, #288 ; 0x120 + 8008936: 601a str r2, [r3, #0] + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8008938: 687b ldr r3, [r7, #4] + 800893a: 681b ldr r3, [r3, #0] + 800893c: 689a ldr r2, [r3, #8] + 800893e: 687b ldr r3, [r7, #4] + 8008940: 681b ldr r3, [r3, #0] + 8008942: f022 0201 bic.w r2, r2, #1 + 8008946: 609a str r2, [r3, #8] + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8008948: 687b ldr r3, [r7, #4] + 800894a: 2220 movs r2, #32 + 800894c: 679a str r2, [r3, #120] ; 0x78 + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 800894e: 687b ldr r3, [r7, #4] + 8008950: 2200 movs r2, #0 + 8008952: 661a str r2, [r3, #96] ; 0x60 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); + 8008954: 6878 ldr r0, [r7, #4] + 8008956: f7f8 fead bl 80016b4 + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + 800895a: e007 b.n 800896c + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 800895c: 687b ldr r3, [r7, #4] + 800895e: 681b ldr r3, [r3, #0] + 8008960: 699a ldr r2, [r3, #24] + 8008962: 687b ldr r3, [r7, #4] + 8008964: 681b ldr r3, [r3, #0] + 8008966: f042 0208 orr.w r2, r2, #8 + 800896a: 619a str r2, [r3, #24] +} + 800896c: bf00 nop + 800896e: 3710 adds r7, #16 + 8008970: 46bd mov sp, r7 + 8008972: bd80 pop {r7, pc} + +08008974 <__libc_init_array>: + 8008974: b570 push {r4, r5, r6, lr} + 8008976: 4e0d ldr r6, [pc, #52] ; (80089ac <__libc_init_array+0x38>) + 8008978: 4c0d ldr r4, [pc, #52] ; (80089b0 <__libc_init_array+0x3c>) + 800897a: 1ba4 subs r4, r4, r6 + 800897c: 10a4 asrs r4, r4, #2 + 800897e: 2500 movs r5, #0 + 8008980: 42a5 cmp r5, r4 + 8008982: d109 bne.n 8008998 <__libc_init_array+0x24> + 8008984: 4e0b ldr r6, [pc, #44] ; (80089b4 <__libc_init_array+0x40>) + 8008986: 4c0c ldr r4, [pc, #48] ; (80089b8 <__libc_init_array+0x44>) + 8008988: f000 f820 bl 80089cc <_init> + 800898c: 1ba4 subs r4, r4, r6 + 800898e: 10a4 asrs r4, r4, #2 + 8008990: 2500 movs r5, #0 + 8008992: 42a5 cmp r5, r4 + 8008994: d105 bne.n 80089a2 <__libc_init_array+0x2e> + 8008996: bd70 pop {r4, r5, r6, pc} + 8008998: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 800899c: 4798 blx r3 + 800899e: 3501 adds r5, #1 + 80089a0: e7ee b.n 8008980 <__libc_init_array+0xc> + 80089a2: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 80089a6: 4798 blx r3 + 80089a8: 3501 adds r5, #1 + 80089aa: e7f2 b.n 8008992 <__libc_init_array+0x1e> + 80089ac: 08008cec .word 0x08008cec + 80089b0: 08008cec .word 0x08008cec + 80089b4: 08008cec .word 0x08008cec + 80089b8: 08008cf4 .word 0x08008cf4 + +080089bc : + 80089bc: 4402 add r2, r0 + 80089be: 4603 mov r3, r0 + 80089c0: 4293 cmp r3, r2 + 80089c2: d100 bne.n 80089c6 + 80089c4: 4770 bx lr + 80089c6: f803 1b01 strb.w r1, [r3], #1 + 80089ca: e7f9 b.n 80089c0 + +080089cc <_init>: + 80089cc: b5f8 push {r3, r4, r5, r6, r7, lr} + 80089ce: bf00 nop + 80089d0: bcf8 pop {r3, r4, r5, r6, r7} + 80089d2: bc08 pop {r3} + 80089d4: 469e mov lr, r3 + 80089d6: 4770 bx lr + +080089d8 <_fini>: + 80089d8: b5f8 push {r3, r4, r5, r6, r7, lr} + 80089da: bf00 nop + 80089dc: bcf8 pop {r3, r4, r5, r6, r7} + 80089de: bc08 pop {r3} + 80089e0: 469e mov lr, r3 + 80089e2: 4770 bx lr diff --git a/utils/proto_test/otto_proto_test/Debug/sources.mk b/utils/proto_test/otto_proto_test/Debug/sources.mk new file mode 100644 index 0000000..ab6831f --- /dev/null +++ b/utils/proto_test/otto_proto_test/Debug/sources.mk @@ -0,0 +1,32 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +ELF_SRCS := +C_UPPER_SRCS := +CXX_SRCS := +C++_SRCS := +OBJ_SRCS := +S_SRCS := +CC_SRCS := +C_SRCS := +CPP_SRCS := +S_UPPER_SRCS := +O_SRCS := +CC_DEPS := +SIZE_OUTPUT := +OBJDUMP_LIST := +C++_DEPS := +EXECUTABLES := +OBJS := +C_UPPER_DEPS := +CXX_DEPS := +C_DEPS := +CPP_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Drivers/STM32F7xx_HAL_Driver/Src \ + diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h new file mode 100644 index 0000000..7b979c3 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h @@ -0,0 +1,18631 @@ +/** + ****************************************************************************** + * @file stm32f767xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheralÂ’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f767xx + * @{ + */ + +#ifndef __STM32F767xx_H +#define __STM32F767xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief STM32F7xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + DFSDM1_FLT0_IRQn = 99, /*!< DFSDM1 Filter 0 global Interrupt */ + DFSDM1_FLT1_IRQn = 100, /*!< DFSDM1 Filter 1 global Interrupt */ + DFSDM1_FLT2_IRQn = 101, /*!< DFSDM1 Filter 2 global Interrupt */ + DFSDM1_FLT3_IRQn = 102, /*!< DFSDM1 Filter 3 global Interrupt */ + SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */ + CAN3_TX_IRQn = 104, /*!< CAN3 TX Interrupt */ + CAN3_RX0_IRQn = 105, /*!< CAN3 RX0 Interrupt */ + CAN3_RX1_IRQn = 106, /*!< CAN3 RX1 Interrupt */ + CAN3_SCE_IRQn = 107, /*!< CAN3 SCE Interrupt */ + JPEG_IRQn = 108, /*!< JPEG global Interrupt */ + MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +/** + * @brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ +#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ +#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ + + +#include "system_stm32f7xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief HDMI-CEC + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1; + __IO uint32_t MACDBGR; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */ +} FLASH_TypeDef; + + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5_6 + */ + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED; /*!< Reserved, 0x18 */ + __IO uint32_t CBR; /*!< SYSCFG Class B register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ +} PWR_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ + __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */ + __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */ + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t reserved; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ +} SPDIFRX_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */ + +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ +} LPTIM_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ +} USART_TypeDef; + + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + uint32_t Reserved7; /*!< Reserved 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + uint32_t Reserved43[40]; /*!< Reserved 60h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encoder, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encoder, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */ + __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */ + __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */ + __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */ + __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */ + __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */ + __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */ + uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */ + __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */ + __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */ + __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */ + __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */ + __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */ + __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */ + __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */ + __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */ + __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */ + __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */ + __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */ + __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */ + __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */ + __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */ + __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */ + __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */ + __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */ + __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */ + __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */ + __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */ + __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */ + __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */ + __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */ + __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */ + __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */ + __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */ + __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */ + __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */ + __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */ + __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */ + __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */ + __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */ + __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */ + __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */ + __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */ + __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */ + __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */ + __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */ + __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */ + __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */ + __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */ + __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */ + __IO uint32_t DOUTR10; /*!< MDIOS Output Data Register (MDIOS_DOUTR10), Address offset: 1A8h */ + __IO uint32_t DOUTR11; /*!< MDIOS Output Data Register (MDIOS_DOUTR11), Address offset: 1ACh */ + __IO uint32_t DOUTR12; /*!< MDIOS Output Data Register (MDIOS_DOUTR12), Address offset: 1B0h */ + __IO uint32_t DOUTR13; /*!< MDIOS Output Data Register (MDIOS_DOUTR13), Address offset: 1B4h */ + __IO uint32_t DOUTR14; /*!< MDIOS Output Data Register (MDIOS_DOUTR14), Address offset: 1B8h */ + __IO uint32_t DOUTR15; /*!< MDIOS Output Data Register (MDIOS_DOUTR15), Address offset: 1BCh */ + __IO uint32_t DOUTR16; /*!< MDIOS Output Data Register (MDIOS_DOUTR16), Address offset: 1C0h */ + __IO uint32_t DOUTR17; /*!< MDIOS Output Data Register (MDIOS_DOUTR17), Address offset: 1C4h */ + __IO uint32_t DOUTR18; /*!< MDIOS Output Data Register (MDIOS_DOUTR18), Address offset: 1C8h */ + __IO uint32_t DOUTR19; /*!< MDIOS Output Data Register (MDIOS_DOUTR19), Address offset: 1CCh */ + __IO uint32_t DOUTR20; /*!< MDIOS Output Data Register (MDIOS_DOUTR20), Address offset: 1D0h */ + __IO uint32_t DOUTR21; /*!< MDIOS Output Data Register (MDIOS_DOUTR21), Address offset: 1D4h */ + __IO uint32_t DOUTR22; /*!< MDIOS Output Data Register (MDIOS_DOUTR22), Address offset: 1D8h */ + __IO uint32_t DOUTR23; /*!< MDIOS Output Data Register (MDIOS_DOUTR23), Address offset: 1DCh */ + __IO uint32_t DOUTR24; /*!< MDIOS Output Data Register (MDIOS_DOUTR24), Address offset: 1E0h */ + __IO uint32_t DOUTR25; /*!< MDIOS Output Data Register (MDIOS_DOUTR25), Address offset: 1E4h */ + __IO uint32_t DOUTR26; /*!< MDIOS Output Data Register (MDIOS_DOUTR26), Address offset: 1E8h */ + __IO uint32_t DOUTR27; /*!< MDIOS Output Data Register (MDIOS_DOUTR27), Address offset: 1ECh */ + __IO uint32_t DOUTR28; /*!< MDIOS Output Data Register (MDIOS_DOUTR28), Address offset: 1F0h */ + __IO uint32_t DOUTR29; /*!< MDIOS Output Data Register (MDIOS_DOUTR29), Address offset: 1F4h */ + __IO uint32_t DOUTR30; /*!< MDIOS Output Data Register (MDIOS_DOUTR30), Address offset: 1F8h */ + __IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */ +} MDIOS_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define RAMITCM_BASE 0x00000000UL /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define FLASHITCM_BASE 0x00200000UL /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */ +#define FLASHAXI_BASE 0x08000000UL /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */ +#define RAMDTCM_BASE 0x20000000UL /*!< Base address of : 128KB system data RAM accessible over DTCM */ +#define PERIPH_BASE 0x40000000UL /*!< Base address of : AHB/ABP Peripherals */ +#define BKPSRAM_BASE 0x40024000UL /*!< Base address of : Backup SRAM(4 KB) */ +#define QSPI_BASE 0x90000000UL /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_R_BASE 0xA0000000UL /*!< Base address of : FMC Control registers */ +#define QSPI_R_BASE 0xA0001000UL /*!< Base address of : QSPI Control registers */ +#define SRAM1_BASE 0x20020000UL /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */ +#define SRAM2_BASE 0x2007C000UL /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */ +#define FLASH_END 0x081FFFFFUL /*!< FLASH end address */ +#define FLASH_OTP_BASE 0x1FF0F000UL /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */ +#define FLASH_OTP_END 0x1FF0F41FUL /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */ + +/* Legacy define */ +#define FLASH_BASE FLASHAXI_BASE + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define CAN3_BASE (APB1PERIPH_BASE + 0x3400UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define I2C4_BASE (APB1PERIPH_BASE + 0x6000UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL) +#define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL) +#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00UL) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300UL) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL) +#define SPI6_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL) +#define LTDC_BASE (APB2PERIPH_BASE + 0x6800UL) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x0084UL) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x0104UL) +#define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL) +#define MDIOS_BASE (APB2PERIPH_BASE + 0x7800UL) +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400UL) +#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL) +#define UID_BASE 0x1FF0F420UL /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE 0x1FF0F442UL /*!< FLASH Size register base address */ +#define PACKAGE_BASE 0x1FF0F7E0UL /*!< Package size register base address */ +/* Legacy define */ +#define PACKAGESIZE_BASE PACKAGE_BASE + +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100UL) +#define ETH_PTP_BASE (ETH_BASE + 0x0700UL) +#define ETH_DMA_BASE (ETH_BASE + 0x1000UL) +#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL) +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL) +#define JPEG_BASE (AHB2PERIPH_BASE + 0x51000UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL) +/*!< FMC Bankx registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE 0xE0042000UL + +/*!< USB registers base address */ +#define USB_OTG_HS_PERIPH_BASE 0x40040000UL +#define USB_OTG_FS_PERIPH_BASE 0x50000000UL + +#define USB_OTG_GLOBAL_BASE 0x0000UL +#define USB_OTG_DEVICE_BASE 0x0800UL +#define USB_OTG_IN_ENDPOINT_BASE 0x0900UL +#define USB_OTG_OUT_ENDPOINT_BASE 0x0B00UL +#define USB_OTG_EP_REG_SIZE 0x0020UL +#define USB_OTG_HOST_BASE 0x0400UL +#define USB_OTG_HOST_PORT_BASE 0x0440UL +#define USB_OTG_HOST_CHANNEL_BASE 0x0500UL +#define USB_OTG_HOST_CHANNEL_SIZE 0x0020UL +#define USB_OTG_PCGCCTL_BASE 0x0E00UL +#define USB_OTG_FIFO_BASE 0x1000UL +#define USB_OTG_FIFO_SIZE 0x1000UL + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) +#define CAN3 ((CAN_TypeDef *) CAN3_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) +#define JPEG ((JPEG_TypeDef *) JPEG_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD_Pos (0U) +#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ +#define ADC_SR_AWD ADC_SR_AWD_Msk /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx + * @{ + */ + +#ifndef __STM32F7xx_H +#define __STM32F7xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F7) +#define STM32F7 +#endif /* STM32F7 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ +#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \ + !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \ + !defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx) && !defined (STM32F730xx) && \ + !defined (STM32F750xx) + + /* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG, + STM32F756NG Devices */ + /* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG, + STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */ + /* #define STM32F745xx */ /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */ + /* #define STM32F765xx */ /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG, + STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */ + /* #define STM32F767xx */ /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI, + STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI Devices */ + /* #define STM32F769xx */ /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II, + STM32F769NG, STM32F769NI, STM32F768AI Devices */ + /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI Devices */ + /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI Devices */ + /* #define STM32F722xx */ /*!< STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC, + STM32F722VC, STM32F722RC Devices */ + /* #define STM32F723xx */ /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */ + /* #define STM32F732xx */ /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */ + /* #define STM32F733xx */ /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */ + /* #define STM32F730xx */ /*!< STM32F730R, STM32F730V, STM32F730Z, STM32F730I Devices */ + /* #define STM32F750xx */ /*!< STM32F750V, STM32F750Z, STM32F750N Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V1.2.4 + */ +#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ +#define __STM32F7_CMSIS_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */ +#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\ + |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32F7_CMSIS_VERSION_RC)) +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ +#if defined(STM32F722xx) + #include "stm32f722xx.h" +#elif defined(STM32F723xx) + #include "stm32f723xx.h" +#elif defined(STM32F732xx) + #include "stm32f732xx.h" +#elif defined(STM32F733xx) + #include "stm32f733xx.h" +#elif defined(STM32F756xx) + #include "stm32f756xx.h" +#elif defined(STM32F746xx) + #include "stm32f746xx.h" +#elif defined(STM32F745xx) + #include "stm32f745xx.h" +#elif defined(STM32F765xx) + #include "stm32f765xx.h" +#elif defined(STM32F767xx) + #include "stm32f767xx.h" +#elif defined(STM32F769xx) + #include "stm32f769xx.h" +#elif defined(STM32F777xx) + #include "stm32f777xx.h" +#elif defined(STM32F779xx) + #include "stm32f779xx.h" +#elif defined(STM32F730xx) + #include "stm32f730xx.h" +#elif defined(STM32F750xx) + #include "stm32f750xx.h" +#else + #error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0U, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0U, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0U, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Exported_macro + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + +/** + * @} + */ + +#ifdef USE_HAL_DRIVER + #include "stm32f7xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F7xx_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h new file mode 100644 index 0000000..126ac71 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h @@ -0,0 +1,123 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F7XX_H +#define __SYSTEM_STM32F7XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F7xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F7xx_System_Exported_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F7XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_armcc.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000..7d751fb --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,865 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_armclang.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000..d8031b0 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1869 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_compiler.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000..79a2cac --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_gcc.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000..1bd41a4 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_iccarm.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000..3c90a2c --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,935 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 19. June 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_version.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000..ae3f2e3 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_armv8mbl.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000..ec76ab2 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1918 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_armv8mml.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000..2d0f106 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2927 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm0.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..6f82227 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,949 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm0plus.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..b9377e8 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1083 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm1.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000..fd1c407 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm1.h @@ -0,0 +1,976 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 23. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm23.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000..8202a8d --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm23.h @@ -0,0 +1,1993 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm3.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..b0dfbd3 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1941 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm33.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000..02f82e2 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm33.h @@ -0,0 +1,3002 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_PCS_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm4.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..308b868 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm7.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000..ada6c2a --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2671 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_sc000.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..9086c64 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,1022 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_sc300.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..665822d --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1915 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/mpu_armv7.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000..7d4b600 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/mpu_armv8.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000..99ee9f9 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/tz_context.h b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 0000000..d4c1474 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h new file mode 100644 index 0000000..13b68bc --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -0,0 +1,3451 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR + +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#endif /* STM32L4 */ + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#define PAGESIZE FLASH_PAGE_SIZE +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#endif + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 +#endif + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/ + +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) + #define I2S_IT_TXE I2S_IT_TXP + #define I2S_IT_RXNE I2S_IT_RXP + + #define I2S_FLAG_TXE I2S_FLAG_TXP + #define I2S_FLAG_RXNE I2S_FLAG_RXP + #define I2S_FLAG_FRE I2S_FLAG_TIFRE +#endif + +#if defined(STM32F7) + #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + + #define SPI_FLAG_TXE SPI_FLAG_TXP + #define SPI_FLAG_RXNE SPI_FLAG_RXP + + #define SPI_IT_TXE SPI_IT_TXP + #define SPI_IT_RXNE SPI_IT_RXP + + #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET + #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET + #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET + #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + + /** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ + /** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + + /** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +# endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) + #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32L4) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#elif defined(STM32WB) || defined(STM32G0) +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h new file mode 100644 index 0000000..bc029ab --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h @@ -0,0 +1,276 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_H +#define __STM32F7xx_HAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_conf.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/** @defgroup SYSCFG_BootMode Boot Mode + * @{ + */ +#define SYSCFG_MEM_BOOT_ADD0 ((uint32_t)0x00000000U) +#define SYSCFG_MEM_BOOT_ADD1 SYSCFG_MEMRMP_MEM_BOOT +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @brief Freeze/Unfreeze Peripherals in Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)) +#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP)) +#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP)) + +#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#define __HAL_DBGMCU_UNFREEZE_LPTIM1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP)) + + +/** @brief FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FMC() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC)) + + +/** @brief FMC/SDRAM mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\ + SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\ + }while(0); +/** + * @brief Return the memory boot mapping as configured by user. + * @retval The boot mode as configured by user. The returned value can be one + * of the following values: + * @arg @ref SYSCFG_MEM_BOOT_ADD0 + * @arg @ref SYSCFG_MEM_BOOT_ADD1 + */ +#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT) + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @brief SYSCFG Break Cortex-M7 Lockup lock. + * Enable and lock the connection of Cortex-M7 LOCKUP (Hardfault) output to TIM1/8 Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL) + +/** @brief SYSCFG Break PVD lock. + * Enable and lock the PVD connection to Timer1/8 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_PVDL) +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Functions + * @{ + */ +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ +/* Initialization and Configuration functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); +/** + * @} + */ + + /* Exported variables ---------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); +void HAL_EnableCompensationCell(void); +void HAL_DisableCompensationCell(void); +void HAL_EnableFMCMemorySwapping(void); +void HAL_DisableFMCMemorySwapping(void); +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +void HAL_EnableMemorySwappingBank(void); +void HAL_DisableMemorySwappingBank(void); +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Variables HAL Private Variables + * @{ + */ +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h new file mode 100644 index 0000000..f600c5b --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h @@ -0,0 +1,406 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CORTEX_H +#define __STM32F7xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types Cortex Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +}MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) + +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) +#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U) +#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U) +#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01U) +#define MPU_REGION_DISABLE ((uint8_t)0x00U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00U) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01U) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01U) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05U) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00U) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01U) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02U) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03U) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04U) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05U) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06U) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07U) +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + + +/* Exported Macros -----------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +#if (__MPU_PRESENT == 1) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ + ((SIZE) == MPU_REGION_SIZE_64B) || \ + ((SIZE) == MPU_REGION_SIZE_128B) || \ + ((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CORTEX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h new file mode 100644 index 0000000..b8c3a86 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h @@ -0,0 +1,205 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_DEF +#define __STM32F7xx_HAL_DEF + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" +#include "Legacy/stm32_hal_legacy.h" +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockTypeDef; + +/* Exported macro ------------------------------------------------------------*/ + +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0) + +/** @brief Reset the Handle's State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) + +#if (USE_RTOS == 1U) + /* Reserved for future use */ + #error "USE_RTOS should be 0 in the current HAL release" +#else + #define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0U) + + #define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0U) +#endif /* USE_RTOS */ + +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ +#else + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #endif /* __CC_ARM */ + #endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */ +#if defined (__GNUC__) /* GNU Compiler */ + #define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32))) +#elif defined (__ICCARM__) /* IAR Compiler */ + #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf +#elif defined (__CC_ARM) /* ARM Compiler */ + #define ALIGN_32BYTES(buf) __align(32) buf +#endif + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) +/* ARM Compiler + ------------ + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || defined ( __GNUC__ ) +/* ARM & GNUCompiler + ---------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32F7xx_HAL_DEF */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h new file mode 100644 index 0000000..63f752a --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h @@ -0,0 +1,749 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_DMA_H +#define __STM32F7xx_HAL_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @brief DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Channel; /*!< Specifies the channel used for the specified stream. + This parameter can be a value of @ref DMAEx_Channel_selection */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Stream */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. + This parameter can be a value of @ref DMA_Priority_level */ + + uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. + This parameter can be a value of @ref DMA_FIFO_direct_mode + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected stream */ + + uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_FIFO_threshold_level */ + + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_Memory_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ + + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_Peripheral_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ +}DMA_InitTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ + HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ + HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ +}HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ +}HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ + HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ + HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ +}HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Stream_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + + void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ + + void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ + + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ + + uint32_t StreamIndex; /*!< DMA Stream Index */ + +}DMA_HandleTypeDef; + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @brief DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ +#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @brief DMA data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @brief DMA peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE DMA_SxCR_PINC /*!< Peripheral increment mode enable */ +#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @brief DMA memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE DMA_SxCR_MINC /*!< Memory increment mode enable */ +#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @brief DMA peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ +#define DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment: HalfWord */ +#define DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @brief DMA memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ +#define DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment: HalfWord */ +#define DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @brief DMA mode + * @{ + */ +#define DMA_NORMAL 0x00000000U /*!< Normal mode */ +#define DMA_CIRCULAR DMA_SxCR_CIRC /*!< Circular mode */ +#define DMA_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @brief DMA priority levels + * @{ + */ +#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ +#define DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level: Medium */ +#define DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level: High */ +#define DMA_PRIORITY_VERY_HIGH DMA_SxCR_PL /*!< Priority level: Very High */ +/** + * @} + */ + +/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode + * @brief DMA FIFO direct mode + * @{ + */ +#define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level + * @brief DMA FIFO level + * @{ + */ +#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ +#define DMA_FIFO_THRESHOLD_HALFFULL DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ +#define DMA_FIFO_THRESHOLD_3QUARTERSFULL DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ +#define DMA_FIFO_THRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ +/** + * @} + */ + +/** @defgroup DMA_Memory_burst DMA Memory burst + * @brief DMA memory burst + * @{ + */ +#define DMA_MBURST_SINGLE 0x00000000U +#define DMA_MBURST_INC4 DMA_SxCR_MBURST_0 +#define DMA_MBURST_INC8 DMA_SxCR_MBURST_1 +#define DMA_MBURST_INC16 DMA_SxCR_MBURST +/** + * @} + */ + +/** @defgroup DMA_Peripheral_burst DMA Peripheral burst + * @brief DMA peripheral burst + * @{ + */ +#define DMA_PBURST_SINGLE 0x00000000U +#define DMA_PBURST_INC4 DMA_SxCR_PBURST_0 +#define DMA_PBURST_INC8 DMA_SxCR_PBURST_1 +#define DMA_PBURST_INC16 DMA_SxCR_PBURST +/** + * @} + */ + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @brief DMA interrupts definition + * @{ + */ +#define DMA_IT_TC DMA_SxCR_TCIE +#define DMA_IT_HT DMA_SxCR_HTIE +#define DMA_IT_TE DMA_SxCR_TEIE +#define DMA_IT_DME DMA_SxCR_DMEIE +#define DMA_IT_FE 0x00000080U +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @brief DMA flag definitions + * @{ + */ +#define DMA_FLAG_FEIF0_4 0x00000001U +#define DMA_FLAG_DMEIF0_4 0x00000004U +#define DMA_FLAG_TEIF0_4 0x00000008U +#define DMA_FLAG_HTIF0_4 0x00000010U +#define DMA_FLAG_TCIF0_4 0x00000020U +#define DMA_FLAG_FEIF1_5 0x00000040U +#define DMA_FLAG_DMEIF1_5 0x00000100U +#define DMA_FLAG_TEIF1_5 0x00000200U +#define DMA_FLAG_HTIF1_5 0x00000400U +#define DMA_FLAG_TCIF1_5 0x00000800U +#define DMA_FLAG_FEIF2_6 0x00010000U +#define DMA_FLAG_DMEIF2_6 0x00040000U +#define DMA_FLAG_TEIF2_6 0x00080000U +#define DMA_FLAG_HTIF2_6 0x00100000U +#define DMA_FLAG_TCIF2_6 0x00200000U +#define DMA_FLAG_FEIF3_7 0x00400000U +#define DMA_FLAG_DMEIF3_7 0x01000000U +#define DMA_FLAG_TEIF3_7 0x02000000U +#define DMA_FLAG_HTIF3_7 0x04000000U +#define DMA_FLAG_TCIF3_7 0x08000000U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @brief Reset DMA handle state + * @param __HANDLE__ specifies the DMA handle. + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Return the current DMA Stream FIFO filled level. + * @param __HANDLE__ DMA handle + * @retval The FIFO filling state. + * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full + * and not empty. + * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. + * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. + * - DMA_FIFOStatus_Empty: when FIFO is empty + * - DMA_FIFOStatus_Full: when FIFO is full + */ +#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) + +/** + * @brief Enable the specified DMA Stream. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) + +/** + * @brief Disable the specified DMA Stream. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) + +/* Interrupt & Flag management */ + +/** + * @brief Return the current DMA Stream transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ + DMA_FLAG_TCIF3_7) + +/** + * @brief Return the current DMA Stream half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ + DMA_FLAG_HTIF3_7) + +/** + * @brief Return the current DMA Stream transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ + DMA_FLAG_TEIF3_7) + +/** + * @brief Return the current DMA Stream FIFO error flag. + * @param __HANDLE__ DMA handle + * @retval The specified FIFO error flag index. + */ +#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ + DMA_FLAG_FEIF3_7) + +/** + * @brief Return the current DMA Stream direct mode error flag. + * @param __HANDLE__ DMA handle + * @retval The specified direct mode error flag index. + */ +#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ + DMA_FLAG_DMEIF3_7) + +/** + * @brief Get the DMA Stream pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) + +/** + * @brief Clear the DMA Stream pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) + +/** + * @brief Enable the specified DMA Stream interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ +((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) + +/** + * @brief Disable the specified DMA Stream interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ +((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) + +/** + * @brief Check whether the specified DMA Stream interrupt is enabled or not. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval The state of DMA_IT. + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ + ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ + ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) + +/** + * @brief Writes the number of data units to be transferred on the DMA Stream. + * @param __HANDLE__ DMA handle + * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) + * Number of data items depends only on the Peripheral data format. + * + * @note If Peripheral data format is Bytes: number of data units is equal + * to total number of bytes to be transferred. + * + * @note If Peripheral data format is Half-Word: number of data units is + * equal to total number of bytes to be transferred / 2. + * + * @note If Peripheral data format is Word: number of data units is equal + * to total number of bytes to be transferred / 4. + * + * @retval The number of remaining data units in the current DMAy Streamx transfer. + */ +#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) + +/** + * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. + * @param __HANDLE__ DMA handle + * + * @retval The number of remaining data units in the current DMA Stream transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) + + +/* Include DMA HAL Extension module */ +#include "stm32f7xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @brief DMA Exported functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions + * @brief I/O operation functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/** + * @} + */ +/* Private Constants -------------------------------------------------------------*/ +/** @defgroup DMA_Private_Constants DMA Private Constants + * @brief DMA private defines and constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @brief DMA private macros + * @{ + */ +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR) || \ + ((MODE) == DMA_PFCTRL)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ + ((STATE) == DMA_FIFOMODE_ENABLE)) + +#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) + +#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ + ((BURST) == DMA_MBURST_INC4) || \ + ((BURST) == DMA_MBURST_INC8) || \ + ((BURST) == DMA_MBURST_INC16)) + +#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ + ((BURST) == DMA_PBURST_INC4) || \ + ((BURST) == DMA_PBURST_INC8) || \ + ((BURST) == DMA_PBURST_INC16)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h new file mode 100644 index 0000000..e657a89 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h @@ -0,0 +1,185 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_DMA_EX_H +#define __STM32F7xx_HAL_DMA_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @brief DMAEx Exported types + * @{ + */ + +/** + * @brief HAL DMA Memory definition + */ +typedef enum +{ + MEMORY0 = 0x00U, /*!< Memory 0 */ + MEMORY1 = 0x01U, /*!< Memory 1 */ + +}HAL_DMA_MemoryTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMAEx_Channel_selection DMA Channel selection + * @brief DMAEx channel selection + * @{ + */ +#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ +#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */ +#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */ +#define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */ +#define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */ +#define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */ +#define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */ +#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ +#define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ +#define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10*/ +#define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11*/ +#define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12*/ +#define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13*/ +#define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14*/ +#define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15*/ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @brief DMAEx Exported functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory); + +/** + * @} + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMA Private Macros + * @brief DMAEx private macros + * @{ + */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ + ((CHANNEL) == DMA_CHANNEL_1) || \ + ((CHANNEL) == DMA_CHANNEL_2) || \ + ((CHANNEL) == DMA_CHANNEL_3) || \ + ((CHANNEL) == DMA_CHANNEL_4) || \ + ((CHANNEL) == DMA_CHANNEL_5) || \ + ((CHANNEL) == DMA_CHANNEL_6) || \ + ((CHANNEL) == DMA_CHANNEL_7) || \ + ((CHANNEL) == DMA_CHANNEL_8) || \ + ((CHANNEL) == DMA_CHANNEL_9) || \ + ((CHANNEL) == DMA_CHANNEL_10) || \ + ((CHANNEL) == DMA_CHANNEL_11) || \ + ((CHANNEL) == DMA_CHANNEL_12) || \ + ((CHANNEL) == DMA_CHANNEL_13) || \ + ((CHANNEL) == DMA_CHANNEL_14) || \ + ((CHANNEL) == DMA_CHANNEL_15)) +#else +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ + ((CHANNEL) == DMA_CHANNEL_1) || \ + ((CHANNEL) == DMA_CHANNEL_2) || \ + ((CHANNEL) == DMA_CHANNEL_3) || \ + ((CHANNEL) == DMA_CHANNEL_4) || \ + ((CHANNEL) == DMA_CHANNEL_5) || \ + ((CHANNEL) == DMA_CHANNEL_6) || \ + ((CHANNEL) == DMA_CHANNEL_7)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx*/ +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h new file mode 100644 index 0000000..bf82a38 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h @@ -0,0 +1,260 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_EXTI_H +#define __STM32F7xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U, + HAL_EXTI_RISING_CB_ID = 0x01U, + HAL_EXTI_FALLING_CB_ID = 0x02U, +} EXTI_CallbackIDTypeDef; + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 EXTI_IMR_IM0 /*!< External interrupt line 0 */ +#define EXTI_LINE_1 EXTI_IMR_IM1 /*!< External interrupt line 1 */ +#define EXTI_LINE_2 EXTI_IMR_IM2 /*!< External interrupt line 2 */ +#define EXTI_LINE_3 EXTI_IMR_IM3 /*!< External interrupt line 3 */ +#define EXTI_LINE_4 EXTI_IMR_IM4 /*!< External interrupt line 4 */ +#define EXTI_LINE_5 EXTI_IMR_IM5 /*!< External interrupt line 5 */ +#define EXTI_LINE_6 EXTI_IMR_IM6 /*!< External interrupt line 6 */ +#define EXTI_LINE_7 EXTI_IMR_IM7 /*!< External interrupt line 7 */ +#define EXTI_LINE_8 EXTI_IMR_IM8 /*!< External interrupt line 8 */ +#define EXTI_LINE_9 EXTI_IMR_IM9 /*!< External interrupt line 9 */ +#define EXTI_LINE_10 EXTI_IMR_IM10 /*!< External interrupt line 10 */ +#define EXTI_LINE_11 EXTI_IMR_IM11 /*!< External interrupt line 11 */ +#define EXTI_LINE_12 EXTI_IMR_IM12 /*!< External interrupt line 12 */ +#define EXTI_LINE_13 EXTI_IMR_IM13 /*!< External interrupt line 13 */ +#define EXTI_LINE_14 EXTI_IMR_IM14 /*!< External interrupt line 14 */ +#define EXTI_LINE_15 EXTI_IMR_IM15 /*!< External interrupt line 15 */ +#if defined(EXTI_IMR_IM16) +#define EXTI_LINE_16 EXTI_IMR_IM16 /*!< External interrupt line 16 Connected to the PVD Output */ +#endif /* EXTI_IMR_IM16 */ +#if defined(EXTI_IMR_IM17) +#define EXTI_LINE_17 EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#endif /* EXTI_IMR_IM17 */ +#if defined(EXTI_IMR_IM18) +#define EXTI_LINE_18 EXTI_IMR_IM18 /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ +#endif /* EXTI_IMR_IM18 */ +#if defined(EXTI_IMR_IM19) +#define EXTI_LINE_19 EXTI_IMR_IM19 /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ +#endif /* EXTI_IMR_IM19 */ +#if defined(EXTI_IMR_IM20) +#define EXTI_LINE_20 EXTI_IMR_IM20 /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ +#endif /* EXTI_IMR_IM20 */ +#if defined(EXTI_IMR_IM21) +#define EXTI_LINE_21 EXTI_IMR_IM21 /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ +#endif /* EXTI_IMR_IM21 */ +#if defined(EXTI_IMR_IM22) +#define EXTI_LINE_22 EXTI_IMR_IM22 /*!< External interrupt line 22 Connected to the RTC Wakeup event */ +#endif /* EXTI_IMR_IM22 */ +#if defined(EXTI_IMR_IM23) +#define EXTI_LINE_23 EXTI_IMR_IM23 /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */ +#endif /* EXTI_IMR_IM23 */ +#if defined(EXTI_IMR_IM24) +#define EXTI_LINE_24 EXTI_IMR_IM24 /*!< External interrupt line 24 Connected to the MDIO Slave global Interrupt Wakeup event */ +#endif /* EXTI_IMR_IM24 */ +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING | EXTI_TRIGGER_RISING_FALLING) + +/** + * @brief EXTI Line number + */ +#define EXTI_LINE_NB 25u + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~EXTI_IMR_IM) == 0x00U) && (__LINE__)) + +#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & ~EXTI_MODE_MASK) == 0x00U)) + +#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U) + +#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_FALLING) || \ + ((__LINE__) == EXTI_TRIGGER_RISING) || \ + ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)) + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h new file mode 100644 index 0000000..66a901e --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h @@ -0,0 +1,418 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_FLASH_H +#define __STM32F7xx_HAL_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0U, + FLASH_PROC_SECTERASE, + FLASH_PROC_MASSERASE, + FLASH_PROC_PROGRAM +} FLASH_ProcedureTypeDef; + + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ + + __IO uint32_t NbSectorsToErase; /* Internal variable to save the remaining sectors to erase in IT context */ + + __IO uint8_t VoltageForErase; /* Internal variable to provide voltage range selected by user in IT context */ + + __IO uint32_t Sector; /* Internal variable to define the current sector which is erasing */ + + __IO uint32_t Address; /* Internal variable to save address selected for program */ + + HAL_LockTypeDef Lock; /* FLASH locking object */ + + __IO uint32_t ErrorCode; /* FLASH error code */ + +}FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Error_Code FLASH Error Code + * @brief FLASH Error Code + * @{ + */ +#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002U) /*!< Programming Sequence error */ +#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U) /*!< Programming Parallelism error */ +#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U) /*!< Programming Alignment error */ +#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U) /*!< Write protection error */ +#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U) /*!< Operation Error */ +#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000040U) /*!< Read Protection Error */ +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Type Program + * @{ + */ +#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U) /*!< Program a double word (64-bit) at a specified address */ +/** + * @} + */ + +/** @defgroup FLASH_Flag_definition FLASH Flag definition + * @brief Flag definition + * @{ + */ +#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH operation Error flag */ +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ +#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */ +#define FLASH_FLAG_ERSERR FLASH_SR_ERSERR /*!< FLASH Erasing Sequence error flag */ +#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ + +#if defined (FLASH_OPTCR2_PCROP) +#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protection error flag */ +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR | FLASH_FLAG_RDERR) +#else +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR) +#endif /* FLASH_OPTCR2_PCROP */ +/** + * @} + */ + +/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition + * @brief FLASH Interrupt definition + * @{ + */ +#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_ERR ((uint32_t)0x02000000U) /*!< Error Interrupt source */ +/** + * @} + */ + +/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism + * @{ + */ +#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U) +#define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0) +#define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1) +#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE) +#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU) +/** + * @} + */ + +/** @defgroup FLASH_Keys FLASH Keys + * @{ + */ +#define FLASH_KEY1 ((uint32_t)0x45670123U) +#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU) +#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU) +#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU) +/** + * @} + */ + +/** @defgroup FLASH_Sectors FLASH Sectors + * @{ + */ +#if (FLASH_SECTOR_TOTAL == 2) +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#elif (FLASH_SECTOR_TOTAL == 4) +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ +#else +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ +#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */ +#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */ +#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */ +#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */ +#endif /* FLASH_SECTOR_TOTAL */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @{ + */ +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__ FLASH Latency + * The value of this parameter depend on device used within the same series + * @retval none + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__)) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * The value of this parameter depend on device used within the same series + */ +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) + +/** + * @brief Enable the FLASH prefetch buffer. + * @retval none + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval none + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN)) + +/** + * @brief Enable the FLASH Adaptive Real-Time memory accelerator. + * @note The ART accelerator is available only for flash access on ITCM interface. + * @retval none + */ +#define __HAL_FLASH_ART_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN) + +/** + * @brief Disable the FLASH Adaptive Real-Time memory accelerator. + * @retval none + */ +#define __HAL_FLASH_ART_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN) + +/** + * @brief Resets the FLASH Adaptive Real-Time memory accelerator. + * @note This function must be used only when the Adaptive Real-Time memory accelerator + * is disabled. + * @retval None + */ +#define __HAL_FLASH_ART_RESET() (FLASH->ACR |= FLASH_ACR_ARTRST) + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_ERR: Error Interrupt + * @retval none + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_ERR: Error Interrupt + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__)) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR : FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag + * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag + * @arg FLASH_FLAG_BSY : FLASH Busy flag + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__))) + +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR : FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag + * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) +/** + * @} + */ + +/* Include FLASH HAL Extension module */ +#include "stm32f7xx_hal_flash_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +/* Program operation functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +/* Option bytes control */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ************************************************/ +uint32_t HAL_FLASH_GetError(void); +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ + +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ + +/** + * @brief OPTCR register byte 1 (Bits[15:8]) base address + */ +#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters + * @{ + */ +#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \ + ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_FLASH_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h new file mode 100644 index 0000000..d417503 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h @@ -0,0 +1,700 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_FLASH_EX_H +#define __STM32F7xx_HAL_FLASH_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or sector Erase. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + +#if defined (FLASH_OPTCR_nDBANK) + uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. + This parameter must be a value of @ref FLASHEx_Banks */ +#endif /* FLASH_OPTCR_nDBANK */ + + uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled + This parameter must be a value of @ref FLASHEx_Sectors */ + + uint32_t NbSectors; /*!< Number of sectors to be erased. + This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ + + uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism + This parameter must be a value of @ref FLASHEx_Voltage_Range */ + +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a value of @ref FLASHEx_Option_Type */ + + uint32_t WRPState; /*!< Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_WRP_State */ + + uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. + The value of this parameter depend on device used within the same series */ + + uint32_t RDPLevel; /*!< Set the read protection level. + This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ + + uint32_t BORLevel; /*!< Set the BOR Level. + This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ + + uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY / + IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT. + nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */ + + uint32_t BootAddr0; /*!< Boot base address when Boot pin = 0. + This parameter can be a value of @ref FLASHEx_Boot_Address */ + + uint32_t BootAddr1; /*!< Boot base address when Boot pin = 1. + This parameter can be a value of @ref FLASHEx_Boot_Address */ + +#if defined (FLASH_OPTCR2_PCROP) + uint32_t PCROPSector; /*!< Set the PCROP sector. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_Sectors */ + + uint32_t PCROPRdp; /*!< Set the PCROP_RDP option. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_RDP */ +#endif /* FLASH_OPTCR2_PCROP */ + +} FLASH_OBProgramInitTypeDef; + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASHEx_Type_Erase FLASH Type Erase + * @{ + */ +#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */ +#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */ +/** + * @} + */ + +/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range + * @{ + */ +#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */ +#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */ +#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */ +#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U) /*!< Device operating range: 2.7V to 3.6V + External Vpp */ +/** + * @} + */ + +/** @defgroup FLASHEx_WRP_State FLASH WRP State + * @{ + */ +#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */ +#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Type FLASH Option Type + * @{ + */ +#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */ +#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */ +#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */ +#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10U) /*!< Boot 0 Address configuration */ +#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20U) /*!< Boot 1 Address configuration */ +#if defined (FLASH_OPTCR2_PCROP) +#define OPTIONBYTE_PCROP ((uint32_t)0x40U) /*!< PCROP configuration */ +#define OPTIONBYTE_PCROP_RDP ((uint32_t)0x80U) /*!< PCROP_RDP configuration */ +#endif /* FLASH_OPTCR2_PCROP */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection + * @{ + */ +#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU) +#define OB_RDP_LEVEL_1 ((uint8_t)0x55U) +#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2 + it s no more possible to go back to level 1 or 0 */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog + * @{ + */ +#define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */ +#define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */ +/** + * @} + */ + + +/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog + * @{ + */ +#define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP + * @{ + */ +#define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY + * @{ + */ +#define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP + * @{ + */ +#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */ +#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY + * @{ + */ +#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */ +#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */ +/** + * @} + */ + +/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level + * @{ + */ +#define OB_BOR_LEVEL3 ((uint32_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */ +#define OB_BOR_LEVEL2 ((uint32_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */ +#define OB_BOR_LEVEL1 ((uint32_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */ +#define OB_BOR_OFF ((uint32_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */ +/** + * @} + */ + +#if defined (FLASH_OPTCR_nDBOOT) +/** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT + * @{ + */ +#define OB_DUAL_BOOT_DISABLE ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */ +#define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash + (Dual bank Boot mode), or RAM if Boot address option in RAM */ +/** + * @} + */ +#endif /* FLASH_OPTCR_nDBOOT */ + +#if defined (FLASH_OPTCR_nDBANK) +/** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank + * @{ + */ +#define OB_NDBANK_SINGLE_BANK ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */ +#define OB_NDBANK_DUAL_BANK ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */ +/** + * @} + */ +#endif /* FLASH_OPTCR_nDBANK */ + +/** @defgroup FLASHEx_Boot_Address FLASH Boot Address + * @{ + */ +#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U) /*!< Boot from ITCM RAM (0x00000000) */ +#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U) /*!< Boot from System memory bootloader (0x00100000) */ +#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U) /*!< Boot from Flash on ITCM interface (0x00200000) */ +#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */ +#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */ +#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */ +#if (SRAM2_BASE == 0x2003C000U) +#define OB_BOOTADDR_SRAM2 ((uint32_t)0x800FU) /*!< Boot from SRAM2 (0x2003C000) */ +#else +#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */ +#endif /* SRAM2_BASE == 0x2003C000U */ +/** + * @} + */ + +/** @defgroup FLASH_Latency FLASH Latency + * @{ + */ +#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */ +#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */ +#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */ +#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ +#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */ +#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */ +#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */ +#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */ +#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */ +#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */ +#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */ +#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */ +#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */ +#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */ +#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */ +#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */ +/** + * @} + */ + +#if defined (FLASH_OPTCR_nDBANK) +/** @defgroup FLASHEx_Banks FLASH Banks + * @{ + */ +#define FLASH_BANK_1 ((uint32_t)0x01U) /*!< Bank 1 */ +#define FLASH_BANK_2 ((uint32_t)0x02U) /*!< Bank 2 */ +#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */ +/** + * @} + */ +#endif /* FLASH_OPTCR_nDBANK */ + +/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit + * @{ + */ +#if defined (FLASH_OPTCR_nDBANK) +#define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */ +#else +#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER bit */ +#endif /* FLASH_OPTCR_nDBANK */ +/** + * @} + */ + +/** @defgroup FLASHEx_Sectors FLASH Sectors + * @{ + */ +#if (FLASH_SECTOR_TOTAL == 24) +#define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */ +#define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */ +#define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */ +#define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */ +#define FLASH_SECTOR_12 ((uint32_t)12U) /*!< Sector Number 12 */ +#define FLASH_SECTOR_13 ((uint32_t)13U) /*!< Sector Number 13 */ +#define FLASH_SECTOR_14 ((uint32_t)14U) /*!< Sector Number 14 */ +#define FLASH_SECTOR_15 ((uint32_t)15U) /*!< Sector Number 15 */ +#define FLASH_SECTOR_16 ((uint32_t)16U) /*!< Sector Number 16 */ +#define FLASH_SECTOR_17 ((uint32_t)17U) /*!< Sector Number 17 */ +#define FLASH_SECTOR_18 ((uint32_t)18U) /*!< Sector Number 18 */ +#define FLASH_SECTOR_19 ((uint32_t)19U) /*!< Sector Number 19 */ +#define FLASH_SECTOR_20 ((uint32_t)20U) /*!< Sector Number 20 */ +#define FLASH_SECTOR_21 ((uint32_t)21U) /*!< Sector Number 21 */ +#define FLASH_SECTOR_22 ((uint32_t)22U) /*!< Sector Number 22 */ +#define FLASH_SECTOR_23 ((uint32_t)23U) /*!< Sector Number 23 */ +#endif /* FLASH_SECTOR_TOTAL == 24 */ +/** + * @} + */ + +#if (FLASH_SECTOR_TOTAL == 24) +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register, + * nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11. + * For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register, + * nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and + * a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1). + * This behavior is applicable only for STM32F76xxx / STM32F77xxx devices. + * @{ + */ +/* Single Bank Sectors */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1 */ +#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2 */ +#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3 */ +#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4 */ +#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5 */ +#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6 */ +#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7 */ +#define OB_WRP_SECTOR_8 ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8 */ +#define OB_WRP_SECTOR_9 ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9 */ +#define OB_WRP_SECTOR_10 ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10 */ +#define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */ + +/* Dual Bank Sectors */ +#define OB_WRP_DB_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0 */ +#define OB_WRP_DB_SECTOR_1 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1 */ +#define OB_WRP_DB_SECTOR_2 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2 */ +#define OB_WRP_DB_SECTOR_3 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3 */ +#define OB_WRP_DB_SECTOR_4 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4 */ +#define OB_WRP_DB_SECTOR_5 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5 */ +#define OB_WRP_DB_SECTOR_6 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6 */ +#define OB_WRP_DB_SECTOR_7 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7 */ +#define OB_WRP_DB_SECTOR_8 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8 */ +#define OB_WRP_DB_SECTOR_9 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9 */ +#define OB_WRP_DB_SECTOR_10 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10 */ +#define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */ +#define OB_WRP_DB_SECTOR_12 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12 */ +#define OB_WRP_DB_SECTOR_13 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13 */ +#define OB_WRP_DB_SECTOR_14 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14 */ +#define OB_WRP_DB_SECTOR_15 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15 */ +#define OB_WRP_DB_SECTOR_16 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16 */ +#define OB_WRP_DB_SECTOR_17 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17 */ +#define OB_WRP_DB_SECTOR_18 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18 */ +#define OB_WRP_DB_SECTOR_19 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19 */ +#define OB_WRP_DB_SECTOR_20 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20 */ +#define OB_WRP_DB_SECTOR_21 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21 */ +#define OB_WRP_DB_SECTOR_22 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22 */ +#define OB_WRP_DB_SECTOR_23 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23 */ +#define OB_WRP_DB_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 24 */ + +#if (FLASH_SECTOR_TOTAL == 8) +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @{ + */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */ +#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */ +#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Sector4 */ +#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Sector5 */ +#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Sector6 */ +#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Sector7 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 8 */ + +#if (FLASH_SECTOR_TOTAL == 4) +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @{ + */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */ +#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x000F0000U) /*!< Write protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 4 */ + +#if (FLASH_SECTOR_TOTAL == 2) +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @{ + */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x00030000U) /*!< Write protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 2 */ + +#if defined (FLASH_OPTCR2_PCROP) +#if (FLASH_SECTOR_TOTAL == 8) +/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors + * @{ + */ +#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */ +#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */ +#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */ +#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */ +#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010U) /*!< PC Readout protection of Sector4 */ +#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020U) /*!< PC Readout protection of Sector5 */ +#define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040U) /*!< PC Readout protection of Sector6 */ +#define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080U) /*!< PC Readout protection of Sector7 */ +#define OB_PCROP_SECTOR_All ((uint32_t)0x000000FFU) /*!< PC Readout protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 8 */ + +#if (FLASH_SECTOR_TOTAL == 4) +/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors + * @{ + */ +#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */ +#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */ +#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */ +#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */ +#define OB_PCROP_SECTOR_All ((uint32_t)0x0000000FU) /*!< PC Readout protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 4 */ + +/** @defgroup FLASHEx_Option_Bytes_PCROP_RDP FLASH Option Bytes PCROP_RDP Bit + * @{ + */ +#define OB_PCROP_RDP_ENABLE ((uint32_t)0x80000000U) /*!< PCROP_RDP Enable */ +#define OB_PCROP_RDP_DISABLE ((uint32_t)0x00000000U) /*!< PCROP_RDP Disable */ +/** + * @} + */ +#endif /* FLASH_OPTCR2_PCROP */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @{ + */ +/** + * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1) + * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. + * @param __ADDRESS__ FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) + * @retval The FLASH Boot Base Adress + */ +#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14) + /** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ +/* Extension Program operation functions *************************************/ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASH Private Macros + * @{ + */ + +/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters + * @{ + */ + +#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + +#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_4)) + +#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \ + ((VALUE) == OB_WRPSTATE_ENABLE)) + +#if defined (FLASH_OPTCR2_PCROP) +#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1 |\ + OPTIONBYTE_PCROP | OPTIONBYTE_PCROP_RDP))) +#else +#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1))) +#endif /* FLASH_OPTCR2_PCROP */ + +#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013) + +#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ + ((LEVEL) == OB_RDP_LEVEL_1) ||\ + ((LEVEL) == OB_RDP_LEVEL_2)) + +#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW)) + +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) + +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) + +#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE)) + +#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE)) + +#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ + ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ + ((LATENCY) == FLASH_LATENCY_1) || \ + ((LATENCY) == FLASH_LATENCY_2) || \ + ((LATENCY) == FLASH_LATENCY_3) || \ + ((LATENCY) == FLASH_LATENCY_4) || \ + ((LATENCY) == FLASH_LATENCY_5) || \ + ((LATENCY) == FLASH_LATENCY_6) || \ + ((LATENCY) == FLASH_LATENCY_7) || \ + ((LATENCY) == FLASH_LATENCY_8) || \ + ((LATENCY) == FLASH_LATENCY_9) || \ + ((LATENCY) == FLASH_LATENCY_10) || \ + ((LATENCY) == FLASH_LATENCY_11) || \ + ((LATENCY) == FLASH_LATENCY_12) || \ + ((LATENCY) == FLASH_LATENCY_13) || \ + ((LATENCY) == FLASH_LATENCY_14) || \ + ((LATENCY) == FLASH_LATENCY_15)) + +#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \ + (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END))) +#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) + +#if (FLASH_SECTOR_TOTAL == 8) +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ + ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ + ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ + ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7)) + +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFF00FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 8 */ + +#if (FLASH_SECTOR_TOTAL == 24) +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ + ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ + ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ + ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\ + ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\ + ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\ + ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\ + ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\ + ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\ + ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\ + ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\ + ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23)) + +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 24 */ + +#if (FLASH_SECTOR_TOTAL == 4) +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ + ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3)) + +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFF0FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 4 */ + +#if (FLASH_SECTOR_TOTAL == 2) +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1)) + +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFCFFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 2 */ + +#if defined (FLASH_OPTCR_nDBANK) +#define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \ + ((VALUE) == OB_NDBANK_DUAL_BANK)) + +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2) || \ + ((BANK) == FLASH_BANK_BOTH)) +#endif /* FLASH_OPTCR_nDBANK */ + +#if defined (FLASH_OPTCR_nDBOOT) +#define IS_OB_NDBOOT(VALUE) (((VALUE) == OB_DUAL_BOOT_DISABLE) || \ + ((VALUE) == OB_DUAL_BOOT_ENABLE)) +#endif /* FLASH_OPTCR_nDBOOT */ + +#if defined (FLASH_OPTCR2_PCROP) +#define IS_OB_PCROP_SECTOR(SECTOR) (((SECTOR) & (uint32_t)0xFFFFFF00U) == 0x00000000U) +#define IS_OB_PCROP_RDP_VALUE(VALUE) (((VALUE) == OB_PCROP_RDP_DISABLE) || \ + ((VALUE) == OB_PCROP_RDP_ENABLE)) +#endif /* FLASH_OPTCR2_PCROP */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASH Private Functions + * @{ + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_FLASH_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h new file mode 100644 index 0000000..3d9de6e --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h @@ -0,0 +1,309 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_GPIO_H +#define __STM32F7xx_HAL_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode_define */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull_define */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed_define */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_Alternate_function_selection */ +}GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0, + GPIO_PIN_SET +}GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_pins_define GPIO pins define + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */ + +#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode_define GPIO mode define + * @brief GPIO Configuration Mode + * Elements values convention: 0xX0yz00YZ + * - X : GPIO mode or EXTI Mode + * - y : External IT or Event trigger detection + * - z : IO configuration on External IT or Event + * - Y : Output type (Push Pull or Open Drain) + * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * @{ + */ +#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */ + +#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */ + +#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup GPIO_speed_define GPIO speed define + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< Fast speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< High speed */ +/** + * @} + */ + + /** @defgroup GPIO_pull_define GPIO pull define + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */ +#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) +/** + * @} + */ + +/* Include GPIO HAL Extension module */ +#include "stm32f7xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) +#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00)) +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ + ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ + ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ + ((MODE) == GPIO_MODE_AF_PP) ||\ + ((MODE) == GPIO_MODE_AF_OD) ||\ + ((MODE) == GPIO_MODE_IT_RISING) ||\ + ((MODE) == GPIO_MODE_IT_FALLING) ||\ + ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING) ||\ + ((MODE) == GPIO_MODE_EVT_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_ANALOG)) +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \ + ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH)) +#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ + ((PULL) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h new file mode 100644 index 0000000..cd1413c --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h @@ -0,0 +1,658 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_GPIO_EX_H +#define __STM32F7xx_HAL_GPIO_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection + * @{ + */ +/*--------------- STM32F74xxx/STM32F75xxx/STM32F76xxx/STM32F77xxx -------------*/ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) ||\ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF1_UART5 ((uint8_t)0x01U) /* UART5 Alternate Function mapping */ +#define GPIO_AF1_I2C4 ((uint8_t)0x01U) /* I2C4 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */ +#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF3_CEC ((uint8_t)0x03U) /* CEC Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF3_DFSDM1 ((uint8_t)0x03U) /* DFSDM1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_I2C4 ((uint8_t)0x04U) /* I2C4 Alternate Function mapping */ +#define GPIO_AF4_CEC ((uint8_t)0x04U) /* CEC Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05U) /* SPI6 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF6_UART4 ((uint8_t)0x06U) /* UART4 Alternate Function mapping */ +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06U) /* DFSDM1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */ +#define GPIO_AF7_SPDIFRX ((uint8_t)0x07U) /* SPDIF-RX Alternate Function mapping */ +#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF7_SPI6 ((uint8_t)0x07U) /* SPI6 Alternate Function mapping */ +#define GPIO_AF7_DFSDM1 ((uint8_t)0x07U) /* DFSDM1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_SPDIFRX ((uint8_t)0x08U) /* SPIDIF-RX Alternate Function mapping */ +#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF8_SPI6 ((uint8_t)0x08U) /* SPI6 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09U) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx) +#define GPIO_AF9_LTDC ((uint8_t)0x09U) /* LCD-TFT Alternate Function mapping */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx) +#define GPIO_AF9_FMC ((uint8_t)0x09U) /* FMC Alternate Function mapping */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */ +#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */ +#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF10_DFSDM1 ((uint8_t)0x0AU) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */ +#define GPIO_AF10_LTDC ((uint8_t)0x0AU) /* LCD-TFT Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0BU) /* ETHERNET Alternate Function mapping */ +#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define GPIO_AF11_CAN3 ((uint8_t)0x0BU) /* CAN3 Alternate Function mapping */ +#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */ +#define GPIO_AF11_I2C4 ((uint8_t)0x0BU) /* I2C4 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ +#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define GPIO_AF12_MDIOS ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ +#define GPIO_AF12_UART7 ((uint8_t)0xCU) /* UART7 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0DU) /* DCMI Alternate Function mapping */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define GPIO_AF13_DSI ((uint8_t)0x0DU) /* DSI Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx) +#define GPIO_AF13_LTDC ((uint8_t)0x0DU) /* LTDC Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LTDC ((uint8_t)0x0EU) /* LCD-TFT Alternate Function mapping */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------- STM32F72xxx/STM32F73xxx -----------------------*/ +#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) || defined(STM32F730xx) + /** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */ +#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */ +#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */ +#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */ +#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */ +#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_RNG ((uint8_t)0x0DU) /* RNG Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ +/*----------------------------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros + * @{ + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions + * @{ + */ +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Constants GPIO Private Constants + * @{ + */ + +/** + * @brief GPIO pin available on the platform + */ +/* Defines the available pins per GPIOs */ +#define GPIOA_PIN_AVAILABLE GPIO_PIN_All +#define GPIOB_PIN_AVAILABLE GPIO_PIN_All +#define GPIOC_PIN_AVAILABLE GPIO_PIN_All +#define GPIOD_PIN_AVAILABLE GPIO_PIN_All +#define GPIOE_PIN_AVAILABLE GPIO_PIN_All +#define GPIOF_PIN_AVAILABLE GPIO_PIN_All +#define GPIOG_PIN_AVAILABLE GPIO_PIN_All +#define GPIOI_PIN_AVAILABLE GPIO_PIN_All +#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All +#define GPIOH_PIN_AVAILABLE GPIO_PIN_All +#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \ + GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Macros GPIO Private Macros + * @{ + */ +/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index + * @{ + */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U :\ + ((__GPIOx__) == (GPIOH))? 7U :\ + ((__GPIOx__) == (GPIOI))? 8U :\ + ((__GPIOx__) == (GPIOJ))? 9U : 10U) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U :\ + ((__GPIOx__) == (GPIOH))? 7U : 8U) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ +/** + * @} + */ + +#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \ + ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE)))) +/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function + * @{ + */ +#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \ + ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF14_LTDC)) +#elif defined(STM32F745xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF10_OTG_FS) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT)) +#elif defined(STM32F767xx) || defined(STM32F777xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF9_LTDC) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ + ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF14_LTDC)) +#elif defined(STM32F769xx) || defined(STM32F779xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ + ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI)) +#elif defined(STM32F765xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ + ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF10_OTG_FS)) +#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF5_SPI3) || \ + ((AF) == GPIO_AF5_SPI4) || ((AF) == GPIO_AF5_SPI5) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF9_QUADSPI) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QUADSPI) || \ + ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ + ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \ + ((AF) == GPIO_AF10_OTG_FS)) +#endif /* STM32F756xx || STM32F746xx || STM32F750xx */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_GPIO_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h new file mode 100644 index 0000000..f09e057 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h @@ -0,0 +1,782 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_I2C_H +#define STM32F7xx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter calculated by referring to I2C initialization + section in Reference manual */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap :\n + * b7-b6 Error information\n + * 00 : No Error\n + * 01 : Abort (Abort user request on going)\n + * 10 : Timeout\n + * 11 : Error\n + * b5 Peripheral initialization status\n + * 0 : Reset (peripheral not initialized)\n + * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n + * b4 (not used)\n + * x : Should be set to 0\n + * b3\n + * 0 : Ready or Busy (No Listen mode ongoing)\n + * 1 : Listen (peripheral in Address Listen Mode)\n + * b2 Intrinsic process state\n + * 0 : Ready\n + * 1 : Busy (peripheral busy with some configuration or internal operations)\n + * b1 Rx state\n + * 0 : Ready (no Rx operation ongoing)\n + * 1 : Busy (Rx operation ongoing)\n + * b0 Tx state\n + * 0 : Ready (no Tx operation ongoing)\n + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +typedef struct __I2C_HandleTypeDef +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can + be a value of @ref I2C_XFEROPTIONS */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state */ + + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options + * @{ + */ +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x000000AAU) +#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) +/** + * @} + */ + +/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE (0x00000000U) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks + * @{ + */ +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + +/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE (0x00000000U) +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE (0x00000000U) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0x00000001U) +#define I2C_MEMADD_SIZE_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View + * @{ + */ +#define I2C_DIRECTION_TRANSMIT (0x00000000U) +#define I2C_DIRECTION_RECEIVE (0x00000001U) +/** + * @} + */ + +/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode + * @{ + */ +#define I2C_RELOAD_MODE I2C_CR2_RELOAD +#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND +#define I2C_SOFTEND_MODE (0x00000000U) +/** + * @} + */ + +/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode + * @{ + */ +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_AF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY +#define I2C_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif + +/** @brief Enable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_TXIS Transmit interrupt status + * @arg @ref I2C_FLAG_RXNE Receive data register not empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_TC Transfer complete (master mode) + * @arg @ref I2C_FLAG_TCR Transfer complete reload + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * @arg @ref I2C_FLAG_BUSY Bus busy + * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define I2C_FLAG_MASK (0x0001FFFFU) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ + : ((__HANDLE__)->Instance->ICR = (__FLAG__))) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +/** + * @} + */ + +/* Include I2C HAL Extended module */ +#include "stm32f7xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ + +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + +#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) + +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) + +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) + +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)) +#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) + +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32f7xx_hal_i2c.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F7xx_HAL_I2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h new file mode 100644 index 0000000..d5d7531 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h @@ -0,0 +1,205 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_I2C_EX_H +#define STM32F7xx_HAL_I2C_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus + * @{ + */ +#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ +#if defined(SYSCFG_PMC_I2C_PB6_FMP) +#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#else +#define I2C_FASTMODEPLUS_PB6 (uint32_t)(0x00000004U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB6 not supported */ +#define I2C_FASTMODEPLUS_PB7 (uint32_t)(0x00000008U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB7 not supported */ +#endif +#if defined(SYSCFG_PMC_I2C_PB8_FMP) +#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#else +#define I2C_FASTMODEPLUS_PB8 (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported */ +#define I2C_FASTMODEPLUS_PB9 (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported */ +#endif +#if defined(SYSCFG_PMC_I2C1_FMP) +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#else +#define I2C_FASTMODEPLUS_I2C1 (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported */ +#endif +#if defined(SYSCFG_PMC_I2C2_FMP) +#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#else +#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ +#endif +#if defined(SYSCFG_PMC_I2C3_FMP) +#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#else +#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */ +#endif +#if defined(SYSCFG_PMC_I2C4_FMP) +#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ +#else +#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */ +#endif +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +#if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP) +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +#endif + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#if (defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) && defined(SYSCFG_PMC_I2C4_FMP)) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4)) +#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3)) +#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2)) +#elif defined(SYSCFG_PMC_I2C1_FMP) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1)) +#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */ +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_I2C_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h new file mode 100644 index 0000000..e9ca922 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h @@ -0,0 +1,404 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_PWR_H +#define __STM32F7xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. + This parameter can be a value of @ref PWR_PVD_detection_level */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode */ +}PWR_PVDTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_PVD_detection_level PWR PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 +#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 +#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 +#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 +#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 +#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 +#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 +#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7/* External input analog voltage + (Compare internally to VREFINT) */ + +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U) +#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) +/** + * @} + */ + +/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale + * @{ + */ +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS +#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 +#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR1_VOS_0 +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Flag + * @{ + */ +#define PWR_FLAG_WU PWR_CSR1_WUIF +#define PWR_FLAG_SB PWR_CSR1_SBF +#define PWR_FLAG_PVDO PWR_CSR1_PVDO +#define PWR_FLAG_BRR PWR_CSR1_BRR +#define PWR_FLAG_VOSRDY PWR_CSR1_VOSRDY +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macro PWR Exported Macro + * @{ + */ + +/** @brief macros configure the main internal regulator output voltage. + * @param __REGULATOR__ specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption when the device does + * not operate at the maximum frequency (refer to the datasheets for more details). + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode + * @retval None + */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ + __IO uint32_t tmpreg; \ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Check PWR flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received on the internal wakeup line in standby mode (RTC alarm (Alarm A or Alarm B), + * RTC Tamper event, RTC TimeStamp event or RTC Wakeup)). + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset + * when the device wakes up from Standby mode or by a system reset + * or power reset. + * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage + * scaling output selection is ready. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the PWR's pending flags. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_SB: StandBy flag + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR1 |= (__FLAG__) << 2) + +/** + * @brief Enable the PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable the PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief PVD EXTI line configuration: set rising & falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + +/** + * @brief checks whether the specified PVD Exti interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) + +/** + * @brief Clear the PVD Exti flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) + +/** + * @brief Generates a Software interrupt on PVD EXTI line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) + +/** + * @} + */ + +/* Include PWR HAL Extension module */ +#include "stm32f7xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions **********************************************/ +/* PVD configuration */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + +/* WakeUp pins configuration */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes entry */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +/* Power PVD IRQ Handler */ +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); + +/* Cortex System Control functions *******************************************/ +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line + * @{ + */ +#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_IM16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ +/** + * @} + */ + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters + * @{ + */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) +#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F7xx_HAL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h new file mode 100644 index 0000000..e35d3bb --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h @@ -0,0 +1,262 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_PWR_EX_H +#define __STM32F7xx_HAL_PWR_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ +/** @defgroup PWREx_WakeUp_Pins PWREx Wake Up Pins + * @{ + */ +#define PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1 +#define PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2 +#define PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3 +#define PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4 +#define PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5 +#define PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6 +#define PWR_WAKEUP_PIN1_HIGH PWR_CSR2_EWUP1 +#define PWR_WAKEUP_PIN2_HIGH PWR_CSR2_EWUP2 +#define PWR_WAKEUP_PIN3_HIGH PWR_CSR2_EWUP3 +#define PWR_WAKEUP_PIN4_HIGH PWR_CSR2_EWUP4 +#define PWR_WAKEUP_PIN5_HIGH PWR_CSR2_EWUP5 +#define PWR_WAKEUP_PIN6_HIGH PWR_CSR2_EWUP6 +#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1) +#define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2) +#define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3) +#define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4) +#define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5) +#define PWR_WAKEUP_PIN6_LOW (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6) + +/** + * @} + */ + +/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode + * @{ + */ +#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR1_MRUDS +#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS)) +/** + * @} + */ + +/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag + * @{ + */ +#define PWR_FLAG_ODRDY PWR_CSR1_ODRDY +#define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY +#define PWR_FLAG_UDRDY PWR_CSR1_UDRDY +/** + * @} + */ + +/** @defgroup PWREx_Wakeup_Pins_Flag PWREx Wake Up Pin Flags + * @{ + */ +#define PWR_WAKEUP_PIN_FLAG1 PWR_CSR2_WUPF1 +#define PWR_WAKEUP_PIN_FLAG2 PWR_CSR2_WUPF2 +#define PWR_WAKEUP_PIN_FLAG3 PWR_CSR2_WUPF3 +#define PWR_WAKEUP_PIN_FLAG4 PWR_CSR2_WUPF4 +#define PWR_WAKEUP_PIN_FLAG5 PWR_CSR2_WUPF5 +#define PWR_WAKEUP_PIN_FLAG6 PWR_CSR2_WUPF6 +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Macro PWREx Exported Macro + * @{ + */ +/** @brief Macros to enable or disable the Over drive mode. + */ +#define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN) +#define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN)) + +/** @brief Macros to enable or disable the Over drive switching. + */ +#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN) +#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN)) + +/** @brief Macros to enable or disable the Under drive mode. + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main regulator or the low power regulator + * is in low voltage mode. + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + */ +#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN) +#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN)) + +/** @brief Check PWR flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode + * is ready + * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode + * switching is ready + * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode + * is enabled in Stop mode + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the Under-Drive Ready flag. + */ +#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY) + +/** @brief Check Wake Up flag is set or not. + * @param __WUFLAG__ specifies the Wake Up flag to check. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0 + * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2 + * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1 + * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13 + * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8 + * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11 + */ +#define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__)) + +/** @brief Clear the WakeUp pins flags. + * @param __WUFLAG__ specifies the Wake Up pin flag to clear. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0 + * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2 + * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1 + * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13 + * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8 + * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11 + */ +#define __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |= (__WUFLAG__)) +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 + * @{ + */ +uint32_t HAL_PWREx_GetVoltageRange(void); +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); + +void HAL_PWREx_EnableFlashPowerDown(void); +void HAL_PWREx_DisableFlashPowerDown(void); +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void); +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); + +void HAL_PWREx_EnableMainRegulatorLowVoltage(void); +void HAL_PWREx_DisableMainRegulatorLowVoltage(void); +void HAL_PWREx_EnableLowRegulatorLowVoltage(void); +void HAL_PWREx_DisableLowRegulatorLowVoltage(void); + +HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void); +HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void); +HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWREx_Private_Macros PWREx Private Macros + * @{ + */ + +/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters + * @{ + */ +#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON)) +#define IS_PWR_WAKEUP_PIN(__PIN__) (((__PIN__) == PWR_WAKEUP_PIN1) || \ + ((__PIN__) == PWR_WAKEUP_PIN2) || \ + ((__PIN__) == PWR_WAKEUP_PIN3) || \ + ((__PIN__) == PWR_WAKEUP_PIN4) || \ + ((__PIN__) == PWR_WAKEUP_PIN5) || \ + ((__PIN__) == PWR_WAKEUP_PIN6) || \ + ((__PIN__) == PWR_WAKEUP_PIN1_HIGH) || \ + ((__PIN__) == PWR_WAKEUP_PIN2_HIGH) || \ + ((__PIN__) == PWR_WAKEUP_PIN3_HIGH) || \ + ((__PIN__) == PWR_WAKEUP_PIN4_HIGH) || \ + ((__PIN__) == PWR_WAKEUP_PIN5_HIGH) || \ + ((__PIN__) == PWR_WAKEUP_PIN6_HIGH) || \ + ((__PIN__) == PWR_WAKEUP_PIN1_LOW) || \ + ((__PIN__) == PWR_WAKEUP_PIN2_LOW) || \ + ((__PIN__) == PWR_WAKEUP_PIN3_LOW) || \ + ((__PIN__) == PWR_WAKEUP_PIN4_LOW) || \ + ((__PIN__) == PWR_WAKEUP_PIN5_LOW) || \ + ((__PIN__) == PWR_WAKEUP_PIN6_LOW)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F7xx_HAL_PWR_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h new file mode 100644 index 0000000..dfeb31b --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h @@ -0,0 +1,1310 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_RCC_H +#define __STM32F7xx_HAL_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/* Include RCC HAL Extended module */ +/* (include on top of file since RCC structures are defined in extended file) */ +#include "stm32f7xx_hal_rcc_ex.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ + +}RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + +}RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) +#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) +#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) +#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) +#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) +/** + * @} + */ + +/** @defgroup RCC_HSE_Config RCC HSE Config + * @{ + */ +#define RCC_HSE_OFF ((uint32_t)0x00000000U) +#define RCC_HSE_ON RCC_CR_HSEON +#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) +/** + * @} + */ + +/** @defgroup RCC_LSE_Config RCC LSE Config + * @{ + */ +#define RCC_LSE_OFF ((uint32_t)0x00000000U) +#define RCC_LSE_ON RCC_BDCR_LSEON +#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) +/** + * @} + */ + +/** @defgroup RCC_HSI_Config RCC HSI Config + * @{ + */ +#define RCC_HSI_OFF ((uint32_t)0x00000000U) +#define RCC_HSI_ON RCC_CR_HSION + +#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config RCC LSI Config + * @{ + */ +#define RCC_LSI_OFF ((uint32_t)0x00000000U) +#define RCC_LSI_ON RCC_CSR_LSION +/** + * @} + */ + +/** @defgroup RCC_PLL_Config RCC PLL Config + * @{ + */ +#define RCC_PLL_NONE ((uint32_t)0x00000000U) +#define RCC_PLL_OFF ((uint32_t)0x00000001U) +#define RCC_PLL_ON ((uint32_t)0x00000002U) +/** + * @} + */ + +/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider + * @{ + */ +#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) +#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) +#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) +#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ +#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI +#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type RCC System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) +#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) +#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) +#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source RCC System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL +/** + * @} + */ + + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 +#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 +#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 +#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 +#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 +#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 +#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 +#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 +#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 +#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 +#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) +#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U) +#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U) +#define RCC_RTCCLKSOURCE_HSE_DIVX ((uint32_t)0x00000300U) +#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U) +#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U) +#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U) +#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U) +#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U) +#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U) +#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U) +#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U) +#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U) +#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U) +#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U) +#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U) +#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U) +#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U) +#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U) +#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U) +#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U) +#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U) +#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U) +/** + * @} + */ + + + +/** @defgroup RCC_MCO_Index RCC MCO Index + * @{ + */ +#define RCC_MCO1 ((uint32_t)0x00000000U) +#define RCC_MCO2 ((uint32_t)0x00000001U) +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U) +#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 +#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 +#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 +/** + * @} + */ + +/** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source + * @{ + */ +#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U) +#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 +#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 +#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 ((uint32_t)0x00000000U) +#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 +#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) +#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) +#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE +/** + * @} + */ + +/** @defgroup RCC_Interrupt RCC Interrupt + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)0x01U) +#define RCC_IT_LSERDY ((uint8_t)0x02U) +#define RCC_IT_HSIRDY ((uint8_t)0x04U) +#define RCC_IT_HSERDY ((uint8_t)0x08U) +#define RCC_IT_PLLRDY ((uint8_t)0x10U) +#define RCC_IT_PLLI2SRDY ((uint8_t)0x20U) +#define RCC_IT_PLLSAIRDY ((uint8_t)0x40U) +#define RCC_IT_CSS ((uint8_t)0x80U) +/** + * @} + */ + +/** @defgroup RCC_Flag RCC Flags + * Elements values convention: 0XXYYYYYb + * - YYYYY : Flag position in the register + * - 0XX : Register index + * - 01: CR register + * - 10: BDCR register + * - 11: CSR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21U) +#define RCC_FLAG_HSERDY ((uint8_t)0x31U) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39U) +#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU) +#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU) + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((uint8_t)0x41U) + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((uint8_t)0x61U) +#define RCC_FLAG_BORRST ((uint8_t)0x79U) +#define RCC_FLAG_PINRST ((uint8_t)0x7AU) +#define RCC_FLAG_PORRST ((uint8_t)0x7BU) +#define RCC_FLAG_SFTRST ((uint8_t)0x7CU) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7DU) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7EU) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7FU) +/** + * @} + */ + +/** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations + * @{ + */ +#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) +#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 +#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET) + +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) + +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief EGet the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release + * @brief Force or release AHB peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) +#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) + +#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) +#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) + +/** + * @} + */ + +/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) + +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) + +/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) +#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) + +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) +#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) + +/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET) + +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET) + +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_HSI_Configuration HSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION)) +#define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION)) + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value. + * (default is RCC_HSICALIBRATION_DEFAULT). + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\ + RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_CR_HSITRIM_Pos)) +/** + * @} + */ + +/** @defgroup RCC_LSI_Configuration LSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION)) +#define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION)) +/** + * @} + */ + +/** @defgroup RCC_HSE_Configuration HSE Configuration + * @{ + */ +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator. + * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + } while(0) +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration LSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * User should request a transition to LSE Off first and then LSE On or LSE Bypass. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg RCC_LSE_ON: turn ON the LSE oscillator. + * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + } while(0) +/** + * @} + */ + +/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration + * @{ + */ + +/** @brief Macros to enable or disable the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN)) +#define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN)) + +/** @brief Macros to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by + * a Power On Reset (POR). + * @param __RTCCLKSource__ specifies the RTC clock source. + * This parameter can be one of the following values: + @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + */ +#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) + +#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ + RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \ + } while (0) + +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** + * @brief Get the RTC and HSE clock divider (RTCPRE). + * @retval Returned value can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + */ +#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL) + +/** @brief Macros to force or release the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST)) +#define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST)) +/** + * @} + */ + +/** @defgroup RCC_PLL_Configuration PLL Configuration + * @{ + */ + +/** @brief Macros to enable or disable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) +#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) + +/** @brief Macro to configure the PLL clock source. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * + */ +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) + +/** @brief Macro to configure the PLL multiplication factor. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * + */ +#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) +/** + * @} + */ + +/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration + * @{ + */ + +/** @brief Macro to configure the I2S clock source (I2SCLK). + * @note This function must be called before enabling the I2S APB clock. + * @param __SOURCE__ specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. + * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin + * used as I2S clock source. + */ +#define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \ + RCC->CFGR |= (__SOURCE__); \ + }while(0) + +/** @brief Macros to enable or disable the PLLI2S. + * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON)) +#define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON)) +/** + * @} + */ + +/** @defgroup RCC_Get_Clock_source Get Clock source + * @{ + */ +/** + * @brief Macro to configure the system clock source. + * @param __RCC_SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. + */ +#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) + +/** + * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability. + * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. + * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. + * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. + * @retval None + */ +#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \ + (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) + +/** @brief Macro to get the oscillator used as PLL clock source. + * @retval The oscillator used as PLL clock source. The returned value can be one + * of the following: + * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) +/** + * @} + */ + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +/** @brief Macro to configure the MCO1 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + */ + +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** @brief Macro to configure the MCO2 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + */ + +#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3))); +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable + * the selected interrupts). + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) + +/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable + * the selected interrupts). + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) + +/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] + * bits to clear the selected interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + * @arg RCC_IT_CSS: Clock Security System interrupt + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, + * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) + +/** @brief Check RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. + * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. + * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready. + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. + * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. + * @arg RCC_FLAG_PINRST: Pin reset. + * @arg RCC_FLAG_PORRST: POR/PDR reset. + * @arg RCC_FLAG_SFTRST: Software reset. + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. + * @arg RCC_FLAG_LPWRRST: Low Power reset. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define RCC_FLAG_MASK ((uint8_t)0x1F) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0) + +/** + * @} + */ + +/** + * @} + */ + +/* Include RCC HAL Extension module */ +#include "stm32f7xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ + /** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); + +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); + +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ +#define PLLI2S_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */ +#define PLLSAI_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */ + +/** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias + * @brief RCC registers bit address alias + * @{ + */ +/* CIR register byte 2 (Bits[15:8]) base address */ +#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) + +#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +/** + * @} + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ +#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15) + +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_BYPASS)) + +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_BYPASS)) + +#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) + +#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) + +#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) + +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) +#define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63)) + +#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) + +#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \ + ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8)) +#define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) + +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ + ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ + ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ + ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ + ((HCLK) == RCC_SYSCLK_DIV512)) + +#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15)) + +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ + ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ + ((PCLK) == RCC_HCLK_DIV16)) + +#define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2)) + + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) + +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ + ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ + ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ + ((DIV) == RCC_MCODIV_5)) +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) + +#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31)) + + +#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \ + ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \ + ((DRIVE) == RCC_LSEDRIVE_HIGH)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h new file mode 100644 index 0000000..f92f9d6 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h @@ -0,0 +1,3524 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_RCC_EX_H +#define __STM32F7xx_HAL_RCC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ + + uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). + This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ + + uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks. + This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + uint32_t PLLR; /*!< PLLR: Division factor for DSI clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +}RCC_PLLInitTypeDef; + +/** + * @brief PLLI2S Clock structure definition + */ +typedef struct +{ + uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock. + This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. + This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +}RCC_PLLI2SInitTypeDef; + +/** + * @brief PLLSAI Clock structure definition + */ +typedef struct +{ + uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432. + This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ + + uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock. + This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider + This parameter will be used only when PLLSAI is disabled */ +}RCC_PLLSAIInitTypeDef; + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ + + uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + + uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLSAI is selected as Clock Source SAI */ + + uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. + This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection. + This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ + + uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. + This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ + + uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection + This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ + + uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection + This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ + + uint32_t Usart3ClockSelection; /*!< USART3 clock source + This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ + + uint32_t Uart4ClockSelection; /*!< UART4 clock source + This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ + + uint32_t Uart5ClockSelection; /*!< UART5 clock source + This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ + + uint32_t Usart6ClockSelection; /*!< USART6 clock source + This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ + + uint32_t Uart7ClockSelection; /*!< UART7 clock source + This parameter can be a value of @ref RCCEx_UART7_Clock_Source */ + + uint32_t Uart8ClockSelection; /*!< UART8 clock source + This parameter can be a value of @ref RCCEx_UART8_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ + + uint32_t I2c2ClockSelection; /*!< I2C2 clock source + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ + + uint32_t I2c3ClockSelection; /*!< I2C3 clock source + This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ + + uint32_t I2c4ClockSelection; /*!< I2C4 clock source + This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ + + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source + This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ + + uint32_t CecClockSelection; /*!< CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + + uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC + This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ + + uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source + This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) + uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source + This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source + This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ + + uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source + This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +}RCC_PeriphCLKInitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection + * @{ + */ +#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U) +#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U) +#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U) +#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U) +#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U) +#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U) +#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U) +#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U) +#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U) +#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U) +#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U) +#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U) +#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U) +#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U) +#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U) +#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U) +#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U) +#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U) +#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U) +#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U) +#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U) +#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U) +#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @} + */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider + * @{ + */ +#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U) +#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U) +#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U) +#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U) +/** + * @} + */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider + * @{ + */ +#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U) +#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U) +#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U) +#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U) +/** + * @} + */ + +/** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR + * @{ + */ +#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U) +#define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0 +#define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1 +#define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR +/** + * @} + */ + +/** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source + * @{ + */ +#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U) +#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC + +/** + * @} + */ + +/** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source + * @{ + */ +#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) +#define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0 +#define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1 +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @} + */ + +/** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source + * @{ + */ +#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) +#define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0 +#define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1 +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @} + */ + +/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source + * @{ + */ +#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U) +#define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/ +/** + * @} + */ + +/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) +#define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0 +#define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1 +#define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL +/** + * @} + */ + +/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source + * @{ + */ +#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0 +#define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1 +#define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL +/** + * @} + */ + +/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source + * @{ + */ +#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0 +#define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1 +#define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL +/** + * @} + */ + +/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source + * @{ + */ +#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0 +#define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1 +#define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL +/** + * @} + */ + +/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source + * @{ + */ +#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0 +#define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1 +#define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL +/** + * @} + */ + +/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source + * @{ + */ +#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) +#define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0 +#define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1 +#define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL +/** + * @} + */ + +/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source + * @{ + */ +#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0 +#define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1 +#define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL +/** + * @} + */ + +/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source + * @{ + */ +#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0 +#define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1 +#define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL +/** + * @} + */ + +/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source + * @{ + */ +#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0 +#define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1 +/** + * @} + */ + +/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source + * @{ + */ +#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0 +#define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1 + +/** + * @} + */ + +/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source + * @{ + */ +#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0 +#define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1 +/** + * @} + */ + +/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source + * @{ + */ +#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0 +#define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1 +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 +#define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 +#define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL + +/** + * @} + */ + +/** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source + * @{ + */ +#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U) +#define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL +/** + * @} + */ + +/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection + * @{ + */ +#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U) +#define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE +/** + * @} + */ + +/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source + * @{ + */ +#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U) +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL +/** + * @} + */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +/** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source + * @{ + */ +#define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U) +#define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL +/** + * @} + */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source + * @{ + */ +#define RCC_DFSDM1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) +#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL +/** + * @} + */ + +/** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source + * @{ + */ +#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U) +#define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL +/** + * @} + */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source + * @{ + */ +#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U) +#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL) +/** + * @} + */ +#endif /* STM32F769xx || STM32F779xx */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable + * @brief Enables or disables the AHB/APB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +/** @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) +#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN)) +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) +#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) +#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) +#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) +#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +/** + * @brief Enable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETH_CLK_ENABLE() do { \ + __HAL_RCC_ETHMAC_CLK_ENABLE(); \ + __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ + __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ + } while(0) +/** + * @brief Disable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) +#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) +#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) +#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) +#define __HAL_RCC_ETH_CLK_DISABLE() do { \ + __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ + __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ + __HAL_RCC_ETHMAC_CLK_DISABLE(); \ + } while(0) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ + UNUSED(tmpreg); \ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + } while(0) + +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) +#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) +#endif /* STM32F756x || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_AES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ + +/** @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) +#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) + +/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_RTC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) +#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) +#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN)) +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F750xx */ + +/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F730xx */ + +#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM11_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F769xx || STM32F779xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_MDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_OTGPHYC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + +#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) +#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) +#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN)) +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) +#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) +#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) +#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) +#define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_OTGPHYC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_OTGPHYCEN)) +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB/APB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +/** @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) +#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET) +#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) +#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) +#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) +#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) +#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET) +#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) +#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) +#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +/** + * @brief Enable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) +#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ + __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ + __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) + +/** + * @brief Disable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) +#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ + __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ + __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Get the enable or disable status of the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) + +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) +#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) + +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) +#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) +#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) +#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) +#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET) +#define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** @brief Get the enable or disable status of the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) + +#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) +#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) + +/** @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) +#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) +#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) +#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) +#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET) + +#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) +#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET) +#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +/** @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) +#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) +#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) +#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) +#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) +#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) +#define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_OTGPHYC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) != RESET) +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) +#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) +#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) +#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) +#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) +#define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_OTGPHYC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) == RESET) +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset + * @brief Forces or releases AHB/APB peripheral reset. + * @{ + */ + +/** @brief Force or release AHB1 peripheral reset. + */ +#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) +#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) + +#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) +#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) +#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) +#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) + +#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) +#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) +#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Force or release AHB2 peripheral reset. + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST)) +#define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) +#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) +#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) +#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) +#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) +#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Force or release AHB3 peripheral reset + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) +#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) + +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) +#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) +#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) + +/** @brief Force or release APB1 peripheral reset. + */ +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) +#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) +#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) +#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST)) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) + +#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) +#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST)) +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Force or release APB2 peripheral reset. + */ +#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) +#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) +#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST)) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) +#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) +#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) +#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_OTGPHYC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_OTGPHYCRST)) +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + +#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) +#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) +#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST)) +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) +#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) +#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) +#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_OTGPHYC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_OTGPHYCRST)) +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) +#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) +#endif /* STM32F769xx || STM32F779xx */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST)) +#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) +#define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST)) +#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) +#define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @} + */ + +/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable + * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + */ +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) +#define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) +#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) + +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) +#define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) +#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) +#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) + +#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) +#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN)) +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) + +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) + +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) +#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ + +/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) + +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) + +/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN)) +#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) +#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) + +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) +#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) +#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN)) +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) +#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) +#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN)) +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) +#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)|| defined (STM32F750xx) +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) +#define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN)) +#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) +#define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) +#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +/** + * @} + */ + +/** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +/** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET) +#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET) +#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET) +#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET) +#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET) +#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET) + +#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET) +#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET) +#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET) +#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET) +#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET) +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET) +#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET) +#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET) +#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET) +#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET) + +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET) +#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET) +#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET) +#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET) +#define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET) +#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET) + +#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET) + +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET) +#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET) + +#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET) +#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) != RESET) +#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) == RESET) +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ + +/** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET) +#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET) + +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET) + +/** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET) +#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET) +#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET) +#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET) +#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET) +#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET) + +#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET) +#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET) +#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET) +#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET) +#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET) +#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET) +#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET) +#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET) +#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET) +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) +#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET) +#define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET) +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET) +#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET) +#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET) +#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET) +#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET) +#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET) +#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET) +#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET) +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) +#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET) +#define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) +#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +/** + * @} + */ + +/*------------------------------- PLL Configuration --------------------------*/ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * @param __RCC_PLLSource__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on + * the System clock frequency. + * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * @param __PLLR__ specifies the division factor for DSI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ + (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ + ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ + ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) +#else +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * @param __RCC_PLLSource__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on + * the System clock frequency. + * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ + (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \ + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ + ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/*---------------------------------------------------------------------------------------------*/ + +/** @brief Macro to configure the Timers clocks prescalers + * @param __PRESC__ specifies the Timers clocks prescalers selection + * This parameter can be one of the following values: + * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1 or 2, + * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to + * division by 4 or more. + * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, + * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding + * to division by 8 or more. + */ +#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\ + RCC->DCKCFGR1 |= (__PRESC__); \ + }while(0) + +/** @brief Macros to Enable or Disable the PLLISAI. + * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION)) +#define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION)) + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +/** @brief Macro to configure the PLLSAI clock multiplication and division factors. + * @note This function must be used only when the PLLSAI is disabled. + * @note PLLSAI clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks + * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. + * @param __PLLSAIQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__) \ + (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ + ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)) + +/** @brief Macro to configure the PLLI2S clock multiplication and division factors. + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API) + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLI2SQ__ specifies the division factor for SAI clock. + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)) +#else +/** @brief Macro to configure the PLLSAI clock multiplication and division factors. + * @note This function must be used only when the PLLSAI is disabled. + * @note PLLSAI clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks + * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. + * @param __PLLSAIQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @param __PLLSAIR__ specifies the division factor for LTDC clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ + (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ + ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ + ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)) + +/** @brief Macro to configure the PLLI2S clock multiplication and division factors. + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API) + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLI2SP__ specifies the division factor for SPDDIF-RX clock. + * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider. + * @param __PLLI2SQ__ specifies the division factor for SAI clock. + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SP__) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ + ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ + +/** @brief Macro to configure the SAI clock Divider coming from PLLI2S. + * @note This function must be called before enabling the PLLI2S. + * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock . + * This parameter must be a number between 1 and 32. + * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ + */ +#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1)) + +/** @brief Macro to configure the SAI clock Divider coming from PLLSAI. + * @note This function must be called before enabling the PLLSAI. + * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . + * This parameter must be a number between Min_Data = 1 and Max_Data = 32. + * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ + */ +#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. + * @note This function must be called before enabling the PLLSAI. + * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . + * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR. + * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ + */ +#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Macro to configure SAI1 clock source selection. + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin + * used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI1 clock. + * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + */ +#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__)) + +/** @brief Macro to get the SAI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin + * used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI1 clock. + * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + */ +#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL))) + +/** @brief Macro to configure SAI2 clock source selection. + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI2 clock source. + * This parameter can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin + * used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI2 clock. + * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + */ +#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__)) + + +/** @brief Macro to get the SAI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin + * used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI2 clock. + * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + */ +#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL))) + + +/** @brief Enable PLLSAI_RDY interrupt. + */ +#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) + +/** @brief Disable PLLSAI_RDY interrupt. + */ +#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) + +/** @brief Clear the PLLSAI RDY interrupt pending bits. + */ +#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) + +/** @brief Check the PLLSAI RDY interrupt has occurred or not. + * @retval The new state (TRUE or FALSE). + */ +#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) + +/** @brief Check PLLSAI RDY flag is set or not. + * @retval The new state (TRUE or FALSE). + */ +#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) + +/** @brief Macro to Get I2S clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. + * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source + */ +#define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)) + +/** @brief Macro to configure the I2C1 clock (I2C1CLK). + * + * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock + */ +#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) + +/** @brief Macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock + */ +#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL))) + +/** @brief Macro to configure the I2C2 clock (I2C2CLK). + * + * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock + */ +#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) + +/** @brief Macro to get the I2C2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock + */ +#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL))) + +/** @brief Macro to configure the I2C3 clock (I2C3CLK). + * + * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock + */ +#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) + +/** @brief macro to get the I2C3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock + */ +#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL))) + +/** @brief Macro to configure the I2C4 clock (I2C4CLK). + * + * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock + */ +#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) + +/** @brief macro to get the I2C4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock + */ +#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL))) + +/** @brief Macro to configure the USART1 clock (USART1CLK). + * + * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock + */ +#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) + +/** @brief macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL))) + +/** @brief Macro to configure the USART2 clock (USART2CLK). + * + * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock + */ +#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) + +/** @brief macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock + */ +#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL))) + +/** @brief Macro to configure the USART3 clock (USART3CLK). + * + * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock + */ +#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) + +/** @brief macro to get the USART3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock + */ +#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL))) + + /** @brief Macro to configure the UART4 clock (UART4CLK). + * + * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock + */ +#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) + +/** @brief macro to get the UART4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock + */ +#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL))) + + /** @brief Macro to configure the UART5 clock (UART5CLK). + * + * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock + */ +#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) + +/** @brief macro to get the UART5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock + */ +#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL))) + + /** @brief Macro to configure the USART6 clock (USART6CLK). + * + * @param __USART6_CLKSOURCE__ specifies the USART6 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock + */ +#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) + +/** @brief macro to get the USART6 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock + */ +#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL))) + + /** @brief Macro to configure the UART7 clock (UART7CLK). + * + * @param __UART7_CLKSOURCE__ specifies the UART7 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock + */ +#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__)) + +/** @brief macro to get the UART7 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock + */ +#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL))) + +/** @brief Macro to configure the UART8 clock (UART8CLK). + * + * @param __UART8_CLKSOURCE__ specifies the UART8 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock + */ +#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__)) + +/** @brief macro to get the UART8 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock + */ +#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL))) + +/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). + * + * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) + +/** @brief macro to get the LPTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))) + +/** @brief Macro to configure the CEC clock (CECCLK). + * + * @param __CEC_CLKSOURCE__ specifies the CEC clock source. + * This parameter can be one of the following values: + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + * @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock + */ +#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) + +/** @brief macro to get the CEC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock + */ +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))) + +/** @brief Macro to configure the CLK48 source (CLK48CLK). + * + * @param __CLK48_SOURCE__ specifies the CLK48 clock source. + * This parameter can be one of the following values: + * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source + * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source + */ +#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__)) + +/** @brief macro to get the CLK48 source. + * @retval The clock source can be one of the following values: + * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source + * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source + */ +#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))) + +/** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK). + * + * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock + * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock + */ +#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) + +/** @brief macro to get the SDMMC1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock + * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock + */ +#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +/** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK). + * @param __SDMMC2_CLKSOURCE__ specifies the SDMMC2 clock source. + * This parameter can be one of the following values: + * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock + * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock + */ +#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__)) + +/** @brief macro to get the SDMMC2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock + * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock + */ +#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL))) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @brief Macro to configure the DFSDM1 clock + * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM clock + * @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock + */ +#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM1 clock + * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock + */ +#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL))) + +/** @brief Macro to configure the DFSDM1 Audio clock + * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 Audio clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock + */ +#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM1 Audio clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock + */ +#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL))) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +/** @brief Macro to configure the DSI clock. + * @param __DSI_CLKSOURCE__ specifies the DSI clock source. + * This parameter can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__))) + +/** @brief Macro to Get the DSI clock. + * @retval The clock source can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL)) +#endif /* STM32F769xx || STM32F779xx */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ +#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined(STM32F745xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined (STM32F765xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#endif /* STM32F746xx || STM32F756xx || STM32F750xx */ +#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ + ((VALUE) == RCC_PLLI2SP_DIV4) ||\ + ((VALUE) == RCC_PLLI2SP_DIV6) ||\ + ((VALUE) == RCC_PLLI2SP_DIV8)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) +#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + +#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ + ((VALUE) == RCC_PLLSAIP_DIV4) ||\ + ((VALUE) == RCC_PLLSAIP_DIV6) ||\ + ((VALUE) == RCC_PLLSAIP_DIV8)) +#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) +#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + +#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) + +#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) + +#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ + ((VALUE) == RCC_PLLSAIDIVR_4) ||\ + ((VALUE) == RCC_PLLSAIDIVR_8) ||\ + ((VALUE) == RCC_PLLSAIDIVR_16)) +#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) + +#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48)) + +#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_CECCLKSOURCE_LSE)) +#define IS_RCC_USART1CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) + +#define IS_RCC_USART2CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) +#define IS_RCC_USART3CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) + +#define IS_RCC_UART4CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) + +#define IS_RCC_UART5CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) + +#define IS_RCC_USART6CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_HSI)) + +#define IS_RCC_UART7CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_HSI)) + +#define IS_RCC_UART8CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_HSI)) +#define IS_RCC_I2C1CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ + ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)) +#define IS_RCC_I2C2CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ + ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)) + +#define IS_RCC_I2C3CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ + ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)) +#define IS_RCC_I2C4CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ + ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)) +#define IS_RCC_LPTIM1CLK(SOURCE) \ + (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) +#define IS_RCC_CLK48SOURCE(SOURCE) \ + (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \ + ((SOURCE) == RCC_CLK48SOURCE_PLL)) +#define IS_RCC_TIMPRES(VALUE) \ + (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ + ((VALUE) == RCC_TIMPRES_ACTIVATED)) + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F745xx) ||\ + defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F730xx) || defined (STM32F750xx) +#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)) +#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx || STM32F750xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + +#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC)) + +#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) + +#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ + ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK)) + +#define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ + ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_RCC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h new file mode 100644 index 0000000..6a29ae5 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h @@ -0,0 +1,2166 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_TIM_H +#define STM32F7xx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + * @note Advanced timers provide TRGO2 internal line which is redirected + * to the ADC + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + uint32_t LockLevel; /*!< TIM Lock level + This parameter can be a value of @ref TIM_Lock_level */ + uint32_t DeadTime; /*!< TIM dead Time + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint32_t BreakState; /*!< TIM Break State + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + uint32_t BreakPolarity; /*!< TIM Break input polarity + This parameter can be a value of @ref TIM_Break_Polarity */ + uint32_t BreakFilter; /*!< Specifies the break input filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t Break2State; /*!< TIM Break2 State + This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + uint32_t Break2Polarity; /*!< TIM Break2 input polarity + This parameter can be a value of @ref TIM_Break2_Polarity */ + uint32_t Break2Filter; /*!< TIM break2 input filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ + HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ + void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + + ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +#define TIM_DMABASE_OR 0x00000014U +#define TIM_DMABASE_CCMR3 0x00000015U +#define TIM_DMABASE_CCR5 0x00000016U +#define TIM_DMABASE_CCR6 0x00000017U +#if defined(TIM_BREAK_INPUT_SUPPORT) +#define TIM_DMABASE_AF1 0x00000018U +#define TIM_DMABASE_AF2 0x00000019U +#endif /* TIM_BREAK_INPUT_SUPPORT */ +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ +#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ +#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ +#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable + * @{ + */ +#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ +#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity + * @{ + */ +#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ +#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event + (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 + * @{ + */ +#define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) + * @{ + */ +#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ +#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ +#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ +#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ +#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_System TIM Break System + * @{ + */ +#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ +#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ +#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */ +#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder +mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) \ + ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ + ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ + ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @arg TIM_CHANNEL_5: get capture/compare 5 register value + * @arg TIM_CHANNEL_6: get capture/compare 6 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ + ((__HANDLE__)->Instance->CCR6)) + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) + +#if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE) +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_OR) || \ + ((__BASE__) == TIM_DMABASE_CCMR3) || \ + ((__BASE__) == TIM_DMABASE_CCR5) || \ + ((__BASE__) == TIM_DMABASE_CCR6) || \ + ((__BASE__) == TIM_DMABASE_AF1) || \ + ((__BASE__) == TIM_DMABASE_AF2)) +#else +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_OR) || \ + ((__BASE__) == TIM_DMABASE_CCMR3) || \ + ((__BASE__) == TIM_DMABASE_CCR5) || \ + ((__BASE__) == TIM_DMABASE_CCR6)) +#endif /* TIM_AF1_BKINE && TIM_AF1_BKINE */ + +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_5) || \ + ((__CHANNEL__) == TIM_CHANNEL_6) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3)) + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) + +#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ + ((__STATE__) == TIM_BREAK2_DISABLE)) + +#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) + +#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ + ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO2_OC1) || \ + ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ + ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ + ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) + +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) + +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32f7xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ + uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions +* @{ +*/ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** +* @} +*/ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_TIM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h new file mode 100644 index 0000000..598f5c6 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h @@ -0,0 +1,355 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_TIM_EX_H +#define STM32F7xx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; +#if defined(TIM_BREAK_INPUT_SUPPORT) + +/** + * @brief TIM Break/Break2 input configuration + */ +typedef struct +{ + uint32_t Source; /*!< Specifies the source of the timer break input. + This parameter can be a value of @ref TIMEx_Break_Input_Source */ + uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ + uint32_t Polarity; /*!< Specifies the break input source polarity. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity + Not relevant when analog watchdog output of the DFSDM1 used as break input source */ +} +TIMEx_BreakInputConfigTypeDef; + +#endif /* TIM_BREAK_INPUT_SUPPORT */ +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +#define TIM_TIM2_TIM8_TRGO (0x00000000U) +#define TIM_TIM2_ETH_PTP (0x00000400U) +#define TIM_TIM2_USBFS_SOF (0x00000800U) +#define TIM_TIM2_USBHS_SOF (0x00000C00U) +#define TIM_TIM5_GPIO (0x00000000U) +#define TIM_TIM5_LSI (0x00000040U) +#define TIM_TIM5_LSE (0x00000080U) +#define TIM_TIM5_RTC (0x000000C0U) +#define TIM_TIM11_GPIO (0x00000000U) +#define TIM_TIM11_SPDIFRX (0x00000001U) +#define TIM_TIM11_HSE (0x00000002U) +#define TIM_TIM11_MCO1 (0x00000003U) +/** + * @} + */ +#if defined(TIM_BREAK_INPUT_SUPPORT) + +/** @defgroup TIMEx_Break_Input TIM Extended Break input + * @{ + */ +#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */ +#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source + * @{ + */ +#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin */ +#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling + * @{ + */ +#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity + * @{ + */ +#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */ +#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */ +/** + * @} + */ +#endif /* TIM_BREAK_INPUT_SUPPORT */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ +#define IS_TIM_REMAP(__TIM_REMAP__) (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\ + ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP) ||\ + ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\ + ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\ + ((__TIM_REMAP__) == TIM_TIM5_GPIO) ||\ + ((__TIM_REMAP__) == TIM_TIM5_LSI) ||\ + ((__TIM_REMAP__) == TIM_TIM5_LSE) ||\ + ((__TIM_REMAP__) == TIM_TIM5_RTC) ||\ + ((__TIM_REMAP__) == TIM_TIM11_GPIO) ||\ + ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX) ||\ + ((__TIM_REMAP__) == TIM_TIM11_HSE) ||\ + ((__TIM_REMAP__) == TIM_TIM11_MCO1)) +#if defined(TIM_BREAK_INPUT_SUPPORT) + +#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ + ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) + +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM)) + +#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ + ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) + +#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) +#endif /* TIM_BREAK_INPUT_SUPPORT */ + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +#if defined(TIM_BREAK_INPUT_SUPPORT) +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); +#endif /* TIM_BREAK_INPUT_SUPPORT */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F7xx_HAL_TIM_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h new file mode 100644 index 0000000..4209206 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h @@ -0,0 +1,1429 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_uart.h + * @author MCD Application Team + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_UART_H +#define STM32F7xx_HAL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ck) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ck) / ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ck) / ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck is the UART input clock */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ + + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + + +} UART_InitTypeDef; + +/** + * @brief UART Advanced Features initialization structure definition + */ +typedef struct +{ + uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several + Advanced Features may be initialized at the same time . + This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */ + + uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. + This parameter can be a value of @ref UART_Tx_Inv. */ + + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. + This parameter can be a value of @ref UART_Rx_Inv. */ + + uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic + vs negative/inverted logic). + This parameter can be a value of @ref UART_Data_Inv. */ + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + This parameter can be a value of @ref UART_Rx_Tx_Swap. */ + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + This parameter can be a value of @ref UART_Overrun_Disable. */ + + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ + + uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. + This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ + + uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate + detection is carried out. + This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + This parameter can be a value of @ref UART_MSB_First. */ +} UART_AdvFeatureInitTypeDef; + + + +/** + * @brief HAL UART State definition + * @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition). + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef uint32_t HAL_UART_StateTypeDef; + +/** + * @brief UART clock sources definition + */ +typedef enum +{ + UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ +} UART_ClockSourceTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct __UART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< UART registers base address */ + + UART_InitTypeDef Init; /*!< UART communication parameters */ + + UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ + + uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< UART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< UART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + + uint16_t Mask; /*!< UART Rx RDR register mask */ + + + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ + void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ + HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported Constants + * @{ + */ + +/** @defgroup UART_State_Definition UART State Code Definition + * @{ + */ +#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ +#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup UART_Error_Definition UART Error Definition + * @{ + */ +#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ +#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ +#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ +#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE 0x00000000U /*!< No parity */ +#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ +#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ +#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ +#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ +#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method + * @{ + */ +#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ +#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ +/** + * @} + */ + +/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut + * @{ + */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART receiver timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART receiver timeout enable */ +/** + * @} + */ + +/** @defgroup UART_LIN UART Local Interconnection Network mode + * @{ + */ +#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ +#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ +/** + * @} + */ + +/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ +#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ +/** + * @} + */ + +/** @defgroup UART_DMA_Tx UART DMA Tx + * @{ + */ +#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ +#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ +/** + * @} + */ + +/** @defgroup UART_DMA_Rx UART DMA Rx + * @{ + */ +#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ +#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ +/** + * @} + */ + +/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection + * @{ + */ +#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ +#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_Methods UART WakeUp Methods + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ +#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ +/** + * @} + */ + +/** @defgroup UART_Request_Parameters UART Request Parameters + * @{ + */ +#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ +#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ +#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ +#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type + * @{ + */ +#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ +#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ +#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ +#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ +#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ +/** + * @} + */ + +/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ +#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion + * @{ + */ +#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ +#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap + * @{ + */ +#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ +#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ +/** + * @} + */ + +/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable + * @{ + */ +#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ +/** + * @} + */ + +/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ +/** + * @} + */ + +/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error + * @{ + */ +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ +#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ +/** + * @} + */ + +/** @defgroup UART_MSB_First UART Advanced Feature MSB First + * @{ + */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */ +/** + * @} + */ + +/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable + * @{ + */ +#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ +#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ +/** + * @} + */ + +/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register + * @{ + */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ +/** + * @} + */ + +/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity + * @{ + */ +#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ +#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask + * @{ + */ +#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ +/** + * @} + */ + +/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value + * @{ + */ +#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ +/** + * @} + */ + +/** @defgroup UART_Flags UART Status Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ +#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ +#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ +#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ +#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ +#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ +#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ +#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ +#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ +#define UART_FLAG_TXE USART_ISR_TXE /*!< UART transmit data register empty */ +#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ +#define UART_FLAG_RXNE USART_ISR_RXNE /*!< UART read data register not empty */ +#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ +#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ +#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ +#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ +#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UART Interrupts Definition + * Elements values convention: 000ZZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZZ : Flag position in the ISR register(5bits) + * Elements values convention: 000000000XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * Elements values convention: 0000ZZZZ00000000b + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ + +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ + +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +/** + * @} + */ + +/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags + * @{ + */ +#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */ +#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ +#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ +#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Reset UART handle states. + * @param __HANDLE__ UART handle. + * @retval None + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + +/** @brief Flush the UART Data registers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0U) + +/** @brief Clear the specified UART pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the UART PE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) + +/** @brief Clear the UART FE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) + +/** @brief Clear the UART NE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) + +/** @brief Clear the UART ORE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) + +/** @brief Clear the UART IDLE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) + + +/** @brief Check whether the specified UART flag is set or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) + * @arg @ref UART_FLAG_SBKF Send Break flag + * @arg @ref UART_FLAG_CMF Character match flag + * @arg @ref UART_FLAG_BUSY Busy flag + * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag + * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag + * @arg @ref UART_FLAG_CTS CTS Change flag + * @arg @ref UART_FLAG_LBDF LIN Break detection flag + * @arg @ref UART_FLAG_TXE Transmit data register empty flag + * @arg @ref UART_FLAG_TC Transmission Complete flag + * @arg @ref UART_FLAG_RXNE Receive data register not empty flag + * @arg @ref UART_FLAG_IDLE Idle Line detection flag + * @arg @ref UART_FLAG_ORE Overrun Error flag + * @arg @ref UART_FLAG_NE Noise Error flag + * @arg @ref UART_FLAG_FE Framing Error flag + * @arg @ref UART_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Enable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK)))) + + +/** @brief Disable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Check whether the specified UART interrupt has occurred or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt to check. + * This parameter can be one of the following values: + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) + +/** @brief Check whether the specified UART interrupt source is enabled or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) + +/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @retval None + */ +#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific UART request flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __REQ__ specifies the request flag to set + * This parameter can be one of the following values: + * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request + * @arg @ref UART_SENDBREAK_REQUEST Send Break Request + * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request + * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request + * @retval None + */ +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) + +/** @brief Enable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** @brief Enable CTS flow control. + * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0U) + +/** @brief Disable CTS flow control. + * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0U) + +/** @brief Enable RTS flow control. + * @note This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0U) + +/** @brief Disable RTS flow control. + * @note This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0U) +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ + + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @retval Division result + */ +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @retval Division result + */ +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__)) + + +/** @brief Check UART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) + */ +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 27000001U) + +/** @brief Check UART assertion time. + * @param __TIME__ 5-bit value assertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** @brief Check UART deassertion time. + * @param __TIME__ 5-bit value deassertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** + * @brief Ensure that UART frame number of stop bits is valid. + * @param __STOPBITS__ UART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ + ((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_1_5) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + + +/** + * @brief Ensure that UART frame parity is valid. + * @param __PARITY__ UART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ + ((__PARITY__) == UART_PARITY_EVEN) || \ + ((__PARITY__) == UART_PARITY_ODD)) + +/** + * @brief Ensure that UART hardware flow control is valid. + * @param __CONTROL__ UART hardware flow control. + * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) + */ +#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + +/** + * @brief Ensure that UART communication mode is valid. + * @param __MODE__ UART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) + +/** + * @brief Ensure that UART state is valid. + * @param __STATE__ UART state. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ + ((__STATE__) == UART_STATE_ENABLE)) + +/** + * @brief Ensure that UART oversampling is valid. + * @param __SAMPLING__ UART oversampling. + * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) + */ +#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == UART_OVERSAMPLING_8)) + +/** + * @brief Ensure that UART frame sampling is valid. + * @param __ONEBIT__ UART frame sampling. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) + +/** + * @brief Ensure that UART auto Baud rate detection mode is valid. + * @param __MODE__ UART auto Baud rate detection mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) + +/** + * @brief Ensure that UART receiver timeout setting is valid. + * @param __TIMEOUT__ UART receiver timeout setting. + * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) + */ +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** + * @brief Ensure that UART LIN state is valid. + * @param __LIN__ UART LIN state. + * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) + */ +#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ + ((__LIN__) == UART_LIN_ENABLE)) + +/** + * @brief Ensure that UART LIN break detection length is valid. + * @param __LENGTH__ UART LIN break detection length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) + +/** + * @brief Ensure that UART DMA TX state is valid. + * @param __DMATX__ UART DMA TX state. + * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) + */ +#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ + ((__DMATX__) == UART_DMA_TX_ENABLE)) + +/** + * @brief Ensure that UART DMA RX state is valid. + * @param __DMARX__ UART DMA RX state. + * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) + */ +#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ + ((__DMARX__) == UART_DMA_RX_ENABLE)) + +/** + * @brief Ensure that UART half-duplex state is valid. + * @param __HDSEL__ UART half-duplex state. + * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) + */ +#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ + ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) + +/** + * @brief Ensure that UART wake-up method is valid. + * @param __WAKEUP__ UART wake-up method . + * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) + */ +#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) + +/** + * @brief Ensure that UART request parameter is valid. + * @param __PARAM__ UART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ + ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ + ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ + ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) + +/** + * @brief Ensure that UART advanced features initialization is valid. + * @param __INIT__ UART advanced features initialization. + * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) + */ +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) + +/** + * @brief Ensure that UART frame TX inversion setting is valid. + * @param __TXINV__ UART frame TX inversion setting. + * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ + ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX inversion setting is valid. + * @param __RXINV__ UART frame RX inversion setting. + * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ + ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) + +/** + * @brief Ensure that UART frame data inversion setting is valid. + * @param __DATAINV__ UART frame data inversion setting. + * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ + ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX/TX pins swap setting is valid. + * @param __SWAP__ UART frame RX/TX pins swap setting. + * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) + */ +#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ + ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) + +/** + * @brief Ensure that UART frame overrun setting is valid. + * @param __OVERRUN__ UART frame overrun setting. + * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) + */ +#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ + ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) + +/** + * @brief Ensure that UART auto Baud rate state is valid. + * @param __AUTOBAUDRATE__ UART auto Baud rate state. + * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) + +/** + * @brief Ensure that UART DMA enabling or disabling on error setting is valid. + * @param __DMA__ UART DMA enabling or disabling on error setting. + * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) + */ +#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) + +/** + * @brief Ensure that UART frame MSB first setting is valid. + * @param __MSBFIRST__ UART frame MSB first setting. + * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) + */ +#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) + +/** + * @brief Ensure that UART mute mode state is valid. + * @param __MUTE__ UART mute mode state. + * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) + */ +#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ + ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) + +/** + * @brief Ensure that UART driver enable polarity is valid. + * @param __POLARITY__ UART driver enable polarity. + * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) + */ +#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ + ((__POLARITY__) == UART_DE_POLARITY_LOW)) + + +/** + * @} + */ + +/* Include UART HAL Extended module */ +#include "stm32f7xx_hal_uart_ex.h" + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -----------------------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_UART_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h new file mode 100644 index 0000000..a5907f5 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h @@ -0,0 +1,393 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_uart_ex.h + * @author MCD Application Team + * @brief Header file of UART HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_UART_EX_H +#define STM32F7xx_HAL_UART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup UARTEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Types UARTEx Exported Types + * @{ + */ + + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants + * @{ + */ + +/** @defgroup UARTEx_Word_Length UARTEx Word Length + * @{ + */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +/** + * @} + */ + +/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length + * @{ + */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup UARTEx_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group2 + * @{ + */ + + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UARTEx_Private_Macros UARTEx Private Macros + * @{ + */ + +/** @brief Report the UART clock source. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + switch(__HAL_RCC_GET_UART4_SOURCE()) \ + { \ + case RCC_UART4CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART4CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART4CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART4CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if ((__HANDLE__)->Instance == UART5) \ + { \ + switch(__HAL_RCC_GET_UART5_SOURCE()) \ + { \ + case RCC_UART5CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART5CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART5CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART5CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ + case RCC_USART6CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART6CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART6CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART6CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if ((__HANDLE__)->Instance == UART7) \ + { \ + switch(__HAL_RCC_GET_UART7_SOURCE()) \ + { \ + case RCC_UART7CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART7CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART7CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART7CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if ((__HANDLE__)->Instance == UART8) \ + { \ + switch(__HAL_RCC_GET_UART8_SOURCE()) \ + { \ + case RCC_UART8CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART8CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART8CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART8CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) + +/** @brief Report the UART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @note If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define UART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU ; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ +} while(0U) + +/** + * @brief Ensure that UART frame length is valid. + * @param __LENGTH__ UART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ + ((__LENGTH__) == UART_WORDLENGTH_8B) || \ + ((__LENGTH__) == UART_WORDLENGTH_9B)) + +/** + * @brief Ensure that UART wake-up address length is valid. + * @param __ADDRESS__ UART wake-up address length. + * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) + */ +#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ + ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) + + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_UART_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c new file mode 100644 index 0000000..81a39d7 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c @@ -0,0 +1,608 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup HAL_Private_Constants + * @{ + */ +/** + * @brief STM32F7xx HAL Driver version number V1.2.7 + */ +#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ +#define __STM32F7xx_HAL_VERSION_SUB2 (0x07) /*!< [15:8] sub2 version */ +#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\ + |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\ + |(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\ + |(__STM32F7xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Exported variables ---------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface the NVIC allocation and initial clock + configuration. It initializes the systick also when timeout is needed + and the backup domain when enabled. + (+) De-Initializes common part of the HAL. + (+) Configure the time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief This function is used to initialize the HAL Library; it must be the first + * instruction to be executed in the main program (before to call any other + * HAL function), it performs the following: + * Configure the Flash prefetch, and instruction cache through ART accelerator. + * Configures the SysTick to generate an interrupt each 1 millisecond, + * which is clocked by the HSI (at this stage, the clock is not yet + * configured and thus the system is running from the internal HSI at 16 MHz). + * Set NVIC Group Priority to 4. + * Calls the HAL_MspInit() callback function defined in user file + * "stm32f7xx_hal_msp.c" to do the global low level hardware initialization + * + * @note SysTick is used as time base for the HAL_Delay() function, the application + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Configure Instruction cache through ART accelerator */ +#if (ART_ACCLERATOR_ENABLE != 0) + __HAL_FLASH_ART_ENABLE(); +#endif /* ART_ACCLERATOR_ENABLE */ + + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the systick. + * This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_AHB1_FORCE_RESET(); + __HAL_RCC_AHB1_RELEASE_RESET(); + + __HAL_RCC_AHB2_FORCE_RESET(); + __HAL_RCC_AHB2_RELEASE_RESET(); + + __HAL_RCC_AHB3_FORCE_RESET(); + __HAL_RCC_AHB3_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + { + return HAL_ERROR; + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval Status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval tick period in Hz + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32F7xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return((DBGMCU->IDCODE) >> 16U); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return(READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Enables the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @retval None + */ +void HAL_EnableCompensationCell(void) +{ + SYSCFG->CMPCR |= SYSCFG_CMPCR_CMP_PD; +} + +/** + * @brief Power-down the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @retval None + */ +void HAL_DisableCompensationCell(void) +{ + SYSCFG->CMPCR &= (uint32_t)~((uint32_t)SYSCFG_CMPCR_CMP_PD); +} + +/** + * @brief Enables the FMC Memory Mapping Swapping. + * + * @note SDRAM is accessible at 0x60000000 + * and NOR/RAM is accessible at 0xC0000000 + * + * @retval None + */ +void HAL_EnableFMCMemorySwapping(void) +{ + SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0; +} + +/** + * @brief Disables the FMC Memory Mapping Swapping + * + * @note SDRAM is accessible at 0xC0000000 (default mapping) + * and NOR/RAM is accessible at 0x60000000 (default mapping) + * + * @retval None + */ +void HAL_DisableFMCMemorySwapping(void) +{ + + SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC); +} + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** +* @brief Enable the Internal FLASH Bank Swapping. +* +* @note This function can be used only for STM32F77xx/STM32F76xx devices. +* +* @note Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) +* and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM)) +* +* @retval None +*/ +void HAL_EnableMemorySwappingBank(void) +{ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB); +} + +/** +* @brief Disable the Internal FLASH Bank Swapping. +* +* @note This function can be used only for STM32F77xx/STM32F76xx devices. +* +* @note The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) +* and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM)) +* +* @retval None +*/ +void HAL_DisableMemorySwappingBank(void) +{ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB); +} +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c new file mode 100644 index 0000000..b0a816a --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c @@ -0,0 +1,505 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M4 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() + function according to the following table. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + (#) please refer to programming manual for details in how to configure priority. + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest preemption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32f7xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Sets the priority grouping field (preemption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @param PreemptPriority The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup = 0x00; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** + * @brief Disables the MPU + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0; +} + +/** + * @brief Enables the MPU + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + +/** + * @brief Initializes and configures the Region and the memory to be protected. + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + if ((MPU_Init->Enable) != RESET) + { + /* Check the parameters */ + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + } + else + { + MPU->RBAR = 0x00; + MPU->RASR = 0x00; + } +} +#endif /* __MPU_PRESENT */ + +/** + * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @param PriorityGroup the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c new file mode 100644 index 0000000..6bd09e1 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c @@ -0,0 +1,1307 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Stream + (except for internal SRAM/FLASH memories: no initialization is + necessary) please refer to Reference manual for connection between peripherals + and DMA requests. + + (#) For a given Stream, program the required configuration through the following parameters: + Transfer Direction, Source and Destination data formats, + Circular, Normal or peripheral flow control mode, Stream Priority level, + Source and Destination Increment mode, FIFO mode and its Threshold (if needed), + Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. + + -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros: + __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE(). + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred. + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + (+) Use HAL_DMA_Abort() function to abort the current transfer. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Select Callbacks functions using HAL_DMA_RegisterCallback() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. In this + case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). + [..] + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort_IT() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + + -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is + possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set + Half-Word data size for the peripheral to access its data register and set Word data size + for the Memory to gain in access time. Each two half words will be packed and written in + a single access to a Word in the Memory). + + -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source + and Destination. In this case the Peripheral Data Size will be applied to both Source + and Destination. + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register */ + __IO uint32_t Reserved0; + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */ +} DMA_Base_Registers; + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Constants + * @{ + */ + #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)5) /* 5 ms */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Stream source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Stream priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and create the associated handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp = 0U; + uint32_t tickstart = HAL_GetTick(); + DMA_Base_Registers *regs; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); + /* Check the memory burst, peripheral burst and FIFO threshold parameters only + when FIFO mode is enabled */ + if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) + { + assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); + assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); + assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); + } + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + + /* Get the CR register value */ + tmp = hdma->Instance->CR; + + /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ + tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); + + /* Prepare the DMA Stream configuration */ + tmp |= hdma->Init.Channel | hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get memory burst and peripheral burst */ + tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; + } + + /* Write to DMA Stream CR register */ + hdma->Instance->CR = tmp; + + /* Get the FCR register value */ + tmp = hdma->Instance->FCR; + + /* Clear Direct mode and FIFO threshold bits */ + tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + + /* Prepare the DMA Stream FIFO configuration */ + tmp |= hdma->Init.FIFOMode; + + /* The FIFO threshold is not used when the FIFO mode is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get the FIFO threshold */ + tmp |= hdma->Init.FIFOThreshold; + + /* Check compatibility between FIFO threshold level and size of the memory burst */ + /* for INCR4, INCR8, INCR16 bursts */ + if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) + { + if (DMA_CheckFifoParam(hdma) != HAL_OK) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_ERROR; + } + } + } + + /* Write to DMA Stream FCR */ + hdma->Instance->FCR = tmp; + + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the DMA peripheral + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + DMA_Base_Registers *regs; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the DMA peripheral state */ + if(hdma->State == HAL_DMA_STATE_BUSY) + { + /* Return error status */ + return HAL_BUSY; + } + + /* Check the parameters */ + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Streamx */ + __HAL_DMA_DISABLE(hdma); + + /* Reset DMA Streamx control register */ + hdma->Instance->CR = 0U; + + /* Reset DMA Streamx number of data to transfer register */ + hdma->Instance->NDTR = 0U; + + /* Reset DMA Streamx peripheral address register */ + hdma->Instance->PAR = 0U; + + /* Reset DMA Streamx memory 0 address register */ + hdma->Instance->M0AR = 0U; + + /* Reset DMA Streamx memory 1 address register */ + hdma->Instance->M1AR = 0U; + + /* Reset DMA Streamx FIFO control register */ + hdma->Instance->FCR = (uint32_t)0x00000021U; + + /* Get DMA steam Base Address */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Reset the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Reset the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Starts the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Enable Common interrupts*/ + hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; + hdma->Instance->FCR |= DMA_IT_FE; + + if(hdma->XferHalfCpltCallback != NULL) + { + hdma->Instance->CR |= DMA_IT_HT; + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + + return status; +} + +/** + * @brief Aborts the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * + * @note After disabling a DMA Stream, a check for wait until the DMA Stream is + * effectively disabled is added. If a Stream is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Stream will be effectively disabled only after the transfer of + * this single data is finished. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + uint32_t tickstart = HAL_GetTick(); + + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Disable all the transfer interrupts */ + hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + hdma->Instance->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + } + return HAL_OK; +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + return HAL_ERROR; + } + else + { + /* Set Abort State */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + } + + return HAL_OK; +} + +/** + * @brief Polling for transfer complete. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CompleteLevel Specifies the DMA level complete. + * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead. + * This model could be used for debug purpose. + * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t mask_cpltlevel; + uint32_t tickstart = HAL_GetTick(); + uint32_t tmpisr; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* No transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode and double buffering mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + } + else + { + /* Half Transfer Complete flag */ + mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + } + + regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + tmpisr = regs->ISR; + + while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET)) + { + /* Check for the Timeout (Not applicable in circular mode)*/ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_TIMEOUT; + } + } + + /* Get the ISR register value */ + tmpisr = regs->ISR; + + if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + + /* Clear the transfer error flag */ + regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; + } + + if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + + /* Clear the FIFO error flag */ + regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; + } + + if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + + /* Clear the Direct Mode error flag */ + regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; + } + } + + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + { + HAL_DMA_Abort(hdma); + + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_READY; + + return HAL_ERROR; + } + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + hdma->State = HAL_DMA_STATE_READY; + } + else + { + /* Clear the half transfer flag */ + regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; + } + + return status; +} + +/** + * @brief Handles DMA interrupt request. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t tmpisr; + __IO uint32_t count = 0; + uint32_t timeout = SystemCoreClock / 9600; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + tmpisr = regs->ISR; + + /* Transfer Error Interrupt management ***************************************/ + if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) + { + /* Disable the transfer error interrupt */ + hdma->Instance->CR &= ~(DMA_IT_TE); + + /* Clear the transfer error flag */ + regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + } + } + /* FIFO Error Interrupt management ******************************************/ + if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) + { + /* Clear the FIFO error flag */ + regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + } + } + /* Direct Mode Error Interrupt management ***********************************/ + if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) + { + /* Clear the direct mode error flag */ + regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + } + } + /* Half Transfer Complete Interrupt management ******************************/ + if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) + { + /* Clear the half transfer complete flag */ + regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + + /* Multi_Buffering mode enabled */ + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + { + /* Current memory buffer used is Memory 0 */ + if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) + { + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferM1HalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferM1HalfCpltCallback(hdma); + } + } + } + else + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) + { + /* Disable the half transfer interrupt */ + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + } + /* Transfer Complete Interrupt management ***********************************/ + if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) + { + /* Clear the transfer complete flag */ + regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + + if(HAL_DMA_STATE_ABORT == hdma->State) + { + /* Disable all the transfer interrupts */ + hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + hdma->Instance->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + return; + } + + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + { + /* Current memory buffer used is Memory 0 */ + if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) + { + if(hdma->XferM1CpltCallback != NULL) + { + /* Transfer complete Callback for memory1 */ + hdma->XferM1CpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete Callback for memory0 */ + hdma->XferCpltCallback(hdma); + } + } + } + /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ + else + { + if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) + { + /* Disable the transfer complete interrupt */ + hdma->Instance->CR &= ~(DMA_IT_TC); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + } + + /* manage error case */ + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + { + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + do + { + if (++count > timeout) + { + break; + } + } + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } +} + +/** + * @brief Register callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifer + * a DMA_HandleTypeDef structure as parameter. + * @param pCallback pointer to private callbacsk function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) +{ + + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA state. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + return hdma->State; +} + +/** + * @brief Return the DMA error code + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear DBM bit */ + hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + hdma->Instance->NDTR = DataLength; + + /* Memory to Peripheral */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + hdma->Instance->PAR = DstAddress; + + /* Configure DMA Stream source address */ + hdma->Instance->M0AR = SrcAddress; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Stream source address */ + hdma->Instance->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + hdma->Instance->M0AR = DstAddress; + } +} + +/** + * @brief Returns the DMA Stream base address depending on stream number + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval Stream base address + */ +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ + uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; + + /* lookup table for necessary bitshift of flags within status registers */ + static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; + hdma->StreamIndex = flagBitshiftOffset[stream_number]; + + if (stream_number > 3U) + { + /* return pointer to HISR and HIFCR */ + hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); + } + else + { + /* return pointer to LISR and LIFCR */ + hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); + } + + return hdma->StreamBaseAddress; +} + +/** + * @brief Check compatibility between FIFO threshold level and size of the memory burst + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp = hdma->Init.FIFOThreshold; + + /* Memory Data size equal to Byte */ + if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_HALFFULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_FULL: + break; + default: + break; + } + } + + /* Memory Data size equal to Half-Word */ + else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + case DMA_FIFO_THRESHOLD_HALFFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_FULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + default: + break; + } + } + + /* Memory Data size equal to Word */ + else + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_HALFFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + case DMA_FIFO_THRESHOLD_FULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + default: + break; + } + } + + return status; +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c new file mode 100644 index 0000000..0873354 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c @@ -0,0 +1,310 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following + * functionalities of the DMA Extension peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DMA Extension HAL driver can be used as follows: + (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function + for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode. + + -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. + -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default. + -@- In Multi (Double) buffer mode, it is possible to update the base address for + the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private Constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMAEx_Private_Functions + * @{ + */ + +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + + +/** @addtogroup DMAEx_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and + Start MultiBuffer DMA transfer + (+) Configure the source, destination address and data length and + Start MultiBuffer DMA transfer with interrupt + (+) Change on the fly the memory0 or memory1 address. + +@endverbatim + * @{ + */ + + +/** + * @brief Starts the multi_buffer DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + } + else + { + /* Process Locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Enable the double buffer mode */ + hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + hdma->Instance->M1AR = SecondMemAddress; + + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Return error status */ + status = HAL_BUSY; + } + } + return status; +} + +/** + * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Enable the Double buffer mode */ + hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + hdma->Instance->M1AR = SecondMemAddress; + + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + + /* Enable Common interrupts*/ + hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; + hdma->Instance->FCR |= DMA_IT_FE; + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR |= DMA_IT_HT; + } + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Change the memory0 or memory1 address on the fly. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param Address The new address + * @param memory the memory to be changed, This parameter can be one of + * the following values: + * MEMORY0 / + * MEMORY1 + * @note The MEMORY0 address can be changed only when the current transfer use + * MEMORY1 and the MEMORY1 address can be changed only when the current + * transfer use MEMORY0. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory) +{ + if(memory == MEMORY0) + { + /* change the memory0 address */ + hdma->Instance->M0AR = Address; + } + else + { + /* change the memory1 address */ + hdma->Instance->M1AR = Address; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMAEx_Private_Functions + * @{ + */ + +/** + * @brief Set the DMA Transfer parameter. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Configure DMA Stream data length */ + hdma->Instance->NDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + hdma->Instance->PAR = DstAddress; + + /* Configure DMA Stream source address */ + hdma->Instance->M0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + hdma->Instance->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + hdma->Instance->M0AR = DstAddress; + } +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c new file mode 100644 index 0000000..07e5353 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c @@ -0,0 +1,451 @@ +/** + ****************************************************************************** + * @file stm32F7xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two different + interrupts pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" +#include "stm32f7xx_hal_exti.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rule: + * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + * of bounds [0,3] in following API : + * HAL_EXTI_SetConfigLine + * HAL_EXTI_GetConfigLine + * HAL_EXTI_ClearConfigLine + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* Clear EXTI line configuration */ + EXTI->IMR &= ~pExtiConfig->Line; + EXTI->EMR &= ~pExtiConfig->Line; + + /* Select the Mode for the selected external interrupts */ + regval = (uint32_t)EXTI_BASE; + regval += pExtiConfig->Mode; + *(__IO uint32_t *) regval |= pExtiConfig->Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~pExtiConfig->Line; + EXTI->FTSR &= ~pExtiConfig->Line; + + /* Select the trigger for the selected external interrupts */ + if (pExtiConfig->Trigger == EXTI_TRIGGER_RISING_FALLING) + { + /* Rising Falling edge */ + EXTI->RTSR |= pExtiConfig->Line; + EXTI->FTSR |= pExtiConfig->Line; + } + else + { + regval = (uint32_t)EXTI_BASE; + regval += pExtiConfig->Trigger; + *(__IO uint32_t *) regval |= pExtiConfig->Line; + } + return HAL_OK; +} + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* Get EXTI mode to configiguration structure */ + if ((EXTI->IMR & hexti->Line) == hexti->Line) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else if ((EXTI->EMR & hexti->Line) == hexti->Line) + { + pExtiConfig->Mode = EXTI_MODE_EVENT; + } + else + { + /* No MODE selected */ + pExtiConfig->Mode = 0x0Bu; + } + + /* Get EXTI Trigger to configiguration structure */ + if ((EXTI->RTSR & hexti->Line) == hexti->Line) + { + if ((EXTI->FTSR & hexti->Line) == hexti->Line) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING_FALLING; + } + else + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + } + else if ((EXTI->FTSR & hexti->Line) == hexti->Line) + { + pExtiConfig->Trigger = EXTI_TRIGGER_FALLING; + } + else + { + /* No Trigger selected */ + pExtiConfig->Trigger = 0x00u; + } + + return HAL_OK; +} + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +{ + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* 1] Clear interrupt mode */ + EXTI->IMR = (EXTI->IMR & ~hexti->Line); + + /* 2] Clear event mode */ + EXTI->EMR = (EXTI->EMR & ~hexti->Line); + + /* 3] Clear triggers */ + EXTI->RTSR = (EXTI->RTSR & ~hexti->Line); + EXTI->FTSR = (EXTI->FTSR & ~hexti->Line); + + return HAL_OK; +} + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + + /* Get pending bit */ + regaddr = (&EXTI->PR); + regval = (*regaddr & hexti->Line); + + if (regval != 0x00u) + { + /* Clear pending bit */ + *regaddr = hexti->Line; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t regval; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Get pending bit */ + regaddr = &EXTI->PR; + + /* return 1 if bit is set else 0 */ + regval = ((*regaddr & hexti->Line) >> POSITION_VAL(hexti->Line)); + + return regval; +} + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Clear Pending bit */ + EXTI->PR = hexti->Line; +} + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +{ + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + EXTI->SWIER = hexti->Line; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c new file mode 100644 index 0000000..27fa98c --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c @@ -0,0 +1,817 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral Errors functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch and cache lines. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Prefetch on I-Code + (+) 64 cache lines of 128 bits on I-Code + (+) 8 cache lines of 128 bits on D-Code + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32F7xx devices. + + (#) FLASH Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Program functions: byte, half word, word and double word + (++) There Two modes of programming : + (+++) Polling mode using HAL_FLASH_Program() function + (+++) Interrupt mode using HAL_FLASH_Program_IT() function + + (#) Interrupts and flags management functions : + (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + (++) Wait for last FLASH operation according to its status + (++) Get error flag status by calling HAL_SetErrorCode() + [..] + In addition to these functions, this driver includes a set of macros allowing + to handle the following operations: + (+) Set the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the Instruction cache and the Data cache + (+) Reset the Instruction cache and the Data cache + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + [..] + (@) For any Flash memory program operation (erase or program), the CPU clock frequency + (HCLK) must be at least 1MHz. + (@) The contents of the Flash memory are not guaranteed if a device reset occurs during + a Flash memory operation. + (@) Any attempt to read the Flash memory while it is being written or erased, causes the + bus to stall. Read operations are processed correctly once the program operation has + completed. This means that code or data fetches cannot be performed while a write/erase + operation is ongoing. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define SECTOR_MASK ((uint32_t)0xFFFFFF07U) +#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +/* Variable used for Erase sectors under interruption */ +FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions + * @{ + */ +/* Program operations */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); +static void FLASH_Program_Word(uint32_t Address, uint32_t Data); +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); +static void FLASH_Program_Byte(uint32_t Address, uint8_t Data); +static void FLASH_SetErrorCode(void); + +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim + =============================================================================== + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + +@endverbatim + * @{ + */ + +/** + * @brief Program byte, halfword, word or double word at a specified address + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + switch(TypeProgram) + { + case FLASH_TYPEPROGRAM_BYTE : + { + /*Program byte (8-bit) at a specified address.*/ + FLASH_Program_Byte(Address, (uint8_t) Data); + break; + } + + case FLASH_TYPEPROGRAM_HALFWORD : + { + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(Address, (uint16_t) Data); + break; + } + + case FLASH_TYPEPROGRAM_WORD : + { + /*Program word (32-bit) at a specified address.*/ + FLASH_Program_Word(Address, (uint32_t) Data); + break; + } + + case FLASH_TYPEPROGRAM_DOUBLEWORD : + { + /*Program double word (64-bit) at a specified address.*/ + FLASH_Program_DoubleWord(Address, Data); + break; + } + default : + break; + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Program byte, halfword, word or double word at a specified address with interrupt enabled. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Enable End of FLASH Operation interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); + + /* Enable Error source interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\ + FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); + + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; + pFlash.Address = Address; + + switch(TypeProgram) + { + case FLASH_TYPEPROGRAM_BYTE : + { + /*Program byte (8-bit) at a specified address.*/ + FLASH_Program_Byte(Address, (uint8_t) Data); + break; + } + + case FLASH_TYPEPROGRAM_HALFWORD : + { + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(Address, (uint16_t) Data); + break; + } + + case FLASH_TYPEPROGRAM_WORD : + { + /*Program word (32-bit) at a specified address.*/ + FLASH_Program_Word(Address, (uint32_t) Data); + break; + } + + case FLASH_TYPEPROGRAM_DOUBLEWORD : + { + /*Program double word (64-bit) at a specified address.*/ + FLASH_Program_DoubleWord(Address, Data); + break; + } + default : + break; + } + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t temp = 0; + + /* If the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + + /* If the erase operation is completed, disable the SER Bit */ + FLASH->CR &= (~FLASH_CR_SER); + FLASH->CR &= SECTOR_MASK; + + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= (~FLASH_MER_BIT); + + /* Check FLASH End of Operation flag */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + + switch (pFlash.ProcedureOnGoing) + { + case FLASH_PROC_SECTERASE : + { + /* Nb of sector to erased can be decreased */ + pFlash.NbSectorsToErase--; + + /* Check if there are still sectors to erase */ + if(pFlash.NbSectorsToErase != 0) + { + temp = pFlash.Sector; + /* Indicate user which sector has been erased */ + HAL_FLASH_EndOfOperationCallback(temp); + + /* Increment sector number */ + temp = ++pFlash.Sector; + FLASH_Erase_Sector(temp, pFlash.VoltageForErase); + } + else + { + /* No more sectors to Erase, user callback can be called.*/ + /* Reset Sector and stop Erase sectors procedure */ + pFlash.Sector = temp = 0xFFFFFFFFU; + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(temp); + /* Sector Erase procedure is completed */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + break; + } + + case FLASH_PROC_MASSERASE : + { + /* MassErase ended. Return the selected bank : in this product we don't have Banks */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(0); + /* MAss Erase procedure is completed */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + break; + } + + case FLASH_PROC_PROGRAM : + { + /*Program ended. Return the selected address*/ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + /* Programming procedure is completed */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + break; + } + default : + break; + } + } + + /* Check FLASH operation error flags */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET) + { + switch (pFlash.ProcedureOnGoing) + { + case FLASH_PROC_SECTERASE : + { + /* return the faulty sector */ + temp = pFlash.Sector; + pFlash.Sector = 0xFFFFFFFFU; + break; + } + case FLASH_PROC_MASSERASE : + { + /* No return in case of Mass Erase */ + temp = 0; + break; + } + case FLASH_PROC_PROGRAM : + { + /*return the faulty address*/ + temp = pFlash.Address; + break; + } + default : + break; + } + /*Save the Error code*/ + FLASH_SetErrorCode(); + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(temp); + + /*Stop the procedure ongoing */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + + if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { + /* Disable End of FLASH Operation interrupt */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP); + + /* Disable Error source interrupt */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that + * all the selected sectors have been erased) + * - Program : Address which was selected for data program + * - Mass Erase : No return value expected + * @retval None + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that + * all the selected sectors have been erased) + * - Program : Address which was selected for data program + * - Mass Erase : No return value expected + * @retval None + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Locks the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Registers access */ + FLASH->CR |= FLASH_CR_LOCK; + + return HAL_OK; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) + { + /* Authorizes the Option Byte register programming */ + FLASH->OPTKEYR = FLASH_OPT_KEY1; + FLASH->OPTKEYR = FLASH_OPT_KEY2; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; + + return HAL_OK; +} + +/** + * @brief Launch the option byte loading. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the OPTSTRT bit in OPTCR register */ + FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT; + + /* Wait for last operation to be completed */ + return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode: The returned value can be: + * @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag + * @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag + * @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag + * @arg FLASH_ERROR_WRP: FLASH Write protected error flag + * @arg FLASH_ERROR_OPERATION: FLASH operation Error flag + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operationtimeout + * @retval HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Clear Error Code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET) + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + /* If there is an error flag set */ + return HAL_OK; + +} + +/** + * @brief Program a double word (64-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.6V and an External Vpp is present. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; + FLASH->CR |= FLASH_CR_PG; + + /* Program the double-word */ + *(__IO uint32_t*)Address = (uint32_t)Data; + *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32); + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + + +/** + * @brief Program word (32-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.6V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_Word(uint32_t Address, uint32_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint32_t*)Address = Data; + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Program a half-word (16-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.6V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_HALF_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint16_t*)Address = Data; + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); + +} + +/** + * @brief Program byte (8-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.6V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_Byte(uint32_t Address, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_BYTE; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint8_t*)Address = Data; + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Set the specific FLASH error flag. + * @retval None + */ +static void FLASH_SetErrorCode(void) +{ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION; + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP; + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ERSERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS; + } + +#if defined (FLASH_OPTCR2_PCROP) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; + } +#endif /* FLASH_OPTCR2_PCROP */ + + /* Clear error programming flags */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c new file mode 100644 index 0000000..33314d4 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c @@ -0,0 +1,1122 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the FLASH extension peripheral: + * + Extended programming operations functions + * + @verbatim + ============================================================================== + ##### Flash Extension features ##### + ============================================================================== + + [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx + devices contains the following additional features + + (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write + capability (RWW) + (+) Dual bank memory organization + (+) Dual boot mode + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32F7xx devices. It includes + (#) FLASH Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Erase function: Erase sector, erase all sectors + (++) There are two modes of erase : + (+++) Polling Mode using HAL_FLASHEx_Erase() + (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + + (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to : + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Set the BOR level + (++) Program the user Option Bytes + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Constants + * @{ + */ +#define SECTOR_MASK 0xFFFFFF07U +#define FLASH_TIMEOUT_VALUE 50000U/* 50 s */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ +/* Option bytes control */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector); +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector); +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level); +static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level); +static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address); +static uint32_t FLASH_OB_GetUser(void); +static uint32_t FLASH_OB_GetWRP(void); +static uint8_t FLASH_OB_GetRDP(void); +static uint32_t FLASH_OB_GetBOR(void); +static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption); + +#if defined (FLASH_OPTCR_nDBANK) +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \ + uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot); +#else +static void FLASH_MassErase(uint8_t VoltageRange); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby); +#endif /* FLASH_OPTCR_nDBANK */ + +#if defined (FLASH_OPTCR2_PCROP) +static HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector); +static HAL_StatusTypeDef FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp); +static uint32_t FLASH_OB_GetPCROP(void); +static uint32_t FLASH_OB_GetPCROPRDP(void); +#endif /* FLASH_OPTCR2_PCROP */ + +extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### Extended programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extension FLASH + programming operations Operations. + +@endverbatim + * @{ + */ +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] SectorError pointer to variable that + * contains the configuration information on faulty sector in case of error + * (0xFFFFFFFF means that all the sectors have been correctly erased) + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t index = 0; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /*Initialization of SectorError variable*/ + *SectorError = 0xFFFFFFFFU; + + if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ +#if defined (FLASH_OPTCR_nDBANK) + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); +#else + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); +#endif /* FLASH_OPTCR_nDBANK */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= (~FLASH_MER_BIT); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); + + /* Erase by sector by sector to be done*/ + for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++) + { + FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the SER Bit and SNB Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); + + if(status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty sector*/ + *SectorError = index; + break; + } + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Enable End of FLASH Operation interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); + + /* Enable Error source interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\ + FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); + + if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; +#if defined (FLASH_OPTCR_nDBANK) + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); +#else + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); +#endif /* FLASH_OPTCR_nDBANK */ + } + else + { + /* Erase by sector to be done*/ + + /* Check the parameters */ + assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); + + pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE; + pFlash.NbSectorsToErase = pEraseInit->NbSectors; + pFlash.Sector = pEraseInit->Sector; + pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange; + + /*Erase 1st sector and wait for IT*/ + FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange); + } + + return status; +} + +/** + * @brief Program option bytes + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Write protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + if(pOBInit->WRPState == OB_WRPSTATE_ENABLE) + { + /*Enable of Write protection on the selected Sector*/ + status = FLASH_OB_EnableWRP(pOBInit->WRPSector); + } + else + { + /*Disable of Write protection on the selected Sector*/ + status = FLASH_OB_DisableWRP(pOBInit->WRPSector); + } + } + + /* Read protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + { + status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); + } + + /* USER configuration */ + if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + { +#if defined (FLASH_OPTCR_nDBANK) + status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, + pOBInit->USERConfig & OB_IWDG_SW, + pOBInit->USERConfig & OB_STOP_NO_RST, + pOBInit->USERConfig & OB_STDBY_NO_RST, + pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE, + pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE, + pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK, + pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE); +#else + status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, + pOBInit->USERConfig & OB_IWDG_SW, + pOBInit->USERConfig & OB_STOP_NO_RST, + pOBInit->USERConfig & OB_STDBY_NO_RST, + pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE, + pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE); +#endif /* FLASH_OPTCR_nDBANK */ + } + + /* BOR Level configuration */ + if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) + { + status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel); + } + + /* Boot 0 Address configuration */ + if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0) + { + status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0); + } + + /* Boot 1 Address configuration */ + if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1) + { + status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1); + } + +#if defined (FLASH_OPTCR2_PCROP) + /* PCROP configuration */ + if((pOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) + { + status = FLASH_OB_PCROP_Config(pOBInit->PCROPSector); + } + + /* PCROP_RDP configuration */ + if((pOBInit->OptionType & OPTIONBYTE_PCROP_RDP) == OPTIONBYTE_PCROP_RDP) + { + status = FLASH_OB_PCROP_RDP_Config(pOBInit->PCROPRdp); + } +#endif /* FLASH_OPTCR2_PCROP */ + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1; + + /*Get WRP*/ + pOBInit->WRPSector = FLASH_OB_GetWRP(); + + /*Get RDP Level*/ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /*Get USER*/ + pOBInit->USERConfig = FLASH_OB_GetUser(); + + /*Get BOR Level*/ + pOBInit->BORLevel = FLASH_OB_GetBOR(); + + /*Get Boot Address when Boot pin = 0 */ + pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0); + + /*Get Boot Address when Boot pin = 1 */ + pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1); + +#if defined (FLASH_OPTCR2_PCROP) + /*Get PCROP Sectors */ + pOBInit->PCROPSector = FLASH_OB_GetPCROP(); + + /*Get PCROP_RDP Value */ + pOBInit->PCROPRdp = FLASH_OB_GetPCROPRDP(); +#endif /* FLASH_OPTCR2_PCROP */ +} +/** + * @} + */ + +#if defined (FLASH_OPTCR_nDBANK) +/** + * @brief Full erase of FLASH memory sectors + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * + * @retval HAL Status + */ +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_VOLTAGERANGE(VoltageRange)); + assert_param(IS_FLASH_BANK(Banks)); + + /* if the previous operation is completed, proceed to erase all sectors */ + FLASH->CR &= CR_PSIZE_MASK; + if(Banks == FLASH_BANK_BOTH) + { + /* bank1 & bank2 will be erased*/ + FLASH->CR |= FLASH_MER_BIT; + } + else if(Banks == FLASH_BANK_2) + { + /*Only bank2 will be erased*/ + FLASH->CR |= FLASH_CR_MER2; + } + else + { + /*Only bank1 will be erased*/ + FLASH->CR |= FLASH_CR_MER1; + } + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8); + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Erase the specified FLASH memory sector + * @param Sector FLASH sector to erase + * The value of this parameter depend on device used within the same series + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval None + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == FLASH_VOLTAGE_RANGE_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + + /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */ + if(Sector > FLASH_SECTOR_11) + { + Sector += 4; + } + + /* If the previous operation is completed, proceed to erase the sector */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); + FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); + FLASH->CR |= FLASH_CR_STRT; + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval uint32_t FLASH Write Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000)); +} + +/** + * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param Wwdg Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_WWDG_SW: Software WWDG selected + * @arg OB_WWDG_HW: Hardware WWDG selected + * @param Iwdg Selects the WWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param Stop Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NO_RST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param Stdby Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @param Iwdgstop Independent watchdog counter freeze in Stop mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP + * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP + * @param Iwdgstdby Independent watchdog counter freeze in standby mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY + * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY + * @param NDBank Flash Single Bank mode enabled. + * This parameter can be one of the following values: + * @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank) + * @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode) + * @param NDBoot Flash Dual boot mode disable. + * This parameter can be one of the following values: + * @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot + * @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot + + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \ + uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot) +{ + uint32_t useroptionmask = 0x00; + uint32_t useroptionvalue = 0x00; + + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WWDG_SOURCE(Wwdg)); + assert_param(IS_OB_IWDG_SOURCE(Iwdg)); + assert_param(IS_OB_STOP_SOURCE(Stop)); + assert_param(IS_OB_STDBY_SOURCE(Stdby)); + assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); + assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); + assert_param(IS_OB_NDBANK(NDBank)); + assert_param(IS_OB_NDBOOT(NDBoot)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \ + FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \ + FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK); + + useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank); + + /* Update User Option Byte */ + MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue); + } + + return status; +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), + * nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31). + */ +static uint32_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U)); +} +#else + +/** + * @brief Full erase of FLASH memory sectors + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval HAL Status + */ +static void FLASH_MassErase(uint8_t VoltageRange) +{ + /* Check the parameters */ + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + /* if the previous operation is completed, proceed to erase all sectors */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_CR_MER; + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8); + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Erase the specified FLASH memory sector + * @param Sector FLASH sector to erase + * The value of this parameter depend on device used within the same series + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval None + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == FLASH_VOLTAGE_RANGE_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + + /* If the previous operation is completed, proceed to erase the sector */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + FLASH->CR &= SECTOR_MASK; + FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); + FLASH->CR |= FLASH_CR_STRT; + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval uint32_t FLASH Write Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return ((uint32_t)(FLASH->OPTCR & 0x00FF0000)); +} + +/** + * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param Wwdg Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_WWDG_SW: Software WWDG selected + * @arg OB_WWDG_HW: Hardware WWDG selected + * @param Iwdg Selects the WWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param Stop Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NO_RST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param Stdby Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @param Iwdgstop Independent watchdog counter freeze in Stop mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP + * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP + * @param Iwdgstdby Independent watchdog counter freeze in standby mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY + * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby) +{ + uint32_t useroptionmask = 0x00; + uint32_t useroptionvalue = 0x00; + + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WWDG_SOURCE(Wwdg)); + assert_param(IS_OB_IWDG_SOURCE(Iwdg)); + assert_param(IS_OB_STOP_SOURCE(Stop)); + assert_param(IS_OB_STDBY_SOURCE(Stdby)); + assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); + assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \ + FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY); + + useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby); + + /* Update User Option Byte */ + MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue); + } + + return status; + +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), + * nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31). + */ +static uint32_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return ((uint32_t)(FLASH->OPTCR & 0xC00000F0U)); +} +#endif /* FLASH_OPTCR_nDBANK */ + +/** + * @brief Enable the write protection of the desired bank1 or bank2 sectors + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM7 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WRPSector specifies the sector(s) to be write protected. + * This parameter can be one of the following values: + * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices) + * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices) + * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices) + * @arg OB_WRP_SECTOR_All + * + * @retval HAL FLASH State + */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /*Write protection enabled on sectors */ + FLASH->OPTCR &= (~WRPSector); + } + + return status; +} + +/** + * @brief Disable the write protection of the desired bank1 or bank 2 sectors + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WRPSector specifies the sector(s) to be write protected. + * This parameter can be one of the following values: + * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices) + * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices) + * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices) + * @arg OB_WRP_Sector_All + * + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Write protection disabled on sectors */ + FLASH->OPTCR |= (WRPSector); + } + + return status; +} + +/** + * @brief Set the read protection level. + * @param Level specifies the read protection level. + * This parameter can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + * + * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(Level)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level; + } + + return status; +} + +/** + * @brief Set the BOR Level. + * @param Level specifies the Option Bytes BOR Reset Level. + * This parameter can be one of the following values: + * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level) +{ + /* Check the parameters */ + assert_param(IS_OB_BOR_LEVEL(Level)); + + /* Set the BOR Level */ + MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level); + + return HAL_OK; + +} + +/** + * @brief Configure Boot base address. + * + * @param BootOption specifies Boot base address depending from Boot pin = 0 or pin = 1 + * This parameter can be one of the following values: + * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 + * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 + * @param Address specifies Boot base address + * This parameter can be one of the following values: + * @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) + * @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) + * @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000) + * @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000) + * @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000) + * @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000) + * @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_BOOT_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + if(BootOption == OPTIONBYTE_BOOTADDR_0) + { + MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address); + } + else + { + MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16)); + } + } + + return status; +} + +/** + * @brief Returns the FLASH Read Protection level. + * @retval FlagStatus FLASH ReadOut Protection Status: + * This parameter can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + */ +static uint8_t FLASH_OB_GetRDP(void) +{ + uint8_t readstatus = OB_RDP_LEVEL_0; + + if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0) + { + readstatus = OB_RDP_LEVEL_0; + } + else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2) + { + readstatus = OB_RDP_LEVEL_2; + } + else + { + readstatus = OB_RDP_LEVEL_1; + } + + return readstatus; +} + +/** + * @brief Returns the FLASH BOR level. + * @retval uint32_t The FLASH BOR level: + * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V + */ +static uint32_t FLASH_OB_GetBOR(void) +{ + /* Return the FLASH BOR level */ + return ((uint32_t)(FLASH->OPTCR & 0x0C)); +} + +/** + * @brief Configure Boot base address. + * + * @param BootOption specifies Boot base address depending from Boot pin = 0 or pin = 1 + * This parameter can be one of the following values: + * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 + * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 + * + * @retval uint32_t Boot Base Address: + * - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) + * - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) + * - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000) + * - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000) + * - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000) + * - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000) + * - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) + */ +static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption) +{ + uint32_t Address = 0; + + /* Return the Boot base Address */ + if(BootOption == OPTIONBYTE_BOOTADDR_0) + { + Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0; + } + else + { + Address = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16); + } + + return Address; +} + +#if defined (FLASH_OPTCR2_PCROP) +/** + * @brief Set the PCROP protection for sectors. + * @param PCROPSector specifies the sector(s) to be PCROP protected. + * This parameter can be one of the following values: + * @arg OB_PCROP_SECTOR_x: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_7 + * @arg OB_PCROP_SECTOR_ALL + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_PCROP_SECTOR(PCROPSector)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP, PCROPSector); + } + + return status; +} + +/** + * @brief Set the PCROP_RDP value + * @param Pcrop_Rdp specifies the PCROP_RDP bit value. + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_PCROP_RDP_VALUE(Pcrop_Rdp)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP_RDP, Pcrop_Rdp); + } + + return status; +} + +/** + * @brief Return the FLASH PCROP Protection Option Bytes value. + * @retval uint32_t FLASH PCROP Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetPCROP(void) +{ + /* Return the FLASH write protection Register value */ + return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP)); +} + +/** + * @brief Return the FLASH PCROP_RDP option byte value. + * @retval uint32_t FLASH PCROP_RDP option byte value + */ +static uint32_t FLASH_OB_GetPCROPRDP(void) +{ + /* Return the FLASH write protection Register value */ + return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP_RDP)); +} +#endif /* FLASH_OPTCR2_PCROP */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c new file mode 100644 index 0000000..ffc617d --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c @@ -0,0 +1,531 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each + port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software + in several modes: + (+) Input mode + (+) Analog mode + (+) Output mode + (+) Alternate function mode + (+) External interrupt/event lines + + [..] + During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + [..] + In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + [..] + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + [..] + The external interrupt/event controller consists of up to 23 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE ((uint32_t)0x00000003U) +#define EXTI_MODE ((uint32_t)0x10000000U) +#define GPIO_MODE_IT ((uint32_t)0x00010000U) +#define GPIO_MODE_EVT ((uint32_t)0x00020000U) +#define RISING_EDGE ((uint32_t)0x00100000U) +#define FALLING_EDGE ((uint32_t)0x00200000U) +#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U) + +#define GPIO_NUMBER ((uint32_t)16U) +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the GPIOs + to be ready for use. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00; + uint32_t ioposition = 0x00; + uint32_t iocurrent = 0x00; + uint32_t temp = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + for(position = 0; position < GPIO_NUMBER; position++) + { + /* Get the IO position */ + ioposition = ((uint32_t)0x01) << position; + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + + if(iocurrent == ioposition) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameter */ + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3]; + temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); + GPIOx->AFR[position >> 3] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODER0 << (position * 2)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + GPIOx->MODER = temp; + + /* In case of Output or Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + temp |= (GPIO_Init->Speed << (position * 2)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); + GPIOx->OTYPER = temp; + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + temp |= ((GPIO_Init->Pull) << (position * 2)); + GPIOx->PUPDR = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + temp = SYSCFG->EXTICR[position >> 2]; + temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + SYSCFG->EXTICR[position >> 2] = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + { + temp |= iocurrent; + } + EXTI->IMR = temp; + + temp = EXTI->EMR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + { + temp |= iocurrent; + } + EXTI->EMR = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + { + temp |= iocurrent; + } + EXTI->RTSR = temp; + + temp = EXTI->FTSR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + { + temp |= iocurrent; + } + EXTI->FTSR = temp; + } + } + } +} + +/** + * @brief De-initializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position; + uint32_t ioposition = 0x00; + uint32_t iocurrent = 0x00; + uint32_t tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Configure the port pins */ + for(position = 0; position < GPIO_NUMBER; position++) + { + /* Get the IO position */ + ioposition = ((uint32_t)0x01) << position; + /* Get the current IO position */ + iocurrent = (GPIO_Pin) & ioposition; + + if(iocurrent == ioposition) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + tmp = SYSCFG->EXTICR[position >> 2]; + tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); + if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)))) + { + /* Configure the External Interrupt or event for the current IO */ + tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); + SYSCFG->EXTICR[position >> 2] &= ~tmp; + + /* Clear EXTI line configuration */ + EXTI->IMR &= ~((uint32_t)iocurrent); + EXTI->EMR &= ~((uint32_t)iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~((uint32_t)iocurrent); + EXTI->FTSR &= ~((uint32_t)iocurrent); + } + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO Direction in Input Floating Mode */ + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + } + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read and Write + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Sets or clears the selected data port bit. + * + * @note This function uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if(PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; + } +} + +/** + * @brief Toggles the specified GPIO pins. + * @param GPIOx Where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin Specifies the pins to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; + } + else + { + GPIOx->BSRR = GPIO_Pin; + } +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F7 family + * @param GPIO_Pin specifies the port bit to be locked. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + + if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin Specifies the pins connected EXTI line + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callbacks. + * @param GPIO_Pin Specifies the pins connected EXTI line + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c new file mode 100644 index 0000000..775bff2 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c @@ -0,0 +1,6523 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx stream + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx stream + + (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, + Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition, an then permit a call the same master sequential interface + several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() + or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential + interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. + + (+) Differents sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() + or using @ref HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT() + or using @ref HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). + (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT() + or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT() + or using @ref HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + @ref HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + @ref HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + @ref HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + @ref HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + + Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). + + Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + + For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). + + By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() + or @ref HAL_I2C_Init() function. + + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup I2C_Private_Define I2C Private Define + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ +#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + +#define MAX_NBYTE_SIZE 255U +#define SlaveAddr_SHIFT 7U +#define SlaveAddr_MSK 0x06U + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + + +/* Private define to centralize the enable/disable of Interrupts */ +#define I2C_XFER_TX_IT (0x00000001U) +#define I2C_XFER_RX_IT (0x00000002U) +#define I2C_XFER_LISTEN_IT (0x00000004U) + +#define I2C_XFER_ERROR_IT (0x00000011U) +#define I2C_XFER_CPLT_IT (0x00000012U) +#define I2C_XFER_RELOAD_IT (0x00000012U) + +/* Private define Sequential Transfer Options default/reset value */ +#define I2C_NO_OPTION_FRAME (0xFFFF0000U) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +/* Private functions to handle IT transfer */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + +/* Private functions to handle IT transfer */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); + +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + +/* Private function to flush TXDR register */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + +/* Private function to handle start, restart or stop a transfer */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + hi2c->Instance->CR2 = (I2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Seq_Transmit_IT() + (++) HAL_I2C_Master_Seq_Receive_IT() + (++) HAL_I2C_Slave_Seq_Transmit_IT() + (++) HAL_I2C_Slave_Seq_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Seq_Transmit_DMA() + (++) HAL_I2C_Master_Seq_Receive_DMA() + (++) HAL_I2C_Slave_Seq_Transmit_DMA() + (++) HAL_I2C_Slave_Seq_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Wait until DIR flag is set Transmitter mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Normal use case for Transmitter mode */ + /* A NACK is generated to confirm the end of transfer */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + return HAL_ERROR; + } + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Wait until DIR flag is reset Receiver mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + do + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + + } + while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + } + + do + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +{ + uint32_t tickstart; + + __IO uint32_t I2C_Trials = 0UL; + + FlagStatus tmp1; + FlagStatus tmp2; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + do + { + /* Generate Start */ + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Check if the maximum allowed number of trials has been reached */ + if (I2C_Trials == Trials) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Increment Trials */ + I2C_Trials++; + } + while (I2C_Trials < Trials); + + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount < MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount < MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount < MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount < MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Abort DMA Xfer if any */ + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + if (hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Set State at HAL_I2C_STATE_ABORT */ + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + /* Get current IT Flags and IT sources value */ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C events treatment -------------------------------------*/ + if (hi2c->XferISR != NULL) + { + hi2c->XferISR(hi2c, itflags, itsources); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + uint32_t tmperror; + + /* I2C Bus error interrupt occurred ------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the Error Callback in case of Error detected */ + if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c, tmperror); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** +* @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. +* @retval I2C Error Code +*/ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t tmpITFlags = ITFlags; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + if (hi2c->XferCount > 0U) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + + if ((hi2c->XferCount == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Datas have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hi2c->XferCount > 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + else + { + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + } + else + { + /* Nothing to do */ + } + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t xfermode; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + + if (hi2c->XferCount != 0U) + { + /* Recover Slave address */ + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + xfermode = hi2c->XferOptions; + } + else + { + xfermode = I2C_AUTOEND_MODE; + } + } + + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t treatdmanack = 0U; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + { + /* Split check of hdmarx, for MISRA compliance */ + if (hi2c->hdmarx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) + { + if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) + { + treatdmanack = 1U; + } + } + } + + /* Split check of hdmatx, for MISRA compliance */ + if (hi2c->hdmatx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) + { + if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) + { + treatdmanack = 1U; + } + } + } + + if (treatdmanack == 1U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else + { + /* Only Clear NACK Flag, no DMA treatment is pending */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, ITFlags); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TC flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief I2C Address complete process callback. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint8_t transferdirection; + uint16_t slaveaddrcode; + uint16_t ownadd1code; + uint16_t ownadd2code; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + + /* In case of Listen state, need to inform upper layer of address match code event */ + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + transferdirection = I2C_GET_DIR(hi2c); + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + + /* If 10bits addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + { + slaveaddrcode = ownadd1code; + hi2c->AddrEventCount++; + if (hi2c->AddrEventCount == 2U) + { + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0U; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + slaveaddrcode = ownadd2code; + + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* Else clear address flag only */ + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief I2C Master sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Slave sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Master complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmperror; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Reset handle parameters */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = NULL; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Slave complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + uint32_t tmpITFlags = ITFlags; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + if (hi2c->hdmatx != NULL) + { + hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); + } + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + if (hi2c->hdmarx != NULL) + { + hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); + } + } + else + { + /* Do nothing */ + } + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + } + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */ + I2C_ITSlaveSeqCplt(hi2c); + + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Listen complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} + +/** + * @brief I2C interrupts error process. + * @param hi2c I2C handle. + * @param ErrorCode Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferCount = 0U; + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + + /* Disable Interrupts */ + if ((tmpstate == HAL_I2C_STATE_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = I2C_Slave_ISR_IT; + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* If state is an abort treatment on goind, don't change state */ + /* This change will be do later */ + if (hi2c->State != HAL_I2C_STATE_ABORT) + { + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + } + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = NULL; + } + + /* Abort DMA TX transfer if any */ + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + /* Abort DMA RX transfer if any */ + else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + else if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + { + hi2c->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + } +} + +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tmpoptions = hi2c->XferOptions; + + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + +/** + * @brief DMA I2C master receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + +/** + * @brief DMA I2C slave receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tmpoptions = hi2c->XferOptions; + + if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + uint32_t treatdmaerror = 0U; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + if (hi2c->hdmatx != NULL) + { + if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) + { + treatdmaerror = 1U; + } + } + + if (hi2c->hdmarx != NULL) + { + if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) + { + treatdmaerror = 1U; + } + } + + /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */ + if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U)) + { + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } +} + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Reset AbortCpltCallback */ + hi2c->hdmatx->XferAbortCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Check if come from abort from user */ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief This function handles I2C Communication Timeout. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag Specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + return HAL_OK; + } + else + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Wait until STOP Flag is reset */ + /* AutoEnd should be initiate after AF */ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hi2c I2C handle. + * @param DevAddress Specifies the slave address to be programmed. + * @param Size Specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_RELOAD_MODE Enable Reload mode . + * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. + * @param Request New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* update CR2 register */ + MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); +} + +/** + * @brief Manage the enabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + (hi2c->XferISR == I2C_Slave_ISR_DMA)) + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + } + else + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK, and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c new file mode 100644 index 0000000..1bde438 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c @@ -0,0 +1,258 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C Extended peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### I2C peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32F7xx + devices contains the following additional features + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + (+) Disable or enable Fast Mode Plus + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to: + (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_I2CEx_EnableFastModePlus() + (++) HAL_I2CEx_DisableFastModePlus() + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C Extended HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Analog noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure I2C Digital noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP) +/** + * @brief Enable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C4 parameter. + * @retval None + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C4 parameter. + * @retval None + */ +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus); +} + +#endif +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c new file mode 100644 index 0000000..51c4468 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c @@ -0,0 +1,599 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup PWR_Private_Constants + * @{ + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#define PVD_MODE_IT ((uint32_t)0x00010000U) +#define PVD_MODE_EVT ((uint32_t)0x00020000U) +#define PVD_RISING_EDGE ((uint32_t)0x00000001U) +#define PVD_FALLING_EDGE ((uint32_t)0x00000002U) +/** + * @} + */ + +/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask + * @{ + */ +#define PWR_EWUP_MASK ((uint32_t)0x00003F00) +/** + * @} + */ + +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() macro. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the HAL PWR peripheral registers to their default reset values. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); +} + +/** + * @brief Enables access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + /* Enable access to RTC and backup registers */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Disables access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + /* Disable access to RTC and backup registers */ + CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled. This is done through + __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. + (+) The PVD is stopped in Standby mode. + + *** Wake-up pin configuration *** + ================================ + [..] + (+) Wake-up pin is used to wake up the system from Standby mode. This pin is + forced in input pull-down configuration and is active on rising edges. + (+) There are up to 6 Wake-up pin in the STM32F7 devices family + + *** Low Power modes configuration *** + ===================================== + [..] + The devices feature 3 low-power modes: + (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running. + (+) Stop mode: all clocks are stopped, regulator running, regulator + in low power mode + (+) Standby mode: 1.2V domain powered off. + + *** Sleep mode *** + ================== + [..] + (+) Entry: + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI) + functions with + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + + -@@- The Regulator parameter is not used for the STM32F7 family + and is kept as parameter just to maintain compatibility with the + lower power families (STM32L). + (+) Exit: + Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + *** Stop mode *** + ================= + [..] + In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, + and the HSE RC oscillators are disabled. Internal SRAM and register contents + are preserved. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption In Stop mode, FLASH can be powered off before + entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function. + It can be switched on again by software after exiting the Stop mode using + the HAL_PWREx_DisableFlashPowerDown() function. + + (+) Entry: + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) + function with: + (++) Main regulator ON. + (++) Low Power regulator ON. + (+) Exit: + Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + + *** Standby mode *** + ==================== + [..] + (+) + The Standby mode allows to achieve the lowest power consumption. It is based + on the Cortex-M7 deep sleep mode, with the voltage regulator disabled. + The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and + the HSE oscillator are also switched off. SRAM and register contents are lost + except for the RTC registers, RTC backup registers, backup SRAM and Standby + circuitry. + + The voltage regulator is OFF. + + (++) Entry: + (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + (++) Exit: + (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC + wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + + (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wakeup event, a tamper event or a time-stamp event, without depending on + an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the Stop and Standby modes + + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. + + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to configure the RTC to detect the tamper or time stamp event using the + HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. + + (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to + configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration + * information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Enables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_EnablePVD(void) +{ + /* Enable the power voltage detector */ + SET_BIT(PWR->CR1, PWR_CR1_PVDE); +} + +/** + * @brief Disables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_DisablePVD(void) +{ + /* Disable the power voltage detector */ + CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE); +} + +/** + * @brief Enable the WakeUp PINx functionality. + * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable. + * This parameter can be one of the following legacy values, which sets the default polarity: + * detection on high level (rising edge): + * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 + * or one of the following value where the user can explicitly states the enabled pin and + * the chosen polarity + * @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW + * @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW + * @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW + * @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW + * @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW + * @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW + * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) +{ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); + + /* Enable wake-up pin */ + SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity)); + + /* Specifies the Wake-Up pin polarity for the event detection + (rising or falling edge) */ + MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06)); +} + +/** + * @brief Disables the WakeUp PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @arg PWR_WAKEUP_PIN2 + * @arg PWR_WAKEUP_PIN3 + * @arg PWR_WAKEUP_PIN4 + * @arg PWR_WAKEUP_PIN5 + * @arg PWR_WAKEUP_PIN6 + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + + CLEAR_BIT(PWR->CSR2, WakeUpPinx); +} + +/** + * @brief Enters Sleep mode. + * + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * + * @note In Sleep mode, the systick is stopped to avoid exit from this mode with + * systick interrupt when used as time base for Timeout + * + * @param Regulator Specifies the regulator state in SLEEP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON + * @note This parameter is not used for the STM32F7 family and is kept as parameter + * just to maintain compatibility with the lower power families. + * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Ensure that all instructions done before entering SLEEP mode */ + __DSB(); + __ISB(); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enters Stop mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param Regulator Specifies the regulator state in Stop mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON + * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction + * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Select the regulator state in Stop mode ---------------------------------*/ + tmpreg = PWR->CR1; + /* Clear PDDS and LPDS bits */ + tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS); + + /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */ + tmpreg |= Regulator; + + /* Store the new value */ + PWR->CR1 = tmpreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Ensure that all instructions done before entering STOP mode */ + __DSB(); + __ISB(); + + /* Select Stop mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enters Standby mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC + * Alarm out, or RTC clock calibration out. + * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. + * - WKUP pins if enabled. + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select Standby mode */ + PWR->CR1 |= PWR_CR1_PDDS; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler(). + * @retval None + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + /* Check PWR Exti flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR PVD interrupt callback + * @retval None + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback could be implemented in the user file + */ +} + +/** + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run only on + * interruptions handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enables CORTEX M4 SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Disables CORTEX M4 SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c new file mode 100644 index 0000000..6ff3321 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c @@ -0,0 +1,554 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of PWR extension peripheral: + * + Peripheral Extended features functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup PWREx_Private_Constants + * @{ + */ +#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000 +#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000 +#define PWR_BKPREG_TIMEOUT_VALUE 1000 +#define PWR_VOSRDY_TIMEOUT_VALUE 1000 +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions + * @brief Peripheral Extended features functions + * +@verbatim + + =============================================================================== + ##### Peripheral extended features functions ##### + =============================================================================== + + *** Main and Backup Regulators configuration *** + ================================================ + [..] + (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from + the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is + retained even in Standby or VBAT mode when the low power backup regulator + is enabled. It can be considered as an internal EEPROM when VBAT is + always present. You can use the HAL_PWREx_EnableBkUpReg() function to + enable the low power backup regulator. + + (+) When the backup domain is supplied by VDD (analog switch connected to VDD) + the backup SRAM is powered from VDD which replaces the VBAT power supply to + save battery life. + + (+) The backup SRAM is not mass erased by a tamper event. It is read + protected to prevent confidential data, such as cryptographic private + key, from being accessed. The backup SRAM can be erased only through + the Flash interface when a protection level change from level 1 to + level 0 is requested. + -@- Refer to the description of Read protection (RDP) in the Flash + programming manual. + + (+) The main internal regulator can be configured to have a tradeoff between + performance and power consumption when the device does not operate at + the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() + macro which configure VOS bit in PWR_CR register + + Refer to the product datasheets for more details. + + *** FLASH Power Down configuration **** + ======================================= + [..] + (+) By setting the FPDS bit in the PWR_CR register by using the + HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power + down mode when the device enters Stop mode. When the Flash memory + is in power down mode, an additional startup delay is incurred when + waking up from Stop mode. + + *** Over-Drive and Under-Drive configuration **** + ================================================= + [..] + (+) In Run mode: the main regulator has 2 operating modes available: + (++) Normal mode: The CPU and core logic operate at maximum frequency at a given + voltage scaling (scale 1, scale 2 or scale 3) + (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a + higher frequency than the normal mode for a given voltage scaling (scale 1, + scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and + disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow + the sequence described in Reference manual. + + (+) In Stop mode: the main regulator or low power regulator supplies a low power + voltage to the 1.2V domain, thus preserving the content of registers + and internal SRAM. 2 operating modes are available: + (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only + available when the main regulator or the low power regulator is used in Scale 3 or + low voltage mode. + (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only + available when the main regulator or the low power regulator is in low voltage mode. + +@endverbatim + * @{ + */ + +/** + * @brief Enables the Backup Regulator. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) +{ + uint32_t tickstart = 0; + + /* Enable Backup regulator */ + PWR->CSR1 |= PWR_CSR1_BRE; + + /* Workaround for the following hardware bug: */ + /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */ + PWR->CSR1 |= PWR_CSR1_EIWUP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till Backup regulator ready flag is set */ + while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET) + { + if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Disables the Backup Regulator. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) +{ + uint32_t tickstart = 0; + + /* Disable Backup regulator */ + PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE); + + /* Workaround for the following hardware bug: */ + /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */ + PWR->CSR1 |= PWR_CSR1_EIWUP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till Backup regulator ready flag is set */ + while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET) + { + if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Enables the Flash Power Down in Stop mode. + * @retval None + */ +void HAL_PWREx_EnableFlashPowerDown(void) +{ + /* Enable the Flash Power Down */ + PWR->CR1 |= PWR_CR1_FPDS; +} + +/** + * @brief Disables the Flash Power Down in Stop mode. + * @retval None + */ +void HAL_PWREx_DisableFlashPowerDown(void) +{ + /* Disable the Flash Power Down */ + PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS); +} + +/** + * @brief Enables Main Regulator low voltage mode. + * @retval None + */ +void HAL_PWREx_EnableMainRegulatorLowVoltage(void) +{ + /* Enable Main regulator low voltage */ + PWR->CR1 |= PWR_CR1_MRUDS; +} + +/** + * @brief Disables Main Regulator low voltage mode. + * @retval None + */ +void HAL_PWREx_DisableMainRegulatorLowVoltage(void) +{ + /* Disable Main regulator low voltage */ + PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS); +} + +/** + * @brief Enables Low Power Regulator low voltage mode. + * @retval None + */ +void HAL_PWREx_EnableLowRegulatorLowVoltage(void) +{ + /* Enable low power regulator */ + PWR->CR1 |= PWR_CR1_LPUDS; +} + +/** + * @brief Disables Low Power Regulator low voltage mode. + * @retval None + */ +void HAL_PWREx_DisableLowRegulatorLowVoltage(void) +{ + /* Disable low power regulator */ + PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS); +} + +/** + * @brief Activates the Over-Drive mode. + * @note This mode allows the CPU and the core logic to operate at a higher frequency + * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). + * @note It is recommended to enter or exit Over-drive mode when the application is not running + * critical tasks and when the system clock source is either HSI or HSE. + * During the Over-drive switch activation, no peripheral clocks should be enabled. + * The peripheral clocks must be enabled once the Over-drive mode is activated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) +{ + uint32_t tickstart = 0; + + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable the Over-drive to extend the clock frequency to 216 MHz */ + __HAL_PWR_OVERDRIVE_ENABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Enable the Over-drive switch */ + __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Deactivates the Over-Drive mode. + * @note This mode allows the CPU and the core logic to operate at a higher frequency + * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). + * @note It is recommended to enter or exit Over-drive mode when the application is not running + * critical tasks and when the system clock source is either HSI or HSE. + * During the Over-drive switch activation, no peripheral clocks should be enabled. + * The peripheral clocks must be enabled once the Over-drive mode is activated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) +{ + uint32_t tickstart = 0; + + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Disable the Over-drive switch */ + __HAL_PWR_OVERDRIVESWITCHING_DISABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Disable the Over-drive */ + __HAL_PWR_OVERDRIVE_DISABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Enters in Under-Drive STOP mode. + * + * @note This mode can be selected only when the Under-Drive is already active + * + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main regulator or the low power regulator + * is in low voltage mode + * + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + * + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * + * @param Regulator specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode + * and Flash memory in power-down when the device is in Stop under-drive mode + * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode + * and Flash memory in power-down when the device is in Stop under-drive mode + * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction + * @retval None + */ +HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + uint32_t tempreg = 0; + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + /* Enable the Under-drive Mode ---------------------------------------------*/ + /* Clear Under-drive flag */ + __HAL_PWR_CLEAR_ODRUDR_FLAG(); + + /* Enable the Under-drive */ + __HAL_PWR_UNDERDRIVE_ENABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for UnderDrive mode is ready */ + while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Select the regulator state in STOP mode ---------------------------------*/ + tempreg = PWR->CR1; + /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */ + tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS); + + /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ + tempreg |= Regulator; + + /* Store the new value */ + PWR->CR1 = tempreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + return HAL_OK; +} + +/** + * @brief Returns Voltage Scaling Range. + * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or + * PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1 + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + return (PWR->CR1 & PWR_CR1_VOS); +} + +/** + * @brief Configures the main internal regulator output voltage. + * @param VoltageScaling specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption. + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, + * typical output voltage at 1.4 V, + * system frequency up to 216 MHz. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, + * typical output voltage at 1.2 V, + * system frequency up to 180 MHz. + * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode, + * typical output voltage at 1.00 V, + * system frequency up to 151 MHz. + * @note To update the system clock frequency(SYSCLK): + * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig(). + * - Call the HAL_RCC_OscConfig() to configure the PLL. + * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale. + * - Set the new system clock frequency using the HAL_RCC_ClockConfig(). + * @note The scale can be modified only when the HSI or HSE clock source is selected + * as system clock source, otherwise the API returns HAL_ERROR. + * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits + * value in the PWR_CR1 register are not taken in account. + * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2. + * @note The new voltage scale is active only when the PLL is ON. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + uint32_t tickstart = 0; + + assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling)); + + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + { + /* Disable the main PLL */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set Range */ + __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); + + /* Enable the main PLL */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) + { + if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c new file mode 100644 index 0000000..bf33cff --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c @@ -0,0 +1,1221 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache + and I-Cache are disabled, and all peripherals are off except internal + SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; + all peripherals mapped on these busses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB busses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle + after the clock enable bit is set on the hardware register + (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle + after the clock enable bit is set on the hardware register + + [..] + Implemented Workaround: + (+) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +#define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define MCO2_GPIO_PORT GPIOC +#define MCO2_PIN GPIO_PIN_9 + +/** + * @} + */ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== +##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 + and APB2). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL (clocked by HSI or HSE), featuring two different output clocks: + (++) The first output is used to generate the high speed system clock (up to 216 MHz) + (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), + the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). + + (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS() + and if a HSE clock failure occurs(HSE used directly or through PLL as System + clock source), the System clock is automatically switched to HSI and an interrupt + is generated if enabled. The interrupt is linked to the Cortex-M7 NMI + (Non-Maskable Interrupt) exception vector. + + (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL + clock (through a configurable prescaler) on PA8 pin. + + (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S + clock (through a configurable prescaler) on PC9 pin. + + [..] System, AHB and APB busses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or + from an external clock mapped on the I2S_CKIN pin. + You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. + (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or + from an external clock mapped on the I2S_CKIN pin. + You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. + (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE() + macros to configure this clock. + (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz + to work correctly, while the SDIO require a frequency equal or lower than + to 48. This clock is derived of the main PLL through PLLQ divider. + (+@) IWDG clock which is always the LSI clock. +@endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL, PLLI2S and PLLSAI OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Set HSION bit to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM[4:0] bits to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSITRIM_4); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear HSEON, HSEBYP and CSSON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLLON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLLI2SON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); + + /* Wait till PLLI2S is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLLSAI bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); + + /* Wait till PLLSAI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */ + RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | 0x20000000U; + + /* Reset PLLI2SCFGR register to default value */ + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1; + + /* Reset PLLSAICFGR register to default value */ + RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | 0x20000000U; + + /* Disable all interrupts */ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE); + + /* Clear all interrupt flags */ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC); + + /* Clear LSION bit */ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this function. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this function. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + FlagStatus pwrclkchanged = RESET; + + /* Check Null pointer */ + if(RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is bypassed or disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Restore clock configuration if changed */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); +#if defined (RCC_PLLCFGR_PLLR) + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); +#endif + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ +#if defined (RCC_PLLCFGR_PLLR) + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLM, + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); +#else + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLM, + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ); +#endif + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB busses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency, this parameter depend on device selected + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * startup from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @note Depending on the device voltage range, the software has to set correctly + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart = 0; + + /* Check Null pointer */ + if(RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + } + + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick (TICK_INT_PRIORITY); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * + @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + +@endverbatim + * @{ + */ + +/** + * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). + * @note PA8/PC9 should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). + * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source + * @param RCC_MCODiv specifies the MCOx prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef GPIO_InitStruct; + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + /* RCC_MCO1 */ + if(RCC_MCOx == RCC_MCO1) + { + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* MCO1 Clock Enable */ + MCO1_CLK_ENABLE(); + + /* Configure the MCO1 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO1_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); + } + else + { + assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); + + /* MCO2 Clock Enable */ + MCO2_CLK_ENABLE(); + + /* Configure the MCO2 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO2_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3))); + } +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Returns the SYSCLK frequency + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t pllm = 0, pllvco = 0, pllp = 0; + uint32_t sysclockfreq = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + break; + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2); + + sysclockfreq = pllvco/pllp; + break; + } + default: + { + sysclockfreq = HSI_VALUE; + break; + } + } + return sysclockfreq; +} + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]); +} + +/** + * @brief Returns the PCLK2 frequency + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]); +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + + /* Get the HSE configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the HSI configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + + /* Get the LSE configuration -----------------------------------------------*/ + if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the PLL configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); + RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> RCC_PLLCFGR_PLLP_Pos); + RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos); +#if defined (RCC_PLLCFGR_PLLR) + RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)); +#endif +} + +/** + * @brief Configures the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if(__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval None + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c new file mode 100644 index 0000000..c1cbbd2 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c @@ -0,0 +1,1776 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extension RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCCEx HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Defines RCCEx Private Defines + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ + +/** + * @} + */ + + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) and RCC_BDCR register will be set to their reset values. + +@endverbatim + * @{ + */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || \ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || \ + defined (STM32F750xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0; + uint32_t tmpreg0 = 0; + uint32_t tmpreg1 = 0; + uint32_t plli2sused = 0; + uint32_t pllsaiused = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*----------------------------------- I2S configuration ----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + + /* Enable the PLLI2S when it's used as clock source for I2S */ + if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + } + + /*------------------------------------ SAI1 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) + { + pllsaiused = 1; + } + } + + /*------------------------------------ SAI2 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + + /* Configure SAI2 Clock source */ + __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) + { + pllsaiused = 1; + } + } + + /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + { + plli2sused = 1; + } + + /*------------------------------------ RTC configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait for Backup domain Write protection disable */ + while((PWR->CR1 & PWR_CR1_DBP) == RESET) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); + + if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg0; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + + /*------------------------------------ TIM configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + /* Check the parameters */ + assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + + /*-------------------------------------- I2C1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + } + + /*-------------------------------------- I2C2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + } + + /*-------------------------------------- I2C3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + } + + /*-------------------------------------- I2C4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); + + /* Configure the I2C4 clock source */ + __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); + } + + /*-------------------------------------- USART1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + + /*-------------------------------------- USART2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + } + + /*-------------------------------------- USART3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + } + + /*-------------------------------------- UART4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + { + /* Check the parameters */ + assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); + + /* Configure the UART4 clock source */ + __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); + } + + /*-------------------------------------- UART5 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + { + /* Check the parameters */ + assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); + + /* Configure the UART5 clock source */ + __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); + } + + /*-------------------------------------- USART6 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) + { + /* Check the parameters */ + assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); + + /* Configure the USART6 clock source */ + __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); + } + + /*-------------------------------------- UART7 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) + { + /* Check the parameters */ + assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); + + /* Configure the UART7 clock source */ + __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); + } + + /*-------------------------------------- UART8 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) + { + /* Check the parameters */ + assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); + + /* Configure the UART8 clock source */ + __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); + } + + /*--------------------------------------- CEC Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } + + /*-------------------------------------- CK48 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + + /* Enable the PLLSAI when it's used as clock source for CK48 */ + if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) + { + pllsaiused = 1; + } + } + + /*-------------------------------------- LTDC Configuration -----------------------------------*/ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + { + pllsaiused = 1; + } +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LTPIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + + /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); + + /* Configure the SDMMC1 clock source */ + __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); + } + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); + + /* Configure the SDMMC2 clock source */ + __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); + } + + /*------------------------------------- DFSDM1 Configuration -------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); + + /* Configure the DFSDM1 interface clock source */ + __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); + } + + /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); + + /* Configure the DFSDM interface clock source */ + __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + + /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ + /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ + if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) + { + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* check for common PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + { + /* Check for PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + /* Check for PLLI2S/DIVQ parameters */ + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ + /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + + /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ + /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ + if(pllsaiused == 1) + { + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLSAI is disabled */ + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + { + /* check for PLLSAIQ Parameter */ + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + /* check for PLLSAI/DIVQ Parameter */ + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ + /* In Case of PLLI2S is selected as source clock for CK48 */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + + /* Configure the PLLSAI division factors */ + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ + /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); + } + +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + /*---------------------------- LTDC configuration -------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) + { + assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); + assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); + + /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR); + + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); + } +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLSAI is ready */ + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg = 0; + + /* Set all possible values for the extended clock type parameter------------*/ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ + RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ + RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ + RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ + RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2 |\ + RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1_AUDIO; +#else + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ + RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ + RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ + RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ + RCC_PERIPHCLK_CLK48; +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + + /* Get the PLLI2S Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + + /* Get the PLLSAI Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + + /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos); + PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos); + + /* Get the SAI1 clock configuration ----------------------------------------------*/ + PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); + + /* Get the SAI2 clock configuration ----------------------------------------------*/ + PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); + + /* Get the I2S clock configuration ------------------------------------------*/ + PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE(); + + /* Get the I2C1 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + + /* Get the I2C2 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); + + /* Get the I2C3 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); + + /* Get the I2C4 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); + + /* Get the USART1 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + + /* Get the USART2 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); + + /* Get the USART3 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); + + /* Get the UART4 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); + + /* Get the UART5 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); + + /* Get the USART6 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); + + /* Get the UART7 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); + + /* Get the UART8 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); + + /* Get the LPTIM1 clock configuration ------------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + + /* Get the CEC clock configuration -----------------------------------------------*/ + PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); + + /* Get the CK48 clock configuration -----------------------------------------------*/ + PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + + /* Get the SDMMC1 clock configuration -----------------------------------------------*/ + PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + /* Get the SDMMC2 clock configuration -----------------------------------------------*/ + PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); + + /* Get the DFSDM clock configuration -----------------------------------------------*/ + PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); + + /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/ + PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + + /* Get the RTC Clock configuration -----------------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + /* Get the TIM Prescaler configuration --------------------------------------------*/ + if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, SAI, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0; + uint32_t tmpreg0 = 0; + uint32_t plli2sused = 0; + uint32_t pllsaiused = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*----------------------------------- I2S configuration ----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + + /* Enable the PLLI2S when it's used as clock source for I2S */ + if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + } + + /*------------------------------------ SAI1 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) + { + pllsaiused = 1; + } + } + + /*------------------------------------ SAI2 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + + /* Configure SAI2 Clock source */ + __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) + { + pllsaiused = 1; + } + } + + /*------------------------------------ RTC configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait for Backup domain Write protection disable */ + while((PWR->CR1 & PWR_CR1_DBP) == RESET) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); + + if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg0; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + + /*------------------------------------ TIM configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + /* Check the parameters */ + assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + + /*-------------------------------------- I2C1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + } + + /*-------------------------------------- I2C2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + } + + /*-------------------------------------- I2C3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + } + + /*-------------------------------------- USART1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + + /*-------------------------------------- USART2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + } + + /*-------------------------------------- USART3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + } + + /*-------------------------------------- UART4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + { + /* Check the parameters */ + assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); + + /* Configure the UART4 clock source */ + __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); + } + + /*-------------------------------------- UART5 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + { + /* Check the parameters */ + assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); + + /* Configure the UART5 clock source */ + __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); + } + + /*-------------------------------------- USART6 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) + { + /* Check the parameters */ + assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); + + /* Configure the USART6 clock source */ + __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); + } + + /*-------------------------------------- UART7 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) + { + /* Check the parameters */ + assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); + + /* Configure the UART7 clock source */ + __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); + } + + /*-------------------------------------- UART8 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) + { + /* Check the parameters */ + assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); + + /* Configure the UART8 clock source */ + __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); + } + + /*-------------------------------------- CK48 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + + /* Enable the PLLSAI when it's used as clock source for CK48 */ + if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) + { + pllsaiused = 1; + } + } + + /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LTPIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + + /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); + + /* Configure the SDMMC1 clock source */ + __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); + } + + /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); + + /* Configure the SDMMC2 clock source */ + __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); + } + + /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ + /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */ + if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) + { + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* check for common PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + { + /* Check for PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + /* Check for PLLI2S/DIVQ parameters */ + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg0); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + + /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ + /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ + if(pllsaiused == 1) + { + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLSAI is disabled */ + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + { + /* check for PLLSAIQ Parameter */ + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + /* check for PLLSAI/DIVQ Parameter */ + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ + /* In Case of PLLI2S is selected as source clock for CK48 */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + + /* Configure the PLLSAI division factors */ + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ + /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0); + } + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLSAI is ready */ + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg = 0; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ + RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ + RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ + RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ + RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2; + + /* Get the PLLI2S Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + + /* Get the PLLSAI Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + + /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos); + + /* Get the SAI1 clock configuration ----------------------------------------------*/ + PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); + + /* Get the SAI2 clock configuration ----------------------------------------------*/ + PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); + + /* Get the I2S clock configuration ------------------------------------------*/ + PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE(); + + /* Get the I2C1 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + + /* Get the I2C2 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); + + /* Get the I2C3 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); + + /* Get the USART1 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + + /* Get the USART2 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); + + /* Get the USART3 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); + + /* Get the UART4 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); + + /* Get the UART5 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); + + /* Get the USART6 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); + + /* Get the UART7 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); + + /* Get the UART8 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); + + /* Get the LPTIM1 clock configuration ------------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + + /* Get the CK48 clock configuration -----------------------------------------------*/ + PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + + /* Get the SDMMC1 clock configuration -----------------------------------------------*/ + PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); + + /* Get the SDMMC2 clock configuration -----------------------------------------------*/ + PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); + + /* Get the RTC Clock configuration -----------------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + /* Get the TIM Prescaler configuration --------------------------------------------*/ + if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock + * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + uint32_t tmpreg = 0; + /* This variable is used to store the SAI clock frequency (value in Hz) */ + uint32_t frequency = 0; + /* This variable is used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0; + /* This variable is used to store the SAI clock source */ + uint32_t saiclocksource = 0; + + if (PeriphClk == RCC_PERIPHCLK_SAI1) + { + saiclocksource = RCC->DCKCFGR1; + saiclocksource &= RCC_DCKCFGR1_SAI1SEL; + switch (saiclocksource) + { + case 0: /* PLLSAI is the clock source for SAI1 */ + { + /* Configure the PLLSAI division factor */ + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); + } + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; + frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); + frequency = frequency/(tmpreg); + break; + } + case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */ + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; + frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); + frequency = frequency/(tmpreg); + break; + } + case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/ + { + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the main PLL Source is HSI */ + frequency = HSI_VALUE; + } + else + { + /* In Case the main PLL Source is HSE */ + frequency = HSE_VALUE; + } + break; + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + default : + { + break; + } + } + } + + if (PeriphClk == RCC_PERIPHCLK_SAI2) + { + saiclocksource = RCC->DCKCFGR1; + saiclocksource &= RCC_DCKCFGR1_SAI2SEL; + switch (saiclocksource) + { + case 0: /* PLLSAI is the clock source for SAI*/ + { + /* Configure the PLLSAI division factor */ + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); + } + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; + frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); + frequency = frequency/(tmpreg); + break; + } + case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */ + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; + frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); + frequency = frequency/(tmpreg); + break; + } + case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */ + { + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the main PLL Source is HSI */ + frequency = HSI_VALUE; + } + else + { + /* In Case the main PLL Source is HSE */ + frequency = HSE_VALUE; + } + break; + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + default : + { + break; + } + } + } + + return frequency; +} + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions + * @brief Extended Clock management functions + * +@verbatim + =============================================================================== + ##### Extended clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + activation or deactivation of PLLI2S, PLLSAI. +@endverbatim + * @{ + */ + +/** + * @brief Enable PLLI2S. + * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that + * contains the configuration information for the PLLI2S + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ)); +#if defined(RCC_PLLI2SCFGR_PLLI2SP) + assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP)); +#endif /* RCC_PLLI2SCFGR_PLLI2SP */ + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLI2S division factors */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#else + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ + /* I2SPCLK = PLLI2S_VCO / PLLI2SP */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Wait till PLLI2S is ready */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLI2S. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) +{ + uint32_t tickstart; + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Enable PLLSAI. + * @param PLLSAIInit pointer to an RCC_PLLSAIInitTypeDef structure that + * contains the configuration information for the PLLSAI + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN)); + assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ)); + assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP)); +#if defined(RCC_PLLSAICFGR_PLLSAIR) + assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR)); +#endif /* RCC_PLLSAICFGR_PLLSAIR */ + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLSAI division factors */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ); +#else + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \ + PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ + + /* Enable the PLLSAI */ + __HAL_RCC_PLLSAI_ENABLE(); + + /* Wait till PLLSAI is ready */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLSAI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void) +{ + uint32_t tickstart; + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c new file mode 100644 index 0000000..c467692 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c @@ -0,0 +1,6880 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Function @ref HAL_TIM_RegisterCallback() to register a callback. + @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + (+) Break2Callback : TIM Break2 Callback. + +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). + + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Change the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + if ((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((htim->State == HAL_TIM_STATE_READY)) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + if ((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((htim->State == HAL_TIM_STATE_READY)) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + if ((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((htim->State == HAL_TIM_STATE_READY)) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + if ((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((htim->State == HAL_TIM_STATE_READY)) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + if ((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((htim->State == HAL_TIM_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_ALL: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + default: + break; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break2 input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 5 in Output Compare */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 6 in Output Compare */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + break; + } + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the Channel 5 in PWM mode */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel5*/ + htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the Channel 6 in PWM mode */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel6 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + break; + } + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel) +{ + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + default: + break; + } + + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 (*) + * @arg TIM_DMABASE_AF2 (*) + * (*) value not defined in all devices + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t *BurstBuffer, uint32_t BurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + + if ((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((htim->State == HAL_TIM_STATE_READY)) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + default: + break; + } + /* configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA stream) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + break; + } + + if (HAL_OK == status) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 (*) + * @arg TIM_DMABASE_AF2 (*) + * (*) value not defined in all devices + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t *BurstBuffer, uint32_t BurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + + if ((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((htim->State == HAL_TIM_STATE_READY)) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture/compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + default: + break; + } + + /* configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA stream) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + break; + } + + if (HAL_OK == status) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant + * only for timer instances supporting break input(s). + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + break; + } + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + break; + } + + default: + break; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + case TIM_CHANNEL_5: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 5 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + else + { + /* Disable the OCREF clear feature for Channel 5 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + break; + } + case TIM_CHANNEL_6: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 6 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + else + { + /* Disable the OCREF clear feature for Channel 6 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + break; + } + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */ + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */ + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ + break; + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 5 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, + TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC5E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC5M); + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC5P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 16U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS5; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 8U); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR5 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 6 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, + TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC6E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC6M); + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)~TIM_CCER_CC6P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 20U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS6; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 10U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR6 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } + + default: + break; + } + return HAL_OK; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ + htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */ +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c new file mode 100644 index 0000000..271f11e --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c @@ -0,0 +1,2137 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + * + Timer remapping capabilities configuration + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + if ((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((htim->State == HAL_TIM_STATE_READY)) + { + if (((uint32_t)pData == 0U) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream for Capture 1*/ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer; + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + if ((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((htim->State == HAL_TIM_STATE_READY)) + { + if (((uint32_t)pData == 0U) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. + (+) Start the Complementary Input Capture measurement. + (+) Stop the Complementary Input Capture. + (+) Start the Complementary Input Capture and enable interrupts. + (+) Stop the Complementary Input Capture and disable interrupts. + (+) Start the Complementary Input Capture and enable DMA transfers. + (+) Stop the Complementary Input Capture and disable DMA transfers. + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + if ((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((htim->State == HAL_TIM_STATE_READY)) + { + if (((uint32_t)pData == 0U) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + break; + } + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Enable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + (+) Enable or disable channel grouping. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); + + /* Clear the MMS2 bits */ + tmpcr2 &= ~TIM_CR2_MMS2; + /* Select the TRGO2 source*/ + tmpcr2 |= sMasterConfig->MasterOutputTrigger2; + } + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); + + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); + assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + + /* Set the BREAK2 input related BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); + } + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#if defined(TIM_BREAK_INPUT_SUPPORT) + +/** + * @brief Configures the break input source. + * @param htim TIM handle. + * @param BreakInput Break input to configure + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @param sBreakInputConfig Break input source configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, + uint32_t BreakInput, + TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) + +{ + uint32_t tmporx; + uint32_t bkin_enable_mask = 0U; + uint32_t bkin_polarity_mask = 0U; + uint32_t bkin_enable_bitpos = 0U; + uint32_t bkin_polarity_bitpos = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); + assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); +#if defined(DFSDM1_Channel0) + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) + { + assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); + } +#else + assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); +#endif /* DFSDM1_Channel0 */ + + /* Check input state */ + __HAL_LOCK(htim); + + switch (sBreakInputConfig->Source) + { + case TIM_BREAKINPUTSOURCE_BKIN: + { + bkin_enable_mask = TIM1_AF1_BKINE; + bkin_enable_bitpos = 0; + bkin_polarity_mask = TIM1_AF1_BKINP; + bkin_polarity_bitpos = 9; + break; + } + + case TIM_BREAKINPUTSOURCE_DFSDM1: + { + bkin_enable_mask = TIM1_AF1_BKDF1BKE; + bkin_enable_bitpos = 8; + break; + } + + default: + break; + } + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Get the TIMx_AF1 register value */ + tmporx = htim->Instance->AF1; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ +#if defined(DFSDM1_Channel0) + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) +#endif /* DFSDM1_Channel0 */ + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } + + /* Set TIMx_AF1 */ + htim->Instance->AF1 = tmporx; + break; + } + case TIM_BREAKINPUT_BRK2: + { + /* Get the TIMx_AF2 register value */ + tmporx = htim->Instance->AF2; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ +#if defined(DFSDM1_Channel0) + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) +#endif /* DFSDM1_Channel0 */ + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } + + /* Set TIMx_AF2 */ + htim->Instance->AF2 = tmporx; + break; + } + default: + break; + } + + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#endif /*TIM_BREAK_INPUT_SUPPORT */ + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * This parameter can be one of the following values: + * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) + * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output. + * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. + * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. + * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) + * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock. + * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock. + * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. + * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) + * @arg TIM_TIM11_SPDIF: SPDIF Frame synchronous + * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock + * (HSE divided by a programmable prescaler) + * @arg TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1 + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + __HAL_LOCK(htim); + + /* Check parameters */ + assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); + assert_param(IS_TIM_REMAP(Remap)); + + /* Set the Timer remapping configuration */ + htim->Instance->OR = Remap; + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Group channel 5 and channel 1, 2 or 3 + * @param htim TIM handle. + * @param Channels specifies the reference signal(s) the OC5REF is combined with. + * This parameter can be any combination of the following values: + * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC + * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF + * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF + * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) +{ + /* Check parameters */ + assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_GROUPCH5(Channels)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Clear GC5Cx bit fields */ + htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); + + /* Set GC5Cx bit fields */ + htim->Instance->CCR5 |= Channels; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Hall commutation changed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Hall commutation changed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c new file mode 100644 index 0000000..76efbf8 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c @@ -0,0 +1,3471 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_uart.c + * @author MCD Application Team + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure these UART pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) UART interrupts handling: + -@@- The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) + are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() + inside the transmit and receive processes. + (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. + + (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) + in the huart handle AdvancedInit structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers + by calling the HAL_LIN_Init() API. + + (#) For the UART Multiprocessor mode, initialize the UART registers + by calling the HAL_MultiProcessor_Init() API. + + (#) For the UART RS485 Driver Enabled mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + [..] + (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), + also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by + calling the customized HAL_UART_MspInit() API. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_UART_RegisterCallback() to register a user callback. + Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() + and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() + or @ref HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief HAL UART module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ + + +#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ +#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions + * @{ + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API + follow respectively the UART asynchronous, UART Half duplex, UART LIN mode + and UART multiprocessor mode configuration procedures (details for the procedures + are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the UART mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* Check the parameters */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + } + else + { + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Initialize the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check UART instance */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the LIN mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param BreakDetectLength Specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection + * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + /* Check the Break detection length parameter */ + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + + /* LIN mode limited to 16-bit oversampling only */ + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + return HAL_ERROR; + } + /* LIN mode limited to 8-bit data length */ + if (huart->Init.WordLength != UART_WORDLENGTH_8B) + { + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In LIN mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + + /* Set the USART LIN Break detection length. */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the multiprocessor mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @param Address UART node address (4-, 6-, 7- or 8-bit long). + * @param WakeUpMethod Specifies the UART wakeup method. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection + * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark + * @note If the user resorts to idle line detection wake up, the Address parameter + * is useless and ignored by the initialization function. + * @note If the user resorts to address mark wake up, the address length detection + * is configured by default to 4 bits only. For the UART to be able to + * manage 6-, 7- or 8-bit long addresses detection, the API + * HAL_MultiProcessorEx_AddressLength_Set() must be called after + * HAL_MultiProcessor_Init(). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the wake up method parameter */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In multiprocessor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) + { + /* If address mark wake up method is chosen, set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); + } + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief DeInitialize the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + huart->Instance->CR1 = 0x0U; + huart->Instance->CR2 = 0x0U; + huart->Instance->CR3 = 0x0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Initialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used instead of the weak predefined callback + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = pCallback; + break; + + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(huart); + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + + return status; +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two mode of transfer: + (+) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (+) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode API's are : + (+) HAL_UART_Transmit() + (+) HAL_UART_Receive() + + (#) Non-Blocking mode API's with Interrupt are : + (+) HAL_UART_Transmit_IT() + (+) HAL_UART_Receive_IT() + (+) HAL_UART_IRQHandler() + + (#) Non-Blocking mode API's with DMA are : + (+) HAL_UART_Transmit_DMA() + (+) HAL_UART_Receive_DMA() + (+) HAL_UART_DMAPause() + (+) HAL_UART_DMAResume() + (+) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (+) HAL_UART_TxHalfCpltCallback() + (+) HAL_UART_TxCpltCallback() + (+) HAL_UART_RxHalfCpltCallback() + (+) HAL_UART_RxCpltCallback() + (+) HAL_UART_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (+) HAL_UART_Abort() + (+) HAL_UART_AbortTransmit() + (+) HAL_UART_AbortReceive() + (+) HAL_UART_Abort_IT() + (+) HAL_UART_AbortTransmit_IT() + (+) HAL_UART_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (+) HAL_UART_AbortCpltCallback() + (+) HAL_UART_AbortTransmitCpltCallback() + (+) HAL_UART_AbortReceiveCpltCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + + -@- In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + while (huart->TxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; + } + else + { + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; + } + huart->TxXferCount--; + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + huart->RxXferCount--; + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + huart->TxISR = NULL; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT; + } + else + { + huart->TxISR = UART_TxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the Transmit Data Register Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + huart->RxISR = NULL; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in DMA mode. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + if (huart->hdmatx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + + /* Enable the UART transmit DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->hdmarx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Process Locked */ + __HAL_LOCK(huart); + + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + /* Disable the UART DMA Tx request */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + /* Enable the UART DMA Tx request */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the UART DMA Rx request */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndRxTransfer(huart); + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Reset Handle ErrorCode to No Error */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t abortcplt = 1U; + + /* Disable interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + if (errorflags == 0U) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && (((cr3its & USART_CR3_EIE) != 0U) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U))) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE) != 0U) || + ((cr3its & USART_CR3_EIE) != 0U))) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* Call UART Error Call back function if need be --------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + errorcode = huart->ErrorCode; + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + ((errorcode & HAL_UART_ERROR_ORE) != 0U)) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE) != 0U) + && ((cr1its & USART_CR1_TXEIE) != 0U)) + { + if (huart->TxISR != NULL) + { + huart->TxISR(huart); + } + return; + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + UART_EndTransmit_IT(huart); + return; + } + +} + +/** + * @brief Tx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART. + (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode + (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode + (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode + (+) UART_SetConfig() API configures the UART peripheral + (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features + (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization + (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter + (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver + (+) HAL_LIN_SendBreak() API transmits the break characters +@endverbatim + * @{ + */ + +/** + * @brief Enable UART in mute mode (does not mean UART enters mute mode; + * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Enable USART mute mode by setting the MME bit in the CR1 register */ + SET_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Disable UART mute mode (does not mean the UART actually exits mute mode + * as it may not have been in mute mode at this very moment). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Enter UART mute mode (means UART actually enters mute mode). + * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. + * @param huart UART handle. + * @retval None + */ +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); +} + +/** + * @brief Enable the UART transmitter and disable the UART receiver. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + SET_BIT(huart->Instance->CR1, USART_CR1_TE); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the UART receiver and disable the UART transmitter. + * @param huart UART handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + SET_BIT(huart->Instance->CR1, USART_CR1_RE); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + + +/** + * @brief Transmit break characters. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Send break characters */ + __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @brief UART Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Return the UART handle state. + (+) Return the UART handle error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the UART handle state. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +{ + uint32_t temp1, temp2; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the UART handle error code. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval UART Error Code +*/ +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv = 0x00000000U; + HAL_StatusTypeDef ret = HAL_OK; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); + + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + + tmpreg |= huart->Init.OneBitSampling; + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_PCLK2: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_SYSCLK: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + } + else + { + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_PCLK2: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_SYSCLK: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = usartdiv; + } + else + { + ret = HAL_ERROR; + } + } + + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + return ret; +} + +/** + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + } + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + } + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + } +} + +/** + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Handle UART Communication Timeout. + * @param huart UART handle. + * @param Flag Specifies the UART flag to check + * @param Status Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} + + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; +} + + +/** + * @brief DMA UART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (hdma->Init.Mode != DMA_CIRCULAR) + { + huart->TxXferCount = 0U; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx Half complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx Half complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (hdma->Init.Mode != DMA_CIRCULAR) + { + huart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + huart->TxXferCount = 0U; + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + huart->RxXferCount = 0U; + UART_EndRxTransfer(huart); + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + huart->RxXferCount = 0U; + huart->TxXferCount = 0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmarx != NULL) + { + if (huart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmatx != NULL) + { + if (huart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->TxXferCount = 0U; + + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief TX interrrupt handler for 7 or 8 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) +{ + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrrupt handler for 9 bits data word length. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + tmp = (uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + } +} + + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief RX interrrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrrupt handler for 9 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c new file mode 100644 index 0000000..415fb56 --- /dev/null +++ b/utils/proto_test/otto_proto_test/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c @@ -0,0 +1,330 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_uart_ex.c + * @author MCD Application Team + * @brief Extended UART HAL module driver. + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * + @verbatim + ============================================================================== + ##### UART peripheral extended features ##### + ============================================================================== + + (#) Declare a UART_HandleTypeDef handle structure. + + (#) For the UART RS485 Driver Enable mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup UARTEx UARTEx + * @brief UART Extended HAL module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UARTEx_Private_Functions UARTEx Private Functions + * @{ + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions + * @{ + */ + +/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Extended Initialization and Configuration Functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration + procedures (details for the procedures are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the RS485 Driver enable feature according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param Polarity Select the driver enable polarity. + * This parameter can be one of the following values: + * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high + * @arg @ref UART_DE_POLARITY_LOW DE signal is active low + * @param AssertionTime Driver Enable assertion time: + * 5-bit value defining the time between the activation of the DE (Driver Enable) + * signal and the beginning of the start bit. It is expressed in sample time + * units (1/8 or 1/16 bit time, depending on the oversampling rate) + * @param DeassertionTime Driver Enable deassertion time: + * 5-bit value defining the time between the end of the last stop bit, in a + * transmitted message, and the de-activation of the DE (Driver Enable) signal. + * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + * oversampling rate). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) +{ + uint32_t temp; + + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + /* Check the Driver Enable UART instance */ + assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); + + /* Check the Driver Enable polarity */ + assert_param(IS_UART_DE_POLARITY(Polarity)); + + /* Check the Driver Enable assertion time */ + assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + + /* Check the Driver Enable deassertion time */ + assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + + /* Set the Driver Enable polarity */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + + /* Set the Driver Enable assertion and deassertion times */ + temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions + * @brief Extended functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of Wakeup and FIFO mode related callback functions. + +@endverbatim + * @{ + */ + + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides the following functions: + (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + detection length to more than 4 bits for multiprocessor address mark wake up. + +@endverbatim + * @{ + */ + + + + +/** + * @brief By default in multiprocessor mode, when the wake up method is set + * to address mark, the UART handles only 4-bit long addresses detection; + * this API allows to enable longer addresses detection (6-, 7- or 8-bit + * long). + * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. + * @param huart UART handle. + * @param AddressLength This parameter can be one of the following values: + * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address + * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the address length parameter */ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState to Ready */ + return (UART_CheckIdleState(huart)); +} + + + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UARTEx_Private_Functions + * @{ + */ + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/utils/proto_test/otto_proto_test/STM32F767ZITX_FLASH.ld b/utils/proto_test/otto_proto_test/STM32F767ZITX_FLASH.ld new file mode 100644 index 0000000..07fe73e --- /dev/null +++ b/utils/proto_test/otto_proto_test/STM32F767ZITX_FLASH.ld @@ -0,0 +1,200 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : Auto-generated by STM32CubeIDE +** +** Abstract : Linker script for STM32F767ZITx Device from STM32F7 series +** 2048Kbytes FLASH +** 512Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2019 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200 ; /* required amount of heap */ +_Min_Stack_Size = 0x400 ; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/utils/proto_test/otto_proto_test/STM32F767ZITX_RAM.ld b/utils/proto_test/otto_proto_test/STM32F767ZITX_RAM.ld new file mode 100644 index 0000000..29e7601 --- /dev/null +++ b/utils/proto_test/otto_proto_test/STM32F767ZITX_RAM.ld @@ -0,0 +1,200 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld (debug in RAM dedicated) +** +** Author : Auto-generated by STM32CubeIDE +** +** Abstract : Linker script for STM32F767ZITx Device from STM32F7 series +** 2048Kbytes FLASH +** 512Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2019 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >RAM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >RAM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >RAM + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >RAM + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >RAM + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >RAM + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >RAM + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >RAM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/utils/proto_test/otto_proto_test/otto_proto_test Debug.launch b/utils/proto_test/otto_proto_test/otto_proto_test Debug.launch new file mode 100644 index 0000000..7df8a0b --- /dev/null +++ b/utils/proto_test/otto_proto_test/otto_proto_test Debug.launch @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/utils/proto_test/otto_proto_test/otto_proto_test.ioc b/utils/proto_test/otto_proto_test/otto_proto_test.ioc new file mode 100644 index 0000000..572f062 --- /dev/null +++ b/utils/proto_test/otto_proto_test/otto_proto_test.ioc @@ -0,0 +1,245 @@ +#MicroXplorer Configuration settings - do not modify +File.Version=6 +KeepUserPlacement=false +Mcu.Family=STM32F7 +Mcu.IP0=CORTEX_M7 +Mcu.IP1=NVIC +Mcu.IP2=RCC +Mcu.IP3=SYS +Mcu.IP4=TIM2 +Mcu.IP5=TIM3 +Mcu.IP6=TIM4 +Mcu.IP7=TIM5 +Mcu.IP8=TIM6 +Mcu.IP9=USART6 +Mcu.IPNb=10 +Mcu.Name=STM32F767ZITx +Mcu.Package=LQFP144 +Mcu.Pin0=PC13 +Mcu.Pin1=PC0 +Mcu.Pin10=PF15 +Mcu.Pin11=PE9 +Mcu.Pin12=PD14 +Mcu.Pin13=PD15 +Mcu.Pin14=PC6 +Mcu.Pin15=PC7 +Mcu.Pin16=PA13 +Mcu.Pin17=PA14 +Mcu.Pin18=PB3 +Mcu.Pin19=VP_SYS_VS_Systick +Mcu.Pin2=PA0/WKUP +Mcu.Pin20=VP_TIM3_VS_ClockSourceINT +Mcu.Pin21=VP_TIM4_VS_ClockSourceINT +Mcu.Pin22=VP_TIM6_VS_ClockSourceINT +Mcu.Pin3=PA1 +Mcu.Pin4=PA3 +Mcu.Pin5=PA5 +Mcu.Pin6=PA6 +Mcu.Pin7=PF12 +Mcu.Pin8=PF13 +Mcu.Pin9=PF14 +Mcu.PinsNb=23 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F767ZITx +MxCube.Version=5.4.0 +MxDb.Version=DB.5.0.40 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.EXTI15_10_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_2 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +NVIC.TIM3_IRQn=true\:2\:1\:true\:true\:true\:1\:true\:true +NVIC.TIM6_DAC_IRQn=true\:2\:2\:true\:true\:true\:2\:true\:true +NVIC.USART6_IRQn=true\:1\:0\:true\:true\:true\:3\:true\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PA0/WKUP.GPIOParameters=GPIO_Label +PA0/WKUP.GPIO_Label=encoder_dx1 +PA0/WKUP.Locked=true +PA0/WKUP.Signal=S_TIM5_CH1 +PA1.GPIOParameters=GPIO_Label +PA1.GPIO_Label=encoder_dx2 +PA1.Locked=true +PA1.Signal=S_TIM5_CH2 +PA13.Mode=Serial_Wire +PA13.Signal=SYS_JTMS-SWDIO +PA14.Mode=Serial_Wire +PA14.Signal=SYS_JTCK-SWCLK +PA3.GPIOParameters=GPIO_Label +PA3.GPIO_Label=current1 +PA3.Locked=true +PA3.Signal=GPIO_Analog +PA5.GPIOParameters=GPIO_Label +PA5.GPIO_Label=encoder_sx1 +PA5.Locked=true +PA5.Signal=S_TIM2_CH1_ETR +PA6.GPIOParameters=GPIO_Label +PA6.GPIO_Label=fault2 +PA6.Locked=true +PA6.Signal=GPIO_Input +PB3.GPIOParameters=GPIO_Label +PB3.GPIO_Label=encoder_sx2 +PB3.Locked=true +PB3.Signal=S_TIM2_CH2 +PC0.GPIOParameters=GPIO_Label +PC0.GPIO_Label=current2 +PC0.Locked=true +PC0.Signal=GPIO_Analog +PC13.GPIOParameters=GPIO_Label +PC13.GPIO_Label=user_button +PC13.Locked=true +PC13.Signal=GPXTI13 +PC6.Mode=Asynchronous +PC6.Signal=USART6_TX +PC7.Mode=Asynchronous +PC7.Signal=USART6_RX +PCC.Checker=false +PCC.Line=STM32F7x7 +PCC.MCU=STM32F767ZITx +PCC.PartNumber=STM32F767ZITx +PCC.Seq0=0 +PCC.Series=STM32F7 +PCC.Temperature=25 +PCC.Vdd=3.3 +PD14.GPIOParameters=GPIO_Label +PD14.GPIO_Label=pwm2 +PD14.Locked=true +PD14.Signal=S_TIM4_CH3 +PD15.GPIOParameters=GPIO_Label +PD15.GPIO_Label=pwm1 +PD15.Locked=true +PD15.Signal=S_TIM4_CH4 +PE9.GPIOParameters=GPIO_Label +PE9.GPIO_Label=fault1 +PE9.Locked=true +PE9.Signal=GPIO_Input +PF12.GPIOParameters=GPIO_Label +PF12.GPIO_Label=dir2 +PF12.Locked=true +PF12.Signal=GPIO_Output +PF13.GPIOParameters=GPIO_Label +PF13.GPIO_Label=dir1 +PF13.Locked=true +PF13.Signal=GPIO_Output +PF14.GPIOParameters=PinState,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP +PF14.GPIO_Label=sleep2 +PF14.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_PP +PF14.GPIO_PuPd=GPIO_PULLUP +PF14.Locked=true +PF14.PinState=GPIO_PIN_SET +PF14.Signal=GPIO_Output +PF15.GPIOParameters=PinState,GPIO_PuPd,GPIO_Label +PF15.GPIO_Label=sleep1 +PF15.GPIO_PuPd=GPIO_PULLUP +PF15.Locked=true +PF15.PinState=GPIO_PIN_SET +PF15.Signal=GPIO_Output +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F767ZITx +ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.15.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=otto_proto_test.ioc +ProjectManager.ProjectName=otto_proto_test +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=STM32CubeIDE +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-MX_TIM2_Init-TIM2-false-HAL-true,4-MX_TIM3_Init-TIM3-false-HAL-true,5-MX_TIM4_Init-TIM4-false-HAL-true,6-MX_TIM5_Init-TIM5-false-HAL-true,7-MX_USART6_UART_Init-USART6-false-HAL-true +RCC.CECFreq_Value=32786.88524590164 +RCC.DFSDMFreq_Value=16000000 +RCC.FamilyName=M +RCC.HSE_VALUE=25000000 +RCC.HSI_VALUE=16000000 +RCC.I2SFreq_Value=96000000 +RCC.IPParameters=CECFreq_Value,DFSDMFreq_Value,FamilyName,HSE_VALUE,HSI_VALUE,I2SFreq_Value,LCDTFTFreq_Value,LSE_VALUE,LSI_VALUE,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLQCLKFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSAIoutputFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC2Freq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value +RCC.LCDTFTFreq_Value=48000000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.PLLCLKFreq_Value=96000000 +RCC.PLLI2SPCLKFreq_Value=96000000 +RCC.PLLI2SQCLKFreq_Value=96000000 +RCC.PLLI2SRCLKFreq_Value=96000000 +RCC.PLLQCLKFreq_Value=96000000 +RCC.PLLSAIPCLKFreq_Value=96000000 +RCC.PLLSAIQCLKFreq_Value=96000000 +RCC.PLLSAIRCLKFreq_Value=96000000 +RCC.PLLSAIoutputFreq_Value=96000000 +RCC.RNGFreq_Value=96000000 +RCC.SAI1Freq_Value=96000000 +RCC.SAI2Freq_Value=96000000 +RCC.SDMMC2Freq_Value=16000000 +RCC.SDMMCFreq_Value=16000000 +RCC.SPDIFRXFreq_Value=96000000 +RCC.USBFreq_Value=96000000 +RCC.VCOI2SOutputFreq_Value=192000000 +RCC.VCOInputFreq_Value=1000000 +RCC.VCOOutputFreq_Value=192000000 +RCC.VCOSAIOutputFreq_Value=192000000 +SH.GPXTI13.0=GPIO_EXTI13 +SH.GPXTI13.ConfNb=1 +SH.S_TIM2_CH1_ETR.0=TIM2_CH1,Encoder_Interface +SH.S_TIM2_CH1_ETR.ConfNb=1 +SH.S_TIM2_CH2.0=TIM2_CH2,Encoder_Interface +SH.S_TIM2_CH2.ConfNb=1 +SH.S_TIM4_CH3.0=TIM4_CH3,PWM Generation3 CH3 +SH.S_TIM4_CH3.ConfNb=1 +SH.S_TIM4_CH4.0=TIM4_CH4,PWM Generation4 CH4 +SH.S_TIM4_CH4.ConfNb=1 +SH.S_TIM5_CH1.0=TIM5_CH1,Encoder_Interface +SH.S_TIM5_CH1.ConfNb=1 +SH.S_TIM5_CH2.0=TIM5_CH2,Encoder_Interface +SH.S_TIM5_CH2.ConfNb=1 +TIM2.EncoderMode=TIM_ENCODERMODE_TI12 +TIM2.IPParameters=Period,EncoderMode +TIM2.Period=4294967295 +TIM3.IPParameters=Prescaler,Period +TIM3.IPParametersWithoutCheck=Period +TIM3.Period=159 +TIM3.Prescaler=999 +TIM4.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 +TIM4.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 +TIM4.IPParameters=Channel-PWM Generation4 CH4,Channel-PWM Generation3 CH3,Period +TIM4.Period=799 +TIM5.EncoderMode=TIM_ENCODERMODE_TI12 +TIM5.IPParameters=Period,EncoderMode +TIM5.Period=4294967295 +TIM6.IPParameters=Prescaler,Period +TIM6.Period=799 +TIM6.Prescaler=9999 +USART6.IPParameters=VirtualMode-Asynchronous,WordLength,Parity +USART6.Parity=PARITY_NONE +USART6.VirtualMode-Asynchronous=VM_ASYNC +USART6.WordLength=WORDLENGTH_8B +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TIM3_VS_ClockSourceINT.Mode=Internal +VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT +VP_TIM4_VS_ClockSourceINT.Mode=Internal +VP_TIM4_VS_ClockSourceINT.Signal=TIM4_VS_ClockSourceINT +VP_TIM6_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM6_VS_ClockSourceINT.Signal=TIM6_VS_ClockSourceINT +board=custom +isbadioc=false diff --git a/utils/proto_test/proto_receive.py b/utils/proto_test/proto_receive.py new file mode 100644 index 0000000..97632ae --- /dev/null +++ b/utils/proto_test/proto_receive.py @@ -0,0 +1,28 @@ +import velocities_pb2 + +import time, serial, struct +from serial import SerialException +ser = serial.Serial( + baudrate=115200, + parity=serial.PARITY_NONE, + stopbits=serial.STOPBITS_ONE, + bytesize=serial.EIGHTBITS, + rtscts=False) +while (ser.is_open == False): + try: + ser.port = '/dev/ttyUSB0' + ser.open() + except SerialException: + print("couldn't open ttyUSB0, check the connection") + time.sleep(2) + +print("port open") + + +while (1): + ser.reset_input_buffer() + buffer = ser.read(10) + + message = velocities_pb2.Velocities() + message.ParseFromString(buffer) + print(message) diff --git a/utils/proto_test/proto_transmit.py b/utils/proto_test/proto_transmit.py new file mode 100644 index 0000000..46e25ae --- /dev/null +++ b/utils/proto_test/proto_transmit.py @@ -0,0 +1,30 @@ +import velocities_pb2 + +import time, serial, struct +from serial import SerialException +ser = serial.Serial( + baudrate=115200, + parity=serial.PARITY_NONE, + stopbits=serial.STOPBITS_ONE, + bytesize=serial.EIGHTBITS, + rtscts=False) +while (ser.is_open == False): + try: + ser.port = '/dev/ttyUSB0' + ser.open() + except SerialException: + print("couldn't open ttyUSB0, check the connection") + time.sleep(2) + +print("port open") +message = velocities_pb2.Velocities() + +while (1): + message.linear_vel += 0.1 + message.angular_vel += 0.1 + buffer = message.SerializeToString() + ser.write(buffer) + print(message) + print(buffer) + ser.reset_output_buffer() + time.sleep(3) \ No newline at end of file diff --git a/utils/proto_test/velocities.pb.c b/utils/proto_test/velocities.pb.c new file mode 100644 index 0000000..b3f3839 --- /dev/null +++ b/utils/proto_test/velocities.pb.c @@ -0,0 +1,12 @@ +/* Automatically generated nanopb constant definitions */ +/* Generated by 0.4.1-dev */ + +#include "velocities.pb.h" +#if PB_PROTO_HEADER_VERSION != 40 +#error Regenerate this file with the current version of nanopb generator. +#endif + +PB_BIND(Velocities, Velocities, AUTO) + + + diff --git a/utils/proto_test/velocities.pb.h b/utils/proto_test/velocities.pb.h new file mode 100644 index 0000000..fdede34 --- /dev/null +++ b/utils/proto_test/velocities.pb.h @@ -0,0 +1,50 @@ +/* Automatically generated nanopb header */ +/* Generated by 0.4.1-dev */ + +#ifndef PB_VELOCITIES_PB_H_INCLUDED +#define PB_VELOCITIES_PB_H_INCLUDED +#include + +#if PB_PROTO_HEADER_VERSION != 40 +#error Regenerate this file with the current version of nanopb generator. +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* Struct definitions */ +typedef struct _Velocities { + float linear_vel; + float angular_vel; +} Velocities; + + +/* Initializer values for message structs */ +#define Velocities_init_default {0, 0} +#define Velocities_init_zero {0, 0} + +/* Field tags (for use in manual encoding/decoding) */ +#define Velocities_linear_vel_tag 1 +#define Velocities_angular_vel_tag 2 + +/* Struct field encoding specification for nanopb */ +#define Velocities_FIELDLIST(X, a) \ +X(a, STATIC, SINGULAR, FLOAT, linear_vel, 1) \ +X(a, STATIC, SINGULAR, FLOAT, angular_vel, 2) +#define Velocities_CALLBACK NULL +#define Velocities_DEFAULT NULL + +extern const pb_msgdesc_t Velocities_msg; + +/* Defines for backwards compatibility with code written before nanopb-0.4.0 */ +#define Velocities_fields &Velocities_msg + +/* Maximum encoded size of messages (where known) */ +#define Velocities_size 10 + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif diff --git a/utils/proto_test/velocities.proto b/utils/proto_test/velocities.proto new file mode 100644 index 0000000..cf03fc3 --- /dev/null +++ b/utils/proto_test/velocities.proto @@ -0,0 +1,6 @@ +syntax = "proto3"; + +message Velocities { + float linear_vel = 1; + float angular_vel = 2; +} diff --git a/utils/proto_test/velocities_pb2.py b/utils/proto_test/velocities_pb2.py new file mode 100644 index 0000000..2f13360 --- /dev/null +++ b/utils/proto_test/velocities_pb2.py @@ -0,0 +1,76 @@ +# Generated by the protocol buffer compiler. DO NOT EDIT! +# source: velocities.proto + +import sys +_b=sys.version_info[0]<3 and (lambda x:x) or (lambda x:x.encode('latin1')) +from google.protobuf import descriptor as _descriptor +from google.protobuf import message as _message +from google.protobuf import reflection as _reflection +from google.protobuf import symbol_database as _symbol_database +from google.protobuf import descriptor_pb2 +# @@protoc_insertion_point(imports) + +_sym_db = _symbol_database.Default() + + + + +DESCRIPTOR = _descriptor.FileDescriptor( + name='velocities.proto', + package='', + syntax='proto3', + serialized_pb=_b('\n\x10velocities.proto\"5\n\nVelocities\x12\x12\n\nlinear_vel\x18\x01 \x01(\x02\x12\x13\n\x0b\x61ngular_vel\x18\x02 \x01(\x02\x62\x06proto3') +) +_sym_db.RegisterFileDescriptor(DESCRIPTOR) + + + + +_VELOCITIES = _descriptor.Descriptor( + name='Velocities', + full_name='Velocities', + filename=None, + file=DESCRIPTOR, + containing_type=None, + fields=[ + _descriptor.FieldDescriptor( + name='linear_vel', full_name='Velocities.linear_vel', index=0, + number=1, type=2, cpp_type=6, label=1, + has_default_value=False, default_value=float(0), + message_type=None, enum_type=None, containing_type=None, + is_extension=False, extension_scope=None, + options=None), + _descriptor.FieldDescriptor( + name='angular_vel', full_name='Velocities.angular_vel', index=1, + number=2, type=2, cpp_type=6, label=1, + has_default_value=False, default_value=float(0), + message_type=None, enum_type=None, containing_type=None, + is_extension=False, extension_scope=None, + options=None), + ], + extensions=[ + ], + nested_types=[], + enum_types=[ + ], + options=None, + is_extendable=False, + syntax='proto3', + extension_ranges=[], + oneofs=[ + ], + serialized_start=20, + serialized_end=73, +) + +DESCRIPTOR.message_types_by_name['Velocities'] = _VELOCITIES + +Velocities = _reflection.GeneratedProtocolMessageType('Velocities', (_message.Message,), dict( + DESCRIPTOR = _VELOCITIES, + __module__ = 'velocities_pb2' + # @@protoc_insertion_point(class_scope:Velocities) + )) +_sym_db.RegisterMessage(Velocities) + + +# @@protoc_insertion_point(module_scope) diff --git a/utils/ticks_calibration/otto_ticks_calibration/Core/Inc/encoder.h b/utils/ticks_calibration/otto_ticks_calibration/Core/Inc/encoder.h index bd05dfb..1bd94ab 100644 --- a/utils/ticks_calibration/otto_ticks_calibration/Core/Inc/encoder.h +++ b/utils/ticks_calibration/otto_ticks_calibration/Core/Inc/encoder.h @@ -19,8 +19,8 @@ class Encoder { ticks_per_meter_ = 0; } -// Encoder(TIM_HandleTypeDef *timer, float wheel_circ); - Encoder(TIM_HandleTypeDef *timer, int ticks_per_meters); + Encoder(TIM_HandleTypeDef *timer, float wheel_circ); +// Encoder(TIM_HandleTypeDef *timer, int ticks_per_meters); void Setup(); diff --git a/utils/ticks_calibration/otto_ticks_calibration/Core/Src/encoder.cpp b/utils/ticks_calibration/otto_ticks_calibration/Core/Src/encoder.cpp index 5deedf6..53d0fec 100644 --- a/utils/ticks_calibration/otto_ticks_calibration/Core/Src/encoder.cpp +++ b/utils/ticks_calibration/otto_ticks_calibration/Core/Src/encoder.cpp @@ -1,16 +1,16 @@ #include "encoder.h" -//Encoder::Encoder(TIM_HandleTypeDef *timer, float wheel_circ) { -// timer_ = timer; -// wheel_circumference_ = wheel_circ; -// -//} - -Encoder::Encoder(TIM_HandleTypeDef *timer, int ticks_per_meter) { +Encoder::Encoder(TIM_HandleTypeDef *timer, float wheel_circ) { timer_ = timer; - ticks_per_meter_ = ticks_per_meter; + wheel_circumference_ = wheel_circ; } +// +//Encoder::Encoder(TIM_HandleTypeDef *timer, int ticks_per_meter) { +// timer_ = timer; +// ticks_per_meter_ = ticks_per_meter; +// +//} void Encoder::Setup() { HAL_TIM_Encoder_Start(timer_, TIM_CHANNEL_ALL); @@ -26,17 +26,17 @@ void Encoder::UpdateValues() { this->ResetCount(); } -//float Encoder::GetMeters() { -// float meters = ((float) this->ticks_ * this->wheel_circumference_) -// / TICKS_PER_REVOLUTION; -// return meters; -//} - float Encoder::GetMeters() { - float meters = (((float) this->ticks_) / this->ticks_per_meter_); + float meters = ((float) this->ticks_ * this->wheel_circumference_) + / TICKS_PER_REVOLUTION; return meters; } +//float Encoder::GetMeters() { +// float meters = (((float) this->ticks_) / this->ticks_per_meter_); +// return meters; +//} + float Encoder::GetLinearVelocity() { this->UpdateValues(); diff --git a/utils/ticks_calibration/otto_ticks_calibration/Core/Src/main.cpp b/utils/ticks_calibration/otto_ticks_calibration/Core/Src/main.cpp index a9b5855..ce0bce7 100644 --- a/utils/ticks_calibration/otto_ticks_calibration/Core/Src/main.cpp +++ b/utils/ticks_calibration/otto_ticks_calibration/Core/Src/main.cpp @@ -59,7 +59,7 @@ UART_HandleTypeDef huart6; /* USER CODE BEGIN PV */ //Odometry -Encoder right_encoder = Encoder(&htim5, RIGHT_TICKS_PER_METER); +Encoder right_encoder = Encoder(&htim5, RIGHT_WHEEL_CIRCUMFERENCE); Encoder left_encoder = Encoder(&htim2, LEFT_TICKS_PER_METER); Odometry odom = Odometry(); float left_velocity = 0; @@ -585,20 +585,26 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { //TIMER 100Hz PID control if (htim->Instance == TIM3) { - left_velocity = left_encoder.GetLinearVelocity(); - left_dutycycle = left_pid.update(left_velocity); - left_motor.set_speed(left_dutycycle); + left_pid.set(0.5); + right_pid.set(0.5); + cross_pid.set(0); + +// left_velocity = left_encoder.GetLinearVelocity(); +// left_dutycycle = left_pid.update(left_velocity); +// left_motor.set_speed(left_dutycycle); right_velocity = right_encoder.GetLinearVelocity(); right_dutycycle = right_pid.update(right_velocity); right_motor.set_speed(right_dutycycle); - float difference = left_velocity - right_velocity; - - int cross_dutycycle = cross_pid.update(difference); +// float difference = left_velocity - right_velocity; +// +// int cross_dutycycle = cross_pid.update(difference); +// +// left_dutycycle += cross_dutycycle; +// right_dutycycle -= cross_dutycycle; - left_dutycycle += cross_dutycycle; - right_dutycycle -= cross_dutycycle; + HAL_UART_Transmit(&huart6, (uint8_t*) &right_velocity, 4, 100); } diff --git a/utils/ticks_calibration/otto_ticks_calibration/Debug/Core/Src/subdir.mk b/utils/ticks_calibration/otto_ticks_calibration/Debug/Core/Src/subdir.mk new file mode 100644 index 0000000..4fcd8af --- /dev/null +++ b/utils/ticks_calibration/otto_ticks_calibration/Debug/Core/Src/subdir.mk @@ -0,0 +1,53 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/stm32f7xx_hal_msp.c \ +../Core/Src/stm32f7xx_it.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32f7xx.c + +CPP_SRCS += \ +../Core/Src/encoder.cpp \ +../Core/Src/main.cpp + +OBJS += \ +./Core/Src/encoder.o \ +./Core/Src/main.o \ +./Core/Src/stm32f7xx_hal_msp.o \ +./Core/Src/stm32f7xx_it.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32f7xx.o + +C_DEPS += \ +./Core/Src/stm32f7xx_hal_msp.d \ +./Core/Src/stm32f7xx_it.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32f7xx.d + +CPP_DEPS += \ +./Core/Src/encoder.d \ +./Core/Src/main.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/encoder.o: ../Core/Src/encoder.cpp + arm-none-eabi-g++ "$<" -mcpu=cortex-m7 -std=gnu++14 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-threadsafe-statics -fno-use-cxa-atexit -Wall -fstack-usage -MMD -MP -MF"Core/Src/encoder.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/main.o: ../Core/Src/main.cpp + arm-none-eabi-g++ "$<" -mcpu=cortex-m7 -std=gnu++14 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-threadsafe-statics -fno-use-cxa-atexit -Wall -fstack-usage -MMD -MP -MF"Core/Src/main.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32f7xx_hal_msp.o: ../Core/Src/stm32f7xx_hal_msp.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f7xx_hal_msp.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32f7xx_it.o: ../Core/Src/stm32f7xx_it.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f7xx_it.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/syscalls.o: ../Core/Src/syscalls.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/syscalls.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/sysmem.o: ../Core/Src/sysmem.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/sysmem.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/system_stm32f7xx.o: ../Core/Src/system_stm32f7xx.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/system_stm32f7xx.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/utils/ticks_calibration/otto_ticks_calibration/Debug/Core/Startup/subdir.mk b/utils/ticks_calibration/otto_ticks_calibration/Debug/Core/Startup/subdir.mk new file mode 100644 index 0000000..481e2a5 --- /dev/null +++ b/utils/ticks_calibration/otto_ticks_calibration/Debug/Core/Startup/subdir.mk @@ -0,0 +1,16 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32f767zitx.s + +OBJS += \ +./Core/Startup/startup_stm32f767zitx.o + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/%.o: ../Core/Startup/%.s + arm-none-eabi-gcc -mcpu=cortex-m7 -g3 -c -x assembler-with-cpp --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" "$<" + diff --git a/utils/ticks_calibration/otto_ticks_calibration/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk b/utils/ticks_calibration/otto_ticks_calibration/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk new file mode 100644 index 0000000..2a0a6ce --- /dev/null +++ b/utils/ticks_calibration/otto_ticks_calibration/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,104 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c + +OBJS += \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + +C_DEPS += \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/utils/ticks_calibration/otto_ticks_calibration/Debug/makefile b/utils/ticks_calibration/otto_ticks_calibration/Debug/makefile new file mode 100644 index 0000000..d402658 --- /dev/null +++ b/utils/ticks_calibration/otto_ticks_calibration/Debug/makefile @@ -0,0 +1,80 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +otto_ticks_calibration.elf \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +otto_ticks_calibration.list \ + + +# All Target +all: otto_ticks_calibration.elf secondary-outputs + +# Tool invocations +otto_ticks_calibration.elf: $(OBJS) $(USER_OBJS) /home/fdila/Projects/otto/utils/ticks_calibration/otto_ticks_calibration/STM32F767ZITX_FLASH.ld + arm-none-eabi-g++ -o "otto_ticks_calibration.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m7 -T"/home/fdila/Projects/otto/utils/ticks_calibration/otto_ticks_calibration/STM32F767ZITX_FLASH.ld" -Wl,-Map="otto_ticks_calibration.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +otto_ticks_calibration.list: $(EXECUTABLES) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "otto_ticks_calibration.list" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) * + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets diff --git a/utils/ticks_calibration/otto_ticks_calibration/Debug/objects.list b/utils/ticks_calibration/otto_ticks_calibration/Debug/objects.list new file mode 100644 index 0000000..c7c9831 --- /dev/null +++ b/utils/ticks_calibration/otto_ticks_calibration/Debug/objects.list @@ -0,0 +1,26 @@ +"Core/Src/encoder.o" +"Core/Src/main.o" +"Core/Src/stm32f7xx_hal_msp.o" +"Core/Src/stm32f7xx_it.o" +"Core/Src/syscalls.o" +"Core/Src/sysmem.o" +"Core/Src/system_stm32f7xx.o" +"Core/Startup/startup_stm32f767zitx.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o" diff --git a/utils/ticks_calibration/otto_ticks_calibration/Debug/objects.mk b/utils/ticks_calibration/otto_ticks_calibration/Debug/objects.mk new file mode 100644 index 0000000..742c2da --- /dev/null +++ b/utils/ticks_calibration/otto_ticks_calibration/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/utils/ticks_calibration/otto_ticks_calibration/Debug/otto_ticks_calibration.list b/utils/ticks_calibration/otto_ticks_calibration/Debug/otto_ticks_calibration.list new file mode 100644 index 0000000..2e620cd --- /dev/null +++ b/utils/ticks_calibration/otto_ticks_calibration/Debug/otto_ticks_calibration.list @@ -0,0 +1,13869 @@ + +otto_ticks_calibration.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 000001f8 08000000 08000000 00010000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 000052ac 080001f8 080001f8 000101f8 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00000018 080054a4 080054a4 000154a4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 080054bc 080054bc 00020010 2**0 + CONTENTS + 4 .ARM 00000008 080054bc 080054bc 000154bc 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 080054c4 080054c4 00020010 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000008 080054c4 080054c4 000154c4 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .fini_array 00000004 080054cc 080054cc 000154cc 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 .data 00000010 20000000 080054d0 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 000002f4 20000010 080054e0 00020010 2**2 + ALLOC + 10 ._user_heap_stack 00000604 20000304 080054e0 00020304 2**0 + ALLOC + 11 .ARM.attributes 0000002e 00000000 00000000 00020010 2**0 + CONTENTS, READONLY + 12 .debug_info 0000dbdb 00000000 00000000 0002003e 2**0 + CONTENTS, READONLY, DEBUGGING + 13 .debug_abbrev 00001e34 00000000 00000000 0002dc19 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_aranges 00000d70 00000000 00000000 0002fa50 2**3 + CONTENTS, READONLY, DEBUGGING + 15 .debug_ranges 00000c88 00000000 00000000 000307c0 2**3 + CONTENTS, READONLY, DEBUGGING + 16 .debug_macro 00028243 00000000 00000000 00031448 2**0 + CONTENTS, READONLY, DEBUGGING + 17 .debug_line 00009a7c 00000000 00000000 0005968b 2**0 + CONTENTS, READONLY, DEBUGGING + 18 .debug_str 000f1e12 00000000 00000000 00063107 2**0 + CONTENTS, READONLY, DEBUGGING + 19 .comment 0000007b 00000000 00000000 00154f19 2**0 + CONTENTS, READONLY + 20 .debug_frame 00003884 00000000 00000000 00154f94 2**2 + CONTENTS, READONLY, DEBUGGING + +Disassembly of section .text: + +080001f8 <__do_global_dtors_aux>: + 80001f8: b510 push {r4, lr} + 80001fa: 4c05 ldr r4, [pc, #20] ; (8000210 <__do_global_dtors_aux+0x18>) + 80001fc: 7823 ldrb r3, [r4, #0] + 80001fe: b933 cbnz r3, 800020e <__do_global_dtors_aux+0x16> + 8000200: 4b04 ldr r3, [pc, #16] ; (8000214 <__do_global_dtors_aux+0x1c>) + 8000202: b113 cbz r3, 800020a <__do_global_dtors_aux+0x12> + 8000204: 4804 ldr r0, [pc, #16] ; (8000218 <__do_global_dtors_aux+0x20>) + 8000206: f3af 8000 nop.w + 800020a: 2301 movs r3, #1 + 800020c: 7023 strb r3, [r4, #0] + 800020e: bd10 pop {r4, pc} + 8000210: 20000010 .word 0x20000010 + 8000214: 00000000 .word 0x00000000 + 8000218: 0800548c .word 0x0800548c + +0800021c : + 800021c: b508 push {r3, lr} + 800021e: 4b03 ldr r3, [pc, #12] ; (800022c ) + 8000220: b11b cbz r3, 800022a + 8000222: 4903 ldr r1, [pc, #12] ; (8000230 ) + 8000224: 4803 ldr r0, [pc, #12] ; (8000234 ) + 8000226: f3af 8000 nop.w + 800022a: bd08 pop {r3, pc} + 800022c: 00000000 .word 0x00000000 + 8000230: 20000014 .word 0x20000014 + 8000234: 0800548c .word 0x0800548c + +08000238 <__aeabi_uldivmod>: + 8000238: b953 cbnz r3, 8000250 <__aeabi_uldivmod+0x18> + 800023a: b94a cbnz r2, 8000250 <__aeabi_uldivmod+0x18> + 800023c: 2900 cmp r1, #0 + 800023e: bf08 it eq + 8000240: 2800 cmpeq r0, #0 + 8000242: bf1c itt ne + 8000244: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff + 8000248: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff + 800024c: f000 b972 b.w 8000534 <__aeabi_idiv0> + 8000250: f1ad 0c08 sub.w ip, sp, #8 + 8000254: e96d ce04 strd ip, lr, [sp, #-16]! + 8000258: f000 f806 bl 8000268 <__udivmoddi4> + 800025c: f8dd e004 ldr.w lr, [sp, #4] + 8000260: e9dd 2302 ldrd r2, r3, [sp, #8] + 8000264: b004 add sp, #16 + 8000266: 4770 bx lr + +08000268 <__udivmoddi4>: + 8000268: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800026c: 9e08 ldr r6, [sp, #32] + 800026e: 4604 mov r4, r0 + 8000270: 4688 mov r8, r1 + 8000272: 2b00 cmp r3, #0 + 8000274: d14b bne.n 800030e <__udivmoddi4+0xa6> + 8000276: 428a cmp r2, r1 + 8000278: 4615 mov r5, r2 + 800027a: d967 bls.n 800034c <__udivmoddi4+0xe4> + 800027c: fab2 f282 clz r2, r2 + 8000280: b14a cbz r2, 8000296 <__udivmoddi4+0x2e> + 8000282: f1c2 0720 rsb r7, r2, #32 + 8000286: fa01 f302 lsl.w r3, r1, r2 + 800028a: fa20 f707 lsr.w r7, r0, r7 + 800028e: 4095 lsls r5, r2 + 8000290: ea47 0803 orr.w r8, r7, r3 + 8000294: 4094 lsls r4, r2 + 8000296: ea4f 4e15 mov.w lr, r5, lsr #16 + 800029a: 0c23 lsrs r3, r4, #16 + 800029c: fbb8 f7fe udiv r7, r8, lr + 80002a0: fa1f fc85 uxth.w ip, r5 + 80002a4: fb0e 8817 mls r8, lr, r7, r8 + 80002a8: ea43 4308 orr.w r3, r3, r8, lsl #16 + 80002ac: fb07 f10c mul.w r1, r7, ip + 80002b0: 4299 cmp r1, r3 + 80002b2: d909 bls.n 80002c8 <__udivmoddi4+0x60> + 80002b4: 18eb adds r3, r5, r3 + 80002b6: f107 30ff add.w r0, r7, #4294967295 ; 0xffffffff + 80002ba: f080 811b bcs.w 80004f4 <__udivmoddi4+0x28c> + 80002be: 4299 cmp r1, r3 + 80002c0: f240 8118 bls.w 80004f4 <__udivmoddi4+0x28c> + 80002c4: 3f02 subs r7, #2 + 80002c6: 442b add r3, r5 + 80002c8: 1a5b subs r3, r3, r1 + 80002ca: b2a4 uxth r4, r4 + 80002cc: fbb3 f0fe udiv r0, r3, lr + 80002d0: fb0e 3310 mls r3, lr, r0, r3 + 80002d4: ea44 4403 orr.w r4, r4, r3, lsl #16 + 80002d8: fb00 fc0c mul.w ip, r0, ip + 80002dc: 45a4 cmp ip, r4 + 80002de: d909 bls.n 80002f4 <__udivmoddi4+0x8c> + 80002e0: 192c adds r4, r5, r4 + 80002e2: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff + 80002e6: f080 8107 bcs.w 80004f8 <__udivmoddi4+0x290> + 80002ea: 45a4 cmp ip, r4 + 80002ec: f240 8104 bls.w 80004f8 <__udivmoddi4+0x290> + 80002f0: 3802 subs r0, #2 + 80002f2: 442c add r4, r5 + 80002f4: ea40 4007 orr.w r0, r0, r7, lsl #16 + 80002f8: eba4 040c sub.w r4, r4, ip + 80002fc: 2700 movs r7, #0 + 80002fe: b11e cbz r6, 8000308 <__udivmoddi4+0xa0> + 8000300: 40d4 lsrs r4, r2 + 8000302: 2300 movs r3, #0 + 8000304: e9c6 4300 strd r4, r3, [r6] + 8000308: 4639 mov r1, r7 + 800030a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800030e: 428b cmp r3, r1 + 8000310: d909 bls.n 8000326 <__udivmoddi4+0xbe> + 8000312: 2e00 cmp r6, #0 + 8000314: f000 80eb beq.w 80004ee <__udivmoddi4+0x286> + 8000318: 2700 movs r7, #0 + 800031a: e9c6 0100 strd r0, r1, [r6] + 800031e: 4638 mov r0, r7 + 8000320: 4639 mov r1, r7 + 8000322: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000326: fab3 f783 clz r7, r3 + 800032a: 2f00 cmp r7, #0 + 800032c: d147 bne.n 80003be <__udivmoddi4+0x156> + 800032e: 428b cmp r3, r1 + 8000330: d302 bcc.n 8000338 <__udivmoddi4+0xd0> + 8000332: 4282 cmp r2, r0 + 8000334: f200 80fa bhi.w 800052c <__udivmoddi4+0x2c4> + 8000338: 1a84 subs r4, r0, r2 + 800033a: eb61 0303 sbc.w r3, r1, r3 + 800033e: 2001 movs r0, #1 + 8000340: 4698 mov r8, r3 + 8000342: 2e00 cmp r6, #0 + 8000344: d0e0 beq.n 8000308 <__udivmoddi4+0xa0> + 8000346: e9c6 4800 strd r4, r8, [r6] + 800034a: e7dd b.n 8000308 <__udivmoddi4+0xa0> + 800034c: b902 cbnz r2, 8000350 <__udivmoddi4+0xe8> + 800034e: deff udf #255 ; 0xff + 8000350: fab2 f282 clz r2, r2 + 8000354: 2a00 cmp r2, #0 + 8000356: f040 808f bne.w 8000478 <__udivmoddi4+0x210> + 800035a: 1b49 subs r1, r1, r5 + 800035c: ea4f 4e15 mov.w lr, r5, lsr #16 + 8000360: fa1f f885 uxth.w r8, r5 + 8000364: 2701 movs r7, #1 + 8000366: fbb1 fcfe udiv ip, r1, lr + 800036a: 0c23 lsrs r3, r4, #16 + 800036c: fb0e 111c mls r1, lr, ip, r1 + 8000370: ea43 4301 orr.w r3, r3, r1, lsl #16 + 8000374: fb08 f10c mul.w r1, r8, ip + 8000378: 4299 cmp r1, r3 + 800037a: d907 bls.n 800038c <__udivmoddi4+0x124> + 800037c: 18eb adds r3, r5, r3 + 800037e: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff + 8000382: d202 bcs.n 800038a <__udivmoddi4+0x122> + 8000384: 4299 cmp r1, r3 + 8000386: f200 80cd bhi.w 8000524 <__udivmoddi4+0x2bc> + 800038a: 4684 mov ip, r0 + 800038c: 1a59 subs r1, r3, r1 + 800038e: b2a3 uxth r3, r4 + 8000390: fbb1 f0fe udiv r0, r1, lr + 8000394: fb0e 1410 mls r4, lr, r0, r1 + 8000398: ea43 4404 orr.w r4, r3, r4, lsl #16 + 800039c: fb08 f800 mul.w r8, r8, r0 + 80003a0: 45a0 cmp r8, r4 + 80003a2: d907 bls.n 80003b4 <__udivmoddi4+0x14c> + 80003a4: 192c adds r4, r5, r4 + 80003a6: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff + 80003aa: d202 bcs.n 80003b2 <__udivmoddi4+0x14a> + 80003ac: 45a0 cmp r8, r4 + 80003ae: f200 80b6 bhi.w 800051e <__udivmoddi4+0x2b6> + 80003b2: 4618 mov r0, r3 + 80003b4: eba4 0408 sub.w r4, r4, r8 + 80003b8: ea40 400c orr.w r0, r0, ip, lsl #16 + 80003bc: e79f b.n 80002fe <__udivmoddi4+0x96> + 80003be: f1c7 0c20 rsb ip, r7, #32 + 80003c2: 40bb lsls r3, r7 + 80003c4: fa22 fe0c lsr.w lr, r2, ip + 80003c8: ea4e 0e03 orr.w lr, lr, r3 + 80003cc: fa01 f407 lsl.w r4, r1, r7 + 80003d0: fa20 f50c lsr.w r5, r0, ip + 80003d4: fa21 f30c lsr.w r3, r1, ip + 80003d8: ea4f 481e mov.w r8, lr, lsr #16 + 80003dc: 4325 orrs r5, r4 + 80003de: fbb3 f9f8 udiv r9, r3, r8 + 80003e2: 0c2c lsrs r4, r5, #16 + 80003e4: fb08 3319 mls r3, r8, r9, r3 + 80003e8: fa1f fa8e uxth.w sl, lr + 80003ec: ea44 4303 orr.w r3, r4, r3, lsl #16 + 80003f0: fb09 f40a mul.w r4, r9, sl + 80003f4: 429c cmp r4, r3 + 80003f6: fa02 f207 lsl.w r2, r2, r7 + 80003fa: fa00 f107 lsl.w r1, r0, r7 + 80003fe: d90b bls.n 8000418 <__udivmoddi4+0x1b0> + 8000400: eb1e 0303 adds.w r3, lr, r3 + 8000404: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff + 8000408: f080 8087 bcs.w 800051a <__udivmoddi4+0x2b2> + 800040c: 429c cmp r4, r3 + 800040e: f240 8084 bls.w 800051a <__udivmoddi4+0x2b2> + 8000412: f1a9 0902 sub.w r9, r9, #2 + 8000416: 4473 add r3, lr + 8000418: 1b1b subs r3, r3, r4 + 800041a: b2ad uxth r5, r5 + 800041c: fbb3 f0f8 udiv r0, r3, r8 + 8000420: fb08 3310 mls r3, r8, r0, r3 + 8000424: ea45 4403 orr.w r4, r5, r3, lsl #16 + 8000428: fb00 fa0a mul.w sl, r0, sl + 800042c: 45a2 cmp sl, r4 + 800042e: d908 bls.n 8000442 <__udivmoddi4+0x1da> + 8000430: eb1e 0404 adds.w r4, lr, r4 + 8000434: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff + 8000438: d26b bcs.n 8000512 <__udivmoddi4+0x2aa> + 800043a: 45a2 cmp sl, r4 + 800043c: d969 bls.n 8000512 <__udivmoddi4+0x2aa> + 800043e: 3802 subs r0, #2 + 8000440: 4474 add r4, lr + 8000442: ea40 4009 orr.w r0, r0, r9, lsl #16 + 8000446: fba0 8902 umull r8, r9, r0, r2 + 800044a: eba4 040a sub.w r4, r4, sl + 800044e: 454c cmp r4, r9 + 8000450: 46c2 mov sl, r8 + 8000452: 464b mov r3, r9 + 8000454: d354 bcc.n 8000500 <__udivmoddi4+0x298> + 8000456: d051 beq.n 80004fc <__udivmoddi4+0x294> + 8000458: 2e00 cmp r6, #0 + 800045a: d069 beq.n 8000530 <__udivmoddi4+0x2c8> + 800045c: ebb1 050a subs.w r5, r1, sl + 8000460: eb64 0403 sbc.w r4, r4, r3 + 8000464: fa04 fc0c lsl.w ip, r4, ip + 8000468: 40fd lsrs r5, r7 + 800046a: 40fc lsrs r4, r7 + 800046c: ea4c 0505 orr.w r5, ip, r5 + 8000470: e9c6 5400 strd r5, r4, [r6] + 8000474: 2700 movs r7, #0 + 8000476: e747 b.n 8000308 <__udivmoddi4+0xa0> + 8000478: f1c2 0320 rsb r3, r2, #32 + 800047c: fa20 f703 lsr.w r7, r0, r3 + 8000480: 4095 lsls r5, r2 + 8000482: fa01 f002 lsl.w r0, r1, r2 + 8000486: fa21 f303 lsr.w r3, r1, r3 + 800048a: ea4f 4e15 mov.w lr, r5, lsr #16 + 800048e: 4338 orrs r0, r7 + 8000490: 0c01 lsrs r1, r0, #16 + 8000492: fbb3 f7fe udiv r7, r3, lr + 8000496: fa1f f885 uxth.w r8, r5 + 800049a: fb0e 3317 mls r3, lr, r7, r3 + 800049e: ea41 4103 orr.w r1, r1, r3, lsl #16 + 80004a2: fb07 f308 mul.w r3, r7, r8 + 80004a6: 428b cmp r3, r1 + 80004a8: fa04 f402 lsl.w r4, r4, r2 + 80004ac: d907 bls.n 80004be <__udivmoddi4+0x256> + 80004ae: 1869 adds r1, r5, r1 + 80004b0: f107 3cff add.w ip, r7, #4294967295 ; 0xffffffff + 80004b4: d22f bcs.n 8000516 <__udivmoddi4+0x2ae> + 80004b6: 428b cmp r3, r1 + 80004b8: d92d bls.n 8000516 <__udivmoddi4+0x2ae> + 80004ba: 3f02 subs r7, #2 + 80004bc: 4429 add r1, r5 + 80004be: 1acb subs r3, r1, r3 + 80004c0: b281 uxth r1, r0 + 80004c2: fbb3 f0fe udiv r0, r3, lr + 80004c6: fb0e 3310 mls r3, lr, r0, r3 + 80004ca: ea41 4103 orr.w r1, r1, r3, lsl #16 + 80004ce: fb00 f308 mul.w r3, r0, r8 + 80004d2: 428b cmp r3, r1 + 80004d4: d907 bls.n 80004e6 <__udivmoddi4+0x27e> + 80004d6: 1869 adds r1, r5, r1 + 80004d8: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff + 80004dc: d217 bcs.n 800050e <__udivmoddi4+0x2a6> + 80004de: 428b cmp r3, r1 + 80004e0: d915 bls.n 800050e <__udivmoddi4+0x2a6> + 80004e2: 3802 subs r0, #2 + 80004e4: 4429 add r1, r5 + 80004e6: 1ac9 subs r1, r1, r3 + 80004e8: ea40 4707 orr.w r7, r0, r7, lsl #16 + 80004ec: e73b b.n 8000366 <__udivmoddi4+0xfe> + 80004ee: 4637 mov r7, r6 + 80004f0: 4630 mov r0, r6 + 80004f2: e709 b.n 8000308 <__udivmoddi4+0xa0> + 80004f4: 4607 mov r7, r0 + 80004f6: e6e7 b.n 80002c8 <__udivmoddi4+0x60> + 80004f8: 4618 mov r0, r3 + 80004fa: e6fb b.n 80002f4 <__udivmoddi4+0x8c> + 80004fc: 4541 cmp r1, r8 + 80004fe: d2ab bcs.n 8000458 <__udivmoddi4+0x1f0> + 8000500: ebb8 0a02 subs.w sl, r8, r2 + 8000504: eb69 020e sbc.w r2, r9, lr + 8000508: 3801 subs r0, #1 + 800050a: 4613 mov r3, r2 + 800050c: e7a4 b.n 8000458 <__udivmoddi4+0x1f0> + 800050e: 4660 mov r0, ip + 8000510: e7e9 b.n 80004e6 <__udivmoddi4+0x27e> + 8000512: 4618 mov r0, r3 + 8000514: e795 b.n 8000442 <__udivmoddi4+0x1da> + 8000516: 4667 mov r7, ip + 8000518: e7d1 b.n 80004be <__udivmoddi4+0x256> + 800051a: 4681 mov r9, r0 + 800051c: e77c b.n 8000418 <__udivmoddi4+0x1b0> + 800051e: 3802 subs r0, #2 + 8000520: 442c add r4, r5 + 8000522: e747 b.n 80003b4 <__udivmoddi4+0x14c> + 8000524: f1ac 0c02 sub.w ip, ip, #2 + 8000528: 442b add r3, r5 + 800052a: e72f b.n 800038c <__udivmoddi4+0x124> + 800052c: 4638 mov r0, r7 + 800052e: e708 b.n 8000342 <__udivmoddi4+0xda> + 8000530: 4637 mov r7, r6 + 8000532: e6e9 b.n 8000308 <__udivmoddi4+0xa0> + +08000534 <__aeabi_idiv0>: + 8000534: 4770 bx lr + 8000536: bf00 nop + +08000538 <_ZN7Encoder8GetCountEv>: +// Encoder(TIM_HandleTypeDef *timer, int ticks_per_meters); + + + void Setup(); + + int GetCount() { + 8000538: b480 push {r7} + 800053a: b085 sub sp, #20 + 800053c: af00 add r7, sp, #0 + 800053e: 6078 str r0, [r7, #4] + int count = ((int) __HAL_TIM_GET_COUNTER(this->timer_) + 8000540: 687b ldr r3, [r7, #4] + 8000542: 681b ldr r3, [r3, #0] + 8000544: 681b ldr r3, [r3, #0] + 8000546: 6a5a ldr r2, [r3, #36] ; 0x24 + - ((this->timer_->Init.Period) / 2)); + 8000548: 687b ldr r3, [r7, #4] + 800054a: 681b ldr r3, [r3, #0] + 800054c: 68db ldr r3, [r3, #12] + 800054e: 085b lsrs r3, r3, #1 + 8000550: 1ad3 subs r3, r2, r3 + 8000552: 60fb str r3, [r7, #12] + return count; + 8000554: 68fb ldr r3, [r7, #12] + } + 8000556: 4618 mov r0, r3 + 8000558: 3714 adds r7, #20 + 800055a: 46bd mov sp, r7 + 800055c: f85d 7b04 ldr.w r7, [sp], #4 + 8000560: 4770 bx lr + +08000562 <_ZN7Encoder10ResetCountEv>: + + void ResetCount() { + 8000562: b480 push {r7} + 8000564: b083 sub sp, #12 + 8000566: af00 add r7, sp, #0 + 8000568: 6078 str r0, [r7, #4] + //set counter to half its maximum value + __HAL_TIM_SET_COUNTER(timer_, (timer_->Init.Period / 2)); + 800056a: 687b ldr r3, [r7, #4] + 800056c: 681b ldr r3, [r3, #0] + 800056e: 68da ldr r2, [r3, #12] + 8000570: 687b ldr r3, [r7, #4] + 8000572: 681b ldr r3, [r3, #0] + 8000574: 681b ldr r3, [r3, #0] + 8000576: 0852 lsrs r2, r2, #1 + 8000578: 625a str r2, [r3, #36] ; 0x24 + } + 800057a: bf00 nop + 800057c: 370c adds r7, #12 + 800057e: 46bd mov sp, r7 + 8000580: f85d 7b04 ldr.w r7, [sp], #4 + 8000584: 4770 bx lr + +08000586 <_ZN7EncoderC1EP17TIM_HandleTypeDeff>: +#include "encoder.h" + +Encoder::Encoder(TIM_HandleTypeDef *timer, float wheel_circ) { + 8000586: b480 push {r7} + 8000588: b085 sub sp, #20 + 800058a: af00 add r7, sp, #0 + 800058c: 60f8 str r0, [r7, #12] + 800058e: 60b9 str r1, [r7, #8] + 8000590: ed87 0a01 vstr s0, [r7, #4] + timer_ = timer; + 8000594: 68fb ldr r3, [r7, #12] + 8000596: 68ba ldr r2, [r7, #8] + 8000598: 601a str r2, [r3, #0] + wheel_circumference_ = wheel_circ; + 800059a: 68fb ldr r3, [r7, #12] + 800059c: 687a ldr r2, [r7, #4] + 800059e: 611a str r2, [r3, #16] + +} + 80005a0: 68fb ldr r3, [r7, #12] + 80005a2: 4618 mov r0, r3 + 80005a4: 3714 adds r7, #20 + 80005a6: 46bd mov sp, r7 + 80005a8: f85d 7b04 ldr.w r7, [sp], #4 + 80005ac: 4770 bx lr + +080005ae <_ZN7Encoder5SetupEv>: +// timer_ = timer; +// ticks_per_meter_ = ticks_per_meter; +// +//} + +void Encoder::Setup() { + 80005ae: b580 push {r7, lr} + 80005b0: b082 sub sp, #8 + 80005b2: af00 add r7, sp, #0 + 80005b4: 6078 str r0, [r7, #4] + HAL_TIM_Encoder_Start(timer_, TIM_CHANNEL_ALL); + 80005b6: 687b ldr r3, [r7, #4] + 80005b8: 681b ldr r3, [r3, #0] + 80005ba: 213c movs r1, #60 ; 0x3c + 80005bc: 4618 mov r0, r3 + 80005be: f003 f84d bl 800365c + this->ResetCount(); + 80005c2: 6878 ldr r0, [r7, #4] + 80005c4: f7ff ffcd bl 8000562 <_ZN7Encoder10ResetCountEv> + this->previous_millis_ = 0; + 80005c8: 687b ldr r3, [r7, #4] + 80005ca: 2200 movs r2, #0 + 80005cc: 605a str r2, [r3, #4] + this->current_millis_ = HAL_GetTick(); + 80005ce: f001 fb61 bl 8001c94 + 80005d2: 4602 mov r2, r0 + 80005d4: 687b ldr r3, [r7, #4] + 80005d6: 609a str r2, [r3, #8] +} + 80005d8: bf00 nop + 80005da: 3708 adds r7, #8 + 80005dc: 46bd mov sp, r7 + 80005de: bd80 pop {r7, pc} + +080005e0 <_ZN7Encoder12UpdateValuesEv>: + +void Encoder::UpdateValues() { + 80005e0: b580 push {r7, lr} + 80005e2: b082 sub sp, #8 + 80005e4: af00 add r7, sp, #0 + 80005e6: 6078 str r0, [r7, #4] + this->previous_millis_ = this->current_millis_; + 80005e8: 687b ldr r3, [r7, #4] + 80005ea: 689a ldr r2, [r3, #8] + 80005ec: 687b ldr r3, [r7, #4] + 80005ee: 605a str r2, [r3, #4] + this->current_millis_ = HAL_GetTick(); + 80005f0: f001 fb50 bl 8001c94 + 80005f4: 4602 mov r2, r0 + 80005f6: 687b ldr r3, [r7, #4] + 80005f8: 609a str r2, [r3, #8] + this->ticks_ = this->GetCount(); + 80005fa: 6878 ldr r0, [r7, #4] + 80005fc: f7ff ff9c bl 8000538 <_ZN7Encoder8GetCountEv> + 8000600: 4602 mov r2, r0 + 8000602: 687b ldr r3, [r7, #4] + 8000604: 60da str r2, [r3, #12] + this->ResetCount(); + 8000606: 6878 ldr r0, [r7, #4] + 8000608: f7ff ffab bl 8000562 <_ZN7Encoder10ResetCountEv> +} + 800060c: bf00 nop + 800060e: 3708 adds r7, #8 + 8000610: 46bd mov sp, r7 + 8000612: bd80 pop {r7, pc} + +08000614 <_ZN7Encoder9GetMetersEv>: + +float Encoder::GetMeters() { + 8000614: b480 push {r7} + 8000616: b085 sub sp, #20 + 8000618: af00 add r7, sp, #0 + 800061a: 6078 str r0, [r7, #4] + float meters = ((float) this->ticks_ * this->wheel_circumference_) + 800061c: 687b ldr r3, [r7, #4] + 800061e: 68db ldr r3, [r3, #12] + 8000620: ee07 3a90 vmov s15, r3 + 8000624: eeb8 7ae7 vcvt.f32.s32 s14, s15 + 8000628: 687b ldr r3, [r7, #4] + 800062a: edd3 7a04 vldr s15, [r3, #16] + 800062e: ee27 7a27 vmul.f32 s14, s14, s15 + 8000632: eddf 6a08 vldr s13, [pc, #32] ; 8000654 <_ZN7Encoder9GetMetersEv+0x40> + 8000636: eec7 7a26 vdiv.f32 s15, s14, s13 + 800063a: edc7 7a03 vstr s15, [r7, #12] + / TICKS_PER_REVOLUTION; + return meters; + 800063e: 68fb ldr r3, [r7, #12] + 8000640: ee07 3a90 vmov s15, r3 +} + 8000644: eeb0 0a67 vmov.f32 s0, s15 + 8000648: 3714 adds r7, #20 + 800064a: 46bd mov sp, r7 + 800064c: f85d 7b04 ldr.w r7, [sp], #4 + 8000650: 4770 bx lr + 8000652: bf00 nop + 8000654: 48108800 .word 0x48108800 + +08000658 <_ZN7Encoder17GetLinearVelocityEv>: +// float meters = (((float) this->ticks_) / this->ticks_per_meter_); +// return meters; +//} + + +float Encoder::GetLinearVelocity() { + 8000658: b580 push {r7, lr} + 800065a: b086 sub sp, #24 + 800065c: af00 add r7, sp, #0 + 800065e: 6078 str r0, [r7, #4] + this->UpdateValues(); + 8000660: 6878 ldr r0, [r7, #4] + 8000662: f7ff ffbd bl 80005e0 <_ZN7Encoder12UpdateValuesEv> + float meters = this->GetMeters(); + 8000666: 6878 ldr r0, [r7, #4] + 8000668: f7ff ffd4 bl 8000614 <_ZN7Encoder9GetMetersEv> + 800066c: ed87 0a05 vstr s0, [r7, #20] + float deltaTime = this->current_millis_ - this->previous_millis_; + 8000670: 687b ldr r3, [r7, #4] + 8000672: 689a ldr r2, [r3, #8] + 8000674: 687b ldr r3, [r7, #4] + 8000676: 685b ldr r3, [r3, #4] + 8000678: 1ad3 subs r3, r2, r3 + 800067a: ee07 3a90 vmov s15, r3 + 800067e: eef8 7a67 vcvt.f32.u32 s15, s15 + 8000682: edc7 7a04 vstr s15, [r7, #16] + if (deltaTime == 0) + 8000686: edd7 7a04 vldr s15, [r7, #16] + 800068a: eef5 7a40 vcmp.f32 s15, #0.0 + 800068e: eef1 fa10 vmrs APSR_nzcv, fpscr + 8000692: d102 bne.n 800069a <_ZN7Encoder17GetLinearVelocityEv+0x42> + return 0; + 8000694: f04f 0300 mov.w r3, #0 + 8000698: e00c b.n 80006b4 <_ZN7Encoder17GetLinearVelocityEv+0x5c> + float linear_velocity = (meters / (deltaTime / 1000)); + 800069a: edd7 7a04 vldr s15, [r7, #16] + 800069e: eddf 6a09 vldr s13, [pc, #36] ; 80006c4 <_ZN7Encoder17GetLinearVelocityEv+0x6c> + 80006a2: ee87 7aa6 vdiv.f32 s14, s15, s13 + 80006a6: edd7 6a05 vldr s13, [r7, #20] + 80006aa: eec6 7a87 vdiv.f32 s15, s13, s14 + 80006ae: edc7 7a03 vstr s15, [r7, #12] + return linear_velocity; + 80006b2: 68fb ldr r3, [r7, #12] + 80006b4: ee07 3a90 vmov s15, r3 +} + 80006b8: eeb0 0a67 vmov.f32 s0, s15 + 80006bc: 3718 adds r7, #24 + 80006be: 46bd mov sp, r7 + 80006c0: bd80 pop {r7, pc} + 80006c2: bf00 nop + 80006c4: 447a0000 .word 0x447a0000 + +080006c8 <_ZN8OdometryC1Ev>: + float left_velocity_; + float right_velocity_; + + + public: + Odometry() { + 80006c8: b480 push {r7} + 80006ca: b083 sub sp, #12 + 80006cc: af00 add r7, sp, #0 + 80006ce: 6078 str r0, [r7, #4] + left_velocity_ = 0; + 80006d0: 687b ldr r3, [r7, #4] + 80006d2: f04f 0200 mov.w r2, #0 + 80006d6: 601a str r2, [r3, #0] + right_velocity_ = 0; + 80006d8: 687b ldr r3, [r7, #4] + 80006da: f04f 0200 mov.w r2, #0 + 80006de: 605a str r2, [r3, #4] + } + 80006e0: 687b ldr r3, [r7, #4] + 80006e2: 4618 mov r0, r3 + 80006e4: 370c adds r7, #12 + 80006e6: 46bd mov sp, r7 + 80006e8: f85d 7b04 ldr.w r7, [sp], #4 + 80006ec: 4770 bx lr + ... + +080006f0 <_ZN8Odometry12UpdateValuesEff>: + + void UpdateValues(float linear_vel, float angular_vel) { + 80006f0: b480 push {r7} + 80006f2: b085 sub sp, #20 + 80006f4: af00 add r7, sp, #0 + 80006f6: 60f8 str r0, [r7, #12] + 80006f8: ed87 0a02 vstr s0, [r7, #8] + 80006fc: edc7 0a01 vstr s1, [r7, #4] + left_velocity_ = linear_vel - (BASELINE * angular_vel)/2; + 8000700: edd7 7a02 vldr s15, [r7, #8] + 8000704: eeb7 6ae7 vcvt.f64.f32 d6, s15 + 8000708: edd7 7a01 vldr s15, [r7, #4] + 800070c: eeb7 7ae7 vcvt.f64.f32 d7, s15 + 8000710: ed9f 5b15 vldr d5, [pc, #84] ; 8000768 <_ZN8Odometry12UpdateValuesEff+0x78> + 8000714: ee27 5b05 vmul.f64 d5, d7, d5 + 8000718: eeb0 4b00 vmov.f64 d4, #0 ; 0x40000000 2.0 + 800071c: ee85 7b04 vdiv.f64 d7, d5, d4 + 8000720: ee36 7b47 vsub.f64 d7, d6, d7 + 8000724: eef7 7bc7 vcvt.f32.f64 s15, d7 + 8000728: 68fb ldr r3, [r7, #12] + 800072a: edc3 7a00 vstr s15, [r3] + right_velocity_ = linear_vel + (BASELINE * angular_vel)/2; + 800072e: edd7 7a02 vldr s15, [r7, #8] + 8000732: eeb7 6ae7 vcvt.f64.f32 d6, s15 + 8000736: edd7 7a01 vldr s15, [r7, #4] + 800073a: eeb7 7ae7 vcvt.f64.f32 d7, s15 + 800073e: ed9f 5b0a vldr d5, [pc, #40] ; 8000768 <_ZN8Odometry12UpdateValuesEff+0x78> + 8000742: ee27 5b05 vmul.f64 d5, d7, d5 + 8000746: eeb0 4b00 vmov.f64 d4, #0 ; 0x40000000 2.0 + 800074a: ee85 7b04 vdiv.f64 d7, d5, d4 + 800074e: ee36 7b07 vadd.f64 d7, d6, d7 + 8000752: eef7 7bc7 vcvt.f32.f64 s15, d7 + 8000756: 68fb ldr r3, [r7, #12] + 8000758: edc3 7a01 vstr s15, [r3, #4] + } + 800075c: bf00 nop + 800075e: 3714 adds r7, #20 + 8000760: 46bd mov sp, r7 + 8000762: f85d 7b04 ldr.w r7, [sp], #4 + 8000766: 4770 bx lr + 8000768: 33333333 .word 0x33333333 + 800076c: 3fd33333 .word 0x3fd33333 + +08000770 <_ZN8Odometry15GetLeftVelocityEv>: + + float GetLeftVelocity(){ + 8000770: b480 push {r7} + 8000772: b083 sub sp, #12 + 8000774: af00 add r7, sp, #0 + 8000776: 6078 str r0, [r7, #4] + return left_velocity_; + 8000778: 687b ldr r3, [r7, #4] + 800077a: 681b ldr r3, [r3, #0] + 800077c: ee07 3a90 vmov s15, r3 + } + 8000780: eeb0 0a67 vmov.f32 s0, s15 + 8000784: 370c adds r7, #12 + 8000786: 46bd mov sp, r7 + 8000788: f85d 7b04 ldr.w r7, [sp], #4 + 800078c: 4770 bx lr + +0800078e <_ZN8Odometry16GetRightVelocityEv>: + float GetRightVelocity(){ + 800078e: b480 push {r7} + 8000790: b083 sub sp, #12 + 8000792: af00 add r7, sp, #0 + 8000794: 6078 str r0, [r7, #4] + return right_velocity_; + 8000796: 687b ldr r3, [r7, #4] + 8000798: 685b ldr r3, [r3, #4] + 800079a: ee07 3a90 vmov s15, r3 + } + 800079e: eeb0 0a67 vmov.f32 s0, s15 + 80007a2: 370c adds r7, #12 + 80007a4: 46bd mov sp, r7 + 80007a6: f85d 7b04 ldr.w r7, [sp], #4 + 80007aa: 4770 bx lr + +080007ac <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>: + GPIO_TypeDef *dir_gpio_port_; + uint16_t dir_pin_; + TIM_HandleTypeDef *pwm_timer_; + uint32_t pwm_channel_; + + MotorController(GPIO_TypeDef *sleep_gpio_port, uint16_t sleep_pin, + 80007ac: b480 push {r7} + 80007ae: b085 sub sp, #20 + 80007b0: af00 add r7, sp, #0 + 80007b2: 60f8 str r0, [r7, #12] + 80007b4: 60b9 str r1, [r7, #8] + 80007b6: 603b str r3, [r7, #0] + 80007b8: 4613 mov r3, r2 + 80007ba: 80fb strh r3, [r7, #6] + GPIO_TypeDef *dir_gpio_port, uint16_t dir_pin, + TIM_HandleTypeDef *pwm_timer, uint32_t pwm_channel) { + this->sleep_gpio_port_ = sleep_gpio_port; + 80007bc: 68fb ldr r3, [r7, #12] + 80007be: 68ba ldr r2, [r7, #8] + 80007c0: 601a str r2, [r3, #0] + this->sleep_pin_ = sleep_pin; + 80007c2: 68fb ldr r3, [r7, #12] + 80007c4: 88fa ldrh r2, [r7, #6] + 80007c6: 809a strh r2, [r3, #4] + this->dir_gpio_port_ = dir_gpio_port; + 80007c8: 68fb ldr r3, [r7, #12] + 80007ca: 683a ldr r2, [r7, #0] + 80007cc: 609a str r2, [r3, #8] + this->dir_pin_ = dir_pin; + 80007ce: 68fb ldr r3, [r7, #12] + 80007d0: 8b3a ldrh r2, [r7, #24] + 80007d2: 819a strh r2, [r3, #12] + this->pwm_timer_ = pwm_timer; + 80007d4: 68fb ldr r3, [r7, #12] + 80007d6: 69fa ldr r2, [r7, #28] + 80007d8: 611a str r2, [r3, #16] + this->pwm_channel_ = pwm_channel; + 80007da: 68fb ldr r3, [r7, #12] + 80007dc: 6a3a ldr r2, [r7, #32] + 80007de: 615a str r2, [r3, #20] + } + 80007e0: 68fb ldr r3, [r7, #12] + 80007e2: 4618 mov r0, r3 + 80007e4: 3714 adds r7, #20 + 80007e6: 46bd mov sp, r7 + 80007e8: f85d 7b04 ldr.w r7, [sp], #4 + 80007ec: 4770 bx lr + +080007ee <_ZN15MotorController5setupEv>: + + void setup() { + 80007ee: b580 push {r7, lr} + 80007f0: b082 sub sp, #8 + 80007f2: af00 add r7, sp, #0 + 80007f4: 6078 str r0, [r7, #4] + HAL_TIM_PWM_Start(pwm_timer_, pwm_channel_); + 80007f6: 687b ldr r3, [r7, #4] + 80007f8: 691a ldr r2, [r3, #16] + 80007fa: 687b ldr r3, [r7, #4] + 80007fc: 695b ldr r3, [r3, #20] + 80007fe: 4619 mov r1, r3 + 8000800: 4610 mov r0, r2 + 8000802: f002 fe55 bl 80034b0 + } + 8000806: bf00 nop + 8000808: 3708 adds r7, #8 + 800080a: 46bd mov sp, r7 + 800080c: bd80 pop {r7, pc} + ... + +08000810 <_ZN15MotorController9set_speedEi>: + + void set_speed(int duty_cycle) { + 8000810: b580 push {r7, lr} + 8000812: b082 sub sp, #8 + 8000814: af00 add r7, sp, #0 + 8000816: 6078 str r0, [r7, #4] + 8000818: 6039 str r1, [r7, #0] + if (duty_cycle >= 0) { + 800081a: 683b ldr r3, [r7, #0] + 800081c: 2b00 cmp r3, #0 + 800081e: f2c0 8083 blt.w 8000928 <_ZN15MotorController9set_speedEi+0x118> + //set direction to forward + HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_SET); + 8000822: 687b ldr r3, [r7, #4] + 8000824: 6898 ldr r0, [r3, #8] + 8000826: 687b ldr r3, [r7, #4] + 8000828: 899b ldrh r3, [r3, #12] + 800082a: 2201 movs r2, #1 + 800082c: 4619 mov r1, r3 + 800082e: f001 fd1b bl 8002268 + + //check if duty_cycle exceeds maximum + if (duty_cycle > MAX_DUTY_CYCLE) + 8000832: 683b ldr r3, [r7, #0] + 8000834: f240 3216 movw r2, #790 ; 0x316 + 8000838: 4293 cmp r3, r2 + 800083a: dd3d ble.n 80008b8 <_ZN15MotorController9set_speedEi+0xa8> + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, MAX_DUTY_CYCLE); + 800083c: 687b ldr r3, [r7, #4] + 800083e: 695b ldr r3, [r3, #20] + 8000840: 2b00 cmp r3, #0 + 8000842: d106 bne.n 8000852 <_ZN15MotorController9set_speedEi+0x42> + 8000844: 687b ldr r3, [r7, #4] + 8000846: 691b ldr r3, [r3, #16] + 8000848: 681b ldr r3, [r3, #0] + 800084a: f240 3216 movw r2, #790 ; 0x316 + 800084e: 635a str r2, [r3, #52] ; 0x34 + 8000850: e0f5 b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 8000852: 687b ldr r3, [r7, #4] + 8000854: 695b ldr r3, [r3, #20] + 8000856: 2b04 cmp r3, #4 + 8000858: d106 bne.n 8000868 <_ZN15MotorController9set_speedEi+0x58> + 800085a: 687b ldr r3, [r7, #4] + 800085c: 691b ldr r3, [r3, #16] + 800085e: 681b ldr r3, [r3, #0] + 8000860: f240 3216 movw r2, #790 ; 0x316 + 8000864: 639a str r2, [r3, #56] ; 0x38 + 8000866: e0ea b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 8000868: 687b ldr r3, [r7, #4] + 800086a: 695b ldr r3, [r3, #20] + 800086c: 2b08 cmp r3, #8 + 800086e: d106 bne.n 800087e <_ZN15MotorController9set_speedEi+0x6e> + 8000870: 687b ldr r3, [r7, #4] + 8000872: 691b ldr r3, [r3, #16] + 8000874: 681b ldr r3, [r3, #0] + 8000876: f240 3216 movw r2, #790 ; 0x316 + 800087a: 63da str r2, [r3, #60] ; 0x3c + 800087c: e0df b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 800087e: 687b ldr r3, [r7, #4] + 8000880: 695b ldr r3, [r3, #20] + 8000882: 2b0c cmp r3, #12 + 8000884: d106 bne.n 8000894 <_ZN15MotorController9set_speedEi+0x84> + 8000886: 687b ldr r3, [r7, #4] + 8000888: 691b ldr r3, [r3, #16] + 800088a: 681b ldr r3, [r3, #0] + 800088c: f240 3216 movw r2, #790 ; 0x316 + 8000890: 641a str r2, [r3, #64] ; 0x40 + 8000892: e0d4 b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 8000894: 687b ldr r3, [r7, #4] + 8000896: 695b ldr r3, [r3, #20] + 8000898: 2b10 cmp r3, #16 + 800089a: d106 bne.n 80008aa <_ZN15MotorController9set_speedEi+0x9a> + 800089c: 687b ldr r3, [r7, #4] + 800089e: 691b ldr r3, [r3, #16] + 80008a0: 681b ldr r3, [r3, #0] + 80008a2: f240 3216 movw r2, #790 ; 0x316 + 80008a6: 659a str r2, [r3, #88] ; 0x58 + 80008a8: e0c9 b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 80008aa: 687b ldr r3, [r7, #4] + 80008ac: 691b ldr r3, [r3, #16] + 80008ae: 681b ldr r3, [r3, #0] + 80008b0: f240 3216 movw r2, #790 ; 0x316 + 80008b4: 65da str r2, [r3, #92] ; 0x5c + 80008b6: e0c2 b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + else + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle); + 80008b8: 687b ldr r3, [r7, #4] + 80008ba: 695b ldr r3, [r3, #20] + 80008bc: 2b00 cmp r3, #0 + 80008be: d105 bne.n 80008cc <_ZN15MotorController9set_speedEi+0xbc> + 80008c0: 683a ldr r2, [r7, #0] + 80008c2: 687b ldr r3, [r7, #4] + 80008c4: 691b ldr r3, [r3, #16] + 80008c6: 681b ldr r3, [r3, #0] + 80008c8: 635a str r2, [r3, #52] ; 0x34 + 80008ca: e0b8 b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 80008cc: 687b ldr r3, [r7, #4] + 80008ce: 695b ldr r3, [r3, #20] + 80008d0: 2b04 cmp r3, #4 + 80008d2: d105 bne.n 80008e0 <_ZN15MotorController9set_speedEi+0xd0> + 80008d4: 683a ldr r2, [r7, #0] + 80008d6: 687b ldr r3, [r7, #4] + 80008d8: 691b ldr r3, [r3, #16] + 80008da: 681b ldr r3, [r3, #0] + 80008dc: 639a str r2, [r3, #56] ; 0x38 + 80008de: e0ae b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 80008e0: 687b ldr r3, [r7, #4] + 80008e2: 695b ldr r3, [r3, #20] + 80008e4: 2b08 cmp r3, #8 + 80008e6: d105 bne.n 80008f4 <_ZN15MotorController9set_speedEi+0xe4> + 80008e8: 683a ldr r2, [r7, #0] + 80008ea: 687b ldr r3, [r7, #4] + 80008ec: 691b ldr r3, [r3, #16] + 80008ee: 681b ldr r3, [r3, #0] + 80008f0: 63da str r2, [r3, #60] ; 0x3c + 80008f2: e0a4 b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 80008f4: 687b ldr r3, [r7, #4] + 80008f6: 695b ldr r3, [r3, #20] + 80008f8: 2b0c cmp r3, #12 + 80008fa: d105 bne.n 8000908 <_ZN15MotorController9set_speedEi+0xf8> + 80008fc: 683a ldr r2, [r7, #0] + 80008fe: 687b ldr r3, [r7, #4] + 8000900: 691b ldr r3, [r3, #16] + 8000902: 681b ldr r3, [r3, #0] + 8000904: 641a str r2, [r3, #64] ; 0x40 + 8000906: e09a b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 8000908: 687b ldr r3, [r7, #4] + 800090a: 695b ldr r3, [r3, #20] + 800090c: 2b10 cmp r3, #16 + 800090e: d105 bne.n 800091c <_ZN15MotorController9set_speedEi+0x10c> + 8000910: 683a ldr r2, [r7, #0] + 8000912: 687b ldr r3, [r7, #4] + 8000914: 691b ldr r3, [r3, #16] + 8000916: 681b ldr r3, [r3, #0] + 8000918: 659a str r2, [r3, #88] ; 0x58 + 800091a: e090 b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 800091c: 683a ldr r2, [r7, #0] + 800091e: 687b ldr r3, [r7, #4] + 8000920: 691b ldr r3, [r3, #16] + 8000922: 681b ldr r3, [r3, #0] + 8000924: 65da str r2, [r3, #92] ; 0x5c + 8000926: e08a b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + + } else if (duty_cycle < 0){ + 8000928: 683b ldr r3, [r7, #0] + 800092a: 2b00 cmp r3, #0 + 800092c: f280 8087 bge.w 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + //set direction to backwards + HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_RESET); + 8000930: 687b ldr r3, [r7, #4] + 8000932: 6898 ldr r0, [r3, #8] + 8000934: 687b ldr r3, [r7, #4] + 8000936: 899b ldrh r3, [r3, #12] + 8000938: 2200 movs r2, #0 + 800093a: 4619 mov r1, r3 + 800093c: f001 fc94 bl 8002268 + + //check if duty_cycle is lower than minimum + if (duty_cycle < -MAX_DUTY_CYCLE) + 8000940: 683b ldr r3, [r7, #0] + 8000942: 4a45 ldr r2, [pc, #276] ; (8000a58 <_ZN15MotorController9set_speedEi+0x248>) + 8000944: 4293 cmp r3, r2 + 8000946: da3d bge.n 80009c4 <_ZN15MotorController9set_speedEi+0x1b4> + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, MAX_DUTY_CYCLE); + 8000948: 687b ldr r3, [r7, #4] + 800094a: 695b ldr r3, [r3, #20] + 800094c: 2b00 cmp r3, #0 + 800094e: d106 bne.n 800095e <_ZN15MotorController9set_speedEi+0x14e> + 8000950: 687b ldr r3, [r7, #4] + 8000952: 691b ldr r3, [r3, #16] + 8000954: 681b ldr r3, [r3, #0] + 8000956: f240 3216 movw r2, #790 ; 0x316 + 800095a: 635a str r2, [r3, #52] ; 0x34 + 800095c: e06f b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 800095e: 687b ldr r3, [r7, #4] + 8000960: 695b ldr r3, [r3, #20] + 8000962: 2b04 cmp r3, #4 + 8000964: d106 bne.n 8000974 <_ZN15MotorController9set_speedEi+0x164> + 8000966: 687b ldr r3, [r7, #4] + 8000968: 691b ldr r3, [r3, #16] + 800096a: 681b ldr r3, [r3, #0] + 800096c: f240 3216 movw r2, #790 ; 0x316 + 8000970: 639a str r2, [r3, #56] ; 0x38 + 8000972: e064 b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 8000974: 687b ldr r3, [r7, #4] + 8000976: 695b ldr r3, [r3, #20] + 8000978: 2b08 cmp r3, #8 + 800097a: d106 bne.n 800098a <_ZN15MotorController9set_speedEi+0x17a> + 800097c: 687b ldr r3, [r7, #4] + 800097e: 691b ldr r3, [r3, #16] + 8000980: 681b ldr r3, [r3, #0] + 8000982: f240 3216 movw r2, #790 ; 0x316 + 8000986: 63da str r2, [r3, #60] ; 0x3c + 8000988: e059 b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 800098a: 687b ldr r3, [r7, #4] + 800098c: 695b ldr r3, [r3, #20] + 800098e: 2b0c cmp r3, #12 + 8000990: d106 bne.n 80009a0 <_ZN15MotorController9set_speedEi+0x190> + 8000992: 687b ldr r3, [r7, #4] + 8000994: 691b ldr r3, [r3, #16] + 8000996: 681b ldr r3, [r3, #0] + 8000998: f240 3216 movw r2, #790 ; 0x316 + 800099c: 641a str r2, [r3, #64] ; 0x40 + 800099e: e04e b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 80009a0: 687b ldr r3, [r7, #4] + 80009a2: 695b ldr r3, [r3, #20] + 80009a4: 2b10 cmp r3, #16 + 80009a6: d106 bne.n 80009b6 <_ZN15MotorController9set_speedEi+0x1a6> + 80009a8: 687b ldr r3, [r7, #4] + 80009aa: 691b ldr r3, [r3, #16] + 80009ac: 681b ldr r3, [r3, #0] + 80009ae: f240 3216 movw r2, #790 ; 0x316 + 80009b2: 659a str r2, [r3, #88] ; 0x58 + 80009b4: e043 b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 80009b6: 687b ldr r3, [r7, #4] + 80009b8: 691b ldr r3, [r3, #16] + 80009ba: 681b ldr r3, [r3, #0] + 80009bc: f240 3216 movw r2, #790 ; 0x316 + 80009c0: 65da str r2, [r3, #92] ; 0x5c + 80009c2: e03c b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + else + //invert sign to make duty_cycle positive + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle); + 80009c4: 687b ldr r3, [r7, #4] + 80009c6: 695b ldr r3, [r3, #20] + 80009c8: 2b00 cmp r3, #0 + 80009ca: d106 bne.n 80009da <_ZN15MotorController9set_speedEi+0x1ca> + 80009cc: 683b ldr r3, [r7, #0] + 80009ce: 425a negs r2, r3 + 80009d0: 687b ldr r3, [r7, #4] + 80009d2: 691b ldr r3, [r3, #16] + 80009d4: 681b ldr r3, [r3, #0] + 80009d6: 635a str r2, [r3, #52] ; 0x34 + 80009d8: e031 b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 80009da: 687b ldr r3, [r7, #4] + 80009dc: 695b ldr r3, [r3, #20] + 80009de: 2b04 cmp r3, #4 + 80009e0: d106 bne.n 80009f0 <_ZN15MotorController9set_speedEi+0x1e0> + 80009e2: 683b ldr r3, [r7, #0] + 80009e4: 425a negs r2, r3 + 80009e6: 687b ldr r3, [r7, #4] + 80009e8: 691b ldr r3, [r3, #16] + 80009ea: 681b ldr r3, [r3, #0] + 80009ec: 639a str r2, [r3, #56] ; 0x38 + 80009ee: e026 b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 80009f0: 687b ldr r3, [r7, #4] + 80009f2: 695b ldr r3, [r3, #20] + 80009f4: 2b08 cmp r3, #8 + 80009f6: d106 bne.n 8000a06 <_ZN15MotorController9set_speedEi+0x1f6> + 80009f8: 683b ldr r3, [r7, #0] + 80009fa: 425a negs r2, r3 + 80009fc: 687b ldr r3, [r7, #4] + 80009fe: 691b ldr r3, [r3, #16] + 8000a00: 681b ldr r3, [r3, #0] + 8000a02: 63da str r2, [r3, #60] ; 0x3c + 8000a04: e01b b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 8000a06: 687b ldr r3, [r7, #4] + 8000a08: 695b ldr r3, [r3, #20] + 8000a0a: 2b0c cmp r3, #12 + 8000a0c: d106 bne.n 8000a1c <_ZN15MotorController9set_speedEi+0x20c> + 8000a0e: 683b ldr r3, [r7, #0] + 8000a10: 425a negs r2, r3 + 8000a12: 687b ldr r3, [r7, #4] + 8000a14: 691b ldr r3, [r3, #16] + 8000a16: 681b ldr r3, [r3, #0] + 8000a18: 641a str r2, [r3, #64] ; 0x40 + 8000a1a: e010 b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 8000a1c: 687b ldr r3, [r7, #4] + 8000a1e: 695b ldr r3, [r3, #20] + 8000a20: 2b10 cmp r3, #16 + 8000a22: d106 bne.n 8000a32 <_ZN15MotorController9set_speedEi+0x222> + 8000a24: 683b ldr r3, [r7, #0] + 8000a26: 425a negs r2, r3 + 8000a28: 687b ldr r3, [r7, #4] + 8000a2a: 691b ldr r3, [r3, #16] + 8000a2c: 681b ldr r3, [r3, #0] + 8000a2e: 659a str r2, [r3, #88] ; 0x58 + 8000a30: e005 b.n 8000a3e <_ZN15MotorController9set_speedEi+0x22e> + 8000a32: 683b ldr r3, [r7, #0] + 8000a34: 425a negs r2, r3 + 8000a36: 687b ldr r3, [r7, #4] + 8000a38: 691b ldr r3, [r3, #16] + 8000a3a: 681b ldr r3, [r3, #0] + 8000a3c: 65da str r2, [r3, #92] ; 0x5c + } + + HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET); + 8000a3e: 687b ldr r3, [r7, #4] + 8000a40: 6818 ldr r0, [r3, #0] + 8000a42: 687b ldr r3, [r7, #4] + 8000a44: 889b ldrh r3, [r3, #4] + 8000a46: 2201 movs r2, #1 + 8000a48: 4619 mov r1, r3 + 8000a4a: f001 fc0d bl 8002268 + + } + 8000a4e: bf00 nop + 8000a50: 3708 adds r7, #8 + 8000a52: 46bd mov sp, r7 + 8000a54: bd80 pop {r7, pc} + 8000a56: bf00 nop + 8000a58: fffffcea .word 0xfffffcea + +08000a5c <_ZN15MotorController5coastEv>: + void brake() { + HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET); + __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 0); + } + + void coast() { + 8000a5c: b580 push {r7, lr} + 8000a5e: b082 sub sp, #8 + 8000a60: af00 add r7, sp, #0 + 8000a62: 6078 str r0, [r7, #4] + HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_RESET); + 8000a64: 687b ldr r3, [r7, #4] + 8000a66: 6818 ldr r0, [r3, #0] + 8000a68: 687b ldr r3, [r7, #4] + 8000a6a: 889b ldrh r3, [r3, #4] + 8000a6c: 2200 movs r2, #0 + 8000a6e: 4619 mov r1, r3 + 8000a70: f001 fbfa bl 8002268 + } + 8000a74: bf00 nop + 8000a76: 3708 adds r7, #8 + 8000a78: 46bd mov sp, r7 + 8000a7a: bd80 pop {r7, pc} + +08000a7c <_ZN3PidC1Efff>: + float previous_error_; + + int min_; + int max_; + + Pid(float kp, float ki, float kd) { + 8000a7c: b480 push {r7} + 8000a7e: b085 sub sp, #20 + 8000a80: af00 add r7, sp, #0 + 8000a82: 60f8 str r0, [r7, #12] + 8000a84: ed87 0a02 vstr s0, [r7, #8] + 8000a88: edc7 0a01 vstr s1, [r7, #4] + 8000a8c: ed87 1a00 vstr s2, [r7] + this->kp_ = kp; + 8000a90: 68fb ldr r3, [r7, #12] + 8000a92: 68ba ldr r2, [r7, #8] + 8000a94: 601a str r2, [r3, #0] + this->ki_ = ki; + 8000a96: 68fb ldr r3, [r7, #12] + 8000a98: 687a ldr r2, [r7, #4] + 8000a9a: 605a str r2, [r3, #4] + this->kd_ = kd; + 8000a9c: 68fb ldr r3, [r7, #12] + 8000a9e: 683a ldr r2, [r7, #0] + 8000aa0: 609a str r2, [r3, #8] + + this->error_ = 0; + 8000aa2: 68fb ldr r3, [r7, #12] + 8000aa4: f04f 0200 mov.w r2, #0 + 8000aa8: 60da str r2, [r3, #12] + this->setpoint_ = 0; + 8000aaa: 68fb ldr r3, [r7, #12] + 8000aac: f04f 0200 mov.w r2, #0 + 8000ab0: 611a str r2, [r3, #16] + + this->previous_error_ = 0; + 8000ab2: 68fb ldr r3, [r7, #12] + 8000ab4: f04f 0200 mov.w r2, #0 + 8000ab8: 619a str r2, [r3, #24] + this->error_sum_ = 0; + 8000aba: 68fb ldr r3, [r7, #12] + 8000abc: f04f 0200 mov.w r2, #0 + 8000ac0: 615a str r2, [r3, #20] + + this->min_ = -MAX_DUTY_CYCLE; + 8000ac2: 68fb ldr r3, [r7, #12] + 8000ac4: 4a06 ldr r2, [pc, #24] ; (8000ae0 <_ZN3PidC1Efff+0x64>) + 8000ac6: 61da str r2, [r3, #28] + this->max_ = MAX_DUTY_CYCLE; + 8000ac8: 68fb ldr r3, [r7, #12] + 8000aca: f240 3216 movw r2, #790 ; 0x316 + 8000ace: 621a str r2, [r3, #32] + + } + 8000ad0: 68fb ldr r3, [r7, #12] + 8000ad2: 4618 mov r0, r3 + 8000ad4: 3714 adds r7, #20 + 8000ad6: 46bd mov sp, r7 + 8000ad8: f85d 7b04 ldr.w r7, [sp], #4 + 8000adc: 4770 bx lr + 8000ade: bf00 nop + 8000ae0: fffffcea .word 0xfffffcea + +08000ae4 <_ZN3Pid6configEfff>: + + void config(float kp, float ki, float kd) { + 8000ae4: b480 push {r7} + 8000ae6: b085 sub sp, #20 + 8000ae8: af00 add r7, sp, #0 + 8000aea: 60f8 str r0, [r7, #12] + 8000aec: ed87 0a02 vstr s0, [r7, #8] + 8000af0: edc7 0a01 vstr s1, [r7, #4] + 8000af4: ed87 1a00 vstr s2, [r7] + this->kp_ = kp; + 8000af8: 68fb ldr r3, [r7, #12] + 8000afa: 68ba ldr r2, [r7, #8] + 8000afc: 601a str r2, [r3, #0] + this->ki_ = ki; + 8000afe: 68fb ldr r3, [r7, #12] + 8000b00: 687a ldr r2, [r7, #4] + 8000b02: 605a str r2, [r3, #4] + this->kd_ = kd; + 8000b04: 68fb ldr r3, [r7, #12] + 8000b06: 683a ldr r2, [r7, #0] + 8000b08: 609a str r2, [r3, #8] + + this->error_ = 0; + 8000b0a: 68fb ldr r3, [r7, #12] + 8000b0c: f04f 0200 mov.w r2, #0 + 8000b10: 60da str r2, [r3, #12] + this->setpoint_ = 0; + 8000b12: 68fb ldr r3, [r7, #12] + 8000b14: f04f 0200 mov.w r2, #0 + 8000b18: 611a str r2, [r3, #16] + + this->previous_error_ = 0; + 8000b1a: 68fb ldr r3, [r7, #12] + 8000b1c: f04f 0200 mov.w r2, #0 + 8000b20: 619a str r2, [r3, #24] + this->error_sum_ = 0; + 8000b22: 68fb ldr r3, [r7, #12] + 8000b24: f04f 0200 mov.w r2, #0 + 8000b28: 615a str r2, [r3, #20] + + } + 8000b2a: bf00 nop + 8000b2c: 3714 adds r7, #20 + 8000b2e: 46bd mov sp, r7 + 8000b30: f85d 7b04 ldr.w r7, [sp], #4 + 8000b34: 4770 bx lr + +08000b36 <_ZN3Pid3setEf>: + + void set(float setpoint) { + 8000b36: b480 push {r7} + 8000b38: b083 sub sp, #12 + 8000b3a: af00 add r7, sp, #0 + 8000b3c: 6078 str r0, [r7, #4] + 8000b3e: ed87 0a00 vstr s0, [r7] + this->setpoint_ = setpoint; + 8000b42: 687b ldr r3, [r7, #4] + 8000b44: 683a ldr r2, [r7, #0] + 8000b46: 611a str r2, [r3, #16] + } + 8000b48: bf00 nop + 8000b4a: 370c adds r7, #12 + 8000b4c: 46bd mov sp, r7 + 8000b4e: f85d 7b04 ldr.w r7, [sp], #4 + 8000b52: 4770 bx lr + +08000b54 <_ZN3Pid6updateEf>: + + int update(float measure) { + 8000b54: b480 push {r7} + 8000b56: b085 sub sp, #20 + 8000b58: af00 add r7, sp, #0 + 8000b5a: 6078 str r0, [r7, #4] + 8000b5c: ed87 0a00 vstr s0, [r7] + + this->error_ = this->setpoint_ - measure; + 8000b60: 687b ldr r3, [r7, #4] + 8000b62: ed93 7a04 vldr s14, [r3, #16] + 8000b66: edd7 7a00 vldr s15, [r7] + 8000b6a: ee77 7a67 vsub.f32 s15, s14, s15 + 8000b6e: 687b ldr r3, [r7, #4] + 8000b70: edc3 7a03 vstr s15, [r3, #12] + + //proportional term + float output = this->error_ * this->kp_; + 8000b74: 687b ldr r3, [r7, #4] + 8000b76: ed93 7a03 vldr s14, [r3, #12] + 8000b7a: 687b ldr r3, [r7, #4] + 8000b7c: edd3 7a00 vldr s15, [r3] + 8000b80: ee67 7a27 vmul.f32 s15, s14, s15 + 8000b84: edc7 7a03 vstr s15, [r7, #12] + + //integral term without windup + error_sum_ += this->error_; + 8000b88: 687b ldr r3, [r7, #4] + 8000b8a: ed93 7a05 vldr s14, [r3, #20] + 8000b8e: 687b ldr r3, [r7, #4] + 8000b90: edd3 7a03 vldr s15, [r3, #12] + 8000b94: ee77 7a27 vadd.f32 s15, s14, s15 + 8000b98: 687b ldr r3, [r7, #4] + 8000b9a: edc3 7a05 vstr s15, [r3, #20] + output += error_sum_ * this->ki_; + 8000b9e: 687b ldr r3, [r7, #4] + 8000ba0: ed93 7a05 vldr s14, [r3, #20] + 8000ba4: 687b ldr r3, [r7, #4] + 8000ba6: edd3 7a01 vldr s15, [r3, #4] + 8000baa: ee67 7a27 vmul.f32 s15, s14, s15 + 8000bae: ed97 7a03 vldr s14, [r7, #12] + 8000bb2: ee77 7a27 vadd.f32 s15, s14, s15 + 8000bb6: edc7 7a03 vstr s15, [r7, #12] + + //derivative term + output += (this->error_ - this->previous_error_) * kd_; + 8000bba: 687b ldr r3, [r7, #4] + 8000bbc: ed93 7a03 vldr s14, [r3, #12] + 8000bc0: 687b ldr r3, [r7, #4] + 8000bc2: edd3 7a06 vldr s15, [r3, #24] + 8000bc6: ee37 7a67 vsub.f32 s14, s14, s15 + 8000bca: 687b ldr r3, [r7, #4] + 8000bcc: edd3 7a02 vldr s15, [r3, #8] + 8000bd0: ee67 7a27 vmul.f32 s15, s14, s15 + 8000bd4: ed97 7a03 vldr s14, [r7, #12] + 8000bd8: ee77 7a27 vadd.f32 s15, s14, s15 + 8000bdc: edc7 7a03 vstr s15, [r7, #12] + this->previous_error_ = this->error_; + 8000be0: 687b ldr r3, [r7, #4] + 8000be2: 68da ldr r2, [r3, #12] + 8000be4: 687b ldr r3, [r7, #4] + 8000be6: 619a str r2, [r3, #24] + + int integer_output = static_cast (output); + 8000be8: edd7 7a03 vldr s15, [r7, #12] + 8000bec: eefd 7ae7 vcvt.s32.f32 s15, s15 + 8000bf0: ee17 3a90 vmov r3, s15 + 8000bf4: 60bb str r3, [r7, #8] +// if(integer_output > this->max_) +// integer_output = this->max_; +// else if (integer_output < this->min_) +// integer_output = this->min_; + + return integer_output; + 8000bf6: 68bb ldr r3, [r7, #8] + + } + 8000bf8: 4618 mov r0, r3 + 8000bfa: 3714 adds r7, #20 + 8000bfc: 46bd mov sp, r7 + 8000bfe: f85d 7b04 ldr.w r7, [sp], #4 + 8000c02: 4770 bx lr + +08000c04
: + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) { + 8000c04: b580 push {r7, lr} + 8000c06: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 8000c08: f000 fff3 bl 8001bf2 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 8000c0c: f000 f874 bl 8000cf8 <_Z18SystemClock_Configv> + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8000c10: f000 fb4a bl 80012a8 <_ZL12MX_GPIO_Initv> + MX_TIM2_Init(); + 8000c14: f000 f916 bl 8000e44 <_ZL12MX_TIM2_Initv> + MX_TIM3_Init(); + 8000c18: f000 f972 bl 8000f00 <_ZL12MX_TIM3_Initv> + MX_TIM4_Init(); + 8000c1c: f000 f9ce bl 8000fbc <_ZL12MX_TIM4_Initv> + MX_TIM5_Init(); + 8000c20: f000 fa6c bl 80010fc <_ZL12MX_TIM5_Initv> + MX_USART6_UART_Init(); + 8000c24: f000 fb0c bl 8001240 <_ZL19MX_USART6_UART_Initv> + MX_TIM6_Init(); + 8000c28: f000 fac8 bl 80011bc <_ZL12MX_TIM6_Initv> + + /* Initialize interrupts */ + MX_NVIC_Init(); + 8000c2c: f000 f8ee bl 8000e0c <_ZL12MX_NVIC_Initv> + /* USER CODE BEGIN 2 */ + + left_encoder.Setup(); + 8000c30: 481e ldr r0, [pc, #120] ; (8000cac ) + 8000c32: f7ff fcbc bl 80005ae <_ZN7Encoder5SetupEv> + right_encoder.Setup(); + 8000c36: 481e ldr r0, [pc, #120] ; (8000cb0 ) + 8000c38: f7ff fcb9 bl 80005ae <_ZN7Encoder5SetupEv> + + left_motor.setup(); + 8000c3c: 481d ldr r0, [pc, #116] ; (8000cb4 ) + 8000c3e: f7ff fdd6 bl 80007ee <_ZN15MotorController5setupEv> + right_motor.setup(); + 8000c42: 481d ldr r0, [pc, #116] ; (8000cb8 ) + 8000c44: f7ff fdd3 bl 80007ee <_ZN15MotorController5setupEv> + left_motor.coast(); + 8000c48: 481a ldr r0, [pc, #104] ; (8000cb4 ) + 8000c4a: f7ff ff07 bl 8000a5c <_ZN15MotorController5coastEv> + right_motor.coast(); + 8000c4e: 481a ldr r0, [pc, #104] ; (8000cb8 ) + 8000c50: f7ff ff04 bl 8000a5c <_ZN15MotorController5coastEv> + + left_pid.config(180, 200, 0); + 8000c54: ed9f 1a19 vldr s2, [pc, #100] ; 8000cbc + 8000c58: eddf 0a19 vldr s1, [pc, #100] ; 8000cc0 + 8000c5c: ed9f 0a19 vldr s0, [pc, #100] ; 8000cc4 + 8000c60: 4819 ldr r0, [pc, #100] ; (8000cc8 ) + 8000c62: f7ff ff3f bl 8000ae4 <_ZN3Pid6configEfff> + right_pid.config(185, 195, 0); + 8000c66: ed9f 1a15 vldr s2, [pc, #84] ; 8000cbc + 8000c6a: eddf 0a18 vldr s1, [pc, #96] ; 8000ccc + 8000c6e: ed9f 0a18 vldr s0, [pc, #96] ; 8000cd0 + 8000c72: 4818 ldr r0, [pc, #96] ; (8000cd4 ) + 8000c74: f7ff ff36 bl 8000ae4 <_ZN3Pid6configEfff> + cross_pid.config(50, 20, 0); + 8000c78: ed9f 1a10 vldr s2, [pc, #64] ; 8000cbc + 8000c7c: eef3 0a04 vmov.f32 s1, #52 ; 0x41a00000 20.0 + 8000c80: ed9f 0a15 vldr s0, [pc, #84] ; 8000cd8 + 8000c84: 4815 ldr r0, [pc, #84] ; (8000cdc ) + 8000c86: f7ff ff2d bl 8000ae4 <_ZN3Pid6configEfff> + + tx_buffer = (uint8_t*) &output_msg; + 8000c8a: 4b15 ldr r3, [pc, #84] ; (8000ce0 ) + 8000c8c: 4a15 ldr r2, [pc, #84] ; (8000ce4 ) + 8000c8e: 601a str r2, [r3, #0] + rx_buffer = (uint8_t*) &input_msg; + 8000c90: 4b15 ldr r3, [pc, #84] ; (8000ce8 ) + 8000c92: 4a16 ldr r2, [pc, #88] ; (8000cec ) + 8000c94: 601a str r2, [r3, #0] + + //Enables UART RX interrupt + HAL_UART_Receive_IT(&huart6, rx_buffer, 8); + 8000c96: 4b14 ldr r3, [pc, #80] ; (8000ce8 ) + 8000c98: 681b ldr r3, [r3, #0] + 8000c9a: 2208 movs r2, #8 + 8000c9c: 4619 mov r1, r3 + 8000c9e: 4814 ldr r0, [pc, #80] ; (8000cf0 ) + 8000ca0: f003 fd44 bl 800472c + HAL_TIM_Base_Start_IT(&htim6); + 8000ca4: 4813 ldr r0, [pc, #76] ; (8000cf4 ) + 8000ca6: f002 fba3 bl 80033f0 + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) { + 8000caa: e7fe b.n 8000caa + 8000cac: 20000204 .word 0x20000204 + 8000cb0: 200001ec .word 0x200001ec + 8000cb4: 200002bc .word 0x200002bc + 8000cb8: 200002a4 .word 0x200002a4 + 8000cbc: 00000000 .word 0x00000000 + 8000cc0: 43480000 .word 0x43480000 + 8000cc4: 43340000 .word 0x43340000 + 8000cc8: 20000228 .word 0x20000228 + 8000ccc: 43430000 .word 0x43430000 + 8000cd0: 43390000 .word 0x43390000 + 8000cd4: 2000024c .word 0x2000024c + 8000cd8: 42480000 .word 0x42480000 + 8000cdc: 20000270 .word 0x20000270 + 8000ce0: 200002d4 .word 0x200002d4 + 8000ce4: 200002e4 .word 0x200002e4 + 8000ce8: 200002d8 .word 0x200002d8 + 8000cec: 200002dc .word 0x200002dc + 8000cf0: 2000016c .word 0x2000016c + 8000cf4: 2000012c .word 0x2000012c + +08000cf8 <_Z18SystemClock_Configv>: + +/** + * @brief System Clock Configuration + * @retval Nonewheel_circumference_ + */ +void SystemClock_Config(void) { + 8000cf8: b580 push {r7, lr} + 8000cfa: b0b8 sub sp, #224 ; 0xe0 + 8000cfc: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; + 8000cfe: f107 03ac add.w r3, r7, #172 ; 0xac + 8000d02: 2234 movs r2, #52 ; 0x34 + 8000d04: 2100 movs r1, #0 + 8000d06: 4618 mov r0, r3 + 8000d08: f004 fbb8 bl 800547c + RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; + 8000d0c: f107 0398 add.w r3, r7, #152 ; 0x98 + 8000d10: 2200 movs r2, #0 + 8000d12: 601a str r2, [r3, #0] + 8000d14: 605a str r2, [r3, #4] + 8000d16: 609a str r2, [r3, #8] + 8000d18: 60da str r2, [r3, #12] + 8000d1a: 611a str r2, [r3, #16] + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 }; + 8000d1c: f107 0308 add.w r3, r7, #8 + 8000d20: 2290 movs r2, #144 ; 0x90 + 8000d22: 2100 movs r1, #0 + 8000d24: 4618 mov r0, r3 + 8000d26: f004 fba9 bl 800547c + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + 8000d2a: 4b36 ldr r3, [pc, #216] ; (8000e04 <_Z18SystemClock_Configv+0x10c>) + 8000d2c: 6c1b ldr r3, [r3, #64] ; 0x40 + 8000d2e: 4a35 ldr r2, [pc, #212] ; (8000e04 <_Z18SystemClock_Configv+0x10c>) + 8000d30: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8000d34: 6413 str r3, [r2, #64] ; 0x40 + 8000d36: 4b33 ldr r3, [pc, #204] ; (8000e04 <_Z18SystemClock_Configv+0x10c>) + 8000d38: 6c1b ldr r3, [r3, #64] ; 0x40 + 8000d3a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8000d3e: 607b str r3, [r7, #4] + 8000d40: 687b ldr r3, [r7, #4] + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); + 8000d42: 4b31 ldr r3, [pc, #196] ; (8000e08 <_Z18SystemClock_Configv+0x110>) + 8000d44: 681b ldr r3, [r3, #0] + 8000d46: f423 4340 bic.w r3, r3, #49152 ; 0xc000 + 8000d4a: 4a2f ldr r2, [pc, #188] ; (8000e08 <_Z18SystemClock_Configv+0x110>) + 8000d4c: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8000d50: 6013 str r3, [r2, #0] + 8000d52: 4b2d ldr r3, [pc, #180] ; (8000e08 <_Z18SystemClock_Configv+0x110>) + 8000d54: 681b ldr r3, [r3, #0] + 8000d56: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 8000d5a: 603b str r3, [r7, #0] + 8000d5c: 683b ldr r3, [r7, #0] + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 8000d5e: 2302 movs r3, #2 + 8000d60: f8c7 30ac str.w r3, [r7, #172] ; 0xac + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 8000d64: 2301 movs r3, #1 + 8000d66: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 8000d6a: 2310 movs r3, #16 + 8000d6c: f8c7 30bc str.w r3, [r7, #188] ; 0xbc + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 8000d70: 2300 movs r3, #0 + 8000d72: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + 8000d76: f107 03ac add.w r3, r7, #172 ; 0xac + 8000d7a: 4618 mov r0, r3 + 8000d7c: f001 faa6 bl 80022cc + 8000d80: 4603 mov r3, r0 + 8000d82: 2b00 cmp r3, #0 + 8000d84: bf14 ite ne + 8000d86: 2301 movne r3, #1 + 8000d88: 2300 moveq r3, #0 + 8000d8a: b2db uxtb r3, r3 + 8000d8c: 2b00 cmp r3, #0 + 8000d8e: d001 beq.n 8000d94 <_Z18SystemClock_Configv+0x9c> + Error_Handler(); + 8000d90: f000 fc7e bl 8001690 + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + 8000d94: 230f movs r3, #15 + 8000d96: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + 8000d9a: 2300 movs r3, #0 + 8000d9c: f8c7 309c str.w r3, [r7, #156] ; 0x9c + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 8000da0: 2300 movs r3, #0 + 8000da2: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 8000da6: 2300 movs r3, #0 + 8000da8: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 8000dac: 2300 movs r3, #0 + 8000dae: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) { + 8000db2: f107 0398 add.w r3, r7, #152 ; 0x98 + 8000db6: 2100 movs r1, #0 + 8000db8: 4618 mov r0, r3 + 8000dba: f001 fcf9 bl 80027b0 + 8000dbe: 4603 mov r3, r0 + 8000dc0: 2b00 cmp r3, #0 + 8000dc2: bf14 ite ne + 8000dc4: 2301 movne r3, #1 + 8000dc6: 2300 moveq r3, #0 + 8000dc8: b2db uxtb r3, r3 + 8000dca: 2b00 cmp r3, #0 + 8000dcc: d001 beq.n 8000dd2 <_Z18SystemClock_Configv+0xda> + Error_Handler(); + 8000dce: f000 fc5f bl 8001690 + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6; + 8000dd2: f44f 6300 mov.w r3, #2048 ; 0x800 + 8000dd6: 60bb str r3, [r7, #8] + PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2; + 8000dd8: 2300 movs r3, #0 + 8000dda: 663b str r3, [r7, #96] ; 0x60 + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + 8000ddc: f107 0308 add.w r3, r7, #8 + 8000de0: 4618 mov r0, r3 + 8000de2: f001 feb3 bl 8002b4c + 8000de6: 4603 mov r3, r0 + 8000de8: 2b00 cmp r3, #0 + 8000dea: bf14 ite ne + 8000dec: 2301 movne r3, #1 + 8000dee: 2300 moveq r3, #0 + 8000df0: b2db uxtb r3, r3 + 8000df2: 2b00 cmp r3, #0 + 8000df4: d001 beq.n 8000dfa <_Z18SystemClock_Configv+0x102> + Error_Handler(); + 8000df6: f000 fc4b bl 8001690 + } +} + 8000dfa: bf00 nop + 8000dfc: 37e0 adds r7, #224 ; 0xe0 + 8000dfe: 46bd mov sp, r7 + 8000e00: bd80 pop {r7, pc} + 8000e02: bf00 nop + 8000e04: 40023800 .word 0x40023800 + 8000e08: 40007000 .word 0x40007000 + +08000e0c <_ZL12MX_NVIC_Initv>: + +/** + * @brief NVIC Configuration. + * @retval None + */ +static void MX_NVIC_Init(void) { + 8000e0c: b580 push {r7, lr} + 8000e0e: af00 add r7, sp, #0 + /* TIM3_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(TIM3_IRQn, 2, 1); + 8000e10: 2201 movs r2, #1 + 8000e12: 2102 movs r1, #2 + 8000e14: 201d movs r0, #29 + 8000e16: f001 f824 bl 8001e62 + HAL_NVIC_EnableIRQ(TIM3_IRQn); + 8000e1a: 201d movs r0, #29 + 8000e1c: f001 f83d bl 8001e9a + /* TIM6_DAC_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 2, 2); + 8000e20: 2202 movs r2, #2 + 8000e22: 2102 movs r1, #2 + 8000e24: 2036 movs r0, #54 ; 0x36 + 8000e26: f001 f81c bl 8001e62 + HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); + 8000e2a: 2036 movs r0, #54 ; 0x36 + 8000e2c: f001 f835 bl 8001e9a + /* USART6_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(USART6_IRQn, 1, 0); + 8000e30: 2200 movs r2, #0 + 8000e32: 2101 movs r1, #1 + 8000e34: 2047 movs r0, #71 ; 0x47 + 8000e36: f001 f814 bl 8001e62 + HAL_NVIC_EnableIRQ(USART6_IRQn); + 8000e3a: 2047 movs r0, #71 ; 0x47 + 8000e3c: f001 f82d bl 8001e9a +} + 8000e40: bf00 nop + 8000e42: bd80 pop {r7, pc} + +08000e44 <_ZL12MX_TIM2_Initv>: +/** + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) { + 8000e44: b580 push {r7, lr} + 8000e46: b08c sub sp, #48 ; 0x30 + 8000e48: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_Encoder_InitTypeDef sConfig = { 0 }; + 8000e4a: f107 030c add.w r3, r7, #12 + 8000e4e: 2224 movs r2, #36 ; 0x24 + 8000e50: 2100 movs r1, #0 + 8000e52: 4618 mov r0, r3 + 8000e54: f004 fb12 bl 800547c + TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + 8000e58: 463b mov r3, r7 + 8000e5a: 2200 movs r2, #0 + 8000e5c: 601a str r2, [r3, #0] + 8000e5e: 605a str r2, [r3, #4] + 8000e60: 609a str r2, [r3, #8] + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + 8000e62: 4b26 ldr r3, [pc, #152] ; (8000efc <_ZL12MX_TIM2_Initv+0xb8>) + 8000e64: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 + 8000e68: 601a str r2, [r3, #0] + htim2.Init.Prescaler = 0; + 8000e6a: 4b24 ldr r3, [pc, #144] ; (8000efc <_ZL12MX_TIM2_Initv+0xb8>) + 8000e6c: 2200 movs r2, #0 + 8000e6e: 605a str r2, [r3, #4] + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + 8000e70: 4b22 ldr r3, [pc, #136] ; (8000efc <_ZL12MX_TIM2_Initv+0xb8>) + 8000e72: 2200 movs r2, #0 + 8000e74: 609a str r2, [r3, #8] + htim2.Init.Period = 4294967295; + 8000e76: 4b21 ldr r3, [pc, #132] ; (8000efc <_ZL12MX_TIM2_Initv+0xb8>) + 8000e78: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 8000e7c: 60da str r2, [r3, #12] + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8000e7e: 4b1f ldr r3, [pc, #124] ; (8000efc <_ZL12MX_TIM2_Initv+0xb8>) + 8000e80: 2200 movs r2, #0 + 8000e82: 611a str r2, [r3, #16] + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 8000e84: 4b1d ldr r3, [pc, #116] ; (8000efc <_ZL12MX_TIM2_Initv+0xb8>) + 8000e86: 2200 movs r2, #0 + 8000e88: 619a str r2, [r3, #24] + sConfig.EncoderMode = TIM_ENCODERMODE_TI12; + 8000e8a: 2303 movs r3, #3 + 8000e8c: 60fb str r3, [r7, #12] + sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; + 8000e8e: 2300 movs r3, #0 + 8000e90: 613b str r3, [r7, #16] + sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; + 8000e92: 2301 movs r3, #1 + 8000e94: 617b str r3, [r7, #20] + sConfig.IC1Prescaler = TIM_ICPSC_DIV1; + 8000e96: 2300 movs r3, #0 + 8000e98: 61bb str r3, [r7, #24] + sConfig.IC1Filter = 0; + 8000e9a: 2300 movs r3, #0 + 8000e9c: 61fb str r3, [r7, #28] + sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; + 8000e9e: 2300 movs r3, #0 + 8000ea0: 623b str r3, [r7, #32] + sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; + 8000ea2: 2301 movs r3, #1 + 8000ea4: 627b str r3, [r7, #36] ; 0x24 + sConfig.IC2Prescaler = TIM_ICPSC_DIV1; + 8000ea6: 2300 movs r3, #0 + 8000ea8: 62bb str r3, [r7, #40] ; 0x28 + sConfig.IC2Filter = 0; + 8000eaa: 2300 movs r3, #0 + 8000eac: 62fb str r3, [r7, #44] ; 0x2c + if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK) { + 8000eae: f107 030c add.w r3, r7, #12 + 8000eb2: 4619 mov r1, r3 + 8000eb4: 4811 ldr r0, [pc, #68] ; (8000efc <_ZL12MX_TIM2_Initv+0xb8>) + 8000eb6: f002 fb3f bl 8003538 + 8000eba: 4603 mov r3, r0 + 8000ebc: 2b00 cmp r3, #0 + 8000ebe: bf14 ite ne + 8000ec0: 2301 movne r3, #1 + 8000ec2: 2300 moveq r3, #0 + 8000ec4: b2db uxtb r3, r3 + 8000ec6: 2b00 cmp r3, #0 + 8000ec8: d001 beq.n 8000ece <_ZL12MX_TIM2_Initv+0x8a> + Error_Handler(); + 8000eca: f000 fbe1 bl 8001690 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8000ece: 2300 movs r3, #0 + 8000ed0: 603b str r3, [r7, #0] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8000ed2: 2300 movs r3, #0 + 8000ed4: 60bb str r3, [r7, #8] + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) { + 8000ed6: 463b mov r3, r7 + 8000ed8: 4619 mov r1, r3 + 8000eda: 4808 ldr r0, [pc, #32] ; (8000efc <_ZL12MX_TIM2_Initv+0xb8>) + 8000edc: f003 facc bl 8004478 + 8000ee0: 4603 mov r3, r0 + 8000ee2: 2b00 cmp r3, #0 + 8000ee4: bf14 ite ne + 8000ee6: 2301 movne r3, #1 + 8000ee8: 2300 moveq r3, #0 + 8000eea: b2db uxtb r3, r3 + 8000eec: 2b00 cmp r3, #0 + 8000eee: d001 beq.n 8000ef4 <_ZL12MX_TIM2_Initv+0xb0> + Error_Handler(); + 8000ef0: f000 fbce bl 8001690 + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + +} + 8000ef4: bf00 nop + 8000ef6: 3730 adds r7, #48 ; 0x30 + 8000ef8: 46bd mov sp, r7 + 8000efa: bd80 pop {r7, pc} + 8000efc: 2000002c .word 0x2000002c + +08000f00 <_ZL12MX_TIM3_Initv>: +/** + * @brief TIM3 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM3_Init(void) { + 8000f00: b580 push {r7, lr} + 8000f02: b088 sub sp, #32 + 8000f04: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = { 0 }; + 8000f06: f107 0310 add.w r3, r7, #16 + 8000f0a: 2200 movs r2, #0 + 8000f0c: 601a str r2, [r3, #0] + 8000f0e: 605a str r2, [r3, #4] + 8000f10: 609a str r2, [r3, #8] + 8000f12: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + 8000f14: 1d3b adds r3, r7, #4 + 8000f16: 2200 movs r2, #0 + 8000f18: 601a str r2, [r3, #0] + 8000f1a: 605a str r2, [r3, #4] + 8000f1c: 609a str r2, [r3, #8] + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + htim3.Instance = TIM3; + 8000f1e: 4b25 ldr r3, [pc, #148] ; (8000fb4 <_ZL12MX_TIM3_Initv+0xb4>) + 8000f20: 4a25 ldr r2, [pc, #148] ; (8000fb8 <_ZL12MX_TIM3_Initv+0xb8>) + 8000f22: 601a str r2, [r3, #0] + htim3.Init.Prescaler = 999; + 8000f24: 4b23 ldr r3, [pc, #140] ; (8000fb4 <_ZL12MX_TIM3_Initv+0xb4>) + 8000f26: f240 32e7 movw r2, #999 ; 0x3e7 + 8000f2a: 605a str r2, [r3, #4] + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + 8000f2c: 4b21 ldr r3, [pc, #132] ; (8000fb4 <_ZL12MX_TIM3_Initv+0xb4>) + 8000f2e: 2200 movs r2, #0 + 8000f30: 609a str r2, [r3, #8] + htim3.Init.Period = 159; + 8000f32: 4b20 ldr r3, [pc, #128] ; (8000fb4 <_ZL12MX_TIM3_Initv+0xb4>) + 8000f34: 229f movs r2, #159 ; 0x9f + 8000f36: 60da str r2, [r3, #12] + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8000f38: 4b1e ldr r3, [pc, #120] ; (8000fb4 <_ZL12MX_TIM3_Initv+0xb4>) + 8000f3a: 2200 movs r2, #0 + 8000f3c: 611a str r2, [r3, #16] + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 8000f3e: 4b1d ldr r3, [pc, #116] ; (8000fb4 <_ZL12MX_TIM3_Initv+0xb4>) + 8000f40: 2200 movs r2, #0 + 8000f42: 619a str r2, [r3, #24] + if (HAL_TIM_Base_Init(&htim3) != HAL_OK) { + 8000f44: 481b ldr r0, [pc, #108] ; (8000fb4 <_ZL12MX_TIM3_Initv+0xb4>) + 8000f46: f002 fa27 bl 8003398 + 8000f4a: 4603 mov r3, r0 + 8000f4c: 2b00 cmp r3, #0 + 8000f4e: bf14 ite ne + 8000f50: 2301 movne r3, #1 + 8000f52: 2300 moveq r3, #0 + 8000f54: b2db uxtb r3, r3 + 8000f56: 2b00 cmp r3, #0 + 8000f58: d001 beq.n 8000f5e <_ZL12MX_TIM3_Initv+0x5e> + Error_Handler(); + 8000f5a: f000 fb99 bl 8001690 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 8000f5e: f44f 5380 mov.w r3, #4096 ; 0x1000 + 8000f62: 613b str r3, [r7, #16] + if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) { + 8000f64: f107 0310 add.w r3, r7, #16 + 8000f68: 4619 mov r1, r3 + 8000f6a: 4812 ldr r0, [pc, #72] ; (8000fb4 <_ZL12MX_TIM3_Initv+0xb4>) + 8000f6c: f002 fde4 bl 8003b38 + 8000f70: 4603 mov r3, r0 + 8000f72: 2b00 cmp r3, #0 + 8000f74: bf14 ite ne + 8000f76: 2301 movne r3, #1 + 8000f78: 2300 moveq r3, #0 + 8000f7a: b2db uxtb r3, r3 + 8000f7c: 2b00 cmp r3, #0 + 8000f7e: d001 beq.n 8000f84 <_ZL12MX_TIM3_Initv+0x84> + Error_Handler(); + 8000f80: f000 fb86 bl 8001690 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8000f84: 2300 movs r3, #0 + 8000f86: 607b str r3, [r7, #4] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8000f88: 2300 movs r3, #0 + 8000f8a: 60fb str r3, [r7, #12] + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) { + 8000f8c: 1d3b adds r3, r7, #4 + 8000f8e: 4619 mov r1, r3 + 8000f90: 4808 ldr r0, [pc, #32] ; (8000fb4 <_ZL12MX_TIM3_Initv+0xb4>) + 8000f92: f003 fa71 bl 8004478 + 8000f96: 4603 mov r3, r0 + 8000f98: 2b00 cmp r3, #0 + 8000f9a: bf14 ite ne + 8000f9c: 2301 movne r3, #1 + 8000f9e: 2300 moveq r3, #0 + 8000fa0: b2db uxtb r3, r3 + 8000fa2: 2b00 cmp r3, #0 + 8000fa4: d001 beq.n 8000faa <_ZL12MX_TIM3_Initv+0xaa> + Error_Handler(); + 8000fa6: f000 fb73 bl 8001690 + } + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + +} + 8000faa: bf00 nop + 8000fac: 3720 adds r7, #32 + 8000fae: 46bd mov sp, r7 + 8000fb0: bd80 pop {r7, pc} + 8000fb2: bf00 nop + 8000fb4: 2000006c .word 0x2000006c + 8000fb8: 40000400 .word 0x40000400 + +08000fbc <_ZL12MX_TIM4_Initv>: +/** + * @brief TIM4 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM4_Init(void) { + 8000fbc: b580 push {r7, lr} + 8000fbe: b08e sub sp, #56 ; 0x38 + 8000fc0: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM4_Init 0 */ + + /* USER CODE END TIM4_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = { 0 }; + 8000fc2: f107 0328 add.w r3, r7, #40 ; 0x28 + 8000fc6: 2200 movs r2, #0 + 8000fc8: 601a str r2, [r3, #0] + 8000fca: 605a str r2, [r3, #4] + 8000fcc: 609a str r2, [r3, #8] + 8000fce: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + 8000fd0: f107 031c add.w r3, r7, #28 + 8000fd4: 2200 movs r2, #0 + 8000fd6: 601a str r2, [r3, #0] + 8000fd8: 605a str r2, [r3, #4] + 8000fda: 609a str r2, [r3, #8] + TIM_OC_InitTypeDef sConfigOC = { 0 }; + 8000fdc: 463b mov r3, r7 + 8000fde: 2200 movs r2, #0 + 8000fe0: 601a str r2, [r3, #0] + 8000fe2: 605a str r2, [r3, #4] + 8000fe4: 609a str r2, [r3, #8] + 8000fe6: 60da str r2, [r3, #12] + 8000fe8: 611a str r2, [r3, #16] + 8000fea: 615a str r2, [r3, #20] + 8000fec: 619a str r2, [r3, #24] + + /* USER CODE BEGIN TIM4_Init 1 */ + + /* USER CODE END TIM4_Init 1 */ + htim4.Instance = TIM4; + 8000fee: 4b41 ldr r3, [pc, #260] ; (80010f4 <_ZL12MX_TIM4_Initv+0x138>) + 8000ff0: 4a41 ldr r2, [pc, #260] ; (80010f8 <_ZL12MX_TIM4_Initv+0x13c>) + 8000ff2: 601a str r2, [r3, #0] + htim4.Init.Prescaler = 0; + 8000ff4: 4b3f ldr r3, [pc, #252] ; (80010f4 <_ZL12MX_TIM4_Initv+0x138>) + 8000ff6: 2200 movs r2, #0 + 8000ff8: 605a str r2, [r3, #4] + htim4.Init.CounterMode = TIM_COUNTERMODE_UP; + 8000ffa: 4b3e ldr r3, [pc, #248] ; (80010f4 <_ZL12MX_TIM4_Initv+0x138>) + 8000ffc: 2200 movs r2, #0 + 8000ffe: 609a str r2, [r3, #8] + htim4.Init.Period = 799; + 8001000: 4b3c ldr r3, [pc, #240] ; (80010f4 <_ZL12MX_TIM4_Initv+0x138>) + 8001002: f240 321f movw r2, #799 ; 0x31f + 8001006: 60da str r2, [r3, #12] + htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8001008: 4b3a ldr r3, [pc, #232] ; (80010f4 <_ZL12MX_TIM4_Initv+0x138>) + 800100a: 2200 movs r2, #0 + 800100c: 611a str r2, [r3, #16] + htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 800100e: 4b39 ldr r3, [pc, #228] ; (80010f4 <_ZL12MX_TIM4_Initv+0x138>) + 8001010: 2200 movs r2, #0 + 8001012: 619a str r2, [r3, #24] + if (HAL_TIM_Base_Init(&htim4) != HAL_OK) { + 8001014: 4837 ldr r0, [pc, #220] ; (80010f4 <_ZL12MX_TIM4_Initv+0x138>) + 8001016: f002 f9bf bl 8003398 + 800101a: 4603 mov r3, r0 + 800101c: 2b00 cmp r3, #0 + 800101e: bf14 ite ne + 8001020: 2301 movne r3, #1 + 8001022: 2300 moveq r3, #0 + 8001024: b2db uxtb r3, r3 + 8001026: 2b00 cmp r3, #0 + 8001028: d001 beq.n 800102e <_ZL12MX_TIM4_Initv+0x72> + Error_Handler(); + 800102a: f000 fb31 bl 8001690 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 800102e: f44f 5380 mov.w r3, #4096 ; 0x1000 + 8001032: 62bb str r3, [r7, #40] ; 0x28 + if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) { + 8001034: f107 0328 add.w r3, r7, #40 ; 0x28 + 8001038: 4619 mov r1, r3 + 800103a: 482e ldr r0, [pc, #184] ; (80010f4 <_ZL12MX_TIM4_Initv+0x138>) + 800103c: f002 fd7c bl 8003b38 + 8001040: 4603 mov r3, r0 + 8001042: 2b00 cmp r3, #0 + 8001044: bf14 ite ne + 8001046: 2301 movne r3, #1 + 8001048: 2300 moveq r3, #0 + 800104a: b2db uxtb r3, r3 + 800104c: 2b00 cmp r3, #0 + 800104e: d001 beq.n 8001054 <_ZL12MX_TIM4_Initv+0x98> + Error_Handler(); + 8001050: f000 fb1e bl 8001690 + } + if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) { + 8001054: 4827 ldr r0, [pc, #156] ; (80010f4 <_ZL12MX_TIM4_Initv+0x138>) + 8001056: f002 f9f5 bl 8003444 + 800105a: 4603 mov r3, r0 + 800105c: 2b00 cmp r3, #0 + 800105e: bf14 ite ne + 8001060: 2301 movne r3, #1 + 8001062: 2300 moveq r3, #0 + 8001064: b2db uxtb r3, r3 + 8001066: 2b00 cmp r3, #0 + 8001068: d001 beq.n 800106e <_ZL12MX_TIM4_Initv+0xb2> + Error_Handler(); + 800106a: f000 fb11 bl 8001690 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 800106e: 2300 movs r3, #0 + 8001070: 61fb str r3, [r7, #28] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8001072: 2300 movs r3, #0 + 8001074: 627b str r3, [r7, #36] ; 0x24 + if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) { + 8001076: f107 031c add.w r3, r7, #28 + 800107a: 4619 mov r1, r3 + 800107c: 481d ldr r0, [pc, #116] ; (80010f4 <_ZL12MX_TIM4_Initv+0x138>) + 800107e: f003 f9fb bl 8004478 + 8001082: 4603 mov r3, r0 + 8001084: 2b00 cmp r3, #0 + 8001086: bf14 ite ne + 8001088: 2301 movne r3, #1 + 800108a: 2300 moveq r3, #0 + 800108c: b2db uxtb r3, r3 + 800108e: 2b00 cmp r3, #0 + 8001090: d001 beq.n 8001096 <_ZL12MX_TIM4_Initv+0xda> + Error_Handler(); + 8001092: f000 fafd bl 8001690 + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + 8001096: 2360 movs r3, #96 ; 0x60 + 8001098: 603b str r3, [r7, #0] + sConfigOC.Pulse = 0; + 800109a: 2300 movs r3, #0 + 800109c: 607b str r3, [r7, #4] + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 800109e: 2300 movs r3, #0 + 80010a0: 60bb str r3, [r7, #8] + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 80010a2: 2300 movs r3, #0 + 80010a4: 613b str r3, [r7, #16] + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) { + 80010a6: 463b mov r3, r7 + 80010a8: 2208 movs r2, #8 + 80010aa: 4619 mov r1, r3 + 80010ac: 4811 ldr r0, [pc, #68] ; (80010f4 <_ZL12MX_TIM4_Initv+0x138>) + 80010ae: f002 fc2b bl 8003908 + 80010b2: 4603 mov r3, r0 + 80010b4: 2b00 cmp r3, #0 + 80010b6: bf14 ite ne + 80010b8: 2301 movne r3, #1 + 80010ba: 2300 moveq r3, #0 + 80010bc: b2db uxtb r3, r3 + 80010be: 2b00 cmp r3, #0 + 80010c0: d001 beq.n 80010c6 <_ZL12MX_TIM4_Initv+0x10a> + Error_Handler(); + 80010c2: f000 fae5 bl 8001690 + } + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) { + 80010c6: 463b mov r3, r7 + 80010c8: 220c movs r2, #12 + 80010ca: 4619 mov r1, r3 + 80010cc: 4809 ldr r0, [pc, #36] ; (80010f4 <_ZL12MX_TIM4_Initv+0x138>) + 80010ce: f002 fc1b bl 8003908 + 80010d2: 4603 mov r3, r0 + 80010d4: 2b00 cmp r3, #0 + 80010d6: bf14 ite ne + 80010d8: 2301 movne r3, #1 + 80010da: 2300 moveq r3, #0 + 80010dc: b2db uxtb r3, r3 + 80010de: 2b00 cmp r3, #0 + 80010e0: d001 beq.n 80010e6 <_ZL12MX_TIM4_Initv+0x12a> + Error_Handler(); + 80010e2: f000 fad5 bl 8001690 + } + /* USER CODE BEGIN TIM4_Init 2 */ + + /* USER CODE END TIM4_Init 2 */ + HAL_TIM_MspPostInit(&htim4); + 80010e6: 4803 ldr r0, [pc, #12] ; (80010f4 <_ZL12MX_TIM4_Initv+0x138>) + 80010e8: f000 fc54 bl 8001994 + +} + 80010ec: bf00 nop + 80010ee: 3738 adds r7, #56 ; 0x38 + 80010f0: 46bd mov sp, r7 + 80010f2: bd80 pop {r7, pc} + 80010f4: 200000ac .word 0x200000ac + 80010f8: 40000800 .word 0x40000800 + +080010fc <_ZL12MX_TIM5_Initv>: +/** + * @brief TIM5 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM5_Init(void) { + 80010fc: b580 push {r7, lr} + 80010fe: b08c sub sp, #48 ; 0x30 + 8001100: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM5_Init 0 */ + + /* USER CODE END TIM5_Init 0 */ + + TIM_Encoder_InitTypeDef sConfig = { 0 }; + 8001102: f107 030c add.w r3, r7, #12 + 8001106: 2224 movs r2, #36 ; 0x24 + 8001108: 2100 movs r1, #0 + 800110a: 4618 mov r0, r3 + 800110c: f004 f9b6 bl 800547c + TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + 8001110: 463b mov r3, r7 + 8001112: 2200 movs r2, #0 + 8001114: 601a str r2, [r3, #0] + 8001116: 605a str r2, [r3, #4] + 8001118: 609a str r2, [r3, #8] + + /* USER CODE BEGIN TIM5_Init 1 */ + + /* USER CODE END TIM5_Init 1 */ + htim5.Instance = TIM5; + 800111a: 4b26 ldr r3, [pc, #152] ; (80011b4 <_ZL12MX_TIM5_Initv+0xb8>) + 800111c: 4a26 ldr r2, [pc, #152] ; (80011b8 <_ZL12MX_TIM5_Initv+0xbc>) + 800111e: 601a str r2, [r3, #0] + htim5.Init.Prescaler = 0; + 8001120: 4b24 ldr r3, [pc, #144] ; (80011b4 <_ZL12MX_TIM5_Initv+0xb8>) + 8001122: 2200 movs r2, #0 + 8001124: 605a str r2, [r3, #4] + htim5.Init.CounterMode = TIM_COUNTERMODE_UP; + 8001126: 4b23 ldr r3, [pc, #140] ; (80011b4 <_ZL12MX_TIM5_Initv+0xb8>) + 8001128: 2200 movs r2, #0 + 800112a: 609a str r2, [r3, #8] + htim5.Init.Period = 4294967295; + 800112c: 4b21 ldr r3, [pc, #132] ; (80011b4 <_ZL12MX_TIM5_Initv+0xb8>) + 800112e: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 8001132: 60da str r2, [r3, #12] + htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8001134: 4b1f ldr r3, [pc, #124] ; (80011b4 <_ZL12MX_TIM5_Initv+0xb8>) + 8001136: 2200 movs r2, #0 + 8001138: 611a str r2, [r3, #16] + htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 800113a: 4b1e ldr r3, [pc, #120] ; (80011b4 <_ZL12MX_TIM5_Initv+0xb8>) + 800113c: 2200 movs r2, #0 + 800113e: 619a str r2, [r3, #24] + sConfig.EncoderMode = TIM_ENCODERMODE_TI12; + 8001140: 2303 movs r3, #3 + 8001142: 60fb str r3, [r7, #12] + sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; + 8001144: 2300 movs r3, #0 + 8001146: 613b str r3, [r7, #16] + sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; + 8001148: 2301 movs r3, #1 + 800114a: 617b str r3, [r7, #20] + sConfig.IC1Prescaler = TIM_ICPSC_DIV1; + 800114c: 2300 movs r3, #0 + 800114e: 61bb str r3, [r7, #24] + sConfig.IC1Filter = 0; + 8001150: 2300 movs r3, #0 + 8001152: 61fb str r3, [r7, #28] + sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; + 8001154: 2300 movs r3, #0 + 8001156: 623b str r3, [r7, #32] + sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; + 8001158: 2301 movs r3, #1 + 800115a: 627b str r3, [r7, #36] ; 0x24 + sConfig.IC2Prescaler = TIM_ICPSC_DIV1; + 800115c: 2300 movs r3, #0 + 800115e: 62bb str r3, [r7, #40] ; 0x28 + sConfig.IC2Filter = 0; + 8001160: 2300 movs r3, #0 + 8001162: 62fb str r3, [r7, #44] ; 0x2c + if (HAL_TIM_Encoder_Init(&htim5, &sConfig) != HAL_OK) { + 8001164: f107 030c add.w r3, r7, #12 + 8001168: 4619 mov r1, r3 + 800116a: 4812 ldr r0, [pc, #72] ; (80011b4 <_ZL12MX_TIM5_Initv+0xb8>) + 800116c: f002 f9e4 bl 8003538 + 8001170: 4603 mov r3, r0 + 8001172: 2b00 cmp r3, #0 + 8001174: bf14 ite ne + 8001176: 2301 movne r3, #1 + 8001178: 2300 moveq r3, #0 + 800117a: b2db uxtb r3, r3 + 800117c: 2b00 cmp r3, #0 + 800117e: d001 beq.n 8001184 <_ZL12MX_TIM5_Initv+0x88> + Error_Handler(); + 8001180: f000 fa86 bl 8001690 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8001184: 2300 movs r3, #0 + 8001186: 603b str r3, [r7, #0] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8001188: 2300 movs r3, #0 + 800118a: 60bb str r3, [r7, #8] + if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) { + 800118c: 463b mov r3, r7 + 800118e: 4619 mov r1, r3 + 8001190: 4808 ldr r0, [pc, #32] ; (80011b4 <_ZL12MX_TIM5_Initv+0xb8>) + 8001192: f003 f971 bl 8004478 + 8001196: 4603 mov r3, r0 + 8001198: 2b00 cmp r3, #0 + 800119a: bf14 ite ne + 800119c: 2301 movne r3, #1 + 800119e: 2300 moveq r3, #0 + 80011a0: b2db uxtb r3, r3 + 80011a2: 2b00 cmp r3, #0 + 80011a4: d001 beq.n 80011aa <_ZL12MX_TIM5_Initv+0xae> + Error_Handler(); + 80011a6: f000 fa73 bl 8001690 + } + /* USER CODE BEGIN TIM5_Init 2 */ + + /* USER CODE END TIM5_Init 2 */ + +} + 80011aa: bf00 nop + 80011ac: 3730 adds r7, #48 ; 0x30 + 80011ae: 46bd mov sp, r7 + 80011b0: bd80 pop {r7, pc} + 80011b2: bf00 nop + 80011b4: 200000ec .word 0x200000ec + 80011b8: 40000c00 .word 0x40000c00 + +080011bc <_ZL12MX_TIM6_Initv>: +/** + * @brief TIM6 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM6_Init(void) { + 80011bc: b580 push {r7, lr} + 80011be: b084 sub sp, #16 + 80011c0: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM6_Init 0 */ + + /* USER CODE END TIM6_Init 0 */ + + TIM_MasterConfigTypeDef sMasterConfig = { 0 }; + 80011c2: 1d3b adds r3, r7, #4 + 80011c4: 2200 movs r2, #0 + 80011c6: 601a str r2, [r3, #0] + 80011c8: 605a str r2, [r3, #4] + 80011ca: 609a str r2, [r3, #8] + + /* USER CODE BEGIN TIM6_Init 1 */ + + /* USER CODE END TIM6_Init 1 */ + htim6.Instance = TIM6; + 80011cc: 4b1a ldr r3, [pc, #104] ; (8001238 <_ZL12MX_TIM6_Initv+0x7c>) + 80011ce: 4a1b ldr r2, [pc, #108] ; (800123c <_ZL12MX_TIM6_Initv+0x80>) + 80011d0: 601a str r2, [r3, #0] + htim6.Init.Prescaler = 9999; + 80011d2: 4b19 ldr r3, [pc, #100] ; (8001238 <_ZL12MX_TIM6_Initv+0x7c>) + 80011d4: f242 720f movw r2, #9999 ; 0x270f + 80011d8: 605a str r2, [r3, #4] + htim6.Init.CounterMode = TIM_COUNTERMODE_UP; + 80011da: 4b17 ldr r3, [pc, #92] ; (8001238 <_ZL12MX_TIM6_Initv+0x7c>) + 80011dc: 2200 movs r2, #0 + 80011de: 609a str r2, [r3, #8] + htim6.Init.Period = 799; + 80011e0: 4b15 ldr r3, [pc, #84] ; (8001238 <_ZL12MX_TIM6_Initv+0x7c>) + 80011e2: f240 321f movw r2, #799 ; 0x31f + 80011e6: 60da str r2, [r3, #12] + htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 80011e8: 4b13 ldr r3, [pc, #76] ; (8001238 <_ZL12MX_TIM6_Initv+0x7c>) + 80011ea: 2200 movs r2, #0 + 80011ec: 619a str r2, [r3, #24] + if (HAL_TIM_Base_Init(&htim6) != HAL_OK) { + 80011ee: 4812 ldr r0, [pc, #72] ; (8001238 <_ZL12MX_TIM6_Initv+0x7c>) + 80011f0: f002 f8d2 bl 8003398 + 80011f4: 4603 mov r3, r0 + 80011f6: 2b00 cmp r3, #0 + 80011f8: bf14 ite ne + 80011fa: 2301 movne r3, #1 + 80011fc: 2300 moveq r3, #0 + 80011fe: b2db uxtb r3, r3 + 8001200: 2b00 cmp r3, #0 + 8001202: d001 beq.n 8001208 <_ZL12MX_TIM6_Initv+0x4c> + Error_Handler(); + 8001204: f000 fa44 bl 8001690 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8001208: 2300 movs r3, #0 + 800120a: 607b str r3, [r7, #4] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 800120c: 2300 movs r3, #0 + 800120e: 60fb str r3, [r7, #12] + if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) { + 8001210: 1d3b adds r3, r7, #4 + 8001212: 4619 mov r1, r3 + 8001214: 4808 ldr r0, [pc, #32] ; (8001238 <_ZL12MX_TIM6_Initv+0x7c>) + 8001216: f003 f92f bl 8004478 + 800121a: 4603 mov r3, r0 + 800121c: 2b00 cmp r3, #0 + 800121e: bf14 ite ne + 8001220: 2301 movne r3, #1 + 8001222: 2300 moveq r3, #0 + 8001224: b2db uxtb r3, r3 + 8001226: 2b00 cmp r3, #0 + 8001228: d001 beq.n 800122e <_ZL12MX_TIM6_Initv+0x72> + Error_Handler(); + 800122a: f000 fa31 bl 8001690 + } + /* USER CODE BEGIN TIM6_Init 2 */ + + /* USER CODE END TIM6_Init 2 */ + +} + 800122e: bf00 nop + 8001230: 3710 adds r7, #16 + 8001232: 46bd mov sp, r7 + 8001234: bd80 pop {r7, pc} + 8001236: bf00 nop + 8001238: 2000012c .word 0x2000012c + 800123c: 40001000 .word 0x40001000 + +08001240 <_ZL19MX_USART6_UART_Initv>: +/** + * @brief USART6 Initialization Function + * @param None + * @retval None + */ +static void MX_USART6_UART_Init(void) { + 8001240: b580 push {r7, lr} + 8001242: af00 add r7, sp, #0 + /* USER CODE END USART6_Init 0 */ + + /* USER CODE BEGIN USART6_Init 1 */ + + /* USER CODE END USART6_Init 1 */ + huart6.Instance = USART6; + 8001244: 4b16 ldr r3, [pc, #88] ; (80012a0 <_ZL19MX_USART6_UART_Initv+0x60>) + 8001246: 4a17 ldr r2, [pc, #92] ; (80012a4 <_ZL19MX_USART6_UART_Initv+0x64>) + 8001248: 601a str r2, [r3, #0] + huart6.Init.BaudRate = 115200; + 800124a: 4b15 ldr r3, [pc, #84] ; (80012a0 <_ZL19MX_USART6_UART_Initv+0x60>) + 800124c: f44f 32e1 mov.w r2, #115200 ; 0x1c200 + 8001250: 605a str r2, [r3, #4] + huart6.Init.WordLength = UART_WORDLENGTH_8B; + 8001252: 4b13 ldr r3, [pc, #76] ; (80012a0 <_ZL19MX_USART6_UART_Initv+0x60>) + 8001254: 2200 movs r2, #0 + 8001256: 609a str r2, [r3, #8] + huart6.Init.StopBits = UART_STOPBITS_1; + 8001258: 4b11 ldr r3, [pc, #68] ; (80012a0 <_ZL19MX_USART6_UART_Initv+0x60>) + 800125a: 2200 movs r2, #0 + 800125c: 60da str r2, [r3, #12] + huart6.Init.Parity = UART_PARITY_NONE; + 800125e: 4b10 ldr r3, [pc, #64] ; (80012a0 <_ZL19MX_USART6_UART_Initv+0x60>) + 8001260: 2200 movs r2, #0 + 8001262: 611a str r2, [r3, #16] + huart6.Init.Mode = UART_MODE_TX_RX; + 8001264: 4b0e ldr r3, [pc, #56] ; (80012a0 <_ZL19MX_USART6_UART_Initv+0x60>) + 8001266: 220c movs r2, #12 + 8001268: 615a str r2, [r3, #20] + huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 800126a: 4b0d ldr r3, [pc, #52] ; (80012a0 <_ZL19MX_USART6_UART_Initv+0x60>) + 800126c: 2200 movs r2, #0 + 800126e: 619a str r2, [r3, #24] + huart6.Init.OverSampling = UART_OVERSAMPLING_16; + 8001270: 4b0b ldr r3, [pc, #44] ; (80012a0 <_ZL19MX_USART6_UART_Initv+0x60>) + 8001272: 2200 movs r2, #0 + 8001274: 61da str r2, [r3, #28] + huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 8001276: 4b0a ldr r3, [pc, #40] ; (80012a0 <_ZL19MX_USART6_UART_Initv+0x60>) + 8001278: 2200 movs r2, #0 + 800127a: 621a str r2, [r3, #32] + huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 800127c: 4b08 ldr r3, [pc, #32] ; (80012a0 <_ZL19MX_USART6_UART_Initv+0x60>) + 800127e: 2200 movs r2, #0 + 8001280: 625a str r2, [r3, #36] ; 0x24 + if (HAL_UART_Init(&huart6) != HAL_OK) { + 8001282: 4807 ldr r0, [pc, #28] ; (80012a0 <_ZL19MX_USART6_UART_Initv+0x60>) + 8001284: f003 f972 bl 800456c + 8001288: 4603 mov r3, r0 + 800128a: 2b00 cmp r3, #0 + 800128c: bf14 ite ne + 800128e: 2301 movne r3, #1 + 8001290: 2300 moveq r3, #0 + 8001292: b2db uxtb r3, r3 + 8001294: 2b00 cmp r3, #0 + 8001296: d001 beq.n 800129c <_ZL19MX_USART6_UART_Initv+0x5c> + Error_Handler(); + 8001298: f000 f9fa bl 8001690 + } + /* USER CODE BEGIN USART6_Init 2 */ + + /* USER CODE END USART6_Init 2 */ + +} + 800129c: bf00 nop + 800129e: bd80 pop {r7, pc} + 80012a0: 2000016c .word 0x2000016c + 80012a4: 40011400 .word 0x40011400 + +080012a8 <_ZL12MX_GPIO_Initv>: +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) { + 80012a8: b580 push {r7, lr} + 80012aa: b08c sub sp, #48 ; 0x30 + 80012ac: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = { 0 }; + 80012ae: f107 031c add.w r3, r7, #28 + 80012b2: 2200 movs r2, #0 + 80012b4: 601a str r2, [r3, #0] + 80012b6: 605a str r2, [r3, #4] + 80012b8: 609a str r2, [r3, #8] + 80012ba: 60da str r2, [r3, #12] + 80012bc: 611a str r2, [r3, #16] + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 80012be: 4b5e ldr r3, [pc, #376] ; (8001438 <_ZL12MX_GPIO_Initv+0x190>) + 80012c0: 6b1b ldr r3, [r3, #48] ; 0x30 + 80012c2: 4a5d ldr r2, [pc, #372] ; (8001438 <_ZL12MX_GPIO_Initv+0x190>) + 80012c4: f043 0304 orr.w r3, r3, #4 + 80012c8: 6313 str r3, [r2, #48] ; 0x30 + 80012ca: 4b5b ldr r3, [pc, #364] ; (8001438 <_ZL12MX_GPIO_Initv+0x190>) + 80012cc: 6b1b ldr r3, [r3, #48] ; 0x30 + 80012ce: f003 0304 and.w r3, r3, #4 + 80012d2: 61bb str r3, [r7, #24] + 80012d4: 69bb ldr r3, [r7, #24] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80012d6: 4b58 ldr r3, [pc, #352] ; (8001438 <_ZL12MX_GPIO_Initv+0x190>) + 80012d8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80012da: 4a57 ldr r2, [pc, #348] ; (8001438 <_ZL12MX_GPIO_Initv+0x190>) + 80012dc: f043 0301 orr.w r3, r3, #1 + 80012e0: 6313 str r3, [r2, #48] ; 0x30 + 80012e2: 4b55 ldr r3, [pc, #340] ; (8001438 <_ZL12MX_GPIO_Initv+0x190>) + 80012e4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80012e6: f003 0301 and.w r3, r3, #1 + 80012ea: 617b str r3, [r7, #20] + 80012ec: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOF_CLK_ENABLE(); + 80012ee: 4b52 ldr r3, [pc, #328] ; (8001438 <_ZL12MX_GPIO_Initv+0x190>) + 80012f0: 6b1b ldr r3, [r3, #48] ; 0x30 + 80012f2: 4a51 ldr r2, [pc, #324] ; (8001438 <_ZL12MX_GPIO_Initv+0x190>) + 80012f4: f043 0320 orr.w r3, r3, #32 + 80012f8: 6313 str r3, [r2, #48] ; 0x30 + 80012fa: 4b4f ldr r3, [pc, #316] ; (8001438 <_ZL12MX_GPIO_Initv+0x190>) + 80012fc: 6b1b ldr r3, [r3, #48] ; 0x30 + 80012fe: f003 0320 and.w r3, r3, #32 + 8001302: 613b str r3, [r7, #16] + 8001304: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOE_CLK_ENABLE(); + 8001306: 4b4c ldr r3, [pc, #304] ; (8001438 <_ZL12MX_GPIO_Initv+0x190>) + 8001308: 6b1b ldr r3, [r3, #48] ; 0x30 + 800130a: 4a4b ldr r2, [pc, #300] ; (8001438 <_ZL12MX_GPIO_Initv+0x190>) + 800130c: f043 0310 orr.w r3, r3, #16 + 8001310: 6313 str r3, [r2, #48] ; 0x30 + 8001312: 4b49 ldr r3, [pc, #292] ; (8001438 <_ZL12MX_GPIO_Initv+0x190>) + 8001314: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001316: f003 0310 and.w r3, r3, #16 + 800131a: 60fb str r3, [r7, #12] + 800131c: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOD_CLK_ENABLE(); + 800131e: 4b46 ldr r3, [pc, #280] ; (8001438 <_ZL12MX_GPIO_Initv+0x190>) + 8001320: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001322: 4a45 ldr r2, [pc, #276] ; (8001438 <_ZL12MX_GPIO_Initv+0x190>) + 8001324: f043 0308 orr.w r3, r3, #8 + 8001328: 6313 str r3, [r2, #48] ; 0x30 + 800132a: 4b43 ldr r3, [pc, #268] ; (8001438 <_ZL12MX_GPIO_Initv+0x190>) + 800132c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800132e: f003 0308 and.w r3, r3, #8 + 8001332: 60bb str r3, [r7, #8] + 8001334: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8001336: 4b40 ldr r3, [pc, #256] ; (8001438 <_ZL12MX_GPIO_Initv+0x190>) + 8001338: 6b1b ldr r3, [r3, #48] ; 0x30 + 800133a: 4a3f ldr r2, [pc, #252] ; (8001438 <_ZL12MX_GPIO_Initv+0x190>) + 800133c: f043 0302 orr.w r3, r3, #2 + 8001340: 6313 str r3, [r2, #48] ; 0x30 + 8001342: 4b3d ldr r3, [pc, #244] ; (8001438 <_ZL12MX_GPIO_Initv+0x190>) + 8001344: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001346: f003 0302 and.w r3, r3, #2 + 800134a: 607b str r3, [r7, #4] + 800134c: 687b ldr r3, [r7, #4] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOF, dir2_Pin | dir1_Pin, GPIO_PIN_RESET); + 800134e: 2200 movs r2, #0 + 8001350: f44f 5140 mov.w r1, #12288 ; 0x3000 + 8001354: 4839 ldr r0, [pc, #228] ; (800143c <_ZL12MX_GPIO_Initv+0x194>) + 8001356: f000 ff87 bl 8002268 + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOF, sleep2_Pin | sleep1_Pin, GPIO_PIN_SET); + 800135a: 2201 movs r2, #1 + 800135c: f44f 4140 mov.w r1, #49152 ; 0xc000 + 8001360: 4836 ldr r0, [pc, #216] ; (800143c <_ZL12MX_GPIO_Initv+0x194>) + 8001362: f000 ff81 bl 8002268 + + /*Configure GPIO pin : user_button_Pin */ + GPIO_InitStruct.Pin = user_button_Pin; + 8001366: f44f 5300 mov.w r3, #8192 ; 0x2000 + 800136a: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + 800136c: 4b34 ldr r3, [pc, #208] ; (8001440 <_ZL12MX_GPIO_Initv+0x198>) + 800136e: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001370: 2300 movs r3, #0 + 8001372: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(user_button_GPIO_Port, &GPIO_InitStruct); + 8001374: f107 031c add.w r3, r7, #28 + 8001378: 4619 mov r1, r3 + 800137a: 4832 ldr r0, [pc, #200] ; (8001444 <_ZL12MX_GPIO_Initv+0x19c>) + 800137c: f000 fdca bl 8001f14 + + /*Configure GPIO pin : current2_Pin */ + GPIO_InitStruct.Pin = current2_Pin; + 8001380: 2301 movs r3, #1 + 8001382: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 8001384: 2303 movs r3, #3 + 8001386: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001388: 2300 movs r3, #0 + 800138a: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(current2_GPIO_Port, &GPIO_InitStruct); + 800138c: f107 031c add.w r3, r7, #28 + 8001390: 4619 mov r1, r3 + 8001392: 482c ldr r0, [pc, #176] ; (8001444 <_ZL12MX_GPIO_Initv+0x19c>) + 8001394: f000 fdbe bl 8001f14 + + /*Configure GPIO pin : current1_Pin */ + GPIO_InitStruct.Pin = current1_Pin; + 8001398: 2308 movs r3, #8 + 800139a: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 800139c: 2303 movs r3, #3 + 800139e: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80013a0: 2300 movs r3, #0 + 80013a2: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(current1_GPIO_Port, &GPIO_InitStruct); + 80013a4: f107 031c add.w r3, r7, #28 + 80013a8: 4619 mov r1, r3 + 80013aa: 4827 ldr r0, [pc, #156] ; (8001448 <_ZL12MX_GPIO_Initv+0x1a0>) + 80013ac: f000 fdb2 bl 8001f14 + + /*Configure GPIO pin : fault2_Pin */ + GPIO_InitStruct.Pin = fault2_Pin; + 80013b0: 2340 movs r3, #64 ; 0x40 + 80013b2: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 80013b4: 2300 movs r3, #0 + 80013b6: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80013b8: 2300 movs r3, #0 + 80013ba: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(fault2_GPIO_Port, &GPIO_InitStruct); + 80013bc: f107 031c add.w r3, r7, #28 + 80013c0: 4619 mov r1, r3 + 80013c2: 4821 ldr r0, [pc, #132] ; (8001448 <_ZL12MX_GPIO_Initv+0x1a0>) + 80013c4: f000 fda6 bl 8001f14 + + /*Configure GPIO pins : dir2_Pin dir1_Pin */ + GPIO_InitStruct.Pin = dir2_Pin | dir1_Pin; + 80013c8: f44f 5340 mov.w r3, #12288 ; 0x3000 + 80013cc: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 80013ce: 2301 movs r3, #1 + 80013d0: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80013d2: 2300 movs r3, #0 + 80013d4: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80013d6: 2300 movs r3, #0 + 80013d8: 62bb str r3, [r7, #40] ; 0x28 + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + 80013da: f107 031c add.w r3, r7, #28 + 80013de: 4619 mov r1, r3 + 80013e0: 4816 ldr r0, [pc, #88] ; (800143c <_ZL12MX_GPIO_Initv+0x194>) + 80013e2: f000 fd97 bl 8001f14 + + /*Configure GPIO pins : sleep2_Pin sleep1_Pin */ + GPIO_InitStruct.Pin = sleep2_Pin | sleep1_Pin; + 80013e6: f44f 4340 mov.w r3, #49152 ; 0xc000 + 80013ea: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 80013ec: 2301 movs r3, #1 + 80013ee: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 80013f0: 2301 movs r3, #1 + 80013f2: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80013f4: 2300 movs r3, #0 + 80013f6: 62bb str r3, [r7, #40] ; 0x28 + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + 80013f8: f107 031c add.w r3, r7, #28 + 80013fc: 4619 mov r1, r3 + 80013fe: 480f ldr r0, [pc, #60] ; (800143c <_ZL12MX_GPIO_Initv+0x194>) + 8001400: f000 fd88 bl 8001f14 + + /*Configure GPIO pin : fault1_Pin */ + GPIO_InitStruct.Pin = fault1_Pin; + 8001404: f44f 7300 mov.w r3, #512 ; 0x200 + 8001408: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 800140a: 2300 movs r3, #0 + 800140c: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800140e: 2300 movs r3, #0 + 8001410: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(fault1_GPIO_Port, &GPIO_InitStruct); + 8001412: f107 031c add.w r3, r7, #28 + 8001416: 4619 mov r1, r3 + 8001418: 480c ldr r0, [pc, #48] ; (800144c <_ZL12MX_GPIO_Initv+0x1a4>) + 800141a: f000 fd7b bl 8001f14 + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); + 800141e: 2200 movs r2, #0 + 8001420: 2100 movs r1, #0 + 8001422: 2028 movs r0, #40 ; 0x28 + 8001424: f000 fd1d bl 8001e62 + HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); + 8001428: 2028 movs r0, #40 ; 0x28 + 800142a: f000 fd36 bl 8001e9a + +} + 800142e: bf00 nop + 8001430: 3730 adds r7, #48 ; 0x30 + 8001432: 46bd mov sp, r7 + 8001434: bd80 pop {r7, pc} + 8001436: bf00 nop + 8001438: 40023800 .word 0x40023800 + 800143c: 40021400 .word 0x40021400 + 8001440: 10110000 .word 0x10110000 + 8001444: 40020800 .word 0x40020800 + 8001448: 40020000 .word 0x40020000 + 800144c: 40021000 .word 0x40021000 + +08001450 : + +/* USER CODE BEGIN 4 */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { + 8001450: b580 push {r7, lr} + 8001452: b082 sub sp, #8 + 8001454: af00 add r7, sp, #0 + 8001456: 6078 str r0, [r7, #4] + + //TIMER 100Hz PID control + if (htim->Instance == TIM3) { + 8001458: 687b ldr r3, [r7, #4] + 800145a: 681b ldr r3, [r3, #0] + 800145c: 4a1a ldr r2, [pc, #104] ; (80014c8 ) + 800145e: 4293 cmp r3, r2 + 8001460: d12d bne.n 80014be + + left_pid.set(0.5); + 8001462: eeb6 0a00 vmov.f32 s0, #96 ; 0x3f000000 0.5 + 8001466: 4819 ldr r0, [pc, #100] ; (80014cc ) + 8001468: f7ff fb65 bl 8000b36 <_ZN3Pid3setEf> + right_pid.set(0.5); + 800146c: eeb6 0a00 vmov.f32 s0, #96 ; 0x3f000000 0.5 + 8001470: 4817 ldr r0, [pc, #92] ; (80014d0 ) + 8001472: f7ff fb60 bl 8000b36 <_ZN3Pid3setEf> + cross_pid.set(0); + 8001476: ed9f 0a17 vldr s0, [pc, #92] ; 80014d4 + 800147a: 4817 ldr r0, [pc, #92] ; (80014d8 ) + 800147c: f7ff fb5b bl 8000b36 <_ZN3Pid3setEf> + +// left_velocity = left_encoder.GetLinearVelocity(); +// left_dutycycle = left_pid.update(left_velocity); +// left_motor.set_speed(left_dutycycle); + + right_velocity = right_encoder.GetLinearVelocity(); + 8001480: 4816 ldr r0, [pc, #88] ; (80014dc ) + 8001482: f7ff f8e9 bl 8000658 <_ZN7Encoder17GetLinearVelocityEv> + 8001486: eef0 7a40 vmov.f32 s15, s0 + 800148a: 4b15 ldr r3, [pc, #84] ; (80014e0 ) + 800148c: edc3 7a00 vstr s15, [r3] + right_dutycycle = right_pid.update(right_velocity); + 8001490: 4b13 ldr r3, [pc, #76] ; (80014e0 ) + 8001492: edd3 7a00 vldr s15, [r3] + 8001496: eeb0 0a67 vmov.f32 s0, s15 + 800149a: 480d ldr r0, [pc, #52] ; (80014d0 ) + 800149c: f7ff fb5a bl 8000b54 <_ZN3Pid6updateEf> + 80014a0: 4602 mov r2, r0 + 80014a2: 4b10 ldr r3, [pc, #64] ; (80014e4 ) + 80014a4: 601a str r2, [r3, #0] + right_motor.set_speed(right_dutycycle); + 80014a6: 4b0f ldr r3, [pc, #60] ; (80014e4 ) + 80014a8: 681b ldr r3, [r3, #0] + 80014aa: 4619 mov r1, r3 + 80014ac: 480e ldr r0, [pc, #56] ; (80014e8 ) + 80014ae: f7ff f9af bl 8000810 <_ZN15MotorController9set_speedEi> +// int cross_dutycycle = cross_pid.update(difference); +// +// left_dutycycle += cross_dutycycle; +// right_dutycycle -= cross_dutycycle; + + HAL_UART_Transmit(&huart6, (uint8_t*) &right_velocity, 4, 100); + 80014b2: 2364 movs r3, #100 ; 0x64 + 80014b4: 2204 movs r2, #4 + 80014b6: 490a ldr r1, [pc, #40] ; (80014e0 ) + 80014b8: 480c ldr r0, [pc, #48] ; (80014ec ) + 80014ba: f003 f8a5 bl 8004608 + } + + //TIMER 2Hz Transmit + if (htim->Instance == TIM6) { + } +} + 80014be: bf00 nop + 80014c0: 3708 adds r7, #8 + 80014c2: 46bd mov sp, r7 + 80014c4: bd80 pop {r7, pc} + 80014c6: bf00 nop + 80014c8: 40000400 .word 0x40000400 + 80014cc: 20000228 .word 0x20000228 + 80014d0: 2000024c .word 0x2000024c + 80014d4: 00000000 .word 0x00000000 + 80014d8: 20000270 .word 0x20000270 + 80014dc: 200001ec .word 0x200001ec + 80014e0: 20000224 .word 0x20000224 + 80014e4: 200002a0 .word 0x200002a0 + 80014e8: 200002a4 .word 0x200002a4 + 80014ec: 2000016c .word 0x2000016c + +080014f0 : + +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *UartHandle) { + 80014f0: b580 push {r7, lr} + 80014f2: b082 sub sp, #8 + 80014f4: af00 add r7, sp, #0 + 80014f6: 6078 str r0, [r7, #4] + + odom.UpdateValues(input_msg.linear_velocity, input_msg.angular_velocity); + 80014f8: 4b25 ldr r3, [pc, #148] ; (8001590 ) + 80014fa: edd3 7a00 vldr s15, [r3] + 80014fe: 4b24 ldr r3, [pc, #144] ; (8001590 ) + 8001500: ed93 7a01 vldr s14, [r3, #4] + 8001504: eef0 0a47 vmov.f32 s1, s14 + 8001508: eeb0 0a67 vmov.f32 s0, s15 + 800150c: 4821 ldr r0, [pc, #132] ; (8001594 ) + 800150e: f7ff f8ef bl 80006f0 <_ZN8Odometry12UpdateValuesEff> + + left_setpoint = odom.GetLeftVelocity(); + 8001512: 4820 ldr r0, [pc, #128] ; (8001594 ) + 8001514: f7ff f92c bl 8000770 <_ZN8Odometry15GetLeftVelocityEv> + 8001518: eef0 7a40 vmov.f32 s15, s0 + 800151c: 4b1e ldr r3, [pc, #120] ; (8001598 ) + 800151e: edc3 7a00 vstr s15, [r3] + right_setpoint = odom.GetRightVelocity(); + 8001522: 481c ldr r0, [pc, #112] ; (8001594 ) + 8001524: f7ff f933 bl 800078e <_ZN8Odometry16GetRightVelocityEv> + 8001528: eef0 7a40 vmov.f32 s15, s0 + 800152c: 4b1b ldr r3, [pc, #108] ; (800159c ) + 800152e: edc3 7a00 vstr s15, [r3] + + left_pid.set(left_setpoint); + 8001532: 4b19 ldr r3, [pc, #100] ; (8001598 ) + 8001534: edd3 7a00 vldr s15, [r3] + 8001538: eeb0 0a67 vmov.f32 s0, s15 + 800153c: 4818 ldr r0, [pc, #96] ; (80015a0 ) + 800153e: f7ff fafa bl 8000b36 <_ZN3Pid3setEf> + right_pid.set(right_setpoint); + 8001542: 4b16 ldr r3, [pc, #88] ; (800159c ) + 8001544: edd3 7a00 vldr s15, [r3] + 8001548: eeb0 0a67 vmov.f32 s0, s15 + 800154c: 4815 ldr r0, [pc, #84] ; (80015a4 ) + 800154e: f7ff faf2 bl 8000b36 <_ZN3Pid3setEf> + + cross_setpoint = left_setpoint - right_setpoint; + 8001552: 4b11 ldr r3, [pc, #68] ; (8001598 ) + 8001554: ed93 7a00 vldr s14, [r3] + 8001558: 4b10 ldr r3, [pc, #64] ; (800159c ) + 800155a: edd3 7a00 vldr s15, [r3] + 800155e: ee77 7a67 vsub.f32 s15, s14, s15 + 8001562: 4b11 ldr r3, [pc, #68] ; (80015a8 ) + 8001564: edc3 7a00 vstr s15, [r3] + cross_pid.set(cross_setpoint); + 8001568: 4b0f ldr r3, [pc, #60] ; (80015a8 ) + 800156a: edd3 7a00 vldr s15, [r3] + 800156e: eeb0 0a67 vmov.f32 s0, s15 + 8001572: 480e ldr r0, [pc, #56] ; (80015ac ) + 8001574: f7ff fadf bl 8000b36 <_ZN3Pid3setEf> + + HAL_UART_Receive_IT(&huart6, rx_buffer, 8); + 8001578: 4b0d ldr r3, [pc, #52] ; (80015b0 ) + 800157a: 681b ldr r3, [r3, #0] + 800157c: 2208 movs r2, #8 + 800157e: 4619 mov r1, r3 + 8001580: 480c ldr r0, [pc, #48] ; (80015b4 ) + 8001582: f003 f8d3 bl 800472c + +} + 8001586: bf00 nop + 8001588: 3708 adds r7, #8 + 800158a: 46bd mov sp, r7 + 800158c: bd80 pop {r7, pc} + 800158e: bf00 nop + 8001590: 200002dc .word 0x200002dc + 8001594: 2000021c .word 0x2000021c + 8001598: 20000294 .word 0x20000294 + 800159c: 20000298 .word 0x20000298 + 80015a0: 20000228 .word 0x20000228 + 80015a4: 2000024c .word 0x2000024c + 80015a8: 2000029c .word 0x2000029c + 80015ac: 20000270 .word 0x20000270 + 80015b0: 200002d8 .word 0x200002d8 + 80015b4: 2000016c .word 0x2000016c + +080015b8 : + +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { + 80015b8: b580 push {r7, lr} + 80015ba: b082 sub sp, #8 + 80015bc: af00 add r7, sp, #0 + 80015be: 4603 mov r3, r0 + 80015c0: 80fb strh r3, [r7, #6] + //Blue user button + if (GPIO_Pin == GPIO_PIN_13) { + 80015c2: 88fb ldrh r3, [r7, #6] + 80015c4: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 80015c8: d149 bne.n 800165e + previous_millis = current_millis; + 80015ca: 4b27 ldr r3, [pc, #156] ; (8001668 ) + 80015cc: 681b ldr r3, [r3, #0] + 80015ce: 4a27 ldr r2, [pc, #156] ; (800166c ) + 80015d0: 6013 str r3, [r2, #0] + current_millis = HAL_GetTick(); + 80015d2: f000 fb5f bl 8001c94 + 80015d6: 4603 mov r3, r0 + 80015d8: 461a mov r2, r3 + 80015da: 4b23 ldr r3, [pc, #140] ; (8001668 ) + 80015dc: 601a str r2, [r3, #0] + if (current_millis - previous_millis < 500) + 80015de: 4b22 ldr r3, [pc, #136] ; (8001668 ) + 80015e0: 681a ldr r2, [r3, #0] + 80015e2: 4b22 ldr r3, [pc, #136] ; (800166c ) + 80015e4: 681b ldr r3, [r3, #0] + 80015e6: 1ad3 subs r3, r2, r3 + 80015e8: f5b3 7ffa cmp.w r3, #500 ; 0x1f4 + 80015ec: da03 bge.n 80015f6 + debounce = false; + 80015ee: 4b20 ldr r3, [pc, #128] ; (8001670 ) + 80015f0: 2200 movs r2, #0 + 80015f2: 701a strb r2, [r3, #0] + 80015f4: e002 b.n 80015fc + else + debounce = true; + 80015f6: 4b1e ldr r3, [pc, #120] ; (8001670 ) + 80015f8: 2201 movs r2, #1 + 80015fa: 701a strb r2, [r3, #0] + if (mode == 0 && debounce) { + 80015fc: 4b1d ldr r3, [pc, #116] ; (8001674 ) + 80015fe: edd3 7a00 vldr s15, [r3] + 8001602: eef5 7a40 vcmp.f32 s15, #0.0 + 8001606: eef1 fa10 vmrs APSR_nzcv, fpscr + 800160a: d10b bne.n 8001624 + 800160c: 4b18 ldr r3, [pc, #96] ; (8001670 ) + 800160e: 781b ldrb r3, [r3, #0] + 8001610: 2b00 cmp r3, #0 + 8001612: d007 beq.n 8001624 + mode = 1; + 8001614: 4b17 ldr r3, [pc, #92] ; (8001674 ) + 8001616: f04f 527e mov.w r2, #1065353216 ; 0x3f800000 + 800161a: 601a str r2, [r3, #0] + //Enables TIM3 interrupt (used for PID control) + HAL_TIM_Base_Start_IT(&htim3); + 800161c: 4816 ldr r0, [pc, #88] ; (8001678 ) + 800161e: f001 fee7 bl 80033f0 + HAL_UART_Transmit(&huart6, tx_buffer, 8, 100); + output_msg.left_ticks = 0; + output_msg.right_ticks = 0; + } + } +} + 8001622: e01c b.n 800165e + } else if (debounce) { + 8001624: 4b12 ldr r3, [pc, #72] ; (8001670 ) + 8001626: 781b ldrb r3, [r3, #0] + 8001628: 2b00 cmp r3, #0 + 800162a: d018 beq.n 800165e + mode = 2; + 800162c: 4b11 ldr r3, [pc, #68] ; (8001674 ) + 800162e: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 + 8001632: 601a str r2, [r3, #0] + output_msg.left_ticks = left_ticks; + 8001634: 4b11 ldr r3, [pc, #68] ; (800167c ) + 8001636: 681b ldr r3, [r3, #0] + 8001638: 4a11 ldr r2, [pc, #68] ; (8001680 ) + 800163a: 6013 str r3, [r2, #0] + output_msg.right_ticks = right_ticks; + 800163c: 4b11 ldr r3, [pc, #68] ; (8001684 ) + 800163e: 681b ldr r3, [r3, #0] + 8001640: 4a0f ldr r2, [pc, #60] ; (8001680 ) + 8001642: 6053 str r3, [r2, #4] + HAL_UART_Transmit(&huart6, tx_buffer, 8, 100); + 8001644: 4b10 ldr r3, [pc, #64] ; (8001688 ) + 8001646: 6819 ldr r1, [r3, #0] + 8001648: 2364 movs r3, #100 ; 0x64 + 800164a: 2208 movs r2, #8 + 800164c: 480f ldr r0, [pc, #60] ; (800168c ) + 800164e: f002 ffdb bl 8004608 + output_msg.left_ticks = 0; + 8001652: 4b0b ldr r3, [pc, #44] ; (8001680 ) + 8001654: 2200 movs r2, #0 + 8001656: 601a str r2, [r3, #0] + output_msg.right_ticks = 0; + 8001658: 4b09 ldr r3, [pc, #36] ; (8001680 ) + 800165a: 2200 movs r2, #0 + 800165c: 605a str r2, [r3, #4] +} + 800165e: bf00 nop + 8001660: 3708 adds r7, #8 + 8001662: 46bd mov sp, r7 + 8001664: bd80 pop {r7, pc} + 8001666: bf00 nop + 8001668: 200002f0 .word 0x200002f0 + 800166c: 200002ec .word 0x200002ec + 8001670: 20000000 .word 0x20000000 + 8001674: 200002f4 .word 0x200002f4 + 8001678: 2000006c .word 0x2000006c + 800167c: 200002f8 .word 0x200002f8 + 8001680: 200002e4 .word 0x200002e4 + 8001684: 200002fc .word 0x200002fc + 8001688: 200002d4 .word 0x200002d4 + 800168c: 2000016c .word 0x2000016c + +08001690 : + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) { + 8001690: b480 push {r7} + 8001692: af00 add r7, sp, #0 + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} + 8001694: bf00 nop + 8001696: 46bd mov sp, r7 + 8001698: f85d 7b04 ldr.w r7, [sp], #4 + 800169c: 4770 bx lr + ... + +080016a0 <_Z41__static_initialization_and_destruction_0ii>: + 80016a0: b580 push {r7, lr} + 80016a2: b086 sub sp, #24 + 80016a4: af04 add r7, sp, #16 + 80016a6: 6078 str r0, [r7, #4] + 80016a8: 6039 str r1, [r7, #0] + 80016aa: 687b ldr r3, [r7, #4] + 80016ac: 2b01 cmp r3, #1 + 80016ae: d14a bne.n 8001746 <_Z41__static_initialization_and_destruction_0ii+0xa6> + 80016b0: 683b ldr r3, [r7, #0] + 80016b2: f64f 72ff movw r2, #65535 ; 0xffff + 80016b6: 4293 cmp r3, r2 + 80016b8: d145 bne.n 8001746 <_Z41__static_initialization_and_destruction_0ii+0xa6> +Encoder right_encoder = Encoder(&htim5, RIGHT_WHEEL_CIRCUMFERENCE); + 80016ba: ed9f 0a25 vldr s0, [pc, #148] ; 8001750 <_Z41__static_initialization_and_destruction_0ii+0xb0> + 80016be: 4925 ldr r1, [pc, #148] ; (8001754 <_Z41__static_initialization_and_destruction_0ii+0xb4>) + 80016c0: 4825 ldr r0, [pc, #148] ; (8001758 <_Z41__static_initialization_and_destruction_0ii+0xb8>) + 80016c2: f7fe ff60 bl 8000586 <_ZN7EncoderC1EP17TIM_HandleTypeDeff> +Encoder left_encoder = Encoder(&htim2, LEFT_TICKS_PER_METER); + 80016c6: ed9f 0a25 vldr s0, [pc, #148] ; 800175c <_Z41__static_initialization_and_destruction_0ii+0xbc> + 80016ca: 4925 ldr r1, [pc, #148] ; (8001760 <_Z41__static_initialization_and_destruction_0ii+0xc0>) + 80016cc: 4825 ldr r0, [pc, #148] ; (8001764 <_Z41__static_initialization_and_destruction_0ii+0xc4>) + 80016ce: f7fe ff5a bl 8000586 <_ZN7EncoderC1EP17TIM_HandleTypeDeff> +Odometry odom = Odometry(); + 80016d2: 4825 ldr r0, [pc, #148] ; (8001768 <_Z41__static_initialization_and_destruction_0ii+0xc8>) + 80016d4: f7fe fff8 bl 80006c8 <_ZN8OdometryC1Ev> +Pid left_pid(0, 0, 0); + 80016d8: ed9f 1a24 vldr s2, [pc, #144] ; 800176c <_Z41__static_initialization_and_destruction_0ii+0xcc> + 80016dc: eddf 0a23 vldr s1, [pc, #140] ; 800176c <_Z41__static_initialization_and_destruction_0ii+0xcc> + 80016e0: ed9f 0a22 vldr s0, [pc, #136] ; 800176c <_Z41__static_initialization_and_destruction_0ii+0xcc> + 80016e4: 4822 ldr r0, [pc, #136] ; (8001770 <_Z41__static_initialization_and_destruction_0ii+0xd0>) + 80016e6: f7ff f9c9 bl 8000a7c <_ZN3PidC1Efff> +Pid right_pid(0, 0, 0); + 80016ea: ed9f 1a20 vldr s2, [pc, #128] ; 800176c <_Z41__static_initialization_and_destruction_0ii+0xcc> + 80016ee: eddf 0a1f vldr s1, [pc, #124] ; 800176c <_Z41__static_initialization_and_destruction_0ii+0xcc> + 80016f2: ed9f 0a1e vldr s0, [pc, #120] ; 800176c <_Z41__static_initialization_and_destruction_0ii+0xcc> + 80016f6: 481f ldr r0, [pc, #124] ; (8001774 <_Z41__static_initialization_and_destruction_0ii+0xd4>) + 80016f8: f7ff f9c0 bl 8000a7c <_ZN3PidC1Efff> +Pid cross_pid(0, 0, 0); + 80016fc: ed9f 1a1b vldr s2, [pc, #108] ; 800176c <_Z41__static_initialization_and_destruction_0ii+0xcc> + 8001700: eddf 0a1a vldr s1, [pc, #104] ; 800176c <_Z41__static_initialization_and_destruction_0ii+0xcc> + 8001704: ed9f 0a19 vldr s0, [pc, #100] ; 800176c <_Z41__static_initialization_and_destruction_0ii+0xcc> + 8001708: 481b ldr r0, [pc, #108] ; (8001778 <_Z41__static_initialization_and_destruction_0ii+0xd8>) + 800170a: f7ff f9b7 bl 8000a7c <_ZN3PidC1Efff> + TIM_CHANNEL_4); + 800170e: 230c movs r3, #12 + 8001710: 9302 str r3, [sp, #8] + 8001712: 4b1a ldr r3, [pc, #104] ; (800177c <_Z41__static_initialization_and_destruction_0ii+0xdc>) + 8001714: 9301 str r3, [sp, #4] + 8001716: f44f 5300 mov.w r3, #8192 ; 0x2000 + 800171a: 9300 str r3, [sp, #0] + 800171c: 4b18 ldr r3, [pc, #96] ; (8001780 <_Z41__static_initialization_and_destruction_0ii+0xe0>) + 800171e: f44f 4200 mov.w r2, #32768 ; 0x8000 + 8001722: 4917 ldr r1, [pc, #92] ; (8001780 <_Z41__static_initialization_and_destruction_0ii+0xe0>) + 8001724: 4817 ldr r0, [pc, #92] ; (8001784 <_Z41__static_initialization_and_destruction_0ii+0xe4>) + 8001726: f7ff f841 bl 80007ac <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm> + TIM_CHANNEL_3); + 800172a: 2308 movs r3, #8 + 800172c: 9302 str r3, [sp, #8] + 800172e: 4b13 ldr r3, [pc, #76] ; (800177c <_Z41__static_initialization_and_destruction_0ii+0xdc>) + 8001730: 9301 str r3, [sp, #4] + 8001732: f44f 5380 mov.w r3, #4096 ; 0x1000 + 8001736: 9300 str r3, [sp, #0] + 8001738: 4b11 ldr r3, [pc, #68] ; (8001780 <_Z41__static_initialization_and_destruction_0ii+0xe0>) + 800173a: f44f 4280 mov.w r2, #16384 ; 0x4000 + 800173e: 4910 ldr r1, [pc, #64] ; (8001780 <_Z41__static_initialization_and_destruction_0ii+0xe0>) + 8001740: 4811 ldr r0, [pc, #68] ; (8001788 <_Z41__static_initialization_and_destruction_0ii+0xe8>) + 8001742: f7ff f833 bl 80007ac <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm> +} + 8001746: bf00 nop + 8001748: 3708 adds r7, #8 + 800174a: 46bd mov sp, r7 + 800174c: bd80 pop {r7, pc} + 800174e: bf00 nop + 8001750: 3f4ccccd .word 0x3f4ccccd + 8001754: 200000ec .word 0x200000ec + 8001758: 200001ec .word 0x200001ec + 800175c: 483f3300 .word 0x483f3300 + 8001760: 2000002c .word 0x2000002c + 8001764: 20000204 .word 0x20000204 + 8001768: 2000021c .word 0x2000021c + 800176c: 00000000 .word 0x00000000 + 8001770: 20000228 .word 0x20000228 + 8001774: 2000024c .word 0x2000024c + 8001778: 20000270 .word 0x20000270 + 800177c: 200000ac .word 0x200000ac + 8001780: 40021400 .word 0x40021400 + 8001784: 200002a4 .word 0x200002a4 + 8001788: 200002bc .word 0x200002bc + +0800178c <_GLOBAL__sub_I_htim2>: + 800178c: b580 push {r7, lr} + 800178e: af00 add r7, sp, #0 + 8001790: f64f 71ff movw r1, #65535 ; 0xffff + 8001794: 2001 movs r0, #1 + 8001796: f7ff ff83 bl 80016a0 <_Z41__static_initialization_and_destruction_0ii> + 800179a: bd80 pop {r7, pc} + +0800179c : +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 800179c: b480 push {r7} + 800179e: b083 sub sp, #12 + 80017a0: af00 add r7, sp, #0 + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_PWR_CLK_ENABLE(); + 80017a2: 4b0f ldr r3, [pc, #60] ; (80017e0 ) + 80017a4: 6c1b ldr r3, [r3, #64] ; 0x40 + 80017a6: 4a0e ldr r2, [pc, #56] ; (80017e0 ) + 80017a8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 80017ac: 6413 str r3, [r2, #64] ; 0x40 + 80017ae: 4b0c ldr r3, [pc, #48] ; (80017e0 ) + 80017b0: 6c1b ldr r3, [r3, #64] ; 0x40 + 80017b2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 80017b6: 607b str r3, [r7, #4] + 80017b8: 687b ldr r3, [r7, #4] + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 80017ba: 4b09 ldr r3, [pc, #36] ; (80017e0 ) + 80017bc: 6c5b ldr r3, [r3, #68] ; 0x44 + 80017be: 4a08 ldr r2, [pc, #32] ; (80017e0 ) + 80017c0: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 80017c4: 6453 str r3, [r2, #68] ; 0x44 + 80017c6: 4b06 ldr r3, [pc, #24] ; (80017e0 ) + 80017c8: 6c5b ldr r3, [r3, #68] ; 0x44 + 80017ca: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 80017ce: 603b str r3, [r7, #0] + 80017d0: 683b ldr r3, [r7, #0] + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 80017d2: bf00 nop + 80017d4: 370c adds r7, #12 + 80017d6: 46bd mov sp, r7 + 80017d8: f85d 7b04 ldr.w r7, [sp], #4 + 80017dc: 4770 bx lr + 80017de: bf00 nop + 80017e0: 40023800 .word 0x40023800 + +080017e4 : +* This function configures the hardware resources used in this example +* @param htim_encoder: TIM_Encoder handle pointer +* @retval None +*/ +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder) +{ + 80017e4: b580 push {r7, lr} + 80017e6: b08c sub sp, #48 ; 0x30 + 80017e8: af00 add r7, sp, #0 + 80017ea: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80017ec: f107 031c add.w r3, r7, #28 + 80017f0: 2200 movs r2, #0 + 80017f2: 601a str r2, [r3, #0] + 80017f4: 605a str r2, [r3, #4] + 80017f6: 609a str r2, [r3, #8] + 80017f8: 60da str r2, [r3, #12] + 80017fa: 611a str r2, [r3, #16] + if(htim_encoder->Instance==TIM2) + 80017fc: 687b ldr r3, [r7, #4] + 80017fe: 681b ldr r3, [r3, #0] + 8001800: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 8001804: d144 bne.n 8001890 + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + 8001806: 4b3b ldr r3, [pc, #236] ; (80018f4 ) + 8001808: 6c1b ldr r3, [r3, #64] ; 0x40 + 800180a: 4a3a ldr r2, [pc, #232] ; (80018f4 ) + 800180c: f043 0301 orr.w r3, r3, #1 + 8001810: 6413 str r3, [r2, #64] ; 0x40 + 8001812: 4b38 ldr r3, [pc, #224] ; (80018f4 ) + 8001814: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001816: f003 0301 and.w r3, r3, #1 + 800181a: 61bb str r3, [r7, #24] + 800181c: 69bb ldr r3, [r7, #24] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800181e: 4b35 ldr r3, [pc, #212] ; (80018f4 ) + 8001820: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001822: 4a34 ldr r2, [pc, #208] ; (80018f4 ) + 8001824: f043 0301 orr.w r3, r3, #1 + 8001828: 6313 str r3, [r2, #48] ; 0x30 + 800182a: 4b32 ldr r3, [pc, #200] ; (80018f4 ) + 800182c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800182e: f003 0301 and.w r3, r3, #1 + 8001832: 617b str r3, [r7, #20] + 8001834: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8001836: 4b2f ldr r3, [pc, #188] ; (80018f4 ) + 8001838: 6b1b ldr r3, [r3, #48] ; 0x30 + 800183a: 4a2e ldr r2, [pc, #184] ; (80018f4 ) + 800183c: f043 0302 orr.w r3, r3, #2 + 8001840: 6313 str r3, [r2, #48] ; 0x30 + 8001842: 4b2c ldr r3, [pc, #176] ; (80018f4 ) + 8001844: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001846: f003 0302 and.w r3, r3, #2 + 800184a: 613b str r3, [r7, #16] + 800184c: 693b ldr r3, [r7, #16] + /**TIM2 GPIO Configuration + PA5 ------> TIM2_CH1 + PB3 ------> TIM2_CH2 + */ + GPIO_InitStruct.Pin = encoder_sx1_Pin; + 800184e: 2320 movs r3, #32 + 8001850: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001852: 2302 movs r3, #2 + 8001854: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001856: 2300 movs r3, #0 + 8001858: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800185a: 2300 movs r3, #0 + 800185c: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; + 800185e: 2301 movs r3, #1 + 8001860: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(encoder_sx1_GPIO_Port, &GPIO_InitStruct); + 8001862: f107 031c add.w r3, r7, #28 + 8001866: 4619 mov r1, r3 + 8001868: 4823 ldr r0, [pc, #140] ; (80018f8 ) + 800186a: f000 fb53 bl 8001f14 + + GPIO_InitStruct.Pin = encoder_sx2_Pin; + 800186e: 2308 movs r3, #8 + 8001870: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001872: 2302 movs r3, #2 + 8001874: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001876: 2300 movs r3, #0 + 8001878: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800187a: 2300 movs r3, #0 + 800187c: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; + 800187e: 2301 movs r3, #1 + 8001880: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(encoder_sx2_GPIO_Port, &GPIO_InitStruct); + 8001882: f107 031c add.w r3, r7, #28 + 8001886: 4619 mov r1, r3 + 8001888: 481c ldr r0, [pc, #112] ; (80018fc ) + 800188a: f000 fb43 bl 8001f14 + /* USER CODE BEGIN TIM5_MspInit 1 */ + + /* USER CODE END TIM5_MspInit 1 */ + } + +} + 800188e: e02c b.n 80018ea + else if(htim_encoder->Instance==TIM5) + 8001890: 687b ldr r3, [r7, #4] + 8001892: 681b ldr r3, [r3, #0] + 8001894: 4a1a ldr r2, [pc, #104] ; (8001900 ) + 8001896: 4293 cmp r3, r2 + 8001898: d127 bne.n 80018ea + __HAL_RCC_TIM5_CLK_ENABLE(); + 800189a: 4b16 ldr r3, [pc, #88] ; (80018f4 ) + 800189c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800189e: 4a15 ldr r2, [pc, #84] ; (80018f4 ) + 80018a0: f043 0308 orr.w r3, r3, #8 + 80018a4: 6413 str r3, [r2, #64] ; 0x40 + 80018a6: 4b13 ldr r3, [pc, #76] ; (80018f4 ) + 80018a8: 6c1b ldr r3, [r3, #64] ; 0x40 + 80018aa: f003 0308 and.w r3, r3, #8 + 80018ae: 60fb str r3, [r7, #12] + 80018b0: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80018b2: 4b10 ldr r3, [pc, #64] ; (80018f4 ) + 80018b4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80018b6: 4a0f ldr r2, [pc, #60] ; (80018f4 ) + 80018b8: f043 0301 orr.w r3, r3, #1 + 80018bc: 6313 str r3, [r2, #48] ; 0x30 + 80018be: 4b0d ldr r3, [pc, #52] ; (80018f4 ) + 80018c0: 6b1b ldr r3, [r3, #48] ; 0x30 + 80018c2: f003 0301 and.w r3, r3, #1 + 80018c6: 60bb str r3, [r7, #8] + 80018c8: 68bb ldr r3, [r7, #8] + GPIO_InitStruct.Pin = encoder_dx1_Pin|encoder_dx2_Pin; + 80018ca: 2303 movs r3, #3 + 80018cc: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80018ce: 2302 movs r3, #2 + 80018d0: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80018d2: 2300 movs r3, #0 + 80018d4: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80018d6: 2300 movs r3, #0 + 80018d8: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Alternate = GPIO_AF2_TIM5; + 80018da: 2302 movs r3, #2 + 80018dc: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80018de: f107 031c add.w r3, r7, #28 + 80018e2: 4619 mov r1, r3 + 80018e4: 4804 ldr r0, [pc, #16] ; (80018f8 ) + 80018e6: f000 fb15 bl 8001f14 +} + 80018ea: bf00 nop + 80018ec: 3730 adds r7, #48 ; 0x30 + 80018ee: 46bd mov sp, r7 + 80018f0: bd80 pop {r7, pc} + 80018f2: bf00 nop + 80018f4: 40023800 .word 0x40023800 + 80018f8: 40020000 .word 0x40020000 + 80018fc: 40020400 .word 0x40020400 + 8001900: 40000c00 .word 0x40000c00 + +08001904 : +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + 8001904: b480 push {r7} + 8001906: b087 sub sp, #28 + 8001908: af00 add r7, sp, #0 + 800190a: 6078 str r0, [r7, #4] + if(htim_base->Instance==TIM3) + 800190c: 687b ldr r3, [r7, #4] + 800190e: 681b ldr r3, [r3, #0] + 8001910: 4a1c ldr r2, [pc, #112] ; (8001984 ) + 8001912: 4293 cmp r3, r2 + 8001914: d10c bne.n 8001930 + { + /* USER CODE BEGIN TIM3_MspInit 0 */ + + /* USER CODE END TIM3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM3_CLK_ENABLE(); + 8001916: 4b1c ldr r3, [pc, #112] ; (8001988 ) + 8001918: 6c1b ldr r3, [r3, #64] ; 0x40 + 800191a: 4a1b ldr r2, [pc, #108] ; (8001988 ) + 800191c: f043 0302 orr.w r3, r3, #2 + 8001920: 6413 str r3, [r2, #64] ; 0x40 + 8001922: 4b19 ldr r3, [pc, #100] ; (8001988 ) + 8001924: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001926: f003 0302 and.w r3, r3, #2 + 800192a: 617b str r3, [r7, #20] + 800192c: 697b ldr r3, [r7, #20] + /* USER CODE BEGIN TIM6_MspInit 1 */ + + /* USER CODE END TIM6_MspInit 1 */ + } + +} + 800192e: e022 b.n 8001976 + else if(htim_base->Instance==TIM4) + 8001930: 687b ldr r3, [r7, #4] + 8001932: 681b ldr r3, [r3, #0] + 8001934: 4a15 ldr r2, [pc, #84] ; (800198c ) + 8001936: 4293 cmp r3, r2 + 8001938: d10c bne.n 8001954 + __HAL_RCC_TIM4_CLK_ENABLE(); + 800193a: 4b13 ldr r3, [pc, #76] ; (8001988 ) + 800193c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800193e: 4a12 ldr r2, [pc, #72] ; (8001988 ) + 8001940: f043 0304 orr.w r3, r3, #4 + 8001944: 6413 str r3, [r2, #64] ; 0x40 + 8001946: 4b10 ldr r3, [pc, #64] ; (8001988 ) + 8001948: 6c1b ldr r3, [r3, #64] ; 0x40 + 800194a: f003 0304 and.w r3, r3, #4 + 800194e: 613b str r3, [r7, #16] + 8001950: 693b ldr r3, [r7, #16] +} + 8001952: e010 b.n 8001976 + else if(htim_base->Instance==TIM6) + 8001954: 687b ldr r3, [r7, #4] + 8001956: 681b ldr r3, [r3, #0] + 8001958: 4a0d ldr r2, [pc, #52] ; (8001990 ) + 800195a: 4293 cmp r3, r2 + 800195c: d10b bne.n 8001976 + __HAL_RCC_TIM6_CLK_ENABLE(); + 800195e: 4b0a ldr r3, [pc, #40] ; (8001988 ) + 8001960: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001962: 4a09 ldr r2, [pc, #36] ; (8001988 ) + 8001964: f043 0310 orr.w r3, r3, #16 + 8001968: 6413 str r3, [r2, #64] ; 0x40 + 800196a: 4b07 ldr r3, [pc, #28] ; (8001988 ) + 800196c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800196e: f003 0310 and.w r3, r3, #16 + 8001972: 60fb str r3, [r7, #12] + 8001974: 68fb ldr r3, [r7, #12] +} + 8001976: bf00 nop + 8001978: 371c adds r7, #28 + 800197a: 46bd mov sp, r7 + 800197c: f85d 7b04 ldr.w r7, [sp], #4 + 8001980: 4770 bx lr + 8001982: bf00 nop + 8001984: 40000400 .word 0x40000400 + 8001988: 40023800 .word 0x40023800 + 800198c: 40000800 .word 0x40000800 + 8001990: 40001000 .word 0x40001000 + +08001994 : + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + 8001994: b580 push {r7, lr} + 8001996: b088 sub sp, #32 + 8001998: af00 add r7, sp, #0 + 800199a: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800199c: f107 030c add.w r3, r7, #12 + 80019a0: 2200 movs r2, #0 + 80019a2: 601a str r2, [r3, #0] + 80019a4: 605a str r2, [r3, #4] + 80019a6: 609a str r2, [r3, #8] + 80019a8: 60da str r2, [r3, #12] + 80019aa: 611a str r2, [r3, #16] + if(htim->Instance==TIM4) + 80019ac: 687b ldr r3, [r7, #4] + 80019ae: 681b ldr r3, [r3, #0] + 80019b0: 4a11 ldr r2, [pc, #68] ; (80019f8 ) + 80019b2: 4293 cmp r3, r2 + 80019b4: d11c bne.n 80019f0 + { + /* USER CODE BEGIN TIM4_MspPostInit 0 */ + + /* USER CODE END TIM4_MspPostInit 0 */ + + __HAL_RCC_GPIOD_CLK_ENABLE(); + 80019b6: 4b11 ldr r3, [pc, #68] ; (80019fc ) + 80019b8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80019ba: 4a10 ldr r2, [pc, #64] ; (80019fc ) + 80019bc: f043 0308 orr.w r3, r3, #8 + 80019c0: 6313 str r3, [r2, #48] ; 0x30 + 80019c2: 4b0e ldr r3, [pc, #56] ; (80019fc ) + 80019c4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80019c6: f003 0308 and.w r3, r3, #8 + 80019ca: 60bb str r3, [r7, #8] + 80019cc: 68bb ldr r3, [r7, #8] + /**TIM4 GPIO Configuration + PD14 ------> TIM4_CH3 + PD15 ------> TIM4_CH4 + */ + GPIO_InitStruct.Pin = pwm2_Pin|pwm1_Pin; + 80019ce: f44f 4340 mov.w r3, #49152 ; 0xc000 + 80019d2: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80019d4: 2302 movs r3, #2 + 80019d6: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80019d8: 2300 movs r3, #0 + 80019da: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80019dc: 2300 movs r3, #0 + 80019de: 61bb str r3, [r7, #24] + GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; + 80019e0: 2302 movs r3, #2 + 80019e2: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 80019e4: f107 030c add.w r3, r7, #12 + 80019e8: 4619 mov r1, r3 + 80019ea: 4805 ldr r0, [pc, #20] ; (8001a00 ) + 80019ec: f000 fa92 bl 8001f14 + /* USER CODE BEGIN TIM4_MspPostInit 1 */ + + /* USER CODE END TIM4_MspPostInit 1 */ + } + +} + 80019f0: bf00 nop + 80019f2: 3720 adds r7, #32 + 80019f4: 46bd mov sp, r7 + 80019f6: bd80 pop {r7, pc} + 80019f8: 40000800 .word 0x40000800 + 80019fc: 40023800 .word 0x40023800 + 8001a00: 40020c00 .word 0x40020c00 + +08001a04 : +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + 8001a04: b580 push {r7, lr} + 8001a06: b08a sub sp, #40 ; 0x28 + 8001a08: af00 add r7, sp, #0 + 8001a0a: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8001a0c: f107 0314 add.w r3, r7, #20 + 8001a10: 2200 movs r2, #0 + 8001a12: 601a str r2, [r3, #0] + 8001a14: 605a str r2, [r3, #4] + 8001a16: 609a str r2, [r3, #8] + 8001a18: 60da str r2, [r3, #12] + 8001a1a: 611a str r2, [r3, #16] + if(huart->Instance==USART6) + 8001a1c: 687b ldr r3, [r7, #4] + 8001a1e: 681b ldr r3, [r3, #0] + 8001a20: 4a17 ldr r2, [pc, #92] ; (8001a80 ) + 8001a22: 4293 cmp r3, r2 + 8001a24: d127 bne.n 8001a76 + { + /* USER CODE BEGIN USART6_MspInit 0 */ + + /* USER CODE END USART6_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART6_CLK_ENABLE(); + 8001a26: 4b17 ldr r3, [pc, #92] ; (8001a84 ) + 8001a28: 6c5b ldr r3, [r3, #68] ; 0x44 + 8001a2a: 4a16 ldr r2, [pc, #88] ; (8001a84 ) + 8001a2c: f043 0320 orr.w r3, r3, #32 + 8001a30: 6453 str r3, [r2, #68] ; 0x44 + 8001a32: 4b14 ldr r3, [pc, #80] ; (8001a84 ) + 8001a34: 6c5b ldr r3, [r3, #68] ; 0x44 + 8001a36: f003 0320 and.w r3, r3, #32 + 8001a3a: 613b str r3, [r7, #16] + 8001a3c: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8001a3e: 4b11 ldr r3, [pc, #68] ; (8001a84 ) + 8001a40: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001a42: 4a10 ldr r2, [pc, #64] ; (8001a84 ) + 8001a44: f043 0304 orr.w r3, r3, #4 + 8001a48: 6313 str r3, [r2, #48] ; 0x30 + 8001a4a: 4b0e ldr r3, [pc, #56] ; (8001a84 ) + 8001a4c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001a4e: f003 0304 and.w r3, r3, #4 + 8001a52: 60fb str r3, [r7, #12] + 8001a54: 68fb ldr r3, [r7, #12] + /**USART6 GPIO Configuration + PC6 ------> USART6_TX + PC7 ------> USART6_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + 8001a56: 23c0 movs r3, #192 ; 0xc0 + 8001a58: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001a5a: 2302 movs r3, #2 + 8001a5c: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001a5e: 2300 movs r3, #0 + 8001a60: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8001a62: 2303 movs r3, #3 + 8001a64: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF8_USART6; + 8001a66: 2308 movs r3, #8 + 8001a68: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 8001a6a: f107 0314 add.w r3, r7, #20 + 8001a6e: 4619 mov r1, r3 + 8001a70: 4805 ldr r0, [pc, #20] ; (8001a88 ) + 8001a72: f000 fa4f bl 8001f14 + /* USER CODE BEGIN USART6_MspInit 1 */ + + /* USER CODE END USART6_MspInit 1 */ + } + +} + 8001a76: bf00 nop + 8001a78: 3728 adds r7, #40 ; 0x28 + 8001a7a: 46bd mov sp, r7 + 8001a7c: bd80 pop {r7, pc} + 8001a7e: bf00 nop + 8001a80: 40011400 .word 0x40011400 + 8001a84: 40023800 .word 0x40023800 + 8001a88: 40020800 .word 0x40020800 + +08001a8c : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 8001a8c: b480 push {r7} + 8001a8e: af00 add r7, sp, #0 + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + 8001a90: bf00 nop + 8001a92: 46bd mov sp, r7 + 8001a94: f85d 7b04 ldr.w r7, [sp], #4 + 8001a98: 4770 bx lr + +08001a9a : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 8001a9a: b480 push {r7} + 8001a9c: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8001a9e: e7fe b.n 8001a9e + +08001aa0 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 8001aa0: b480 push {r7} + 8001aa2: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 8001aa4: e7fe b.n 8001aa4 + +08001aa6 : + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 8001aa6: b480 push {r7} + 8001aa8: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 8001aaa: e7fe b.n 8001aaa + +08001aac : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 8001aac: b480 push {r7} + 8001aae: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8001ab0: e7fe b.n 8001ab0 + +08001ab2 : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 8001ab2: b480 push {r7} + 8001ab4: af00 add r7, sp, #0 + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + 8001ab6: bf00 nop + 8001ab8: 46bd mov sp, r7 + 8001aba: f85d 7b04 ldr.w r7, [sp], #4 + 8001abe: 4770 bx lr + +08001ac0 : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 8001ac0: b480 push {r7} + 8001ac2: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 8001ac4: bf00 nop + 8001ac6: 46bd mov sp, r7 + 8001ac8: f85d 7b04 ldr.w r7, [sp], #4 + 8001acc: 4770 bx lr + +08001ace : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8001ace: b480 push {r7} + 8001ad0: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8001ad2: bf00 nop + 8001ad4: 46bd mov sp, r7 + 8001ad6: f85d 7b04 ldr.w r7, [sp], #4 + 8001ada: 4770 bx lr + +08001adc : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 8001adc: b580 push {r7, lr} + 8001ade: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 8001ae0: f000 f8c4 bl 8001c6c + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8001ae4: bf00 nop + 8001ae6: bd80 pop {r7, pc} + +08001ae8 : + +/** + * @brief This function handles TIM3 global interrupt. + */ +void TIM3_IRQHandler(void) +{ + 8001ae8: b580 push {r7, lr} + 8001aea: af00 add r7, sp, #0 + /* USER CODE BEGIN TIM3_IRQn 0 */ + + /* USER CODE END TIM3_IRQn 0 */ + HAL_TIM_IRQHandler(&htim3); + 8001aec: 4802 ldr r0, [pc, #8] ; (8001af8 ) + 8001aee: f001 fdec bl 80036ca + /* USER CODE BEGIN TIM3_IRQn 1 */ + + /* USER CODE END TIM3_IRQn 1 */ +} + 8001af2: bf00 nop + 8001af4: bd80 pop {r7, pc} + 8001af6: bf00 nop + 8001af8: 2000006c .word 0x2000006c + +08001afc : + +/** + * @brief This function handles EXTI line[15:10] interrupts. + */ +void EXTI15_10_IRQHandler(void) +{ + 8001afc: b580 push {r7, lr} + 8001afe: af00 add r7, sp, #0 + /* USER CODE BEGIN EXTI15_10_IRQn 0 */ + + /* USER CODE END EXTI15_10_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13); + 8001b00: f44f 5000 mov.w r0, #8192 ; 0x2000 + 8001b04: f000 fbca bl 800229c + /* USER CODE BEGIN EXTI15_10_IRQn 1 */ + + /* USER CODE END EXTI15_10_IRQn 1 */ +} + 8001b08: bf00 nop + 8001b0a: bd80 pop {r7, pc} + +08001b0c : + +/** + * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts. + */ +void TIM6_DAC_IRQHandler(void) +{ + 8001b0c: b580 push {r7, lr} + 8001b0e: af00 add r7, sp, #0 + /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ + + /* USER CODE END TIM6_DAC_IRQn 0 */ + HAL_TIM_IRQHandler(&htim6); + 8001b10: 4802 ldr r0, [pc, #8] ; (8001b1c ) + 8001b12: f001 fdda bl 80036ca + /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ + + /* USER CODE END TIM6_DAC_IRQn 1 */ +} + 8001b16: bf00 nop + 8001b18: bd80 pop {r7, pc} + 8001b1a: bf00 nop + 8001b1c: 2000012c .word 0x2000012c + +08001b20 : + +/** + * @brief This function handles USART6 global interrupt. + */ +void USART6_IRQHandler(void) +{ + 8001b20: b580 push {r7, lr} + 8001b22: af00 add r7, sp, #0 + /* USER CODE BEGIN USART6_IRQn 0 */ + + /* USER CODE END USART6_IRQn 0 */ + HAL_UART_IRQHandler(&huart6); + 8001b24: 4802 ldr r0, [pc, #8] ; (8001b30 ) + 8001b26: f002 fea3 bl 8004870 + /* USER CODE BEGIN USART6_IRQn 1 */ + + /* USER CODE END USART6_IRQn 1 */ +} + 8001b2a: bf00 nop + 8001b2c: bd80 pop {r7, pc} + 8001b2e: bf00 nop + 8001b30: 2000016c .word 0x2000016c + +08001b34 : + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + 8001b34: b480 push {r7} + 8001b36: af00 add r7, sp, #0 + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + 8001b38: 4b15 ldr r3, [pc, #84] ; (8001b90 ) + 8001b3a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8001b3e: 4a14 ldr r2, [pc, #80] ; (8001b90 ) + 8001b40: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 + 8001b44: f8c2 3088 str.w r3, [r2, #136] ; 0x88 + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + 8001b48: 4b12 ldr r3, [pc, #72] ; (8001b94 ) + 8001b4a: 681b ldr r3, [r3, #0] + 8001b4c: 4a11 ldr r2, [pc, #68] ; (8001b94 ) + 8001b4e: f043 0301 orr.w r3, r3, #1 + 8001b52: 6013 str r3, [r2, #0] + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + 8001b54: 4b0f ldr r3, [pc, #60] ; (8001b94 ) + 8001b56: 2200 movs r2, #0 + 8001b58: 609a str r2, [r3, #8] + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + 8001b5a: 4b0e ldr r3, [pc, #56] ; (8001b94 ) + 8001b5c: 681a ldr r2, [r3, #0] + 8001b5e: 490d ldr r1, [pc, #52] ; (8001b94 ) + 8001b60: 4b0d ldr r3, [pc, #52] ; (8001b98 ) + 8001b62: 4013 ands r3, r2 + 8001b64: 600b str r3, [r1, #0] + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + 8001b66: 4b0b ldr r3, [pc, #44] ; (8001b94 ) + 8001b68: 4a0c ldr r2, [pc, #48] ; (8001b9c ) + 8001b6a: 605a str r2, [r3, #4] + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + 8001b6c: 4b09 ldr r3, [pc, #36] ; (8001b94 ) + 8001b6e: 681b ldr r3, [r3, #0] + 8001b70: 4a08 ldr r2, [pc, #32] ; (8001b94 ) + 8001b72: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8001b76: 6013 str r3, [r2, #0] + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + 8001b78: 4b06 ldr r3, [pc, #24] ; (8001b94 ) + 8001b7a: 2200 movs r2, #0 + 8001b7c: 60da str r2, [r3, #12] + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + 8001b7e: 4b04 ldr r3, [pc, #16] ; (8001b90 ) + 8001b80: f04f 6200 mov.w r2, #134217728 ; 0x8000000 + 8001b84: 609a str r2, [r3, #8] +#endif +} + 8001b86: bf00 nop + 8001b88: 46bd mov sp, r7 + 8001b8a: f85d 7b04 ldr.w r7, [sp], #4 + 8001b8e: 4770 bx lr + 8001b90: e000ed00 .word 0xe000ed00 + 8001b94: 40023800 .word 0x40023800 + 8001b98: fef6ffff .word 0xfef6ffff + 8001b9c: 24003010 .word 0x24003010 + +08001ba0 : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + 8001ba0: f8df d034 ldr.w sp, [pc, #52] ; 8001bd8 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + 8001ba4: 2100 movs r1, #0 + b LoopCopyDataInit + 8001ba6: e003 b.n 8001bb0 + +08001ba8 : + +CopyDataInit: + ldr r3, =_sidata + 8001ba8: 4b0c ldr r3, [pc, #48] ; (8001bdc ) + ldr r3, [r3, r1] + 8001baa: 585b ldr r3, [r3, r1] + str r3, [r0, r1] + 8001bac: 5043 str r3, [r0, r1] + adds r1, r1, #4 + 8001bae: 3104 adds r1, #4 + +08001bb0 : + +LoopCopyDataInit: + ldr r0, =_sdata + 8001bb0: 480b ldr r0, [pc, #44] ; (8001be0 ) + ldr r3, =_edata + 8001bb2: 4b0c ldr r3, [pc, #48] ; (8001be4 ) + adds r2, r0, r1 + 8001bb4: 1842 adds r2, r0, r1 + cmp r2, r3 + 8001bb6: 429a cmp r2, r3 + bcc CopyDataInit + 8001bb8: d3f6 bcc.n 8001ba8 + ldr r2, =_sbss + 8001bba: 4a0b ldr r2, [pc, #44] ; (8001be8 ) + b LoopFillZerobss + 8001bbc: e002 b.n 8001bc4 + +08001bbe : +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + 8001bbe: 2300 movs r3, #0 + str r3, [r2], #4 + 8001bc0: f842 3b04 str.w r3, [r2], #4 + +08001bc4 : + +LoopFillZerobss: + ldr r3, = _ebss + 8001bc4: 4b09 ldr r3, [pc, #36] ; (8001bec ) + cmp r2, r3 + 8001bc6: 429a cmp r2, r3 + bcc FillZerobss + 8001bc8: d3f9 bcc.n 8001bbe + +/* Call the clock system initialization function.*/ + bl SystemInit + 8001bca: f7ff ffb3 bl 8001b34 +/* Call static constructors */ + bl __libc_init_array + 8001bce: f003 fc31 bl 8005434 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 8001bd2: f7ff f817 bl 8000c04
+ bx lr + 8001bd6: 4770 bx lr + ldr sp, =_estack /* set stack pointer */ + 8001bd8: 20080000 .word 0x20080000 + ldr r3, =_sidata + 8001bdc: 080054d0 .word 0x080054d0 + ldr r0, =_sdata + 8001be0: 20000000 .word 0x20000000 + ldr r3, =_edata + 8001be4: 20000010 .word 0x20000010 + ldr r2, =_sbss + 8001be8: 20000010 .word 0x20000010 + ldr r3, = _ebss + 8001bec: 20000304 .word 0x20000304 + +08001bf0 : + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8001bf0: e7fe b.n 8001bf0 + +08001bf2 : + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8001bf2: b580 push {r7, lr} + 8001bf4: af00 add r7, sp, #0 +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8001bf6: 2003 movs r0, #3 + 8001bf8: f000 f928 bl 8001e4c + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + 8001bfc: 2000 movs r0, #0 + 8001bfe: f000 f805 bl 8001c0c + + /* Init the low level hardware */ + HAL_MspInit(); + 8001c02: f7ff fdcb bl 800179c + + /* Return function status */ + return HAL_OK; + 8001c06: 2300 movs r3, #0 +} + 8001c08: 4618 mov r0, r3 + 8001c0a: bd80 pop {r7, pc} + +08001c0c : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8001c0c: b580 push {r7, lr} + 8001c0e: b082 sub sp, #8 + 8001c10: af00 add r7, sp, #0 + 8001c12: 6078 str r0, [r7, #4] + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + 8001c14: 4b12 ldr r3, [pc, #72] ; (8001c60 ) + 8001c16: 681a ldr r2, [r3, #0] + 8001c18: 4b12 ldr r3, [pc, #72] ; (8001c64 ) + 8001c1a: 781b ldrb r3, [r3, #0] + 8001c1c: 4619 mov r1, r3 + 8001c1e: f44f 737a mov.w r3, #1000 ; 0x3e8 + 8001c22: fbb3 f3f1 udiv r3, r3, r1 + 8001c26: fbb2 f3f3 udiv r3, r2, r3 + 8001c2a: 4618 mov r0, r3 + 8001c2c: f000 f943 bl 8001eb6 + 8001c30: 4603 mov r3, r0 + 8001c32: 2b00 cmp r3, #0 + 8001c34: d001 beq.n 8001c3a + { + return HAL_ERROR; + 8001c36: 2301 movs r3, #1 + 8001c38: e00e b.n 8001c58 + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8001c3a: 687b ldr r3, [r7, #4] + 8001c3c: 2b0f cmp r3, #15 + 8001c3e: d80a bhi.n 8001c56 + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8001c40: 2200 movs r2, #0 + 8001c42: 6879 ldr r1, [r7, #4] + 8001c44: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8001c48: f000 f90b bl 8001e62 + uwTickPrio = TickPriority; + 8001c4c: 4a06 ldr r2, [pc, #24] ; (8001c68 ) + 8001c4e: 687b ldr r3, [r7, #4] + 8001c50: 6013 str r3, [r2, #0] + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; + 8001c52: 2300 movs r3, #0 + 8001c54: e000 b.n 8001c58 + return HAL_ERROR; + 8001c56: 2301 movs r3, #1 +} + 8001c58: 4618 mov r0, r3 + 8001c5a: 3708 adds r7, #8 + 8001c5c: 46bd mov sp, r7 + 8001c5e: bd80 pop {r7, pc} + 8001c60: 20000004 .word 0x20000004 + 8001c64: 2000000c .word 0x2000000c + 8001c68: 20000008 .word 0x20000008 + +08001c6c : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 8001c6c: b480 push {r7} + 8001c6e: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 8001c70: 4b06 ldr r3, [pc, #24] ; (8001c8c ) + 8001c72: 781b ldrb r3, [r3, #0] + 8001c74: 461a mov r2, r3 + 8001c76: 4b06 ldr r3, [pc, #24] ; (8001c90 ) + 8001c78: 681b ldr r3, [r3, #0] + 8001c7a: 4413 add r3, r2 + 8001c7c: 4a04 ldr r2, [pc, #16] ; (8001c90 ) + 8001c7e: 6013 str r3, [r2, #0] +} + 8001c80: bf00 nop + 8001c82: 46bd mov sp, r7 + 8001c84: f85d 7b04 ldr.w r7, [sp], #4 + 8001c88: 4770 bx lr + 8001c8a: bf00 nop + 8001c8c: 2000000c .word 0x2000000c + 8001c90: 20000300 .word 0x20000300 + +08001c94 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 8001c94: b480 push {r7} + 8001c96: af00 add r7, sp, #0 + return uwTick; + 8001c98: 4b03 ldr r3, [pc, #12] ; (8001ca8 ) + 8001c9a: 681b ldr r3, [r3, #0] +} + 8001c9c: 4618 mov r0, r3 + 8001c9e: 46bd mov sp, r7 + 8001ca0: f85d 7b04 ldr.w r7, [sp], #4 + 8001ca4: 4770 bx lr + 8001ca6: bf00 nop + 8001ca8: 20000300 .word 0x20000300 + +08001cac <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8001cac: b480 push {r7} + 8001cae: b085 sub sp, #20 + 8001cb0: af00 add r7, sp, #0 + 8001cb2: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8001cb4: 687b ldr r3, [r7, #4] + 8001cb6: f003 0307 and.w r3, r3, #7 + 8001cba: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 8001cbc: 4b0b ldr r3, [pc, #44] ; (8001cec <__NVIC_SetPriorityGrouping+0x40>) + 8001cbe: 68db ldr r3, [r3, #12] + 8001cc0: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8001cc2: 68ba ldr r2, [r7, #8] + 8001cc4: f64f 03ff movw r3, #63743 ; 0xf8ff + 8001cc8: 4013 ands r3, r2 + 8001cca: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 8001ccc: 68fb ldr r3, [r7, #12] + 8001cce: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8001cd0: 68bb ldr r3, [r7, #8] + 8001cd2: 431a orrs r2, r3 + reg_value = (reg_value | + 8001cd4: 4b06 ldr r3, [pc, #24] ; (8001cf0 <__NVIC_SetPriorityGrouping+0x44>) + 8001cd6: 4313 orrs r3, r2 + 8001cd8: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 8001cda: 4a04 ldr r2, [pc, #16] ; (8001cec <__NVIC_SetPriorityGrouping+0x40>) + 8001cdc: 68bb ldr r3, [r7, #8] + 8001cde: 60d3 str r3, [r2, #12] +} + 8001ce0: bf00 nop + 8001ce2: 3714 adds r7, #20 + 8001ce4: 46bd mov sp, r7 + 8001ce6: f85d 7b04 ldr.w r7, [sp], #4 + 8001cea: 4770 bx lr + 8001cec: e000ed00 .word 0xe000ed00 + 8001cf0: 05fa0000 .word 0x05fa0000 + +08001cf4 <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 8001cf4: b480 push {r7} + 8001cf6: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8001cf8: 4b04 ldr r3, [pc, #16] ; (8001d0c <__NVIC_GetPriorityGrouping+0x18>) + 8001cfa: 68db ldr r3, [r3, #12] + 8001cfc: 0a1b lsrs r3, r3, #8 + 8001cfe: f003 0307 and.w r3, r3, #7 +} + 8001d02: 4618 mov r0, r3 + 8001d04: 46bd mov sp, r7 + 8001d06: f85d 7b04 ldr.w r7, [sp], #4 + 8001d0a: 4770 bx lr + 8001d0c: e000ed00 .word 0xe000ed00 + +08001d10 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8001d10: b480 push {r7} + 8001d12: b083 sub sp, #12 + 8001d14: af00 add r7, sp, #0 + 8001d16: 4603 mov r3, r0 + 8001d18: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8001d1a: f997 3007 ldrsb.w r3, [r7, #7] + 8001d1e: 2b00 cmp r3, #0 + 8001d20: db0b blt.n 8001d3a <__NVIC_EnableIRQ+0x2a> + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8001d22: 79fb ldrb r3, [r7, #7] + 8001d24: f003 021f and.w r2, r3, #31 + 8001d28: 4907 ldr r1, [pc, #28] ; (8001d48 <__NVIC_EnableIRQ+0x38>) + 8001d2a: f997 3007 ldrsb.w r3, [r7, #7] + 8001d2e: 095b lsrs r3, r3, #5 + 8001d30: 2001 movs r0, #1 + 8001d32: fa00 f202 lsl.w r2, r0, r2 + 8001d36: f841 2023 str.w r2, [r1, r3, lsl #2] + } +} + 8001d3a: bf00 nop + 8001d3c: 370c adds r7, #12 + 8001d3e: 46bd mov sp, r7 + 8001d40: f85d 7b04 ldr.w r7, [sp], #4 + 8001d44: 4770 bx lr + 8001d46: bf00 nop + 8001d48: e000e100 .word 0xe000e100 + +08001d4c <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8001d4c: b480 push {r7} + 8001d4e: b083 sub sp, #12 + 8001d50: af00 add r7, sp, #0 + 8001d52: 4603 mov r3, r0 + 8001d54: 6039 str r1, [r7, #0] + 8001d56: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8001d58: f997 3007 ldrsb.w r3, [r7, #7] + 8001d5c: 2b00 cmp r3, #0 + 8001d5e: db0a blt.n 8001d76 <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8001d60: 683b ldr r3, [r7, #0] + 8001d62: b2da uxtb r2, r3 + 8001d64: 490c ldr r1, [pc, #48] ; (8001d98 <__NVIC_SetPriority+0x4c>) + 8001d66: f997 3007 ldrsb.w r3, [r7, #7] + 8001d6a: 0112 lsls r2, r2, #4 + 8001d6c: b2d2 uxtb r2, r2 + 8001d6e: 440b add r3, r1 + 8001d70: f883 2300 strb.w r2, [r3, #768] ; 0x300 + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 8001d74: e00a b.n 8001d8c <__NVIC_SetPriority+0x40> + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8001d76: 683b ldr r3, [r7, #0] + 8001d78: b2da uxtb r2, r3 + 8001d7a: 4908 ldr r1, [pc, #32] ; (8001d9c <__NVIC_SetPriority+0x50>) + 8001d7c: 79fb ldrb r3, [r7, #7] + 8001d7e: f003 030f and.w r3, r3, #15 + 8001d82: 3b04 subs r3, #4 + 8001d84: 0112 lsls r2, r2, #4 + 8001d86: b2d2 uxtb r2, r2 + 8001d88: 440b add r3, r1 + 8001d8a: 761a strb r2, [r3, #24] +} + 8001d8c: bf00 nop + 8001d8e: 370c adds r7, #12 + 8001d90: 46bd mov sp, r7 + 8001d92: f85d 7b04 ldr.w r7, [sp], #4 + 8001d96: 4770 bx lr + 8001d98: e000e100 .word 0xe000e100 + 8001d9c: e000ed00 .word 0xe000ed00 + +08001da0 : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8001da0: b480 push {r7} + 8001da2: b089 sub sp, #36 ; 0x24 + 8001da4: af00 add r7, sp, #0 + 8001da6: 60f8 str r0, [r7, #12] + 8001da8: 60b9 str r1, [r7, #8] + 8001daa: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8001dac: 68fb ldr r3, [r7, #12] + 8001dae: f003 0307 and.w r3, r3, #7 + 8001db2: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8001db4: 69fb ldr r3, [r7, #28] + 8001db6: f1c3 0307 rsb r3, r3, #7 + 8001dba: 2b04 cmp r3, #4 + 8001dbc: bf28 it cs + 8001dbe: 2304 movcs r3, #4 + 8001dc0: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8001dc2: 69fb ldr r3, [r7, #28] + 8001dc4: 3304 adds r3, #4 + 8001dc6: 2b06 cmp r3, #6 + 8001dc8: d902 bls.n 8001dd0 + 8001dca: 69fb ldr r3, [r7, #28] + 8001dcc: 3b03 subs r3, #3 + 8001dce: e000 b.n 8001dd2 + 8001dd0: 2300 movs r3, #0 + 8001dd2: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8001dd4: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 8001dd8: 69bb ldr r3, [r7, #24] + 8001dda: fa02 f303 lsl.w r3, r2, r3 + 8001dde: 43da mvns r2, r3 + 8001de0: 68bb ldr r3, [r7, #8] + 8001de2: 401a ands r2, r3 + 8001de4: 697b ldr r3, [r7, #20] + 8001de6: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8001de8: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff + 8001dec: 697b ldr r3, [r7, #20] + 8001dee: fa01 f303 lsl.w r3, r1, r3 + 8001df2: 43d9 mvns r1, r3 + 8001df4: 687b ldr r3, [r7, #4] + 8001df6: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8001df8: 4313 orrs r3, r2 + ); +} + 8001dfa: 4618 mov r0, r3 + 8001dfc: 3724 adds r7, #36 ; 0x24 + 8001dfe: 46bd mov sp, r7 + 8001e00: f85d 7b04 ldr.w r7, [sp], #4 + 8001e04: 4770 bx lr + ... + +08001e08 : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8001e08: b580 push {r7, lr} + 8001e0a: b082 sub sp, #8 + 8001e0c: af00 add r7, sp, #0 + 8001e0e: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8001e10: 687b ldr r3, [r7, #4] + 8001e12: 3b01 subs r3, #1 + 8001e14: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 + 8001e18: d301 bcc.n 8001e1e + { + return (1UL); /* Reload value impossible */ + 8001e1a: 2301 movs r3, #1 + 8001e1c: e00f b.n 8001e3e + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8001e1e: 4a0a ldr r2, [pc, #40] ; (8001e48 ) + 8001e20: 687b ldr r3, [r7, #4] + 8001e22: 3b01 subs r3, #1 + 8001e24: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 8001e26: 210f movs r1, #15 + 8001e28: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8001e2c: f7ff ff8e bl 8001d4c <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8001e30: 4b05 ldr r3, [pc, #20] ; (8001e48 ) + 8001e32: 2200 movs r2, #0 + 8001e34: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8001e36: 4b04 ldr r3, [pc, #16] ; (8001e48 ) + 8001e38: 2207 movs r2, #7 + 8001e3a: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8001e3c: 2300 movs r3, #0 +} + 8001e3e: 4618 mov r0, r3 + 8001e40: 3708 adds r7, #8 + 8001e42: 46bd mov sp, r7 + 8001e44: bd80 pop {r7, pc} + 8001e46: bf00 nop + 8001e48: e000e010 .word 0xe000e010 + +08001e4c : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8001e4c: b580 push {r7, lr} + 8001e4e: b082 sub sp, #8 + 8001e50: af00 add r7, sp, #0 + 8001e52: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8001e54: 6878 ldr r0, [r7, #4] + 8001e56: f7ff ff29 bl 8001cac <__NVIC_SetPriorityGrouping> +} + 8001e5a: bf00 nop + 8001e5c: 3708 adds r7, #8 + 8001e5e: 46bd mov sp, r7 + 8001e60: bd80 pop {r7, pc} + +08001e62 : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8001e62: b580 push {r7, lr} + 8001e64: b086 sub sp, #24 + 8001e66: af00 add r7, sp, #0 + 8001e68: 4603 mov r3, r0 + 8001e6a: 60b9 str r1, [r7, #8] + 8001e6c: 607a str r2, [r7, #4] + 8001e6e: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00; + 8001e70: 2300 movs r3, #0 + 8001e72: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8001e74: f7ff ff3e bl 8001cf4 <__NVIC_GetPriorityGrouping> + 8001e78: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8001e7a: 687a ldr r2, [r7, #4] + 8001e7c: 68b9 ldr r1, [r7, #8] + 8001e7e: 6978 ldr r0, [r7, #20] + 8001e80: f7ff ff8e bl 8001da0 + 8001e84: 4602 mov r2, r0 + 8001e86: f997 300f ldrsb.w r3, [r7, #15] + 8001e8a: 4611 mov r1, r2 + 8001e8c: 4618 mov r0, r3 + 8001e8e: f7ff ff5d bl 8001d4c <__NVIC_SetPriority> +} + 8001e92: bf00 nop + 8001e94: 3718 adds r7, #24 + 8001e96: 46bd mov sp, r7 + 8001e98: bd80 pop {r7, pc} + +08001e9a : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8001e9a: b580 push {r7, lr} + 8001e9c: b082 sub sp, #8 + 8001e9e: af00 add r7, sp, #0 + 8001ea0: 4603 mov r3, r0 + 8001ea2: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 8001ea4: f997 3007 ldrsb.w r3, [r7, #7] + 8001ea8: 4618 mov r0, r3 + 8001eaa: f7ff ff31 bl 8001d10 <__NVIC_EnableIRQ> +} + 8001eae: bf00 nop + 8001eb0: 3708 adds r7, #8 + 8001eb2: 46bd mov sp, r7 + 8001eb4: bd80 pop {r7, pc} + +08001eb6 : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 8001eb6: b580 push {r7, lr} + 8001eb8: b082 sub sp, #8 + 8001eba: af00 add r7, sp, #0 + 8001ebc: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 8001ebe: 6878 ldr r0, [r7, #4] + 8001ec0: f7ff ffa2 bl 8001e08 + 8001ec4: 4603 mov r3, r0 +} + 8001ec6: 4618 mov r0, r3 + 8001ec8: 3708 adds r7, #8 + 8001eca: 46bd mov sp, r7 + 8001ecc: bd80 pop {r7, pc} + +08001ece : + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + 8001ece: b480 push {r7} + 8001ed0: b083 sub sp, #12 + 8001ed2: af00 add r7, sp, #0 + 8001ed4: 6078 str r0, [r7, #4] + if(hdma->State != HAL_DMA_STATE_BUSY) + 8001ed6: 687b ldr r3, [r7, #4] + 8001ed8: f893 3035 ldrb.w r3, [r3, #53] ; 0x35 + 8001edc: b2db uxtb r3, r3 + 8001ede: 2b02 cmp r3, #2 + 8001ee0: d004 beq.n 8001eec + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 8001ee2: 687b ldr r3, [r7, #4] + 8001ee4: 2280 movs r2, #128 ; 0x80 + 8001ee6: 655a str r2, [r3, #84] ; 0x54 + return HAL_ERROR; + 8001ee8: 2301 movs r3, #1 + 8001eea: e00c b.n 8001f06 + } + else + { + /* Set Abort State */ + hdma->State = HAL_DMA_STATE_ABORT; + 8001eec: 687b ldr r3, [r7, #4] + 8001eee: 2205 movs r2, #5 + 8001ef0: f883 2035 strb.w r2, [r3, #53] ; 0x35 + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + 8001ef4: 687b ldr r3, [r7, #4] + 8001ef6: 681b ldr r3, [r3, #0] + 8001ef8: 681a ldr r2, [r3, #0] + 8001efa: 687b ldr r3, [r7, #4] + 8001efc: 681b ldr r3, [r3, #0] + 8001efe: f022 0201 bic.w r2, r2, #1 + 8001f02: 601a str r2, [r3, #0] + } + + return HAL_OK; + 8001f04: 2300 movs r3, #0 +} + 8001f06: 4618 mov r0, r3 + 8001f08: 370c adds r7, #12 + 8001f0a: 46bd mov sp, r7 + 8001f0c: f85d 7b04 ldr.w r7, [sp], #4 + 8001f10: 4770 bx lr + ... + +08001f14 : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8001f14: b480 push {r7} + 8001f16: b089 sub sp, #36 ; 0x24 + 8001f18: af00 add r7, sp, #0 + 8001f1a: 6078 str r0, [r7, #4] + 8001f1c: 6039 str r1, [r7, #0] + uint32_t position = 0x00; + 8001f1e: 2300 movs r3, #0 + 8001f20: 61fb str r3, [r7, #28] + uint32_t ioposition = 0x00; + 8001f22: 2300 movs r3, #0 + 8001f24: 617b str r3, [r7, #20] + uint32_t iocurrent = 0x00; + 8001f26: 2300 movs r3, #0 + 8001f28: 613b str r3, [r7, #16] + uint32_t temp = 0x00; + 8001f2a: 2300 movs r3, #0 + 8001f2c: 61bb str r3, [r7, #24] + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + for(position = 0; position < GPIO_NUMBER; position++) + 8001f2e: 2300 movs r3, #0 + 8001f30: 61fb str r3, [r7, #28] + 8001f32: e175 b.n 8002220 + { + /* Get the IO position */ + ioposition = ((uint32_t)0x01) << position; + 8001f34: 2201 movs r2, #1 + 8001f36: 69fb ldr r3, [r7, #28] + 8001f38: fa02 f303 lsl.w r3, r2, r3 + 8001f3c: 617b str r3, [r7, #20] + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + 8001f3e: 683b ldr r3, [r7, #0] + 8001f40: 681b ldr r3, [r3, #0] + 8001f42: 697a ldr r2, [r7, #20] + 8001f44: 4013 ands r3, r2 + 8001f46: 613b str r3, [r7, #16] + + if(iocurrent == ioposition) + 8001f48: 693a ldr r2, [r7, #16] + 8001f4a: 697b ldr r3, [r7, #20] + 8001f4c: 429a cmp r2, r3 + 8001f4e: f040 8164 bne.w 800221a + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 8001f52: 683b ldr r3, [r7, #0] + 8001f54: 685b ldr r3, [r3, #4] + 8001f56: 2b02 cmp r3, #2 + 8001f58: d003 beq.n 8001f62 + 8001f5a: 683b ldr r3, [r7, #0] + 8001f5c: 685b ldr r3, [r3, #4] + 8001f5e: 2b12 cmp r3, #18 + 8001f60: d123 bne.n 8001faa + { + /* Check the Alternate function parameter */ + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3]; + 8001f62: 69fb ldr r3, [r7, #28] + 8001f64: 08da lsrs r2, r3, #3 + 8001f66: 687b ldr r3, [r7, #4] + 8001f68: 3208 adds r2, #8 + 8001f6a: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8001f6e: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + 8001f70: 69fb ldr r3, [r7, #28] + 8001f72: f003 0307 and.w r3, r3, #7 + 8001f76: 009b lsls r3, r3, #2 + 8001f78: 220f movs r2, #15 + 8001f7a: fa02 f303 lsl.w r3, r2, r3 + 8001f7e: 43db mvns r3, r3 + 8001f80: 69ba ldr r2, [r7, #24] + 8001f82: 4013 ands r3, r2 + 8001f84: 61bb str r3, [r7, #24] + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); + 8001f86: 683b ldr r3, [r7, #0] + 8001f88: 691a ldr r2, [r3, #16] + 8001f8a: 69fb ldr r3, [r7, #28] + 8001f8c: f003 0307 and.w r3, r3, #7 + 8001f90: 009b lsls r3, r3, #2 + 8001f92: fa02 f303 lsl.w r3, r2, r3 + 8001f96: 69ba ldr r2, [r7, #24] + 8001f98: 4313 orrs r3, r2 + 8001f9a: 61bb str r3, [r7, #24] + GPIOx->AFR[position >> 3] = temp; + 8001f9c: 69fb ldr r3, [r7, #28] + 8001f9e: 08da lsrs r2, r3, #3 + 8001fa0: 687b ldr r3, [r7, #4] + 8001fa2: 3208 adds r2, #8 + 8001fa4: 69b9 ldr r1, [r7, #24] + 8001fa6: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 8001faa: 687b ldr r3, [r7, #4] + 8001fac: 681b ldr r3, [r3, #0] + 8001fae: 61bb str r3, [r7, #24] + temp &= ~(GPIO_MODER_MODER0 << (position * 2)); + 8001fb0: 69fb ldr r3, [r7, #28] + 8001fb2: 005b lsls r3, r3, #1 + 8001fb4: 2203 movs r2, #3 + 8001fb6: fa02 f303 lsl.w r3, r2, r3 + 8001fba: 43db mvns r3, r3 + 8001fbc: 69ba ldr r2, [r7, #24] + 8001fbe: 4013 ands r3, r2 + 8001fc0: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 8001fc2: 683b ldr r3, [r7, #0] + 8001fc4: 685b ldr r3, [r3, #4] + 8001fc6: f003 0203 and.w r2, r3, #3 + 8001fca: 69fb ldr r3, [r7, #28] + 8001fcc: 005b lsls r3, r3, #1 + 8001fce: fa02 f303 lsl.w r3, r2, r3 + 8001fd2: 69ba ldr r2, [r7, #24] + 8001fd4: 4313 orrs r3, r2 + 8001fd6: 61bb str r3, [r7, #24] + GPIOx->MODER = temp; + 8001fd8: 687b ldr r3, [r7, #4] + 8001fda: 69ba ldr r2, [r7, #24] + 8001fdc: 601a str r2, [r3, #0] + + /* In case of Output or Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 8001fde: 683b ldr r3, [r7, #0] + 8001fe0: 685b ldr r3, [r3, #4] + 8001fe2: 2b01 cmp r3, #1 + 8001fe4: d00b beq.n 8001ffe + 8001fe6: 683b ldr r3, [r7, #0] + 8001fe8: 685b ldr r3, [r3, #4] + 8001fea: 2b02 cmp r3, #2 + 8001fec: d007 beq.n 8001ffe + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 8001fee: 683b ldr r3, [r7, #0] + 8001ff0: 685b ldr r3, [r3, #4] + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 8001ff2: 2b11 cmp r3, #17 + 8001ff4: d003 beq.n 8001ffe + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 8001ff6: 683b ldr r3, [r7, #0] + 8001ff8: 685b ldr r3, [r3, #4] + 8001ffa: 2b12 cmp r3, #18 + 8001ffc: d130 bne.n 8002060 + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8001ffe: 687b ldr r3, [r7, #4] + 8002000: 689b ldr r3, [r3, #8] + 8002002: 61bb str r3, [r7, #24] + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + 8002004: 69fb ldr r3, [r7, #28] + 8002006: 005b lsls r3, r3, #1 + 8002008: 2203 movs r2, #3 + 800200a: fa02 f303 lsl.w r3, r2, r3 + 800200e: 43db mvns r3, r3 + 8002010: 69ba ldr r2, [r7, #24] + 8002012: 4013 ands r3, r2 + 8002014: 61bb str r3, [r7, #24] + temp |= (GPIO_Init->Speed << (position * 2)); + 8002016: 683b ldr r3, [r7, #0] + 8002018: 68da ldr r2, [r3, #12] + 800201a: 69fb ldr r3, [r7, #28] + 800201c: 005b lsls r3, r3, #1 + 800201e: fa02 f303 lsl.w r3, r2, r3 + 8002022: 69ba ldr r2, [r7, #24] + 8002024: 4313 orrs r3, r2 + 8002026: 61bb str r3, [r7, #24] + GPIOx->OSPEEDR = temp; + 8002028: 687b ldr r3, [r7, #4] + 800202a: 69ba ldr r2, [r7, #24] + 800202c: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 800202e: 687b ldr r3, [r7, #4] + 8002030: 685b ldr r3, [r3, #4] + 8002032: 61bb str r3, [r7, #24] + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + 8002034: 2201 movs r2, #1 + 8002036: 69fb ldr r3, [r7, #28] + 8002038: fa02 f303 lsl.w r3, r2, r3 + 800203c: 43db mvns r3, r3 + 800203e: 69ba ldr r2, [r7, #24] + 8002040: 4013 ands r3, r2 + 8002042: 61bb str r3, [r7, #24] + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); + 8002044: 683b ldr r3, [r7, #0] + 8002046: 685b ldr r3, [r3, #4] + 8002048: 091b lsrs r3, r3, #4 + 800204a: f003 0201 and.w r2, r3, #1 + 800204e: 69fb ldr r3, [r7, #28] + 8002050: fa02 f303 lsl.w r3, r2, r3 + 8002054: 69ba ldr r2, [r7, #24] + 8002056: 4313 orrs r3, r2 + 8002058: 61bb str r3, [r7, #24] + GPIOx->OTYPER = temp; + 800205a: 687b ldr r3, [r7, #4] + 800205c: 69ba ldr r2, [r7, #24] + 800205e: 605a str r2, [r3, #4] + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 8002060: 687b ldr r3, [r7, #4] + 8002062: 68db ldr r3, [r3, #12] + 8002064: 61bb str r3, [r7, #24] + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + 8002066: 69fb ldr r3, [r7, #28] + 8002068: 005b lsls r3, r3, #1 + 800206a: 2203 movs r2, #3 + 800206c: fa02 f303 lsl.w r3, r2, r3 + 8002070: 43db mvns r3, r3 + 8002072: 69ba ldr r2, [r7, #24] + 8002074: 4013 ands r3, r2 + 8002076: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Pull) << (position * 2)); + 8002078: 683b ldr r3, [r7, #0] + 800207a: 689a ldr r2, [r3, #8] + 800207c: 69fb ldr r3, [r7, #28] + 800207e: 005b lsls r3, r3, #1 + 8002080: fa02 f303 lsl.w r3, r2, r3 + 8002084: 69ba ldr r2, [r7, #24] + 8002086: 4313 orrs r3, r2 + 8002088: 61bb str r3, [r7, #24] + GPIOx->PUPDR = temp; + 800208a: 687b ldr r3, [r7, #4] + 800208c: 69ba ldr r2, [r7, #24] + 800208e: 60da str r2, [r3, #12] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + 8002090: 683b ldr r3, [r7, #0] + 8002092: 685b ldr r3, [r3, #4] + 8002094: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8002098: 2b00 cmp r3, #0 + 800209a: f000 80be beq.w 800221a + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 800209e: 4b65 ldr r3, [pc, #404] ; (8002234 ) + 80020a0: 6c5b ldr r3, [r3, #68] ; 0x44 + 80020a2: 4a64 ldr r2, [pc, #400] ; (8002234 ) + 80020a4: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 80020a8: 6453 str r3, [r2, #68] ; 0x44 + 80020aa: 4b62 ldr r3, [pc, #392] ; (8002234 ) + 80020ac: 6c5b ldr r3, [r3, #68] ; 0x44 + 80020ae: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 80020b2: 60fb str r3, [r7, #12] + 80020b4: 68fb ldr r3, [r7, #12] + + temp = SYSCFG->EXTICR[position >> 2]; + 80020b6: 4a60 ldr r2, [pc, #384] ; (8002238 ) + 80020b8: 69fb ldr r3, [r7, #28] + 80020ba: 089b lsrs r3, r3, #2 + 80020bc: 3302 adds r3, #2 + 80020be: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80020c2: 61bb str r3, [r7, #24] + temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); + 80020c4: 69fb ldr r3, [r7, #28] + 80020c6: f003 0303 and.w r3, r3, #3 + 80020ca: 009b lsls r3, r3, #2 + 80020cc: 220f movs r2, #15 + 80020ce: fa02 f303 lsl.w r3, r2, r3 + 80020d2: 43db mvns r3, r3 + 80020d4: 69ba ldr r2, [r7, #24] + 80020d6: 4013 ands r3, r2 + 80020d8: 61bb str r3, [r7, #24] + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 80020da: 687b ldr r3, [r7, #4] + 80020dc: 4a57 ldr r2, [pc, #348] ; (800223c ) + 80020de: 4293 cmp r3, r2 + 80020e0: d037 beq.n 8002152 + 80020e2: 687b ldr r3, [r7, #4] + 80020e4: 4a56 ldr r2, [pc, #344] ; (8002240 ) + 80020e6: 4293 cmp r3, r2 + 80020e8: d031 beq.n 800214e + 80020ea: 687b ldr r3, [r7, #4] + 80020ec: 4a55 ldr r2, [pc, #340] ; (8002244 ) + 80020ee: 4293 cmp r3, r2 + 80020f0: d02b beq.n 800214a + 80020f2: 687b ldr r3, [r7, #4] + 80020f4: 4a54 ldr r2, [pc, #336] ; (8002248 ) + 80020f6: 4293 cmp r3, r2 + 80020f8: d025 beq.n 8002146 + 80020fa: 687b ldr r3, [r7, #4] + 80020fc: 4a53 ldr r2, [pc, #332] ; (800224c ) + 80020fe: 4293 cmp r3, r2 + 8002100: d01f beq.n 8002142 + 8002102: 687b ldr r3, [r7, #4] + 8002104: 4a52 ldr r2, [pc, #328] ; (8002250 ) + 8002106: 4293 cmp r3, r2 + 8002108: d019 beq.n 800213e + 800210a: 687b ldr r3, [r7, #4] + 800210c: 4a51 ldr r2, [pc, #324] ; (8002254 ) + 800210e: 4293 cmp r3, r2 + 8002110: d013 beq.n 800213a + 8002112: 687b ldr r3, [r7, #4] + 8002114: 4a50 ldr r2, [pc, #320] ; (8002258 ) + 8002116: 4293 cmp r3, r2 + 8002118: d00d beq.n 8002136 + 800211a: 687b ldr r3, [r7, #4] + 800211c: 4a4f ldr r2, [pc, #316] ; (800225c ) + 800211e: 4293 cmp r3, r2 + 8002120: d007 beq.n 8002132 + 8002122: 687b ldr r3, [r7, #4] + 8002124: 4a4e ldr r2, [pc, #312] ; (8002260 ) + 8002126: 4293 cmp r3, r2 + 8002128: d101 bne.n 800212e + 800212a: 2309 movs r3, #9 + 800212c: e012 b.n 8002154 + 800212e: 230a movs r3, #10 + 8002130: e010 b.n 8002154 + 8002132: 2308 movs r3, #8 + 8002134: e00e b.n 8002154 + 8002136: 2307 movs r3, #7 + 8002138: e00c b.n 8002154 + 800213a: 2306 movs r3, #6 + 800213c: e00a b.n 8002154 + 800213e: 2305 movs r3, #5 + 8002140: e008 b.n 8002154 + 8002142: 2304 movs r3, #4 + 8002144: e006 b.n 8002154 + 8002146: 2303 movs r3, #3 + 8002148: e004 b.n 8002154 + 800214a: 2302 movs r3, #2 + 800214c: e002 b.n 8002154 + 800214e: 2301 movs r3, #1 + 8002150: e000 b.n 8002154 + 8002152: 2300 movs r3, #0 + 8002154: 69fa ldr r2, [r7, #28] + 8002156: f002 0203 and.w r2, r2, #3 + 800215a: 0092 lsls r2, r2, #2 + 800215c: 4093 lsls r3, r2 + 800215e: 69ba ldr r2, [r7, #24] + 8002160: 4313 orrs r3, r2 + 8002162: 61bb str r3, [r7, #24] + SYSCFG->EXTICR[position >> 2] = temp; + 8002164: 4934 ldr r1, [pc, #208] ; (8002238 ) + 8002166: 69fb ldr r3, [r7, #28] + 8002168: 089b lsrs r3, r3, #2 + 800216a: 3302 adds r3, #2 + 800216c: 69ba ldr r2, [r7, #24] + 800216e: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 8002172: 4b3c ldr r3, [pc, #240] ; (8002264 ) + 8002174: 681b ldr r3, [r3, #0] + 8002176: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 8002178: 693b ldr r3, [r7, #16] + 800217a: 43db mvns r3, r3 + 800217c: 69ba ldr r2, [r7, #24] + 800217e: 4013 ands r3, r2 + 8002180: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + 8002182: 683b ldr r3, [r7, #0] + 8002184: 685b ldr r3, [r3, #4] + 8002186: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 800218a: 2b00 cmp r3, #0 + 800218c: d003 beq.n 8002196 + { + temp |= iocurrent; + 800218e: 69ba ldr r2, [r7, #24] + 8002190: 693b ldr r3, [r7, #16] + 8002192: 4313 orrs r3, r2 + 8002194: 61bb str r3, [r7, #24] + } + EXTI->IMR = temp; + 8002196: 4a33 ldr r2, [pc, #204] ; (8002264 ) + 8002198: 69bb ldr r3, [r7, #24] + 800219a: 6013 str r3, [r2, #0] + + temp = EXTI->EMR; + 800219c: 4b31 ldr r3, [pc, #196] ; (8002264 ) + 800219e: 685b ldr r3, [r3, #4] + 80021a0: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 80021a2: 693b ldr r3, [r7, #16] + 80021a4: 43db mvns r3, r3 + 80021a6: 69ba ldr r2, [r7, #24] + 80021a8: 4013 ands r3, r2 + 80021aa: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + 80021ac: 683b ldr r3, [r7, #0] + 80021ae: 685b ldr r3, [r3, #4] + 80021b0: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80021b4: 2b00 cmp r3, #0 + 80021b6: d003 beq.n 80021c0 + { + temp |= iocurrent; + 80021b8: 69ba ldr r2, [r7, #24] + 80021ba: 693b ldr r3, [r7, #16] + 80021bc: 4313 orrs r3, r2 + 80021be: 61bb str r3, [r7, #24] + } + EXTI->EMR = temp; + 80021c0: 4a28 ldr r2, [pc, #160] ; (8002264 ) + 80021c2: 69bb ldr r3, [r7, #24] + 80021c4: 6053 str r3, [r2, #4] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 80021c6: 4b27 ldr r3, [pc, #156] ; (8002264 ) + 80021c8: 689b ldr r3, [r3, #8] + 80021ca: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 80021cc: 693b ldr r3, [r7, #16] + 80021ce: 43db mvns r3, r3 + 80021d0: 69ba ldr r2, [r7, #24] + 80021d2: 4013 ands r3, r2 + 80021d4: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + 80021d6: 683b ldr r3, [r7, #0] + 80021d8: 685b ldr r3, [r3, #4] + 80021da: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 80021de: 2b00 cmp r3, #0 + 80021e0: d003 beq.n 80021ea + { + temp |= iocurrent; + 80021e2: 69ba ldr r2, [r7, #24] + 80021e4: 693b ldr r3, [r7, #16] + 80021e6: 4313 orrs r3, r2 + 80021e8: 61bb str r3, [r7, #24] + } + EXTI->RTSR = temp; + 80021ea: 4a1e ldr r2, [pc, #120] ; (8002264 ) + 80021ec: 69bb ldr r3, [r7, #24] + 80021ee: 6093 str r3, [r2, #8] + + temp = EXTI->FTSR; + 80021f0: 4b1c ldr r3, [pc, #112] ; (8002264 ) + 80021f2: 68db ldr r3, [r3, #12] + 80021f4: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 80021f6: 693b ldr r3, [r7, #16] + 80021f8: 43db mvns r3, r3 + 80021fa: 69ba ldr r2, [r7, #24] + 80021fc: 4013 ands r3, r2 + 80021fe: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + 8002200: 683b ldr r3, [r7, #0] + 8002202: 685b ldr r3, [r3, #4] + 8002204: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8002208: 2b00 cmp r3, #0 + 800220a: d003 beq.n 8002214 + { + temp |= iocurrent; + 800220c: 69ba ldr r2, [r7, #24] + 800220e: 693b ldr r3, [r7, #16] + 8002210: 4313 orrs r3, r2 + 8002212: 61bb str r3, [r7, #24] + } + EXTI->FTSR = temp; + 8002214: 4a13 ldr r2, [pc, #76] ; (8002264 ) + 8002216: 69bb ldr r3, [r7, #24] + 8002218: 60d3 str r3, [r2, #12] + for(position = 0; position < GPIO_NUMBER; position++) + 800221a: 69fb ldr r3, [r7, #28] + 800221c: 3301 adds r3, #1 + 800221e: 61fb str r3, [r7, #28] + 8002220: 69fb ldr r3, [r7, #28] + 8002222: 2b0f cmp r3, #15 + 8002224: f67f ae86 bls.w 8001f34 + } + } + } +} + 8002228: bf00 nop + 800222a: 3724 adds r7, #36 ; 0x24 + 800222c: 46bd mov sp, r7 + 800222e: f85d 7b04 ldr.w r7, [sp], #4 + 8002232: 4770 bx lr + 8002234: 40023800 .word 0x40023800 + 8002238: 40013800 .word 0x40013800 + 800223c: 40020000 .word 0x40020000 + 8002240: 40020400 .word 0x40020400 + 8002244: 40020800 .word 0x40020800 + 8002248: 40020c00 .word 0x40020c00 + 800224c: 40021000 .word 0x40021000 + 8002250: 40021400 .word 0x40021400 + 8002254: 40021800 .word 0x40021800 + 8002258: 40021c00 .word 0x40021c00 + 800225c: 40022000 .word 0x40022000 + 8002260: 40022400 .word 0x40022400 + 8002264: 40013c00 .word 0x40013c00 + +08002268 : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 8002268: b480 push {r7} + 800226a: b083 sub sp, #12 + 800226c: af00 add r7, sp, #0 + 800226e: 6078 str r0, [r7, #4] + 8002270: 460b mov r3, r1 + 8002272: 807b strh r3, [r7, #2] + 8002274: 4613 mov r3, r2 + 8002276: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if(PinState != GPIO_PIN_RESET) + 8002278: 787b ldrb r3, [r7, #1] + 800227a: 2b00 cmp r3, #0 + 800227c: d003 beq.n 8002286 + { + GPIOx->BSRR = GPIO_Pin; + 800227e: 887a ldrh r2, [r7, #2] + 8002280: 687b ldr r3, [r7, #4] + 8002282: 619a str r2, [r3, #24] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; + } +} + 8002284: e003 b.n 800228e + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; + 8002286: 887b ldrh r3, [r7, #2] + 8002288: 041a lsls r2, r3, #16 + 800228a: 687b ldr r3, [r7, #4] + 800228c: 619a str r2, [r3, #24] +} + 800228e: bf00 nop + 8002290: 370c adds r7, #12 + 8002292: 46bd mov sp, r7 + 8002294: f85d 7b04 ldr.w r7, [sp], #4 + 8002298: 4770 bx lr + ... + +0800229c : + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin Specifies the pins connected EXTI line + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + 800229c: b580 push {r7, lr} + 800229e: b082 sub sp, #8 + 80022a0: af00 add r7, sp, #0 + 80022a2: 4603 mov r3, r0 + 80022a4: 80fb strh r3, [r7, #6] + /* EXTI line interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + 80022a6: 4b08 ldr r3, [pc, #32] ; (80022c8 ) + 80022a8: 695a ldr r2, [r3, #20] + 80022aa: 88fb ldrh r3, [r7, #6] + 80022ac: 4013 ands r3, r2 + 80022ae: 2b00 cmp r3, #0 + 80022b0: d006 beq.n 80022c0 + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + 80022b2: 4a05 ldr r2, [pc, #20] ; (80022c8 ) + 80022b4: 88fb ldrh r3, [r7, #6] + 80022b6: 6153 str r3, [r2, #20] + HAL_GPIO_EXTI_Callback(GPIO_Pin); + 80022b8: 88fb ldrh r3, [r7, #6] + 80022ba: 4618 mov r0, r3 + 80022bc: f7ff f97c bl 80015b8 + } +} + 80022c0: bf00 nop + 80022c2: 3708 adds r7, #8 + 80022c4: 46bd mov sp, r7 + 80022c6: bd80 pop {r7, pc} + 80022c8: 40013c00 .word 0x40013c00 + +080022cc : + * supported by this function. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 80022cc: b580 push {r7, lr} + 80022ce: b086 sub sp, #24 + 80022d0: af00 add r7, sp, #0 + 80022d2: 6078 str r0, [r7, #4] + uint32_t tickstart; + FlagStatus pwrclkchanged = RESET; + 80022d4: 2300 movs r3, #0 + 80022d6: 75fb strb r3, [r7, #23] + + /* Check Null pointer */ + if(RCC_OscInitStruct == NULL) + 80022d8: 687b ldr r3, [r7, #4] + 80022da: 2b00 cmp r3, #0 + 80022dc: d101 bne.n 80022e2 + { + return HAL_ERROR; + 80022de: 2301 movs r3, #1 + 80022e0: e25e b.n 80027a0 + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 80022e2: 687b ldr r3, [r7, #4] + 80022e4: 681b ldr r3, [r3, #0] + 80022e6: f003 0301 and.w r3, r3, #1 + 80022ea: 2b00 cmp r3, #0 + 80022ec: f000 8087 beq.w 80023fe + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + 80022f0: 4b96 ldr r3, [pc, #600] ; (800254c ) + 80022f2: 689b ldr r3, [r3, #8] + 80022f4: f003 030c and.w r3, r3, #12 + 80022f8: 2b04 cmp r3, #4 + 80022fa: d00c beq.n 8002316 + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + 80022fc: 4b93 ldr r3, [pc, #588] ; (800254c ) + 80022fe: 689b ldr r3, [r3, #8] + 8002300: f003 030c and.w r3, r3, #12 + 8002304: 2b08 cmp r3, #8 + 8002306: d112 bne.n 800232e + 8002308: 4b90 ldr r3, [pc, #576] ; (800254c ) + 800230a: 685b ldr r3, [r3, #4] + 800230c: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8002310: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 8002314: d10b bne.n 800232e + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8002316: 4b8d ldr r3, [pc, #564] ; (800254c ) + 8002318: 681b ldr r3, [r3, #0] + 800231a: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800231e: 2b00 cmp r3, #0 + 8002320: d06c beq.n 80023fc + 8002322: 687b ldr r3, [r7, #4] + 8002324: 685b ldr r3, [r3, #4] + 8002326: 2b00 cmp r3, #0 + 8002328: d168 bne.n 80023fc + { + return HAL_ERROR; + 800232a: 2301 movs r3, #1 + 800232c: e238 b.n 80027a0 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 800232e: 687b ldr r3, [r7, #4] + 8002330: 685b ldr r3, [r3, #4] + 8002332: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8002336: d106 bne.n 8002346 + 8002338: 4b84 ldr r3, [pc, #528] ; (800254c ) + 800233a: 681b ldr r3, [r3, #0] + 800233c: 4a83 ldr r2, [pc, #524] ; (800254c ) + 800233e: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8002342: 6013 str r3, [r2, #0] + 8002344: e02e b.n 80023a4 + 8002346: 687b ldr r3, [r7, #4] + 8002348: 685b ldr r3, [r3, #4] + 800234a: 2b00 cmp r3, #0 + 800234c: d10c bne.n 8002368 + 800234e: 4b7f ldr r3, [pc, #508] ; (800254c ) + 8002350: 681b ldr r3, [r3, #0] + 8002352: 4a7e ldr r2, [pc, #504] ; (800254c ) + 8002354: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8002358: 6013 str r3, [r2, #0] + 800235a: 4b7c ldr r3, [pc, #496] ; (800254c ) + 800235c: 681b ldr r3, [r3, #0] + 800235e: 4a7b ldr r2, [pc, #492] ; (800254c ) + 8002360: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8002364: 6013 str r3, [r2, #0] + 8002366: e01d b.n 80023a4 + 8002368: 687b ldr r3, [r7, #4] + 800236a: 685b ldr r3, [r3, #4] + 800236c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 + 8002370: d10c bne.n 800238c + 8002372: 4b76 ldr r3, [pc, #472] ; (800254c ) + 8002374: 681b ldr r3, [r3, #0] + 8002376: 4a75 ldr r2, [pc, #468] ; (800254c ) + 8002378: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 800237c: 6013 str r3, [r2, #0] + 800237e: 4b73 ldr r3, [pc, #460] ; (800254c ) + 8002380: 681b ldr r3, [r3, #0] + 8002382: 4a72 ldr r2, [pc, #456] ; (800254c ) + 8002384: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8002388: 6013 str r3, [r2, #0] + 800238a: e00b b.n 80023a4 + 800238c: 4b6f ldr r3, [pc, #444] ; (800254c ) + 800238e: 681b ldr r3, [r3, #0] + 8002390: 4a6e ldr r2, [pc, #440] ; (800254c ) + 8002392: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8002396: 6013 str r3, [r2, #0] + 8002398: 4b6c ldr r3, [pc, #432] ; (800254c ) + 800239a: 681b ldr r3, [r3, #0] + 800239c: 4a6b ldr r2, [pc, #428] ; (800254c ) + 800239e: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 80023a2: 6013 str r3, [r2, #0] + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 80023a4: 687b ldr r3, [r7, #4] + 80023a6: 685b ldr r3, [r3, #4] + 80023a8: 2b00 cmp r3, #0 + 80023aa: d013 beq.n 80023d4 + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80023ac: f7ff fc72 bl 8001c94 + 80023b0: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 80023b2: e008 b.n 80023c6 + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 80023b4: f7ff fc6e bl 8001c94 + 80023b8: 4602 mov r2, r0 + 80023ba: 693b ldr r3, [r7, #16] + 80023bc: 1ad3 subs r3, r2, r3 + 80023be: 2b64 cmp r3, #100 ; 0x64 + 80023c0: d901 bls.n 80023c6 + { + return HAL_TIMEOUT; + 80023c2: 2303 movs r3, #3 + 80023c4: e1ec b.n 80027a0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 80023c6: 4b61 ldr r3, [pc, #388] ; (800254c ) + 80023c8: 681b ldr r3, [r3, #0] + 80023ca: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80023ce: 2b00 cmp r3, #0 + 80023d0: d0f0 beq.n 80023b4 + 80023d2: e014 b.n 80023fe + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80023d4: f7ff fc5e bl 8001c94 + 80023d8: 6138 str r0, [r7, #16] + + /* Wait till HSE is bypassed or disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 80023da: e008 b.n 80023ee + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 80023dc: f7ff fc5a bl 8001c94 + 80023e0: 4602 mov r2, r0 + 80023e2: 693b ldr r3, [r7, #16] + 80023e4: 1ad3 subs r3, r2, r3 + 80023e6: 2b64 cmp r3, #100 ; 0x64 + 80023e8: d901 bls.n 80023ee + { + return HAL_TIMEOUT; + 80023ea: 2303 movs r3, #3 + 80023ec: e1d8 b.n 80027a0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 80023ee: 4b57 ldr r3, [pc, #348] ; (800254c ) + 80023f0: 681b ldr r3, [r3, #0] + 80023f2: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80023f6: 2b00 cmp r3, #0 + 80023f8: d1f0 bne.n 80023dc + 80023fa: e000 b.n 80023fe + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 80023fc: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 80023fe: 687b ldr r3, [r7, #4] + 8002400: 681b ldr r3, [r3, #0] + 8002402: f003 0302 and.w r3, r3, #2 + 8002406: 2b00 cmp r3, #0 + 8002408: d069 beq.n 80024de + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + 800240a: 4b50 ldr r3, [pc, #320] ; (800254c ) + 800240c: 689b ldr r3, [r3, #8] + 800240e: f003 030c and.w r3, r3, #12 + 8002412: 2b00 cmp r3, #0 + 8002414: d00b beq.n 800242e + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + 8002416: 4b4d ldr r3, [pc, #308] ; (800254c ) + 8002418: 689b ldr r3, [r3, #8] + 800241a: f003 030c and.w r3, r3, #12 + 800241e: 2b08 cmp r3, #8 + 8002420: d11c bne.n 800245c + 8002422: 4b4a ldr r3, [pc, #296] ; (800254c ) + 8002424: 685b ldr r3, [r3, #4] + 8002426: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 800242a: 2b00 cmp r3, #0 + 800242c: d116 bne.n 800245c + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 800242e: 4b47 ldr r3, [pc, #284] ; (800254c ) + 8002430: 681b ldr r3, [r3, #0] + 8002432: f003 0302 and.w r3, r3, #2 + 8002436: 2b00 cmp r3, #0 + 8002438: d005 beq.n 8002446 + 800243a: 687b ldr r3, [r7, #4] + 800243c: 68db ldr r3, [r3, #12] + 800243e: 2b01 cmp r3, #1 + 8002440: d001 beq.n 8002446 + { + return HAL_ERROR; + 8002442: 2301 movs r3, #1 + 8002444: e1ac b.n 80027a0 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8002446: 4b41 ldr r3, [pc, #260] ; (800254c ) + 8002448: 681b ldr r3, [r3, #0] + 800244a: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 800244e: 687b ldr r3, [r7, #4] + 8002450: 691b ldr r3, [r3, #16] + 8002452: 00db lsls r3, r3, #3 + 8002454: 493d ldr r1, [pc, #244] ; (800254c ) + 8002456: 4313 orrs r3, r2 + 8002458: 600b str r3, [r1, #0] + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 800245a: e040 b.n 80024de + } + } + else + { + /* Check the HSI State */ + if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) + 800245c: 687b ldr r3, [r7, #4] + 800245e: 68db ldr r3, [r3, #12] + 8002460: 2b00 cmp r3, #0 + 8002462: d023 beq.n 80024ac + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 8002464: 4b39 ldr r3, [pc, #228] ; (800254c ) + 8002466: 681b ldr r3, [r3, #0] + 8002468: 4a38 ldr r2, [pc, #224] ; (800254c ) + 800246a: f043 0301 orr.w r3, r3, #1 + 800246e: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002470: f7ff fc10 bl 8001c94 + 8002474: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8002476: e008 b.n 800248a + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8002478: f7ff fc0c bl 8001c94 + 800247c: 4602 mov r2, r0 + 800247e: 693b ldr r3, [r7, #16] + 8002480: 1ad3 subs r3, r2, r3 + 8002482: 2b02 cmp r3, #2 + 8002484: d901 bls.n 800248a + { + return HAL_TIMEOUT; + 8002486: 2303 movs r3, #3 + 8002488: e18a b.n 80027a0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 800248a: 4b30 ldr r3, [pc, #192] ; (800254c ) + 800248c: 681b ldr r3, [r3, #0] + 800248e: f003 0302 and.w r3, r3, #2 + 8002492: 2b00 cmp r3, #0 + 8002494: d0f0 beq.n 8002478 + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8002496: 4b2d ldr r3, [pc, #180] ; (800254c ) + 8002498: 681b ldr r3, [r3, #0] + 800249a: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 800249e: 687b ldr r3, [r7, #4] + 80024a0: 691b ldr r3, [r3, #16] + 80024a2: 00db lsls r3, r3, #3 + 80024a4: 4929 ldr r1, [pc, #164] ; (800254c ) + 80024a6: 4313 orrs r3, r2 + 80024a8: 600b str r3, [r1, #0] + 80024aa: e018 b.n 80024de + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 80024ac: 4b27 ldr r3, [pc, #156] ; (800254c ) + 80024ae: 681b ldr r3, [r3, #0] + 80024b0: 4a26 ldr r2, [pc, #152] ; (800254c ) + 80024b2: f023 0301 bic.w r3, r3, #1 + 80024b6: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80024b8: f7ff fbec bl 8001c94 + 80024bc: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 80024be: e008 b.n 80024d2 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 80024c0: f7ff fbe8 bl 8001c94 + 80024c4: 4602 mov r2, r0 + 80024c6: 693b ldr r3, [r7, #16] + 80024c8: 1ad3 subs r3, r2, r3 + 80024ca: 2b02 cmp r3, #2 + 80024cc: d901 bls.n 80024d2 + { + return HAL_TIMEOUT; + 80024ce: 2303 movs r3, #3 + 80024d0: e166 b.n 80027a0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 80024d2: 4b1e ldr r3, [pc, #120] ; (800254c ) + 80024d4: 681b ldr r3, [r3, #0] + 80024d6: f003 0302 and.w r3, r3, #2 + 80024da: 2b00 cmp r3, #0 + 80024dc: d1f0 bne.n 80024c0 + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 80024de: 687b ldr r3, [r7, #4] + 80024e0: 681b ldr r3, [r3, #0] + 80024e2: f003 0308 and.w r3, r3, #8 + 80024e6: 2b00 cmp r3, #0 + 80024e8: d038 beq.n 800255c + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) + 80024ea: 687b ldr r3, [r7, #4] + 80024ec: 695b ldr r3, [r3, #20] + 80024ee: 2b00 cmp r3, #0 + 80024f0: d019 beq.n 8002526 + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 80024f2: 4b16 ldr r3, [pc, #88] ; (800254c ) + 80024f4: 6f5b ldr r3, [r3, #116] ; 0x74 + 80024f6: 4a15 ldr r2, [pc, #84] ; (800254c ) + 80024f8: f043 0301 orr.w r3, r3, #1 + 80024fc: 6753 str r3, [r2, #116] ; 0x74 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80024fe: f7ff fbc9 bl 8001c94 + 8002502: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8002504: e008 b.n 8002518 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8002506: f7ff fbc5 bl 8001c94 + 800250a: 4602 mov r2, r0 + 800250c: 693b ldr r3, [r7, #16] + 800250e: 1ad3 subs r3, r2, r3 + 8002510: 2b02 cmp r3, #2 + 8002512: d901 bls.n 8002518 + { + return HAL_TIMEOUT; + 8002514: 2303 movs r3, #3 + 8002516: e143 b.n 80027a0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8002518: 4b0c ldr r3, [pc, #48] ; (800254c ) + 800251a: 6f5b ldr r3, [r3, #116] ; 0x74 + 800251c: f003 0302 and.w r3, r3, #2 + 8002520: 2b00 cmp r3, #0 + 8002522: d0f0 beq.n 8002506 + 8002524: e01a b.n 800255c + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8002526: 4b09 ldr r3, [pc, #36] ; (800254c ) + 8002528: 6f5b ldr r3, [r3, #116] ; 0x74 + 800252a: 4a08 ldr r2, [pc, #32] ; (800254c ) + 800252c: f023 0301 bic.w r3, r3, #1 + 8002530: 6753 str r3, [r2, #116] ; 0x74 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002532: f7ff fbaf bl 8001c94 + 8002536: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8002538: e00a b.n 8002550 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 800253a: f7ff fbab bl 8001c94 + 800253e: 4602 mov r2, r0 + 8002540: 693b ldr r3, [r7, #16] + 8002542: 1ad3 subs r3, r2, r3 + 8002544: 2b02 cmp r3, #2 + 8002546: d903 bls.n 8002550 + { + return HAL_TIMEOUT; + 8002548: 2303 movs r3, #3 + 800254a: e129 b.n 80027a0 + 800254c: 40023800 .word 0x40023800 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8002550: 4b95 ldr r3, [pc, #596] ; (80027a8 ) + 8002552: 6f5b ldr r3, [r3, #116] ; 0x74 + 8002554: f003 0302 and.w r3, r3, #2 + 8002558: 2b00 cmp r3, #0 + 800255a: d1ee bne.n 800253a + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 800255c: 687b ldr r3, [r7, #4] + 800255e: 681b ldr r3, [r3, #0] + 8002560: f003 0304 and.w r3, r3, #4 + 8002564: 2b00 cmp r3, #0 + 8002566: f000 80a4 beq.w 80026b2 + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 800256a: 4b8f ldr r3, [pc, #572] ; (80027a8 ) + 800256c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800256e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8002572: 2b00 cmp r3, #0 + 8002574: d10d bne.n 8002592 + { + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + 8002576: 4b8c ldr r3, [pc, #560] ; (80027a8 ) + 8002578: 6c1b ldr r3, [r3, #64] ; 0x40 + 800257a: 4a8b ldr r2, [pc, #556] ; (80027a8 ) + 800257c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8002580: 6413 str r3, [r2, #64] ; 0x40 + 8002582: 4b89 ldr r3, [pc, #548] ; (80027a8 ) + 8002584: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002586: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 800258a: 60fb str r3, [r7, #12] + 800258c: 68fb ldr r3, [r7, #12] + pwrclkchanged = SET; + 800258e: 2301 movs r3, #1 + 8002590: 75fb strb r3, [r7, #23] + } + + if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 8002592: 4b86 ldr r3, [pc, #536] ; (80027ac ) + 8002594: 681b ldr r3, [r3, #0] + 8002596: f403 7380 and.w r3, r3, #256 ; 0x100 + 800259a: 2b00 cmp r3, #0 + 800259c: d118 bne.n 80025d0 + { + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + 800259e: 4b83 ldr r3, [pc, #524] ; (80027ac ) + 80025a0: 681b ldr r3, [r3, #0] + 80025a2: 4a82 ldr r2, [pc, #520] ; (80027ac ) + 80025a4: f443 7380 orr.w r3, r3, #256 ; 0x100 + 80025a8: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 80025aa: f7ff fb73 bl 8001c94 + 80025ae: 6138 str r0, [r7, #16] + + while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 80025b0: e008 b.n 80025c4 + { + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + 80025b2: f7ff fb6f bl 8001c94 + 80025b6: 4602 mov r2, r0 + 80025b8: 693b ldr r3, [r7, #16] + 80025ba: 1ad3 subs r3, r2, r3 + 80025bc: 2b64 cmp r3, #100 ; 0x64 + 80025be: d901 bls.n 80025c4 + { + return HAL_TIMEOUT; + 80025c0: 2303 movs r3, #3 + 80025c2: e0ed b.n 80027a0 + while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 80025c4: 4b79 ldr r3, [pc, #484] ; (80027ac ) + 80025c6: 681b ldr r3, [r3, #0] + 80025c8: f403 7380 and.w r3, r3, #256 ; 0x100 + 80025cc: 2b00 cmp r3, #0 + 80025ce: d0f0 beq.n 80025b2 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 80025d0: 687b ldr r3, [r7, #4] + 80025d2: 689b ldr r3, [r3, #8] + 80025d4: 2b01 cmp r3, #1 + 80025d6: d106 bne.n 80025e6 + 80025d8: 4b73 ldr r3, [pc, #460] ; (80027a8 ) + 80025da: 6f1b ldr r3, [r3, #112] ; 0x70 + 80025dc: 4a72 ldr r2, [pc, #456] ; (80027a8 ) + 80025de: f043 0301 orr.w r3, r3, #1 + 80025e2: 6713 str r3, [r2, #112] ; 0x70 + 80025e4: e02d b.n 8002642 + 80025e6: 687b ldr r3, [r7, #4] + 80025e8: 689b ldr r3, [r3, #8] + 80025ea: 2b00 cmp r3, #0 + 80025ec: d10c bne.n 8002608 + 80025ee: 4b6e ldr r3, [pc, #440] ; (80027a8 ) + 80025f0: 6f1b ldr r3, [r3, #112] ; 0x70 + 80025f2: 4a6d ldr r2, [pc, #436] ; (80027a8 ) + 80025f4: f023 0301 bic.w r3, r3, #1 + 80025f8: 6713 str r3, [r2, #112] ; 0x70 + 80025fa: 4b6b ldr r3, [pc, #428] ; (80027a8 ) + 80025fc: 6f1b ldr r3, [r3, #112] ; 0x70 + 80025fe: 4a6a ldr r2, [pc, #424] ; (80027a8 ) + 8002600: f023 0304 bic.w r3, r3, #4 + 8002604: 6713 str r3, [r2, #112] ; 0x70 + 8002606: e01c b.n 8002642 + 8002608: 687b ldr r3, [r7, #4] + 800260a: 689b ldr r3, [r3, #8] + 800260c: 2b05 cmp r3, #5 + 800260e: d10c bne.n 800262a + 8002610: 4b65 ldr r3, [pc, #404] ; (80027a8 ) + 8002612: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002614: 4a64 ldr r2, [pc, #400] ; (80027a8 ) + 8002616: f043 0304 orr.w r3, r3, #4 + 800261a: 6713 str r3, [r2, #112] ; 0x70 + 800261c: 4b62 ldr r3, [pc, #392] ; (80027a8 ) + 800261e: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002620: 4a61 ldr r2, [pc, #388] ; (80027a8 ) + 8002622: f043 0301 orr.w r3, r3, #1 + 8002626: 6713 str r3, [r2, #112] ; 0x70 + 8002628: e00b b.n 8002642 + 800262a: 4b5f ldr r3, [pc, #380] ; (80027a8 ) + 800262c: 6f1b ldr r3, [r3, #112] ; 0x70 + 800262e: 4a5e ldr r2, [pc, #376] ; (80027a8 ) + 8002630: f023 0301 bic.w r3, r3, #1 + 8002634: 6713 str r3, [r2, #112] ; 0x70 + 8002636: 4b5c ldr r3, [pc, #368] ; (80027a8 ) + 8002638: 6f1b ldr r3, [r3, #112] ; 0x70 + 800263a: 4a5b ldr r2, [pc, #364] ; (80027a8 ) + 800263c: f023 0304 bic.w r3, r3, #4 + 8002640: 6713 str r3, [r2, #112] ; 0x70 + /* Check the LSE State */ + if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + 8002642: 687b ldr r3, [r7, #4] + 8002644: 689b ldr r3, [r3, #8] + 8002646: 2b00 cmp r3, #0 + 8002648: d015 beq.n 8002676 + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800264a: f7ff fb23 bl 8001c94 + 800264e: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8002650: e00a b.n 8002668 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8002652: f7ff fb1f bl 8001c94 + 8002656: 4602 mov r2, r0 + 8002658: 693b ldr r3, [r7, #16] + 800265a: 1ad3 subs r3, r2, r3 + 800265c: f241 3288 movw r2, #5000 ; 0x1388 + 8002660: 4293 cmp r3, r2 + 8002662: d901 bls.n 8002668 + { + return HAL_TIMEOUT; + 8002664: 2303 movs r3, #3 + 8002666: e09b b.n 80027a0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8002668: 4b4f ldr r3, [pc, #316] ; (80027a8 ) + 800266a: 6f1b ldr r3, [r3, #112] ; 0x70 + 800266c: f003 0302 and.w r3, r3, #2 + 8002670: 2b00 cmp r3, #0 + 8002672: d0ee beq.n 8002652 + 8002674: e014 b.n 80026a0 + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002676: f7ff fb0d bl 8001c94 + 800267a: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 800267c: e00a b.n 8002694 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 800267e: f7ff fb09 bl 8001c94 + 8002682: 4602 mov r2, r0 + 8002684: 693b ldr r3, [r7, #16] + 8002686: 1ad3 subs r3, r2, r3 + 8002688: f241 3288 movw r2, #5000 ; 0x1388 + 800268c: 4293 cmp r3, r2 + 800268e: d901 bls.n 8002694 + { + return HAL_TIMEOUT; + 8002690: 2303 movs r3, #3 + 8002692: e085 b.n 80027a0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8002694: 4b44 ldr r3, [pc, #272] ; (80027a8 ) + 8002696: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002698: f003 0302 and.w r3, r3, #2 + 800269c: 2b00 cmp r3, #0 + 800269e: d1ee bne.n 800267e + } + } + } + + /* Restore clock configuration if changed */ + if(pwrclkchanged == SET) + 80026a0: 7dfb ldrb r3, [r7, #23] + 80026a2: 2b01 cmp r3, #1 + 80026a4: d105 bne.n 80026b2 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 80026a6: 4b40 ldr r3, [pc, #256] ; (80027a8 ) + 80026a8: 6c1b ldr r3, [r3, #64] ; 0x40 + 80026aa: 4a3f ldr r2, [pc, #252] ; (80027a8 ) + 80026ac: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 80026b0: 6413 str r3, [r2, #64] ; 0x40 + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 80026b2: 687b ldr r3, [r7, #4] + 80026b4: 699b ldr r3, [r3, #24] + 80026b6: 2b00 cmp r3, #0 + 80026b8: d071 beq.n 800279e + { + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 80026ba: 4b3b ldr r3, [pc, #236] ; (80027a8 ) + 80026bc: 689b ldr r3, [r3, #8] + 80026be: f003 030c and.w r3, r3, #12 + 80026c2: 2b08 cmp r3, #8 + 80026c4: d069 beq.n 800279a + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 80026c6: 687b ldr r3, [r7, #4] + 80026c8: 699b ldr r3, [r3, #24] + 80026ca: 2b02 cmp r3, #2 + 80026cc: d14b bne.n 8002766 +#if defined (RCC_PLLCFGR_PLLR) + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); +#endif + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 80026ce: 4b36 ldr r3, [pc, #216] ; (80027a8 ) + 80026d0: 681b ldr r3, [r3, #0] + 80026d2: 4a35 ldr r2, [pc, #212] ; (80027a8 ) + 80026d4: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 80026d8: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80026da: f7ff fadb bl 8001c94 + 80026de: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 80026e0: e008 b.n 80026f4 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 80026e2: f7ff fad7 bl 8001c94 + 80026e6: 4602 mov r2, r0 + 80026e8: 693b ldr r3, [r7, #16] + 80026ea: 1ad3 subs r3, r2, r3 + 80026ec: 2b02 cmp r3, #2 + 80026ee: d901 bls.n 80026f4 + { + return HAL_TIMEOUT; + 80026f0: 2303 movs r3, #3 + 80026f2: e055 b.n 80027a0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 80026f4: 4b2c ldr r3, [pc, #176] ; (80027a8 ) + 80026f6: 681b ldr r3, [r3, #0] + 80026f8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 80026fc: 2b00 cmp r3, #0 + 80026fe: d1f0 bne.n 80026e2 + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ +#if defined (RCC_PLLCFGR_PLLR) + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8002700: 687b ldr r3, [r7, #4] + 8002702: 69da ldr r2, [r3, #28] + 8002704: 687b ldr r3, [r7, #4] + 8002706: 6a1b ldr r3, [r3, #32] + 8002708: 431a orrs r2, r3 + 800270a: 687b ldr r3, [r7, #4] + 800270c: 6a5b ldr r3, [r3, #36] ; 0x24 + 800270e: 019b lsls r3, r3, #6 + 8002710: 431a orrs r2, r3 + 8002712: 687b ldr r3, [r7, #4] + 8002714: 6a9b ldr r3, [r3, #40] ; 0x28 + 8002716: 085b lsrs r3, r3, #1 + 8002718: 3b01 subs r3, #1 + 800271a: 041b lsls r3, r3, #16 + 800271c: 431a orrs r2, r3 + 800271e: 687b ldr r3, [r7, #4] + 8002720: 6adb ldr r3, [r3, #44] ; 0x2c + 8002722: 061b lsls r3, r3, #24 + 8002724: 431a orrs r2, r3 + 8002726: 687b ldr r3, [r7, #4] + 8002728: 6b1b ldr r3, [r3, #48] ; 0x30 + 800272a: 071b lsls r3, r3, #28 + 800272c: 491e ldr r1, [pc, #120] ; (80027a8 ) + 800272e: 4313 orrs r3, r2 + 8002730: 604b str r3, [r1, #4] + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ); +#endif + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8002732: 4b1d ldr r3, [pc, #116] ; (80027a8 ) + 8002734: 681b ldr r3, [r3, #0] + 8002736: 4a1c ldr r2, [pc, #112] ; (80027a8 ) + 8002738: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 800273c: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800273e: f7ff faa9 bl 8001c94 + 8002742: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8002744: e008 b.n 8002758 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8002746: f7ff faa5 bl 8001c94 + 800274a: 4602 mov r2, r0 + 800274c: 693b ldr r3, [r7, #16] + 800274e: 1ad3 subs r3, r2, r3 + 8002750: 2b02 cmp r3, #2 + 8002752: d901 bls.n 8002758 + { + return HAL_TIMEOUT; + 8002754: 2303 movs r3, #3 + 8002756: e023 b.n 80027a0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8002758: 4b13 ldr r3, [pc, #76] ; (80027a8 ) + 800275a: 681b ldr r3, [r3, #0] + 800275c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8002760: 2b00 cmp r3, #0 + 8002762: d0f0 beq.n 8002746 + 8002764: e01b b.n 800279e + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8002766: 4b10 ldr r3, [pc, #64] ; (80027a8 ) + 8002768: 681b ldr r3, [r3, #0] + 800276a: 4a0f ldr r2, [pc, #60] ; (80027a8 ) + 800276c: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 8002770: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002772: f7ff fa8f bl 8001c94 + 8002776: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8002778: e008 b.n 800278c + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 800277a: f7ff fa8b bl 8001c94 + 800277e: 4602 mov r2, r0 + 8002780: 693b ldr r3, [r7, #16] + 8002782: 1ad3 subs r3, r2, r3 + 8002784: 2b02 cmp r3, #2 + 8002786: d901 bls.n 800278c + { + return HAL_TIMEOUT; + 8002788: 2303 movs r3, #3 + 800278a: e009 b.n 80027a0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 800278c: 4b06 ldr r3, [pc, #24] ; (80027a8 ) + 800278e: 681b ldr r3, [r3, #0] + 8002790: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8002794: 2b00 cmp r3, #0 + 8002796: d1f0 bne.n 800277a + 8002798: e001 b.n 800279e + } + } + } + else + { + return HAL_ERROR; + 800279a: 2301 movs r3, #1 + 800279c: e000 b.n 80027a0 + } + } + return HAL_OK; + 800279e: 2300 movs r3, #0 +} + 80027a0: 4618 mov r0, r3 + 80027a2: 3718 adds r7, #24 + 80027a4: 46bd mov sp, r7 + 80027a6: bd80 pop {r7, pc} + 80027a8: 40023800 .word 0x40023800 + 80027ac: 40007000 .word 0x40007000 + +080027b0 : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 80027b0: b580 push {r7, lr} + 80027b2: b084 sub sp, #16 + 80027b4: af00 add r7, sp, #0 + 80027b6: 6078 str r0, [r7, #4] + 80027b8: 6039 str r1, [r7, #0] + uint32_t tickstart = 0; + 80027ba: 2300 movs r3, #0 + 80027bc: 60fb str r3, [r7, #12] + + /* Check Null pointer */ + if(RCC_ClkInitStruct == NULL) + 80027be: 687b ldr r3, [r7, #4] + 80027c0: 2b00 cmp r3, #0 + 80027c2: d101 bne.n 80027c8 + { + return HAL_ERROR; + 80027c4: 2301 movs r3, #1 + 80027c6: e0ce b.n 8002966 + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 80027c8: 4b69 ldr r3, [pc, #420] ; (8002970 ) + 80027ca: 681b ldr r3, [r3, #0] + 80027cc: f003 030f and.w r3, r3, #15 + 80027d0: 683a ldr r2, [r7, #0] + 80027d2: 429a cmp r2, r3 + 80027d4: d910 bls.n 80027f8 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 80027d6: 4b66 ldr r3, [pc, #408] ; (8002970 ) + 80027d8: 681b ldr r3, [r3, #0] + 80027da: f023 020f bic.w r2, r3, #15 + 80027de: 4964 ldr r1, [pc, #400] ; (8002970 ) + 80027e0: 683b ldr r3, [r7, #0] + 80027e2: 4313 orrs r3, r2 + 80027e4: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 80027e6: 4b62 ldr r3, [pc, #392] ; (8002970 ) + 80027e8: 681b ldr r3, [r3, #0] + 80027ea: f003 030f and.w r3, r3, #15 + 80027ee: 683a ldr r2, [r7, #0] + 80027f0: 429a cmp r2, r3 + 80027f2: d001 beq.n 80027f8 + { + return HAL_ERROR; + 80027f4: 2301 movs r3, #1 + 80027f6: e0b6 b.n 8002966 + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 80027f8: 687b ldr r3, [r7, #4] + 80027fa: 681b ldr r3, [r3, #0] + 80027fc: f003 0302 and.w r3, r3, #2 + 8002800: 2b00 cmp r3, #0 + 8002802: d020 beq.n 8002846 + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8002804: 687b ldr r3, [r7, #4] + 8002806: 681b ldr r3, [r3, #0] + 8002808: f003 0304 and.w r3, r3, #4 + 800280c: 2b00 cmp r3, #0 + 800280e: d005 beq.n 800281c + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + 8002810: 4b58 ldr r3, [pc, #352] ; (8002974 ) + 8002812: 689b ldr r3, [r3, #8] + 8002814: 4a57 ldr r2, [pc, #348] ; (8002974 ) + 8002816: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00 + 800281a: 6093 str r3, [r2, #8] + } + + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 800281c: 687b ldr r3, [r7, #4] + 800281e: 681b ldr r3, [r3, #0] + 8002820: f003 0308 and.w r3, r3, #8 + 8002824: 2b00 cmp r3, #0 + 8002826: d005 beq.n 8002834 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + 8002828: 4b52 ldr r3, [pc, #328] ; (8002974 ) + 800282a: 689b ldr r3, [r3, #8] + 800282c: 4a51 ldr r2, [pc, #324] ; (8002974 ) + 800282e: f443 4360 orr.w r3, r3, #57344 ; 0xe000 + 8002832: 6093 str r3, [r2, #8] + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8002834: 4b4f ldr r3, [pc, #316] ; (8002974 ) + 8002836: 689b ldr r3, [r3, #8] + 8002838: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 800283c: 687b ldr r3, [r7, #4] + 800283e: 689b ldr r3, [r3, #8] + 8002840: 494c ldr r1, [pc, #304] ; (8002974 ) + 8002842: 4313 orrs r3, r2 + 8002844: 608b str r3, [r1, #8] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8002846: 687b ldr r3, [r7, #4] + 8002848: 681b ldr r3, [r3, #0] + 800284a: f003 0301 and.w r3, r3, #1 + 800284e: 2b00 cmp r3, #0 + 8002850: d040 beq.n 80028d4 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8002852: 687b ldr r3, [r7, #4] + 8002854: 685b ldr r3, [r3, #4] + 8002856: 2b01 cmp r3, #1 + 8002858: d107 bne.n 800286a + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 800285a: 4b46 ldr r3, [pc, #280] ; (8002974 ) + 800285c: 681b ldr r3, [r3, #0] + 800285e: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002862: 2b00 cmp r3, #0 + 8002864: d115 bne.n 8002892 + { + return HAL_ERROR; + 8002866: 2301 movs r3, #1 + 8002868: e07d b.n 8002966 + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 800286a: 687b ldr r3, [r7, #4] + 800286c: 685b ldr r3, [r3, #4] + 800286e: 2b02 cmp r3, #2 + 8002870: d107 bne.n 8002882 + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8002872: 4b40 ldr r3, [pc, #256] ; (8002974 ) + 8002874: 681b ldr r3, [r3, #0] + 8002876: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 800287a: 2b00 cmp r3, #0 + 800287c: d109 bne.n 8002892 + { + return HAL_ERROR; + 800287e: 2301 movs r3, #1 + 8002880: e071 b.n 8002966 + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8002882: 4b3c ldr r3, [pc, #240] ; (8002974 ) + 8002884: 681b ldr r3, [r3, #0] + 8002886: f003 0302 and.w r3, r3, #2 + 800288a: 2b00 cmp r3, #0 + 800288c: d101 bne.n 8002892 + { + return HAL_ERROR; + 800288e: 2301 movs r3, #1 + 8002890: e069 b.n 8002966 + } + } + + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 8002892: 4b38 ldr r3, [pc, #224] ; (8002974 ) + 8002894: 689b ldr r3, [r3, #8] + 8002896: f023 0203 bic.w r2, r3, #3 + 800289a: 687b ldr r3, [r7, #4] + 800289c: 685b ldr r3, [r3, #4] + 800289e: 4935 ldr r1, [pc, #212] ; (8002974 ) + 80028a0: 4313 orrs r3, r2 + 80028a2: 608b str r3, [r1, #8] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80028a4: f7ff f9f6 bl 8001c94 + 80028a8: 60f8 str r0, [r7, #12] + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 80028aa: e00a b.n 80028c2 + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 80028ac: f7ff f9f2 bl 8001c94 + 80028b0: 4602 mov r2, r0 + 80028b2: 68fb ldr r3, [r7, #12] + 80028b4: 1ad3 subs r3, r2, r3 + 80028b6: f241 3288 movw r2, #5000 ; 0x1388 + 80028ba: 4293 cmp r3, r2 + 80028bc: d901 bls.n 80028c2 + { + return HAL_TIMEOUT; + 80028be: 2303 movs r3, #3 + 80028c0: e051 b.n 8002966 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 80028c2: 4b2c ldr r3, [pc, #176] ; (8002974 ) + 80028c4: 689b ldr r3, [r3, #8] + 80028c6: f003 020c and.w r2, r3, #12 + 80028ca: 687b ldr r3, [r7, #4] + 80028cc: 685b ldr r3, [r3, #4] + 80028ce: 009b lsls r3, r3, #2 + 80028d0: 429a cmp r2, r3 + 80028d2: d1eb bne.n 80028ac + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 80028d4: 4b26 ldr r3, [pc, #152] ; (8002970 ) + 80028d6: 681b ldr r3, [r3, #0] + 80028d8: f003 030f and.w r3, r3, #15 + 80028dc: 683a ldr r2, [r7, #0] + 80028de: 429a cmp r2, r3 + 80028e0: d210 bcs.n 8002904 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 80028e2: 4b23 ldr r3, [pc, #140] ; (8002970 ) + 80028e4: 681b ldr r3, [r3, #0] + 80028e6: f023 020f bic.w r2, r3, #15 + 80028ea: 4921 ldr r1, [pc, #132] ; (8002970 ) + 80028ec: 683b ldr r3, [r7, #0] + 80028ee: 4313 orrs r3, r2 + 80028f0: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 80028f2: 4b1f ldr r3, [pc, #124] ; (8002970 ) + 80028f4: 681b ldr r3, [r3, #0] + 80028f6: f003 030f and.w r3, r3, #15 + 80028fa: 683a ldr r2, [r7, #0] + 80028fc: 429a cmp r2, r3 + 80028fe: d001 beq.n 8002904 + { + return HAL_ERROR; + 8002900: 2301 movs r3, #1 + 8002902: e030 b.n 8002966 + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8002904: 687b ldr r3, [r7, #4] + 8002906: 681b ldr r3, [r3, #0] + 8002908: f003 0304 and.w r3, r3, #4 + 800290c: 2b00 cmp r3, #0 + 800290e: d008 beq.n 8002922 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 8002910: 4b18 ldr r3, [pc, #96] ; (8002974 ) + 8002912: 689b ldr r3, [r3, #8] + 8002914: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 + 8002918: 687b ldr r3, [r7, #4] + 800291a: 68db ldr r3, [r3, #12] + 800291c: 4915 ldr r1, [pc, #84] ; (8002974 ) + 800291e: 4313 orrs r3, r2 + 8002920: 608b str r3, [r1, #8] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8002922: 687b ldr r3, [r7, #4] + 8002924: 681b ldr r3, [r3, #0] + 8002926: f003 0308 and.w r3, r3, #8 + 800292a: 2b00 cmp r3, #0 + 800292c: d009 beq.n 8002942 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + 800292e: 4b11 ldr r3, [pc, #68] ; (8002974 ) + 8002930: 689b ldr r3, [r3, #8] + 8002932: f423 4260 bic.w r2, r3, #57344 ; 0xe000 + 8002936: 687b ldr r3, [r7, #4] + 8002938: 691b ldr r3, [r3, #16] + 800293a: 00db lsls r3, r3, #3 + 800293c: 490d ldr r1, [pc, #52] ; (8002974 ) + 800293e: 4313 orrs r3, r2 + 8002940: 608b str r3, [r1, #8] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + 8002942: f000 f81d bl 8002980 + 8002946: 4601 mov r1, r0 + 8002948: 4b0a ldr r3, [pc, #40] ; (8002974 ) + 800294a: 689b ldr r3, [r3, #8] + 800294c: 091b lsrs r3, r3, #4 + 800294e: f003 030f and.w r3, r3, #15 + 8002952: 4a09 ldr r2, [pc, #36] ; (8002978 ) + 8002954: 5cd3 ldrb r3, [r2, r3] + 8002956: fa21 f303 lsr.w r3, r1, r3 + 800295a: 4a08 ldr r2, [pc, #32] ; (800297c ) + 800295c: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick (TICK_INT_PRIORITY); + 800295e: 2000 movs r0, #0 + 8002960: f7ff f954 bl 8001c0c + + return HAL_OK; + 8002964: 2300 movs r3, #0 +} + 8002966: 4618 mov r0, r3 + 8002968: 3710 adds r7, #16 + 800296a: 46bd mov sp, r7 + 800296c: bd80 pop {r7, pc} + 800296e: bf00 nop + 8002970: 40023c00 .word 0x40023c00 + 8002974: 40023800 .word 0x40023800 + 8002978: 080054a4 .word 0x080054a4 + 800297c: 20000004 .word 0x20000004 + +08002980 : + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8002980: b5f0 push {r4, r5, r6, r7, lr} + 8002982: b085 sub sp, #20 + 8002984: af00 add r7, sp, #0 + uint32_t pllm = 0, pllvco = 0, pllp = 0; + 8002986: 2300 movs r3, #0 + 8002988: 607b str r3, [r7, #4] + 800298a: 2300 movs r3, #0 + 800298c: 60fb str r3, [r7, #12] + 800298e: 2300 movs r3, #0 + 8002990: 603b str r3, [r7, #0] + uint32_t sysclockfreq = 0; + 8002992: 2300 movs r3, #0 + 8002994: 60bb str r3, [r7, #8] + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + 8002996: 4b50 ldr r3, [pc, #320] ; (8002ad8 ) + 8002998: 689b ldr r3, [r3, #8] + 800299a: f003 030c and.w r3, r3, #12 + 800299e: 2b04 cmp r3, #4 + 80029a0: d007 beq.n 80029b2 + 80029a2: 2b08 cmp r3, #8 + 80029a4: d008 beq.n 80029b8 + 80029a6: 2b00 cmp r3, #0 + 80029a8: f040 808d bne.w 8002ac6 + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + 80029ac: 4b4b ldr r3, [pc, #300] ; (8002adc ) + 80029ae: 60bb str r3, [r7, #8] + break; + 80029b0: e08c b.n 8002acc + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + { + sysclockfreq = HSE_VALUE; + 80029b2: 4b4b ldr r3, [pc, #300] ; (8002ae0 ) + 80029b4: 60bb str r3, [r7, #8] + break; + 80029b6: e089 b.n 8002acc + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + 80029b8: 4b47 ldr r3, [pc, #284] ; (8002ad8 ) + 80029ba: 685b ldr r3, [r3, #4] + 80029bc: f003 033f and.w r3, r3, #63 ; 0x3f + 80029c0: 607b str r3, [r7, #4] + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) + 80029c2: 4b45 ldr r3, [pc, #276] ; (8002ad8 ) + 80029c4: 685b ldr r3, [r3, #4] + 80029c6: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 80029ca: 2b00 cmp r3, #0 + 80029cc: d023 beq.n 8002a16 + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 80029ce: 4b42 ldr r3, [pc, #264] ; (8002ad8 ) + 80029d0: 685b ldr r3, [r3, #4] + 80029d2: 099b lsrs r3, r3, #6 + 80029d4: f04f 0400 mov.w r4, #0 + 80029d8: f240 11ff movw r1, #511 ; 0x1ff + 80029dc: f04f 0200 mov.w r2, #0 + 80029e0: ea03 0501 and.w r5, r3, r1 + 80029e4: ea04 0602 and.w r6, r4, r2 + 80029e8: 4a3d ldr r2, [pc, #244] ; (8002ae0 ) + 80029ea: fb02 f106 mul.w r1, r2, r6 + 80029ee: 2200 movs r2, #0 + 80029f0: fb02 f205 mul.w r2, r2, r5 + 80029f4: 440a add r2, r1 + 80029f6: 493a ldr r1, [pc, #232] ; (8002ae0 ) + 80029f8: fba5 0101 umull r0, r1, r5, r1 + 80029fc: 1853 adds r3, r2, r1 + 80029fe: 4619 mov r1, r3 + 8002a00: 687b ldr r3, [r7, #4] + 8002a02: f04f 0400 mov.w r4, #0 + 8002a06: 461a mov r2, r3 + 8002a08: 4623 mov r3, r4 + 8002a0a: f7fd fc15 bl 8000238 <__aeabi_uldivmod> + 8002a0e: 4603 mov r3, r0 + 8002a10: 460c mov r4, r1 + 8002a12: 60fb str r3, [r7, #12] + 8002a14: e049 b.n 8002aaa + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 8002a16: 4b30 ldr r3, [pc, #192] ; (8002ad8 ) + 8002a18: 685b ldr r3, [r3, #4] + 8002a1a: 099b lsrs r3, r3, #6 + 8002a1c: f04f 0400 mov.w r4, #0 + 8002a20: f240 11ff movw r1, #511 ; 0x1ff + 8002a24: f04f 0200 mov.w r2, #0 + 8002a28: ea03 0501 and.w r5, r3, r1 + 8002a2c: ea04 0602 and.w r6, r4, r2 + 8002a30: 4629 mov r1, r5 + 8002a32: 4632 mov r2, r6 + 8002a34: f04f 0300 mov.w r3, #0 + 8002a38: f04f 0400 mov.w r4, #0 + 8002a3c: 0154 lsls r4, r2, #5 + 8002a3e: ea44 64d1 orr.w r4, r4, r1, lsr #27 + 8002a42: 014b lsls r3, r1, #5 + 8002a44: 4619 mov r1, r3 + 8002a46: 4622 mov r2, r4 + 8002a48: 1b49 subs r1, r1, r5 + 8002a4a: eb62 0206 sbc.w r2, r2, r6 + 8002a4e: f04f 0300 mov.w r3, #0 + 8002a52: f04f 0400 mov.w r4, #0 + 8002a56: 0194 lsls r4, r2, #6 + 8002a58: ea44 6491 orr.w r4, r4, r1, lsr #26 + 8002a5c: 018b lsls r3, r1, #6 + 8002a5e: 1a5b subs r3, r3, r1 + 8002a60: eb64 0402 sbc.w r4, r4, r2 + 8002a64: f04f 0100 mov.w r1, #0 + 8002a68: f04f 0200 mov.w r2, #0 + 8002a6c: 00e2 lsls r2, r4, #3 + 8002a6e: ea42 7253 orr.w r2, r2, r3, lsr #29 + 8002a72: 00d9 lsls r1, r3, #3 + 8002a74: 460b mov r3, r1 + 8002a76: 4614 mov r4, r2 + 8002a78: 195b adds r3, r3, r5 + 8002a7a: eb44 0406 adc.w r4, r4, r6 + 8002a7e: f04f 0100 mov.w r1, #0 + 8002a82: f04f 0200 mov.w r2, #0 + 8002a86: 02a2 lsls r2, r4, #10 + 8002a88: ea42 5293 orr.w r2, r2, r3, lsr #22 + 8002a8c: 0299 lsls r1, r3, #10 + 8002a8e: 460b mov r3, r1 + 8002a90: 4614 mov r4, r2 + 8002a92: 4618 mov r0, r3 + 8002a94: 4621 mov r1, r4 + 8002a96: 687b ldr r3, [r7, #4] + 8002a98: f04f 0400 mov.w r4, #0 + 8002a9c: 461a mov r2, r3 + 8002a9e: 4623 mov r3, r4 + 8002aa0: f7fd fbca bl 8000238 <__aeabi_uldivmod> + 8002aa4: 4603 mov r3, r0 + 8002aa6: 460c mov r4, r1 + 8002aa8: 60fb str r3, [r7, #12] + } + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2); + 8002aaa: 4b0b ldr r3, [pc, #44] ; (8002ad8 ) + 8002aac: 685b ldr r3, [r3, #4] + 8002aae: 0c1b lsrs r3, r3, #16 + 8002ab0: f003 0303 and.w r3, r3, #3 + 8002ab4: 3301 adds r3, #1 + 8002ab6: 005b lsls r3, r3, #1 + 8002ab8: 603b str r3, [r7, #0] + + sysclockfreq = pllvco/pllp; + 8002aba: 68fa ldr r2, [r7, #12] + 8002abc: 683b ldr r3, [r7, #0] + 8002abe: fbb2 f3f3 udiv r3, r2, r3 + 8002ac2: 60bb str r3, [r7, #8] + break; + 8002ac4: e002 b.n 8002acc + } + default: + { + sysclockfreq = HSI_VALUE; + 8002ac6: 4b05 ldr r3, [pc, #20] ; (8002adc ) + 8002ac8: 60bb str r3, [r7, #8] + break; + 8002aca: bf00 nop + } + } + return sysclockfreq; + 8002acc: 68bb ldr r3, [r7, #8] +} + 8002ace: 4618 mov r0, r3 + 8002ad0: 3714 adds r7, #20 + 8002ad2: 46bd mov sp, r7 + 8002ad4: bdf0 pop {r4, r5, r6, r7, pc} + 8002ad6: bf00 nop + 8002ad8: 40023800 .word 0x40023800 + 8002adc: 00f42400 .word 0x00f42400 + 8002ae0: 017d7840 .word 0x017d7840 + +08002ae4 : + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + 8002ae4: b480 push {r7} + 8002ae6: af00 add r7, sp, #0 + return SystemCoreClock; + 8002ae8: 4b03 ldr r3, [pc, #12] ; (8002af8 ) + 8002aea: 681b ldr r3, [r3, #0] +} + 8002aec: 4618 mov r0, r3 + 8002aee: 46bd mov sp, r7 + 8002af0: f85d 7b04 ldr.w r7, [sp], #4 + 8002af4: 4770 bx lr + 8002af6: bf00 nop + 8002af8: 20000004 .word 0x20000004 + +08002afc : + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + 8002afc: b580 push {r7, lr} + 8002afe: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]); + 8002b00: f7ff fff0 bl 8002ae4 + 8002b04: 4601 mov r1, r0 + 8002b06: 4b05 ldr r3, [pc, #20] ; (8002b1c ) + 8002b08: 689b ldr r3, [r3, #8] + 8002b0a: 0a9b lsrs r3, r3, #10 + 8002b0c: f003 0307 and.w r3, r3, #7 + 8002b10: 4a03 ldr r2, [pc, #12] ; (8002b20 ) + 8002b12: 5cd3 ldrb r3, [r2, r3] + 8002b14: fa21 f303 lsr.w r3, r1, r3 +} + 8002b18: 4618 mov r0, r3 + 8002b1a: bd80 pop {r7, pc} + 8002b1c: 40023800 .word 0x40023800 + 8002b20: 080054b4 .word 0x080054b4 + +08002b24 : + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + 8002b24: b580 push {r7, lr} + 8002b26: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]); + 8002b28: f7ff ffdc bl 8002ae4 + 8002b2c: 4601 mov r1, r0 + 8002b2e: 4b05 ldr r3, [pc, #20] ; (8002b44 ) + 8002b30: 689b ldr r3, [r3, #8] + 8002b32: 0b5b lsrs r3, r3, #13 + 8002b34: f003 0307 and.w r3, r3, #7 + 8002b38: 4a03 ldr r2, [pc, #12] ; (8002b48 ) + 8002b3a: 5cd3 ldrb r3, [r2, r3] + 8002b3c: fa21 f303 lsr.w r3, r1, r3 +} + 8002b40: 4618 mov r0, r3 + 8002b42: bd80 pop {r7, pc} + 8002b44: 40023800 .word 0x40023800 + 8002b48: 080054b4 .word 0x080054b4 + +08002b4c : + * the backup registers) are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + 8002b4c: b580 push {r7, lr} + 8002b4e: b088 sub sp, #32 + 8002b50: af00 add r7, sp, #0 + 8002b52: 6078 str r0, [r7, #4] + uint32_t tickstart = 0; + 8002b54: 2300 movs r3, #0 + 8002b56: 617b str r3, [r7, #20] + uint32_t tmpreg0 = 0; + 8002b58: 2300 movs r3, #0 + 8002b5a: 613b str r3, [r7, #16] + uint32_t tmpreg1 = 0; + 8002b5c: 2300 movs r3, #0 + 8002b5e: 60fb str r3, [r7, #12] + uint32_t plli2sused = 0; + 8002b60: 2300 movs r3, #0 + 8002b62: 61fb str r3, [r7, #28] + uint32_t pllsaiused = 0; + 8002b64: 2300 movs r3, #0 + 8002b66: 61bb str r3, [r7, #24] + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*----------------------------------- I2S configuration ----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + 8002b68: 687b ldr r3, [r7, #4] + 8002b6a: 681b ldr r3, [r3, #0] + 8002b6c: f003 0301 and.w r3, r3, #1 + 8002b70: 2b00 cmp r3, #0 + 8002b72: d012 beq.n 8002b9a + { + /* Check the parameters */ + assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + 8002b74: 4b69 ldr r3, [pc, #420] ; (8002d1c ) + 8002b76: 689b ldr r3, [r3, #8] + 8002b78: 4a68 ldr r2, [pc, #416] ; (8002d1c ) + 8002b7a: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 + 8002b7e: 6093 str r3, [r2, #8] + 8002b80: 4b66 ldr r3, [pc, #408] ; (8002d1c ) + 8002b82: 689a ldr r2, [r3, #8] + 8002b84: 687b ldr r3, [r7, #4] + 8002b86: 6b5b ldr r3, [r3, #52] ; 0x34 + 8002b88: 4964 ldr r1, [pc, #400] ; (8002d1c ) + 8002b8a: 4313 orrs r3, r2 + 8002b8c: 608b str r3, [r1, #8] + + /* Enable the PLLI2S when it's used as clock source for I2S */ + if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) + 8002b8e: 687b ldr r3, [r7, #4] + 8002b90: 6b5b ldr r3, [r3, #52] ; 0x34 + 8002b92: 2b00 cmp r3, #0 + 8002b94: d101 bne.n 8002b9a + { + plli2sused = 1; + 8002b96: 2301 movs r3, #1 + 8002b98: 61fb str r3, [r7, #28] + } + } + + /*------------------------------------ SAI1 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) + 8002b9a: 687b ldr r3, [r7, #4] + 8002b9c: 681b ldr r3, [r3, #0] + 8002b9e: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 8002ba2: 2b00 cmp r3, #0 + 8002ba4: d017 beq.n 8002bd6 + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + 8002ba6: 4b5d ldr r3, [pc, #372] ; (8002d1c ) + 8002ba8: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8002bac: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 + 8002bb0: 687b ldr r3, [r7, #4] + 8002bb2: 6bdb ldr r3, [r3, #60] ; 0x3c + 8002bb4: 4959 ldr r1, [pc, #356] ; (8002d1c ) + 8002bb6: 4313 orrs r3, r2 + 8002bb8: f8c1 308c str.w r3, [r1, #140] ; 0x8c + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) + 8002bbc: 687b ldr r3, [r7, #4] + 8002bbe: 6bdb ldr r3, [r3, #60] ; 0x3c + 8002bc0: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 8002bc4: d101 bne.n 8002bca + { + plli2sused = 1; + 8002bc6: 2301 movs r3, #1 + 8002bc8: 61fb str r3, [r7, #28] + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) + 8002bca: 687b ldr r3, [r7, #4] + 8002bcc: 6bdb ldr r3, [r3, #60] ; 0x3c + 8002bce: 2b00 cmp r3, #0 + 8002bd0: d101 bne.n 8002bd6 + { + pllsaiused = 1; + 8002bd2: 2301 movs r3, #1 + 8002bd4: 61bb str r3, [r7, #24] + } + } + + /*------------------------------------ SAI2 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) + 8002bd6: 687b ldr r3, [r7, #4] + 8002bd8: 681b ldr r3, [r3, #0] + 8002bda: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8002bde: 2b00 cmp r3, #0 + 8002be0: d017 beq.n 8002c12 + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + + /* Configure SAI2 Clock source */ + __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + 8002be2: 4b4e ldr r3, [pc, #312] ; (8002d1c ) + 8002be4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8002be8: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 + 8002bec: 687b ldr r3, [r7, #4] + 8002bee: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002bf0: 494a ldr r1, [pc, #296] ; (8002d1c ) + 8002bf2: 4313 orrs r3, r2 + 8002bf4: f8c1 308c str.w r3, [r1, #140] ; 0x8c + + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) + 8002bf8: 687b ldr r3, [r7, #4] + 8002bfa: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002bfc: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 8002c00: d101 bne.n 8002c06 + { + plli2sused = 1; + 8002c02: 2301 movs r3, #1 + 8002c04: 61fb str r3, [r7, #28] + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) + 8002c06: 687b ldr r3, [r7, #4] + 8002c08: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002c0a: 2b00 cmp r3, #0 + 8002c0c: d101 bne.n 8002c12 + { + pllsaiused = 1; + 8002c0e: 2301 movs r3, #1 + 8002c10: 61bb str r3, [r7, #24] + } + } + + /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + 8002c12: 687b ldr r3, [r7, #4] + 8002c14: 681b ldr r3, [r3, #0] + 8002c16: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 8002c1a: 2b00 cmp r3, #0 + 8002c1c: d001 beq.n 8002c22 + { + plli2sused = 1; + 8002c1e: 2301 movs r3, #1 + 8002c20: 61fb str r3, [r7, #28] + } + + /*------------------------------------ RTC configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + 8002c22: 687b ldr r3, [r7, #4] + 8002c24: 681b ldr r3, [r3, #0] + 8002c26: f003 0320 and.w r3, r3, #32 + 8002c2a: 2b00 cmp r3, #0 + 8002c2c: f000 808b beq.w 8002d46 + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + 8002c30: 4b3a ldr r3, [pc, #232] ; (8002d1c ) + 8002c32: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002c34: 4a39 ldr r2, [pc, #228] ; (8002d1c ) + 8002c36: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8002c3a: 6413 str r3, [r2, #64] ; 0x40 + 8002c3c: 4b37 ldr r3, [pc, #220] ; (8002d1c ) + 8002c3e: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002c40: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8002c44: 60bb str r3, [r7, #8] + 8002c46: 68bb ldr r3, [r7, #8] + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + 8002c48: 4b35 ldr r3, [pc, #212] ; (8002d20 ) + 8002c4a: 681b ldr r3, [r3, #0] + 8002c4c: 4a34 ldr r2, [pc, #208] ; (8002d20 ) + 8002c4e: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8002c52: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002c54: f7ff f81e bl 8001c94 + 8002c58: 6178 str r0, [r7, #20] + + /* Wait for Backup domain Write protection disable */ + while((PWR->CR1 & PWR_CR1_DBP) == RESET) + 8002c5a: e008 b.n 8002c6e + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8002c5c: f7ff f81a bl 8001c94 + 8002c60: 4602 mov r2, r0 + 8002c62: 697b ldr r3, [r7, #20] + 8002c64: 1ad3 subs r3, r2, r3 + 8002c66: 2b64 cmp r3, #100 ; 0x64 + 8002c68: d901 bls.n 8002c6e + { + return HAL_TIMEOUT; + 8002c6a: 2303 movs r3, #3 + 8002c6c: e38d b.n 800338a + while((PWR->CR1 & PWR_CR1_DBP) == RESET) + 8002c6e: 4b2c ldr r3, [pc, #176] ; (8002d20 ) + 8002c70: 681b ldr r3, [r3, #0] + 8002c72: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002c76: 2b00 cmp r3, #0 + 8002c78: d0f0 beq.n 8002c5c + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); + 8002c7a: 4b28 ldr r3, [pc, #160] ; (8002d1c ) + 8002c7c: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002c7e: f403 7340 and.w r3, r3, #768 ; 0x300 + 8002c82: 613b str r3, [r7, #16] + + if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + 8002c84: 693b ldr r3, [r7, #16] + 8002c86: 2b00 cmp r3, #0 + 8002c88: d035 beq.n 8002cf6 + 8002c8a: 687b ldr r3, [r7, #4] + 8002c8c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002c8e: f403 7340 and.w r3, r3, #768 ; 0x300 + 8002c92: 693a ldr r2, [r7, #16] + 8002c94: 429a cmp r2, r3 + 8002c96: d02e beq.n 8002cf6 + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + 8002c98: 4b20 ldr r3, [pc, #128] ; (8002d1c ) + 8002c9a: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002c9c: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8002ca0: 613b str r3, [r7, #16] + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + 8002ca2: 4b1e ldr r3, [pc, #120] ; (8002d1c ) + 8002ca4: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002ca6: 4a1d ldr r2, [pc, #116] ; (8002d1c ) + 8002ca8: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8002cac: 6713 str r3, [r2, #112] ; 0x70 + __HAL_RCC_BACKUPRESET_RELEASE(); + 8002cae: 4b1b ldr r3, [pc, #108] ; (8002d1c ) + 8002cb0: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002cb2: 4a1a ldr r2, [pc, #104] ; (8002d1c ) + 8002cb4: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8002cb8: 6713 str r3, [r2, #112] ; 0x70 + + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg0; + 8002cba: 4a18 ldr r2, [pc, #96] ; (8002d1c ) + 8002cbc: 693b ldr r3, [r7, #16] + 8002cbe: 6713 str r3, [r2, #112] ; 0x70 + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + 8002cc0: 4b16 ldr r3, [pc, #88] ; (8002d1c ) + 8002cc2: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002cc4: f003 0301 and.w r3, r3, #1 + 8002cc8: 2b01 cmp r3, #1 + 8002cca: d114 bne.n 8002cf6 + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8002ccc: f7fe ffe2 bl 8001c94 + 8002cd0: 6178 str r0, [r7, #20] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8002cd2: e00a b.n 8002cea + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8002cd4: f7fe ffde bl 8001c94 + 8002cd8: 4602 mov r2, r0 + 8002cda: 697b ldr r3, [r7, #20] + 8002cdc: 1ad3 subs r3, r2, r3 + 8002cde: f241 3288 movw r2, #5000 ; 0x1388 + 8002ce2: 4293 cmp r3, r2 + 8002ce4: d901 bls.n 8002cea + { + return HAL_TIMEOUT; + 8002ce6: 2303 movs r3, #3 + 8002ce8: e34f b.n 800338a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8002cea: 4b0c ldr r3, [pc, #48] ; (8002d1c ) + 8002cec: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002cee: f003 0302 and.w r3, r3, #2 + 8002cf2: 2b00 cmp r3, #0 + 8002cf4: d0ee beq.n 8002cd4 + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 8002cf6: 687b ldr r3, [r7, #4] + 8002cf8: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002cfa: f403 7340 and.w r3, r3, #768 ; 0x300 + 8002cfe: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 8002d02: d111 bne.n 8002d28 + 8002d04: 4b05 ldr r3, [pc, #20] ; (8002d1c ) + 8002d06: 689b ldr r3, [r3, #8] + 8002d08: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000 + 8002d0c: 687b ldr r3, [r7, #4] + 8002d0e: 6b19 ldr r1, [r3, #48] ; 0x30 + 8002d10: 4b04 ldr r3, [pc, #16] ; (8002d24 ) + 8002d12: 400b ands r3, r1 + 8002d14: 4901 ldr r1, [pc, #4] ; (8002d1c ) + 8002d16: 4313 orrs r3, r2 + 8002d18: 608b str r3, [r1, #8] + 8002d1a: e00b b.n 8002d34 + 8002d1c: 40023800 .word 0x40023800 + 8002d20: 40007000 .word 0x40007000 + 8002d24: 0ffffcff .word 0x0ffffcff + 8002d28: 4bb3 ldr r3, [pc, #716] ; (8002ff8 ) + 8002d2a: 689b ldr r3, [r3, #8] + 8002d2c: 4ab2 ldr r2, [pc, #712] ; (8002ff8 ) + 8002d2e: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000 + 8002d32: 6093 str r3, [r2, #8] + 8002d34: 4bb0 ldr r3, [pc, #704] ; (8002ff8 ) + 8002d36: 6f1a ldr r2, [r3, #112] ; 0x70 + 8002d38: 687b ldr r3, [r7, #4] + 8002d3a: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002d3c: f3c3 030b ubfx r3, r3, #0, #12 + 8002d40: 49ad ldr r1, [pc, #692] ; (8002ff8 ) + 8002d42: 4313 orrs r3, r2 + 8002d44: 670b str r3, [r1, #112] ; 0x70 + } + + /*------------------------------------ TIM configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + 8002d46: 687b ldr r3, [r7, #4] + 8002d48: 681b ldr r3, [r3, #0] + 8002d4a: f003 0310 and.w r3, r3, #16 + 8002d4e: 2b00 cmp r3, #0 + 8002d50: d010 beq.n 8002d74 + { + /* Check the parameters */ + assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + 8002d52: 4ba9 ldr r3, [pc, #676] ; (8002ff8 ) + 8002d54: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8002d58: 4aa7 ldr r2, [pc, #668] ; (8002ff8 ) + 8002d5a: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 8002d5e: f8c2 308c str.w r3, [r2, #140] ; 0x8c + 8002d62: 4ba5 ldr r3, [pc, #660] ; (8002ff8 ) + 8002d64: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c + 8002d68: 687b ldr r3, [r7, #4] + 8002d6a: 6b9b ldr r3, [r3, #56] ; 0x38 + 8002d6c: 49a2 ldr r1, [pc, #648] ; (8002ff8 ) + 8002d6e: 4313 orrs r3, r2 + 8002d70: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } + + /*-------------------------------------- I2C1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 8002d74: 687b ldr r3, [r7, #4] + 8002d76: 681b ldr r3, [r3, #0] + 8002d78: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8002d7c: 2b00 cmp r3, #0 + 8002d7e: d00a beq.n 8002d96 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 8002d80: 4b9d ldr r3, [pc, #628] ; (8002ff8 ) + 8002d82: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002d86: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 8002d8a: 687b ldr r3, [r7, #4] + 8002d8c: 6e5b ldr r3, [r3, #100] ; 0x64 + 8002d8e: 499a ldr r1, [pc, #616] ; (8002ff8 ) + 8002d90: 4313 orrs r3, r2 + 8002d92: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- I2C2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + 8002d96: 687b ldr r3, [r7, #4] + 8002d98: 681b ldr r3, [r3, #0] + 8002d9a: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 8002d9e: 2b00 cmp r3, #0 + 8002da0: d00a beq.n 8002db8 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + 8002da2: 4b95 ldr r3, [pc, #596] ; (8002ff8 ) + 8002da4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002da8: f423 2240 bic.w r2, r3, #786432 ; 0xc0000 + 8002dac: 687b ldr r3, [r7, #4] + 8002dae: 6e9b ldr r3, [r3, #104] ; 0x68 + 8002db0: 4991 ldr r1, [pc, #580] ; (8002ff8 ) + 8002db2: 4313 orrs r3, r2 + 8002db4: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- I2C3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + 8002db8: 687b ldr r3, [r7, #4] + 8002dba: 681b ldr r3, [r3, #0] + 8002dbc: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8002dc0: 2b00 cmp r3, #0 + 8002dc2: d00a beq.n 8002dda + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + 8002dc4: 4b8c ldr r3, [pc, #560] ; (8002ff8 ) + 8002dc6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002dca: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 + 8002dce: 687b ldr r3, [r7, #4] + 8002dd0: 6edb ldr r3, [r3, #108] ; 0x6c + 8002dd2: 4989 ldr r1, [pc, #548] ; (8002ff8 ) + 8002dd4: 4313 orrs r3, r2 + 8002dd6: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- I2C4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) + 8002dda: 687b ldr r3, [r7, #4] + 8002ddc: 681b ldr r3, [r3, #0] + 8002dde: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002de2: 2b00 cmp r3, #0 + 8002de4: d00a beq.n 8002dfc + { + /* Check the parameters */ + assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); + + /* Configure the I2C4 clock source */ + __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); + 8002de6: 4b84 ldr r3, [pc, #528] ; (8002ff8 ) + 8002de8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002dec: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 + 8002df0: 687b ldr r3, [r7, #4] + 8002df2: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002df4: 4980 ldr r1, [pc, #512] ; (8002ff8 ) + 8002df6: 4313 orrs r3, r2 + 8002df8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 8002dfc: 687b ldr r3, [r7, #4] + 8002dfe: 681b ldr r3, [r3, #0] + 8002e00: f003 0340 and.w r3, r3, #64 ; 0x40 + 8002e04: 2b00 cmp r3, #0 + 8002e06: d00a beq.n 8002e1e + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 8002e08: 4b7b ldr r3, [pc, #492] ; (8002ff8 ) + 8002e0a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002e0e: f023 0203 bic.w r2, r3, #3 + 8002e12: 687b ldr r3, [r7, #4] + 8002e14: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002e16: 4978 ldr r1, [pc, #480] ; (8002ff8 ) + 8002e18: 4313 orrs r3, r2 + 8002e1a: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 8002e1e: 687b ldr r3, [r7, #4] + 8002e20: 681b ldr r3, [r3, #0] + 8002e22: f003 0380 and.w r3, r3, #128 ; 0x80 + 8002e26: 2b00 cmp r3, #0 + 8002e28: d00a beq.n 8002e40 + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 8002e2a: 4b73 ldr r3, [pc, #460] ; (8002ff8 ) + 8002e2c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002e30: f023 020c bic.w r2, r3, #12 + 8002e34: 687b ldr r3, [r7, #4] + 8002e36: 6c9b ldr r3, [r3, #72] ; 0x48 + 8002e38: 496f ldr r1, [pc, #444] ; (8002ff8 ) + 8002e3a: 4313 orrs r3, r2 + 8002e3c: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + 8002e40: 687b ldr r3, [r7, #4] + 8002e42: 681b ldr r3, [r3, #0] + 8002e44: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002e48: 2b00 cmp r3, #0 + 8002e4a: d00a beq.n 8002e62 + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + 8002e4c: 4b6a ldr r3, [pc, #424] ; (8002ff8 ) + 8002e4e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002e52: f023 0230 bic.w r2, r3, #48 ; 0x30 + 8002e56: 687b ldr r3, [r7, #4] + 8002e58: 6cdb ldr r3, [r3, #76] ; 0x4c + 8002e5a: 4967 ldr r1, [pc, #412] ; (8002ff8 ) + 8002e5c: 4313 orrs r3, r2 + 8002e5e: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + 8002e62: 687b ldr r3, [r7, #4] + 8002e64: 681b ldr r3, [r3, #0] + 8002e66: f403 7300 and.w r3, r3, #512 ; 0x200 + 8002e6a: 2b00 cmp r3, #0 + 8002e6c: d00a beq.n 8002e84 + { + /* Check the parameters */ + assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); + + /* Configure the UART4 clock source */ + __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); + 8002e6e: 4b62 ldr r3, [pc, #392] ; (8002ff8 ) + 8002e70: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002e74: f023 02c0 bic.w r2, r3, #192 ; 0xc0 + 8002e78: 687b ldr r3, [r7, #4] + 8002e7a: 6d1b ldr r3, [r3, #80] ; 0x50 + 8002e7c: 495e ldr r1, [pc, #376] ; (8002ff8 ) + 8002e7e: 4313 orrs r3, r2 + 8002e80: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART5 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + 8002e84: 687b ldr r3, [r7, #4] + 8002e86: 681b ldr r3, [r3, #0] + 8002e88: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8002e8c: 2b00 cmp r3, #0 + 8002e8e: d00a beq.n 8002ea6 + { + /* Check the parameters */ + assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); + + /* Configure the UART5 clock source */ + __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); + 8002e90: 4b59 ldr r3, [pc, #356] ; (8002ff8 ) + 8002e92: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002e96: f423 7240 bic.w r2, r3, #768 ; 0x300 + 8002e9a: 687b ldr r3, [r7, #4] + 8002e9c: 6d5b ldr r3, [r3, #84] ; 0x54 + 8002e9e: 4956 ldr r1, [pc, #344] ; (8002ff8 ) + 8002ea0: 4313 orrs r3, r2 + 8002ea2: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART6 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) + 8002ea6: 687b ldr r3, [r7, #4] + 8002ea8: 681b ldr r3, [r3, #0] + 8002eaa: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8002eae: 2b00 cmp r3, #0 + 8002eb0: d00a beq.n 8002ec8 + { + /* Check the parameters */ + assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); + + /* Configure the USART6 clock source */ + __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); + 8002eb2: 4b51 ldr r3, [pc, #324] ; (8002ff8 ) + 8002eb4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002eb8: f423 6240 bic.w r2, r3, #3072 ; 0xc00 + 8002ebc: 687b ldr r3, [r7, #4] + 8002ebe: 6d9b ldr r3, [r3, #88] ; 0x58 + 8002ec0: 494d ldr r1, [pc, #308] ; (8002ff8 ) + 8002ec2: 4313 orrs r3, r2 + 8002ec4: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART7 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) + 8002ec8: 687b ldr r3, [r7, #4] + 8002eca: 681b ldr r3, [r3, #0] + 8002ecc: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8002ed0: 2b00 cmp r3, #0 + 8002ed2: d00a beq.n 8002eea + { + /* Check the parameters */ + assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); + + /* Configure the UART7 clock source */ + __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); + 8002ed4: 4b48 ldr r3, [pc, #288] ; (8002ff8 ) + 8002ed6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002eda: f423 5240 bic.w r2, r3, #12288 ; 0x3000 + 8002ede: 687b ldr r3, [r7, #4] + 8002ee0: 6ddb ldr r3, [r3, #92] ; 0x5c + 8002ee2: 4945 ldr r1, [pc, #276] ; (8002ff8 ) + 8002ee4: 4313 orrs r3, r2 + 8002ee6: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART8 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) + 8002eea: 687b ldr r3, [r7, #4] + 8002eec: 681b ldr r3, [r3, #0] + 8002eee: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8002ef2: 2b00 cmp r3, #0 + 8002ef4: d00a beq.n 8002f0c + { + /* Check the parameters */ + assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); + + /* Configure the UART8 clock source */ + __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); + 8002ef6: 4b40 ldr r3, [pc, #256] ; (8002ff8 ) + 8002ef8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002efc: f423 4240 bic.w r2, r3, #49152 ; 0xc000 + 8002f00: 687b ldr r3, [r7, #4] + 8002f02: 6e1b ldr r3, [r3, #96] ; 0x60 + 8002f04: 493c ldr r1, [pc, #240] ; (8002ff8 ) + 8002f06: 4313 orrs r3, r2 + 8002f08: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*--------------------------------------- CEC Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + 8002f0c: 687b ldr r3, [r7, #4] + 8002f0e: 681b ldr r3, [r3, #0] + 8002f10: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8002f14: 2b00 cmp r3, #0 + 8002f16: d00a beq.n 8002f2e + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + 8002f18: 4b37 ldr r3, [pc, #220] ; (8002ff8 ) + 8002f1a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002f1e: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 + 8002f22: 687b ldr r3, [r7, #4] + 8002f24: 6f9b ldr r3, [r3, #120] ; 0x78 + 8002f26: 4934 ldr r1, [pc, #208] ; (8002ff8 ) + 8002f28: 4313 orrs r3, r2 + 8002f2a: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- CK48 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + 8002f2e: 687b ldr r3, [r7, #4] + 8002f30: 681b ldr r3, [r3, #0] + 8002f32: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8002f36: 2b00 cmp r3, #0 + 8002f38: d011 beq.n 8002f5e + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + 8002f3a: 4b2f ldr r3, [pc, #188] ; (8002ff8 ) + 8002f3c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002f40: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000 + 8002f44: 687b ldr r3, [r7, #4] + 8002f46: 6fdb ldr r3, [r3, #124] ; 0x7c + 8002f48: 492b ldr r1, [pc, #172] ; (8002ff8 ) + 8002f4a: 4313 orrs r3, r2 + 8002f4c: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + + /* Enable the PLLSAI when it's used as clock source for CK48 */ + if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) + 8002f50: 687b ldr r3, [r7, #4] + 8002f52: 6fdb ldr r3, [r3, #124] ; 0x7c + 8002f54: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 + 8002f58: d101 bne.n 8002f5e + { + pllsaiused = 1; + 8002f5a: 2301 movs r3, #1 + 8002f5c: 61bb str r3, [r7, #24] + } + } + + /*-------------------------------------- LTDC Configuration -----------------------------------*/ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + 8002f5e: 687b ldr r3, [r7, #4] + 8002f60: 681b ldr r3, [r3, #0] + 8002f62: f003 0308 and.w r3, r3, #8 + 8002f66: 2b00 cmp r3, #0 + 8002f68: d001 beq.n 8002f6e + { + pllsaiused = 1; + 8002f6a: 2301 movs r3, #1 + 8002f6c: 61bb str r3, [r7, #24] + } +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + 8002f6e: 687b ldr r3, [r7, #4] + 8002f70: 681b ldr r3, [r3, #0] + 8002f72: f403 2380 and.w r3, r3, #262144 ; 0x40000 + 8002f76: 2b00 cmp r3, #0 + 8002f78: d00a beq.n 8002f90 + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LTPIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + 8002f7a: 4b1f ldr r3, [pc, #124] ; (8002ff8 ) + 8002f7c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002f80: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000 + 8002f84: 687b ldr r3, [r7, #4] + 8002f86: 6f5b ldr r3, [r3, #116] ; 0x74 + 8002f88: 491b ldr r1, [pc, #108] ; (8002ff8 ) + 8002f8a: 4313 orrs r3, r2 + 8002f8c: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) + 8002f90: 687b ldr r3, [r7, #4] + 8002f92: 681b ldr r3, [r3, #0] + 8002f94: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 8002f98: 2b00 cmp r3, #0 + 8002f9a: d00b beq.n 8002fb4 + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); + + /* Configure the SDMMC1 clock source */ + __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); + 8002f9c: 4b16 ldr r3, [pc, #88] ; (8002ff8 ) + 8002f9e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002fa2: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000 + 8002fa6: 687b ldr r3, [r7, #4] + 8002fa8: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 8002fac: 4912 ldr r1, [pc, #72] ; (8002ff8 ) + 8002fae: 4313 orrs r3, r2 + 8002fb0: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) + 8002fb4: 687b ldr r3, [r7, #4] + 8002fb6: 681b ldr r3, [r3, #0] + 8002fb8: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 8002fbc: 2b00 cmp r3, #0 + 8002fbe: d00b beq.n 8002fd8 + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); + + /* Configure the SDMMC2 clock source */ + __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); + 8002fc0: 4b0d ldr r3, [pc, #52] ; (8002ff8 ) + 8002fc2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002fc6: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000 + 8002fca: 687b ldr r3, [r7, #4] + 8002fcc: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8002fd0: 4909 ldr r1, [pc, #36] ; (8002ff8 ) + 8002fd2: 4313 orrs r3, r2 + 8002fd4: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*------------------------------------- DFSDM1 Configuration -------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) + 8002fd8: 687b ldr r3, [r7, #4] + 8002fda: 681b ldr r3, [r3, #0] + 8002fdc: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 8002fe0: 2b00 cmp r3, #0 + 8002fe2: d00f beq.n 8003004 + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); + + /* Configure the DFSDM1 interface clock source */ + __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); + 8002fe4: 4b04 ldr r3, [pc, #16] ; (8002ff8 ) + 8002fe6: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8002fea: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000 + 8002fee: 687b ldr r3, [r7, #4] + 8002ff0: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8002ff4: e002 b.n 8002ffc + 8002ff6: bf00 nop + 8002ff8: 40023800 .word 0x40023800 + 8002ffc: 4985 ldr r1, [pc, #532] ; (8003214 ) + 8002ffe: 4313 orrs r3, r2 + 8003000: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } + + /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) + 8003004: 687b ldr r3, [r7, #4] + 8003006: 681b ldr r3, [r3, #0] + 8003008: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 800300c: 2b00 cmp r3, #0 + 800300e: d00b beq.n 8003028 + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); + + /* Configure the DFSDM interface clock source */ + __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); + 8003010: 4b80 ldr r3, [pc, #512] ; (8003214 ) + 8003012: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8003016: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 + 800301a: 687b ldr r3, [r7, #4] + 800301c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8003020: 497c ldr r1, [pc, #496] ; (8003214 ) + 8003022: 4313 orrs r3, r2 + 8003024: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + + /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ + /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ + if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) + 8003028: 69fb ldr r3, [r7, #28] + 800302a: 2b01 cmp r3, #1 + 800302c: d005 beq.n 800303a + 800302e: 687b ldr r3, [r7, #4] + 8003030: 681b ldr r3, [r3, #0] + 8003032: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 + 8003036: f040 80d6 bne.w 80031e6 + { + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + 800303a: 4b76 ldr r3, [pc, #472] ; (8003214 ) + 800303c: 681b ldr r3, [r3, #0] + 800303e: 4a75 ldr r2, [pc, #468] ; (8003214 ) + 8003040: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 + 8003044: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003046: f7fe fe25 bl 8001c94 + 800304a: 6178 str r0, [r7, #20] + + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + 800304c: e008 b.n 8003060 + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + 800304e: f7fe fe21 bl 8001c94 + 8003052: 4602 mov r2, r0 + 8003054: 697b ldr r3, [r7, #20] + 8003056: 1ad3 subs r3, r2, r3 + 8003058: 2b64 cmp r3, #100 ; 0x64 + 800305a: d901 bls.n 8003060 + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 800305c: 2303 movs r3, #3 + 800305e: e194 b.n 800338a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + 8003060: 4b6c ldr r3, [pc, #432] ; (8003214 ) + 8003062: 681b ldr r3, [r3, #0] + 8003064: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 8003068: 2b00 cmp r3, #0 + 800306a: d1f0 bne.n 800304e + + /* check for common PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) + 800306c: 687b ldr r3, [r7, #4] + 800306e: 681b ldr r3, [r3, #0] + 8003070: f003 0301 and.w r3, r3, #1 + 8003074: 2b00 cmp r3, #0 + 8003076: d021 beq.n 80030bc + 8003078: 687b ldr r3, [r7, #4] + 800307a: 6b5b ldr r3, [r3, #52] ; 0x34 + 800307c: 2b00 cmp r3, #0 + 800307e: d11d bne.n 80030bc + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + 8003080: 4b64 ldr r3, [pc, #400] ; (8003214 ) + 8003082: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8003086: 0c1b lsrs r3, r3, #16 + 8003088: f003 0303 and.w r3, r3, #3 + 800308c: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + 800308e: 4b61 ldr r3, [pc, #388] ; (8003214 ) + 8003090: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8003094: 0e1b lsrs r3, r3, #24 + 8003096: f003 030f and.w r3, r3, #15 + 800309a: 60fb str r3, [r7, #12] + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR); + 800309c: 687b ldr r3, [r7, #4] + 800309e: 685b ldr r3, [r3, #4] + 80030a0: 019a lsls r2, r3, #6 + 80030a2: 693b ldr r3, [r7, #16] + 80030a4: 041b lsls r3, r3, #16 + 80030a6: 431a orrs r2, r3 + 80030a8: 68fb ldr r3, [r7, #12] + 80030aa: 061b lsls r3, r3, #24 + 80030ac: 431a orrs r2, r3 + 80030ae: 687b ldr r3, [r7, #4] + 80030b0: 689b ldr r3, [r3, #8] + 80030b2: 071b lsls r3, r3, #28 + 80030b4: 4957 ldr r1, [pc, #348] ; (8003214 ) + 80030b6: 4313 orrs r3, r2 + 80030b8: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + } + + /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + 80030bc: 687b ldr r3, [r7, #4] + 80030be: 681b ldr r3, [r3, #0] + 80030c0: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 80030c4: 2b00 cmp r3, #0 + 80030c6: d004 beq.n 80030d2 + 80030c8: 687b ldr r3, [r7, #4] + 80030ca: 6bdb ldr r3, [r3, #60] ; 0x3c + 80030cc: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 80030d0: d00a beq.n 80030e8 + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + 80030d2: 687b ldr r3, [r7, #4] + 80030d4: 681b ldr r3, [r3, #0] + 80030d6: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + 80030da: 2b00 cmp r3, #0 + 80030dc: d02e beq.n 800313c + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + 80030de: 687b ldr r3, [r7, #4] + 80030e0: 6c1b ldr r3, [r3, #64] ; 0x40 + 80030e2: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 80030e6: d129 bne.n 800313c + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + /* Check for PLLI2S/DIVQ parameters */ + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + 80030e8: 4b4a ldr r3, [pc, #296] ; (8003214 ) + 80030ea: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 80030ee: 0c1b lsrs r3, r3, #16 + 80030f0: f003 0303 and.w r3, r3, #3 + 80030f4: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + 80030f6: 4b47 ldr r3, [pc, #284] ; (8003214 ) + 80030f8: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 80030fc: 0f1b lsrs r3, r3, #28 + 80030fe: f003 0307 and.w r3, r3, #7 + 8003102: 60fb str r3, [r7, #12] + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); + 8003104: 687b ldr r3, [r7, #4] + 8003106: 685b ldr r3, [r3, #4] + 8003108: 019a lsls r2, r3, #6 + 800310a: 693b ldr r3, [r7, #16] + 800310c: 041b lsls r3, r3, #16 + 800310e: 431a orrs r2, r3 + 8003110: 687b ldr r3, [r7, #4] + 8003112: 68db ldr r3, [r3, #12] + 8003114: 061b lsls r3, r3, #24 + 8003116: 431a orrs r2, r3 + 8003118: 68fb ldr r3, [r7, #12] + 800311a: 071b lsls r3, r3, #28 + 800311c: 493d ldr r1, [pc, #244] ; (8003214 ) + 800311e: 4313 orrs r3, r2 + 8003120: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + 8003124: 4b3b ldr r3, [pc, #236] ; (8003214 ) + 8003126: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 800312a: f023 021f bic.w r2, r3, #31 + 800312e: 687b ldr r3, [r7, #4] + 8003130: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003132: 3b01 subs r3, #1 + 8003134: 4937 ldr r1, [pc, #220] ; (8003214 ) + 8003136: 4313 orrs r3, r2 + 8003138: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } + + /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + 800313c: 687b ldr r3, [r7, #4] + 800313e: 681b ldr r3, [r3, #0] + 8003140: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 8003144: 2b00 cmp r3, #0 + 8003146: d01d beq.n 8003184 + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + 8003148: 4b32 ldr r3, [pc, #200] ; (8003214 ) + 800314a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800314e: 0e1b lsrs r3, r3, #24 + 8003150: f003 030f and.w r3, r3, #15 + 8003154: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + 8003156: 4b2f ldr r3, [pc, #188] ; (8003214 ) + 8003158: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800315c: 0f1b lsrs r3, r3, #28 + 800315e: f003 0307 and.w r3, r3, #7 + 8003162: 60fb str r3, [r7, #12] + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1); + 8003164: 687b ldr r3, [r7, #4] + 8003166: 685b ldr r3, [r3, #4] + 8003168: 019a lsls r2, r3, #6 + 800316a: 687b ldr r3, [r7, #4] + 800316c: 691b ldr r3, [r3, #16] + 800316e: 041b lsls r3, r3, #16 + 8003170: 431a orrs r2, r3 + 8003172: 693b ldr r3, [r7, #16] + 8003174: 061b lsls r3, r3, #24 + 8003176: 431a orrs r2, r3 + 8003178: 68fb ldr r3, [r7, #12] + 800317a: 071b lsls r3, r3, #28 + 800317c: 4925 ldr r1, [pc, #148] ; (8003214 ) + 800317e: 4313 orrs r3, r2 + 8003180: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + 8003184: 687b ldr r3, [r7, #4] + 8003186: 681b ldr r3, [r3, #0] + 8003188: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 800318c: 2b00 cmp r3, #0 + 800318e: d011 beq.n 80031b4 + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ + /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + 8003190: 687b ldr r3, [r7, #4] + 8003192: 685b ldr r3, [r3, #4] + 8003194: 019a lsls r2, r3, #6 + 8003196: 687b ldr r3, [r7, #4] + 8003198: 691b ldr r3, [r3, #16] + 800319a: 041b lsls r3, r3, #16 + 800319c: 431a orrs r2, r3 + 800319e: 687b ldr r3, [r7, #4] + 80031a0: 68db ldr r3, [r3, #12] + 80031a2: 061b lsls r3, r3, #24 + 80031a4: 431a orrs r2, r3 + 80031a6: 687b ldr r3, [r7, #4] + 80031a8: 689b ldr r3, [r3, #8] + 80031aa: 071b lsls r3, r3, #28 + 80031ac: 4919 ldr r1, [pc, #100] ; (8003214 ) + 80031ae: 4313 orrs r3, r2 + 80031b0: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + 80031b4: 4b17 ldr r3, [pc, #92] ; (8003214 ) + 80031b6: 681b ldr r3, [r3, #0] + 80031b8: 4a16 ldr r2, [pc, #88] ; (8003214 ) + 80031ba: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 + 80031be: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80031c0: f7fe fd68 bl 8001c94 + 80031c4: 6178 str r0, [r7, #20] + + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 80031c6: e008 b.n 80031da + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + 80031c8: f7fe fd64 bl 8001c94 + 80031cc: 4602 mov r2, r0 + 80031ce: 697b ldr r3, [r7, #20] + 80031d0: 1ad3 subs r3, r2, r3 + 80031d2: 2b64 cmp r3, #100 ; 0x64 + 80031d4: d901 bls.n 80031da + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 80031d6: 2303 movs r3, #3 + 80031d8: e0d7 b.n 800338a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 80031da: 4b0e ldr r3, [pc, #56] ; (8003214 ) + 80031dc: 681b ldr r3, [r3, #0] + 80031de: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 80031e2: 2b00 cmp r3, #0 + 80031e4: d0f0 beq.n 80031c8 + } + } + + /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ + /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ + if(pllsaiused == 1) + 80031e6: 69bb ldr r3, [r7, #24] + 80031e8: 2b01 cmp r3, #1 + 80031ea: f040 80cd bne.w 8003388 + { + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + 80031ee: 4b09 ldr r3, [pc, #36] ; (8003214 ) + 80031f0: 681b ldr r3, [r3, #0] + 80031f2: 4a08 ldr r2, [pc, #32] ; (8003214 ) + 80031f4: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 80031f8: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80031fa: f7fe fd4b bl 8001c94 + 80031fe: 6178 str r0, [r7, #20] + + /* Wait till PLLSAI is disabled */ + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + 8003200: e00a b.n 8003218 + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + 8003202: f7fe fd47 bl 8001c94 + 8003206: 4602 mov r2, r0 + 8003208: 697b ldr r3, [r7, #20] + 800320a: 1ad3 subs r3, r2, r3 + 800320c: 2b64 cmp r3, #100 ; 0x64 + 800320e: d903 bls.n 8003218 + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 8003210: 2303 movs r3, #3 + 8003212: e0ba b.n 800338a + 8003214: 40023800 .word 0x40023800 + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + 8003218: 4b5e ldr r3, [pc, #376] ; (8003394 ) + 800321a: 681b ldr r3, [r3, #0] + 800321c: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 8003220: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 8003224: d0ed beq.n 8003202 + + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ + 8003226: 687b ldr r3, [r7, #4] + 8003228: 681b ldr r3, [r3, #0] + 800322a: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 800322e: 2b00 cmp r3, #0 + 8003230: d003 beq.n 800323a + 8003232: 687b ldr r3, [r7, #4] + 8003234: 6bdb ldr r3, [r3, #60] ; 0x3c + 8003236: 2b00 cmp r3, #0 + 8003238: d009 beq.n 800324e + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + 800323a: 687b ldr r3, [r7, #4] + 800323c: 681b ldr r3, [r3, #0] + 800323e: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ + 8003242: 2b00 cmp r3, #0 + 8003244: d02e beq.n 80032a4 + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + 8003246: 687b ldr r3, [r7, #4] + 8003248: 6c1b ldr r3, [r3, #64] ; 0x40 + 800324a: 2b00 cmp r3, #0 + 800324c: d12a bne.n 80032a4 + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + /* check for PLLSAI/DIVQ Parameter */ + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + 800324e: 4b51 ldr r3, [pc, #324] ; (8003394 ) + 8003250: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8003254: 0c1b lsrs r3, r3, #16 + 8003256: f003 0303 and.w r3, r3, #3 + 800325a: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + 800325c: 4b4d ldr r3, [pc, #308] ; (8003394 ) + 800325e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8003262: 0f1b lsrs r3, r3, #28 + 8003264: f003 0307 and.w r3, r3, #7 + 8003268: 60fb str r3, [r7, #12] + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); + 800326a: 687b ldr r3, [r7, #4] + 800326c: 695b ldr r3, [r3, #20] + 800326e: 019a lsls r2, r3, #6 + 8003270: 693b ldr r3, [r7, #16] + 8003272: 041b lsls r3, r3, #16 + 8003274: 431a orrs r2, r3 + 8003276: 687b ldr r3, [r7, #4] + 8003278: 699b ldr r3, [r3, #24] + 800327a: 061b lsls r3, r3, #24 + 800327c: 431a orrs r2, r3 + 800327e: 68fb ldr r3, [r7, #12] + 8003280: 071b lsls r3, r3, #28 + 8003282: 4944 ldr r1, [pc, #272] ; (8003394 ) + 8003284: 4313 orrs r3, r2 + 8003286: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + 800328a: 4b42 ldr r3, [pc, #264] ; (8003394 ) + 800328c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8003290: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00 + 8003294: 687b ldr r3, [r7, #4] + 8003296: 6a9b ldr r3, [r3, #40] ; 0x28 + 8003298: 3b01 subs r3, #1 + 800329a: 021b lsls r3, r3, #8 + 800329c: 493d ldr r1, [pc, #244] ; (8003394 ) + 800329e: 4313 orrs r3, r2 + 80032a0: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } + + /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ + /* In Case of PLLI2S is selected as source clock for CK48 */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) + 80032a4: 687b ldr r3, [r7, #4] + 80032a6: 681b ldr r3, [r3, #0] + 80032a8: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 80032ac: 2b00 cmp r3, #0 + 80032ae: d022 beq.n 80032f6 + 80032b0: 687b ldr r3, [r7, #4] + 80032b2: 6fdb ldr r3, [r3, #124] ; 0x7c + 80032b4: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 + 80032b8: d11d bne.n 80032f6 + { + /* check for Parameters */ + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + 80032ba: 4b36 ldr r3, [pc, #216] ; (8003394 ) + 80032bc: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 80032c0: 0e1b lsrs r3, r3, #24 + 80032c2: f003 030f and.w r3, r3, #15 + 80032c6: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + 80032c8: 4b32 ldr r3, [pc, #200] ; (8003394 ) + 80032ca: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 80032ce: 0f1b lsrs r3, r3, #28 + 80032d0: f003 0307 and.w r3, r3, #7 + 80032d4: 60fb str r3, [r7, #12] + + /* Configure the PLLSAI division factors */ + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ + /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); + 80032d6: 687b ldr r3, [r7, #4] + 80032d8: 695b ldr r3, [r3, #20] + 80032da: 019a lsls r2, r3, #6 + 80032dc: 687b ldr r3, [r7, #4] + 80032de: 6a1b ldr r3, [r3, #32] + 80032e0: 041b lsls r3, r3, #16 + 80032e2: 431a orrs r2, r3 + 80032e4: 693b ldr r3, [r7, #16] + 80032e6: 061b lsls r3, r3, #24 + 80032e8: 431a orrs r2, r3 + 80032ea: 68fb ldr r3, [r7, #12] + 80032ec: 071b lsls r3, r3, #28 + 80032ee: 4929 ldr r1, [pc, #164] ; (8003394 ) + 80032f0: 4313 orrs r3, r2 + 80032f2: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + } + +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + /*---------------------------- LTDC configuration -------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) + 80032f6: 687b ldr r3, [r7, #4] + 80032f8: 681b ldr r3, [r3, #0] + 80032fa: f003 0308 and.w r3, r3, #8 + 80032fe: 2b00 cmp r3, #0 + 8003300: d028 beq.n 8003354 + { + assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); + assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); + + /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + 8003302: 4b24 ldr r3, [pc, #144] ; (8003394 ) + 8003304: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8003308: 0e1b lsrs r3, r3, #24 + 800330a: f003 030f and.w r3, r3, #15 + 800330e: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + 8003310: 4b20 ldr r3, [pc, #128] ; (8003394 ) + 8003312: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8003316: 0c1b lsrs r3, r3, #16 + 8003318: f003 0303 and.w r3, r3, #3 + 800331c: 60fb str r3, [r7, #12] + + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR); + 800331e: 687b ldr r3, [r7, #4] + 8003320: 695b ldr r3, [r3, #20] + 8003322: 019a lsls r2, r3, #6 + 8003324: 68fb ldr r3, [r7, #12] + 8003326: 041b lsls r3, r3, #16 + 8003328: 431a orrs r2, r3 + 800332a: 693b ldr r3, [r7, #16] + 800332c: 061b lsls r3, r3, #24 + 800332e: 431a orrs r2, r3 + 8003330: 687b ldr r3, [r7, #4] + 8003332: 69db ldr r3, [r3, #28] + 8003334: 071b lsls r3, r3, #28 + 8003336: 4917 ldr r1, [pc, #92] ; (8003394 ) + 8003338: 4313 orrs r3, r2 + 800333a: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); + 800333e: 4b15 ldr r3, [pc, #84] ; (8003394 ) + 8003340: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8003344: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 8003348: 687b ldr r3, [r7, #4] + 800334a: 6adb ldr r3, [r3, #44] ; 0x2c + 800334c: 4911 ldr r1, [pc, #68] ; (8003394 ) + 800334e: 4313 orrs r3, r2 + 8003350: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + 8003354: 4b0f ldr r3, [pc, #60] ; (8003394 ) + 8003356: 681b ldr r3, [r3, #0] + 8003358: 4a0e ldr r2, [pc, #56] ; (8003394 ) + 800335a: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 800335e: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003360: f7fe fc98 bl 8001c94 + 8003364: 6178 str r0, [r7, #20] + + /* Wait till PLLSAI is ready */ + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + 8003366: e008 b.n 800337a + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + 8003368: f7fe fc94 bl 8001c94 + 800336c: 4602 mov r2, r0 + 800336e: 697b ldr r3, [r7, #20] + 8003370: 1ad3 subs r3, r2, r3 + 8003372: 2b64 cmp r3, #100 ; 0x64 + 8003374: d901 bls.n 800337a + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 8003376: 2303 movs r3, #3 + 8003378: e007 b.n 800338a + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + 800337a: 4b06 ldr r3, [pc, #24] ; (8003394 ) + 800337c: 681b ldr r3, [r3, #0] + 800337e: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 8003382: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 8003386: d1ef bne.n 8003368 + } + } + } + return HAL_OK; + 8003388: 2300 movs r3, #0 +} + 800338a: 4618 mov r0, r3 + 800338c: 3720 adds r7, #32 + 800338e: 46bd mov sp, r7 + 8003390: bd80 pop {r7, pc} + 8003392: bf00 nop + 8003394: 40023800 .word 0x40023800 + +08003398 : + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + 8003398: b580 push {r7, lr} + 800339a: b082 sub sp, #8 + 800339c: af00 add r7, sp, #0 + 800339e: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 80033a0: 687b ldr r3, [r7, #4] + 80033a2: 2b00 cmp r3, #0 + 80033a4: d101 bne.n 80033aa + { + return HAL_ERROR; + 80033a6: 2301 movs r3, #1 + 80033a8: e01d b.n 80033e6 + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 80033aa: 687b ldr r3, [r7, #4] + 80033ac: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 80033b0: b2db uxtb r3, r3 + 80033b2: 2b00 cmp r3, #0 + 80033b4: d106 bne.n 80033c4 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 80033b6: 687b ldr r3, [r7, #4] + 80033b8: 2200 movs r2, #0 + 80033ba: f883 203c strb.w r2, [r3, #60] ; 0x3c + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); + 80033be: 6878 ldr r0, [r7, #4] + 80033c0: f7fe faa0 bl 8001904 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 80033c4: 687b ldr r3, [r7, #4] + 80033c6: 2202 movs r2, #2 + 80033c8: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 80033cc: 687b ldr r3, [r7, #4] + 80033ce: 681a ldr r2, [r3, #0] + 80033d0: 687b ldr r3, [r7, #4] + 80033d2: 3304 adds r3, #4 + 80033d4: 4619 mov r1, r3 + 80033d6: 4610 mov r0, r2 + 80033d8: f000 fc90 bl 8003cfc + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 80033dc: 687b ldr r3, [r7, #4] + 80033de: 2201 movs r2, #1 + 80033e0: f883 203d strb.w r2, [r3, #61] ; 0x3d + + return HAL_OK; + 80033e4: 2300 movs r3, #0 +} + 80033e6: 4618 mov r0, r3 + 80033e8: 3708 adds r7, #8 + 80033ea: 46bd mov sp, r7 + 80033ec: bd80 pop {r7, pc} + ... + +080033f0 : + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + 80033f0: b480 push {r7} + 80033f2: b085 sub sp, #20 + 80033f4: af00 add r7, sp, #0 + 80033f6: 6078 str r0, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + 80033f8: 687b ldr r3, [r7, #4] + 80033fa: 681b ldr r3, [r3, #0] + 80033fc: 68da ldr r2, [r3, #12] + 80033fe: 687b ldr r3, [r7, #4] + 8003400: 681b ldr r3, [r3, #0] + 8003402: f042 0201 orr.w r2, r2, #1 + 8003406: 60da str r2, [r3, #12] + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 8003408: 687b ldr r3, [r7, #4] + 800340a: 681b ldr r3, [r3, #0] + 800340c: 689a ldr r2, [r3, #8] + 800340e: 4b0c ldr r3, [pc, #48] ; (8003440 ) + 8003410: 4013 ands r3, r2 + 8003412: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8003414: 68fb ldr r3, [r7, #12] + 8003416: 2b06 cmp r3, #6 + 8003418: d00b beq.n 8003432 + 800341a: 68fb ldr r3, [r7, #12] + 800341c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8003420: d007 beq.n 8003432 + { + __HAL_TIM_ENABLE(htim); + 8003422: 687b ldr r3, [r7, #4] + 8003424: 681b ldr r3, [r3, #0] + 8003426: 681a ldr r2, [r3, #0] + 8003428: 687b ldr r3, [r7, #4] + 800342a: 681b ldr r3, [r3, #0] + 800342c: f042 0201 orr.w r2, r2, #1 + 8003430: 601a str r2, [r3, #0] + } + + /* Return function status */ + return HAL_OK; + 8003432: 2300 movs r3, #0 +} + 8003434: 4618 mov r0, r3 + 8003436: 3714 adds r7, #20 + 8003438: 46bd mov sp, r7 + 800343a: f85d 7b04 ldr.w r7, [sp], #4 + 800343e: 4770 bx lr + 8003440: 00010007 .word 0x00010007 + +08003444 : + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + 8003444: b580 push {r7, lr} + 8003446: b082 sub sp, #8 + 8003448: af00 add r7, sp, #0 + 800344a: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 800344c: 687b ldr r3, [r7, #4] + 800344e: 2b00 cmp r3, #0 + 8003450: d101 bne.n 8003456 + { + return HAL_ERROR; + 8003452: 2301 movs r3, #1 + 8003454: e01d b.n 8003492 + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 8003456: 687b ldr r3, [r7, #4] + 8003458: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 800345c: b2db uxtb r3, r3 + 800345e: 2b00 cmp r3, #0 + 8003460: d106 bne.n 8003470 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 8003462: 687b ldr r3, [r7, #4] + 8003464: 2200 movs r2, #0 + 8003466: f883 203c strb.w r2, [r3, #60] ; 0x3c + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); + 800346a: 6878 ldr r0, [r7, #4] + 800346c: f000 f815 bl 800349a +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8003470: 687b ldr r3, [r7, #4] + 8003472: 2202 movs r2, #2 + 8003474: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8003478: 687b ldr r3, [r7, #4] + 800347a: 681a ldr r2, [r3, #0] + 800347c: 687b ldr r3, [r7, #4] + 800347e: 3304 adds r3, #4 + 8003480: 4619 mov r1, r3 + 8003482: 4610 mov r0, r2 + 8003484: f000 fc3a bl 8003cfc + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 8003488: 687b ldr r3, [r7, #4] + 800348a: 2201 movs r2, #1 + 800348c: f883 203d strb.w r2, [r3, #61] ; 0x3d + + return HAL_OK; + 8003490: 2300 movs r3, #0 +} + 8003492: 4618 mov r0, r3 + 8003494: 3708 adds r7, #8 + 8003496: 46bd mov sp, r7 + 8003498: bd80 pop {r7, pc} + +0800349a : + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + 800349a: b480 push {r7} + 800349c: b083 sub sp, #12 + 800349e: af00 add r7, sp, #0 + 80034a0: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + 80034a2: bf00 nop + 80034a4: 370c adds r7, #12 + 80034a6: 46bd mov sp, r7 + 80034a8: f85d 7b04 ldr.w r7, [sp], #4 + 80034ac: 4770 bx lr + ... + +080034b0 : + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + 80034b0: b580 push {r7, lr} + 80034b2: b084 sub sp, #16 + 80034b4: af00 add r7, sp, #0 + 80034b6: 6078 str r0, [r7, #4] + 80034b8: 6039 str r1, [r7, #0] + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 80034ba: 687b ldr r3, [r7, #4] + 80034bc: 681b ldr r3, [r3, #0] + 80034be: 2201 movs r2, #1 + 80034c0: 6839 ldr r1, [r7, #0] + 80034c2: 4618 mov r0, r3 + 80034c4: f000 ffb2 bl 800442c + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 80034c8: 687b ldr r3, [r7, #4] + 80034ca: 681b ldr r3, [r3, #0] + 80034cc: 4a17 ldr r2, [pc, #92] ; (800352c ) + 80034ce: 4293 cmp r3, r2 + 80034d0: d004 beq.n 80034dc + 80034d2: 687b ldr r3, [r7, #4] + 80034d4: 681b ldr r3, [r3, #0] + 80034d6: 4a16 ldr r2, [pc, #88] ; (8003530 ) + 80034d8: 4293 cmp r3, r2 + 80034da: d101 bne.n 80034e0 + 80034dc: 2301 movs r3, #1 + 80034de: e000 b.n 80034e2 + 80034e0: 2300 movs r3, #0 + 80034e2: 2b00 cmp r3, #0 + 80034e4: d007 beq.n 80034f6 + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + 80034e6: 687b ldr r3, [r7, #4] + 80034e8: 681b ldr r3, [r3, #0] + 80034ea: 6c5a ldr r2, [r3, #68] ; 0x44 + 80034ec: 687b ldr r3, [r7, #4] + 80034ee: 681b ldr r3, [r3, #0] + 80034f0: f442 4200 orr.w r2, r2, #32768 ; 0x8000 + 80034f4: 645a str r2, [r3, #68] ; 0x44 + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 80034f6: 687b ldr r3, [r7, #4] + 80034f8: 681b ldr r3, [r3, #0] + 80034fa: 689a ldr r2, [r3, #8] + 80034fc: 4b0d ldr r3, [pc, #52] ; (8003534 ) + 80034fe: 4013 ands r3, r2 + 8003500: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8003502: 68fb ldr r3, [r7, #12] + 8003504: 2b06 cmp r3, #6 + 8003506: d00b beq.n 8003520 + 8003508: 68fb ldr r3, [r7, #12] + 800350a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800350e: d007 beq.n 8003520 + { + __HAL_TIM_ENABLE(htim); + 8003510: 687b ldr r3, [r7, #4] + 8003512: 681b ldr r3, [r3, #0] + 8003514: 681a ldr r2, [r3, #0] + 8003516: 687b ldr r3, [r7, #4] + 8003518: 681b ldr r3, [r3, #0] + 800351a: f042 0201 orr.w r2, r2, #1 + 800351e: 601a str r2, [r3, #0] + } + + /* Return function status */ + return HAL_OK; + 8003520: 2300 movs r3, #0 +} + 8003522: 4618 mov r0, r3 + 8003524: 3710 adds r7, #16 + 8003526: 46bd mov sp, r7 + 8003528: bd80 pop {r7, pc} + 800352a: bf00 nop + 800352c: 40010000 .word 0x40010000 + 8003530: 40010400 .word 0x40010400 + 8003534: 00010007 .word 0x00010007 + +08003538 : + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +{ + 8003538: b580 push {r7, lr} + 800353a: b086 sub sp, #24 + 800353c: af00 add r7, sp, #0 + 800353e: 6078 str r0, [r7, #4] + 8003540: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + 8003542: 687b ldr r3, [r7, #4] + 8003544: 2b00 cmp r3, #0 + 8003546: d101 bne.n 800354c + { + return HAL_ERROR; + 8003548: 2301 movs r3, #1 + 800354a: e07b b.n 8003644 + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + 800354c: 687b ldr r3, [r7, #4] + 800354e: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 8003552: b2db uxtb r3, r3 + 8003554: 2b00 cmp r3, #0 + 8003556: d106 bne.n 8003566 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 8003558: 687b ldr r3, [r7, #4] + 800355a: 2200 movs r2, #0 + 800355c: f883 203c strb.w r2, [r3, #60] ; 0x3c + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); + 8003560: 6878 ldr r0, [r7, #4] + 8003562: f7fe f93f bl 80017e4 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8003566: 687b ldr r3, [r7, #4] + 8003568: 2202 movs r2, #2 + 800356a: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + 800356e: 687b ldr r3, [r7, #4] + 8003570: 681b ldr r3, [r3, #0] + 8003572: 6899 ldr r1, [r3, #8] + 8003574: 687b ldr r3, [r7, #4] + 8003576: 681a ldr r2, [r3, #0] + 8003578: 4b34 ldr r3, [pc, #208] ; (800364c ) + 800357a: 400b ands r3, r1 + 800357c: 6093 str r3, [r2, #8] + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 800357e: 687b ldr r3, [r7, #4] + 8003580: 681a ldr r2, [r3, #0] + 8003582: 687b ldr r3, [r7, #4] + 8003584: 3304 adds r3, #4 + 8003586: 4619 mov r1, r3 + 8003588: 4610 mov r0, r2 + 800358a: f000 fbb7 bl 8003cfc + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 800358e: 687b ldr r3, [r7, #4] + 8003590: 681b ldr r3, [r3, #0] + 8003592: 689b ldr r3, [r3, #8] + 8003594: 617b str r3, [r7, #20] + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + 8003596: 687b ldr r3, [r7, #4] + 8003598: 681b ldr r3, [r3, #0] + 800359a: 699b ldr r3, [r3, #24] + 800359c: 613b str r3, [r7, #16] + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + 800359e: 687b ldr r3, [r7, #4] + 80035a0: 681b ldr r3, [r3, #0] + 80035a2: 6a1b ldr r3, [r3, #32] + 80035a4: 60fb str r3, [r7, #12] + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + 80035a6: 683b ldr r3, [r7, #0] + 80035a8: 681b ldr r3, [r3, #0] + 80035aa: 697a ldr r2, [r7, #20] + 80035ac: 4313 orrs r3, r2 + 80035ae: 617b str r3, [r7, #20] + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + 80035b0: 693a ldr r2, [r7, #16] + 80035b2: 4b27 ldr r3, [pc, #156] ; (8003650 ) + 80035b4: 4013 ands r3, r2 + 80035b6: 613b str r3, [r7, #16] + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + 80035b8: 683b ldr r3, [r7, #0] + 80035ba: 689a ldr r2, [r3, #8] + 80035bc: 683b ldr r3, [r7, #0] + 80035be: 699b ldr r3, [r3, #24] + 80035c0: 021b lsls r3, r3, #8 + 80035c2: 4313 orrs r3, r2 + 80035c4: 693a ldr r2, [r7, #16] + 80035c6: 4313 orrs r3, r2 + 80035c8: 613b str r3, [r7, #16] + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + 80035ca: 693a ldr r2, [r7, #16] + 80035cc: 4b21 ldr r3, [pc, #132] ; (8003654 ) + 80035ce: 4013 ands r3, r2 + 80035d0: 613b str r3, [r7, #16] + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + 80035d2: 693a ldr r2, [r7, #16] + 80035d4: 4b20 ldr r3, [pc, #128] ; (8003658 ) + 80035d6: 4013 ands r3, r2 + 80035d8: 613b str r3, [r7, #16] + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + 80035da: 683b ldr r3, [r7, #0] + 80035dc: 68da ldr r2, [r3, #12] + 80035de: 683b ldr r3, [r7, #0] + 80035e0: 69db ldr r3, [r3, #28] + 80035e2: 021b lsls r3, r3, #8 + 80035e4: 4313 orrs r3, r2 + 80035e6: 693a ldr r2, [r7, #16] + 80035e8: 4313 orrs r3, r2 + 80035ea: 613b str r3, [r7, #16] + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + 80035ec: 683b ldr r3, [r7, #0] + 80035ee: 691b ldr r3, [r3, #16] + 80035f0: 011a lsls r2, r3, #4 + 80035f2: 683b ldr r3, [r7, #0] + 80035f4: 6a1b ldr r3, [r3, #32] + 80035f6: 031b lsls r3, r3, #12 + 80035f8: 4313 orrs r3, r2 + 80035fa: 693a ldr r2, [r7, #16] + 80035fc: 4313 orrs r3, r2 + 80035fe: 613b str r3, [r7, #16] + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + 8003600: 68fb ldr r3, [r7, #12] + 8003602: f023 0322 bic.w r3, r3, #34 ; 0x22 + 8003606: 60fb str r3, [r7, #12] + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + 8003608: 68fb ldr r3, [r7, #12] + 800360a: f023 0388 bic.w r3, r3, #136 ; 0x88 + 800360e: 60fb str r3, [r7, #12] + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + 8003610: 683b ldr r3, [r7, #0] + 8003612: 685a ldr r2, [r3, #4] + 8003614: 683b ldr r3, [r7, #0] + 8003616: 695b ldr r3, [r3, #20] + 8003618: 011b lsls r3, r3, #4 + 800361a: 4313 orrs r3, r2 + 800361c: 68fa ldr r2, [r7, #12] + 800361e: 4313 orrs r3, r2 + 8003620: 60fb str r3, [r7, #12] + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8003622: 687b ldr r3, [r7, #4] + 8003624: 681b ldr r3, [r3, #0] + 8003626: 697a ldr r2, [r7, #20] + 8003628: 609a str r2, [r3, #8] + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + 800362a: 687b ldr r3, [r7, #4] + 800362c: 681b ldr r3, [r3, #0] + 800362e: 693a ldr r2, [r7, #16] + 8003630: 619a str r2, [r3, #24] + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + 8003632: 687b ldr r3, [r7, #4] + 8003634: 681b ldr r3, [r3, #0] + 8003636: 68fa ldr r2, [r7, #12] + 8003638: 621a str r2, [r3, #32] + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 800363a: 687b ldr r3, [r7, #4] + 800363c: 2201 movs r2, #1 + 800363e: f883 203d strb.w r2, [r3, #61] ; 0x3d + + return HAL_OK; + 8003642: 2300 movs r3, #0 +} + 8003644: 4618 mov r0, r3 + 8003646: 3718 adds r7, #24 + 8003648: 46bd mov sp, r7 + 800364a: bd80 pop {r7, pc} + 800364c: fffebff8 .word 0xfffebff8 + 8003650: fffffcfc .word 0xfffffcfc + 8003654: fffff3f3 .word 0xfffff3f3 + 8003658: ffff0f0f .word 0xffff0f0f + +0800365c : + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + 800365c: b580 push {r7, lr} + 800365e: b082 sub sp, #8 + 8003660: af00 add r7, sp, #0 + 8003662: 6078 str r0, [r7, #4] + 8003664: 6039 str r1, [r7, #0] + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + switch (Channel) + 8003666: 683b ldr r3, [r7, #0] + 8003668: 2b00 cmp r3, #0 + 800366a: d002 beq.n 8003672 + 800366c: 2b04 cmp r3, #4 + 800366e: d008 beq.n 8003682 + 8003670: e00f b.n 8003692 + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 8003672: 687b ldr r3, [r7, #4] + 8003674: 681b ldr r3, [r3, #0] + 8003676: 2201 movs r2, #1 + 8003678: 2100 movs r1, #0 + 800367a: 4618 mov r0, r3 + 800367c: f000 fed6 bl 800442c + break; + 8003680: e016 b.n 80036b0 + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 8003682: 687b ldr r3, [r7, #4] + 8003684: 681b ldr r3, [r3, #0] + 8003686: 2201 movs r2, #1 + 8003688: 2104 movs r1, #4 + 800368a: 4618 mov r0, r3 + 800368c: f000 fece bl 800442c + break; + 8003690: e00e b.n 80036b0 + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 8003692: 687b ldr r3, [r7, #4] + 8003694: 681b ldr r3, [r3, #0] + 8003696: 2201 movs r2, #1 + 8003698: 2100 movs r1, #0 + 800369a: 4618 mov r0, r3 + 800369c: f000 fec6 bl 800442c + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 80036a0: 687b ldr r3, [r7, #4] + 80036a2: 681b ldr r3, [r3, #0] + 80036a4: 2201 movs r2, #1 + 80036a6: 2104 movs r1, #4 + 80036a8: 4618 mov r0, r3 + 80036aa: f000 febf bl 800442c + break; + 80036ae: bf00 nop + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + 80036b0: 687b ldr r3, [r7, #4] + 80036b2: 681b ldr r3, [r3, #0] + 80036b4: 681a ldr r2, [r3, #0] + 80036b6: 687b ldr r3, [r7, #4] + 80036b8: 681b ldr r3, [r3, #0] + 80036ba: f042 0201 orr.w r2, r2, #1 + 80036be: 601a str r2, [r3, #0] + + /* Return function status */ + return HAL_OK; + 80036c0: 2300 movs r3, #0 +} + 80036c2: 4618 mov r0, r3 + 80036c4: 3708 adds r7, #8 + 80036c6: 46bd mov sp, r7 + 80036c8: bd80 pop {r7, pc} + +080036ca : + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + 80036ca: b580 push {r7, lr} + 80036cc: b082 sub sp, #8 + 80036ce: af00 add r7, sp, #0 + 80036d0: 6078 str r0, [r7, #4] + /* Capture compare 1 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + 80036d2: 687b ldr r3, [r7, #4] + 80036d4: 681b ldr r3, [r3, #0] + 80036d6: 691b ldr r3, [r3, #16] + 80036d8: f003 0302 and.w r3, r3, #2 + 80036dc: 2b02 cmp r3, #2 + 80036de: d122 bne.n 8003726 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + 80036e0: 687b ldr r3, [r7, #4] + 80036e2: 681b ldr r3, [r3, #0] + 80036e4: 68db ldr r3, [r3, #12] + 80036e6: f003 0302 and.w r3, r3, #2 + 80036ea: 2b02 cmp r3, #2 + 80036ec: d11b bne.n 8003726 + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + 80036ee: 687b ldr r3, [r7, #4] + 80036f0: 681b ldr r3, [r3, #0] + 80036f2: f06f 0202 mvn.w r2, #2 + 80036f6: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 80036f8: 687b ldr r3, [r7, #4] + 80036fa: 2201 movs r2, #1 + 80036fc: 771a strb r2, [r3, #28] + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + 80036fe: 687b ldr r3, [r7, #4] + 8003700: 681b ldr r3, [r3, #0] + 8003702: 699b ldr r3, [r3, #24] + 8003704: f003 0303 and.w r3, r3, #3 + 8003708: 2b00 cmp r3, #0 + 800370a: d003 beq.n 8003714 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 800370c: 6878 ldr r0, [r7, #4] + 800370e: f000 fad7 bl 8003cc0 + 8003712: e005 b.n 8003720 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8003714: 6878 ldr r0, [r7, #4] + 8003716: f000 fac9 bl 8003cac + HAL_TIM_PWM_PulseFinishedCallback(htim); + 800371a: 6878 ldr r0, [r7, #4] + 800371c: f000 fada bl 8003cd4 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8003720: 687b ldr r3, [r7, #4] + 8003722: 2200 movs r2, #0 + 8003724: 771a strb r2, [r3, #28] + } + } + } + /* Capture compare 2 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + 8003726: 687b ldr r3, [r7, #4] + 8003728: 681b ldr r3, [r3, #0] + 800372a: 691b ldr r3, [r3, #16] + 800372c: f003 0304 and.w r3, r3, #4 + 8003730: 2b04 cmp r3, #4 + 8003732: d122 bne.n 800377a + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + 8003734: 687b ldr r3, [r7, #4] + 8003736: 681b ldr r3, [r3, #0] + 8003738: 68db ldr r3, [r3, #12] + 800373a: f003 0304 and.w r3, r3, #4 + 800373e: 2b04 cmp r3, #4 + 8003740: d11b bne.n 800377a + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + 8003742: 687b ldr r3, [r7, #4] + 8003744: 681b ldr r3, [r3, #0] + 8003746: f06f 0204 mvn.w r2, #4 + 800374a: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 800374c: 687b ldr r3, [r7, #4] + 800374e: 2202 movs r2, #2 + 8003750: 771a strb r2, [r3, #28] + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + 8003752: 687b ldr r3, [r7, #4] + 8003754: 681b ldr r3, [r3, #0] + 8003756: 699b ldr r3, [r3, #24] + 8003758: f403 7340 and.w r3, r3, #768 ; 0x300 + 800375c: 2b00 cmp r3, #0 + 800375e: d003 beq.n 8003768 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8003760: 6878 ldr r0, [r7, #4] + 8003762: f000 faad bl 8003cc0 + 8003766: e005 b.n 8003774 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8003768: 6878 ldr r0, [r7, #4] + 800376a: f000 fa9f bl 8003cac + HAL_TIM_PWM_PulseFinishedCallback(htim); + 800376e: 6878 ldr r0, [r7, #4] + 8003770: f000 fab0 bl 8003cd4 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8003774: 687b ldr r3, [r7, #4] + 8003776: 2200 movs r2, #0 + 8003778: 771a strb r2, [r3, #28] + } + } + /* Capture compare 3 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + 800377a: 687b ldr r3, [r7, #4] + 800377c: 681b ldr r3, [r3, #0] + 800377e: 691b ldr r3, [r3, #16] + 8003780: f003 0308 and.w r3, r3, #8 + 8003784: 2b08 cmp r3, #8 + 8003786: d122 bne.n 80037ce + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + 8003788: 687b ldr r3, [r7, #4] + 800378a: 681b ldr r3, [r3, #0] + 800378c: 68db ldr r3, [r3, #12] + 800378e: f003 0308 and.w r3, r3, #8 + 8003792: 2b08 cmp r3, #8 + 8003794: d11b bne.n 80037ce + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + 8003796: 687b ldr r3, [r7, #4] + 8003798: 681b ldr r3, [r3, #0] + 800379a: f06f 0208 mvn.w r2, #8 + 800379e: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 80037a0: 687b ldr r3, [r7, #4] + 80037a2: 2204 movs r2, #4 + 80037a4: 771a strb r2, [r3, #28] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + 80037a6: 687b ldr r3, [r7, #4] + 80037a8: 681b ldr r3, [r3, #0] + 80037aa: 69db ldr r3, [r3, #28] + 80037ac: f003 0303 and.w r3, r3, #3 + 80037b0: 2b00 cmp r3, #0 + 80037b2: d003 beq.n 80037bc + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 80037b4: 6878 ldr r0, [r7, #4] + 80037b6: f000 fa83 bl 8003cc0 + 80037ba: e005 b.n 80037c8 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 80037bc: 6878 ldr r0, [r7, #4] + 80037be: f000 fa75 bl 8003cac + HAL_TIM_PWM_PulseFinishedCallback(htim); + 80037c2: 6878 ldr r0, [r7, #4] + 80037c4: f000 fa86 bl 8003cd4 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 80037c8: 687b ldr r3, [r7, #4] + 80037ca: 2200 movs r2, #0 + 80037cc: 771a strb r2, [r3, #28] + } + } + /* Capture compare 4 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + 80037ce: 687b ldr r3, [r7, #4] + 80037d0: 681b ldr r3, [r3, #0] + 80037d2: 691b ldr r3, [r3, #16] + 80037d4: f003 0310 and.w r3, r3, #16 + 80037d8: 2b10 cmp r3, #16 + 80037da: d122 bne.n 8003822 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + 80037dc: 687b ldr r3, [r7, #4] + 80037de: 681b ldr r3, [r3, #0] + 80037e0: 68db ldr r3, [r3, #12] + 80037e2: f003 0310 and.w r3, r3, #16 + 80037e6: 2b10 cmp r3, #16 + 80037e8: d11b bne.n 8003822 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + 80037ea: 687b ldr r3, [r7, #4] + 80037ec: 681b ldr r3, [r3, #0] + 80037ee: f06f 0210 mvn.w r2, #16 + 80037f2: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 80037f4: 687b ldr r3, [r7, #4] + 80037f6: 2208 movs r2, #8 + 80037f8: 771a strb r2, [r3, #28] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + 80037fa: 687b ldr r3, [r7, #4] + 80037fc: 681b ldr r3, [r3, #0] + 80037fe: 69db ldr r3, [r3, #28] + 8003800: f403 7340 and.w r3, r3, #768 ; 0x300 + 8003804: 2b00 cmp r3, #0 + 8003806: d003 beq.n 8003810 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8003808: 6878 ldr r0, [r7, #4] + 800380a: f000 fa59 bl 8003cc0 + 800380e: e005 b.n 800381c + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8003810: 6878 ldr r0, [r7, #4] + 8003812: f000 fa4b bl 8003cac + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8003816: 6878 ldr r0, [r7, #4] + 8003818: f000 fa5c bl 8003cd4 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 800381c: 687b ldr r3, [r7, #4] + 800381e: 2200 movs r2, #0 + 8003820: 771a strb r2, [r3, #28] + } + } + /* TIM Update event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + 8003822: 687b ldr r3, [r7, #4] + 8003824: 681b ldr r3, [r3, #0] + 8003826: 691b ldr r3, [r3, #16] + 8003828: f003 0301 and.w r3, r3, #1 + 800382c: 2b01 cmp r3, #1 + 800382e: d10e bne.n 800384e + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + 8003830: 687b ldr r3, [r7, #4] + 8003832: 681b ldr r3, [r3, #0] + 8003834: 68db ldr r3, [r3, #12] + 8003836: f003 0301 and.w r3, r3, #1 + 800383a: 2b01 cmp r3, #1 + 800383c: d107 bne.n 800384e + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + 800383e: 687b ldr r3, [r7, #4] + 8003840: 681b ldr r3, [r3, #0] + 8003842: f06f 0201 mvn.w r2, #1 + 8003846: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); + 8003848: 6878 ldr r0, [r7, #4] + 800384a: f7fd fe01 bl 8001450 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + 800384e: 687b ldr r3, [r7, #4] + 8003850: 681b ldr r3, [r3, #0] + 8003852: 691b ldr r3, [r3, #16] + 8003854: f003 0380 and.w r3, r3, #128 ; 0x80 + 8003858: 2b80 cmp r3, #128 ; 0x80 + 800385a: d10e bne.n 800387a + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + 800385c: 687b ldr r3, [r7, #4] + 800385e: 681b ldr r3, [r3, #0] + 8003860: 68db ldr r3, [r3, #12] + 8003862: f003 0380 and.w r3, r3, #128 ; 0x80 + 8003866: 2b80 cmp r3, #128 ; 0x80 + 8003868: d107 bne.n 800387a + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + 800386a: 687b ldr r3, [r7, #4] + 800386c: 681b ldr r3, [r3, #0] + 800386e: f06f 0280 mvn.w r2, #128 ; 0x80 + 8003872: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); + 8003874: 6878 ldr r0, [r7, #4] + 8003876: f000 fe65 bl 8004544 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break2 input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + 800387a: 687b ldr r3, [r7, #4] + 800387c: 681b ldr r3, [r3, #0] + 800387e: 691b ldr r3, [r3, #16] + 8003880: f403 7380 and.w r3, r3, #256 ; 0x100 + 8003884: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8003888: d10e bne.n 80038a8 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + 800388a: 687b ldr r3, [r7, #4] + 800388c: 681b ldr r3, [r3, #0] + 800388e: 68db ldr r3, [r3, #12] + 8003890: f003 0380 and.w r3, r3, #128 ; 0x80 + 8003894: 2b80 cmp r3, #128 ; 0x80 + 8003896: d107 bne.n 80038a8 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); + 8003898: 687b ldr r3, [r7, #4] + 800389a: 681b ldr r3, [r3, #0] + 800389c: f46f 7280 mvn.w r2, #256 ; 0x100 + 80038a0: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); + 80038a2: 6878 ldr r0, [r7, #4] + 80038a4: f000 fe58 bl 8004558 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + 80038a8: 687b ldr r3, [r7, #4] + 80038aa: 681b ldr r3, [r3, #0] + 80038ac: 691b ldr r3, [r3, #16] + 80038ae: f003 0340 and.w r3, r3, #64 ; 0x40 + 80038b2: 2b40 cmp r3, #64 ; 0x40 + 80038b4: d10e bne.n 80038d4 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + 80038b6: 687b ldr r3, [r7, #4] + 80038b8: 681b ldr r3, [r3, #0] + 80038ba: 68db ldr r3, [r3, #12] + 80038bc: f003 0340 and.w r3, r3, #64 ; 0x40 + 80038c0: 2b40 cmp r3, #64 ; 0x40 + 80038c2: d107 bne.n 80038d4 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + 80038c4: 687b ldr r3, [r7, #4] + 80038c6: 681b ldr r3, [r3, #0] + 80038c8: f06f 0240 mvn.w r2, #64 ; 0x40 + 80038cc: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); + 80038ce: 6878 ldr r0, [r7, #4] + 80038d0: f000 fa0a bl 8003ce8 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + 80038d4: 687b ldr r3, [r7, #4] + 80038d6: 681b ldr r3, [r3, #0] + 80038d8: 691b ldr r3, [r3, #16] + 80038da: f003 0320 and.w r3, r3, #32 + 80038de: 2b20 cmp r3, #32 + 80038e0: d10e bne.n 8003900 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + 80038e2: 687b ldr r3, [r7, #4] + 80038e4: 681b ldr r3, [r3, #0] + 80038e6: 68db ldr r3, [r3, #12] + 80038e8: f003 0320 and.w r3, r3, #32 + 80038ec: 2b20 cmp r3, #32 + 80038ee: d107 bne.n 8003900 + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + 80038f0: 687b ldr r3, [r7, #4] + 80038f2: 681b ldr r3, [r3, #0] + 80038f4: f06f 0220 mvn.w r2, #32 + 80038f8: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); + 80038fa: 6878 ldr r0, [r7, #4] + 80038fc: f000 fe18 bl 8004530 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + 8003900: bf00 nop + 8003902: 3708 adds r7, #8 + 8003904: 46bd mov sp, r7 + 8003906: bd80 pop {r7, pc} + +08003908 : + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + 8003908: b580 push {r7, lr} + 800390a: b084 sub sp, #16 + 800390c: af00 add r7, sp, #0 + 800390e: 60f8 str r0, [r7, #12] + 8003910: 60b9 str r1, [r7, #8] + 8003912: 607a str r2, [r7, #4] + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + 8003914: 68fb ldr r3, [r7, #12] + 8003916: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 800391a: 2b01 cmp r3, #1 + 800391c: d101 bne.n 8003922 + 800391e: 2302 movs r3, #2 + 8003920: e105 b.n 8003b2e + 8003922: 68fb ldr r3, [r7, #12] + 8003924: 2201 movs r2, #1 + 8003926: f883 203c strb.w r2, [r3, #60] ; 0x3c + + htim->State = HAL_TIM_STATE_BUSY; + 800392a: 68fb ldr r3, [r7, #12] + 800392c: 2202 movs r2, #2 + 800392e: f883 203d strb.w r2, [r3, #61] ; 0x3d + + switch (Channel) + 8003932: 687b ldr r3, [r7, #4] + 8003934: 2b14 cmp r3, #20 + 8003936: f200 80f0 bhi.w 8003b1a + 800393a: a201 add r2, pc, #4 ; (adr r2, 8003940 ) + 800393c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8003940: 08003995 .word 0x08003995 + 8003944: 08003b1b .word 0x08003b1b + 8003948: 08003b1b .word 0x08003b1b + 800394c: 08003b1b .word 0x08003b1b + 8003950: 080039d5 .word 0x080039d5 + 8003954: 08003b1b .word 0x08003b1b + 8003958: 08003b1b .word 0x08003b1b + 800395c: 08003b1b .word 0x08003b1b + 8003960: 08003a17 .word 0x08003a17 + 8003964: 08003b1b .word 0x08003b1b + 8003968: 08003b1b .word 0x08003b1b + 800396c: 08003b1b .word 0x08003b1b + 8003970: 08003a57 .word 0x08003a57 + 8003974: 08003b1b .word 0x08003b1b + 8003978: 08003b1b .word 0x08003b1b + 800397c: 08003b1b .word 0x08003b1b + 8003980: 08003a99 .word 0x08003a99 + 8003984: 08003b1b .word 0x08003b1b + 8003988: 08003b1b .word 0x08003b1b + 800398c: 08003b1b .word 0x08003b1b + 8003990: 08003ad9 .word 0x08003ad9 + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + 8003994: 68fb ldr r3, [r7, #12] + 8003996: 681b ldr r3, [r3, #0] + 8003998: 68b9 ldr r1, [r7, #8] + 800399a: 4618 mov r0, r3 + 800399c: f000 fa4e bl 8003e3c + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + 80039a0: 68fb ldr r3, [r7, #12] + 80039a2: 681b ldr r3, [r3, #0] + 80039a4: 699a ldr r2, [r3, #24] + 80039a6: 68fb ldr r3, [r7, #12] + 80039a8: 681b ldr r3, [r3, #0] + 80039aa: f042 0208 orr.w r2, r2, #8 + 80039ae: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + 80039b0: 68fb ldr r3, [r7, #12] + 80039b2: 681b ldr r3, [r3, #0] + 80039b4: 699a ldr r2, [r3, #24] + 80039b6: 68fb ldr r3, [r7, #12] + 80039b8: 681b ldr r3, [r3, #0] + 80039ba: f022 0204 bic.w r2, r2, #4 + 80039be: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode; + 80039c0: 68fb ldr r3, [r7, #12] + 80039c2: 681b ldr r3, [r3, #0] + 80039c4: 6999 ldr r1, [r3, #24] + 80039c6: 68bb ldr r3, [r7, #8] + 80039c8: 691a ldr r2, [r3, #16] + 80039ca: 68fb ldr r3, [r7, #12] + 80039cc: 681b ldr r3, [r3, #0] + 80039ce: 430a orrs r2, r1 + 80039d0: 619a str r2, [r3, #24] + break; + 80039d2: e0a3 b.n 8003b1c + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + 80039d4: 68fb ldr r3, [r7, #12] + 80039d6: 681b ldr r3, [r3, #0] + 80039d8: 68b9 ldr r1, [r7, #8] + 80039da: 4618 mov r0, r3 + 80039dc: f000 faa0 bl 8003f20 + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + 80039e0: 68fb ldr r3, [r7, #12] + 80039e2: 681b ldr r3, [r3, #0] + 80039e4: 699a ldr r2, [r3, #24] + 80039e6: 68fb ldr r3, [r7, #12] + 80039e8: 681b ldr r3, [r3, #0] + 80039ea: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 80039ee: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + 80039f0: 68fb ldr r3, [r7, #12] + 80039f2: 681b ldr r3, [r3, #0] + 80039f4: 699a ldr r2, [r3, #24] + 80039f6: 68fb ldr r3, [r7, #12] + 80039f8: 681b ldr r3, [r3, #0] + 80039fa: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 80039fe: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + 8003a00: 68fb ldr r3, [r7, #12] + 8003a02: 681b ldr r3, [r3, #0] + 8003a04: 6999 ldr r1, [r3, #24] + 8003a06: 68bb ldr r3, [r7, #8] + 8003a08: 691b ldr r3, [r3, #16] + 8003a0a: 021a lsls r2, r3, #8 + 8003a0c: 68fb ldr r3, [r7, #12] + 8003a0e: 681b ldr r3, [r3, #0] + 8003a10: 430a orrs r2, r1 + 8003a12: 619a str r2, [r3, #24] + break; + 8003a14: e082 b.n 8003b1c + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + 8003a16: 68fb ldr r3, [r7, #12] + 8003a18: 681b ldr r3, [r3, #0] + 8003a1a: 68b9 ldr r1, [r7, #8] + 8003a1c: 4618 mov r0, r3 + 8003a1e: f000 faf7 bl 8004010 + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + 8003a22: 68fb ldr r3, [r7, #12] + 8003a24: 681b ldr r3, [r3, #0] + 8003a26: 69da ldr r2, [r3, #28] + 8003a28: 68fb ldr r3, [r7, #12] + 8003a2a: 681b ldr r3, [r3, #0] + 8003a2c: f042 0208 orr.w r2, r2, #8 + 8003a30: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + 8003a32: 68fb ldr r3, [r7, #12] + 8003a34: 681b ldr r3, [r3, #0] + 8003a36: 69da ldr r2, [r3, #28] + 8003a38: 68fb ldr r3, [r7, #12] + 8003a3a: 681b ldr r3, [r3, #0] + 8003a3c: f022 0204 bic.w r2, r2, #4 + 8003a40: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode; + 8003a42: 68fb ldr r3, [r7, #12] + 8003a44: 681b ldr r3, [r3, #0] + 8003a46: 69d9 ldr r1, [r3, #28] + 8003a48: 68bb ldr r3, [r7, #8] + 8003a4a: 691a ldr r2, [r3, #16] + 8003a4c: 68fb ldr r3, [r7, #12] + 8003a4e: 681b ldr r3, [r3, #0] + 8003a50: 430a orrs r2, r1 + 8003a52: 61da str r2, [r3, #28] + break; + 8003a54: e062 b.n 8003b1c + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + 8003a56: 68fb ldr r3, [r7, #12] + 8003a58: 681b ldr r3, [r3, #0] + 8003a5a: 68b9 ldr r1, [r7, #8] + 8003a5c: 4618 mov r0, r3 + 8003a5e: f000 fb4d bl 80040fc + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + 8003a62: 68fb ldr r3, [r7, #12] + 8003a64: 681b ldr r3, [r3, #0] + 8003a66: 69da ldr r2, [r3, #28] + 8003a68: 68fb ldr r3, [r7, #12] + 8003a6a: 681b ldr r3, [r3, #0] + 8003a6c: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 8003a70: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + 8003a72: 68fb ldr r3, [r7, #12] + 8003a74: 681b ldr r3, [r3, #0] + 8003a76: 69da ldr r2, [r3, #28] + 8003a78: 68fb ldr r3, [r7, #12] + 8003a7a: 681b ldr r3, [r3, #0] + 8003a7c: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 8003a80: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + 8003a82: 68fb ldr r3, [r7, #12] + 8003a84: 681b ldr r3, [r3, #0] + 8003a86: 69d9 ldr r1, [r3, #28] + 8003a88: 68bb ldr r3, [r7, #8] + 8003a8a: 691b ldr r3, [r3, #16] + 8003a8c: 021a lsls r2, r3, #8 + 8003a8e: 68fb ldr r3, [r7, #12] + 8003a90: 681b ldr r3, [r3, #0] + 8003a92: 430a orrs r2, r1 + 8003a94: 61da str r2, [r3, #28] + break; + 8003a96: e041 b.n 8003b1c + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the Channel 5 in PWM mode */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + 8003a98: 68fb ldr r3, [r7, #12] + 8003a9a: 681b ldr r3, [r3, #0] + 8003a9c: 68b9 ldr r1, [r7, #8] + 8003a9e: 4618 mov r0, r3 + 8003aa0: f000 fb84 bl 80041ac + + /* Set the Preload enable bit for channel5*/ + htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; + 8003aa4: 68fb ldr r3, [r7, #12] + 8003aa6: 681b ldr r3, [r3, #0] + 8003aa8: 6d5a ldr r2, [r3, #84] ; 0x54 + 8003aaa: 68fb ldr r3, [r7, #12] + 8003aac: 681b ldr r3, [r3, #0] + 8003aae: f042 0208 orr.w r2, r2, #8 + 8003ab2: 655a str r2, [r3, #84] ; 0x54 + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; + 8003ab4: 68fb ldr r3, [r7, #12] + 8003ab6: 681b ldr r3, [r3, #0] + 8003ab8: 6d5a ldr r2, [r3, #84] ; 0x54 + 8003aba: 68fb ldr r3, [r7, #12] + 8003abc: 681b ldr r3, [r3, #0] + 8003abe: f022 0204 bic.w r2, r2, #4 + 8003ac2: 655a str r2, [r3, #84] ; 0x54 + htim->Instance->CCMR3 |= sConfig->OCFastMode; + 8003ac4: 68fb ldr r3, [r7, #12] + 8003ac6: 681b ldr r3, [r3, #0] + 8003ac8: 6d59 ldr r1, [r3, #84] ; 0x54 + 8003aca: 68bb ldr r3, [r7, #8] + 8003acc: 691a ldr r2, [r3, #16] + 8003ace: 68fb ldr r3, [r7, #12] + 8003ad0: 681b ldr r3, [r3, #0] + 8003ad2: 430a orrs r2, r1 + 8003ad4: 655a str r2, [r3, #84] ; 0x54 + break; + 8003ad6: e021 b.n 8003b1c + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the Channel 6 in PWM mode */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + 8003ad8: 68fb ldr r3, [r7, #12] + 8003ada: 681b ldr r3, [r3, #0] + 8003adc: 68b9 ldr r1, [r7, #8] + 8003ade: 4618 mov r0, r3 + 8003ae0: f000 fbb6 bl 8004250 + + /* Set the Preload enable bit for channel6 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; + 8003ae4: 68fb ldr r3, [r7, #12] + 8003ae6: 681b ldr r3, [r3, #0] + 8003ae8: 6d5a ldr r2, [r3, #84] ; 0x54 + 8003aea: 68fb ldr r3, [r7, #12] + 8003aec: 681b ldr r3, [r3, #0] + 8003aee: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 8003af2: 655a str r2, [r3, #84] ; 0x54 + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; + 8003af4: 68fb ldr r3, [r7, #12] + 8003af6: 681b ldr r3, [r3, #0] + 8003af8: 6d5a ldr r2, [r3, #84] ; 0x54 + 8003afa: 68fb ldr r3, [r7, #12] + 8003afc: 681b ldr r3, [r3, #0] + 8003afe: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 8003b02: 655a str r2, [r3, #84] ; 0x54 + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + 8003b04: 68fb ldr r3, [r7, #12] + 8003b06: 681b ldr r3, [r3, #0] + 8003b08: 6d59 ldr r1, [r3, #84] ; 0x54 + 8003b0a: 68bb ldr r3, [r7, #8] + 8003b0c: 691b ldr r3, [r3, #16] + 8003b0e: 021a lsls r2, r3, #8 + 8003b10: 68fb ldr r3, [r7, #12] + 8003b12: 681b ldr r3, [r3, #0] + 8003b14: 430a orrs r2, r1 + 8003b16: 655a str r2, [r3, #84] ; 0x54 + break; + 8003b18: e000 b.n 8003b1c + } + + default: + break; + 8003b1a: bf00 nop + } + + htim->State = HAL_TIM_STATE_READY; + 8003b1c: 68fb ldr r3, [r7, #12] + 8003b1e: 2201 movs r2, #1 + 8003b20: f883 203d strb.w r2, [r3, #61] ; 0x3d + + __HAL_UNLOCK(htim); + 8003b24: 68fb ldr r3, [r7, #12] + 8003b26: 2200 movs r2, #0 + 8003b28: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_OK; + 8003b2c: 2300 movs r3, #0 +} + 8003b2e: 4618 mov r0, r3 + 8003b30: 3710 adds r7, #16 + 8003b32: 46bd mov sp, r7 + 8003b34: bd80 pop {r7, pc} + 8003b36: bf00 nop + +08003b38 : + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + 8003b38: b580 push {r7, lr} + 8003b3a: b084 sub sp, #16 + 8003b3c: af00 add r7, sp, #0 + 8003b3e: 6078 str r0, [r7, #4] + 8003b40: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + 8003b42: 687b ldr r3, [r7, #4] + 8003b44: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 8003b48: 2b01 cmp r3, #1 + 8003b4a: d101 bne.n 8003b50 + 8003b4c: 2302 movs r3, #2 + 8003b4e: e0a6 b.n 8003c9e + 8003b50: 687b ldr r3, [r7, #4] + 8003b52: 2201 movs r2, #1 + 8003b54: f883 203c strb.w r2, [r3, #60] ; 0x3c + + htim->State = HAL_TIM_STATE_BUSY; + 8003b58: 687b ldr r3, [r7, #4] + 8003b5a: 2202 movs r2, #2 + 8003b5c: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + 8003b60: 687b ldr r3, [r7, #4] + 8003b62: 681b ldr r3, [r3, #0] + 8003b64: 689b ldr r3, [r3, #8] + 8003b66: 60fb str r3, [r7, #12] + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + 8003b68: 68fa ldr r2, [r7, #12] + 8003b6a: 4b4f ldr r3, [pc, #316] ; (8003ca8 ) + 8003b6c: 4013 ands r3, r2 + 8003b6e: 60fb str r3, [r7, #12] + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 8003b70: 68fb ldr r3, [r7, #12] + 8003b72: f423 437f bic.w r3, r3, #65280 ; 0xff00 + 8003b76: 60fb str r3, [r7, #12] + htim->Instance->SMCR = tmpsmcr; + 8003b78: 687b ldr r3, [r7, #4] + 8003b7a: 681b ldr r3, [r3, #0] + 8003b7c: 68fa ldr r2, [r7, #12] + 8003b7e: 609a str r2, [r3, #8] + + switch (sClockSourceConfig->ClockSource) + 8003b80: 683b ldr r3, [r7, #0] + 8003b82: 681b ldr r3, [r3, #0] + 8003b84: 2b40 cmp r3, #64 ; 0x40 + 8003b86: d067 beq.n 8003c58 + 8003b88: 2b40 cmp r3, #64 ; 0x40 + 8003b8a: d80b bhi.n 8003ba4 + 8003b8c: 2b10 cmp r3, #16 + 8003b8e: d073 beq.n 8003c78 + 8003b90: 2b10 cmp r3, #16 + 8003b92: d802 bhi.n 8003b9a + 8003b94: 2b00 cmp r3, #0 + 8003b96: d06f beq.n 8003c78 + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + break; + 8003b98: e078 b.n 8003c8c + switch (sClockSourceConfig->ClockSource) + 8003b9a: 2b20 cmp r3, #32 + 8003b9c: d06c beq.n 8003c78 + 8003b9e: 2b30 cmp r3, #48 ; 0x30 + 8003ba0: d06a beq.n 8003c78 + break; + 8003ba2: e073 b.n 8003c8c + switch (sClockSourceConfig->ClockSource) + 8003ba4: 2b70 cmp r3, #112 ; 0x70 + 8003ba6: d00d beq.n 8003bc4 + 8003ba8: 2b70 cmp r3, #112 ; 0x70 + 8003baa: d804 bhi.n 8003bb6 + 8003bac: 2b50 cmp r3, #80 ; 0x50 + 8003bae: d033 beq.n 8003c18 + 8003bb0: 2b60 cmp r3, #96 ; 0x60 + 8003bb2: d041 beq.n 8003c38 + break; + 8003bb4: e06a b.n 8003c8c + switch (sClockSourceConfig->ClockSource) + 8003bb6: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8003bba: d066 beq.n 8003c8a + 8003bbc: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 8003bc0: d017 beq.n 8003bf2 + break; + 8003bc2: e063 b.n 8003c8c + TIM_ETR_SetConfig(htim->Instance, + 8003bc4: 687b ldr r3, [r7, #4] + 8003bc6: 6818 ldr r0, [r3, #0] + 8003bc8: 683b ldr r3, [r7, #0] + 8003bca: 6899 ldr r1, [r3, #8] + 8003bcc: 683b ldr r3, [r7, #0] + 8003bce: 685a ldr r2, [r3, #4] + 8003bd0: 683b ldr r3, [r7, #0] + 8003bd2: 68db ldr r3, [r3, #12] + 8003bd4: f000 fc0a bl 80043ec + tmpsmcr = htim->Instance->SMCR; + 8003bd8: 687b ldr r3, [r7, #4] + 8003bda: 681b ldr r3, [r3, #0] + 8003bdc: 689b ldr r3, [r3, #8] + 8003bde: 60fb str r3, [r7, #12] + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + 8003be0: 68fb ldr r3, [r7, #12] + 8003be2: f043 0377 orr.w r3, r3, #119 ; 0x77 + 8003be6: 60fb str r3, [r7, #12] + htim->Instance->SMCR = tmpsmcr; + 8003be8: 687b ldr r3, [r7, #4] + 8003bea: 681b ldr r3, [r3, #0] + 8003bec: 68fa ldr r2, [r7, #12] + 8003bee: 609a str r2, [r3, #8] + break; + 8003bf0: e04c b.n 8003c8c + TIM_ETR_SetConfig(htim->Instance, + 8003bf2: 687b ldr r3, [r7, #4] + 8003bf4: 6818 ldr r0, [r3, #0] + 8003bf6: 683b ldr r3, [r7, #0] + 8003bf8: 6899 ldr r1, [r3, #8] + 8003bfa: 683b ldr r3, [r7, #0] + 8003bfc: 685a ldr r2, [r3, #4] + 8003bfe: 683b ldr r3, [r7, #0] + 8003c00: 68db ldr r3, [r3, #12] + 8003c02: f000 fbf3 bl 80043ec + htim->Instance->SMCR |= TIM_SMCR_ECE; + 8003c06: 687b ldr r3, [r7, #4] + 8003c08: 681b ldr r3, [r3, #0] + 8003c0a: 689a ldr r2, [r3, #8] + 8003c0c: 687b ldr r3, [r7, #4] + 8003c0e: 681b ldr r3, [r3, #0] + 8003c10: f442 4280 orr.w r2, r2, #16384 ; 0x4000 + 8003c14: 609a str r2, [r3, #8] + break; + 8003c16: e039 b.n 8003c8c + TIM_TI1_ConfigInputStage(htim->Instance, + 8003c18: 687b ldr r3, [r7, #4] + 8003c1a: 6818 ldr r0, [r3, #0] + 8003c1c: 683b ldr r3, [r7, #0] + 8003c1e: 6859 ldr r1, [r3, #4] + 8003c20: 683b ldr r3, [r7, #0] + 8003c22: 68db ldr r3, [r3, #12] + 8003c24: 461a mov r2, r3 + 8003c26: f000 fb67 bl 80042f8 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + 8003c2a: 687b ldr r3, [r7, #4] + 8003c2c: 681b ldr r3, [r3, #0] + 8003c2e: 2150 movs r1, #80 ; 0x50 + 8003c30: 4618 mov r0, r3 + 8003c32: f000 fbc0 bl 80043b6 + break; + 8003c36: e029 b.n 8003c8c + TIM_TI2_ConfigInputStage(htim->Instance, + 8003c38: 687b ldr r3, [r7, #4] + 8003c3a: 6818 ldr r0, [r3, #0] + 8003c3c: 683b ldr r3, [r7, #0] + 8003c3e: 6859 ldr r1, [r3, #4] + 8003c40: 683b ldr r3, [r7, #0] + 8003c42: 68db ldr r3, [r3, #12] + 8003c44: 461a mov r2, r3 + 8003c46: f000 fb86 bl 8004356 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + 8003c4a: 687b ldr r3, [r7, #4] + 8003c4c: 681b ldr r3, [r3, #0] + 8003c4e: 2160 movs r1, #96 ; 0x60 + 8003c50: 4618 mov r0, r3 + 8003c52: f000 fbb0 bl 80043b6 + break; + 8003c56: e019 b.n 8003c8c + TIM_TI1_ConfigInputStage(htim->Instance, + 8003c58: 687b ldr r3, [r7, #4] + 8003c5a: 6818 ldr r0, [r3, #0] + 8003c5c: 683b ldr r3, [r7, #0] + 8003c5e: 6859 ldr r1, [r3, #4] + 8003c60: 683b ldr r3, [r7, #0] + 8003c62: 68db ldr r3, [r3, #12] + 8003c64: 461a mov r2, r3 + 8003c66: f000 fb47 bl 80042f8 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + 8003c6a: 687b ldr r3, [r7, #4] + 8003c6c: 681b ldr r3, [r3, #0] + 8003c6e: 2140 movs r1, #64 ; 0x40 + 8003c70: 4618 mov r0, r3 + 8003c72: f000 fba0 bl 80043b6 + break; + 8003c76: e009 b.n 8003c8c + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + 8003c78: 687b ldr r3, [r7, #4] + 8003c7a: 681a ldr r2, [r3, #0] + 8003c7c: 683b ldr r3, [r7, #0] + 8003c7e: 681b ldr r3, [r3, #0] + 8003c80: 4619 mov r1, r3 + 8003c82: 4610 mov r0, r2 + 8003c84: f000 fb97 bl 80043b6 + break; + 8003c88: e000 b.n 8003c8c + break; + 8003c8a: bf00 nop + } + htim->State = HAL_TIM_STATE_READY; + 8003c8c: 687b ldr r3, [r7, #4] + 8003c8e: 2201 movs r2, #1 + 8003c90: f883 203d strb.w r2, [r3, #61] ; 0x3d + + __HAL_UNLOCK(htim); + 8003c94: 687b ldr r3, [r7, #4] + 8003c96: 2200 movs r2, #0 + 8003c98: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_OK; + 8003c9c: 2300 movs r3, #0 +} + 8003c9e: 4618 mov r0, r3 + 8003ca0: 3710 adds r7, #16 + 8003ca2: 46bd mov sp, r7 + 8003ca4: bd80 pop {r7, pc} + 8003ca6: bf00 nop + 8003ca8: fffeff88 .word 0xfffeff88 + +08003cac : + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + 8003cac: b480 push {r7} + 8003cae: b083 sub sp, #12 + 8003cb0: af00 add r7, sp, #0 + 8003cb2: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + 8003cb4: bf00 nop + 8003cb6: 370c adds r7, #12 + 8003cb8: 46bd mov sp, r7 + 8003cba: f85d 7b04 ldr.w r7, [sp], #4 + 8003cbe: 4770 bx lr + +08003cc0 : + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + 8003cc0: b480 push {r7} + 8003cc2: b083 sub sp, #12 + 8003cc4: af00 add r7, sp, #0 + 8003cc6: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + 8003cc8: bf00 nop + 8003cca: 370c adds r7, #12 + 8003ccc: 46bd mov sp, r7 + 8003cce: f85d 7b04 ldr.w r7, [sp], #4 + 8003cd2: 4770 bx lr + +08003cd4 : + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + 8003cd4: b480 push {r7} + 8003cd6: b083 sub sp, #12 + 8003cd8: af00 add r7, sp, #0 + 8003cda: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + 8003cdc: bf00 nop + 8003cde: 370c adds r7, #12 + 8003ce0: 46bd mov sp, r7 + 8003ce2: f85d 7b04 ldr.w r7, [sp], #4 + 8003ce6: 4770 bx lr + +08003ce8 : + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + 8003ce8: b480 push {r7} + 8003cea: b083 sub sp, #12 + 8003cec: af00 add r7, sp, #0 + 8003cee: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + 8003cf0: bf00 nop + 8003cf2: 370c adds r7, #12 + 8003cf4: 46bd mov sp, r7 + 8003cf6: f85d 7b04 ldr.w r7, [sp], #4 + 8003cfa: 4770 bx lr + +08003cfc : + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + 8003cfc: b480 push {r7} + 8003cfe: b085 sub sp, #20 + 8003d00: af00 add r7, sp, #0 + 8003d02: 6078 str r0, [r7, #4] + 8003d04: 6039 str r1, [r7, #0] + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + 8003d06: 687b ldr r3, [r7, #4] + 8003d08: 681b ldr r3, [r3, #0] + 8003d0a: 60fb str r3, [r7, #12] + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + 8003d0c: 687b ldr r3, [r7, #4] + 8003d0e: 4a40 ldr r2, [pc, #256] ; (8003e10 ) + 8003d10: 4293 cmp r3, r2 + 8003d12: d013 beq.n 8003d3c + 8003d14: 687b ldr r3, [r7, #4] + 8003d16: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 8003d1a: d00f beq.n 8003d3c + 8003d1c: 687b ldr r3, [r7, #4] + 8003d1e: 4a3d ldr r2, [pc, #244] ; (8003e14 ) + 8003d20: 4293 cmp r3, r2 + 8003d22: d00b beq.n 8003d3c + 8003d24: 687b ldr r3, [r7, #4] + 8003d26: 4a3c ldr r2, [pc, #240] ; (8003e18 ) + 8003d28: 4293 cmp r3, r2 + 8003d2a: d007 beq.n 8003d3c + 8003d2c: 687b ldr r3, [r7, #4] + 8003d2e: 4a3b ldr r2, [pc, #236] ; (8003e1c ) + 8003d30: 4293 cmp r3, r2 + 8003d32: d003 beq.n 8003d3c + 8003d34: 687b ldr r3, [r7, #4] + 8003d36: 4a3a ldr r2, [pc, #232] ; (8003e20 ) + 8003d38: 4293 cmp r3, r2 + 8003d3a: d108 bne.n 8003d4e + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + 8003d3c: 68fb ldr r3, [r7, #12] + 8003d3e: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8003d42: 60fb str r3, [r7, #12] + tmpcr1 |= Structure->CounterMode; + 8003d44: 683b ldr r3, [r7, #0] + 8003d46: 685b ldr r3, [r3, #4] + 8003d48: 68fa ldr r2, [r7, #12] + 8003d4a: 4313 orrs r3, r2 + 8003d4c: 60fb str r3, [r7, #12] + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + 8003d4e: 687b ldr r3, [r7, #4] + 8003d50: 4a2f ldr r2, [pc, #188] ; (8003e10 ) + 8003d52: 4293 cmp r3, r2 + 8003d54: d02b beq.n 8003dae + 8003d56: 687b ldr r3, [r7, #4] + 8003d58: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 8003d5c: d027 beq.n 8003dae + 8003d5e: 687b ldr r3, [r7, #4] + 8003d60: 4a2c ldr r2, [pc, #176] ; (8003e14 ) + 8003d62: 4293 cmp r3, r2 + 8003d64: d023 beq.n 8003dae + 8003d66: 687b ldr r3, [r7, #4] + 8003d68: 4a2b ldr r2, [pc, #172] ; (8003e18 ) + 8003d6a: 4293 cmp r3, r2 + 8003d6c: d01f beq.n 8003dae + 8003d6e: 687b ldr r3, [r7, #4] + 8003d70: 4a2a ldr r2, [pc, #168] ; (8003e1c ) + 8003d72: 4293 cmp r3, r2 + 8003d74: d01b beq.n 8003dae + 8003d76: 687b ldr r3, [r7, #4] + 8003d78: 4a29 ldr r2, [pc, #164] ; (8003e20 ) + 8003d7a: 4293 cmp r3, r2 + 8003d7c: d017 beq.n 8003dae + 8003d7e: 687b ldr r3, [r7, #4] + 8003d80: 4a28 ldr r2, [pc, #160] ; (8003e24 ) + 8003d82: 4293 cmp r3, r2 + 8003d84: d013 beq.n 8003dae + 8003d86: 687b ldr r3, [r7, #4] + 8003d88: 4a27 ldr r2, [pc, #156] ; (8003e28 ) + 8003d8a: 4293 cmp r3, r2 + 8003d8c: d00f beq.n 8003dae + 8003d8e: 687b ldr r3, [r7, #4] + 8003d90: 4a26 ldr r2, [pc, #152] ; (8003e2c ) + 8003d92: 4293 cmp r3, r2 + 8003d94: d00b beq.n 8003dae + 8003d96: 687b ldr r3, [r7, #4] + 8003d98: 4a25 ldr r2, [pc, #148] ; (8003e30 ) + 8003d9a: 4293 cmp r3, r2 + 8003d9c: d007 beq.n 8003dae + 8003d9e: 687b ldr r3, [r7, #4] + 8003da0: 4a24 ldr r2, [pc, #144] ; (8003e34 ) + 8003da2: 4293 cmp r3, r2 + 8003da4: d003 beq.n 8003dae + 8003da6: 687b ldr r3, [r7, #4] + 8003da8: 4a23 ldr r2, [pc, #140] ; (8003e38 ) + 8003daa: 4293 cmp r3, r2 + 8003dac: d108 bne.n 8003dc0 + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + 8003dae: 68fb ldr r3, [r7, #12] + 8003db0: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8003db4: 60fb str r3, [r7, #12] + tmpcr1 |= (uint32_t)Structure->ClockDivision; + 8003db6: 683b ldr r3, [r7, #0] + 8003db8: 68db ldr r3, [r3, #12] + 8003dba: 68fa ldr r2, [r7, #12] + 8003dbc: 4313 orrs r3, r2 + 8003dbe: 60fb str r3, [r7, #12] + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + 8003dc0: 68fb ldr r3, [r7, #12] + 8003dc2: f023 0280 bic.w r2, r3, #128 ; 0x80 + 8003dc6: 683b ldr r3, [r7, #0] + 8003dc8: 695b ldr r3, [r3, #20] + 8003dca: 4313 orrs r3, r2 + 8003dcc: 60fb str r3, [r7, #12] + + TIMx->CR1 = tmpcr1; + 8003dce: 687b ldr r3, [r7, #4] + 8003dd0: 68fa ldr r2, [r7, #12] + 8003dd2: 601a str r2, [r3, #0] + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + 8003dd4: 683b ldr r3, [r7, #0] + 8003dd6: 689a ldr r2, [r3, #8] + 8003dd8: 687b ldr r3, [r7, #4] + 8003dda: 62da str r2, [r3, #44] ; 0x2c + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + 8003ddc: 683b ldr r3, [r7, #0] + 8003dde: 681a ldr r2, [r3, #0] + 8003de0: 687b ldr r3, [r7, #4] + 8003de2: 629a str r2, [r3, #40] ; 0x28 + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + 8003de4: 687b ldr r3, [r7, #4] + 8003de6: 4a0a ldr r2, [pc, #40] ; (8003e10 ) + 8003de8: 4293 cmp r3, r2 + 8003dea: d003 beq.n 8003df4 + 8003dec: 687b ldr r3, [r7, #4] + 8003dee: 4a0c ldr r2, [pc, #48] ; (8003e20 ) + 8003df0: 4293 cmp r3, r2 + 8003df2: d103 bne.n 8003dfc + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + 8003df4: 683b ldr r3, [r7, #0] + 8003df6: 691a ldr r2, [r3, #16] + 8003df8: 687b ldr r3, [r7, #4] + 8003dfa: 631a str r2, [r3, #48] ; 0x30 + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + 8003dfc: 687b ldr r3, [r7, #4] + 8003dfe: 2201 movs r2, #1 + 8003e00: 615a str r2, [r3, #20] +} + 8003e02: bf00 nop + 8003e04: 3714 adds r7, #20 + 8003e06: 46bd mov sp, r7 + 8003e08: f85d 7b04 ldr.w r7, [sp], #4 + 8003e0c: 4770 bx lr + 8003e0e: bf00 nop + 8003e10: 40010000 .word 0x40010000 + 8003e14: 40000400 .word 0x40000400 + 8003e18: 40000800 .word 0x40000800 + 8003e1c: 40000c00 .word 0x40000c00 + 8003e20: 40010400 .word 0x40010400 + 8003e24: 40014000 .word 0x40014000 + 8003e28: 40014400 .word 0x40014400 + 8003e2c: 40014800 .word 0x40014800 + 8003e30: 40001800 .word 0x40001800 + 8003e34: 40001c00 .word 0x40001c00 + 8003e38: 40002000 .word 0x40002000 + +08003e3c : + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 8003e3c: b480 push {r7} + 8003e3e: b087 sub sp, #28 + 8003e40: af00 add r7, sp, #0 + 8003e42: 6078 str r0, [r7, #4] + 8003e44: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + 8003e46: 687b ldr r3, [r7, #4] + 8003e48: 6a1b ldr r3, [r3, #32] + 8003e4a: f023 0201 bic.w r2, r3, #1 + 8003e4e: 687b ldr r3, [r7, #4] + 8003e50: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8003e52: 687b ldr r3, [r7, #4] + 8003e54: 6a1b ldr r3, [r3, #32] + 8003e56: 617b str r3, [r7, #20] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8003e58: 687b ldr r3, [r7, #4] + 8003e5a: 685b ldr r3, [r3, #4] + 8003e5c: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 8003e5e: 687b ldr r3, [r7, #4] + 8003e60: 699b ldr r3, [r3, #24] + 8003e62: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + 8003e64: 68fa ldr r2, [r7, #12] + 8003e66: 4b2b ldr r3, [pc, #172] ; (8003f14 ) + 8003e68: 4013 ands r3, r2 + 8003e6a: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC1S; + 8003e6c: 68fb ldr r3, [r7, #12] + 8003e6e: f023 0303 bic.w r3, r3, #3 + 8003e72: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 8003e74: 683b ldr r3, [r7, #0] + 8003e76: 681b ldr r3, [r3, #0] + 8003e78: 68fa ldr r2, [r7, #12] + 8003e7a: 4313 orrs r3, r2 + 8003e7c: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + 8003e7e: 697b ldr r3, [r7, #20] + 8003e80: f023 0302 bic.w r3, r3, #2 + 8003e84: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + 8003e86: 683b ldr r3, [r7, #0] + 8003e88: 689b ldr r3, [r3, #8] + 8003e8a: 697a ldr r2, [r7, #20] + 8003e8c: 4313 orrs r3, r2 + 8003e8e: 617b str r3, [r7, #20] + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + 8003e90: 687b ldr r3, [r7, #4] + 8003e92: 4a21 ldr r2, [pc, #132] ; (8003f18 ) + 8003e94: 4293 cmp r3, r2 + 8003e96: d003 beq.n 8003ea0 + 8003e98: 687b ldr r3, [r7, #4] + 8003e9a: 4a20 ldr r2, [pc, #128] ; (8003f1c ) + 8003e9c: 4293 cmp r3, r2 + 8003e9e: d10c bne.n 8003eba + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + 8003ea0: 697b ldr r3, [r7, #20] + 8003ea2: f023 0308 bic.w r3, r3, #8 + 8003ea6: 617b str r3, [r7, #20] + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + 8003ea8: 683b ldr r3, [r7, #0] + 8003eaa: 68db ldr r3, [r3, #12] + 8003eac: 697a ldr r2, [r7, #20] + 8003eae: 4313 orrs r3, r2 + 8003eb0: 617b str r3, [r7, #20] + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + 8003eb2: 697b ldr r3, [r7, #20] + 8003eb4: f023 0304 bic.w r3, r3, #4 + 8003eb8: 617b str r3, [r7, #20] + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 8003eba: 687b ldr r3, [r7, #4] + 8003ebc: 4a16 ldr r2, [pc, #88] ; (8003f18 ) + 8003ebe: 4293 cmp r3, r2 + 8003ec0: d003 beq.n 8003eca + 8003ec2: 687b ldr r3, [r7, #4] + 8003ec4: 4a15 ldr r2, [pc, #84] ; (8003f1c ) + 8003ec6: 4293 cmp r3, r2 + 8003ec8: d111 bne.n 8003eee + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + 8003eca: 693b ldr r3, [r7, #16] + 8003ecc: f423 7380 bic.w r3, r3, #256 ; 0x100 + 8003ed0: 613b str r3, [r7, #16] + tmpcr2 &= ~TIM_CR2_OIS1N; + 8003ed2: 693b ldr r3, [r7, #16] + 8003ed4: f423 7300 bic.w r3, r3, #512 ; 0x200 + 8003ed8: 613b str r3, [r7, #16] + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + 8003eda: 683b ldr r3, [r7, #0] + 8003edc: 695b ldr r3, [r3, #20] + 8003ede: 693a ldr r2, [r7, #16] + 8003ee0: 4313 orrs r3, r2 + 8003ee2: 613b str r3, [r7, #16] + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + 8003ee4: 683b ldr r3, [r7, #0] + 8003ee6: 699b ldr r3, [r3, #24] + 8003ee8: 693a ldr r2, [r7, #16] + 8003eea: 4313 orrs r3, r2 + 8003eec: 613b str r3, [r7, #16] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8003eee: 687b ldr r3, [r7, #4] + 8003ef0: 693a ldr r2, [r7, #16] + 8003ef2: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8003ef4: 687b ldr r3, [r7, #4] + 8003ef6: 68fa ldr r2, [r7, #12] + 8003ef8: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + 8003efa: 683b ldr r3, [r7, #0] + 8003efc: 685a ldr r2, [r3, #4] + 8003efe: 687b ldr r3, [r7, #4] + 8003f00: 635a str r2, [r3, #52] ; 0x34 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8003f02: 687b ldr r3, [r7, #4] + 8003f04: 697a ldr r2, [r7, #20] + 8003f06: 621a str r2, [r3, #32] +} + 8003f08: bf00 nop + 8003f0a: 371c adds r7, #28 + 8003f0c: 46bd mov sp, r7 + 8003f0e: f85d 7b04 ldr.w r7, [sp], #4 + 8003f12: 4770 bx lr + 8003f14: fffeff8f .word 0xfffeff8f + 8003f18: 40010000 .word 0x40010000 + 8003f1c: 40010400 .word 0x40010400 + +08003f20 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 8003f20: b480 push {r7} + 8003f22: b087 sub sp, #28 + 8003f24: af00 add r7, sp, #0 + 8003f26: 6078 str r0, [r7, #4] + 8003f28: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + 8003f2a: 687b ldr r3, [r7, #4] + 8003f2c: 6a1b ldr r3, [r3, #32] + 8003f2e: f023 0210 bic.w r2, r3, #16 + 8003f32: 687b ldr r3, [r7, #4] + 8003f34: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8003f36: 687b ldr r3, [r7, #4] + 8003f38: 6a1b ldr r3, [r3, #32] + 8003f3a: 617b str r3, [r7, #20] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8003f3c: 687b ldr r3, [r7, #4] + 8003f3e: 685b ldr r3, [r3, #4] + 8003f40: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 8003f42: 687b ldr r3, [r7, #4] + 8003f44: 699b ldr r3, [r3, #24] + 8003f46: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + 8003f48: 68fa ldr r2, [r7, #12] + 8003f4a: 4b2e ldr r3, [pc, #184] ; (8004004 ) + 8003f4c: 4013 ands r3, r2 + 8003f4e: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC2S; + 8003f50: 68fb ldr r3, [r7, #12] + 8003f52: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8003f56: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 8003f58: 683b ldr r3, [r7, #0] + 8003f5a: 681b ldr r3, [r3, #0] + 8003f5c: 021b lsls r3, r3, #8 + 8003f5e: 68fa ldr r2, [r7, #12] + 8003f60: 4313 orrs r3, r2 + 8003f62: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + 8003f64: 697b ldr r3, [r7, #20] + 8003f66: f023 0320 bic.w r3, r3, #32 + 8003f6a: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + 8003f6c: 683b ldr r3, [r7, #0] + 8003f6e: 689b ldr r3, [r3, #8] + 8003f70: 011b lsls r3, r3, #4 + 8003f72: 697a ldr r2, [r7, #20] + 8003f74: 4313 orrs r3, r2 + 8003f76: 617b str r3, [r7, #20] + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + 8003f78: 687b ldr r3, [r7, #4] + 8003f7a: 4a23 ldr r2, [pc, #140] ; (8004008 ) + 8003f7c: 4293 cmp r3, r2 + 8003f7e: d003 beq.n 8003f88 + 8003f80: 687b ldr r3, [r7, #4] + 8003f82: 4a22 ldr r2, [pc, #136] ; (800400c ) + 8003f84: 4293 cmp r3, r2 + 8003f86: d10d bne.n 8003fa4 + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + 8003f88: 697b ldr r3, [r7, #20] + 8003f8a: f023 0380 bic.w r3, r3, #128 ; 0x80 + 8003f8e: 617b str r3, [r7, #20] + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + 8003f90: 683b ldr r3, [r7, #0] + 8003f92: 68db ldr r3, [r3, #12] + 8003f94: 011b lsls r3, r3, #4 + 8003f96: 697a ldr r2, [r7, #20] + 8003f98: 4313 orrs r3, r2 + 8003f9a: 617b str r3, [r7, #20] + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + 8003f9c: 697b ldr r3, [r7, #20] + 8003f9e: f023 0340 bic.w r3, r3, #64 ; 0x40 + 8003fa2: 617b str r3, [r7, #20] + + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 8003fa4: 687b ldr r3, [r7, #4] + 8003fa6: 4a18 ldr r2, [pc, #96] ; (8004008 ) + 8003fa8: 4293 cmp r3, r2 + 8003faa: d003 beq.n 8003fb4 + 8003fac: 687b ldr r3, [r7, #4] + 8003fae: 4a17 ldr r2, [pc, #92] ; (800400c ) + 8003fb0: 4293 cmp r3, r2 + 8003fb2: d113 bne.n 8003fdc + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + 8003fb4: 693b ldr r3, [r7, #16] + 8003fb6: f423 6380 bic.w r3, r3, #1024 ; 0x400 + 8003fba: 613b str r3, [r7, #16] + tmpcr2 &= ~TIM_CR2_OIS2N; + 8003fbc: 693b ldr r3, [r7, #16] + 8003fbe: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 8003fc2: 613b str r3, [r7, #16] + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + 8003fc4: 683b ldr r3, [r7, #0] + 8003fc6: 695b ldr r3, [r3, #20] + 8003fc8: 009b lsls r3, r3, #2 + 8003fca: 693a ldr r2, [r7, #16] + 8003fcc: 4313 orrs r3, r2 + 8003fce: 613b str r3, [r7, #16] + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + 8003fd0: 683b ldr r3, [r7, #0] + 8003fd2: 699b ldr r3, [r3, #24] + 8003fd4: 009b lsls r3, r3, #2 + 8003fd6: 693a ldr r2, [r7, #16] + 8003fd8: 4313 orrs r3, r2 + 8003fda: 613b str r3, [r7, #16] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8003fdc: 687b ldr r3, [r7, #4] + 8003fde: 693a ldr r2, [r7, #16] + 8003fe0: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8003fe2: 687b ldr r3, [r7, #4] + 8003fe4: 68fa ldr r2, [r7, #12] + 8003fe6: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + 8003fe8: 683b ldr r3, [r7, #0] + 8003fea: 685a ldr r2, [r3, #4] + 8003fec: 687b ldr r3, [r7, #4] + 8003fee: 639a str r2, [r3, #56] ; 0x38 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8003ff0: 687b ldr r3, [r7, #4] + 8003ff2: 697a ldr r2, [r7, #20] + 8003ff4: 621a str r2, [r3, #32] +} + 8003ff6: bf00 nop + 8003ff8: 371c adds r7, #28 + 8003ffa: 46bd mov sp, r7 + 8003ffc: f85d 7b04 ldr.w r7, [sp], #4 + 8004000: 4770 bx lr + 8004002: bf00 nop + 8004004: feff8fff .word 0xfeff8fff + 8004008: 40010000 .word 0x40010000 + 800400c: 40010400 .word 0x40010400 + +08004010 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 8004010: b480 push {r7} + 8004012: b087 sub sp, #28 + 8004014: af00 add r7, sp, #0 + 8004016: 6078 str r0, [r7, #4] + 8004018: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + 800401a: 687b ldr r3, [r7, #4] + 800401c: 6a1b ldr r3, [r3, #32] + 800401e: f423 7280 bic.w r2, r3, #256 ; 0x100 + 8004022: 687b ldr r3, [r7, #4] + 8004024: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8004026: 687b ldr r3, [r7, #4] + 8004028: 6a1b ldr r3, [r3, #32] + 800402a: 617b str r3, [r7, #20] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 800402c: 687b ldr r3, [r7, #4] + 800402e: 685b ldr r3, [r3, #4] + 8004030: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 8004032: 687b ldr r3, [r7, #4] + 8004034: 69db ldr r3, [r3, #28] + 8004036: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + 8004038: 68fa ldr r2, [r7, #12] + 800403a: 4b2d ldr r3, [pc, #180] ; (80040f0 ) + 800403c: 4013 ands r3, r2 + 800403e: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC3S; + 8004040: 68fb ldr r3, [r7, #12] + 8004042: f023 0303 bic.w r3, r3, #3 + 8004046: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 8004048: 683b ldr r3, [r7, #0] + 800404a: 681b ldr r3, [r3, #0] + 800404c: 68fa ldr r2, [r7, #12] + 800404e: 4313 orrs r3, r2 + 8004050: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + 8004052: 697b ldr r3, [r7, #20] + 8004054: f423 7300 bic.w r3, r3, #512 ; 0x200 + 8004058: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + 800405a: 683b ldr r3, [r7, #0] + 800405c: 689b ldr r3, [r3, #8] + 800405e: 021b lsls r3, r3, #8 + 8004060: 697a ldr r2, [r7, #20] + 8004062: 4313 orrs r3, r2 + 8004064: 617b str r3, [r7, #20] + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + 8004066: 687b ldr r3, [r7, #4] + 8004068: 4a22 ldr r2, [pc, #136] ; (80040f4 ) + 800406a: 4293 cmp r3, r2 + 800406c: d003 beq.n 8004076 + 800406e: 687b ldr r3, [r7, #4] + 8004070: 4a21 ldr r2, [pc, #132] ; (80040f8 ) + 8004072: 4293 cmp r3, r2 + 8004074: d10d bne.n 8004092 + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + 8004076: 697b ldr r3, [r7, #20] + 8004078: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 800407c: 617b str r3, [r7, #20] + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + 800407e: 683b ldr r3, [r7, #0] + 8004080: 68db ldr r3, [r3, #12] + 8004082: 021b lsls r3, r3, #8 + 8004084: 697a ldr r2, [r7, #20] + 8004086: 4313 orrs r3, r2 + 8004088: 617b str r3, [r7, #20] + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + 800408a: 697b ldr r3, [r7, #20] + 800408c: f423 6380 bic.w r3, r3, #1024 ; 0x400 + 8004090: 617b str r3, [r7, #20] + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 8004092: 687b ldr r3, [r7, #4] + 8004094: 4a17 ldr r2, [pc, #92] ; (80040f4 ) + 8004096: 4293 cmp r3, r2 + 8004098: d003 beq.n 80040a2 + 800409a: 687b ldr r3, [r7, #4] + 800409c: 4a16 ldr r2, [pc, #88] ; (80040f8 ) + 800409e: 4293 cmp r3, r2 + 80040a0: d113 bne.n 80040ca + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + 80040a2: 693b ldr r3, [r7, #16] + 80040a4: f423 5380 bic.w r3, r3, #4096 ; 0x1000 + 80040a8: 613b str r3, [r7, #16] + tmpcr2 &= ~TIM_CR2_OIS3N; + 80040aa: 693b ldr r3, [r7, #16] + 80040ac: f423 5300 bic.w r3, r3, #8192 ; 0x2000 + 80040b0: 613b str r3, [r7, #16] + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + 80040b2: 683b ldr r3, [r7, #0] + 80040b4: 695b ldr r3, [r3, #20] + 80040b6: 011b lsls r3, r3, #4 + 80040b8: 693a ldr r2, [r7, #16] + 80040ba: 4313 orrs r3, r2 + 80040bc: 613b str r3, [r7, #16] + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + 80040be: 683b ldr r3, [r7, #0] + 80040c0: 699b ldr r3, [r3, #24] + 80040c2: 011b lsls r3, r3, #4 + 80040c4: 693a ldr r2, [r7, #16] + 80040c6: 4313 orrs r3, r2 + 80040c8: 613b str r3, [r7, #16] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 80040ca: 687b ldr r3, [r7, #4] + 80040cc: 693a ldr r2, [r7, #16] + 80040ce: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 80040d0: 687b ldr r3, [r7, #4] + 80040d2: 68fa ldr r2, [r7, #12] + 80040d4: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + 80040d6: 683b ldr r3, [r7, #0] + 80040d8: 685a ldr r2, [r3, #4] + 80040da: 687b ldr r3, [r7, #4] + 80040dc: 63da str r2, [r3, #60] ; 0x3c + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 80040de: 687b ldr r3, [r7, #4] + 80040e0: 697a ldr r2, [r7, #20] + 80040e2: 621a str r2, [r3, #32] +} + 80040e4: bf00 nop + 80040e6: 371c adds r7, #28 + 80040e8: 46bd mov sp, r7 + 80040ea: f85d 7b04 ldr.w r7, [sp], #4 + 80040ee: 4770 bx lr + 80040f0: fffeff8f .word 0xfffeff8f + 80040f4: 40010000 .word 0x40010000 + 80040f8: 40010400 .word 0x40010400 + +080040fc : + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 80040fc: b480 push {r7} + 80040fe: b087 sub sp, #28 + 8004100: af00 add r7, sp, #0 + 8004102: 6078 str r0, [r7, #4] + 8004104: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + 8004106: 687b ldr r3, [r7, #4] + 8004108: 6a1b ldr r3, [r3, #32] + 800410a: f423 5280 bic.w r2, r3, #4096 ; 0x1000 + 800410e: 687b ldr r3, [r7, #4] + 8004110: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8004112: 687b ldr r3, [r7, #4] + 8004114: 6a1b ldr r3, [r3, #32] + 8004116: 613b str r3, [r7, #16] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8004118: 687b ldr r3, [r7, #4] + 800411a: 685b ldr r3, [r3, #4] + 800411c: 617b str r3, [r7, #20] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 800411e: 687b ldr r3, [r7, #4] + 8004120: 69db ldr r3, [r3, #28] + 8004122: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + 8004124: 68fa ldr r2, [r7, #12] + 8004126: 4b1e ldr r3, [pc, #120] ; (80041a0 ) + 8004128: 4013 ands r3, r2 + 800412a: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC4S; + 800412c: 68fb ldr r3, [r7, #12] + 800412e: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8004132: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 8004134: 683b ldr r3, [r7, #0] + 8004136: 681b ldr r3, [r3, #0] + 8004138: 021b lsls r3, r3, #8 + 800413a: 68fa ldr r2, [r7, #12] + 800413c: 4313 orrs r3, r2 + 800413e: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + 8004140: 693b ldr r3, [r7, #16] + 8004142: f423 5300 bic.w r3, r3, #8192 ; 0x2000 + 8004146: 613b str r3, [r7, #16] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + 8004148: 683b ldr r3, [r7, #0] + 800414a: 689b ldr r3, [r3, #8] + 800414c: 031b lsls r3, r3, #12 + 800414e: 693a ldr r2, [r7, #16] + 8004150: 4313 orrs r3, r2 + 8004152: 613b str r3, [r7, #16] + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 8004154: 687b ldr r3, [r7, #4] + 8004156: 4a13 ldr r2, [pc, #76] ; (80041a4 ) + 8004158: 4293 cmp r3, r2 + 800415a: d003 beq.n 8004164 + 800415c: 687b ldr r3, [r7, #4] + 800415e: 4a12 ldr r2, [pc, #72] ; (80041a8 ) + 8004160: 4293 cmp r3, r2 + 8004162: d109 bne.n 8004178 + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + 8004164: 697b ldr r3, [r7, #20] + 8004166: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 800416a: 617b str r3, [r7, #20] + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + 800416c: 683b ldr r3, [r7, #0] + 800416e: 695b ldr r3, [r3, #20] + 8004170: 019b lsls r3, r3, #6 + 8004172: 697a ldr r2, [r7, #20] + 8004174: 4313 orrs r3, r2 + 8004176: 617b str r3, [r7, #20] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8004178: 687b ldr r3, [r7, #4] + 800417a: 697a ldr r2, [r7, #20] + 800417c: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 800417e: 687b ldr r3, [r7, #4] + 8004180: 68fa ldr r2, [r7, #12] + 8004182: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + 8004184: 683b ldr r3, [r7, #0] + 8004186: 685a ldr r2, [r3, #4] + 8004188: 687b ldr r3, [r7, #4] + 800418a: 641a str r2, [r3, #64] ; 0x40 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 800418c: 687b ldr r3, [r7, #4] + 800418e: 693a ldr r2, [r7, #16] + 8004190: 621a str r2, [r3, #32] +} + 8004192: bf00 nop + 8004194: 371c adds r7, #28 + 8004196: 46bd mov sp, r7 + 8004198: f85d 7b04 ldr.w r7, [sp], #4 + 800419c: 4770 bx lr + 800419e: bf00 nop + 80041a0: feff8fff .word 0xfeff8fff + 80041a4: 40010000 .word 0x40010000 + 80041a8: 40010400 .word 0x40010400 + +080041ac : + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, + TIM_OC_InitTypeDef *OC_Config) +{ + 80041ac: b480 push {r7} + 80041ae: b087 sub sp, #28 + 80041b0: af00 add r7, sp, #0 + 80041b2: 6078 str r0, [r7, #4] + 80041b4: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC5E; + 80041b6: 687b ldr r3, [r7, #4] + 80041b8: 6a1b ldr r3, [r3, #32] + 80041ba: f423 3280 bic.w r2, r3, #65536 ; 0x10000 + 80041be: 687b ldr r3, [r7, #4] + 80041c0: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 80041c2: 687b ldr r3, [r7, #4] + 80041c4: 6a1b ldr r3, [r3, #32] + 80041c6: 613b str r3, [r7, #16] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 80041c8: 687b ldr r3, [r7, #4] + 80041ca: 685b ldr r3, [r3, #4] + 80041cc: 617b str r3, [r7, #20] + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + 80041ce: 687b ldr r3, [r7, #4] + 80041d0: 6d5b ldr r3, [r3, #84] ; 0x54 + 80041d2: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC5M); + 80041d4: 68fa ldr r2, [r7, #12] + 80041d6: 4b1b ldr r3, [pc, #108] ; (8004244 ) + 80041d8: 4013 ands r3, r2 + 80041da: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 80041dc: 683b ldr r3, [r7, #0] + 80041de: 681b ldr r3, [r3, #0] + 80041e0: 68fa ldr r2, [r7, #12] + 80041e2: 4313 orrs r3, r2 + 80041e4: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC5P; + 80041e6: 693b ldr r3, [r7, #16] + 80041e8: f423 3300 bic.w r3, r3, #131072 ; 0x20000 + 80041ec: 613b str r3, [r7, #16] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 16U); + 80041ee: 683b ldr r3, [r7, #0] + 80041f0: 689b ldr r3, [r3, #8] + 80041f2: 041b lsls r3, r3, #16 + 80041f4: 693a ldr r2, [r7, #16] + 80041f6: 4313 orrs r3, r2 + 80041f8: 613b str r3, [r7, #16] + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 80041fa: 687b ldr r3, [r7, #4] + 80041fc: 4a12 ldr r2, [pc, #72] ; (8004248 ) + 80041fe: 4293 cmp r3, r2 + 8004200: d003 beq.n 800420a + 8004202: 687b ldr r3, [r7, #4] + 8004204: 4a11 ldr r2, [pc, #68] ; (800424c ) + 8004206: 4293 cmp r3, r2 + 8004208: d109 bne.n 800421e + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS5; + 800420a: 697b ldr r3, [r7, #20] + 800420c: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8004210: 617b str r3, [r7, #20] + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 8U); + 8004212: 683b ldr r3, [r7, #0] + 8004214: 695b ldr r3, [r3, #20] + 8004216: 021b lsls r3, r3, #8 + 8004218: 697a ldr r2, [r7, #20] + 800421a: 4313 orrs r3, r2 + 800421c: 617b str r3, [r7, #20] + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 800421e: 687b ldr r3, [r7, #4] + 8004220: 697a ldr r2, [r7, #20] + 8004222: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + 8004224: 687b ldr r3, [r7, #4] + 8004226: 68fa ldr r2, [r7, #12] + 8004228: 655a str r2, [r3, #84] ; 0x54 + + /* Set the Capture Compare Register value */ + TIMx->CCR5 = OC_Config->Pulse; + 800422a: 683b ldr r3, [r7, #0] + 800422c: 685a ldr r2, [r3, #4] + 800422e: 687b ldr r3, [r7, #4] + 8004230: 659a str r2, [r3, #88] ; 0x58 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8004232: 687b ldr r3, [r7, #4] + 8004234: 693a ldr r2, [r7, #16] + 8004236: 621a str r2, [r3, #32] +} + 8004238: bf00 nop + 800423a: 371c adds r7, #28 + 800423c: 46bd mov sp, r7 + 800423e: f85d 7b04 ldr.w r7, [sp], #4 + 8004242: 4770 bx lr + 8004244: fffeff8f .word 0xfffeff8f + 8004248: 40010000 .word 0x40010000 + 800424c: 40010400 .word 0x40010400 + +08004250 : + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, + TIM_OC_InitTypeDef *OC_Config) +{ + 8004250: b480 push {r7} + 8004252: b087 sub sp, #28 + 8004254: af00 add r7, sp, #0 + 8004256: 6078 str r0, [r7, #4] + 8004258: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC6E; + 800425a: 687b ldr r3, [r7, #4] + 800425c: 6a1b ldr r3, [r3, #32] + 800425e: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 + 8004262: 687b ldr r3, [r7, #4] + 8004264: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8004266: 687b ldr r3, [r7, #4] + 8004268: 6a1b ldr r3, [r3, #32] + 800426a: 613b str r3, [r7, #16] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 800426c: 687b ldr r3, [r7, #4] + 800426e: 685b ldr r3, [r3, #4] + 8004270: 617b str r3, [r7, #20] + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + 8004272: 687b ldr r3, [r7, #4] + 8004274: 6d5b ldr r3, [r3, #84] ; 0x54 + 8004276: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC6M); + 8004278: 68fa ldr r2, [r7, #12] + 800427a: 4b1c ldr r3, [pc, #112] ; (80042ec ) + 800427c: 4013 ands r3, r2 + 800427e: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 8004280: 683b ldr r3, [r7, #0] + 8004282: 681b ldr r3, [r3, #0] + 8004284: 021b lsls r3, r3, #8 + 8004286: 68fa ldr r2, [r7, #12] + 8004288: 4313 orrs r3, r2 + 800428a: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)~TIM_CCER_CC6P; + 800428c: 693b ldr r3, [r7, #16] + 800428e: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 + 8004292: 613b str r3, [r7, #16] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 20U); + 8004294: 683b ldr r3, [r7, #0] + 8004296: 689b ldr r3, [r3, #8] + 8004298: 051b lsls r3, r3, #20 + 800429a: 693a ldr r2, [r7, #16] + 800429c: 4313 orrs r3, r2 + 800429e: 613b str r3, [r7, #16] + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 80042a0: 687b ldr r3, [r7, #4] + 80042a2: 4a13 ldr r2, [pc, #76] ; (80042f0 ) + 80042a4: 4293 cmp r3, r2 + 80042a6: d003 beq.n 80042b0 + 80042a8: 687b ldr r3, [r7, #4] + 80042aa: 4a12 ldr r2, [pc, #72] ; (80042f4 ) + 80042ac: 4293 cmp r3, r2 + 80042ae: d109 bne.n 80042c4 + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS6; + 80042b0: 697b ldr r3, [r7, #20] + 80042b2: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 80042b6: 617b str r3, [r7, #20] + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 10U); + 80042b8: 683b ldr r3, [r7, #0] + 80042ba: 695b ldr r3, [r3, #20] + 80042bc: 029b lsls r3, r3, #10 + 80042be: 697a ldr r2, [r7, #20] + 80042c0: 4313 orrs r3, r2 + 80042c2: 617b str r3, [r7, #20] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 80042c4: 687b ldr r3, [r7, #4] + 80042c6: 697a ldr r2, [r7, #20] + 80042c8: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + 80042ca: 687b ldr r3, [r7, #4] + 80042cc: 68fa ldr r2, [r7, #12] + 80042ce: 655a str r2, [r3, #84] ; 0x54 + + /* Set the Capture Compare Register value */ + TIMx->CCR6 = OC_Config->Pulse; + 80042d0: 683b ldr r3, [r7, #0] + 80042d2: 685a ldr r2, [r3, #4] + 80042d4: 687b ldr r3, [r7, #4] + 80042d6: 65da str r2, [r3, #92] ; 0x5c + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 80042d8: 687b ldr r3, [r7, #4] + 80042da: 693a ldr r2, [r7, #16] + 80042dc: 621a str r2, [r3, #32] +} + 80042de: bf00 nop + 80042e0: 371c adds r7, #28 + 80042e2: 46bd mov sp, r7 + 80042e4: f85d 7b04 ldr.w r7, [sp], #4 + 80042e8: 4770 bx lr + 80042ea: bf00 nop + 80042ec: feff8fff .word 0xfeff8fff + 80042f0: 40010000 .word 0x40010000 + 80042f4: 40010400 .word 0x40010400 + +080042f8 : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 80042f8: b480 push {r7} + 80042fa: b087 sub sp, #28 + 80042fc: af00 add r7, sp, #0 + 80042fe: 60f8 str r0, [r7, #12] + 8004300: 60b9 str r1, [r7, #8] + 8004302: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + 8004304: 68fb ldr r3, [r7, #12] + 8004306: 6a1b ldr r3, [r3, #32] + 8004308: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC1E; + 800430a: 68fb ldr r3, [r7, #12] + 800430c: 6a1b ldr r3, [r3, #32] + 800430e: f023 0201 bic.w r2, r3, #1 + 8004312: 68fb ldr r3, [r7, #12] + 8004314: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 8004316: 68fb ldr r3, [r7, #12] + 8004318: 699b ldr r3, [r3, #24] + 800431a: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + 800431c: 693b ldr r3, [r7, #16] + 800431e: f023 03f0 bic.w r3, r3, #240 ; 0xf0 + 8004322: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 4U); + 8004324: 687b ldr r3, [r7, #4] + 8004326: 011b lsls r3, r3, #4 + 8004328: 693a ldr r2, [r7, #16] + 800432a: 4313 orrs r3, r2 + 800432c: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + 800432e: 697b ldr r3, [r7, #20] + 8004330: f023 030a bic.w r3, r3, #10 + 8004334: 617b str r3, [r7, #20] + tmpccer |= TIM_ICPolarity; + 8004336: 697a ldr r2, [r7, #20] + 8004338: 68bb ldr r3, [r7, #8] + 800433a: 4313 orrs r3, r2 + 800433c: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + 800433e: 68fb ldr r3, [r7, #12] + 8004340: 693a ldr r2, [r7, #16] + 8004342: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 8004344: 68fb ldr r3, [r7, #12] + 8004346: 697a ldr r2, [r7, #20] + 8004348: 621a str r2, [r3, #32] +} + 800434a: bf00 nop + 800434c: 371c adds r7, #28 + 800434e: 46bd mov sp, r7 + 8004350: f85d 7b04 ldr.w r7, [sp], #4 + 8004354: 4770 bx lr + +08004356 : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 8004356: b480 push {r7} + 8004358: b087 sub sp, #28 + 800435a: af00 add r7, sp, #0 + 800435c: 60f8 str r0, [r7, #12] + 800435e: 60b9 str r1, [r7, #8] + 8004360: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + 8004362: 68fb ldr r3, [r7, #12] + 8004364: 6a1b ldr r3, [r3, #32] + 8004366: f023 0210 bic.w r2, r3, #16 + 800436a: 68fb ldr r3, [r7, #12] + 800436c: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 800436e: 68fb ldr r3, [r7, #12] + 8004370: 699b ldr r3, [r3, #24] + 8004372: 617b str r3, [r7, #20] + tmpccer = TIMx->CCER; + 8004374: 68fb ldr r3, [r7, #12] + 8004376: 6a1b ldr r3, [r3, #32] + 8004378: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + 800437a: 697b ldr r3, [r7, #20] + 800437c: f423 4370 bic.w r3, r3, #61440 ; 0xf000 + 8004380: 617b str r3, [r7, #20] + tmpccmr1 |= (TIM_ICFilter << 12U); + 8004382: 687b ldr r3, [r7, #4] + 8004384: 031b lsls r3, r3, #12 + 8004386: 697a ldr r2, [r7, #20] + 8004388: 4313 orrs r3, r2 + 800438a: 617b str r3, [r7, #20] + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + 800438c: 693b ldr r3, [r7, #16] + 800438e: f023 03a0 bic.w r3, r3, #160 ; 0xa0 + 8004392: 613b str r3, [r7, #16] + tmpccer |= (TIM_ICPolarity << 4U); + 8004394: 68bb ldr r3, [r7, #8] + 8004396: 011b lsls r3, r3, #4 + 8004398: 693a ldr r2, [r7, #16] + 800439a: 4313 orrs r3, r2 + 800439c: 613b str r3, [r7, #16] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + 800439e: 68fb ldr r3, [r7, #12] + 80043a0: 697a ldr r2, [r7, #20] + 80043a2: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 80043a4: 68fb ldr r3, [r7, #12] + 80043a6: 693a ldr r2, [r7, #16] + 80043a8: 621a str r2, [r3, #32] +} + 80043aa: bf00 nop + 80043ac: 371c adds r7, #28 + 80043ae: 46bd mov sp, r7 + 80043b0: f85d 7b04 ldr.w r7, [sp], #4 + 80043b4: 4770 bx lr + +080043b6 : + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + 80043b6: b480 push {r7} + 80043b8: b085 sub sp, #20 + 80043ba: af00 add r7, sp, #0 + 80043bc: 6078 str r0, [r7, #4] + 80043be: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + 80043c0: 687b ldr r3, [r7, #4] + 80043c2: 689b ldr r3, [r3, #8] + 80043c4: 60fb str r3, [r7, #12] + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + 80043c6: 68fb ldr r3, [r7, #12] + 80043c8: f023 0370 bic.w r3, r3, #112 ; 0x70 + 80043cc: 60fb str r3, [r7, #12] + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + 80043ce: 683a ldr r2, [r7, #0] + 80043d0: 68fb ldr r3, [r7, #12] + 80043d2: 4313 orrs r3, r2 + 80043d4: f043 0307 orr.w r3, r3, #7 + 80043d8: 60fb str r3, [r7, #12] + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 80043da: 687b ldr r3, [r7, #4] + 80043dc: 68fa ldr r2, [r7, #12] + 80043de: 609a str r2, [r3, #8] +} + 80043e0: bf00 nop + 80043e2: 3714 adds r7, #20 + 80043e4: 46bd mov sp, r7 + 80043e6: f85d 7b04 ldr.w r7, [sp], #4 + 80043ea: 4770 bx lr + +080043ec : + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + 80043ec: b480 push {r7} + 80043ee: b087 sub sp, #28 + 80043f0: af00 add r7, sp, #0 + 80043f2: 60f8 str r0, [r7, #12] + 80043f4: 60b9 str r1, [r7, #8] + 80043f6: 607a str r2, [r7, #4] + 80043f8: 603b str r3, [r7, #0] + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + 80043fa: 68fb ldr r3, [r7, #12] + 80043fc: 689b ldr r3, [r3, #8] + 80043fe: 617b str r3, [r7, #20] + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 8004400: 697b ldr r3, [r7, #20] + 8004402: f423 437f bic.w r3, r3, #65280 ; 0xff00 + 8004406: 617b str r3, [r7, #20] + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + 8004408: 683b ldr r3, [r7, #0] + 800440a: 021a lsls r2, r3, #8 + 800440c: 687b ldr r3, [r7, #4] + 800440e: 431a orrs r2, r3 + 8004410: 68bb ldr r3, [r7, #8] + 8004412: 4313 orrs r3, r2 + 8004414: 697a ldr r2, [r7, #20] + 8004416: 4313 orrs r3, r2 + 8004418: 617b str r3, [r7, #20] + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 800441a: 68fb ldr r3, [r7, #12] + 800441c: 697a ldr r2, [r7, #20] + 800441e: 609a str r2, [r3, #8] +} + 8004420: bf00 nop + 8004422: 371c adds r7, #28 + 8004424: 46bd mov sp, r7 + 8004426: f85d 7b04 ldr.w r7, [sp], #4 + 800442a: 4770 bx lr + +0800442c : + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + 800442c: b480 push {r7} + 800442e: b087 sub sp, #28 + 8004430: af00 add r7, sp, #0 + 8004432: 60f8 str r0, [r7, #12] + 8004434: 60b9 str r1, [r7, #8] + 8004436: 607a str r2, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + 8004438: 68bb ldr r3, [r7, #8] + 800443a: f003 031f and.w r3, r3, #31 + 800443e: 2201 movs r2, #1 + 8004440: fa02 f303 lsl.w r3, r2, r3 + 8004444: 617b str r3, [r7, #20] + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + 8004446: 68fb ldr r3, [r7, #12] + 8004448: 6a1a ldr r2, [r3, #32] + 800444a: 697b ldr r3, [r7, #20] + 800444c: 43db mvns r3, r3 + 800444e: 401a ands r2, r3 + 8004450: 68fb ldr r3, [r7, #12] + 8004452: 621a str r2, [r3, #32] + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + 8004454: 68fb ldr r3, [r7, #12] + 8004456: 6a1a ldr r2, [r3, #32] + 8004458: 68bb ldr r3, [r7, #8] + 800445a: f003 031f and.w r3, r3, #31 + 800445e: 6879 ldr r1, [r7, #4] + 8004460: fa01 f303 lsl.w r3, r1, r3 + 8004464: 431a orrs r2, r3 + 8004466: 68fb ldr r3, [r7, #12] + 8004468: 621a str r2, [r3, #32] +} + 800446a: bf00 nop + 800446c: 371c adds r7, #28 + 800446e: 46bd mov sp, r7 + 8004470: f85d 7b04 ldr.w r7, [sp], #4 + 8004474: 4770 bx lr + ... + +08004478 : + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig) +{ + 8004478: b480 push {r7} + 800447a: b085 sub sp, #20 + 800447c: af00 add r7, sp, #0 + 800447e: 6078 str r0, [r7, #4] + 8004480: 6039 str r1, [r7, #0] + assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + 8004482: 687b ldr r3, [r7, #4] + 8004484: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 8004488: 2b01 cmp r3, #1 + 800448a: d101 bne.n 8004490 + 800448c: 2302 movs r3, #2 + 800448e: e045 b.n 800451c + 8004490: 687b ldr r3, [r7, #4] + 8004492: 2201 movs r2, #1 + 8004494: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + 8004498: 687b ldr r3, [r7, #4] + 800449a: 2202 movs r2, #2 + 800449c: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + 80044a0: 687b ldr r3, [r7, #4] + 80044a2: 681b ldr r3, [r3, #0] + 80044a4: 685b ldr r3, [r3, #4] + 80044a6: 60fb str r3, [r7, #12] + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 80044a8: 687b ldr r3, [r7, #4] + 80044aa: 681b ldr r3, [r3, #0] + 80044ac: 689b ldr r3, [r3, #8] + 80044ae: 60bb str r3, [r7, #8] + + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) + 80044b0: 687b ldr r3, [r7, #4] + 80044b2: 681b ldr r3, [r3, #0] + 80044b4: 4a1c ldr r2, [pc, #112] ; (8004528 ) + 80044b6: 4293 cmp r3, r2 + 80044b8: d004 beq.n 80044c4 + 80044ba: 687b ldr r3, [r7, #4] + 80044bc: 681b ldr r3, [r3, #0] + 80044be: 4a1b ldr r2, [pc, #108] ; (800452c ) + 80044c0: 4293 cmp r3, r2 + 80044c2: d108 bne.n 80044d6 + { + /* Check the parameters */ + assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); + + /* Clear the MMS2 bits */ + tmpcr2 &= ~TIM_CR2_MMS2; + 80044c4: 68fb ldr r3, [r7, #12] + 80044c6: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000 + 80044ca: 60fb str r3, [r7, #12] + /* Select the TRGO2 source*/ + tmpcr2 |= sMasterConfig->MasterOutputTrigger2; + 80044cc: 683b ldr r3, [r7, #0] + 80044ce: 685b ldr r3, [r3, #4] + 80044d0: 68fa ldr r2, [r7, #12] + 80044d2: 4313 orrs r3, r2 + 80044d4: 60fb str r3, [r7, #12] + } + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + 80044d6: 68fb ldr r3, [r7, #12] + 80044d8: f023 0370 bic.w r3, r3, #112 ; 0x70 + 80044dc: 60fb str r3, [r7, #12] + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + 80044de: 683b ldr r3, [r7, #0] + 80044e0: 681b ldr r3, [r3, #0] + 80044e2: 68fa ldr r2, [r7, #12] + 80044e4: 4313 orrs r3, r2 + 80044e6: 60fb str r3, [r7, #12] + + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + 80044e8: 68bb ldr r3, [r7, #8] + 80044ea: f023 0380 bic.w r3, r3, #128 ; 0x80 + 80044ee: 60bb str r3, [r7, #8] + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + 80044f0: 683b ldr r3, [r7, #0] + 80044f2: 689b ldr r3, [r3, #8] + 80044f4: 68ba ldr r2, [r7, #8] + 80044f6: 4313 orrs r3, r2 + 80044f8: 60bb str r3, [r7, #8] + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + 80044fa: 687b ldr r3, [r7, #4] + 80044fc: 681b ldr r3, [r3, #0] + 80044fe: 68fa ldr r2, [r7, #12] + 8004500: 605a str r2, [r3, #4] + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8004502: 687b ldr r3, [r7, #4] + 8004504: 681b ldr r3, [r3, #0] + 8004506: 68ba ldr r2, [r7, #8] + 8004508: 609a str r2, [r3, #8] + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + 800450a: 687b ldr r3, [r7, #4] + 800450c: 2201 movs r2, #1 + 800450e: f883 203d strb.w r2, [r3, #61] ; 0x3d + + __HAL_UNLOCK(htim); + 8004512: 687b ldr r3, [r7, #4] + 8004514: 2200 movs r2, #0 + 8004516: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_OK; + 800451a: 2300 movs r3, #0 +} + 800451c: 4618 mov r0, r3 + 800451e: 3714 adds r7, #20 + 8004520: 46bd mov sp, r7 + 8004522: f85d 7b04 ldr.w r7, [sp], #4 + 8004526: 4770 bx lr + 8004528: 40010000 .word 0x40010000 + 800452c: 40010400 .word 0x40010400 + +08004530 : + * @brief Hall commutation changed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + 8004530: b480 push {r7} + 8004532: b083 sub sp, #12 + 8004534: af00 add r7, sp, #0 + 8004536: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} + 8004538: bf00 nop + 800453a: 370c adds r7, #12 + 800453c: 46bd mov sp, r7 + 800453e: f85d 7b04 ldr.w r7, [sp], #4 + 8004542: 4770 bx lr + +08004544 : + * @brief Hall Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + 8004544: b480 push {r7} + 8004546: b083 sub sp, #12 + 8004548: af00 add r7, sp, #0 + 800454a: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + 800454c: bf00 nop + 800454e: 370c adds r7, #12 + 8004550: 46bd mov sp, r7 + 8004552: f85d 7b04 ldr.w r7, [sp], #4 + 8004556: 4770 bx lr + +08004558 : + * @brief Hall Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + 8004558: b480 push {r7} + 800455a: b083 sub sp, #12 + 800455c: af00 add r7, sp, #0 + 800455e: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} + 8004560: bf00 nop + 8004562: 370c adds r7, #12 + 8004564: 46bd mov sp, r7 + 8004566: f85d 7b04 ldr.w r7, [sp], #4 + 800456a: 4770 bx lr + +0800456c : + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + 800456c: b580 push {r7, lr} + 800456e: b082 sub sp, #8 + 8004570: af00 add r7, sp, #0 + 8004572: 6078 str r0, [r7, #4] + /* Check the UART handle allocation */ + if (huart == NULL) + 8004574: 687b ldr r3, [r7, #4] + 8004576: 2b00 cmp r3, #0 + 8004578: d101 bne.n 800457e + { + return HAL_ERROR; + 800457a: 2301 movs r3, #1 + 800457c: e040 b.n 8004600 + { + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + + if (huart->gState == HAL_UART_STATE_RESET) + 800457e: 687b ldr r3, [r7, #4] + 8004580: 6f5b ldr r3, [r3, #116] ; 0x74 + 8004582: 2b00 cmp r3, #0 + 8004584: d106 bne.n 8004594 + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + 8004586: 687b ldr r3, [r7, #4] + 8004588: 2200 movs r2, #0 + 800458a: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); + 800458e: 6878 ldr r0, [r7, #4] + 8004590: f7fd fa38 bl 8001a04 +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + 8004594: 687b ldr r3, [r7, #4] + 8004596: 2224 movs r2, #36 ; 0x24 + 8004598: 675a str r2, [r3, #116] ; 0x74 + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + 800459a: 687b ldr r3, [r7, #4] + 800459c: 681b ldr r3, [r3, #0] + 800459e: 681a ldr r2, [r3, #0] + 80045a0: 687b ldr r3, [r7, #4] + 80045a2: 681b ldr r3, [r3, #0] + 80045a4: f022 0201 bic.w r2, r2, #1 + 80045a8: 601a str r2, [r3, #0] + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + 80045aa: 6878 ldr r0, [r7, #4] + 80045ac: f000 fa90 bl 8004ad0 + 80045b0: 4603 mov r3, r0 + 80045b2: 2b01 cmp r3, #1 + 80045b4: d101 bne.n 80045ba + { + return HAL_ERROR; + 80045b6: 2301 movs r3, #1 + 80045b8: e022 b.n 8004600 + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 80045ba: 687b ldr r3, [r7, #4] + 80045bc: 6a5b ldr r3, [r3, #36] ; 0x24 + 80045be: 2b00 cmp r3, #0 + 80045c0: d002 beq.n 80045c8 + { + UART_AdvFeatureConfig(huart); + 80045c2: 6878 ldr r0, [r7, #4] + 80045c4: f000 fd28 bl 8005018 + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 80045c8: 687b ldr r3, [r7, #4] + 80045ca: 681b ldr r3, [r3, #0] + 80045cc: 685a ldr r2, [r3, #4] + 80045ce: 687b ldr r3, [r7, #4] + 80045d0: 681b ldr r3, [r3, #0] + 80045d2: f422 4290 bic.w r2, r2, #18432 ; 0x4800 + 80045d6: 605a str r2, [r3, #4] + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 80045d8: 687b ldr r3, [r7, #4] + 80045da: 681b ldr r3, [r3, #0] + 80045dc: 689a ldr r2, [r3, #8] + 80045de: 687b ldr r3, [r7, #4] + 80045e0: 681b ldr r3, [r3, #0] + 80045e2: f022 022a bic.w r2, r2, #42 ; 0x2a + 80045e6: 609a str r2, [r3, #8] + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + 80045e8: 687b ldr r3, [r7, #4] + 80045ea: 681b ldr r3, [r3, #0] + 80045ec: 681a ldr r2, [r3, #0] + 80045ee: 687b ldr r3, [r7, #4] + 80045f0: 681b ldr r3, [r3, #0] + 80045f2: f042 0201 orr.w r2, r2, #1 + 80045f6: 601a str r2, [r3, #0] + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); + 80045f8: 6878 ldr r0, [r7, #4] + 80045fa: f000 fdaf bl 800515c + 80045fe: 4603 mov r3, r0 +} + 8004600: 4618 mov r0, r3 + 8004602: 3708 adds r7, #8 + 8004604: 46bd mov sp, r7 + 8004606: bd80 pop {r7, pc} + +08004608 : + * @param Size Amount of data to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8004608: b580 push {r7, lr} + 800460a: b08a sub sp, #40 ; 0x28 + 800460c: af02 add r7, sp, #8 + 800460e: 60f8 str r0, [r7, #12] + 8004610: 60b9 str r1, [r7, #8] + 8004612: 603b str r3, [r7, #0] + 8004614: 4613 mov r3, r2 + 8004616: 80fb strh r3, [r7, #6] + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + 8004618: 68fb ldr r3, [r7, #12] + 800461a: 6f5b ldr r3, [r3, #116] ; 0x74 + 800461c: 2b20 cmp r3, #32 + 800461e: d17f bne.n 8004720 + { + if ((pData == NULL) || (Size == 0U)) + 8004620: 68bb ldr r3, [r7, #8] + 8004622: 2b00 cmp r3, #0 + 8004624: d002 beq.n 800462c + 8004626: 88fb ldrh r3, [r7, #6] + 8004628: 2b00 cmp r3, #0 + 800462a: d101 bne.n 8004630 + { + return HAL_ERROR; + 800462c: 2301 movs r3, #1 + 800462e: e078 b.n 8004722 + } + + /* Process Locked */ + __HAL_LOCK(huart); + 8004630: 68fb ldr r3, [r7, #12] + 8004632: f893 3070 ldrb.w r3, [r3, #112] ; 0x70 + 8004636: 2b01 cmp r3, #1 + 8004638: d101 bne.n 800463e + 800463a: 2302 movs r3, #2 + 800463c: e071 b.n 8004722 + 800463e: 68fb ldr r3, [r7, #12] + 8004640: 2201 movs r2, #1 + 8004642: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8004646: 68fb ldr r3, [r7, #12] + 8004648: 2200 movs r2, #0 + 800464a: 67da str r2, [r3, #124] ; 0x7c + huart->gState = HAL_UART_STATE_BUSY_TX; + 800464c: 68fb ldr r3, [r7, #12] + 800464e: 2221 movs r2, #33 ; 0x21 + 8004650: 675a str r2, [r3, #116] ; 0x74 + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + 8004652: f7fd fb1f bl 8001c94 + 8004656: 6178 str r0, [r7, #20] + + huart->TxXferSize = Size; + 8004658: 68fb ldr r3, [r7, #12] + 800465a: 88fa ldrh r2, [r7, #6] + 800465c: f8a3 2050 strh.w r2, [r3, #80] ; 0x50 + huart->TxXferCount = Size; + 8004660: 68fb ldr r3, [r7, #12] + 8004662: 88fa ldrh r2, [r7, #6] + 8004664: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 8004668: 68fb ldr r3, [r7, #12] + 800466a: 689b ldr r3, [r3, #8] + 800466c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8004670: d108 bne.n 8004684 + 8004672: 68fb ldr r3, [r7, #12] + 8004674: 691b ldr r3, [r3, #16] + 8004676: 2b00 cmp r3, #0 + 8004678: d104 bne.n 8004684 + { + pdata8bits = NULL; + 800467a: 2300 movs r3, #0 + 800467c: 61fb str r3, [r7, #28] + pdata16bits = (uint16_t *) pData; + 800467e: 68bb ldr r3, [r7, #8] + 8004680: 61bb str r3, [r7, #24] + 8004682: e003 b.n 800468c + } + else + { + pdata8bits = pData; + 8004684: 68bb ldr r3, [r7, #8] + 8004686: 61fb str r3, [r7, #28] + pdata16bits = NULL; + 8004688: 2300 movs r3, #0 + 800468a: 61bb str r3, [r7, #24] + } + + while (huart->TxXferCount > 0U) + 800468c: e02c b.n 80046e8 + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + 800468e: 683b ldr r3, [r7, #0] + 8004690: 9300 str r3, [sp, #0] + 8004692: 697b ldr r3, [r7, #20] + 8004694: 2200 movs r2, #0 + 8004696: 2180 movs r1, #128 ; 0x80 + 8004698: 68f8 ldr r0, [r7, #12] + 800469a: f000 fd8e bl 80051ba + 800469e: 4603 mov r3, r0 + 80046a0: 2b00 cmp r3, #0 + 80046a2: d001 beq.n 80046a8 + { + return HAL_TIMEOUT; + 80046a4: 2303 movs r3, #3 + 80046a6: e03c b.n 8004722 + } + if (pdata8bits == NULL) + 80046a8: 69fb ldr r3, [r7, #28] + 80046aa: 2b00 cmp r3, #0 + 80046ac: d10b bne.n 80046c6 + { + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + 80046ae: 69bb ldr r3, [r7, #24] + 80046b0: 881b ldrh r3, [r3, #0] + 80046b2: 461a mov r2, r3 + 80046b4: 68fb ldr r3, [r7, #12] + 80046b6: 681b ldr r3, [r3, #0] + 80046b8: f3c2 0208 ubfx r2, r2, #0, #9 + 80046bc: 629a str r2, [r3, #40] ; 0x28 + pdata16bits++; + 80046be: 69bb ldr r3, [r7, #24] + 80046c0: 3302 adds r3, #2 + 80046c2: 61bb str r3, [r7, #24] + 80046c4: e007 b.n 80046d6 + } + else + { + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + 80046c6: 69fb ldr r3, [r7, #28] + 80046c8: 781a ldrb r2, [r3, #0] + 80046ca: 68fb ldr r3, [r7, #12] + 80046cc: 681b ldr r3, [r3, #0] + 80046ce: 629a str r2, [r3, #40] ; 0x28 + pdata8bits++; + 80046d0: 69fb ldr r3, [r7, #28] + 80046d2: 3301 adds r3, #1 + 80046d4: 61fb str r3, [r7, #28] + } + huart->TxXferCount--; + 80046d6: 68fb ldr r3, [r7, #12] + 80046d8: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 + 80046dc: b29b uxth r3, r3 + 80046de: 3b01 subs r3, #1 + 80046e0: b29a uxth r2, r3 + 80046e2: 68fb ldr r3, [r7, #12] + 80046e4: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 + while (huart->TxXferCount > 0U) + 80046e8: 68fb ldr r3, [r7, #12] + 80046ea: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 + 80046ee: b29b uxth r3, r3 + 80046f0: 2b00 cmp r3, #0 + 80046f2: d1cc bne.n 800468e + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + 80046f4: 683b ldr r3, [r7, #0] + 80046f6: 9300 str r3, [sp, #0] + 80046f8: 697b ldr r3, [r7, #20] + 80046fa: 2200 movs r2, #0 + 80046fc: 2140 movs r1, #64 ; 0x40 + 80046fe: 68f8 ldr r0, [r7, #12] + 8004700: f000 fd5b bl 80051ba + 8004704: 4603 mov r3, r0 + 8004706: 2b00 cmp r3, #0 + 8004708: d001 beq.n 800470e + { + return HAL_TIMEOUT; + 800470a: 2303 movs r3, #3 + 800470c: e009 b.n 8004722 + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 800470e: 68fb ldr r3, [r7, #12] + 8004710: 2220 movs r2, #32 + 8004712: 675a str r2, [r3, #116] ; 0x74 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8004714: 68fb ldr r3, [r7, #12] + 8004716: 2200 movs r2, #0 + 8004718: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + return HAL_OK; + 800471c: 2300 movs r3, #0 + 800471e: e000 b.n 8004722 + } + else + { + return HAL_BUSY; + 8004720: 2302 movs r3, #2 + } +} + 8004722: 4618 mov r0, r3 + 8004724: 3720 adds r7, #32 + 8004726: 46bd mov sp, r7 + 8004728: bd80 pop {r7, pc} + ... + +0800472c : + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + 800472c: b480 push {r7} + 800472e: b085 sub sp, #20 + 8004730: af00 add r7, sp, #0 + 8004732: 60f8 str r0, [r7, #12] + 8004734: 60b9 str r1, [r7, #8] + 8004736: 4613 mov r3, r2 + 8004738: 80fb strh r3, [r7, #6] + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + 800473a: 68fb ldr r3, [r7, #12] + 800473c: 6f9b ldr r3, [r3, #120] ; 0x78 + 800473e: 2b20 cmp r3, #32 + 8004740: f040 808a bne.w 8004858 + { + if ((pData == NULL) || (Size == 0U)) + 8004744: 68bb ldr r3, [r7, #8] + 8004746: 2b00 cmp r3, #0 + 8004748: d002 beq.n 8004750 + 800474a: 88fb ldrh r3, [r7, #6] + 800474c: 2b00 cmp r3, #0 + 800474e: d101 bne.n 8004754 + { + return HAL_ERROR; + 8004750: 2301 movs r3, #1 + 8004752: e082 b.n 800485a + } + + /* Process Locked */ + __HAL_LOCK(huart); + 8004754: 68fb ldr r3, [r7, #12] + 8004756: f893 3070 ldrb.w r3, [r3, #112] ; 0x70 + 800475a: 2b01 cmp r3, #1 + 800475c: d101 bne.n 8004762 + 800475e: 2302 movs r3, #2 + 8004760: e07b b.n 800485a + 8004762: 68fb ldr r3, [r7, #12] + 8004764: 2201 movs r2, #1 + 8004766: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + huart->pRxBuffPtr = pData; + 800476a: 68fb ldr r3, [r7, #12] + 800476c: 68ba ldr r2, [r7, #8] + 800476e: 655a str r2, [r3, #84] ; 0x54 + huart->RxXferSize = Size; + 8004770: 68fb ldr r3, [r7, #12] + 8004772: 88fa ldrh r2, [r7, #6] + 8004774: f8a3 2058 strh.w r2, [r3, #88] ; 0x58 + huart->RxXferCount = Size; + 8004778: 68fb ldr r3, [r7, #12] + 800477a: 88fa ldrh r2, [r7, #6] + 800477c: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + huart->RxISR = NULL; + 8004780: 68fb ldr r3, [r7, #12] + 8004782: 2200 movs r2, #0 + 8004784: 661a str r2, [r3, #96] ; 0x60 + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + 8004786: 68fb ldr r3, [r7, #12] + 8004788: 689b ldr r3, [r3, #8] + 800478a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 800478e: d10e bne.n 80047ae + 8004790: 68fb ldr r3, [r7, #12] + 8004792: 691b ldr r3, [r3, #16] + 8004794: 2b00 cmp r3, #0 + 8004796: d105 bne.n 80047a4 + 8004798: 68fb ldr r3, [r7, #12] + 800479a: f240 12ff movw r2, #511 ; 0x1ff + 800479e: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 80047a2: e02d b.n 8004800 + 80047a4: 68fb ldr r3, [r7, #12] + 80047a6: 22ff movs r2, #255 ; 0xff + 80047a8: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 80047ac: e028 b.n 8004800 + 80047ae: 68fb ldr r3, [r7, #12] + 80047b0: 689b ldr r3, [r3, #8] + 80047b2: 2b00 cmp r3, #0 + 80047b4: d10d bne.n 80047d2 + 80047b6: 68fb ldr r3, [r7, #12] + 80047b8: 691b ldr r3, [r3, #16] + 80047ba: 2b00 cmp r3, #0 + 80047bc: d104 bne.n 80047c8 + 80047be: 68fb ldr r3, [r7, #12] + 80047c0: 22ff movs r2, #255 ; 0xff + 80047c2: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 80047c6: e01b b.n 8004800 + 80047c8: 68fb ldr r3, [r7, #12] + 80047ca: 227f movs r2, #127 ; 0x7f + 80047cc: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 80047d0: e016 b.n 8004800 + 80047d2: 68fb ldr r3, [r7, #12] + 80047d4: 689b ldr r3, [r3, #8] + 80047d6: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 + 80047da: d10d bne.n 80047f8 + 80047dc: 68fb ldr r3, [r7, #12] + 80047de: 691b ldr r3, [r3, #16] + 80047e0: 2b00 cmp r3, #0 + 80047e2: d104 bne.n 80047ee + 80047e4: 68fb ldr r3, [r7, #12] + 80047e6: 227f movs r2, #127 ; 0x7f + 80047e8: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 80047ec: e008 b.n 8004800 + 80047ee: 68fb ldr r3, [r7, #12] + 80047f0: 223f movs r2, #63 ; 0x3f + 80047f2: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 80047f6: e003 b.n 8004800 + 80047f8: 68fb ldr r3, [r7, #12] + 80047fa: 2200 movs r2, #0 + 80047fc: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8004800: 68fb ldr r3, [r7, #12] + 8004802: 2200 movs r2, #0 + 8004804: 67da str r2, [r3, #124] ; 0x7c + huart->RxState = HAL_UART_STATE_BUSY_RX; + 8004806: 68fb ldr r3, [r7, #12] + 8004808: 2222 movs r2, #34 ; 0x22 + 800480a: 679a str r2, [r3, #120] ; 0x78 + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + 800480c: 68fb ldr r3, [r7, #12] + 800480e: 681b ldr r3, [r3, #0] + 8004810: 689a ldr r2, [r3, #8] + 8004812: 68fb ldr r3, [r7, #12] + 8004814: 681b ldr r3, [r3, #0] + 8004816: f042 0201 orr.w r2, r2, #1 + 800481a: 609a str r2, [r3, #8] + + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 800481c: 68fb ldr r3, [r7, #12] + 800481e: 689b ldr r3, [r3, #8] + 8004820: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8004824: d107 bne.n 8004836 + 8004826: 68fb ldr r3, [r7, #12] + 8004828: 691b ldr r3, [r3, #16] + 800482a: 2b00 cmp r3, #0 + 800482c: d103 bne.n 8004836 + { + huart->RxISR = UART_RxISR_16BIT; + 800482e: 68fb ldr r3, [r7, #12] + 8004830: 4a0d ldr r2, [pc, #52] ; (8004868 ) + 8004832: 661a str r2, [r3, #96] ; 0x60 + 8004834: e002 b.n 800483c + } + else + { + huart->RxISR = UART_RxISR_8BIT; + 8004836: 68fb ldr r3, [r7, #12] + 8004838: 4a0c ldr r2, [pc, #48] ; (800486c ) + 800483a: 661a str r2, [r3, #96] ; 0x60 + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 800483c: 68fb ldr r3, [r7, #12] + 800483e: 2200 movs r2, #0 + 8004840: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + 8004844: 68fb ldr r3, [r7, #12] + 8004846: 681b ldr r3, [r3, #0] + 8004848: 681a ldr r2, [r3, #0] + 800484a: 68fb ldr r3, [r7, #12] + 800484c: 681b ldr r3, [r3, #0] + 800484e: f442 7290 orr.w r2, r2, #288 ; 0x120 + 8004852: 601a str r2, [r3, #0] + + return HAL_OK; + 8004854: 2300 movs r3, #0 + 8004856: e000 b.n 800485a + } + else + { + return HAL_BUSY; + 8004858: 2302 movs r3, #2 + } +} + 800485a: 4618 mov r0, r3 + 800485c: 3714 adds r7, #20 + 800485e: 46bd mov sp, r7 + 8004860: f85d 7b04 ldr.w r7, [sp], #4 + 8004864: 4770 bx lr + 8004866: bf00 nop + 8004868: 0800538f .word 0x0800538f + 800486c: 080052e9 .word 0x080052e9 + +08004870 : + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + 8004870: b580 push {r7, lr} + 8004872: b088 sub sp, #32 + 8004874: af00 add r7, sp, #0 + 8004876: 6078 str r0, [r7, #4] + uint32_t isrflags = READ_REG(huart->Instance->ISR); + 8004878: 687b ldr r3, [r7, #4] + 800487a: 681b ldr r3, [r3, #0] + 800487c: 69db ldr r3, [r3, #28] + 800487e: 61fb str r3, [r7, #28] + uint32_t cr1its = READ_REG(huart->Instance->CR1); + 8004880: 687b ldr r3, [r7, #4] + 8004882: 681b ldr r3, [r3, #0] + 8004884: 681b ldr r3, [r3, #0] + 8004886: 61bb str r3, [r7, #24] + uint32_t cr3its = READ_REG(huart->Instance->CR3); + 8004888: 687b ldr r3, [r7, #4] + 800488a: 681b ldr r3, [r3, #0] + 800488c: 689b ldr r3, [r3, #8] + 800488e: 617b str r3, [r7, #20] + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + 8004890: 69fb ldr r3, [r7, #28] + 8004892: f003 030f and.w r3, r3, #15 + 8004896: 613b str r3, [r7, #16] + if (errorflags == 0U) + 8004898: 693b ldr r3, [r7, #16] + 800489a: 2b00 cmp r3, #0 + 800489c: d113 bne.n 80048c6 + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE) != 0U) + 800489e: 69fb ldr r3, [r7, #28] + 80048a0: f003 0320 and.w r3, r3, #32 + 80048a4: 2b00 cmp r3, #0 + 80048a6: d00e beq.n 80048c6 + && ((cr1its & USART_CR1_RXNEIE) != 0U)) + 80048a8: 69bb ldr r3, [r7, #24] + 80048aa: f003 0320 and.w r3, r3, #32 + 80048ae: 2b00 cmp r3, #0 + 80048b0: d009 beq.n 80048c6 + { + if (huart->RxISR != NULL) + 80048b2: 687b ldr r3, [r7, #4] + 80048b4: 6e1b ldr r3, [r3, #96] ; 0x60 + 80048b6: 2b00 cmp r3, #0 + 80048b8: f000 80eb beq.w 8004a92 + { + huart->RxISR(huart); + 80048bc: 687b ldr r3, [r7, #4] + 80048be: 6e1b ldr r3, [r3, #96] ; 0x60 + 80048c0: 6878 ldr r0, [r7, #4] + 80048c2: 4798 blx r3 + } + return; + 80048c4: e0e5 b.n 8004a92 + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + 80048c6: 693b ldr r3, [r7, #16] + 80048c8: 2b00 cmp r3, #0 + 80048ca: f000 80c0 beq.w 8004a4e + && (((cr3its & USART_CR3_EIE) != 0U) + 80048ce: 697b ldr r3, [r7, #20] + 80048d0: f003 0301 and.w r3, r3, #1 + 80048d4: 2b00 cmp r3, #0 + 80048d6: d105 bne.n 80048e4 + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U))) + 80048d8: 69bb ldr r3, [r7, #24] + 80048da: f403 7390 and.w r3, r3, #288 ; 0x120 + 80048de: 2b00 cmp r3, #0 + 80048e0: f000 80b5 beq.w 8004a4e + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + 80048e4: 69fb ldr r3, [r7, #28] + 80048e6: f003 0301 and.w r3, r3, #1 + 80048ea: 2b00 cmp r3, #0 + 80048ec: d00e beq.n 800490c + 80048ee: 69bb ldr r3, [r7, #24] + 80048f0: f403 7380 and.w r3, r3, #256 ; 0x100 + 80048f4: 2b00 cmp r3, #0 + 80048f6: d009 beq.n 800490c + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + 80048f8: 687b ldr r3, [r7, #4] + 80048fa: 681b ldr r3, [r3, #0] + 80048fc: 2201 movs r2, #1 + 80048fe: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_PE; + 8004900: 687b ldr r3, [r7, #4] + 8004902: 6fdb ldr r3, [r3, #124] ; 0x7c + 8004904: f043 0201 orr.w r2, r3, #1 + 8004908: 687b ldr r3, [r7, #4] + 800490a: 67da str r2, [r3, #124] ; 0x7c + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 800490c: 69fb ldr r3, [r7, #28] + 800490e: f003 0302 and.w r3, r3, #2 + 8004912: 2b00 cmp r3, #0 + 8004914: d00e beq.n 8004934 + 8004916: 697b ldr r3, [r7, #20] + 8004918: f003 0301 and.w r3, r3, #1 + 800491c: 2b00 cmp r3, #0 + 800491e: d009 beq.n 8004934 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + 8004920: 687b ldr r3, [r7, #4] + 8004922: 681b ldr r3, [r3, #0] + 8004924: 2202 movs r2, #2 + 8004926: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_FE; + 8004928: 687b ldr r3, [r7, #4] + 800492a: 6fdb ldr r3, [r3, #124] ; 0x7c + 800492c: f043 0204 orr.w r2, r3, #4 + 8004930: 687b ldr r3, [r7, #4] + 8004932: 67da str r2, [r3, #124] ; 0x7c + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8004934: 69fb ldr r3, [r7, #28] + 8004936: f003 0304 and.w r3, r3, #4 + 800493a: 2b00 cmp r3, #0 + 800493c: d00e beq.n 800495c + 800493e: 697b ldr r3, [r7, #20] + 8004940: f003 0301 and.w r3, r3, #1 + 8004944: 2b00 cmp r3, #0 + 8004946: d009 beq.n 800495c + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + 8004948: 687b ldr r3, [r7, #4] + 800494a: 681b ldr r3, [r3, #0] + 800494c: 2204 movs r2, #4 + 800494e: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_NE; + 8004950: 687b ldr r3, [r7, #4] + 8004952: 6fdb ldr r3, [r3, #124] ; 0x7c + 8004954: f043 0202 orr.w r2, r3, #2 + 8004958: 687b ldr r3, [r7, #4] + 800495a: 67da str r2, [r3, #124] ; 0x7c + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + 800495c: 69fb ldr r3, [r7, #28] + 800495e: f003 0308 and.w r3, r3, #8 + 8004962: 2b00 cmp r3, #0 + 8004964: d013 beq.n 800498e + && (((cr1its & USART_CR1_RXNEIE) != 0U) || + 8004966: 69bb ldr r3, [r7, #24] + 8004968: f003 0320 and.w r3, r3, #32 + 800496c: 2b00 cmp r3, #0 + 800496e: d104 bne.n 800497a + ((cr3its & USART_CR3_EIE) != 0U))) + 8004970: 697b ldr r3, [r7, #20] + 8004972: f003 0301 and.w r3, r3, #1 + && (((cr1its & USART_CR1_RXNEIE) != 0U) || + 8004976: 2b00 cmp r3, #0 + 8004978: d009 beq.n 800498e + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + 800497a: 687b ldr r3, [r7, #4] + 800497c: 681b ldr r3, [r3, #0] + 800497e: 2208 movs r2, #8 + 8004980: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + 8004982: 687b ldr r3, [r7, #4] + 8004984: 6fdb ldr r3, [r3, #124] ; 0x7c + 8004986: f043 0208 orr.w r2, r3, #8 + 800498a: 687b ldr r3, [r7, #4] + 800498c: 67da str r2, [r3, #124] ; 0x7c + } + + /* Call UART Error Call back function if need be --------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + 800498e: 687b ldr r3, [r7, #4] + 8004990: 6fdb ldr r3, [r3, #124] ; 0x7c + 8004992: 2b00 cmp r3, #0 + 8004994: d07f beq.n 8004a96 + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE) != 0U) + 8004996: 69fb ldr r3, [r7, #28] + 8004998: f003 0320 and.w r3, r3, #32 + 800499c: 2b00 cmp r3, #0 + 800499e: d00c beq.n 80049ba + && ((cr1its & USART_CR1_RXNEIE) != 0U)) + 80049a0: 69bb ldr r3, [r7, #24] + 80049a2: f003 0320 and.w r3, r3, #32 + 80049a6: 2b00 cmp r3, #0 + 80049a8: d007 beq.n 80049ba + { + if (huart->RxISR != NULL) + 80049aa: 687b ldr r3, [r7, #4] + 80049ac: 6e1b ldr r3, [r3, #96] ; 0x60 + 80049ae: 2b00 cmp r3, #0 + 80049b0: d003 beq.n 80049ba + { + huart->RxISR(huart); + 80049b2: 687b ldr r3, [r7, #4] + 80049b4: 6e1b ldr r3, [r3, #96] ; 0x60 + 80049b6: 6878 ldr r0, [r7, #4] + 80049b8: 4798 blx r3 + } + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + errorcode = huart->ErrorCode; + 80049ba: 687b ldr r3, [r7, #4] + 80049bc: 6fdb ldr r3, [r3, #124] ; 0x7c + 80049be: 60fb str r3, [r7, #12] + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + 80049c0: 687b ldr r3, [r7, #4] + 80049c2: 681b ldr r3, [r3, #0] + 80049c4: 689b ldr r3, [r3, #8] + 80049c6: f003 0340 and.w r3, r3, #64 ; 0x40 + 80049ca: 2b40 cmp r3, #64 ; 0x40 + 80049cc: d004 beq.n 80049d8 + ((errorcode & HAL_UART_ERROR_ORE) != 0U)) + 80049ce: 68fb ldr r3, [r7, #12] + 80049d0: f003 0308 and.w r3, r3, #8 + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + 80049d4: 2b00 cmp r3, #0 + 80049d6: d031 beq.n 8004a3c + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + 80049d8: 6878 ldr r0, [r7, #4] + 80049da: f000 fc36 bl 800524a + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 80049de: 687b ldr r3, [r7, #4] + 80049e0: 681b ldr r3, [r3, #0] + 80049e2: 689b ldr r3, [r3, #8] + 80049e4: f003 0340 and.w r3, r3, #64 ; 0x40 + 80049e8: 2b40 cmp r3, #64 ; 0x40 + 80049ea: d123 bne.n 8004a34 + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 80049ec: 687b ldr r3, [r7, #4] + 80049ee: 681b ldr r3, [r3, #0] + 80049f0: 689a ldr r2, [r3, #8] + 80049f2: 687b ldr r3, [r7, #4] + 80049f4: 681b ldr r3, [r3, #0] + 80049f6: f022 0240 bic.w r2, r2, #64 ; 0x40 + 80049fa: 609a str r2, [r3, #8] + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + 80049fc: 687b ldr r3, [r7, #4] + 80049fe: 6edb ldr r3, [r3, #108] ; 0x6c + 8004a00: 2b00 cmp r3, #0 + 8004a02: d013 beq.n 8004a2c + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + 8004a04: 687b ldr r3, [r7, #4] + 8004a06: 6edb ldr r3, [r3, #108] ; 0x6c + 8004a08: 4a26 ldr r2, [pc, #152] ; (8004aa4 ) + 8004a0a: 651a str r2, [r3, #80] ; 0x50 + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + 8004a0c: 687b ldr r3, [r7, #4] + 8004a0e: 6edb ldr r3, [r3, #108] ; 0x6c + 8004a10: 4618 mov r0, r3 + 8004a12: f7fd fa5c bl 8001ece + 8004a16: 4603 mov r3, r0 + 8004a18: 2b00 cmp r3, #0 + 8004a1a: d016 beq.n 8004a4a + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + 8004a1c: 687b ldr r3, [r7, #4] + 8004a1e: 6edb ldr r3, [r3, #108] ; 0x6c + 8004a20: 6d1b ldr r3, [r3, #80] ; 0x50 + 8004a22: 687a ldr r2, [r7, #4] + 8004a24: 6ed2 ldr r2, [r2, #108] ; 0x6c + 8004a26: 4610 mov r0, r2 + 8004a28: 4798 blx r3 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8004a2a: e00e b.n 8004a4a +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8004a2c: 6878 ldr r0, [r7, #4] + 8004a2e: f000 f845 bl 8004abc + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8004a32: e00a b.n 8004a4a +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8004a34: 6878 ldr r0, [r7, #4] + 8004a36: f000 f841 bl 8004abc + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8004a3a: e006 b.n 8004a4a +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8004a3c: 6878 ldr r0, [r7, #4] + 8004a3e: f000 f83d bl 8004abc +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8004a42: 687b ldr r3, [r7, #4] + 8004a44: 2200 movs r2, #0 + 8004a46: 67da str r2, [r3, #124] ; 0x7c + } + } + return; + 8004a48: e025 b.n 8004a96 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8004a4a: bf00 nop + return; + 8004a4c: e023 b.n 8004a96 + + } /* End if some error occurs */ + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE) != 0U) + 8004a4e: 69fb ldr r3, [r7, #28] + 8004a50: f003 0380 and.w r3, r3, #128 ; 0x80 + 8004a54: 2b00 cmp r3, #0 + 8004a56: d00d beq.n 8004a74 + && ((cr1its & USART_CR1_TXEIE) != 0U)) + 8004a58: 69bb ldr r3, [r7, #24] + 8004a5a: f003 0380 and.w r3, r3, #128 ; 0x80 + 8004a5e: 2b00 cmp r3, #0 + 8004a60: d008 beq.n 8004a74 + { + if (huart->TxISR != NULL) + 8004a62: 687b ldr r3, [r7, #4] + 8004a64: 6e5b ldr r3, [r3, #100] ; 0x64 + 8004a66: 2b00 cmp r3, #0 + 8004a68: d017 beq.n 8004a9a + { + huart->TxISR(huart); + 8004a6a: 687b ldr r3, [r7, #4] + 8004a6c: 6e5b ldr r3, [r3, #100] ; 0x64 + 8004a6e: 6878 ldr r0, [r7, #4] + 8004a70: 4798 blx r3 + } + return; + 8004a72: e012 b.n 8004a9a + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + 8004a74: 69fb ldr r3, [r7, #28] + 8004a76: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004a7a: 2b00 cmp r3, #0 + 8004a7c: d00e beq.n 8004a9c + 8004a7e: 69bb ldr r3, [r7, #24] + 8004a80: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004a84: 2b00 cmp r3, #0 + 8004a86: d009 beq.n 8004a9c + { + UART_EndTransmit_IT(huart); + 8004a88: 6878 ldr r0, [r7, #4] + 8004a8a: f000 fc14 bl 80052b6 + return; + 8004a8e: bf00 nop + 8004a90: e004 b.n 8004a9c + return; + 8004a92: bf00 nop + 8004a94: e002 b.n 8004a9c + return; + 8004a96: bf00 nop + 8004a98: e000 b.n 8004a9c + return; + 8004a9a: bf00 nop + } + +} + 8004a9c: 3720 adds r7, #32 + 8004a9e: 46bd mov sp, r7 + 8004aa0: bd80 pop {r7, pc} + 8004aa2: bf00 nop + 8004aa4: 0800528b .word 0x0800528b + +08004aa8 : + * @brief Tx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + 8004aa8: b480 push {r7} + 8004aaa: b083 sub sp, #12 + 8004aac: af00 add r7, sp, #0 + 8004aae: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file. + */ +} + 8004ab0: bf00 nop + 8004ab2: 370c adds r7, #12 + 8004ab4: 46bd mov sp, r7 + 8004ab6: f85d 7b04 ldr.w r7, [sp], #4 + 8004aba: 4770 bx lr + +08004abc : + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + 8004abc: b480 push {r7} + 8004abe: b083 sub sp, #12 + 8004ac0: af00 add r7, sp, #0 + 8004ac2: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + 8004ac4: bf00 nop + 8004ac6: 370c adds r7, #12 + 8004ac8: 46bd mov sp, r7 + 8004aca: f85d 7b04 ldr.w r7, [sp], #4 + 8004ace: 4770 bx lr + +08004ad0 : + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + 8004ad0: b580 push {r7, lr} + 8004ad2: b088 sub sp, #32 + 8004ad4: af00 add r7, sp, #0 + 8004ad6: 6078 str r0, [r7, #4] + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv = 0x00000000U; + 8004ad8: 2300 movs r3, #0 + 8004ada: 61bb str r3, [r7, #24] + HAL_StatusTypeDef ret = HAL_OK; + 8004adc: 2300 movs r3, #0 + 8004ade: 75fb strb r3, [r7, #23] + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + 8004ae0: 687b ldr r3, [r7, #4] + 8004ae2: 689a ldr r2, [r3, #8] + 8004ae4: 687b ldr r3, [r7, #4] + 8004ae6: 691b ldr r3, [r3, #16] + 8004ae8: 431a orrs r2, r3 + 8004aea: 687b ldr r3, [r7, #4] + 8004aec: 695b ldr r3, [r3, #20] + 8004aee: 431a orrs r2, r3 + 8004af0: 687b ldr r3, [r7, #4] + 8004af2: 69db ldr r3, [r3, #28] + 8004af4: 4313 orrs r3, r2 + 8004af6: 613b str r3, [r7, #16] + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 8004af8: 687b ldr r3, [r7, #4] + 8004afa: 681b ldr r3, [r3, #0] + 8004afc: 681a ldr r2, [r3, #0] + 8004afe: 4bb1 ldr r3, [pc, #708] ; (8004dc4 ) + 8004b00: 4013 ands r3, r2 + 8004b02: 687a ldr r2, [r7, #4] + 8004b04: 6812 ldr r2, [r2, #0] + 8004b06: 6939 ldr r1, [r7, #16] + 8004b08: 430b orrs r3, r1 + 8004b0a: 6013 str r3, [r2, #0] + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + 8004b0c: 687b ldr r3, [r7, #4] + 8004b0e: 681b ldr r3, [r3, #0] + 8004b10: 685b ldr r3, [r3, #4] + 8004b12: f423 5140 bic.w r1, r3, #12288 ; 0x3000 + 8004b16: 687b ldr r3, [r7, #4] + 8004b18: 68da ldr r2, [r3, #12] + 8004b1a: 687b ldr r3, [r7, #4] + 8004b1c: 681b ldr r3, [r3, #0] + 8004b1e: 430a orrs r2, r1 + 8004b20: 605a str r2, [r3, #4] + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + 8004b22: 687b ldr r3, [r7, #4] + 8004b24: 699b ldr r3, [r3, #24] + 8004b26: 613b str r3, [r7, #16] + + tmpreg |= huart->Init.OneBitSampling; + 8004b28: 687b ldr r3, [r7, #4] + 8004b2a: 6a1b ldr r3, [r3, #32] + 8004b2c: 693a ldr r2, [r7, #16] + 8004b2e: 4313 orrs r3, r2 + 8004b30: 613b str r3, [r7, #16] + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + 8004b32: 687b ldr r3, [r7, #4] + 8004b34: 681b ldr r3, [r3, #0] + 8004b36: 689b ldr r3, [r3, #8] + 8004b38: f423 6130 bic.w r1, r3, #2816 ; 0xb00 + 8004b3c: 687b ldr r3, [r7, #4] + 8004b3e: 681b ldr r3, [r3, #0] + 8004b40: 693a ldr r2, [r7, #16] + 8004b42: 430a orrs r2, r1 + 8004b44: 609a str r2, [r3, #8] + + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + 8004b46: 687b ldr r3, [r7, #4] + 8004b48: 681b ldr r3, [r3, #0] + 8004b4a: 4a9f ldr r2, [pc, #636] ; (8004dc8 ) + 8004b4c: 4293 cmp r3, r2 + 8004b4e: d121 bne.n 8004b94 + 8004b50: 4b9e ldr r3, [pc, #632] ; (8004dcc ) + 8004b52: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004b56: f003 0303 and.w r3, r3, #3 + 8004b5a: 2b03 cmp r3, #3 + 8004b5c: d816 bhi.n 8004b8c + 8004b5e: a201 add r2, pc, #4 ; (adr r2, 8004b64 ) + 8004b60: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8004b64: 08004b75 .word 0x08004b75 + 8004b68: 08004b81 .word 0x08004b81 + 8004b6c: 08004b7b .word 0x08004b7b + 8004b70: 08004b87 .word 0x08004b87 + 8004b74: 2301 movs r3, #1 + 8004b76: 77fb strb r3, [r7, #31] + 8004b78: e151 b.n 8004e1e + 8004b7a: 2302 movs r3, #2 + 8004b7c: 77fb strb r3, [r7, #31] + 8004b7e: e14e b.n 8004e1e + 8004b80: 2304 movs r3, #4 + 8004b82: 77fb strb r3, [r7, #31] + 8004b84: e14b b.n 8004e1e + 8004b86: 2308 movs r3, #8 + 8004b88: 77fb strb r3, [r7, #31] + 8004b8a: e148 b.n 8004e1e + 8004b8c: 2310 movs r3, #16 + 8004b8e: 77fb strb r3, [r7, #31] + 8004b90: bf00 nop + 8004b92: e144 b.n 8004e1e + 8004b94: 687b ldr r3, [r7, #4] + 8004b96: 681b ldr r3, [r3, #0] + 8004b98: 4a8d ldr r2, [pc, #564] ; (8004dd0 ) + 8004b9a: 4293 cmp r3, r2 + 8004b9c: d134 bne.n 8004c08 + 8004b9e: 4b8b ldr r3, [pc, #556] ; (8004dcc ) + 8004ba0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004ba4: f003 030c and.w r3, r3, #12 + 8004ba8: 2b0c cmp r3, #12 + 8004baa: d829 bhi.n 8004c00 + 8004bac: a201 add r2, pc, #4 ; (adr r2, 8004bb4 ) + 8004bae: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8004bb2: bf00 nop + 8004bb4: 08004be9 .word 0x08004be9 + 8004bb8: 08004c01 .word 0x08004c01 + 8004bbc: 08004c01 .word 0x08004c01 + 8004bc0: 08004c01 .word 0x08004c01 + 8004bc4: 08004bf5 .word 0x08004bf5 + 8004bc8: 08004c01 .word 0x08004c01 + 8004bcc: 08004c01 .word 0x08004c01 + 8004bd0: 08004c01 .word 0x08004c01 + 8004bd4: 08004bef .word 0x08004bef + 8004bd8: 08004c01 .word 0x08004c01 + 8004bdc: 08004c01 .word 0x08004c01 + 8004be0: 08004c01 .word 0x08004c01 + 8004be4: 08004bfb .word 0x08004bfb + 8004be8: 2300 movs r3, #0 + 8004bea: 77fb strb r3, [r7, #31] + 8004bec: e117 b.n 8004e1e + 8004bee: 2302 movs r3, #2 + 8004bf0: 77fb strb r3, [r7, #31] + 8004bf2: e114 b.n 8004e1e + 8004bf4: 2304 movs r3, #4 + 8004bf6: 77fb strb r3, [r7, #31] + 8004bf8: e111 b.n 8004e1e + 8004bfa: 2308 movs r3, #8 + 8004bfc: 77fb strb r3, [r7, #31] + 8004bfe: e10e b.n 8004e1e + 8004c00: 2310 movs r3, #16 + 8004c02: 77fb strb r3, [r7, #31] + 8004c04: bf00 nop + 8004c06: e10a b.n 8004e1e + 8004c08: 687b ldr r3, [r7, #4] + 8004c0a: 681b ldr r3, [r3, #0] + 8004c0c: 4a71 ldr r2, [pc, #452] ; (8004dd4 ) + 8004c0e: 4293 cmp r3, r2 + 8004c10: d120 bne.n 8004c54 + 8004c12: 4b6e ldr r3, [pc, #440] ; (8004dcc ) + 8004c14: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004c18: f003 0330 and.w r3, r3, #48 ; 0x30 + 8004c1c: 2b10 cmp r3, #16 + 8004c1e: d00f beq.n 8004c40 + 8004c20: 2b10 cmp r3, #16 + 8004c22: d802 bhi.n 8004c2a + 8004c24: 2b00 cmp r3, #0 + 8004c26: d005 beq.n 8004c34 + 8004c28: e010 b.n 8004c4c + 8004c2a: 2b20 cmp r3, #32 + 8004c2c: d005 beq.n 8004c3a + 8004c2e: 2b30 cmp r3, #48 ; 0x30 + 8004c30: d009 beq.n 8004c46 + 8004c32: e00b b.n 8004c4c + 8004c34: 2300 movs r3, #0 + 8004c36: 77fb strb r3, [r7, #31] + 8004c38: e0f1 b.n 8004e1e + 8004c3a: 2302 movs r3, #2 + 8004c3c: 77fb strb r3, [r7, #31] + 8004c3e: e0ee b.n 8004e1e + 8004c40: 2304 movs r3, #4 + 8004c42: 77fb strb r3, [r7, #31] + 8004c44: e0eb b.n 8004e1e + 8004c46: 2308 movs r3, #8 + 8004c48: 77fb strb r3, [r7, #31] + 8004c4a: e0e8 b.n 8004e1e + 8004c4c: 2310 movs r3, #16 + 8004c4e: 77fb strb r3, [r7, #31] + 8004c50: bf00 nop + 8004c52: e0e4 b.n 8004e1e + 8004c54: 687b ldr r3, [r7, #4] + 8004c56: 681b ldr r3, [r3, #0] + 8004c58: 4a5f ldr r2, [pc, #380] ; (8004dd8 ) + 8004c5a: 4293 cmp r3, r2 + 8004c5c: d120 bne.n 8004ca0 + 8004c5e: 4b5b ldr r3, [pc, #364] ; (8004dcc ) + 8004c60: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004c64: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 8004c68: 2b40 cmp r3, #64 ; 0x40 + 8004c6a: d00f beq.n 8004c8c + 8004c6c: 2b40 cmp r3, #64 ; 0x40 + 8004c6e: d802 bhi.n 8004c76 + 8004c70: 2b00 cmp r3, #0 + 8004c72: d005 beq.n 8004c80 + 8004c74: e010 b.n 8004c98 + 8004c76: 2b80 cmp r3, #128 ; 0x80 + 8004c78: d005 beq.n 8004c86 + 8004c7a: 2bc0 cmp r3, #192 ; 0xc0 + 8004c7c: d009 beq.n 8004c92 + 8004c7e: e00b b.n 8004c98 + 8004c80: 2300 movs r3, #0 + 8004c82: 77fb strb r3, [r7, #31] + 8004c84: e0cb b.n 8004e1e + 8004c86: 2302 movs r3, #2 + 8004c88: 77fb strb r3, [r7, #31] + 8004c8a: e0c8 b.n 8004e1e + 8004c8c: 2304 movs r3, #4 + 8004c8e: 77fb strb r3, [r7, #31] + 8004c90: e0c5 b.n 8004e1e + 8004c92: 2308 movs r3, #8 + 8004c94: 77fb strb r3, [r7, #31] + 8004c96: e0c2 b.n 8004e1e + 8004c98: 2310 movs r3, #16 + 8004c9a: 77fb strb r3, [r7, #31] + 8004c9c: bf00 nop + 8004c9e: e0be b.n 8004e1e + 8004ca0: 687b ldr r3, [r7, #4] + 8004ca2: 681b ldr r3, [r3, #0] + 8004ca4: 4a4d ldr r2, [pc, #308] ; (8004ddc ) + 8004ca6: 4293 cmp r3, r2 + 8004ca8: d124 bne.n 8004cf4 + 8004caa: 4b48 ldr r3, [pc, #288] ; (8004dcc ) + 8004cac: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004cb0: f403 7340 and.w r3, r3, #768 ; 0x300 + 8004cb4: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8004cb8: d012 beq.n 8004ce0 + 8004cba: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8004cbe: d802 bhi.n 8004cc6 + 8004cc0: 2b00 cmp r3, #0 + 8004cc2: d007 beq.n 8004cd4 + 8004cc4: e012 b.n 8004cec + 8004cc6: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8004cca: d006 beq.n 8004cda + 8004ccc: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 8004cd0: d009 beq.n 8004ce6 + 8004cd2: e00b b.n 8004cec + 8004cd4: 2300 movs r3, #0 + 8004cd6: 77fb strb r3, [r7, #31] + 8004cd8: e0a1 b.n 8004e1e + 8004cda: 2302 movs r3, #2 + 8004cdc: 77fb strb r3, [r7, #31] + 8004cde: e09e b.n 8004e1e + 8004ce0: 2304 movs r3, #4 + 8004ce2: 77fb strb r3, [r7, #31] + 8004ce4: e09b b.n 8004e1e + 8004ce6: 2308 movs r3, #8 + 8004ce8: 77fb strb r3, [r7, #31] + 8004cea: e098 b.n 8004e1e + 8004cec: 2310 movs r3, #16 + 8004cee: 77fb strb r3, [r7, #31] + 8004cf0: bf00 nop + 8004cf2: e094 b.n 8004e1e + 8004cf4: 687b ldr r3, [r7, #4] + 8004cf6: 681b ldr r3, [r3, #0] + 8004cf8: 4a39 ldr r2, [pc, #228] ; (8004de0 ) + 8004cfa: 4293 cmp r3, r2 + 8004cfc: d124 bne.n 8004d48 + 8004cfe: 4b33 ldr r3, [pc, #204] ; (8004dcc ) + 8004d00: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004d04: f403 6340 and.w r3, r3, #3072 ; 0xc00 + 8004d08: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8004d0c: d012 beq.n 8004d34 + 8004d0e: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8004d12: d802 bhi.n 8004d1a + 8004d14: 2b00 cmp r3, #0 + 8004d16: d007 beq.n 8004d28 + 8004d18: e012 b.n 8004d40 + 8004d1a: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 8004d1e: d006 beq.n 8004d2e + 8004d20: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 + 8004d24: d009 beq.n 8004d3a + 8004d26: e00b b.n 8004d40 + 8004d28: 2301 movs r3, #1 + 8004d2a: 77fb strb r3, [r7, #31] + 8004d2c: e077 b.n 8004e1e + 8004d2e: 2302 movs r3, #2 + 8004d30: 77fb strb r3, [r7, #31] + 8004d32: e074 b.n 8004e1e + 8004d34: 2304 movs r3, #4 + 8004d36: 77fb strb r3, [r7, #31] + 8004d38: e071 b.n 8004e1e + 8004d3a: 2308 movs r3, #8 + 8004d3c: 77fb strb r3, [r7, #31] + 8004d3e: e06e b.n 8004e1e + 8004d40: 2310 movs r3, #16 + 8004d42: 77fb strb r3, [r7, #31] + 8004d44: bf00 nop + 8004d46: e06a b.n 8004e1e + 8004d48: 687b ldr r3, [r7, #4] + 8004d4a: 681b ldr r3, [r3, #0] + 8004d4c: 4a25 ldr r2, [pc, #148] ; (8004de4 ) + 8004d4e: 4293 cmp r3, r2 + 8004d50: d124 bne.n 8004d9c + 8004d52: 4b1e ldr r3, [pc, #120] ; (8004dcc ) + 8004d54: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004d58: f403 5340 and.w r3, r3, #12288 ; 0x3000 + 8004d5c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8004d60: d012 beq.n 8004d88 + 8004d62: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8004d66: d802 bhi.n 8004d6e + 8004d68: 2b00 cmp r3, #0 + 8004d6a: d007 beq.n 8004d7c + 8004d6c: e012 b.n 8004d94 + 8004d6e: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 8004d72: d006 beq.n 8004d82 + 8004d74: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 + 8004d78: d009 beq.n 8004d8e + 8004d7a: e00b b.n 8004d94 + 8004d7c: 2300 movs r3, #0 + 8004d7e: 77fb strb r3, [r7, #31] + 8004d80: e04d b.n 8004e1e + 8004d82: 2302 movs r3, #2 + 8004d84: 77fb strb r3, [r7, #31] + 8004d86: e04a b.n 8004e1e + 8004d88: 2304 movs r3, #4 + 8004d8a: 77fb strb r3, [r7, #31] + 8004d8c: e047 b.n 8004e1e + 8004d8e: 2308 movs r3, #8 + 8004d90: 77fb strb r3, [r7, #31] + 8004d92: e044 b.n 8004e1e + 8004d94: 2310 movs r3, #16 + 8004d96: 77fb strb r3, [r7, #31] + 8004d98: bf00 nop + 8004d9a: e040 b.n 8004e1e + 8004d9c: 687b ldr r3, [r7, #4] + 8004d9e: 681b ldr r3, [r3, #0] + 8004da0: 4a11 ldr r2, [pc, #68] ; (8004de8 ) + 8004da2: 4293 cmp r3, r2 + 8004da4: d139 bne.n 8004e1a + 8004da6: 4b09 ldr r3, [pc, #36] ; (8004dcc ) + 8004da8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004dac: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 8004db0: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 8004db4: d027 beq.n 8004e06 + 8004db6: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 8004dba: d817 bhi.n 8004dec + 8004dbc: 2b00 cmp r3, #0 + 8004dbe: d01c beq.n 8004dfa + 8004dc0: e027 b.n 8004e12 + 8004dc2: bf00 nop + 8004dc4: efff69f3 .word 0xefff69f3 + 8004dc8: 40011000 .word 0x40011000 + 8004dcc: 40023800 .word 0x40023800 + 8004dd0: 40004400 .word 0x40004400 + 8004dd4: 40004800 .word 0x40004800 + 8004dd8: 40004c00 .word 0x40004c00 + 8004ddc: 40005000 .word 0x40005000 + 8004de0: 40011400 .word 0x40011400 + 8004de4: 40007800 .word 0x40007800 + 8004de8: 40007c00 .word 0x40007c00 + 8004dec: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8004df0: d006 beq.n 8004e00 + 8004df2: f5b3 4f40 cmp.w r3, #49152 ; 0xc000 + 8004df6: d009 beq.n 8004e0c + 8004df8: e00b b.n 8004e12 + 8004dfa: 2300 movs r3, #0 + 8004dfc: 77fb strb r3, [r7, #31] + 8004dfe: e00e b.n 8004e1e + 8004e00: 2302 movs r3, #2 + 8004e02: 77fb strb r3, [r7, #31] + 8004e04: e00b b.n 8004e1e + 8004e06: 2304 movs r3, #4 + 8004e08: 77fb strb r3, [r7, #31] + 8004e0a: e008 b.n 8004e1e + 8004e0c: 2308 movs r3, #8 + 8004e0e: 77fb strb r3, [r7, #31] + 8004e10: e005 b.n 8004e1e + 8004e12: 2310 movs r3, #16 + 8004e14: 77fb strb r3, [r7, #31] + 8004e16: bf00 nop + 8004e18: e001 b.n 8004e1e + 8004e1a: 2310 movs r3, #16 + 8004e1c: 77fb strb r3, [r7, #31] + + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + 8004e1e: 687b ldr r3, [r7, #4] + 8004e20: 69db ldr r3, [r3, #28] + 8004e22: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8004e26: d17c bne.n 8004f22 + { + switch (clocksource) + 8004e28: 7ffb ldrb r3, [r7, #31] + 8004e2a: 2b08 cmp r3, #8 + 8004e2c: d859 bhi.n 8004ee2 + 8004e2e: a201 add r2, pc, #4 ; (adr r2, 8004e34 ) + 8004e30: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8004e34: 08004e59 .word 0x08004e59 + 8004e38: 08004e77 .word 0x08004e77 + 8004e3c: 08004e95 .word 0x08004e95 + 8004e40: 08004ee3 .word 0x08004ee3 + 8004e44: 08004ead .word 0x08004ead + 8004e48: 08004ee3 .word 0x08004ee3 + 8004e4c: 08004ee3 .word 0x08004ee3 + 8004e50: 08004ee3 .word 0x08004ee3 + 8004e54: 08004ecb .word 0x08004ecb + { + case UART_CLOCKSOURCE_PCLK1: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + 8004e58: f7fd fe50 bl 8002afc + 8004e5c: 4603 mov r3, r0 + 8004e5e: 005a lsls r2, r3, #1 + 8004e60: 687b ldr r3, [r7, #4] + 8004e62: 685b ldr r3, [r3, #4] + 8004e64: 085b lsrs r3, r3, #1 + 8004e66: 441a add r2, r3 + 8004e68: 687b ldr r3, [r7, #4] + 8004e6a: 685b ldr r3, [r3, #4] + 8004e6c: fbb2 f3f3 udiv r3, r2, r3 + 8004e70: b29b uxth r3, r3 + 8004e72: 61bb str r3, [r7, #24] + break; + 8004e74: e038 b.n 8004ee8 + case UART_CLOCKSOURCE_PCLK2: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); + 8004e76: f7fd fe55 bl 8002b24 + 8004e7a: 4603 mov r3, r0 + 8004e7c: 005a lsls r2, r3, #1 + 8004e7e: 687b ldr r3, [r7, #4] + 8004e80: 685b ldr r3, [r3, #4] + 8004e82: 085b lsrs r3, r3, #1 + 8004e84: 441a add r2, r3 + 8004e86: 687b ldr r3, [r7, #4] + 8004e88: 685b ldr r3, [r3, #4] + 8004e8a: fbb2 f3f3 udiv r3, r2, r3 + 8004e8e: b29b uxth r3, r3 + 8004e90: 61bb str r3, [r7, #24] + break; + 8004e92: e029 b.n 8004ee8 + case UART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); + 8004e94: 687b ldr r3, [r7, #4] + 8004e96: 685b ldr r3, [r3, #4] + 8004e98: 085a lsrs r2, r3, #1 + 8004e9a: 4b5d ldr r3, [pc, #372] ; (8005010 ) + 8004e9c: 4413 add r3, r2 + 8004e9e: 687a ldr r2, [r7, #4] + 8004ea0: 6852 ldr r2, [r2, #4] + 8004ea2: fbb3 f3f2 udiv r3, r3, r2 + 8004ea6: b29b uxth r3, r3 + 8004ea8: 61bb str r3, [r7, #24] + break; + 8004eaa: e01d b.n 8004ee8 + case UART_CLOCKSOURCE_SYSCLK: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + 8004eac: f7fd fd68 bl 8002980 + 8004eb0: 4603 mov r3, r0 + 8004eb2: 005a lsls r2, r3, #1 + 8004eb4: 687b ldr r3, [r7, #4] + 8004eb6: 685b ldr r3, [r3, #4] + 8004eb8: 085b lsrs r3, r3, #1 + 8004eba: 441a add r2, r3 + 8004ebc: 687b ldr r3, [r7, #4] + 8004ebe: 685b ldr r3, [r3, #4] + 8004ec0: fbb2 f3f3 udiv r3, r2, r3 + 8004ec4: b29b uxth r3, r3 + 8004ec6: 61bb str r3, [r7, #24] + break; + 8004ec8: e00e b.n 8004ee8 + case UART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); + 8004eca: 687b ldr r3, [r7, #4] + 8004ecc: 685b ldr r3, [r3, #4] + 8004ece: 085b lsrs r3, r3, #1 + 8004ed0: f503 3280 add.w r2, r3, #65536 ; 0x10000 + 8004ed4: 687b ldr r3, [r7, #4] + 8004ed6: 685b ldr r3, [r3, #4] + 8004ed8: fbb2 f3f3 udiv r3, r2, r3 + 8004edc: b29b uxth r3, r3 + 8004ede: 61bb str r3, [r7, #24] + break; + 8004ee0: e002 b.n 8004ee8 + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + 8004ee2: 2301 movs r3, #1 + 8004ee4: 75fb strb r3, [r7, #23] + break; + 8004ee6: bf00 nop + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 8004ee8: 69bb ldr r3, [r7, #24] + 8004eea: 2b0f cmp r3, #15 + 8004eec: d916 bls.n 8004f1c + 8004eee: 69bb ldr r3, [r7, #24] + 8004ef0: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8004ef4: d212 bcs.n 8004f1c + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + 8004ef6: 69bb ldr r3, [r7, #24] + 8004ef8: b29b uxth r3, r3 + 8004efa: f023 030f bic.w r3, r3, #15 + 8004efe: 81fb strh r3, [r7, #14] + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + 8004f00: 69bb ldr r3, [r7, #24] + 8004f02: 085b lsrs r3, r3, #1 + 8004f04: b29b uxth r3, r3 + 8004f06: f003 0307 and.w r3, r3, #7 + 8004f0a: b29a uxth r2, r3 + 8004f0c: 89fb ldrh r3, [r7, #14] + 8004f0e: 4313 orrs r3, r2 + 8004f10: 81fb strh r3, [r7, #14] + huart->Instance->BRR = brrtemp; + 8004f12: 687b ldr r3, [r7, #4] + 8004f14: 681b ldr r3, [r3, #0] + 8004f16: 89fa ldrh r2, [r7, #14] + 8004f18: 60da str r2, [r3, #12] + 8004f1a: e06e b.n 8004ffa + } + else + { + ret = HAL_ERROR; + 8004f1c: 2301 movs r3, #1 + 8004f1e: 75fb strb r3, [r7, #23] + 8004f20: e06b b.n 8004ffa + } + } + else + { + switch (clocksource) + 8004f22: 7ffb ldrb r3, [r7, #31] + 8004f24: 2b08 cmp r3, #8 + 8004f26: d857 bhi.n 8004fd8 + 8004f28: a201 add r2, pc, #4 ; (adr r2, 8004f30 ) + 8004f2a: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8004f2e: bf00 nop + 8004f30: 08004f55 .word 0x08004f55 + 8004f34: 08004f71 .word 0x08004f71 + 8004f38: 08004f8d .word 0x08004f8d + 8004f3c: 08004fd9 .word 0x08004fd9 + 8004f40: 08004fa5 .word 0x08004fa5 + 8004f44: 08004fd9 .word 0x08004fd9 + 8004f48: 08004fd9 .word 0x08004fd9 + 8004f4c: 08004fd9 .word 0x08004fd9 + 8004f50: 08004fc1 .word 0x08004fc1 + { + case UART_CLOCKSOURCE_PCLK1: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + 8004f54: f7fd fdd2 bl 8002afc + 8004f58: 4602 mov r2, r0 + 8004f5a: 687b ldr r3, [r7, #4] + 8004f5c: 685b ldr r3, [r3, #4] + 8004f5e: 085b lsrs r3, r3, #1 + 8004f60: 441a add r2, r3 + 8004f62: 687b ldr r3, [r7, #4] + 8004f64: 685b ldr r3, [r3, #4] + 8004f66: fbb2 f3f3 udiv r3, r2, r3 + 8004f6a: b29b uxth r3, r3 + 8004f6c: 61bb str r3, [r7, #24] + break; + 8004f6e: e036 b.n 8004fde + case UART_CLOCKSOURCE_PCLK2: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); + 8004f70: f7fd fdd8 bl 8002b24 + 8004f74: 4602 mov r2, r0 + 8004f76: 687b ldr r3, [r7, #4] + 8004f78: 685b ldr r3, [r3, #4] + 8004f7a: 085b lsrs r3, r3, #1 + 8004f7c: 441a add r2, r3 + 8004f7e: 687b ldr r3, [r7, #4] + 8004f80: 685b ldr r3, [r3, #4] + 8004f82: fbb2 f3f3 udiv r3, r2, r3 + 8004f86: b29b uxth r3, r3 + 8004f88: 61bb str r3, [r7, #24] + break; + 8004f8a: e028 b.n 8004fde + case UART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); + 8004f8c: 687b ldr r3, [r7, #4] + 8004f8e: 685b ldr r3, [r3, #4] + 8004f90: 085a lsrs r2, r3, #1 + 8004f92: 4b20 ldr r3, [pc, #128] ; (8005014 ) + 8004f94: 4413 add r3, r2 + 8004f96: 687a ldr r2, [r7, #4] + 8004f98: 6852 ldr r2, [r2, #4] + 8004f9a: fbb3 f3f2 udiv r3, r3, r2 + 8004f9e: b29b uxth r3, r3 + 8004fa0: 61bb str r3, [r7, #24] + break; + 8004fa2: e01c b.n 8004fde + case UART_CLOCKSOURCE_SYSCLK: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + 8004fa4: f7fd fcec bl 8002980 + 8004fa8: 4602 mov r2, r0 + 8004faa: 687b ldr r3, [r7, #4] + 8004fac: 685b ldr r3, [r3, #4] + 8004fae: 085b lsrs r3, r3, #1 + 8004fb0: 441a add r2, r3 + 8004fb2: 687b ldr r3, [r7, #4] + 8004fb4: 685b ldr r3, [r3, #4] + 8004fb6: fbb2 f3f3 udiv r3, r2, r3 + 8004fba: b29b uxth r3, r3 + 8004fbc: 61bb str r3, [r7, #24] + break; + 8004fbe: e00e b.n 8004fde + case UART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); + 8004fc0: 687b ldr r3, [r7, #4] + 8004fc2: 685b ldr r3, [r3, #4] + 8004fc4: 085b lsrs r3, r3, #1 + 8004fc6: f503 4200 add.w r2, r3, #32768 ; 0x8000 + 8004fca: 687b ldr r3, [r7, #4] + 8004fcc: 685b ldr r3, [r3, #4] + 8004fce: fbb2 f3f3 udiv r3, r2, r3 + 8004fd2: b29b uxth r3, r3 + 8004fd4: 61bb str r3, [r7, #24] + break; + 8004fd6: e002 b.n 8004fde + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + 8004fd8: 2301 movs r3, #1 + 8004fda: 75fb strb r3, [r7, #23] + break; + 8004fdc: bf00 nop + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 8004fde: 69bb ldr r3, [r7, #24] + 8004fe0: 2b0f cmp r3, #15 + 8004fe2: d908 bls.n 8004ff6 + 8004fe4: 69bb ldr r3, [r7, #24] + 8004fe6: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8004fea: d204 bcs.n 8004ff6 + { + huart->Instance->BRR = usartdiv; + 8004fec: 687b ldr r3, [r7, #4] + 8004fee: 681b ldr r3, [r3, #0] + 8004ff0: 69ba ldr r2, [r7, #24] + 8004ff2: 60da str r2, [r3, #12] + 8004ff4: e001 b.n 8004ffa + } + else + { + ret = HAL_ERROR; + 8004ff6: 2301 movs r3, #1 + 8004ff8: 75fb strb r3, [r7, #23] + } + } + + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + 8004ffa: 687b ldr r3, [r7, #4] + 8004ffc: 2200 movs r2, #0 + 8004ffe: 661a str r2, [r3, #96] ; 0x60 + huart->TxISR = NULL; + 8005000: 687b ldr r3, [r7, #4] + 8005002: 2200 movs r2, #0 + 8005004: 665a str r2, [r3, #100] ; 0x64 + + return ret; + 8005006: 7dfb ldrb r3, [r7, #23] +} + 8005008: 4618 mov r0, r3 + 800500a: 3720 adds r7, #32 + 800500c: 46bd mov sp, r7 + 800500e: bd80 pop {r7, pc} + 8005010: 01e84800 .word 0x01e84800 + 8005014: 00f42400 .word 0x00f42400 + +08005018 : + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + 8005018: b480 push {r7} + 800501a: b083 sub sp, #12 + 800501c: af00 add r7, sp, #0 + 800501e: 6078 str r0, [r7, #4] + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + 8005020: 687b ldr r3, [r7, #4] + 8005022: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005024: f003 0301 and.w r3, r3, #1 + 8005028: 2b00 cmp r3, #0 + 800502a: d00a beq.n 8005042 + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + 800502c: 687b ldr r3, [r7, #4] + 800502e: 681b ldr r3, [r3, #0] + 8005030: 685b ldr r3, [r3, #4] + 8005032: f423 3100 bic.w r1, r3, #131072 ; 0x20000 + 8005036: 687b ldr r3, [r7, #4] + 8005038: 6a9a ldr r2, [r3, #40] ; 0x28 + 800503a: 687b ldr r3, [r7, #4] + 800503c: 681b ldr r3, [r3, #0] + 800503e: 430a orrs r2, r1 + 8005040: 605a str r2, [r3, #4] + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + 8005042: 687b ldr r3, [r7, #4] + 8005044: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005046: f003 0302 and.w r3, r3, #2 + 800504a: 2b00 cmp r3, #0 + 800504c: d00a beq.n 8005064 + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + 800504e: 687b ldr r3, [r7, #4] + 8005050: 681b ldr r3, [r3, #0] + 8005052: 685b ldr r3, [r3, #4] + 8005054: f423 3180 bic.w r1, r3, #65536 ; 0x10000 + 8005058: 687b ldr r3, [r7, #4] + 800505a: 6ada ldr r2, [r3, #44] ; 0x2c + 800505c: 687b ldr r3, [r7, #4] + 800505e: 681b ldr r3, [r3, #0] + 8005060: 430a orrs r2, r1 + 8005062: 605a str r2, [r3, #4] + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + 8005064: 687b ldr r3, [r7, #4] + 8005066: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005068: f003 0304 and.w r3, r3, #4 + 800506c: 2b00 cmp r3, #0 + 800506e: d00a beq.n 8005086 + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + 8005070: 687b ldr r3, [r7, #4] + 8005072: 681b ldr r3, [r3, #0] + 8005074: 685b ldr r3, [r3, #4] + 8005076: f423 2180 bic.w r1, r3, #262144 ; 0x40000 + 800507a: 687b ldr r3, [r7, #4] + 800507c: 6b1a ldr r2, [r3, #48] ; 0x30 + 800507e: 687b ldr r3, [r7, #4] + 8005080: 681b ldr r3, [r3, #0] + 8005082: 430a orrs r2, r1 + 8005084: 605a str r2, [r3, #4] + } + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + 8005086: 687b ldr r3, [r7, #4] + 8005088: 6a5b ldr r3, [r3, #36] ; 0x24 + 800508a: f003 0308 and.w r3, r3, #8 + 800508e: 2b00 cmp r3, #0 + 8005090: d00a beq.n 80050a8 + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + 8005092: 687b ldr r3, [r7, #4] + 8005094: 681b ldr r3, [r3, #0] + 8005096: 685b ldr r3, [r3, #4] + 8005098: f423 4100 bic.w r1, r3, #32768 ; 0x8000 + 800509c: 687b ldr r3, [r7, #4] + 800509e: 6b5a ldr r2, [r3, #52] ; 0x34 + 80050a0: 687b ldr r3, [r7, #4] + 80050a2: 681b ldr r3, [r3, #0] + 80050a4: 430a orrs r2, r1 + 80050a6: 605a str r2, [r3, #4] + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + 80050a8: 687b ldr r3, [r7, #4] + 80050aa: 6a5b ldr r3, [r3, #36] ; 0x24 + 80050ac: f003 0310 and.w r3, r3, #16 + 80050b0: 2b00 cmp r3, #0 + 80050b2: d00a beq.n 80050ca + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + 80050b4: 687b ldr r3, [r7, #4] + 80050b6: 681b ldr r3, [r3, #0] + 80050b8: 689b ldr r3, [r3, #8] + 80050ba: f423 5180 bic.w r1, r3, #4096 ; 0x1000 + 80050be: 687b ldr r3, [r7, #4] + 80050c0: 6b9a ldr r2, [r3, #56] ; 0x38 + 80050c2: 687b ldr r3, [r7, #4] + 80050c4: 681b ldr r3, [r3, #0] + 80050c6: 430a orrs r2, r1 + 80050c8: 609a str r2, [r3, #8] + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + 80050ca: 687b ldr r3, [r7, #4] + 80050cc: 6a5b ldr r3, [r3, #36] ; 0x24 + 80050ce: f003 0320 and.w r3, r3, #32 + 80050d2: 2b00 cmp r3, #0 + 80050d4: d00a beq.n 80050ec + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + 80050d6: 687b ldr r3, [r7, #4] + 80050d8: 681b ldr r3, [r3, #0] + 80050da: 689b ldr r3, [r3, #8] + 80050dc: f423 5100 bic.w r1, r3, #8192 ; 0x2000 + 80050e0: 687b ldr r3, [r7, #4] + 80050e2: 6bda ldr r2, [r3, #60] ; 0x3c + 80050e4: 687b ldr r3, [r7, #4] + 80050e6: 681b ldr r3, [r3, #0] + 80050e8: 430a orrs r2, r1 + 80050ea: 609a str r2, [r3, #8] + } + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + 80050ec: 687b ldr r3, [r7, #4] + 80050ee: 6a5b ldr r3, [r3, #36] ; 0x24 + 80050f0: f003 0340 and.w r3, r3, #64 ; 0x40 + 80050f4: 2b00 cmp r3, #0 + 80050f6: d01a beq.n 800512e + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + 80050f8: 687b ldr r3, [r7, #4] + 80050fa: 681b ldr r3, [r3, #0] + 80050fc: 685b ldr r3, [r3, #4] + 80050fe: f423 1180 bic.w r1, r3, #1048576 ; 0x100000 + 8005102: 687b ldr r3, [r7, #4] + 8005104: 6c1a ldr r2, [r3, #64] ; 0x40 + 8005106: 687b ldr r3, [r7, #4] + 8005108: 681b ldr r3, [r3, #0] + 800510a: 430a orrs r2, r1 + 800510c: 605a str r2, [r3, #4] + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + 800510e: 687b ldr r3, [r7, #4] + 8005110: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005112: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 8005116: d10a bne.n 800512e + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + 8005118: 687b ldr r3, [r7, #4] + 800511a: 681b ldr r3, [r3, #0] + 800511c: 685b ldr r3, [r3, #4] + 800511e: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000 + 8005122: 687b ldr r3, [r7, #4] + 8005124: 6c5a ldr r2, [r3, #68] ; 0x44 + 8005126: 687b ldr r3, [r7, #4] + 8005128: 681b ldr r3, [r3, #0] + 800512a: 430a orrs r2, r1 + 800512c: 605a str r2, [r3, #4] + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + 800512e: 687b ldr r3, [r7, #4] + 8005130: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005132: f003 0380 and.w r3, r3, #128 ; 0x80 + 8005136: 2b00 cmp r3, #0 + 8005138: d00a beq.n 8005150 + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + 800513a: 687b ldr r3, [r7, #4] + 800513c: 681b ldr r3, [r3, #0] + 800513e: 685b ldr r3, [r3, #4] + 8005140: f423 2100 bic.w r1, r3, #524288 ; 0x80000 + 8005144: 687b ldr r3, [r7, #4] + 8005146: 6c9a ldr r2, [r3, #72] ; 0x48 + 8005148: 687b ldr r3, [r7, #4] + 800514a: 681b ldr r3, [r3, #0] + 800514c: 430a orrs r2, r1 + 800514e: 605a str r2, [r3, #4] + } +} + 8005150: bf00 nop + 8005152: 370c adds r7, #12 + 8005154: 46bd mov sp, r7 + 8005156: f85d 7b04 ldr.w r7, [sp], #4 + 800515a: 4770 bx lr + +0800515c : + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + 800515c: b580 push {r7, lr} + 800515e: b086 sub sp, #24 + 8005160: af02 add r7, sp, #8 + 8005162: 6078 str r0, [r7, #4] + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8005164: 687b ldr r3, [r7, #4] + 8005166: 2200 movs r2, #0 + 8005168: 67da str r2, [r3, #124] ; 0x7c + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + 800516a: f7fc fd93 bl 8001c94 + 800516e: 60f8 str r0, [r7, #12] + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + 8005170: 687b ldr r3, [r7, #4] + 8005172: 681b ldr r3, [r3, #0] + 8005174: 681b ldr r3, [r3, #0] + 8005176: f003 0308 and.w r3, r3, #8 + 800517a: 2b08 cmp r3, #8 + 800517c: d10e bne.n 800519c + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + 800517e: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 + 8005182: 9300 str r3, [sp, #0] + 8005184: 68fb ldr r3, [r7, #12] + 8005186: 2200 movs r2, #0 + 8005188: f44f 1100 mov.w r1, #2097152 ; 0x200000 + 800518c: 6878 ldr r0, [r7, #4] + 800518e: f000 f814 bl 80051ba + 8005192: 4603 mov r3, r0 + 8005194: 2b00 cmp r3, #0 + 8005196: d001 beq.n 800519c + { + /* Timeout occurred */ + return HAL_TIMEOUT; + 8005198: 2303 movs r3, #3 + 800519a: e00a b.n 80051b2 + } + } + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + 800519c: 687b ldr r3, [r7, #4] + 800519e: 2220 movs r2, #32 + 80051a0: 675a str r2, [r3, #116] ; 0x74 + huart->RxState = HAL_UART_STATE_READY; + 80051a2: 687b ldr r3, [r7, #4] + 80051a4: 2220 movs r2, #32 + 80051a6: 679a str r2, [r3, #120] ; 0x78 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 80051a8: 687b ldr r3, [r7, #4] + 80051aa: 2200 movs r2, #0 + 80051ac: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + return HAL_OK; + 80051b0: 2300 movs r3, #0 +} + 80051b2: 4618 mov r0, r3 + 80051b4: 3710 adds r7, #16 + 80051b6: 46bd mov sp, r7 + 80051b8: bd80 pop {r7, pc} + +080051ba : + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +{ + 80051ba: b580 push {r7, lr} + 80051bc: b084 sub sp, #16 + 80051be: af00 add r7, sp, #0 + 80051c0: 60f8 str r0, [r7, #12] + 80051c2: 60b9 str r1, [r7, #8] + 80051c4: 603b str r3, [r7, #0] + 80051c6: 4613 mov r3, r2 + 80051c8: 71fb strb r3, [r7, #7] + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 80051ca: e02a b.n 8005222 + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 80051cc: 69bb ldr r3, [r7, #24] + 80051ce: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 80051d2: d026 beq.n 8005222 + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 80051d4: f7fc fd5e bl 8001c94 + 80051d8: 4602 mov r2, r0 + 80051da: 683b ldr r3, [r7, #0] + 80051dc: 1ad3 subs r3, r2, r3 + 80051de: 69ba ldr r2, [r7, #24] + 80051e0: 429a cmp r2, r3 + 80051e2: d302 bcc.n 80051ea + 80051e4: 69bb ldr r3, [r7, #24] + 80051e6: 2b00 cmp r3, #0 + 80051e8: d11b bne.n 8005222 + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + 80051ea: 68fb ldr r3, [r7, #12] + 80051ec: 681b ldr r3, [r3, #0] + 80051ee: 681a ldr r2, [r3, #0] + 80051f0: 68fb ldr r3, [r7, #12] + 80051f2: 681b ldr r3, [r3, #0] + 80051f4: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 + 80051f8: 601a str r2, [r3, #0] + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 80051fa: 68fb ldr r3, [r7, #12] + 80051fc: 681b ldr r3, [r3, #0] + 80051fe: 689a ldr r2, [r3, #8] + 8005200: 68fb ldr r3, [r7, #12] + 8005202: 681b ldr r3, [r3, #0] + 8005204: f022 0201 bic.w r2, r2, #1 + 8005208: 609a str r2, [r3, #8] + + huart->gState = HAL_UART_STATE_READY; + 800520a: 68fb ldr r3, [r7, #12] + 800520c: 2220 movs r2, #32 + 800520e: 675a str r2, [r3, #116] ; 0x74 + huart->RxState = HAL_UART_STATE_READY; + 8005210: 68fb ldr r3, [r7, #12] + 8005212: 2220 movs r2, #32 + 8005214: 679a str r2, [r3, #120] ; 0x78 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8005216: 68fb ldr r3, [r7, #12] + 8005218: 2200 movs r2, #0 + 800521a: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + return HAL_TIMEOUT; + 800521e: 2303 movs r3, #3 + 8005220: e00f b.n 8005242 + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 8005222: 68fb ldr r3, [r7, #12] + 8005224: 681b ldr r3, [r3, #0] + 8005226: 69da ldr r2, [r3, #28] + 8005228: 68bb ldr r3, [r7, #8] + 800522a: 4013 ands r3, r2 + 800522c: 68ba ldr r2, [r7, #8] + 800522e: 429a cmp r2, r3 + 8005230: bf0c ite eq + 8005232: 2301 moveq r3, #1 + 8005234: 2300 movne r3, #0 + 8005236: b2db uxtb r3, r3 + 8005238: 461a mov r2, r3 + 800523a: 79fb ldrb r3, [r7, #7] + 800523c: 429a cmp r2, r3 + 800523e: d0c5 beq.n 80051cc + } + } + } + return HAL_OK; + 8005240: 2300 movs r3, #0 +} + 8005242: 4618 mov r0, r3 + 8005244: 3710 adds r7, #16 + 8005246: 46bd mov sp, r7 + 8005248: bd80 pop {r7, pc} + +0800524a : + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + 800524a: b480 push {r7} + 800524c: b083 sub sp, #12 + 800524e: af00 add r7, sp, #0 + 8005250: 6078 str r0, [r7, #4] + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + 8005252: 687b ldr r3, [r7, #4] + 8005254: 681b ldr r3, [r3, #0] + 8005256: 681a ldr r2, [r3, #0] + 8005258: 687b ldr r3, [r7, #4] + 800525a: 681b ldr r3, [r3, #0] + 800525c: f422 7290 bic.w r2, r2, #288 ; 0x120 + 8005260: 601a str r2, [r3, #0] + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8005262: 687b ldr r3, [r7, #4] + 8005264: 681b ldr r3, [r3, #0] + 8005266: 689a ldr r2, [r3, #8] + 8005268: 687b ldr r3, [r7, #4] + 800526a: 681b ldr r3, [r3, #0] + 800526c: f022 0201 bic.w r2, r2, #1 + 8005270: 609a str r2, [r3, #8] + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8005272: 687b ldr r3, [r7, #4] + 8005274: 2220 movs r2, #32 + 8005276: 679a str r2, [r3, #120] ; 0x78 + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; + 8005278: 687b ldr r3, [r7, #4] + 800527a: 2200 movs r2, #0 + 800527c: 661a str r2, [r3, #96] ; 0x60 +} + 800527e: bf00 nop + 8005280: 370c adds r7, #12 + 8005282: 46bd mov sp, r7 + 8005284: f85d 7b04 ldr.w r7, [sp], #4 + 8005288: 4770 bx lr + +0800528a : + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + 800528a: b580 push {r7, lr} + 800528c: b084 sub sp, #16 + 800528e: af00 add r7, sp, #0 + 8005290: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 8005292: 687b ldr r3, [r7, #4] + 8005294: 6b9b ldr r3, [r3, #56] ; 0x38 + 8005296: 60fb str r3, [r7, #12] + huart->RxXferCount = 0U; + 8005298: 68fb ldr r3, [r7, #12] + 800529a: 2200 movs r2, #0 + 800529c: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + huart->TxXferCount = 0U; + 80052a0: 68fb ldr r3, [r7, #12] + 80052a2: 2200 movs r2, #0 + 80052a4: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 80052a8: 68f8 ldr r0, [r7, #12] + 80052aa: f7ff fc07 bl 8004abc +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 80052ae: bf00 nop + 80052b0: 3710 adds r7, #16 + 80052b2: 46bd mov sp, r7 + 80052b4: bd80 pop {r7, pc} + +080052b6 : + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + 80052b6: b580 push {r7, lr} + 80052b8: b082 sub sp, #8 + 80052ba: af00 add r7, sp, #0 + 80052bc: 6078 str r0, [r7, #4] + /* Disable the UART Transmit Complete Interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + 80052be: 687b ldr r3, [r7, #4] + 80052c0: 681b ldr r3, [r3, #0] + 80052c2: 681a ldr r2, [r3, #0] + 80052c4: 687b ldr r3, [r7, #4] + 80052c6: 681b ldr r3, [r3, #0] + 80052c8: f022 0240 bic.w r2, r2, #64 ; 0x40 + 80052cc: 601a str r2, [r3, #0] + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 80052ce: 687b ldr r3, [r7, #4] + 80052d0: 2220 movs r2, #32 + 80052d2: 675a str r2, [r3, #116] ; 0x74 + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + 80052d4: 687b ldr r3, [r7, #4] + 80052d6: 2200 movs r2, #0 + 80052d8: 665a str r2, [r3, #100] ; 0x64 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); + 80052da: 6878 ldr r0, [r7, #4] + 80052dc: f7ff fbe4 bl 8004aa8 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 80052e0: bf00 nop + 80052e2: 3708 adds r7, #8 + 80052e4: 46bd mov sp, r7 + 80052e6: bd80 pop {r7, pc} + +080052e8 : + * @brief RX interrrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + 80052e8: b580 push {r7, lr} + 80052ea: b084 sub sp, #16 + 80052ec: af00 add r7, sp, #0 + 80052ee: 6078 str r0, [r7, #4] + uint16_t uhMask = huart->Mask; + 80052f0: 687b ldr r3, [r7, #4] + 80052f2: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c + 80052f6: 81fb strh r3, [r7, #14] + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 80052f8: 687b ldr r3, [r7, #4] + 80052fa: 6f9b ldr r3, [r3, #120] ; 0x78 + 80052fc: 2b22 cmp r3, #34 ; 0x22 + 80052fe: d13a bne.n 8005376 + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 8005300: 687b ldr r3, [r7, #4] + 8005302: 681b ldr r3, [r3, #0] + 8005304: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005306: 81bb strh r3, [r7, #12] + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + 8005308: 89bb ldrh r3, [r7, #12] + 800530a: b2d9 uxtb r1, r3 + 800530c: 89fb ldrh r3, [r7, #14] + 800530e: b2da uxtb r2, r3 + 8005310: 687b ldr r3, [r7, #4] + 8005312: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005314: 400a ands r2, r1 + 8005316: b2d2 uxtb r2, r2 + 8005318: 701a strb r2, [r3, #0] + huart->pRxBuffPtr++; + 800531a: 687b ldr r3, [r7, #4] + 800531c: 6d5b ldr r3, [r3, #84] ; 0x54 + 800531e: 1c5a adds r2, r3, #1 + 8005320: 687b ldr r3, [r7, #4] + 8005322: 655a str r2, [r3, #84] ; 0x54 + huart->RxXferCount--; + 8005324: 687b ldr r3, [r7, #4] + 8005326: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 800532a: b29b uxth r3, r3 + 800532c: 3b01 subs r3, #1 + 800532e: b29a uxth r2, r3 + 8005330: 687b ldr r3, [r7, #4] + 8005332: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + + if (huart->RxXferCount == 0U) + 8005336: 687b ldr r3, [r7, #4] + 8005338: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 800533c: b29b uxth r3, r3 + 800533e: 2b00 cmp r3, #0 + 8005340: d121 bne.n 8005386 + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + 8005342: 687b ldr r3, [r7, #4] + 8005344: 681b ldr r3, [r3, #0] + 8005346: 681a ldr r2, [r3, #0] + 8005348: 687b ldr r3, [r7, #4] + 800534a: 681b ldr r3, [r3, #0] + 800534c: f422 7290 bic.w r2, r2, #288 ; 0x120 + 8005350: 601a str r2, [r3, #0] + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8005352: 687b ldr r3, [r7, #4] + 8005354: 681b ldr r3, [r3, #0] + 8005356: 689a ldr r2, [r3, #8] + 8005358: 687b ldr r3, [r7, #4] + 800535a: 681b ldr r3, [r3, #0] + 800535c: f022 0201 bic.w r2, r2, #1 + 8005360: 609a str r2, [r3, #8] + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8005362: 687b ldr r3, [r7, #4] + 8005364: 2220 movs r2, #32 + 8005366: 679a str r2, [r3, #120] ; 0x78 + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 8005368: 687b ldr r3, [r7, #4] + 800536a: 2200 movs r2, #0 + 800536c: 661a str r2, [r3, #96] ; 0x60 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); + 800536e: 6878 ldr r0, [r7, #4] + 8005370: f7fc f8be bl 80014f0 + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + 8005374: e007 b.n 8005386 + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 8005376: 687b ldr r3, [r7, #4] + 8005378: 681b ldr r3, [r3, #0] + 800537a: 699a ldr r2, [r3, #24] + 800537c: 687b ldr r3, [r7, #4] + 800537e: 681b ldr r3, [r3, #0] + 8005380: f042 0208 orr.w r2, r2, #8 + 8005384: 619a str r2, [r3, #24] +} + 8005386: bf00 nop + 8005388: 3710 adds r7, #16 + 800538a: 46bd mov sp, r7 + 800538c: bd80 pop {r7, pc} + +0800538e : + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + 800538e: b580 push {r7, lr} + 8005390: b084 sub sp, #16 + 8005392: af00 add r7, sp, #0 + 8005394: 6078 str r0, [r7, #4] + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + 8005396: 687b ldr r3, [r7, #4] + 8005398: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c + 800539c: 81fb strh r3, [r7, #14] + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 800539e: 687b ldr r3, [r7, #4] + 80053a0: 6f9b ldr r3, [r3, #120] ; 0x78 + 80053a2: 2b22 cmp r3, #34 ; 0x22 + 80053a4: d13a bne.n 800541c + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 80053a6: 687b ldr r3, [r7, #4] + 80053a8: 681b ldr r3, [r3, #0] + 80053aa: 6a5b ldr r3, [r3, #36] ; 0x24 + 80053ac: 81bb strh r3, [r7, #12] + tmp = (uint16_t *) huart->pRxBuffPtr ; + 80053ae: 687b ldr r3, [r7, #4] + 80053b0: 6d5b ldr r3, [r3, #84] ; 0x54 + 80053b2: 60bb str r3, [r7, #8] + *tmp = (uint16_t)(uhdata & uhMask); + 80053b4: 89ba ldrh r2, [r7, #12] + 80053b6: 89fb ldrh r3, [r7, #14] + 80053b8: 4013 ands r3, r2 + 80053ba: b29a uxth r2, r3 + 80053bc: 68bb ldr r3, [r7, #8] + 80053be: 801a strh r2, [r3, #0] + huart->pRxBuffPtr += 2U; + 80053c0: 687b ldr r3, [r7, #4] + 80053c2: 6d5b ldr r3, [r3, #84] ; 0x54 + 80053c4: 1c9a adds r2, r3, #2 + 80053c6: 687b ldr r3, [r7, #4] + 80053c8: 655a str r2, [r3, #84] ; 0x54 + huart->RxXferCount--; + 80053ca: 687b ldr r3, [r7, #4] + 80053cc: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 80053d0: b29b uxth r3, r3 + 80053d2: 3b01 subs r3, #1 + 80053d4: b29a uxth r2, r3 + 80053d6: 687b ldr r3, [r7, #4] + 80053d8: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + + if (huart->RxXferCount == 0U) + 80053dc: 687b ldr r3, [r7, #4] + 80053de: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 80053e2: b29b uxth r3, r3 + 80053e4: 2b00 cmp r3, #0 + 80053e6: d121 bne.n 800542c + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + 80053e8: 687b ldr r3, [r7, #4] + 80053ea: 681b ldr r3, [r3, #0] + 80053ec: 681a ldr r2, [r3, #0] + 80053ee: 687b ldr r3, [r7, #4] + 80053f0: 681b ldr r3, [r3, #0] + 80053f2: f422 7290 bic.w r2, r2, #288 ; 0x120 + 80053f6: 601a str r2, [r3, #0] + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 80053f8: 687b ldr r3, [r7, #4] + 80053fa: 681b ldr r3, [r3, #0] + 80053fc: 689a ldr r2, [r3, #8] + 80053fe: 687b ldr r3, [r7, #4] + 8005400: 681b ldr r3, [r3, #0] + 8005402: f022 0201 bic.w r2, r2, #1 + 8005406: 609a str r2, [r3, #8] + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8005408: 687b ldr r3, [r7, #4] + 800540a: 2220 movs r2, #32 + 800540c: 679a str r2, [r3, #120] ; 0x78 + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 800540e: 687b ldr r3, [r7, #4] + 8005410: 2200 movs r2, #0 + 8005412: 661a str r2, [r3, #96] ; 0x60 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); + 8005414: 6878 ldr r0, [r7, #4] + 8005416: f7fc f86b bl 80014f0 + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + 800541a: e007 b.n 800542c + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 800541c: 687b ldr r3, [r7, #4] + 800541e: 681b ldr r3, [r3, #0] + 8005420: 699a ldr r2, [r3, #24] + 8005422: 687b ldr r3, [r7, #4] + 8005424: 681b ldr r3, [r3, #0] + 8005426: f042 0208 orr.w r2, r2, #8 + 800542a: 619a str r2, [r3, #24] +} + 800542c: bf00 nop + 800542e: 3710 adds r7, #16 + 8005430: 46bd mov sp, r7 + 8005432: bd80 pop {r7, pc} + +08005434 <__libc_init_array>: + 8005434: b570 push {r4, r5, r6, lr} + 8005436: 4e0d ldr r6, [pc, #52] ; (800546c <__libc_init_array+0x38>) + 8005438: 4c0d ldr r4, [pc, #52] ; (8005470 <__libc_init_array+0x3c>) + 800543a: 1ba4 subs r4, r4, r6 + 800543c: 10a4 asrs r4, r4, #2 + 800543e: 2500 movs r5, #0 + 8005440: 42a5 cmp r5, r4 + 8005442: d109 bne.n 8005458 <__libc_init_array+0x24> + 8005444: 4e0b ldr r6, [pc, #44] ; (8005474 <__libc_init_array+0x40>) + 8005446: 4c0c ldr r4, [pc, #48] ; (8005478 <__libc_init_array+0x44>) + 8005448: f000 f820 bl 800548c <_init> + 800544c: 1ba4 subs r4, r4, r6 + 800544e: 10a4 asrs r4, r4, #2 + 8005450: 2500 movs r5, #0 + 8005452: 42a5 cmp r5, r4 + 8005454: d105 bne.n 8005462 <__libc_init_array+0x2e> + 8005456: bd70 pop {r4, r5, r6, pc} + 8005458: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 800545c: 4798 blx r3 + 800545e: 3501 adds r5, #1 + 8005460: e7ee b.n 8005440 <__libc_init_array+0xc> + 8005462: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 8005466: 4798 blx r3 + 8005468: 3501 adds r5, #1 + 800546a: e7f2 b.n 8005452 <__libc_init_array+0x1e> + 800546c: 080054c4 .word 0x080054c4 + 8005470: 080054c4 .word 0x080054c4 + 8005474: 080054c4 .word 0x080054c4 + 8005478: 080054cc .word 0x080054cc + +0800547c : + 800547c: 4402 add r2, r0 + 800547e: 4603 mov r3, r0 + 8005480: 4293 cmp r3, r2 + 8005482: d100 bne.n 8005486 + 8005484: 4770 bx lr + 8005486: f803 1b01 strb.w r1, [r3], #1 + 800548a: e7f9 b.n 8005480 + +0800548c <_init>: + 800548c: b5f8 push {r3, r4, r5, r6, r7, lr} + 800548e: bf00 nop + 8005490: bcf8 pop {r3, r4, r5, r6, r7} + 8005492: bc08 pop {r3} + 8005494: 469e mov lr, r3 + 8005496: 4770 bx lr + +08005498 <_fini>: + 8005498: b5f8 push {r3, r4, r5, r6, r7, lr} + 800549a: bf00 nop + 800549c: bcf8 pop {r3, r4, r5, r6, r7} + 800549e: bc08 pop {r3} + 80054a0: 469e mov lr, r3 + 80054a2: 4770 bx lr diff --git a/utils/ticks_calibration/otto_ticks_calibration/Debug/sources.mk b/utils/ticks_calibration/otto_ticks_calibration/Debug/sources.mk new file mode 100644 index 0000000..ab6831f --- /dev/null +++ b/utils/ticks_calibration/otto_ticks_calibration/Debug/sources.mk @@ -0,0 +1,32 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +ELF_SRCS := +C_UPPER_SRCS := +CXX_SRCS := +C++_SRCS := +OBJ_SRCS := +S_SRCS := +CC_SRCS := +C_SRCS := +CPP_SRCS := +S_UPPER_SRCS := +O_SRCS := +CC_DEPS := +SIZE_OUTPUT := +OBJDUMP_LIST := +C++_DEPS := +EXECUTABLES := +OBJS := +C_UPPER_DEPS := +CXX_DEPS := +C_DEPS := +CPP_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Drivers/STM32F7xx_HAL_Driver/Src \ + -- 2.52.0