+++ /dev/null
-
-otto_pid_tuning.elf: file format elf32-littlearm
-
-Sections:
-Idx Name Size VMA LMA File off Algn
- 0 .isr_vector 000001f8 08000000 08000000 00010000 2**0
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 1 .text 000053e0 080001f8 080001f8 000101f8 2**3
- CONTENTS, ALLOC, LOAD, READONLY, CODE
- 2 .rodata 00000018 080055d8 080055d8 000155d8 2**2
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 3 .ARM.extab 00000000 080055f0 080055f0 00020010 2**0
- CONTENTS
- 4 .ARM 00000008 080055f0 080055f0 000155f0 2**2
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 5 .preinit_array 00000000 080055f8 080055f8 00020010 2**0
- CONTENTS, ALLOC, LOAD, DATA
- 6 .init_array 00000008 080055f8 080055f8 000155f8 2**2
- CONTENTS, ALLOC, LOAD, DATA
- 7 .fini_array 00000004 08005600 08005600 00015600 2**2
- CONTENTS, ALLOC, LOAD, DATA
- 8 .data 00000010 20000000 08005604 00020000 2**2
- CONTENTS, ALLOC, LOAD, DATA
- 9 .bss 000002fc 20000010 08005614 00020010 2**2
- ALLOC
- 10 ._user_heap_stack 00000604 2000030c 08005614 0002030c 2**0
- ALLOC
- 11 .ARM.attributes 0000002e 00000000 00000000 00020010 2**0
- CONTENTS, READONLY
- 12 .debug_info 0000dba7 00000000 00000000 0002003e 2**0
- CONTENTS, READONLY, DEBUGGING
- 13 .debug_abbrev 00001e1a 00000000 00000000 0002dbe5 2**0
- CONTENTS, READONLY, DEBUGGING
- 14 .debug_aranges 00000d60 00000000 00000000 0002fa00 2**3
- CONTENTS, READONLY, DEBUGGING
- 15 .debug_ranges 00000c78 00000000 00000000 00030760 2**3
- CONTENTS, READONLY, DEBUGGING
- 16 .debug_macro 00028237 00000000 00000000 000313d8 2**0
- CONTENTS, READONLY, DEBUGGING
- 17 .debug_line 00009a73 00000000 00000000 0005960f 2**0
- CONTENTS, READONLY, DEBUGGING
- 18 .debug_str 000f1e08 00000000 00000000 00063082 2**0
- CONTENTS, READONLY, DEBUGGING
- 19 .comment 0000007b 00000000 00000000 00154e8a 2**0
- CONTENTS, READONLY
- 20 .debug_frame 00003830 00000000 00000000 00154f08 2**2
- CONTENTS, READONLY, DEBUGGING
-
-Disassembly of section .text:
-
-080001f8 <__do_global_dtors_aux>:
- 80001f8: b510 push {r4, lr}
- 80001fa: 4c05 ldr r4, [pc, #20] ; (8000210 <__do_global_dtors_aux+0x18>)
- 80001fc: 7823 ldrb r3, [r4, #0]
- 80001fe: b933 cbnz r3, 800020e <__do_global_dtors_aux+0x16>
- 8000200: 4b04 ldr r3, [pc, #16] ; (8000214 <__do_global_dtors_aux+0x1c>)
- 8000202: b113 cbz r3, 800020a <__do_global_dtors_aux+0x12>
- 8000204: 4804 ldr r0, [pc, #16] ; (8000218 <__do_global_dtors_aux+0x20>)
- 8000206: f3af 8000 nop.w
- 800020a: 2301 movs r3, #1
- 800020c: 7023 strb r3, [r4, #0]
- 800020e: bd10 pop {r4, pc}
- 8000210: 20000010 .word 0x20000010
- 8000214: 00000000 .word 0x00000000
- 8000218: 080055c0 .word 0x080055c0
-
-0800021c <frame_dummy>:
- 800021c: b508 push {r3, lr}
- 800021e: 4b03 ldr r3, [pc, #12] ; (800022c <frame_dummy+0x10>)
- 8000220: b11b cbz r3, 800022a <frame_dummy+0xe>
- 8000222: 4903 ldr r1, [pc, #12] ; (8000230 <frame_dummy+0x14>)
- 8000224: 4803 ldr r0, [pc, #12] ; (8000234 <frame_dummy+0x18>)
- 8000226: f3af 8000 nop.w
- 800022a: bd08 pop {r3, pc}
- 800022c: 00000000 .word 0x00000000
- 8000230: 20000014 .word 0x20000014
- 8000234: 080055c0 .word 0x080055c0
-
-08000238 <__aeabi_uldivmod>:
- 8000238: b953 cbnz r3, 8000250 <__aeabi_uldivmod+0x18>
- 800023a: b94a cbnz r2, 8000250 <__aeabi_uldivmod+0x18>
- 800023c: 2900 cmp r1, #0
- 800023e: bf08 it eq
- 8000240: 2800 cmpeq r0, #0
- 8000242: bf1c itt ne
- 8000244: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff
- 8000248: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff
- 800024c: f000 b972 b.w 8000534 <__aeabi_idiv0>
- 8000250: f1ad 0c08 sub.w ip, sp, #8
- 8000254: e96d ce04 strd ip, lr, [sp, #-16]!
- 8000258: f000 f806 bl 8000268 <__udivmoddi4>
- 800025c: f8dd e004 ldr.w lr, [sp, #4]
- 8000260: e9dd 2302 ldrd r2, r3, [sp, #8]
- 8000264: b004 add sp, #16
- 8000266: 4770 bx lr
-
-08000268 <__udivmoddi4>:
- 8000268: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
- 800026c: 9e08 ldr r6, [sp, #32]
- 800026e: 4604 mov r4, r0
- 8000270: 4688 mov r8, r1
- 8000272: 2b00 cmp r3, #0
- 8000274: d14b bne.n 800030e <__udivmoddi4+0xa6>
- 8000276: 428a cmp r2, r1
- 8000278: 4615 mov r5, r2
- 800027a: d967 bls.n 800034c <__udivmoddi4+0xe4>
- 800027c: fab2 f282 clz r2, r2
- 8000280: b14a cbz r2, 8000296 <__udivmoddi4+0x2e>
- 8000282: f1c2 0720 rsb r7, r2, #32
- 8000286: fa01 f302 lsl.w r3, r1, r2
- 800028a: fa20 f707 lsr.w r7, r0, r7
- 800028e: 4095 lsls r5, r2
- 8000290: ea47 0803 orr.w r8, r7, r3
- 8000294: 4094 lsls r4, r2
- 8000296: ea4f 4e15 mov.w lr, r5, lsr #16
- 800029a: 0c23 lsrs r3, r4, #16
- 800029c: fbb8 f7fe udiv r7, r8, lr
- 80002a0: fa1f fc85 uxth.w ip, r5
- 80002a4: fb0e 8817 mls r8, lr, r7, r8
- 80002a8: ea43 4308 orr.w r3, r3, r8, lsl #16
- 80002ac: fb07 f10c mul.w r1, r7, ip
- 80002b0: 4299 cmp r1, r3
- 80002b2: d909 bls.n 80002c8 <__udivmoddi4+0x60>
- 80002b4: 18eb adds r3, r5, r3
- 80002b6: f107 30ff add.w r0, r7, #4294967295 ; 0xffffffff
- 80002ba: f080 811b bcs.w 80004f4 <__udivmoddi4+0x28c>
- 80002be: 4299 cmp r1, r3
- 80002c0: f240 8118 bls.w 80004f4 <__udivmoddi4+0x28c>
- 80002c4: 3f02 subs r7, #2
- 80002c6: 442b add r3, r5
- 80002c8: 1a5b subs r3, r3, r1
- 80002ca: b2a4 uxth r4, r4
- 80002cc: fbb3 f0fe udiv r0, r3, lr
- 80002d0: fb0e 3310 mls r3, lr, r0, r3
- 80002d4: ea44 4403 orr.w r4, r4, r3, lsl #16
- 80002d8: fb00 fc0c mul.w ip, r0, ip
- 80002dc: 45a4 cmp ip, r4
- 80002de: d909 bls.n 80002f4 <__udivmoddi4+0x8c>
- 80002e0: 192c adds r4, r5, r4
- 80002e2: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
- 80002e6: f080 8107 bcs.w 80004f8 <__udivmoddi4+0x290>
- 80002ea: 45a4 cmp ip, r4
- 80002ec: f240 8104 bls.w 80004f8 <__udivmoddi4+0x290>
- 80002f0: 3802 subs r0, #2
- 80002f2: 442c add r4, r5
- 80002f4: ea40 4007 orr.w r0, r0, r7, lsl #16
- 80002f8: eba4 040c sub.w r4, r4, ip
- 80002fc: 2700 movs r7, #0
- 80002fe: b11e cbz r6, 8000308 <__udivmoddi4+0xa0>
- 8000300: 40d4 lsrs r4, r2
- 8000302: 2300 movs r3, #0
- 8000304: e9c6 4300 strd r4, r3, [r6]
- 8000308: 4639 mov r1, r7
- 800030a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 800030e: 428b cmp r3, r1
- 8000310: d909 bls.n 8000326 <__udivmoddi4+0xbe>
- 8000312: 2e00 cmp r6, #0
- 8000314: f000 80eb beq.w 80004ee <__udivmoddi4+0x286>
- 8000318: 2700 movs r7, #0
- 800031a: e9c6 0100 strd r0, r1, [r6]
- 800031e: 4638 mov r0, r7
- 8000320: 4639 mov r1, r7
- 8000322: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 8000326: fab3 f783 clz r7, r3
- 800032a: 2f00 cmp r7, #0
- 800032c: d147 bne.n 80003be <__udivmoddi4+0x156>
- 800032e: 428b cmp r3, r1
- 8000330: d302 bcc.n 8000338 <__udivmoddi4+0xd0>
- 8000332: 4282 cmp r2, r0
- 8000334: f200 80fa bhi.w 800052c <__udivmoddi4+0x2c4>
- 8000338: 1a84 subs r4, r0, r2
- 800033a: eb61 0303 sbc.w r3, r1, r3
- 800033e: 2001 movs r0, #1
- 8000340: 4698 mov r8, r3
- 8000342: 2e00 cmp r6, #0
- 8000344: d0e0 beq.n 8000308 <__udivmoddi4+0xa0>
- 8000346: e9c6 4800 strd r4, r8, [r6]
- 800034a: e7dd b.n 8000308 <__udivmoddi4+0xa0>
- 800034c: b902 cbnz r2, 8000350 <__udivmoddi4+0xe8>
- 800034e: deff udf #255 ; 0xff
- 8000350: fab2 f282 clz r2, r2
- 8000354: 2a00 cmp r2, #0
- 8000356: f040 808f bne.w 8000478 <__udivmoddi4+0x210>
- 800035a: 1b49 subs r1, r1, r5
- 800035c: ea4f 4e15 mov.w lr, r5, lsr #16
- 8000360: fa1f f885 uxth.w r8, r5
- 8000364: 2701 movs r7, #1
- 8000366: fbb1 fcfe udiv ip, r1, lr
- 800036a: 0c23 lsrs r3, r4, #16
- 800036c: fb0e 111c mls r1, lr, ip, r1
- 8000370: ea43 4301 orr.w r3, r3, r1, lsl #16
- 8000374: fb08 f10c mul.w r1, r8, ip
- 8000378: 4299 cmp r1, r3
- 800037a: d907 bls.n 800038c <__udivmoddi4+0x124>
- 800037c: 18eb adds r3, r5, r3
- 800037e: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff
- 8000382: d202 bcs.n 800038a <__udivmoddi4+0x122>
- 8000384: 4299 cmp r1, r3
- 8000386: f200 80cd bhi.w 8000524 <__udivmoddi4+0x2bc>
- 800038a: 4684 mov ip, r0
- 800038c: 1a59 subs r1, r3, r1
- 800038e: b2a3 uxth r3, r4
- 8000390: fbb1 f0fe udiv r0, r1, lr
- 8000394: fb0e 1410 mls r4, lr, r0, r1
- 8000398: ea43 4404 orr.w r4, r3, r4, lsl #16
- 800039c: fb08 f800 mul.w r8, r8, r0
- 80003a0: 45a0 cmp r8, r4
- 80003a2: d907 bls.n 80003b4 <__udivmoddi4+0x14c>
- 80003a4: 192c adds r4, r5, r4
- 80003a6: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
- 80003aa: d202 bcs.n 80003b2 <__udivmoddi4+0x14a>
- 80003ac: 45a0 cmp r8, r4
- 80003ae: f200 80b6 bhi.w 800051e <__udivmoddi4+0x2b6>
- 80003b2: 4618 mov r0, r3
- 80003b4: eba4 0408 sub.w r4, r4, r8
- 80003b8: ea40 400c orr.w r0, r0, ip, lsl #16
- 80003bc: e79f b.n 80002fe <__udivmoddi4+0x96>
- 80003be: f1c7 0c20 rsb ip, r7, #32
- 80003c2: 40bb lsls r3, r7
- 80003c4: fa22 fe0c lsr.w lr, r2, ip
- 80003c8: ea4e 0e03 orr.w lr, lr, r3
- 80003cc: fa01 f407 lsl.w r4, r1, r7
- 80003d0: fa20 f50c lsr.w r5, r0, ip
- 80003d4: fa21 f30c lsr.w r3, r1, ip
- 80003d8: ea4f 481e mov.w r8, lr, lsr #16
- 80003dc: 4325 orrs r5, r4
- 80003de: fbb3 f9f8 udiv r9, r3, r8
- 80003e2: 0c2c lsrs r4, r5, #16
- 80003e4: fb08 3319 mls r3, r8, r9, r3
- 80003e8: fa1f fa8e uxth.w sl, lr
- 80003ec: ea44 4303 orr.w r3, r4, r3, lsl #16
- 80003f0: fb09 f40a mul.w r4, r9, sl
- 80003f4: 429c cmp r4, r3
- 80003f6: fa02 f207 lsl.w r2, r2, r7
- 80003fa: fa00 f107 lsl.w r1, r0, r7
- 80003fe: d90b bls.n 8000418 <__udivmoddi4+0x1b0>
- 8000400: eb1e 0303 adds.w r3, lr, r3
- 8000404: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff
- 8000408: f080 8087 bcs.w 800051a <__udivmoddi4+0x2b2>
- 800040c: 429c cmp r4, r3
- 800040e: f240 8084 bls.w 800051a <__udivmoddi4+0x2b2>
- 8000412: f1a9 0902 sub.w r9, r9, #2
- 8000416: 4473 add r3, lr
- 8000418: 1b1b subs r3, r3, r4
- 800041a: b2ad uxth r5, r5
- 800041c: fbb3 f0f8 udiv r0, r3, r8
- 8000420: fb08 3310 mls r3, r8, r0, r3
- 8000424: ea45 4403 orr.w r4, r5, r3, lsl #16
- 8000428: fb00 fa0a mul.w sl, r0, sl
- 800042c: 45a2 cmp sl, r4
- 800042e: d908 bls.n 8000442 <__udivmoddi4+0x1da>
- 8000430: eb1e 0404 adds.w r4, lr, r4
- 8000434: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
- 8000438: d26b bcs.n 8000512 <__udivmoddi4+0x2aa>
- 800043a: 45a2 cmp sl, r4
- 800043c: d969 bls.n 8000512 <__udivmoddi4+0x2aa>
- 800043e: 3802 subs r0, #2
- 8000440: 4474 add r4, lr
- 8000442: ea40 4009 orr.w r0, r0, r9, lsl #16
- 8000446: fba0 8902 umull r8, r9, r0, r2
- 800044a: eba4 040a sub.w r4, r4, sl
- 800044e: 454c cmp r4, r9
- 8000450: 46c2 mov sl, r8
- 8000452: 464b mov r3, r9
- 8000454: d354 bcc.n 8000500 <__udivmoddi4+0x298>
- 8000456: d051 beq.n 80004fc <__udivmoddi4+0x294>
- 8000458: 2e00 cmp r6, #0
- 800045a: d069 beq.n 8000530 <__udivmoddi4+0x2c8>
- 800045c: ebb1 050a subs.w r5, r1, sl
- 8000460: eb64 0403 sbc.w r4, r4, r3
- 8000464: fa04 fc0c lsl.w ip, r4, ip
- 8000468: 40fd lsrs r5, r7
- 800046a: 40fc lsrs r4, r7
- 800046c: ea4c 0505 orr.w r5, ip, r5
- 8000470: e9c6 5400 strd r5, r4, [r6]
- 8000474: 2700 movs r7, #0
- 8000476: e747 b.n 8000308 <__udivmoddi4+0xa0>
- 8000478: f1c2 0320 rsb r3, r2, #32
- 800047c: fa20 f703 lsr.w r7, r0, r3
- 8000480: 4095 lsls r5, r2
- 8000482: fa01 f002 lsl.w r0, r1, r2
- 8000486: fa21 f303 lsr.w r3, r1, r3
- 800048a: ea4f 4e15 mov.w lr, r5, lsr #16
- 800048e: 4338 orrs r0, r7
- 8000490: 0c01 lsrs r1, r0, #16
- 8000492: fbb3 f7fe udiv r7, r3, lr
- 8000496: fa1f f885 uxth.w r8, r5
- 800049a: fb0e 3317 mls r3, lr, r7, r3
- 800049e: ea41 4103 orr.w r1, r1, r3, lsl #16
- 80004a2: fb07 f308 mul.w r3, r7, r8
- 80004a6: 428b cmp r3, r1
- 80004a8: fa04 f402 lsl.w r4, r4, r2
- 80004ac: d907 bls.n 80004be <__udivmoddi4+0x256>
- 80004ae: 1869 adds r1, r5, r1
- 80004b0: f107 3cff add.w ip, r7, #4294967295 ; 0xffffffff
- 80004b4: d22f bcs.n 8000516 <__udivmoddi4+0x2ae>
- 80004b6: 428b cmp r3, r1
- 80004b8: d92d bls.n 8000516 <__udivmoddi4+0x2ae>
- 80004ba: 3f02 subs r7, #2
- 80004bc: 4429 add r1, r5
- 80004be: 1acb subs r3, r1, r3
- 80004c0: b281 uxth r1, r0
- 80004c2: fbb3 f0fe udiv r0, r3, lr
- 80004c6: fb0e 3310 mls r3, lr, r0, r3
- 80004ca: ea41 4103 orr.w r1, r1, r3, lsl #16
- 80004ce: fb00 f308 mul.w r3, r0, r8
- 80004d2: 428b cmp r3, r1
- 80004d4: d907 bls.n 80004e6 <__udivmoddi4+0x27e>
- 80004d6: 1869 adds r1, r5, r1
- 80004d8: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff
- 80004dc: d217 bcs.n 800050e <__udivmoddi4+0x2a6>
- 80004de: 428b cmp r3, r1
- 80004e0: d915 bls.n 800050e <__udivmoddi4+0x2a6>
- 80004e2: 3802 subs r0, #2
- 80004e4: 4429 add r1, r5
- 80004e6: 1ac9 subs r1, r1, r3
- 80004e8: ea40 4707 orr.w r7, r0, r7, lsl #16
- 80004ec: e73b b.n 8000366 <__udivmoddi4+0xfe>
- 80004ee: 4637 mov r7, r6
- 80004f0: 4630 mov r0, r6
- 80004f2: e709 b.n 8000308 <__udivmoddi4+0xa0>
- 80004f4: 4607 mov r7, r0
- 80004f6: e6e7 b.n 80002c8 <__udivmoddi4+0x60>
- 80004f8: 4618 mov r0, r3
- 80004fa: e6fb b.n 80002f4 <__udivmoddi4+0x8c>
- 80004fc: 4541 cmp r1, r8
- 80004fe: d2ab bcs.n 8000458 <__udivmoddi4+0x1f0>
- 8000500: ebb8 0a02 subs.w sl, r8, r2
- 8000504: eb69 020e sbc.w r2, r9, lr
- 8000508: 3801 subs r0, #1
- 800050a: 4613 mov r3, r2
- 800050c: e7a4 b.n 8000458 <__udivmoddi4+0x1f0>
- 800050e: 4660 mov r0, ip
- 8000510: e7e9 b.n 80004e6 <__udivmoddi4+0x27e>
- 8000512: 4618 mov r0, r3
- 8000514: e795 b.n 8000442 <__udivmoddi4+0x1da>
- 8000516: 4667 mov r7, ip
- 8000518: e7d1 b.n 80004be <__udivmoddi4+0x256>
- 800051a: 4681 mov r9, r0
- 800051c: e77c b.n 8000418 <__udivmoddi4+0x1b0>
- 800051e: 3802 subs r0, #2
- 8000520: 442c add r4, r5
- 8000522: e747 b.n 80003b4 <__udivmoddi4+0x14c>
- 8000524: f1ac 0c02 sub.w ip, ip, #2
- 8000528: 442b add r3, r5
- 800052a: e72f b.n 800038c <__udivmoddi4+0x124>
- 800052c: 4638 mov r0, r7
- 800052e: e708 b.n 8000342 <__udivmoddi4+0xda>
- 8000530: 4637 mov r7, r6
- 8000532: e6e9 b.n 8000308 <__udivmoddi4+0xa0>
-
-08000534 <__aeabi_idiv0>:
- 8000534: 4770 bx lr
- 8000536: bf00 nop
-
-08000538 <_ZN7Encoder8GetCountEv>:
-
- Encoder(TIM_HandleTypeDef *timer, float wheel_circ);
-
- void Setup();
-
- int GetCount() {
- 8000538: b480 push {r7}
- 800053a: b085 sub sp, #20
- 800053c: af00 add r7, sp, #0
- 800053e: 6078 str r0, [r7, #4]
- int count = ((int) __HAL_TIM_GET_COUNTER(this->timer_)
- 8000540: 687b ldr r3, [r7, #4]
- 8000542: 681b ldr r3, [r3, #0]
- 8000544: 681b ldr r3, [r3, #0]
- 8000546: 6a5a ldr r2, [r3, #36] ; 0x24
- - ((this->timer_->Init.Period) / 2));
- 8000548: 687b ldr r3, [r7, #4]
- 800054a: 681b ldr r3, [r3, #0]
- 800054c: 68db ldr r3, [r3, #12]
- 800054e: 085b lsrs r3, r3, #1
- 8000550: 1ad3 subs r3, r2, r3
- 8000552: 60fb str r3, [r7, #12]
- return count;
- 8000554: 68fb ldr r3, [r7, #12]
- }
- 8000556: 4618 mov r0, r3
- 8000558: 3714 adds r7, #20
- 800055a: 46bd mov sp, r7
- 800055c: f85d 7b04 ldr.w r7, [sp], #4
- 8000560: 4770 bx lr
-
-08000562 <_ZN7Encoder10ResetCountEv>:
-
- void ResetCount() {
- 8000562: b480 push {r7}
- 8000564: b083 sub sp, #12
- 8000566: af00 add r7, sp, #0
- 8000568: 6078 str r0, [r7, #4]
- //set counter to half its maximum value
- __HAL_TIM_SET_COUNTER(timer_, (timer_->Init.Period) / 2);
- 800056a: 687b ldr r3, [r7, #4]
- 800056c: 681b ldr r3, [r3, #0]
- 800056e: 68da ldr r2, [r3, #12]
- 8000570: 687b ldr r3, [r7, #4]
- 8000572: 681b ldr r3, [r3, #0]
- 8000574: 681b ldr r3, [r3, #0]
- 8000576: 0852 lsrs r2, r2, #1
- 8000578: 625a str r2, [r3, #36] ; 0x24
- }
- 800057a: bf00 nop
- 800057c: 370c adds r7, #12
- 800057e: 46bd mov sp, r7
- 8000580: f85d 7b04 ldr.w r7, [sp], #4
- 8000584: 4770 bx lr
-
-08000586 <_ZN7EncoderC1EP17TIM_HandleTypeDeff>:
-#include "encoder.h"
-
-Encoder::Encoder(TIM_HandleTypeDef *timer, float wheel_circ) {
- 8000586: b480 push {r7}
- 8000588: b085 sub sp, #20
- 800058a: af00 add r7, sp, #0
- 800058c: 60f8 str r0, [r7, #12]
- 800058e: 60b9 str r1, [r7, #8]
- 8000590: ed87 0a01 vstr s0, [r7, #4]
- timer_ = timer;
- 8000594: 68fb ldr r3, [r7, #12]
- 8000596: 68ba ldr r2, [r7, #8]
- 8000598: 601a str r2, [r3, #0]
- wheel_circumference_ = wheel_circ;
- 800059a: 68fb ldr r3, [r7, #12]
- 800059c: 687a ldr r2, [r7, #4]
- 800059e: 611a str r2, [r3, #16]
-}
- 80005a0: 68fb ldr r3, [r7, #12]
- 80005a2: 4618 mov r0, r3
- 80005a4: 3714 adds r7, #20
- 80005a6: 46bd mov sp, r7
- 80005a8: f85d 7b04 ldr.w r7, [sp], #4
- 80005ac: 4770 bx lr
-
-080005ae <_ZN7Encoder5SetupEv>:
-
-void Encoder::Setup() {
- 80005ae: b580 push {r7, lr}
- 80005b0: b082 sub sp, #8
- 80005b2: af00 add r7, sp, #0
- 80005b4: 6078 str r0, [r7, #4]
- HAL_TIM_Encoder_Start(timer_, TIM_CHANNEL_ALL);
- 80005b6: 687b ldr r3, [r7, #4]
- 80005b8: 681b ldr r3, [r3, #0]
- 80005ba: 213c movs r1, #60 ; 0x3c
- 80005bc: 4618 mov r0, r3
- 80005be: f003 f8e7 bl 8003790 <HAL_TIM_Encoder_Start>
- this->ResetCount();
- 80005c2: 6878 ldr r0, [r7, #4]
- 80005c4: f7ff ffcd bl 8000562 <_ZN7Encoder10ResetCountEv>
- this->previous_millis_ = 0;
- 80005c8: 687b ldr r3, [r7, #4]
- 80005ca: 2200 movs r2, #0
- 80005cc: 605a str r2, [r3, #4]
- this->current_millis_ = HAL_GetTick();
- 80005ce: f001 fbfb bl 8001dc8 <HAL_GetTick>
- 80005d2: 4602 mov r2, r0
- 80005d4: 687b ldr r3, [r7, #4]
- 80005d6: 609a str r2, [r3, #8]
-}
- 80005d8: bf00 nop
- 80005da: 3708 adds r7, #8
- 80005dc: 46bd mov sp, r7
- 80005de: bd80 pop {r7, pc}
-
-080005e0 <_ZN7Encoder12UpdateValuesEv>:
-
-void Encoder::UpdateValues() {
- 80005e0: b580 push {r7, lr}
- 80005e2: b082 sub sp, #8
- 80005e4: af00 add r7, sp, #0
- 80005e6: 6078 str r0, [r7, #4]
- this->previous_millis_ = this->current_millis_;
- 80005e8: 687b ldr r3, [r7, #4]
- 80005ea: 689a ldr r2, [r3, #8]
- 80005ec: 687b ldr r3, [r7, #4]
- 80005ee: 605a str r2, [r3, #4]
- this->current_millis_ = HAL_GetTick();
- 80005f0: f001 fbea bl 8001dc8 <HAL_GetTick>
- 80005f4: 4602 mov r2, r0
- 80005f6: 687b ldr r3, [r7, #4]
- 80005f8: 609a str r2, [r3, #8]
- this->ticks_ = this->GetCount();
- 80005fa: 6878 ldr r0, [r7, #4]
- 80005fc: f7ff ff9c bl 8000538 <_ZN7Encoder8GetCountEv>
- 8000600: 4602 mov r2, r0
- 8000602: 687b ldr r3, [r7, #4]
- 8000604: 60da str r2, [r3, #12]
- this->ResetCount();
- 8000606: 6878 ldr r0, [r7, #4]
- 8000608: f7ff ffab bl 8000562 <_ZN7Encoder10ResetCountEv>
-}
- 800060c: bf00 nop
- 800060e: 3708 adds r7, #8
- 8000610: 46bd mov sp, r7
- 8000612: bd80 pop {r7, pc}
-
-08000614 <_ZN7Encoder17GetLinearVelocityEv>:
- float meters = ((float) this->ticks_ * this->wheel_circumference_)
- / TICKS_PER_REVOLUTION;
- return meters;
-}
-
-float Encoder::GetLinearVelocity() {
- 8000614: b580 push {r7, lr}
- 8000616: b086 sub sp, #24
- 8000618: af00 add r7, sp, #0
- 800061a: 6078 str r0, [r7, #4]
- this->UpdateValues();
- 800061c: 6878 ldr r0, [r7, #4]
- 800061e: f7ff ffdf bl 80005e0 <_ZN7Encoder12UpdateValuesEv>
- float meters = ((float) this->ticks_ * this->wheel_circumference_)
- 8000622: 687b ldr r3, [r7, #4]
- 8000624: 68db ldr r3, [r3, #12]
- 8000626: ee07 3a90 vmov s15, r3
- 800062a: eeb8 7ae7 vcvt.f32.s32 s14, s15
- 800062e: 687b ldr r3, [r7, #4]
- 8000630: edd3 7a04 vldr s15, [r3, #16]
- 8000634: ee27 7a27 vmul.f32 s14, s14, s15
- 8000638: eddf 6a17 vldr s13, [pc, #92] ; 8000698 <_ZN7Encoder17GetLinearVelocityEv+0x84>
- 800063c: eec7 7a26 vdiv.f32 s15, s14, s13
- 8000640: edc7 7a05 vstr s15, [r7, #20]
- / TICKS_PER_REVOLUTION;
- float deltaTime = this->current_millis_ - this->previous_millis_;
- 8000644: 687b ldr r3, [r7, #4]
- 8000646: 689a ldr r2, [r3, #8]
- 8000648: 687b ldr r3, [r7, #4]
- 800064a: 685b ldr r3, [r3, #4]
- 800064c: 1ad3 subs r3, r2, r3
- 800064e: ee07 3a90 vmov s15, r3
- 8000652: eef8 7a67 vcvt.f32.u32 s15, s15
- 8000656: edc7 7a04 vstr s15, [r7, #16]
- if (deltaTime == 0)
- 800065a: edd7 7a04 vldr s15, [r7, #16]
- 800065e: eef5 7a40 vcmp.f32 s15, #0.0
- 8000662: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8000666: d102 bne.n 800066e <_ZN7Encoder17GetLinearVelocityEv+0x5a>
- return 0;
- 8000668: f04f 0300 mov.w r3, #0
- 800066c: e00c b.n 8000688 <_ZN7Encoder17GetLinearVelocityEv+0x74>
- float linear_velocity = (meters / (deltaTime / 1000));
- 800066e: edd7 7a04 vldr s15, [r7, #16]
- 8000672: eddf 6a0a vldr s13, [pc, #40] ; 800069c <_ZN7Encoder17GetLinearVelocityEv+0x88>
- 8000676: ee87 7aa6 vdiv.f32 s14, s15, s13
- 800067a: edd7 6a05 vldr s13, [r7, #20]
- 800067e: eec6 7a87 vdiv.f32 s15, s13, s14
- 8000682: edc7 7a03 vstr s15, [r7, #12]
- return linear_velocity;
- 8000686: 68fb ldr r3, [r7, #12]
- 8000688: ee07 3a90 vmov s15, r3
-}
- 800068c: eeb0 0a67 vmov.f32 s0, s15
- 8000690: 3718 adds r7, #24
- 8000692: 46bd mov sp, r7
- 8000694: bd80 pop {r7, pc}
- 8000696: bf00 nop
- 8000698: 48108800 .word 0x48108800
- 800069c: 447a0000 .word 0x447a0000
-
-080006a0 <_ZN8OdometryC1Ev>:
- float left_velocity_;
- float right_velocity_;
-
-
- public:
- Odometry() {
- 80006a0: b480 push {r7}
- 80006a2: b083 sub sp, #12
- 80006a4: af00 add r7, sp, #0
- 80006a6: 6078 str r0, [r7, #4]
- left_velocity_ = 0;
- 80006a8: 687b ldr r3, [r7, #4]
- 80006aa: f04f 0200 mov.w r2, #0
- 80006ae: 601a str r2, [r3, #0]
- right_velocity_ = 0;
- 80006b0: 687b ldr r3, [r7, #4]
- 80006b2: f04f 0200 mov.w r2, #0
- 80006b6: 605a str r2, [r3, #4]
- }
- 80006b8: 687b ldr r3, [r7, #4]
- 80006ba: 4618 mov r0, r3
- 80006bc: 370c adds r7, #12
- 80006be: 46bd mov sp, r7
- 80006c0: f85d 7b04 ldr.w r7, [sp], #4
- 80006c4: 4770 bx lr
- ...
-
-080006c8 <_ZN8Odometry12UpdateValuesEff>:
-
- void UpdateValues(float linear_vel, float angular_vel) {
- 80006c8: b480 push {r7}
- 80006ca: b085 sub sp, #20
- 80006cc: af00 add r7, sp, #0
- 80006ce: 60f8 str r0, [r7, #12]
- 80006d0: ed87 0a02 vstr s0, [r7, #8]
- 80006d4: edc7 0a01 vstr s1, [r7, #4]
- left_velocity_ = linear_vel - (BASELINE * angular_vel)/2;
- 80006d8: edd7 7a02 vldr s15, [r7, #8]
- 80006dc: eeb7 6ae7 vcvt.f64.f32 d6, s15
- 80006e0: edd7 7a01 vldr s15, [r7, #4]
- 80006e4: eeb7 7ae7 vcvt.f64.f32 d7, s15
- 80006e8: ed9f 5b11 vldr d5, [pc, #68] ; 8000730 <_ZN8Odometry12UpdateValuesEff+0x68>
- 80006ec: ee27 5b05 vmul.f64 d5, d7, d5
- 80006f0: eeb0 4b00 vmov.f64 d4, #0 ; 0x40000000 2.0
- 80006f4: ee85 7b04 vdiv.f64 d7, d5, d4
- 80006f8: ee36 7b47 vsub.f64 d7, d6, d7
- 80006fc: eef7 7bc7 vcvt.f32.f64 s15, d7
- 8000700: 68fb ldr r3, [r7, #12]
- 8000702: edc3 7a00 vstr s15, [r3]
- right_velocity_ = 2 * linear_vel - left_velocity_;
- 8000706: edd7 7a02 vldr s15, [r7, #8]
- 800070a: ee37 7aa7 vadd.f32 s14, s15, s15
- 800070e: 68fb ldr r3, [r7, #12]
- 8000710: edd3 7a00 vldr s15, [r3]
- 8000714: ee77 7a67 vsub.f32 s15, s14, s15
- 8000718: 68fb ldr r3, [r7, #12]
- 800071a: edc3 7a01 vstr s15, [r3, #4]
- }
- 800071e: bf00 nop
- 8000720: 3714 adds r7, #20
- 8000722: 46bd mov sp, r7
- 8000724: f85d 7b04 ldr.w r7, [sp], #4
- 8000728: 4770 bx lr
- 800072a: bf00 nop
- 800072c: f3af 8000 nop.w
- 8000730: 33333333 .word 0x33333333
- 8000734: 3fd33333 .word 0x3fd33333
-
-08000738 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>:
- GPIO_TypeDef *dir_gpio_port_;
- uint16_t dir_pin_;
- TIM_HandleTypeDef *pwm_timer_;
- uint32_t pwm_channel_;
-
- MotorController(GPIO_TypeDef *sleep_gpio_port, uint16_t sleep_pin,
- 8000738: b480 push {r7}
- 800073a: b085 sub sp, #20
- 800073c: af00 add r7, sp, #0
- 800073e: 60f8 str r0, [r7, #12]
- 8000740: 60b9 str r1, [r7, #8]
- 8000742: 603b str r3, [r7, #0]
- 8000744: 4613 mov r3, r2
- 8000746: 80fb strh r3, [r7, #6]
- GPIO_TypeDef *dir_gpio_port, uint16_t dir_pin,
- TIM_HandleTypeDef *pwm_timer, uint32_t pwm_channel) {
- this->sleep_gpio_port_ = sleep_gpio_port;
- 8000748: 68fb ldr r3, [r7, #12]
- 800074a: 68ba ldr r2, [r7, #8]
- 800074c: 601a str r2, [r3, #0]
- this->sleep_pin_ = sleep_pin;
- 800074e: 68fb ldr r3, [r7, #12]
- 8000750: 88fa ldrh r2, [r7, #6]
- 8000752: 809a strh r2, [r3, #4]
- this->dir_gpio_port_ = dir_gpio_port;
- 8000754: 68fb ldr r3, [r7, #12]
- 8000756: 683a ldr r2, [r7, #0]
- 8000758: 609a str r2, [r3, #8]
- this->dir_pin_ = dir_pin;
- 800075a: 68fb ldr r3, [r7, #12]
- 800075c: 8b3a ldrh r2, [r7, #24]
- 800075e: 819a strh r2, [r3, #12]
- this->pwm_timer_ = pwm_timer;
- 8000760: 68fb ldr r3, [r7, #12]
- 8000762: 69fa ldr r2, [r7, #28]
- 8000764: 611a str r2, [r3, #16]
- this->pwm_channel_ = pwm_channel;
- 8000766: 68fb ldr r3, [r7, #12]
- 8000768: 6a3a ldr r2, [r7, #32]
- 800076a: 615a str r2, [r3, #20]
- }
- 800076c: 68fb ldr r3, [r7, #12]
- 800076e: 4618 mov r0, r3
- 8000770: 3714 adds r7, #20
- 8000772: 46bd mov sp, r7
- 8000774: f85d 7b04 ldr.w r7, [sp], #4
- 8000778: 4770 bx lr
-
-0800077a <_ZN15MotorController5setupEv>:
-
- void setup() {
- 800077a: b580 push {r7, lr}
- 800077c: b082 sub sp, #8
- 800077e: af00 add r7, sp, #0
- 8000780: 6078 str r0, [r7, #4]
- HAL_TIM_PWM_Start(pwm_timer_, pwm_channel_);
- 8000782: 687b ldr r3, [r7, #4]
- 8000784: 691a ldr r2, [r3, #16]
- 8000786: 687b ldr r3, [r7, #4]
- 8000788: 695b ldr r3, [r3, #20]
- 800078a: 4619 mov r1, r3
- 800078c: 4610 mov r0, r2
- 800078e: f002 ff29 bl 80035e4 <HAL_TIM_PWM_Start>
- }
- 8000792: bf00 nop
- 8000794: 3708 adds r7, #8
- 8000796: 46bd mov sp, r7
- 8000798: bd80 pop {r7, pc}
- ...
-
-0800079c <_ZN15MotorController9set_speedEi>:
-
- void set_speed(int duty_cycle) {
- 800079c: b580 push {r7, lr}
- 800079e: b082 sub sp, #8
- 80007a0: af00 add r7, sp, #0
- 80007a2: 6078 str r0, [r7, #4]
- 80007a4: 6039 str r1, [r7, #0]
- if (duty_cycle >= 0) {
- 80007a6: 683b ldr r3, [r7, #0]
- 80007a8: 2b00 cmp r3, #0
- 80007aa: f2c0 8083 blt.w 80008b4 <_ZN15MotorController9set_speedEi+0x118>
- //set direction to forward
- HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_SET);
- 80007ae: 687b ldr r3, [r7, #4]
- 80007b0: 6898 ldr r0, [r3, #8]
- 80007b2: 687b ldr r3, [r7, #4]
- 80007b4: 899b ldrh r3, [r3, #12]
- 80007b6: 2201 movs r2, #1
- 80007b8: 4619 mov r1, r3
- 80007ba: f001 fdef bl 800239c <HAL_GPIO_WritePin>
-
- //check if duty_cycle exceeds maximum
- if (duty_cycle > MAX_DUTY_CYCLE)
- 80007be: 683b ldr r3, [r7, #0]
- 80007c0: f240 3216 movw r2, #790 ; 0x316
- 80007c4: 4293 cmp r3, r2
- 80007c6: dd3d ble.n 8000844 <_ZN15MotorController9set_speedEi+0xa8>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, MAX_DUTY_CYCLE);
- 80007c8: 687b ldr r3, [r7, #4]
- 80007ca: 695b ldr r3, [r3, #20]
- 80007cc: 2b00 cmp r3, #0
- 80007ce: d106 bne.n 80007de <_ZN15MotorController9set_speedEi+0x42>
- 80007d0: 687b ldr r3, [r7, #4]
- 80007d2: 691b ldr r3, [r3, #16]
- 80007d4: 681b ldr r3, [r3, #0]
- 80007d6: f240 3216 movw r2, #790 ; 0x316
- 80007da: 635a str r2, [r3, #52] ; 0x34
- 80007dc: e0f5 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 80007de: 687b ldr r3, [r7, #4]
- 80007e0: 695b ldr r3, [r3, #20]
- 80007e2: 2b04 cmp r3, #4
- 80007e4: d106 bne.n 80007f4 <_ZN15MotorController9set_speedEi+0x58>
- 80007e6: 687b ldr r3, [r7, #4]
- 80007e8: 691b ldr r3, [r3, #16]
- 80007ea: 681b ldr r3, [r3, #0]
- 80007ec: f240 3216 movw r2, #790 ; 0x316
- 80007f0: 639a str r2, [r3, #56] ; 0x38
- 80007f2: e0ea b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 80007f4: 687b ldr r3, [r7, #4]
- 80007f6: 695b ldr r3, [r3, #20]
- 80007f8: 2b08 cmp r3, #8
- 80007fa: d106 bne.n 800080a <_ZN15MotorController9set_speedEi+0x6e>
- 80007fc: 687b ldr r3, [r7, #4]
- 80007fe: 691b ldr r3, [r3, #16]
- 8000800: 681b ldr r3, [r3, #0]
- 8000802: f240 3216 movw r2, #790 ; 0x316
- 8000806: 63da str r2, [r3, #60] ; 0x3c
- 8000808: e0df b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 800080a: 687b ldr r3, [r7, #4]
- 800080c: 695b ldr r3, [r3, #20]
- 800080e: 2b0c cmp r3, #12
- 8000810: d106 bne.n 8000820 <_ZN15MotorController9set_speedEi+0x84>
- 8000812: 687b ldr r3, [r7, #4]
- 8000814: 691b ldr r3, [r3, #16]
- 8000816: 681b ldr r3, [r3, #0]
- 8000818: f240 3216 movw r2, #790 ; 0x316
- 800081c: 641a str r2, [r3, #64] ; 0x40
- 800081e: e0d4 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 8000820: 687b ldr r3, [r7, #4]
- 8000822: 695b ldr r3, [r3, #20]
- 8000824: 2b10 cmp r3, #16
- 8000826: d106 bne.n 8000836 <_ZN15MotorController9set_speedEi+0x9a>
- 8000828: 687b ldr r3, [r7, #4]
- 800082a: 691b ldr r3, [r3, #16]
- 800082c: 681b ldr r3, [r3, #0]
- 800082e: f240 3216 movw r2, #790 ; 0x316
- 8000832: 659a str r2, [r3, #88] ; 0x58
- 8000834: e0c9 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 8000836: 687b ldr r3, [r7, #4]
- 8000838: 691b ldr r3, [r3, #16]
- 800083a: 681b ldr r3, [r3, #0]
- 800083c: f240 3216 movw r2, #790 ; 0x316
- 8000840: 65da str r2, [r3, #92] ; 0x5c
- 8000842: e0c2 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- else
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle);
- 8000844: 687b ldr r3, [r7, #4]
- 8000846: 695b ldr r3, [r3, #20]
- 8000848: 2b00 cmp r3, #0
- 800084a: d105 bne.n 8000858 <_ZN15MotorController9set_speedEi+0xbc>
- 800084c: 683a ldr r2, [r7, #0]
- 800084e: 687b ldr r3, [r7, #4]
- 8000850: 691b ldr r3, [r3, #16]
- 8000852: 681b ldr r3, [r3, #0]
- 8000854: 635a str r2, [r3, #52] ; 0x34
- 8000856: e0b8 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 8000858: 687b ldr r3, [r7, #4]
- 800085a: 695b ldr r3, [r3, #20]
- 800085c: 2b04 cmp r3, #4
- 800085e: d105 bne.n 800086c <_ZN15MotorController9set_speedEi+0xd0>
- 8000860: 683a ldr r2, [r7, #0]
- 8000862: 687b ldr r3, [r7, #4]
- 8000864: 691b ldr r3, [r3, #16]
- 8000866: 681b ldr r3, [r3, #0]
- 8000868: 639a str r2, [r3, #56] ; 0x38
- 800086a: e0ae b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 800086c: 687b ldr r3, [r7, #4]
- 800086e: 695b ldr r3, [r3, #20]
- 8000870: 2b08 cmp r3, #8
- 8000872: d105 bne.n 8000880 <_ZN15MotorController9set_speedEi+0xe4>
- 8000874: 683a ldr r2, [r7, #0]
- 8000876: 687b ldr r3, [r7, #4]
- 8000878: 691b ldr r3, [r3, #16]
- 800087a: 681b ldr r3, [r3, #0]
- 800087c: 63da str r2, [r3, #60] ; 0x3c
- 800087e: e0a4 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 8000880: 687b ldr r3, [r7, #4]
- 8000882: 695b ldr r3, [r3, #20]
- 8000884: 2b0c cmp r3, #12
- 8000886: d105 bne.n 8000894 <_ZN15MotorController9set_speedEi+0xf8>
- 8000888: 683a ldr r2, [r7, #0]
- 800088a: 687b ldr r3, [r7, #4]
- 800088c: 691b ldr r3, [r3, #16]
- 800088e: 681b ldr r3, [r3, #0]
- 8000890: 641a str r2, [r3, #64] ; 0x40
- 8000892: e09a b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 8000894: 687b ldr r3, [r7, #4]
- 8000896: 695b ldr r3, [r3, #20]
- 8000898: 2b10 cmp r3, #16
- 800089a: d105 bne.n 80008a8 <_ZN15MotorController9set_speedEi+0x10c>
- 800089c: 683a ldr r2, [r7, #0]
- 800089e: 687b ldr r3, [r7, #4]
- 80008a0: 691b ldr r3, [r3, #16]
- 80008a2: 681b ldr r3, [r3, #0]
- 80008a4: 659a str r2, [r3, #88] ; 0x58
- 80008a6: e090 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 80008a8: 683a ldr r2, [r7, #0]
- 80008aa: 687b ldr r3, [r7, #4]
- 80008ac: 691b ldr r3, [r3, #16]
- 80008ae: 681b ldr r3, [r3, #0]
- 80008b0: 65da str r2, [r3, #92] ; 0x5c
- 80008b2: e08a b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
-
- } else if (duty_cycle < 0){
- 80008b4: 683b ldr r3, [r7, #0]
- 80008b6: 2b00 cmp r3, #0
- 80008b8: f280 8087 bge.w 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- //set direction to backwards
- HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_RESET);
- 80008bc: 687b ldr r3, [r7, #4]
- 80008be: 6898 ldr r0, [r3, #8]
- 80008c0: 687b ldr r3, [r7, #4]
- 80008c2: 899b ldrh r3, [r3, #12]
- 80008c4: 2200 movs r2, #0
- 80008c6: 4619 mov r1, r3
- 80008c8: f001 fd68 bl 800239c <HAL_GPIO_WritePin>
-
- //check if duty_cycle is lower than minimum
- if (duty_cycle < -MAX_DUTY_CYCLE)
- 80008cc: 683b ldr r3, [r7, #0]
- 80008ce: 4a45 ldr r2, [pc, #276] ; (80009e4 <_ZN15MotorController9set_speedEi+0x248>)
- 80008d0: 4293 cmp r3, r2
- 80008d2: da3d bge.n 8000950 <_ZN15MotorController9set_speedEi+0x1b4>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, MAX_DUTY_CYCLE);
- 80008d4: 687b ldr r3, [r7, #4]
- 80008d6: 695b ldr r3, [r3, #20]
- 80008d8: 2b00 cmp r3, #0
- 80008da: d106 bne.n 80008ea <_ZN15MotorController9set_speedEi+0x14e>
- 80008dc: 687b ldr r3, [r7, #4]
- 80008de: 691b ldr r3, [r3, #16]
- 80008e0: 681b ldr r3, [r3, #0]
- 80008e2: f240 3216 movw r2, #790 ; 0x316
- 80008e6: 635a str r2, [r3, #52] ; 0x34
- 80008e8: e06f b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 80008ea: 687b ldr r3, [r7, #4]
- 80008ec: 695b ldr r3, [r3, #20]
- 80008ee: 2b04 cmp r3, #4
- 80008f0: d106 bne.n 8000900 <_ZN15MotorController9set_speedEi+0x164>
- 80008f2: 687b ldr r3, [r7, #4]
- 80008f4: 691b ldr r3, [r3, #16]
- 80008f6: 681b ldr r3, [r3, #0]
- 80008f8: f240 3216 movw r2, #790 ; 0x316
- 80008fc: 639a str r2, [r3, #56] ; 0x38
- 80008fe: e064 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 8000900: 687b ldr r3, [r7, #4]
- 8000902: 695b ldr r3, [r3, #20]
- 8000904: 2b08 cmp r3, #8
- 8000906: d106 bne.n 8000916 <_ZN15MotorController9set_speedEi+0x17a>
- 8000908: 687b ldr r3, [r7, #4]
- 800090a: 691b ldr r3, [r3, #16]
- 800090c: 681b ldr r3, [r3, #0]
- 800090e: f240 3216 movw r2, #790 ; 0x316
- 8000912: 63da str r2, [r3, #60] ; 0x3c
- 8000914: e059 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 8000916: 687b ldr r3, [r7, #4]
- 8000918: 695b ldr r3, [r3, #20]
- 800091a: 2b0c cmp r3, #12
- 800091c: d106 bne.n 800092c <_ZN15MotorController9set_speedEi+0x190>
- 800091e: 687b ldr r3, [r7, #4]
- 8000920: 691b ldr r3, [r3, #16]
- 8000922: 681b ldr r3, [r3, #0]
- 8000924: f240 3216 movw r2, #790 ; 0x316
- 8000928: 641a str r2, [r3, #64] ; 0x40
- 800092a: e04e b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 800092c: 687b ldr r3, [r7, #4]
- 800092e: 695b ldr r3, [r3, #20]
- 8000930: 2b10 cmp r3, #16
- 8000932: d106 bne.n 8000942 <_ZN15MotorController9set_speedEi+0x1a6>
- 8000934: 687b ldr r3, [r7, #4]
- 8000936: 691b ldr r3, [r3, #16]
- 8000938: 681b ldr r3, [r3, #0]
- 800093a: f240 3216 movw r2, #790 ; 0x316
- 800093e: 659a str r2, [r3, #88] ; 0x58
- 8000940: e043 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 8000942: 687b ldr r3, [r7, #4]
- 8000944: 691b ldr r3, [r3, #16]
- 8000946: 681b ldr r3, [r3, #0]
- 8000948: f240 3216 movw r2, #790 ; 0x316
- 800094c: 65da str r2, [r3, #92] ; 0x5c
- 800094e: e03c b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- else
- //invert sign to make duty_cycle positive
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle);
- 8000950: 687b ldr r3, [r7, #4]
- 8000952: 695b ldr r3, [r3, #20]
- 8000954: 2b00 cmp r3, #0
- 8000956: d106 bne.n 8000966 <_ZN15MotorController9set_speedEi+0x1ca>
- 8000958: 683b ldr r3, [r7, #0]
- 800095a: 425a negs r2, r3
- 800095c: 687b ldr r3, [r7, #4]
- 800095e: 691b ldr r3, [r3, #16]
- 8000960: 681b ldr r3, [r3, #0]
- 8000962: 635a str r2, [r3, #52] ; 0x34
- 8000964: e031 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 8000966: 687b ldr r3, [r7, #4]
- 8000968: 695b ldr r3, [r3, #20]
- 800096a: 2b04 cmp r3, #4
- 800096c: d106 bne.n 800097c <_ZN15MotorController9set_speedEi+0x1e0>
- 800096e: 683b ldr r3, [r7, #0]
- 8000970: 425a negs r2, r3
- 8000972: 687b ldr r3, [r7, #4]
- 8000974: 691b ldr r3, [r3, #16]
- 8000976: 681b ldr r3, [r3, #0]
- 8000978: 639a str r2, [r3, #56] ; 0x38
- 800097a: e026 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 800097c: 687b ldr r3, [r7, #4]
- 800097e: 695b ldr r3, [r3, #20]
- 8000980: 2b08 cmp r3, #8
- 8000982: d106 bne.n 8000992 <_ZN15MotorController9set_speedEi+0x1f6>
- 8000984: 683b ldr r3, [r7, #0]
- 8000986: 425a negs r2, r3
- 8000988: 687b ldr r3, [r7, #4]
- 800098a: 691b ldr r3, [r3, #16]
- 800098c: 681b ldr r3, [r3, #0]
- 800098e: 63da str r2, [r3, #60] ; 0x3c
- 8000990: e01b b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 8000992: 687b ldr r3, [r7, #4]
- 8000994: 695b ldr r3, [r3, #20]
- 8000996: 2b0c cmp r3, #12
- 8000998: d106 bne.n 80009a8 <_ZN15MotorController9set_speedEi+0x20c>
- 800099a: 683b ldr r3, [r7, #0]
- 800099c: 425a negs r2, r3
- 800099e: 687b ldr r3, [r7, #4]
- 80009a0: 691b ldr r3, [r3, #16]
- 80009a2: 681b ldr r3, [r3, #0]
- 80009a4: 641a str r2, [r3, #64] ; 0x40
- 80009a6: e010 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 80009a8: 687b ldr r3, [r7, #4]
- 80009aa: 695b ldr r3, [r3, #20]
- 80009ac: 2b10 cmp r3, #16
- 80009ae: d106 bne.n 80009be <_ZN15MotorController9set_speedEi+0x222>
- 80009b0: 683b ldr r3, [r7, #0]
- 80009b2: 425a negs r2, r3
- 80009b4: 687b ldr r3, [r7, #4]
- 80009b6: 691b ldr r3, [r3, #16]
- 80009b8: 681b ldr r3, [r3, #0]
- 80009ba: 659a str r2, [r3, #88] ; 0x58
- 80009bc: e005 b.n 80009ca <_ZN15MotorController9set_speedEi+0x22e>
- 80009be: 683b ldr r3, [r7, #0]
- 80009c0: 425a negs r2, r3
- 80009c2: 687b ldr r3, [r7, #4]
- 80009c4: 691b ldr r3, [r3, #16]
- 80009c6: 681b ldr r3, [r3, #0]
- 80009c8: 65da str r2, [r3, #92] ; 0x5c
- }
-
- HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET);
- 80009ca: 687b ldr r3, [r7, #4]
- 80009cc: 6818 ldr r0, [r3, #0]
- 80009ce: 687b ldr r3, [r7, #4]
- 80009d0: 889b ldrh r3, [r3, #4]
- 80009d2: 2201 movs r2, #1
- 80009d4: 4619 mov r1, r3
- 80009d6: f001 fce1 bl 800239c <HAL_GPIO_WritePin>
-
- }
- 80009da: bf00 nop
- 80009dc: 3708 adds r7, #8
- 80009de: 46bd mov sp, r7
- 80009e0: bd80 pop {r7, pc}
- 80009e2: bf00 nop
- 80009e4: fffffcea .word 0xfffffcea
-
-080009e8 <_ZN15MotorController5coastEv>:
- void brake() {
- HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET);
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 0);
- }
-
- void coast() {
- 80009e8: b580 push {r7, lr}
- 80009ea: b082 sub sp, #8
- 80009ec: af00 add r7, sp, #0
- 80009ee: 6078 str r0, [r7, #4]
- HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_RESET);
- 80009f0: 687b ldr r3, [r7, #4]
- 80009f2: 6818 ldr r0, [r3, #0]
- 80009f4: 687b ldr r3, [r7, #4]
- 80009f6: 889b ldrh r3, [r3, #4]
- 80009f8: 2200 movs r2, #0
- 80009fa: 4619 mov r1, r3
- 80009fc: f001 fcce bl 800239c <HAL_GPIO_WritePin>
- }
- 8000a00: bf00 nop
- 8000a02: 3708 adds r7, #8
- 8000a04: 46bd mov sp, r7
- 8000a06: bd80 pop {r7, pc}
-
-08000a08 <_ZN3PidC1Efff>:
- float previous_error_;
-
- int min_;
- int max_;
-
- Pid(float kp, float ki, float kd) {
- 8000a08: b480 push {r7}
- 8000a0a: b085 sub sp, #20
- 8000a0c: af00 add r7, sp, #0
- 8000a0e: 60f8 str r0, [r7, #12]
- 8000a10: ed87 0a02 vstr s0, [r7, #8]
- 8000a14: edc7 0a01 vstr s1, [r7, #4]
- 8000a18: ed87 1a00 vstr s2, [r7]
- this->kp_ = kp;
- 8000a1c: 68fb ldr r3, [r7, #12]
- 8000a1e: 68ba ldr r2, [r7, #8]
- 8000a20: 601a str r2, [r3, #0]
- this->ki_ = ki;
- 8000a22: 68fb ldr r3, [r7, #12]
- 8000a24: 687a ldr r2, [r7, #4]
- 8000a26: 605a str r2, [r3, #4]
- this->kd_ = kd;
- 8000a28: 68fb ldr r3, [r7, #12]
- 8000a2a: 683a ldr r2, [r7, #0]
- 8000a2c: 609a str r2, [r3, #8]
-
- this->error_ = 0;
- 8000a2e: 68fb ldr r3, [r7, #12]
- 8000a30: f04f 0200 mov.w r2, #0
- 8000a34: 60da str r2, [r3, #12]
- this->setpoint_ = 0;
- 8000a36: 68fb ldr r3, [r7, #12]
- 8000a38: f04f 0200 mov.w r2, #0
- 8000a3c: 611a str r2, [r3, #16]
-
- this->previous_error_ = 0;
- 8000a3e: 68fb ldr r3, [r7, #12]
- 8000a40: f04f 0200 mov.w r2, #0
- 8000a44: 619a str r2, [r3, #24]
- this->error_sum_ = 0;
- 8000a46: 68fb ldr r3, [r7, #12]
- 8000a48: f04f 0200 mov.w r2, #0
- 8000a4c: 615a str r2, [r3, #20]
-
- this->min_ = -MAX_DUTY_CYCLE;
- 8000a4e: 68fb ldr r3, [r7, #12]
- 8000a50: 4a06 ldr r2, [pc, #24] ; (8000a6c <_ZN3PidC1Efff+0x64>)
- 8000a52: 61da str r2, [r3, #28]
- this->max_ = MAX_DUTY_CYCLE;
- 8000a54: 68fb ldr r3, [r7, #12]
- 8000a56: f240 3216 movw r2, #790 ; 0x316
- 8000a5a: 621a str r2, [r3, #32]
-
- }
- 8000a5c: 68fb ldr r3, [r7, #12]
- 8000a5e: 4618 mov r0, r3
- 8000a60: 3714 adds r7, #20
- 8000a62: 46bd mov sp, r7
- 8000a64: f85d 7b04 ldr.w r7, [sp], #4
- 8000a68: 4770 bx lr
- 8000a6a: bf00 nop
- 8000a6c: fffffcea .word 0xfffffcea
-
-08000a70 <_ZN3Pid6configEfff>:
-
- void config(float kp, float ki, float kd) {
- 8000a70: b480 push {r7}
- 8000a72: b085 sub sp, #20
- 8000a74: af00 add r7, sp, #0
- 8000a76: 60f8 str r0, [r7, #12]
- 8000a78: ed87 0a02 vstr s0, [r7, #8]
- 8000a7c: edc7 0a01 vstr s1, [r7, #4]
- 8000a80: ed87 1a00 vstr s2, [r7]
- this->kp_ = kp;
- 8000a84: 68fb ldr r3, [r7, #12]
- 8000a86: 68ba ldr r2, [r7, #8]
- 8000a88: 601a str r2, [r3, #0]
- this->ki_ = ki;
- 8000a8a: 68fb ldr r3, [r7, #12]
- 8000a8c: 687a ldr r2, [r7, #4]
- 8000a8e: 605a str r2, [r3, #4]
- this->kd_ = kd;
- 8000a90: 68fb ldr r3, [r7, #12]
- 8000a92: 683a ldr r2, [r7, #0]
- 8000a94: 609a str r2, [r3, #8]
-
- this->error_ = 0;
- 8000a96: 68fb ldr r3, [r7, #12]
- 8000a98: f04f 0200 mov.w r2, #0
- 8000a9c: 60da str r2, [r3, #12]
- this->setpoint_ = 0;
- 8000a9e: 68fb ldr r3, [r7, #12]
- 8000aa0: f04f 0200 mov.w r2, #0
- 8000aa4: 611a str r2, [r3, #16]
-
- this->previous_error_ = 0;
- 8000aa6: 68fb ldr r3, [r7, #12]
- 8000aa8: f04f 0200 mov.w r2, #0
- 8000aac: 619a str r2, [r3, #24]
- this->error_sum_ = 0;
- 8000aae: 68fb ldr r3, [r7, #12]
- 8000ab0: f04f 0200 mov.w r2, #0
- 8000ab4: 615a str r2, [r3, #20]
-
- }
- 8000ab6: bf00 nop
- 8000ab8: 3714 adds r7, #20
- 8000aba: 46bd mov sp, r7
- 8000abc: f85d 7b04 ldr.w r7, [sp], #4
- 8000ac0: 4770 bx lr
-
-08000ac2 <_ZN3Pid3setEf>:
-
- void set(float setpoint) {
- 8000ac2: b480 push {r7}
- 8000ac4: b083 sub sp, #12
- 8000ac6: af00 add r7, sp, #0
- 8000ac8: 6078 str r0, [r7, #4]
- 8000aca: ed87 0a00 vstr s0, [r7]
- this->setpoint_ = setpoint;
- 8000ace: 687b ldr r3, [r7, #4]
- 8000ad0: 683a ldr r2, [r7, #0]
- 8000ad2: 611a str r2, [r3, #16]
- }
- 8000ad4: bf00 nop
- 8000ad6: 370c adds r7, #12
- 8000ad8: 46bd mov sp, r7
- 8000ada: f85d 7b04 ldr.w r7, [sp], #4
- 8000ade: 4770 bx lr
-
-08000ae0 <_ZN3Pid6updateEf>:
-
- int update(float measure) {
- 8000ae0: b480 push {r7}
- 8000ae2: b085 sub sp, #20
- 8000ae4: af00 add r7, sp, #0
- 8000ae6: 6078 str r0, [r7, #4]
- 8000ae8: ed87 0a00 vstr s0, [r7]
-
- this->error_ = this->setpoint_ - measure;
- 8000aec: 687b ldr r3, [r7, #4]
- 8000aee: ed93 7a04 vldr s14, [r3, #16]
- 8000af2: edd7 7a00 vldr s15, [r7]
- 8000af6: ee77 7a67 vsub.f32 s15, s14, s15
- 8000afa: 687b ldr r3, [r7, #4]
- 8000afc: edc3 7a03 vstr s15, [r3, #12]
-
- //proportional term
- float output = this->error_ * this->kp_;
- 8000b00: 687b ldr r3, [r7, #4]
- 8000b02: ed93 7a03 vldr s14, [r3, #12]
- 8000b06: 687b ldr r3, [r7, #4]
- 8000b08: edd3 7a00 vldr s15, [r3]
- 8000b0c: ee67 7a27 vmul.f32 s15, s14, s15
- 8000b10: edc7 7a03 vstr s15, [r7, #12]
-
- //integral term without windup
- error_sum_ += this->error_;
- 8000b14: 687b ldr r3, [r7, #4]
- 8000b16: ed93 7a05 vldr s14, [r3, #20]
- 8000b1a: 687b ldr r3, [r7, #4]
- 8000b1c: edd3 7a03 vldr s15, [r3, #12]
- 8000b20: ee77 7a27 vadd.f32 s15, s14, s15
- 8000b24: 687b ldr r3, [r7, #4]
- 8000b26: edc3 7a05 vstr s15, [r3, #20]
- output += error_sum_ * this->ki_;
- 8000b2a: 687b ldr r3, [r7, #4]
- 8000b2c: ed93 7a05 vldr s14, [r3, #20]
- 8000b30: 687b ldr r3, [r7, #4]
- 8000b32: edd3 7a01 vldr s15, [r3, #4]
- 8000b36: ee67 7a27 vmul.f32 s15, s14, s15
- 8000b3a: ed97 7a03 vldr s14, [r7, #12]
- 8000b3e: ee77 7a27 vadd.f32 s15, s14, s15
- 8000b42: edc7 7a03 vstr s15, [r7, #12]
-
- //derivative term
- output += (this->error_ - this->previous_error_) * kd_;
- 8000b46: 687b ldr r3, [r7, #4]
- 8000b48: ed93 7a03 vldr s14, [r3, #12]
- 8000b4c: 687b ldr r3, [r7, #4]
- 8000b4e: edd3 7a06 vldr s15, [r3, #24]
- 8000b52: ee37 7a67 vsub.f32 s14, s14, s15
- 8000b56: 687b ldr r3, [r7, #4]
- 8000b58: edd3 7a02 vldr s15, [r3, #8]
- 8000b5c: ee67 7a27 vmul.f32 s15, s14, s15
- 8000b60: ed97 7a03 vldr s14, [r7, #12]
- 8000b64: ee77 7a27 vadd.f32 s15, s14, s15
- 8000b68: edc7 7a03 vstr s15, [r7, #12]
- this->previous_error_ = this->error_;
- 8000b6c: 687b ldr r3, [r7, #4]
- 8000b6e: 68da ldr r2, [r3, #12]
- 8000b70: 687b ldr r3, [r7, #4]
- 8000b72: 619a str r2, [r3, #24]
-
- int integer_output = static_cast<int> (output);
- 8000b74: edd7 7a03 vldr s15, [r7, #12]
- 8000b78: eefd 7ae7 vcvt.s32.f32 s15, s15
- 8000b7c: ee17 3a90 vmov r3, s15
- 8000b80: 60bb str r3, [r7, #8]
-// if(integer_output > this->max_)
-// integer_output = this->max_;
-// else if (integer_output < this->min_)
-// integer_output = this->min_;
-
- return integer_output;
- 8000b82: 68bb ldr r3, [r7, #8]
-
- }
- 8000b84: 4618 mov r0, r3
- 8000b86: 3714 adds r7, #20
- 8000b88: 46bd mov sp, r7
- 8000b8a: f85d 7b04 ldr.w r7, [sp], #4
- 8000b8e: 4770 bx lr
-
-08000b90 <main>:
-/**
- * @brief The application entry point.
- * @retval int
- */
-int main(void)
-{
- 8000b90: b580 push {r7, lr}
- 8000b92: af00 add r7, sp, #0
-
-
- /* MCU Configuration--------------------------------------------------------*/
-
- /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
- HAL_Init();
- 8000b94: f001 f8c7 bl 8001d26 <HAL_Init>
- /* USER CODE BEGIN Init */
-
- /* USER CODE END Init */
-
- /* Configure the system clock */
- SystemClock_Config();
- 8000b98: f000 f842 bl 8000c20 <_Z18SystemClock_Configv>
- /* USER CODE BEGIN SysInit */
-
- /* USER CODE END SysInit */
-
- /* Initialize all configured peripherals */
- MX_GPIO_Init();
- 8000b9c: f000 fb18 bl 80011d0 <_ZL12MX_GPIO_Initv>
- MX_TIM2_Init();
- 8000ba0: f000 f8e4 bl 8000d6c <_ZL12MX_TIM2_Initv>
- MX_TIM3_Init();
- 8000ba4: f000 f940 bl 8000e28 <_ZL12MX_TIM3_Initv>
- MX_TIM4_Init();
- 8000ba8: f000 f99c bl 8000ee4 <_ZL12MX_TIM4_Initv>
- MX_TIM5_Init();
- 8000bac: f000 fa3a bl 8001024 <_ZL12MX_TIM5_Initv>
- MX_USART6_UART_Init();
- 8000bb0: f000 fada bl 8001168 <_ZL19MX_USART6_UART_Initv>
- MX_TIM6_Init();
- 8000bb4: f000 fa96 bl 80010e4 <_ZL12MX_TIM6_Initv>
-
- /* Initialize interrupts */
- MX_NVIC_Init();
- 8000bb8: f000 f8bc bl 8000d34 <_ZL12MX_NVIC_Initv>
- /* USER CODE BEGIN 2 */
-
- left_encoder.Setup();
- 8000bbc: 480f ldr r0, [pc, #60] ; (8000bfc <main+0x6c>)
- 8000bbe: f7ff fcf6 bl 80005ae <_ZN7Encoder5SetupEv>
- right_encoder.Setup();
- 8000bc2: 480f ldr r0, [pc, #60] ; (8000c00 <main+0x70>)
- 8000bc4: f7ff fcf3 bl 80005ae <_ZN7Encoder5SetupEv>
-
- left_motor.setup();
- 8000bc8: 480e ldr r0, [pc, #56] ; (8000c04 <main+0x74>)
- 8000bca: f7ff fdd6 bl 800077a <_ZN15MotorController5setupEv>
- right_motor.setup();
- 8000bce: 480e ldr r0, [pc, #56] ; (8000c08 <main+0x78>)
- 8000bd0: f7ff fdd3 bl 800077a <_ZN15MotorController5setupEv>
-
- left_motor.coast();
- 8000bd4: 480b ldr r0, [pc, #44] ; (8000c04 <main+0x74>)
- 8000bd6: f7ff ff07 bl 80009e8 <_ZN15MotorController5coastEv>
- right_motor.coast();
- 8000bda: 480b ldr r0, [pc, #44] ; (8000c08 <main+0x78>)
- 8000bdc: f7ff ff04 bl 80009e8 <_ZN15MotorController5coastEv>
-
- tx_buffer = (uint8_t*) &output_msg;
- 8000be0: 4b0a ldr r3, [pc, #40] ; (8000c0c <main+0x7c>)
- 8000be2: 4a0b ldr r2, [pc, #44] ; (8000c10 <main+0x80>)
- 8000be4: 601a str r2, [r3, #0]
- rx_buffer = (uint8_t*) &input_msg;
- 8000be6: 4b0b ldr r3, [pc, #44] ; (8000c14 <main+0x84>)
- 8000be8: 4a0b ldr r2, [pc, #44] ; (8000c18 <main+0x88>)
- 8000bea: 601a str r2, [r3, #0]
-
- //Enables UART RX interrupt
- HAL_UART_Receive_IT(&huart6, rx_buffer, 28);
- 8000bec: 4b09 ldr r3, [pc, #36] ; (8000c14 <main+0x84>)
- 8000bee: 681b ldr r3, [r3, #0]
- 8000bf0: 221c movs r2, #28
- 8000bf2: 4619 mov r1, r3
- 8000bf4: 4809 ldr r0, [pc, #36] ; (8000c1c <main+0x8c>)
- 8000bf6: f003 fe33 bl 8004860 <HAL_UART_Receive_IT>
-
- /* USER CODE END 2 */
-
- /* Infinite loop */
- /* USER CODE BEGIN WHILE */
- while (1) {
- 8000bfa: e7fe b.n 8000bfa <main+0x6a>
- 8000bfc: 20000200 .word 0x20000200
- 8000c00: 200001ec .word 0x200001ec
- 8000c04: 200002bc .word 0x200002bc
- 8000c08: 200002a4 .word 0x200002a4
- 8000c0c: 200002d4 .word 0x200002d4
- 8000c10: 200002f8 .word 0x200002f8
- 8000c14: 200002d8 .word 0x200002d8
- 8000c18: 200002dc .word 0x200002dc
- 8000c1c: 2000016c .word 0x2000016c
-
-08000c20 <_Z18SystemClock_Configv>:
-/**
- * @brief System Clock Configuration
- * @retval None
- */
-void SystemClock_Config(void)
-{
- 8000c20: b580 push {r7, lr}
- 8000c22: b0b8 sub sp, #224 ; 0xe0
- 8000c24: af00 add r7, sp, #0
- RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- 8000c26: f107 03ac add.w r3, r7, #172 ; 0xac
- 8000c2a: 2234 movs r2, #52 ; 0x34
- 8000c2c: 2100 movs r1, #0
- 8000c2e: 4618 mov r0, r3
- 8000c30: f004 fcbe bl 80055b0 <memset>
- RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
- 8000c34: f107 0398 add.w r3, r7, #152 ; 0x98
- 8000c38: 2200 movs r2, #0
- 8000c3a: 601a str r2, [r3, #0]
- 8000c3c: 605a str r2, [r3, #4]
- 8000c3e: 609a str r2, [r3, #8]
- 8000c40: 60da str r2, [r3, #12]
- 8000c42: 611a str r2, [r3, #16]
- RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
- 8000c44: f107 0308 add.w r3, r7, #8
- 8000c48: 2290 movs r2, #144 ; 0x90
- 8000c4a: 2100 movs r1, #0
- 8000c4c: 4618 mov r0, r3
- 8000c4e: f004 fcaf bl 80055b0 <memset>
-
- /** Configure the main internal regulator output voltage
- */
- __HAL_RCC_PWR_CLK_ENABLE();
- 8000c52: 4b36 ldr r3, [pc, #216] ; (8000d2c <_Z18SystemClock_Configv+0x10c>)
- 8000c54: 6c1b ldr r3, [r3, #64] ; 0x40
- 8000c56: 4a35 ldr r2, [pc, #212] ; (8000d2c <_Z18SystemClock_Configv+0x10c>)
- 8000c58: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8000c5c: 6413 str r3, [r2, #64] ; 0x40
- 8000c5e: 4b33 ldr r3, [pc, #204] ; (8000d2c <_Z18SystemClock_Configv+0x10c>)
- 8000c60: 6c1b ldr r3, [r3, #64] ; 0x40
- 8000c62: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8000c66: 607b str r3, [r7, #4]
- 8000c68: 687b ldr r3, [r7, #4]
- __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
- 8000c6a: 4b31 ldr r3, [pc, #196] ; (8000d30 <_Z18SystemClock_Configv+0x110>)
- 8000c6c: 681b ldr r3, [r3, #0]
- 8000c6e: f423 4340 bic.w r3, r3, #49152 ; 0xc000
- 8000c72: 4a2f ldr r2, [pc, #188] ; (8000d30 <_Z18SystemClock_Configv+0x110>)
- 8000c74: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 8000c78: 6013 str r3, [r2, #0]
- 8000c7a: 4b2d ldr r3, [pc, #180] ; (8000d30 <_Z18SystemClock_Configv+0x110>)
- 8000c7c: 681b ldr r3, [r3, #0]
- 8000c7e: f403 4340 and.w r3, r3, #49152 ; 0xc000
- 8000c82: 603b str r3, [r7, #0]
- 8000c84: 683b ldr r3, [r7, #0]
- /** Initializes the CPU, AHB and APB busses clocks
- */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
- 8000c86: 2302 movs r3, #2
- 8000c88: f8c7 30ac str.w r3, [r7, #172] ; 0xac
- RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- 8000c8c: 2301 movs r3, #1
- 8000c8e: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
- RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- 8000c92: 2310 movs r3, #16
- 8000c94: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- 8000c98: 2300 movs r3, #0
- 8000c9a: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- 8000c9e: f107 03ac add.w r3, r7, #172 ; 0xac
- 8000ca2: 4618 mov r0, r3
- 8000ca4: f001 fbac bl 8002400 <HAL_RCC_OscConfig>
- 8000ca8: 4603 mov r3, r0
- 8000caa: 2b00 cmp r3, #0
- 8000cac: bf14 ite ne
- 8000cae: 2301 movne r3, #1
- 8000cb0: 2300 moveq r3, #0
- 8000cb2: b2db uxtb r3, r3
- 8000cb4: 2b00 cmp r3, #0
- 8000cb6: d001 beq.n 8000cbc <_Z18SystemClock_Configv+0x9c>
- {
- Error_Handler();
- 8000cb8: f000 fd84 bl 80017c4 <Error_Handler>
- }
- /** Initializes the CPU, AHB and APB busses clocks
- */
- RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- 8000cbc: 230f movs r3, #15
- 8000cbe: f8c7 3098 str.w r3, [r7, #152] ; 0x98
- |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
- 8000cc2: 2300 movs r3, #0
- 8000cc4: f8c7 309c str.w r3, [r7, #156] ; 0x9c
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- 8000cc8: 2300 movs r3, #0
- 8000cca: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- 8000cce: 2300 movs r3, #0
- 8000cd0: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
- 8000cd4: 2300 movs r3, #0
- 8000cd6: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
-
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
- 8000cda: f107 0398 add.w r3, r7, #152 ; 0x98
- 8000cde: 2100 movs r1, #0
- 8000ce0: 4618 mov r0, r3
- 8000ce2: f001 fdff bl 80028e4 <HAL_RCC_ClockConfig>
- 8000ce6: 4603 mov r3, r0
- 8000ce8: 2b00 cmp r3, #0
- 8000cea: bf14 ite ne
- 8000cec: 2301 movne r3, #1
- 8000cee: 2300 moveq r3, #0
- 8000cf0: b2db uxtb r3, r3
- 8000cf2: 2b00 cmp r3, #0
- 8000cf4: d001 beq.n 8000cfa <_Z18SystemClock_Configv+0xda>
- {
- Error_Handler();
- 8000cf6: f000 fd65 bl 80017c4 <Error_Handler>
- }
- PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6;
- 8000cfa: f44f 6300 mov.w r3, #2048 ; 0x800
- 8000cfe: 60bb str r3, [r7, #8]
- PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
- 8000d00: 2300 movs r3, #0
- 8000d02: 663b str r3, [r7, #96] ; 0x60
- if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
- 8000d04: f107 0308 add.w r3, r7, #8
- 8000d08: 4618 mov r0, r3
- 8000d0a: f001 ffb9 bl 8002c80 <HAL_RCCEx_PeriphCLKConfig>
- 8000d0e: 4603 mov r3, r0
- 8000d10: 2b00 cmp r3, #0
- 8000d12: bf14 ite ne
- 8000d14: 2301 movne r3, #1
- 8000d16: 2300 moveq r3, #0
- 8000d18: b2db uxtb r3, r3
- 8000d1a: 2b00 cmp r3, #0
- 8000d1c: d001 beq.n 8000d22 <_Z18SystemClock_Configv+0x102>
- {
- Error_Handler();
- 8000d1e: f000 fd51 bl 80017c4 <Error_Handler>
- }
-}
- 8000d22: bf00 nop
- 8000d24: 37e0 adds r7, #224 ; 0xe0
- 8000d26: 46bd mov sp, r7
- 8000d28: bd80 pop {r7, pc}
- 8000d2a: bf00 nop
- 8000d2c: 40023800 .word 0x40023800
- 8000d30: 40007000 .word 0x40007000
-
-08000d34 <_ZL12MX_NVIC_Initv>:
-/**
- * @brief NVIC Configuration.
- * @retval None
- */
-static void MX_NVIC_Init(void)
-{
- 8000d34: b580 push {r7, lr}
- 8000d36: af00 add r7, sp, #0
- /* TIM3_IRQn interrupt configuration */
- HAL_NVIC_SetPriority(TIM3_IRQn, 2, 1);
- 8000d38: 2201 movs r2, #1
- 8000d3a: 2102 movs r1, #2
- 8000d3c: 201d movs r0, #29
- 8000d3e: f001 f92a bl 8001f96 <HAL_NVIC_SetPriority>
- HAL_NVIC_EnableIRQ(TIM3_IRQn);
- 8000d42: 201d movs r0, #29
- 8000d44: f001 f943 bl 8001fce <HAL_NVIC_EnableIRQ>
- /* TIM6_DAC_IRQn interrupt configuration */
- HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 2, 2);
- 8000d48: 2202 movs r2, #2
- 8000d4a: 2102 movs r1, #2
- 8000d4c: 2036 movs r0, #54 ; 0x36
- 8000d4e: f001 f922 bl 8001f96 <HAL_NVIC_SetPriority>
- HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
- 8000d52: 2036 movs r0, #54 ; 0x36
- 8000d54: f001 f93b bl 8001fce <HAL_NVIC_EnableIRQ>
- /* USART6_IRQn interrupt configuration */
- HAL_NVIC_SetPriority(USART6_IRQn, 2, 0);
- 8000d58: 2200 movs r2, #0
- 8000d5a: 2102 movs r1, #2
- 8000d5c: 2047 movs r0, #71 ; 0x47
- 8000d5e: f001 f91a bl 8001f96 <HAL_NVIC_SetPriority>
- HAL_NVIC_EnableIRQ(USART6_IRQn);
- 8000d62: 2047 movs r0, #71 ; 0x47
- 8000d64: f001 f933 bl 8001fce <HAL_NVIC_EnableIRQ>
-}
- 8000d68: bf00 nop
- 8000d6a: bd80 pop {r7, pc}
-
-08000d6c <_ZL12MX_TIM2_Initv>:
- * @brief TIM2 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM2_Init(void)
-{
- 8000d6c: b580 push {r7, lr}
- 8000d6e: b08c sub sp, #48 ; 0x30
- 8000d70: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM2_Init 0 */
-
- /* USER CODE END TIM2_Init 0 */
-
- TIM_Encoder_InitTypeDef sConfig = {0};
- 8000d72: f107 030c add.w r3, r7, #12
- 8000d76: 2224 movs r2, #36 ; 0x24
- 8000d78: 2100 movs r1, #0
- 8000d7a: 4618 mov r0, r3
- 8000d7c: f004 fc18 bl 80055b0 <memset>
- TIM_MasterConfigTypeDef sMasterConfig = {0};
- 8000d80: 463b mov r3, r7
- 8000d82: 2200 movs r2, #0
- 8000d84: 601a str r2, [r3, #0]
- 8000d86: 605a str r2, [r3, #4]
- 8000d88: 609a str r2, [r3, #8]
-
- /* USER CODE BEGIN TIM2_Init 1 */
-
- /* USER CODE END TIM2_Init 1 */
- htim2.Instance = TIM2;
- 8000d8a: 4b26 ldr r3, [pc, #152] ; (8000e24 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000d8c: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
- 8000d90: 601a str r2, [r3, #0]
- htim2.Init.Prescaler = 0;
- 8000d92: 4b24 ldr r3, [pc, #144] ; (8000e24 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000d94: 2200 movs r2, #0
- 8000d96: 605a str r2, [r3, #4]
- htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8000d98: 4b22 ldr r3, [pc, #136] ; (8000e24 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000d9a: 2200 movs r2, #0
- 8000d9c: 609a str r2, [r3, #8]
- htim2.Init.Period = 4294967295;
- 8000d9e: 4b21 ldr r3, [pc, #132] ; (8000e24 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000da0: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 8000da4: 60da str r2, [r3, #12]
- htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8000da6: 4b1f ldr r3, [pc, #124] ; (8000e24 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000da8: 2200 movs r2, #0
- 8000daa: 611a str r2, [r3, #16]
- htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8000dac: 4b1d ldr r3, [pc, #116] ; (8000e24 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000dae: 2200 movs r2, #0
- 8000db0: 619a str r2, [r3, #24]
- sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
- 8000db2: 2303 movs r3, #3
- 8000db4: 60fb str r3, [r7, #12]
- sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
- 8000db6: 2300 movs r3, #0
- 8000db8: 613b str r3, [r7, #16]
- sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
- 8000dba: 2301 movs r3, #1
- 8000dbc: 617b str r3, [r7, #20]
- sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
- 8000dbe: 2300 movs r3, #0
- 8000dc0: 61bb str r3, [r7, #24]
- sConfig.IC1Filter = 0;
- 8000dc2: 2300 movs r3, #0
- 8000dc4: 61fb str r3, [r7, #28]
- sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
- 8000dc6: 2300 movs r3, #0
- 8000dc8: 623b str r3, [r7, #32]
- sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
- 8000dca: 2301 movs r3, #1
- 8000dcc: 627b str r3, [r7, #36] ; 0x24
- sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
- 8000dce: 2300 movs r3, #0
- 8000dd0: 62bb str r3, [r7, #40] ; 0x28
- sConfig.IC2Filter = 0;
- 8000dd2: 2300 movs r3, #0
- 8000dd4: 62fb str r3, [r7, #44] ; 0x2c
- if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK)
- 8000dd6: f107 030c add.w r3, r7, #12
- 8000dda: 4619 mov r1, r3
- 8000ddc: 4811 ldr r0, [pc, #68] ; (8000e24 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000dde: f002 fc45 bl 800366c <HAL_TIM_Encoder_Init>
- 8000de2: 4603 mov r3, r0
- 8000de4: 2b00 cmp r3, #0
- 8000de6: bf14 ite ne
- 8000de8: 2301 movne r3, #1
- 8000dea: 2300 moveq r3, #0
- 8000dec: b2db uxtb r3, r3
- 8000dee: 2b00 cmp r3, #0
- 8000df0: d001 beq.n 8000df6 <_ZL12MX_TIM2_Initv+0x8a>
- {
- Error_Handler();
- 8000df2: f000 fce7 bl 80017c4 <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8000df6: 2300 movs r3, #0
- 8000df8: 603b str r3, [r7, #0]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8000dfa: 2300 movs r3, #0
- 8000dfc: 60bb str r3, [r7, #8]
- if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
- 8000dfe: 463b mov r3, r7
- 8000e00: 4619 mov r1, r3
- 8000e02: 4808 ldr r0, [pc, #32] ; (8000e24 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000e04: f003 fbd2 bl 80045ac <HAL_TIMEx_MasterConfigSynchronization>
- 8000e08: 4603 mov r3, r0
- 8000e0a: 2b00 cmp r3, #0
- 8000e0c: bf14 ite ne
- 8000e0e: 2301 movne r3, #1
- 8000e10: 2300 moveq r3, #0
- 8000e12: b2db uxtb r3, r3
- 8000e14: 2b00 cmp r3, #0
- 8000e16: d001 beq.n 8000e1c <_ZL12MX_TIM2_Initv+0xb0>
- {
- Error_Handler();
- 8000e18: f000 fcd4 bl 80017c4 <Error_Handler>
- }
- /* USER CODE BEGIN TIM2_Init 2 */
-
- /* USER CODE END TIM2_Init 2 */
-
-}
- 8000e1c: bf00 nop
- 8000e1e: 3730 adds r7, #48 ; 0x30
- 8000e20: 46bd mov sp, r7
- 8000e22: bd80 pop {r7, pc}
- 8000e24: 2000002c .word 0x2000002c
-
-08000e28 <_ZL12MX_TIM3_Initv>:
- * @brief TIM3 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM3_Init(void)
-{
- 8000e28: b580 push {r7, lr}
- 8000e2a: b088 sub sp, #32
- 8000e2c: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM3_Init 0 */
-
- /* USER CODE END TIM3_Init 0 */
-
- TIM_ClockConfigTypeDef sClockSourceConfig = {0};
- 8000e2e: f107 0310 add.w r3, r7, #16
- 8000e32: 2200 movs r2, #0
- 8000e34: 601a str r2, [r3, #0]
- 8000e36: 605a str r2, [r3, #4]
- 8000e38: 609a str r2, [r3, #8]
- 8000e3a: 60da str r2, [r3, #12]
- TIM_MasterConfigTypeDef sMasterConfig = {0};
- 8000e3c: 1d3b adds r3, r7, #4
- 8000e3e: 2200 movs r2, #0
- 8000e40: 601a str r2, [r3, #0]
- 8000e42: 605a str r2, [r3, #4]
- 8000e44: 609a str r2, [r3, #8]
-
- /* USER CODE BEGIN TIM3_Init 1 */
-
- /* USER CODE END TIM3_Init 1 */
- htim3.Instance = TIM3;
- 8000e46: 4b25 ldr r3, [pc, #148] ; (8000edc <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e48: 4a25 ldr r2, [pc, #148] ; (8000ee0 <_ZL12MX_TIM3_Initv+0xb8>)
- 8000e4a: 601a str r2, [r3, #0]
- htim3.Init.Prescaler = 999;
- 8000e4c: 4b23 ldr r3, [pc, #140] ; (8000edc <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e4e: f240 32e7 movw r2, #999 ; 0x3e7
- 8000e52: 605a str r2, [r3, #4]
- htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8000e54: 4b21 ldr r3, [pc, #132] ; (8000edc <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e56: 2200 movs r2, #0
- 8000e58: 609a str r2, [r3, #8]
- htim3.Init.Period = 159;
- 8000e5a: 4b20 ldr r3, [pc, #128] ; (8000edc <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e5c: 229f movs r2, #159 ; 0x9f
- 8000e5e: 60da str r2, [r3, #12]
- htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8000e60: 4b1e ldr r3, [pc, #120] ; (8000edc <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e62: 2200 movs r2, #0
- 8000e64: 611a str r2, [r3, #16]
- htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8000e66: 4b1d ldr r3, [pc, #116] ; (8000edc <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e68: 2200 movs r2, #0
- 8000e6a: 619a str r2, [r3, #24]
- if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
- 8000e6c: 481b ldr r0, [pc, #108] ; (8000edc <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e6e: f002 fb2d bl 80034cc <HAL_TIM_Base_Init>
- 8000e72: 4603 mov r3, r0
- 8000e74: 2b00 cmp r3, #0
- 8000e76: bf14 ite ne
- 8000e78: 2301 movne r3, #1
- 8000e7a: 2300 moveq r3, #0
- 8000e7c: b2db uxtb r3, r3
- 8000e7e: 2b00 cmp r3, #0
- 8000e80: d001 beq.n 8000e86 <_ZL12MX_TIM3_Initv+0x5e>
- {
- Error_Handler();
- 8000e82: f000 fc9f bl 80017c4 <Error_Handler>
- }
- sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
- 8000e86: f44f 5380 mov.w r3, #4096 ; 0x1000
- 8000e8a: 613b str r3, [r7, #16]
- if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
- 8000e8c: f107 0310 add.w r3, r7, #16
- 8000e90: 4619 mov r1, r3
- 8000e92: 4812 ldr r0, [pc, #72] ; (8000edc <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e94: f002 feea bl 8003c6c <HAL_TIM_ConfigClockSource>
- 8000e98: 4603 mov r3, r0
- 8000e9a: 2b00 cmp r3, #0
- 8000e9c: bf14 ite ne
- 8000e9e: 2301 movne r3, #1
- 8000ea0: 2300 moveq r3, #0
- 8000ea2: b2db uxtb r3, r3
- 8000ea4: 2b00 cmp r3, #0
- 8000ea6: d001 beq.n 8000eac <_ZL12MX_TIM3_Initv+0x84>
- {
- Error_Handler();
- 8000ea8: f000 fc8c bl 80017c4 <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8000eac: 2300 movs r3, #0
- 8000eae: 607b str r3, [r7, #4]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8000eb0: 2300 movs r3, #0
- 8000eb2: 60fb str r3, [r7, #12]
- if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
- 8000eb4: 1d3b adds r3, r7, #4
- 8000eb6: 4619 mov r1, r3
- 8000eb8: 4808 ldr r0, [pc, #32] ; (8000edc <_ZL12MX_TIM3_Initv+0xb4>)
- 8000eba: f003 fb77 bl 80045ac <HAL_TIMEx_MasterConfigSynchronization>
- 8000ebe: 4603 mov r3, r0
- 8000ec0: 2b00 cmp r3, #0
- 8000ec2: bf14 ite ne
- 8000ec4: 2301 movne r3, #1
- 8000ec6: 2300 moveq r3, #0
- 8000ec8: b2db uxtb r3, r3
- 8000eca: 2b00 cmp r3, #0
- 8000ecc: d001 beq.n 8000ed2 <_ZL12MX_TIM3_Initv+0xaa>
- {
- Error_Handler();
- 8000ece: f000 fc79 bl 80017c4 <Error_Handler>
- }
- /* USER CODE BEGIN TIM3_Init 2 */
-
- /* USER CODE END TIM3_Init 2 */
-
-}
- 8000ed2: bf00 nop
- 8000ed4: 3720 adds r7, #32
- 8000ed6: 46bd mov sp, r7
- 8000ed8: bd80 pop {r7, pc}
- 8000eda: bf00 nop
- 8000edc: 2000006c .word 0x2000006c
- 8000ee0: 40000400 .word 0x40000400
-
-08000ee4 <_ZL12MX_TIM4_Initv>:
- * @brief TIM4 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM4_Init(void)
-{
- 8000ee4: b580 push {r7, lr}
- 8000ee6: b08e sub sp, #56 ; 0x38
- 8000ee8: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM4_Init 0 */
-
- /* USER CODE END TIM4_Init 0 */
-
- TIM_ClockConfigTypeDef sClockSourceConfig = {0};
- 8000eea: f107 0328 add.w r3, r7, #40 ; 0x28
- 8000eee: 2200 movs r2, #0
- 8000ef0: 601a str r2, [r3, #0]
- 8000ef2: 605a str r2, [r3, #4]
- 8000ef4: 609a str r2, [r3, #8]
- 8000ef6: 60da str r2, [r3, #12]
- TIM_MasterConfigTypeDef sMasterConfig = {0};
- 8000ef8: f107 031c add.w r3, r7, #28
- 8000efc: 2200 movs r2, #0
- 8000efe: 601a str r2, [r3, #0]
- 8000f00: 605a str r2, [r3, #4]
- 8000f02: 609a str r2, [r3, #8]
- TIM_OC_InitTypeDef sConfigOC = {0};
- 8000f04: 463b mov r3, r7
- 8000f06: 2200 movs r2, #0
- 8000f08: 601a str r2, [r3, #0]
- 8000f0a: 605a str r2, [r3, #4]
- 8000f0c: 609a str r2, [r3, #8]
- 8000f0e: 60da str r2, [r3, #12]
- 8000f10: 611a str r2, [r3, #16]
- 8000f12: 615a str r2, [r3, #20]
- 8000f14: 619a str r2, [r3, #24]
-
- /* USER CODE BEGIN TIM4_Init 1 */
-
- /* USER CODE END TIM4_Init 1 */
- htim4.Instance = TIM4;
- 8000f16: 4b41 ldr r3, [pc, #260] ; (800101c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f18: 4a41 ldr r2, [pc, #260] ; (8001020 <_ZL12MX_TIM4_Initv+0x13c>)
- 8000f1a: 601a str r2, [r3, #0]
- htim4.Init.Prescaler = 0;
- 8000f1c: 4b3f ldr r3, [pc, #252] ; (800101c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f1e: 2200 movs r2, #0
- 8000f20: 605a str r2, [r3, #4]
- htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8000f22: 4b3e ldr r3, [pc, #248] ; (800101c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f24: 2200 movs r2, #0
- 8000f26: 609a str r2, [r3, #8]
- htim4.Init.Period = 799;
- 8000f28: 4b3c ldr r3, [pc, #240] ; (800101c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f2a: f240 321f movw r2, #799 ; 0x31f
- 8000f2e: 60da str r2, [r3, #12]
- htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8000f30: 4b3a ldr r3, [pc, #232] ; (800101c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f32: 2200 movs r2, #0
- 8000f34: 611a str r2, [r3, #16]
- htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8000f36: 4b39 ldr r3, [pc, #228] ; (800101c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f38: 2200 movs r2, #0
- 8000f3a: 619a str r2, [r3, #24]
- if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
- 8000f3c: 4837 ldr r0, [pc, #220] ; (800101c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f3e: f002 fac5 bl 80034cc <HAL_TIM_Base_Init>
- 8000f42: 4603 mov r3, r0
- 8000f44: 2b00 cmp r3, #0
- 8000f46: bf14 ite ne
- 8000f48: 2301 movne r3, #1
- 8000f4a: 2300 moveq r3, #0
- 8000f4c: b2db uxtb r3, r3
- 8000f4e: 2b00 cmp r3, #0
- 8000f50: d001 beq.n 8000f56 <_ZL12MX_TIM4_Initv+0x72>
- {
- Error_Handler();
- 8000f52: f000 fc37 bl 80017c4 <Error_Handler>
- }
- sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
- 8000f56: f44f 5380 mov.w r3, #4096 ; 0x1000
- 8000f5a: 62bb str r3, [r7, #40] ; 0x28
- if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK)
- 8000f5c: f107 0328 add.w r3, r7, #40 ; 0x28
- 8000f60: 4619 mov r1, r3
- 8000f62: 482e ldr r0, [pc, #184] ; (800101c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f64: f002 fe82 bl 8003c6c <HAL_TIM_ConfigClockSource>
- 8000f68: 4603 mov r3, r0
- 8000f6a: 2b00 cmp r3, #0
- 8000f6c: bf14 ite ne
- 8000f6e: 2301 movne r3, #1
- 8000f70: 2300 moveq r3, #0
- 8000f72: b2db uxtb r3, r3
- 8000f74: 2b00 cmp r3, #0
- 8000f76: d001 beq.n 8000f7c <_ZL12MX_TIM4_Initv+0x98>
- {
- Error_Handler();
- 8000f78: f000 fc24 bl 80017c4 <Error_Handler>
- }
- if (HAL_TIM_PWM_Init(&htim4) != HAL_OK)
- 8000f7c: 4827 ldr r0, [pc, #156] ; (800101c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f7e: f002 fafb bl 8003578 <HAL_TIM_PWM_Init>
- 8000f82: 4603 mov r3, r0
- 8000f84: 2b00 cmp r3, #0
- 8000f86: bf14 ite ne
- 8000f88: 2301 movne r3, #1
- 8000f8a: 2300 moveq r3, #0
- 8000f8c: b2db uxtb r3, r3
- 8000f8e: 2b00 cmp r3, #0
- 8000f90: d001 beq.n 8000f96 <_ZL12MX_TIM4_Initv+0xb2>
- {
- Error_Handler();
- 8000f92: f000 fc17 bl 80017c4 <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8000f96: 2300 movs r3, #0
- 8000f98: 61fb str r3, [r7, #28]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8000f9a: 2300 movs r3, #0
- 8000f9c: 627b str r3, [r7, #36] ; 0x24
- if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
- 8000f9e: f107 031c add.w r3, r7, #28
- 8000fa2: 4619 mov r1, r3
- 8000fa4: 481d ldr r0, [pc, #116] ; (800101c <_ZL12MX_TIM4_Initv+0x138>)
- 8000fa6: f003 fb01 bl 80045ac <HAL_TIMEx_MasterConfigSynchronization>
- 8000faa: 4603 mov r3, r0
- 8000fac: 2b00 cmp r3, #0
- 8000fae: bf14 ite ne
- 8000fb0: 2301 movne r3, #1
- 8000fb2: 2300 moveq r3, #0
- 8000fb4: b2db uxtb r3, r3
- 8000fb6: 2b00 cmp r3, #0
- 8000fb8: d001 beq.n 8000fbe <_ZL12MX_TIM4_Initv+0xda>
- {
- Error_Handler();
- 8000fba: f000 fc03 bl 80017c4 <Error_Handler>
- }
- sConfigOC.OCMode = TIM_OCMODE_PWM1;
- 8000fbe: 2360 movs r3, #96 ; 0x60
- 8000fc0: 603b str r3, [r7, #0]
- sConfigOC.Pulse = 0;
- 8000fc2: 2300 movs r3, #0
- 8000fc4: 607b str r3, [r7, #4]
- sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
- 8000fc6: 2300 movs r3, #0
- 8000fc8: 60bb str r3, [r7, #8]
- sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
- 8000fca: 2300 movs r3, #0
- 8000fcc: 613b str r3, [r7, #16]
- if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
- 8000fce: 463b mov r3, r7
- 8000fd0: 2208 movs r2, #8
- 8000fd2: 4619 mov r1, r3
- 8000fd4: 4811 ldr r0, [pc, #68] ; (800101c <_ZL12MX_TIM4_Initv+0x138>)
- 8000fd6: f002 fd31 bl 8003a3c <HAL_TIM_PWM_ConfigChannel>
- 8000fda: 4603 mov r3, r0
- 8000fdc: 2b00 cmp r3, #0
- 8000fde: bf14 ite ne
- 8000fe0: 2301 movne r3, #1
- 8000fe2: 2300 moveq r3, #0
- 8000fe4: b2db uxtb r3, r3
- 8000fe6: 2b00 cmp r3, #0
- 8000fe8: d001 beq.n 8000fee <_ZL12MX_TIM4_Initv+0x10a>
- {
- Error_Handler();
- 8000fea: f000 fbeb bl 80017c4 <Error_Handler>
- }
- if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
- 8000fee: 463b mov r3, r7
- 8000ff0: 220c movs r2, #12
- 8000ff2: 4619 mov r1, r3
- 8000ff4: 4809 ldr r0, [pc, #36] ; (800101c <_ZL12MX_TIM4_Initv+0x138>)
- 8000ff6: f002 fd21 bl 8003a3c <HAL_TIM_PWM_ConfigChannel>
- 8000ffa: 4603 mov r3, r0
- 8000ffc: 2b00 cmp r3, #0
- 8000ffe: bf14 ite ne
- 8001000: 2301 movne r3, #1
- 8001002: 2300 moveq r3, #0
- 8001004: b2db uxtb r3, r3
- 8001006: 2b00 cmp r3, #0
- 8001008: d001 beq.n 800100e <_ZL12MX_TIM4_Initv+0x12a>
- {
- Error_Handler();
- 800100a: f000 fbdb bl 80017c4 <Error_Handler>
- }
- /* USER CODE BEGIN TIM4_Init 2 */
-
- /* USER CODE END TIM4_Init 2 */
- HAL_TIM_MspPostInit(&htim4);
- 800100e: 4803 ldr r0, [pc, #12] ; (800101c <_ZL12MX_TIM4_Initv+0x138>)
- 8001010: f000 fd5a bl 8001ac8 <HAL_TIM_MspPostInit>
-
-}
- 8001014: bf00 nop
- 8001016: 3738 adds r7, #56 ; 0x38
- 8001018: 46bd mov sp, r7
- 800101a: bd80 pop {r7, pc}
- 800101c: 200000ac .word 0x200000ac
- 8001020: 40000800 .word 0x40000800
-
-08001024 <_ZL12MX_TIM5_Initv>:
- * @brief TIM5 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM5_Init(void)
-{
- 8001024: b580 push {r7, lr}
- 8001026: b08c sub sp, #48 ; 0x30
- 8001028: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM5_Init 0 */
-
- /* USER CODE END TIM5_Init 0 */
-
- TIM_Encoder_InitTypeDef sConfig = {0};
- 800102a: f107 030c add.w r3, r7, #12
- 800102e: 2224 movs r2, #36 ; 0x24
- 8001030: 2100 movs r1, #0
- 8001032: 4618 mov r0, r3
- 8001034: f004 fabc bl 80055b0 <memset>
- TIM_MasterConfigTypeDef sMasterConfig = {0};
- 8001038: 463b mov r3, r7
- 800103a: 2200 movs r2, #0
- 800103c: 601a str r2, [r3, #0]
- 800103e: 605a str r2, [r3, #4]
- 8001040: 609a str r2, [r3, #8]
-
- /* USER CODE BEGIN TIM5_Init 1 */
-
- /* USER CODE END TIM5_Init 1 */
- htim5.Instance = TIM5;
- 8001042: 4b26 ldr r3, [pc, #152] ; (80010dc <_ZL12MX_TIM5_Initv+0xb8>)
- 8001044: 4a26 ldr r2, [pc, #152] ; (80010e0 <_ZL12MX_TIM5_Initv+0xbc>)
- 8001046: 601a str r2, [r3, #0]
- htim5.Init.Prescaler = 0;
- 8001048: 4b24 ldr r3, [pc, #144] ; (80010dc <_ZL12MX_TIM5_Initv+0xb8>)
- 800104a: 2200 movs r2, #0
- 800104c: 605a str r2, [r3, #4]
- htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
- 800104e: 4b23 ldr r3, [pc, #140] ; (80010dc <_ZL12MX_TIM5_Initv+0xb8>)
- 8001050: 2200 movs r2, #0
- 8001052: 609a str r2, [r3, #8]
- htim5.Init.Period = 4294967295;
- 8001054: 4b21 ldr r3, [pc, #132] ; (80010dc <_ZL12MX_TIM5_Initv+0xb8>)
- 8001056: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 800105a: 60da str r2, [r3, #12]
- htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 800105c: 4b1f ldr r3, [pc, #124] ; (80010dc <_ZL12MX_TIM5_Initv+0xb8>)
- 800105e: 2200 movs r2, #0
- 8001060: 611a str r2, [r3, #16]
- htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8001062: 4b1e ldr r3, [pc, #120] ; (80010dc <_ZL12MX_TIM5_Initv+0xb8>)
- 8001064: 2200 movs r2, #0
- 8001066: 619a str r2, [r3, #24]
- sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
- 8001068: 2303 movs r3, #3
- 800106a: 60fb str r3, [r7, #12]
- sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
- 800106c: 2300 movs r3, #0
- 800106e: 613b str r3, [r7, #16]
- sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
- 8001070: 2301 movs r3, #1
- 8001072: 617b str r3, [r7, #20]
- sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
- 8001074: 2300 movs r3, #0
- 8001076: 61bb str r3, [r7, #24]
- sConfig.IC1Filter = 0;
- 8001078: 2300 movs r3, #0
- 800107a: 61fb str r3, [r7, #28]
- sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
- 800107c: 2300 movs r3, #0
- 800107e: 623b str r3, [r7, #32]
- sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
- 8001080: 2301 movs r3, #1
- 8001082: 627b str r3, [r7, #36] ; 0x24
- sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
- 8001084: 2300 movs r3, #0
- 8001086: 62bb str r3, [r7, #40] ; 0x28
- sConfig.IC2Filter = 0;
- 8001088: 2300 movs r3, #0
- 800108a: 62fb str r3, [r7, #44] ; 0x2c
- if (HAL_TIM_Encoder_Init(&htim5, &sConfig) != HAL_OK)
- 800108c: f107 030c add.w r3, r7, #12
- 8001090: 4619 mov r1, r3
- 8001092: 4812 ldr r0, [pc, #72] ; (80010dc <_ZL12MX_TIM5_Initv+0xb8>)
- 8001094: f002 faea bl 800366c <HAL_TIM_Encoder_Init>
- 8001098: 4603 mov r3, r0
- 800109a: 2b00 cmp r3, #0
- 800109c: bf14 ite ne
- 800109e: 2301 movne r3, #1
- 80010a0: 2300 moveq r3, #0
- 80010a2: b2db uxtb r3, r3
- 80010a4: 2b00 cmp r3, #0
- 80010a6: d001 beq.n 80010ac <_ZL12MX_TIM5_Initv+0x88>
- {
- Error_Handler();
- 80010a8: f000 fb8c bl 80017c4 <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 80010ac: 2300 movs r3, #0
- 80010ae: 603b str r3, [r7, #0]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 80010b0: 2300 movs r3, #0
- 80010b2: 60bb str r3, [r7, #8]
- if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK)
- 80010b4: 463b mov r3, r7
- 80010b6: 4619 mov r1, r3
- 80010b8: 4808 ldr r0, [pc, #32] ; (80010dc <_ZL12MX_TIM5_Initv+0xb8>)
- 80010ba: f003 fa77 bl 80045ac <HAL_TIMEx_MasterConfigSynchronization>
- 80010be: 4603 mov r3, r0
- 80010c0: 2b00 cmp r3, #0
- 80010c2: bf14 ite ne
- 80010c4: 2301 movne r3, #1
- 80010c6: 2300 moveq r3, #0
- 80010c8: b2db uxtb r3, r3
- 80010ca: 2b00 cmp r3, #0
- 80010cc: d001 beq.n 80010d2 <_ZL12MX_TIM5_Initv+0xae>
- {
- Error_Handler();
- 80010ce: f000 fb79 bl 80017c4 <Error_Handler>
- }
- /* USER CODE BEGIN TIM5_Init 2 */
-
- /* USER CODE END TIM5_Init 2 */
-
-}
- 80010d2: bf00 nop
- 80010d4: 3730 adds r7, #48 ; 0x30
- 80010d6: 46bd mov sp, r7
- 80010d8: bd80 pop {r7, pc}
- 80010da: bf00 nop
- 80010dc: 200000ec .word 0x200000ec
- 80010e0: 40000c00 .word 0x40000c00
-
-080010e4 <_ZL12MX_TIM6_Initv>:
- * @brief TIM6 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM6_Init(void)
-{
- 80010e4: b580 push {r7, lr}
- 80010e6: b084 sub sp, #16
- 80010e8: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM6_Init 0 */
-
- /* USER CODE END TIM6_Init 0 */
-
- TIM_MasterConfigTypeDef sMasterConfig = {0};
- 80010ea: 1d3b adds r3, r7, #4
- 80010ec: 2200 movs r2, #0
- 80010ee: 601a str r2, [r3, #0]
- 80010f0: 605a str r2, [r3, #4]
- 80010f2: 609a str r2, [r3, #8]
-
- /* USER CODE BEGIN TIM6_Init 1 */
-
- /* USER CODE END TIM6_Init 1 */
- htim6.Instance = TIM6;
- 80010f4: 4b1a ldr r3, [pc, #104] ; (8001160 <_ZL12MX_TIM6_Initv+0x7c>)
- 80010f6: 4a1b ldr r2, [pc, #108] ; (8001164 <_ZL12MX_TIM6_Initv+0x80>)
- 80010f8: 601a str r2, [r3, #0]
- htim6.Init.Prescaler = 9999;
- 80010fa: 4b19 ldr r3, [pc, #100] ; (8001160 <_ZL12MX_TIM6_Initv+0x7c>)
- 80010fc: f242 720f movw r2, #9999 ; 0x270f
- 8001100: 605a str r2, [r3, #4]
- htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8001102: 4b17 ldr r3, [pc, #92] ; (8001160 <_ZL12MX_TIM6_Initv+0x7c>)
- 8001104: 2200 movs r2, #0
- 8001106: 609a str r2, [r3, #8]
- htim6.Init.Period = 799;
- 8001108: 4b15 ldr r3, [pc, #84] ; (8001160 <_ZL12MX_TIM6_Initv+0x7c>)
- 800110a: f240 321f movw r2, #799 ; 0x31f
- 800110e: 60da str r2, [r3, #12]
- htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8001110: 4b13 ldr r3, [pc, #76] ; (8001160 <_ZL12MX_TIM6_Initv+0x7c>)
- 8001112: 2200 movs r2, #0
- 8001114: 619a str r2, [r3, #24]
- if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
- 8001116: 4812 ldr r0, [pc, #72] ; (8001160 <_ZL12MX_TIM6_Initv+0x7c>)
- 8001118: f002 f9d8 bl 80034cc <HAL_TIM_Base_Init>
- 800111c: 4603 mov r3, r0
- 800111e: 2b00 cmp r3, #0
- 8001120: bf14 ite ne
- 8001122: 2301 movne r3, #1
- 8001124: 2300 moveq r3, #0
- 8001126: b2db uxtb r3, r3
- 8001128: 2b00 cmp r3, #0
- 800112a: d001 beq.n 8001130 <_ZL12MX_TIM6_Initv+0x4c>
- {
- Error_Handler();
- 800112c: f000 fb4a bl 80017c4 <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8001130: 2300 movs r3, #0
- 8001132: 607b str r3, [r7, #4]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8001134: 2300 movs r3, #0
- 8001136: 60fb str r3, [r7, #12]
- if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
- 8001138: 1d3b adds r3, r7, #4
- 800113a: 4619 mov r1, r3
- 800113c: 4808 ldr r0, [pc, #32] ; (8001160 <_ZL12MX_TIM6_Initv+0x7c>)
- 800113e: f003 fa35 bl 80045ac <HAL_TIMEx_MasterConfigSynchronization>
- 8001142: 4603 mov r3, r0
- 8001144: 2b00 cmp r3, #0
- 8001146: bf14 ite ne
- 8001148: 2301 movne r3, #1
- 800114a: 2300 moveq r3, #0
- 800114c: b2db uxtb r3, r3
- 800114e: 2b00 cmp r3, #0
- 8001150: d001 beq.n 8001156 <_ZL12MX_TIM6_Initv+0x72>
- {
- Error_Handler();
- 8001152: f000 fb37 bl 80017c4 <Error_Handler>
- }
- /* USER CODE BEGIN TIM6_Init 2 */
-
- /* USER CODE END TIM6_Init 2 */
-
-}
- 8001156: bf00 nop
- 8001158: 3710 adds r7, #16
- 800115a: 46bd mov sp, r7
- 800115c: bd80 pop {r7, pc}
- 800115e: bf00 nop
- 8001160: 2000012c .word 0x2000012c
- 8001164: 40001000 .word 0x40001000
-
-08001168 <_ZL19MX_USART6_UART_Initv>:
- * @brief USART6 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_USART6_UART_Init(void)
-{
- 8001168: b580 push {r7, lr}
- 800116a: af00 add r7, sp, #0
- /* USER CODE END USART6_Init 0 */
-
- /* USER CODE BEGIN USART6_Init 1 */
-
- /* USER CODE END USART6_Init 1 */
- huart6.Instance = USART6;
- 800116c: 4b16 ldr r3, [pc, #88] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>)
- 800116e: 4a17 ldr r2, [pc, #92] ; (80011cc <_ZL19MX_USART6_UART_Initv+0x64>)
- 8001170: 601a str r2, [r3, #0]
- huart6.Init.BaudRate = 115200;
- 8001172: 4b15 ldr r3, [pc, #84] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>)
- 8001174: f44f 32e1 mov.w r2, #115200 ; 0x1c200
- 8001178: 605a str r2, [r3, #4]
- huart6.Init.WordLength = UART_WORDLENGTH_8B;
- 800117a: 4b13 ldr r3, [pc, #76] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>)
- 800117c: 2200 movs r2, #0
- 800117e: 609a str r2, [r3, #8]
- huart6.Init.StopBits = UART_STOPBITS_1;
- 8001180: 4b11 ldr r3, [pc, #68] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>)
- 8001182: 2200 movs r2, #0
- 8001184: 60da str r2, [r3, #12]
- huart6.Init.Parity = UART_PARITY_NONE;
- 8001186: 4b10 ldr r3, [pc, #64] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>)
- 8001188: 2200 movs r2, #0
- 800118a: 611a str r2, [r3, #16]
- huart6.Init.Mode = UART_MODE_TX_RX;
- 800118c: 4b0e ldr r3, [pc, #56] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>)
- 800118e: 220c movs r2, #12
- 8001190: 615a str r2, [r3, #20]
- huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
- 8001192: 4b0d ldr r3, [pc, #52] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>)
- 8001194: 2200 movs r2, #0
- 8001196: 619a str r2, [r3, #24]
- huart6.Init.OverSampling = UART_OVERSAMPLING_16;
- 8001198: 4b0b ldr r3, [pc, #44] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>)
- 800119a: 2200 movs r2, #0
- 800119c: 61da str r2, [r3, #28]
- huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
- 800119e: 4b0a ldr r3, [pc, #40] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>)
- 80011a0: 2200 movs r2, #0
- 80011a2: 621a str r2, [r3, #32]
- huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
- 80011a4: 4b08 ldr r3, [pc, #32] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>)
- 80011a6: 2200 movs r2, #0
- 80011a8: 625a str r2, [r3, #36] ; 0x24
- if (HAL_UART_Init(&huart6) != HAL_OK)
- 80011aa: 4807 ldr r0, [pc, #28] ; (80011c8 <_ZL19MX_USART6_UART_Initv+0x60>)
- 80011ac: f003 fa78 bl 80046a0 <HAL_UART_Init>
- 80011b0: 4603 mov r3, r0
- 80011b2: 2b00 cmp r3, #0
- 80011b4: bf14 ite ne
- 80011b6: 2301 movne r3, #1
- 80011b8: 2300 moveq r3, #0
- 80011ba: b2db uxtb r3, r3
- 80011bc: 2b00 cmp r3, #0
- 80011be: d001 beq.n 80011c4 <_ZL19MX_USART6_UART_Initv+0x5c>
- {
- Error_Handler();
- 80011c0: f000 fb00 bl 80017c4 <Error_Handler>
- }
- /* USER CODE BEGIN USART6_Init 2 */
-
- /* USER CODE END USART6_Init 2 */
-
-}
- 80011c4: bf00 nop
- 80011c6: bd80 pop {r7, pc}
- 80011c8: 2000016c .word 0x2000016c
- 80011cc: 40011400 .word 0x40011400
-
-080011d0 <_ZL12MX_GPIO_Initv>:
- * @brief GPIO Initialization Function
- * @param None
- * @retval None
- */
-static void MX_GPIO_Init(void)
-{
- 80011d0: b580 push {r7, lr}
- 80011d2: b08c sub sp, #48 ; 0x30
- 80011d4: af00 add r7, sp, #0
- GPIO_InitTypeDef GPIO_InitStruct = {0};
- 80011d6: f107 031c add.w r3, r7, #28
- 80011da: 2200 movs r2, #0
- 80011dc: 601a str r2, [r3, #0]
- 80011de: 605a str r2, [r3, #4]
- 80011e0: 609a str r2, [r3, #8]
- 80011e2: 60da str r2, [r3, #12]
- 80011e4: 611a str r2, [r3, #16]
-
- /* GPIO Ports Clock Enable */
- __HAL_RCC_GPIOC_CLK_ENABLE();
- 80011e6: 4b5e ldr r3, [pc, #376] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>)
- 80011e8: 6b1b ldr r3, [r3, #48] ; 0x30
- 80011ea: 4a5d ldr r2, [pc, #372] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>)
- 80011ec: f043 0304 orr.w r3, r3, #4
- 80011f0: 6313 str r3, [r2, #48] ; 0x30
- 80011f2: 4b5b ldr r3, [pc, #364] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>)
- 80011f4: 6b1b ldr r3, [r3, #48] ; 0x30
- 80011f6: f003 0304 and.w r3, r3, #4
- 80011fa: 61bb str r3, [r7, #24]
- 80011fc: 69bb ldr r3, [r7, #24]
- __HAL_RCC_GPIOA_CLK_ENABLE();
- 80011fe: 4b58 ldr r3, [pc, #352] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>)
- 8001200: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001202: 4a57 ldr r2, [pc, #348] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>)
- 8001204: f043 0301 orr.w r3, r3, #1
- 8001208: 6313 str r3, [r2, #48] ; 0x30
- 800120a: 4b55 ldr r3, [pc, #340] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>)
- 800120c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800120e: f003 0301 and.w r3, r3, #1
- 8001212: 617b str r3, [r7, #20]
- 8001214: 697b ldr r3, [r7, #20]
- __HAL_RCC_GPIOF_CLK_ENABLE();
- 8001216: 4b52 ldr r3, [pc, #328] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>)
- 8001218: 6b1b ldr r3, [r3, #48] ; 0x30
- 800121a: 4a51 ldr r2, [pc, #324] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>)
- 800121c: f043 0320 orr.w r3, r3, #32
- 8001220: 6313 str r3, [r2, #48] ; 0x30
- 8001222: 4b4f ldr r3, [pc, #316] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>)
- 8001224: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001226: f003 0320 and.w r3, r3, #32
- 800122a: 613b str r3, [r7, #16]
- 800122c: 693b ldr r3, [r7, #16]
- __HAL_RCC_GPIOE_CLK_ENABLE();
- 800122e: 4b4c ldr r3, [pc, #304] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>)
- 8001230: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001232: 4a4b ldr r2, [pc, #300] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>)
- 8001234: f043 0310 orr.w r3, r3, #16
- 8001238: 6313 str r3, [r2, #48] ; 0x30
- 800123a: 4b49 ldr r3, [pc, #292] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>)
- 800123c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800123e: f003 0310 and.w r3, r3, #16
- 8001242: 60fb str r3, [r7, #12]
- 8001244: 68fb ldr r3, [r7, #12]
- __HAL_RCC_GPIOD_CLK_ENABLE();
- 8001246: 4b46 ldr r3, [pc, #280] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>)
- 8001248: 6b1b ldr r3, [r3, #48] ; 0x30
- 800124a: 4a45 ldr r2, [pc, #276] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>)
- 800124c: f043 0308 orr.w r3, r3, #8
- 8001250: 6313 str r3, [r2, #48] ; 0x30
- 8001252: 4b43 ldr r3, [pc, #268] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>)
- 8001254: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001256: f003 0308 and.w r3, r3, #8
- 800125a: 60bb str r3, [r7, #8]
- 800125c: 68bb ldr r3, [r7, #8]
- __HAL_RCC_GPIOB_CLK_ENABLE();
- 800125e: 4b40 ldr r3, [pc, #256] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>)
- 8001260: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001262: 4a3f ldr r2, [pc, #252] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>)
- 8001264: f043 0302 orr.w r3, r3, #2
- 8001268: 6313 str r3, [r2, #48] ; 0x30
- 800126a: 4b3d ldr r3, [pc, #244] ; (8001360 <_ZL12MX_GPIO_Initv+0x190>)
- 800126c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800126e: f003 0302 and.w r3, r3, #2
- 8001272: 607b str r3, [r7, #4]
- 8001274: 687b ldr r3, [r7, #4]
-
- /*Configure GPIO pin Output Level */
- HAL_GPIO_WritePin(GPIOF, dir2_Pin|dir1_Pin, GPIO_PIN_RESET);
- 8001276: 2200 movs r2, #0
- 8001278: f44f 5140 mov.w r1, #12288 ; 0x3000
- 800127c: 4839 ldr r0, [pc, #228] ; (8001364 <_ZL12MX_GPIO_Initv+0x194>)
- 800127e: f001 f88d bl 800239c <HAL_GPIO_WritePin>
-
- /*Configure GPIO pin Output Level */
- HAL_GPIO_WritePin(GPIOF, sleep2_Pin|sleep1_Pin, GPIO_PIN_SET);
- 8001282: 2201 movs r2, #1
- 8001284: f44f 4140 mov.w r1, #49152 ; 0xc000
- 8001288: 4836 ldr r0, [pc, #216] ; (8001364 <_ZL12MX_GPIO_Initv+0x194>)
- 800128a: f001 f887 bl 800239c <HAL_GPIO_WritePin>
-
- /*Configure GPIO pin : user_button_Pin */
- GPIO_InitStruct.Pin = user_button_Pin;
- 800128e: f44f 5300 mov.w r3, #8192 ; 0x2000
- 8001292: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
- 8001294: 4b34 ldr r3, [pc, #208] ; (8001368 <_ZL12MX_GPIO_Initv+0x198>)
- 8001296: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001298: 2300 movs r3, #0
- 800129a: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(user_button_GPIO_Port, &GPIO_InitStruct);
- 800129c: f107 031c add.w r3, r7, #28
- 80012a0: 4619 mov r1, r3
- 80012a2: 4832 ldr r0, [pc, #200] ; (800136c <_ZL12MX_GPIO_Initv+0x19c>)
- 80012a4: f000 fed0 bl 8002048 <HAL_GPIO_Init>
-
- /*Configure GPIO pin : current2_Pin */
- GPIO_InitStruct.Pin = current2_Pin;
- 80012a8: 2301 movs r3, #1
- 80012aa: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
- 80012ac: 2303 movs r3, #3
- 80012ae: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80012b0: 2300 movs r3, #0
- 80012b2: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(current2_GPIO_Port, &GPIO_InitStruct);
- 80012b4: f107 031c add.w r3, r7, #28
- 80012b8: 4619 mov r1, r3
- 80012ba: 482c ldr r0, [pc, #176] ; (800136c <_ZL12MX_GPIO_Initv+0x19c>)
- 80012bc: f000 fec4 bl 8002048 <HAL_GPIO_Init>
-
- /*Configure GPIO pin : current1_Pin */
- GPIO_InitStruct.Pin = current1_Pin;
- 80012c0: 2308 movs r3, #8
- 80012c2: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
- 80012c4: 2303 movs r3, #3
- 80012c6: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80012c8: 2300 movs r3, #0
- 80012ca: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(current1_GPIO_Port, &GPIO_InitStruct);
- 80012cc: f107 031c add.w r3, r7, #28
- 80012d0: 4619 mov r1, r3
- 80012d2: 4827 ldr r0, [pc, #156] ; (8001370 <_ZL12MX_GPIO_Initv+0x1a0>)
- 80012d4: f000 feb8 bl 8002048 <HAL_GPIO_Init>
-
- /*Configure GPIO pin : fault2_Pin */
- GPIO_InitStruct.Pin = fault2_Pin;
- 80012d8: 2340 movs r3, #64 ; 0x40
- 80012da: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
- 80012dc: 2300 movs r3, #0
- 80012de: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80012e0: 2300 movs r3, #0
- 80012e2: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(fault2_GPIO_Port, &GPIO_InitStruct);
- 80012e4: f107 031c add.w r3, r7, #28
- 80012e8: 4619 mov r1, r3
- 80012ea: 4821 ldr r0, [pc, #132] ; (8001370 <_ZL12MX_GPIO_Initv+0x1a0>)
- 80012ec: f000 feac bl 8002048 <HAL_GPIO_Init>
-
- /*Configure GPIO pins : dir2_Pin dir1_Pin */
- GPIO_InitStruct.Pin = dir2_Pin|dir1_Pin;
- 80012f0: f44f 5340 mov.w r3, #12288 ; 0x3000
- 80012f4: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
- 80012f6: 2301 movs r3, #1
- 80012f8: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80012fa: 2300 movs r3, #0
- 80012fc: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 80012fe: 2300 movs r3, #0
- 8001300: 62bb str r3, [r7, #40] ; 0x28
- HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
- 8001302: f107 031c add.w r3, r7, #28
- 8001306: 4619 mov r1, r3
- 8001308: 4816 ldr r0, [pc, #88] ; (8001364 <_ZL12MX_GPIO_Initv+0x194>)
- 800130a: f000 fe9d bl 8002048 <HAL_GPIO_Init>
-
- /*Configure GPIO pins : sleep2_Pin sleep1_Pin */
- GPIO_InitStruct.Pin = sleep2_Pin|sleep1_Pin;
- 800130e: f44f 4340 mov.w r3, #49152 ; 0xc000
- 8001312: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
- 8001314: 2301 movs r3, #1
- 8001316: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_PULLUP;
- 8001318: 2301 movs r3, #1
- 800131a: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 800131c: 2300 movs r3, #0
- 800131e: 62bb str r3, [r7, #40] ; 0x28
- HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
- 8001320: f107 031c add.w r3, r7, #28
- 8001324: 4619 mov r1, r3
- 8001326: 480f ldr r0, [pc, #60] ; (8001364 <_ZL12MX_GPIO_Initv+0x194>)
- 8001328: f000 fe8e bl 8002048 <HAL_GPIO_Init>
-
- /*Configure GPIO pin : fault1_Pin */
- GPIO_InitStruct.Pin = fault1_Pin;
- 800132c: f44f 7300 mov.w r3, #512 ; 0x200
- 8001330: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
- 8001332: 2300 movs r3, #0
- 8001334: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001336: 2300 movs r3, #0
- 8001338: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(fault1_GPIO_Port, &GPIO_InitStruct);
- 800133a: f107 031c add.w r3, r7, #28
- 800133e: 4619 mov r1, r3
- 8001340: 480c ldr r0, [pc, #48] ; (8001374 <_ZL12MX_GPIO_Initv+0x1a4>)
- 8001342: f000 fe81 bl 8002048 <HAL_GPIO_Init>
-
- /* EXTI interrupt init*/
- HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);
- 8001346: 2200 movs r2, #0
- 8001348: 2100 movs r1, #0
- 800134a: 2028 movs r0, #40 ; 0x28
- 800134c: f000 fe23 bl 8001f96 <HAL_NVIC_SetPriority>
- HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
- 8001350: 2028 movs r0, #40 ; 0x28
- 8001352: f000 fe3c bl 8001fce <HAL_NVIC_EnableIRQ>
-
-}
- 8001356: bf00 nop
- 8001358: 3730 adds r7, #48 ; 0x30
- 800135a: 46bd mov sp, r7
- 800135c: bd80 pop {r7, pc}
- 800135e: bf00 nop
- 8001360: 40023800 .word 0x40023800
- 8001364: 40021400 .word 0x40021400
- 8001368: 10110000 .word 0x10110000
- 800136c: 40020800 .word 0x40020800
- 8001370: 40020000 .word 0x40020000
- 8001374: 40021000 .word 0x40021000
-
-08001378 <HAL_TIM_PeriodElapsedCallback>:
-
-/* USER CODE BEGIN 4 */
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
- 8001378: b580 push {r7, lr}
- 800137a: b084 sub sp, #16
- 800137c: af00 add r7, sp, #0
- 800137e: 6078 str r0, [r7, #4]
-
- //TIMER 100Hz PID control
- if (htim->Instance == TIM3) {
- 8001380: 687b ldr r3, [r7, #4]
- 8001382: 681b ldr r3, [r3, #0]
- 8001384: 4a62 ldr r2, [pc, #392] ; (8001510 <HAL_TIM_PeriodElapsedCallback+0x198>)
- 8001386: 4293 cmp r3, r2
- 8001388: f040 80be bne.w 8001508 <HAL_TIM_PeriodElapsedCallback+0x190>
-
- if (mode == 1) {
- 800138c: 4b61 ldr r3, [pc, #388] ; (8001514 <HAL_TIM_PeriodElapsedCallback+0x19c>)
- 800138e: edd3 7a00 vldr s15, [r3]
- 8001392: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0
- 8001396: eef4 7a47 vcmp.f32 s15, s14
- 800139a: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800139e: d123 bne.n 80013e8 <HAL_TIM_PeriodElapsedCallback+0x70>
- left_velocity = left_encoder.GetLinearVelocity();
- 80013a0: 485d ldr r0, [pc, #372] ; (8001518 <HAL_TIM_PeriodElapsedCallback+0x1a0>)
- 80013a2: f7ff f937 bl 8000614 <_ZN7Encoder17GetLinearVelocityEv>
- 80013a6: eef0 7a40 vmov.f32 s15, s0
- 80013aa: 4b5c ldr r3, [pc, #368] ; (800151c <HAL_TIM_PeriodElapsedCallback+0x1a4>)
- 80013ac: edc3 7a00 vstr s15, [r3]
- output_msg.velocity = left_velocity;
- 80013b0: 4b5a ldr r3, [pc, #360] ; (800151c <HAL_TIM_PeriodElapsedCallback+0x1a4>)
- 80013b2: 681b ldr r3, [r3, #0]
- 80013b4: 4a5a ldr r2, [pc, #360] ; (8001520 <HAL_TIM_PeriodElapsedCallback+0x1a8>)
- 80013b6: 6013 str r3, [r2, #0]
- left_dutycycle = left_pid.update(left_velocity);
- 80013b8: 4b58 ldr r3, [pc, #352] ; (800151c <HAL_TIM_PeriodElapsedCallback+0x1a4>)
- 80013ba: edd3 7a00 vldr s15, [r3]
- 80013be: eeb0 0a67 vmov.f32 s0, s15
- 80013c2: 4858 ldr r0, [pc, #352] ; (8001524 <HAL_TIM_PeriodElapsedCallback+0x1ac>)
- 80013c4: f7ff fb8c bl 8000ae0 <_ZN3Pid6updateEf>
- 80013c8: 4602 mov r2, r0
- 80013ca: 4b57 ldr r3, [pc, #348] ; (8001528 <HAL_TIM_PeriodElapsedCallback+0x1b0>)
- 80013cc: 601a str r2, [r3, #0]
- left_motor.set_speed(left_dutycycle);
- 80013ce: 4b56 ldr r3, [pc, #344] ; (8001528 <HAL_TIM_PeriodElapsedCallback+0x1b0>)
- 80013d0: 681b ldr r3, [r3, #0]
- 80013d2: 4619 mov r1, r3
- 80013d4: 4855 ldr r0, [pc, #340] ; (800152c <HAL_TIM_PeriodElapsedCallback+0x1b4>)
- 80013d6: f7ff f9e1 bl 800079c <_ZN15MotorController9set_speedEi>
- HAL_UART_Transmit(&huart6, tx_buffer, 4, 100);
- 80013da: 4b55 ldr r3, [pc, #340] ; (8001530 <HAL_TIM_PeriodElapsedCallback+0x1b8>)
- 80013dc: 6819 ldr r1, [r3, #0]
- 80013de: 2364 movs r3, #100 ; 0x64
- 80013e0: 2204 movs r2, #4
- 80013e2: 4854 ldr r0, [pc, #336] ; (8001534 <HAL_TIM_PeriodElapsedCallback+0x1bc>)
- 80013e4: f003 f9aa bl 800473c <HAL_UART_Transmit>
-
- }
- if (mode == 2) {
- 80013e8: 4b4a ldr r3, [pc, #296] ; (8001514 <HAL_TIM_PeriodElapsedCallback+0x19c>)
- 80013ea: edd3 7a00 vldr s15, [r3]
- 80013ee: eeb0 7a00 vmov.f32 s14, #0 ; 0x40000000 2.0
- 80013f2: eef4 7a47 vcmp.f32 s15, s14
- 80013f6: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80013fa: d123 bne.n 8001444 <HAL_TIM_PeriodElapsedCallback+0xcc>
- right_velocity = right_encoder.GetLinearVelocity();
- 80013fc: 484e ldr r0, [pc, #312] ; (8001538 <HAL_TIM_PeriodElapsedCallback+0x1c0>)
- 80013fe: f7ff f909 bl 8000614 <_ZN7Encoder17GetLinearVelocityEv>
- 8001402: eef0 7a40 vmov.f32 s15, s0
- 8001406: 4b4d ldr r3, [pc, #308] ; (800153c <HAL_TIM_PeriodElapsedCallback+0x1c4>)
- 8001408: edc3 7a00 vstr s15, [r3]
- output_msg.velocity = right_velocity;
- 800140c: 4b4b ldr r3, [pc, #300] ; (800153c <HAL_TIM_PeriodElapsedCallback+0x1c4>)
- 800140e: 681b ldr r3, [r3, #0]
- 8001410: 4a43 ldr r2, [pc, #268] ; (8001520 <HAL_TIM_PeriodElapsedCallback+0x1a8>)
- 8001412: 6013 str r3, [r2, #0]
- right_dutycycle = right_pid.update(right_velocity);
- 8001414: 4b49 ldr r3, [pc, #292] ; (800153c <HAL_TIM_PeriodElapsedCallback+0x1c4>)
- 8001416: edd3 7a00 vldr s15, [r3]
- 800141a: eeb0 0a67 vmov.f32 s0, s15
- 800141e: 4848 ldr r0, [pc, #288] ; (8001540 <HAL_TIM_PeriodElapsedCallback+0x1c8>)
- 8001420: f7ff fb5e bl 8000ae0 <_ZN3Pid6updateEf>
- 8001424: 4602 mov r2, r0
- 8001426: 4b47 ldr r3, [pc, #284] ; (8001544 <HAL_TIM_PeriodElapsedCallback+0x1cc>)
- 8001428: 601a str r2, [r3, #0]
- right_motor.set_speed(right_dutycycle);
- 800142a: 4b46 ldr r3, [pc, #280] ; (8001544 <HAL_TIM_PeriodElapsedCallback+0x1cc>)
- 800142c: 681b ldr r3, [r3, #0]
- 800142e: 4619 mov r1, r3
- 8001430: 4845 ldr r0, [pc, #276] ; (8001548 <HAL_TIM_PeriodElapsedCallback+0x1d0>)
- 8001432: f7ff f9b3 bl 800079c <_ZN15MotorController9set_speedEi>
- HAL_UART_Transmit(&huart6, tx_buffer, 4, 100);
- 8001436: 4b3e ldr r3, [pc, #248] ; (8001530 <HAL_TIM_PeriodElapsedCallback+0x1b8>)
- 8001438: 6819 ldr r1, [r3, #0]
- 800143a: 2364 movs r3, #100 ; 0x64
- 800143c: 2204 movs r2, #4
- 800143e: 483d ldr r0, [pc, #244] ; (8001534 <HAL_TIM_PeriodElapsedCallback+0x1bc>)
- 8001440: f003 f97c bl 800473c <HAL_UART_Transmit>
- }
- if (mode == 3) {
- 8001444: 4b33 ldr r3, [pc, #204] ; (8001514 <HAL_TIM_PeriodElapsedCallback+0x19c>)
- 8001446: edd3 7a00 vldr s15, [r3]
- 800144a: eeb0 7a08 vmov.f32 s14, #8 ; 0x40400000 3.0
- 800144e: eef4 7a47 vcmp.f32 s15, s14
- 8001452: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001456: d157 bne.n 8001508 <HAL_TIM_PeriodElapsedCallback+0x190>
-
- left_velocity = left_encoder.GetLinearVelocity();
- 8001458: 482f ldr r0, [pc, #188] ; (8001518 <HAL_TIM_PeriodElapsedCallback+0x1a0>)
- 800145a: f7ff f8db bl 8000614 <_ZN7Encoder17GetLinearVelocityEv>
- 800145e: eef0 7a40 vmov.f32 s15, s0
- 8001462: 4b2e ldr r3, [pc, #184] ; (800151c <HAL_TIM_PeriodElapsedCallback+0x1a4>)
- 8001464: edc3 7a00 vstr s15, [r3]
- left_dutycycle = left_pid.update(left_velocity);
- 8001468: 4b2c ldr r3, [pc, #176] ; (800151c <HAL_TIM_PeriodElapsedCallback+0x1a4>)
- 800146a: edd3 7a00 vldr s15, [r3]
- 800146e: eeb0 0a67 vmov.f32 s0, s15
- 8001472: 482c ldr r0, [pc, #176] ; (8001524 <HAL_TIM_PeriodElapsedCallback+0x1ac>)
- 8001474: f7ff fb34 bl 8000ae0 <_ZN3Pid6updateEf>
- 8001478: 4602 mov r2, r0
- 800147a: 4b2b ldr r3, [pc, #172] ; (8001528 <HAL_TIM_PeriodElapsedCallback+0x1b0>)
- 800147c: 601a str r2, [r3, #0]
- left_motor.set_speed(left_dutycycle);
- 800147e: 4b2a ldr r3, [pc, #168] ; (8001528 <HAL_TIM_PeriodElapsedCallback+0x1b0>)
- 8001480: 681b ldr r3, [r3, #0]
- 8001482: 4619 mov r1, r3
- 8001484: 4829 ldr r0, [pc, #164] ; (800152c <HAL_TIM_PeriodElapsedCallback+0x1b4>)
- 8001486: f7ff f989 bl 800079c <_ZN15MotorController9set_speedEi>
-
- right_velocity = right_encoder.GetLinearVelocity();
- 800148a: 482b ldr r0, [pc, #172] ; (8001538 <HAL_TIM_PeriodElapsedCallback+0x1c0>)
- 800148c: f7ff f8c2 bl 8000614 <_ZN7Encoder17GetLinearVelocityEv>
- 8001490: eef0 7a40 vmov.f32 s15, s0
- 8001494: 4b29 ldr r3, [pc, #164] ; (800153c <HAL_TIM_PeriodElapsedCallback+0x1c4>)
- 8001496: edc3 7a00 vstr s15, [r3]
- right_dutycycle = right_pid.update(right_velocity);
- 800149a: 4b28 ldr r3, [pc, #160] ; (800153c <HAL_TIM_PeriodElapsedCallback+0x1c4>)
- 800149c: edd3 7a00 vldr s15, [r3]
- 80014a0: eeb0 0a67 vmov.f32 s0, s15
- 80014a4: 4826 ldr r0, [pc, #152] ; (8001540 <HAL_TIM_PeriodElapsedCallback+0x1c8>)
- 80014a6: f7ff fb1b bl 8000ae0 <_ZN3Pid6updateEf>
- 80014aa: 4602 mov r2, r0
- 80014ac: 4b25 ldr r3, [pc, #148] ; (8001544 <HAL_TIM_PeriodElapsedCallback+0x1cc>)
- 80014ae: 601a str r2, [r3, #0]
- right_motor.set_speed(right_dutycycle);
- 80014b0: 4b24 ldr r3, [pc, #144] ; (8001544 <HAL_TIM_PeriodElapsedCallback+0x1cc>)
- 80014b2: 681b ldr r3, [r3, #0]
- 80014b4: 4619 mov r1, r3
- 80014b6: 4824 ldr r0, [pc, #144] ; (8001548 <HAL_TIM_PeriodElapsedCallback+0x1d0>)
- 80014b8: f7ff f970 bl 800079c <_ZN15MotorController9set_speedEi>
-
- float difference = left_velocity - right_velocity;
- 80014bc: 4b17 ldr r3, [pc, #92] ; (800151c <HAL_TIM_PeriodElapsedCallback+0x1a4>)
- 80014be: ed93 7a00 vldr s14, [r3]
- 80014c2: 4b1e ldr r3, [pc, #120] ; (800153c <HAL_TIM_PeriodElapsedCallback+0x1c4>)
- 80014c4: edd3 7a00 vldr s15, [r3]
- 80014c8: ee77 7a67 vsub.f32 s15, s14, s15
- 80014cc: edc7 7a03 vstr s15, [r7, #12]
-
- int cross_dutycycle = cross_pid.update(difference);
- 80014d0: ed97 0a03 vldr s0, [r7, #12]
- 80014d4: 481d ldr r0, [pc, #116] ; (800154c <HAL_TIM_PeriodElapsedCallback+0x1d4>)
- 80014d6: f7ff fb03 bl 8000ae0 <_ZN3Pid6updateEf>
- 80014da: 60b8 str r0, [r7, #8]
-
- left_dutycycle += cross_dutycycle;
- 80014dc: 4b12 ldr r3, [pc, #72] ; (8001528 <HAL_TIM_PeriodElapsedCallback+0x1b0>)
- 80014de: 681a ldr r2, [r3, #0]
- 80014e0: 68bb ldr r3, [r7, #8]
- 80014e2: 4413 add r3, r2
- 80014e4: 4a10 ldr r2, [pc, #64] ; (8001528 <HAL_TIM_PeriodElapsedCallback+0x1b0>)
- 80014e6: 6013 str r3, [r2, #0]
- right_dutycycle -= cross_dutycycle;
- 80014e8: 4b16 ldr r3, [pc, #88] ; (8001544 <HAL_TIM_PeriodElapsedCallback+0x1cc>)
- 80014ea: 681a ldr r2, [r3, #0]
- 80014ec: 68bb ldr r3, [r7, #8]
- 80014ee: 1ad3 subs r3, r2, r3
- 80014f0: 4a14 ldr r2, [pc, #80] ; (8001544 <HAL_TIM_PeriodElapsedCallback+0x1cc>)
- 80014f2: 6013 str r3, [r2, #0]
-
- output_msg.velocity = difference;
- 80014f4: 4a0a ldr r2, [pc, #40] ; (8001520 <HAL_TIM_PeriodElapsedCallback+0x1a8>)
- 80014f6: 68fb ldr r3, [r7, #12]
- 80014f8: 6013 str r3, [r2, #0]
- HAL_UART_Transmit(&huart6, tx_buffer, 4, 100);
- 80014fa: 4b0d ldr r3, [pc, #52] ; (8001530 <HAL_TIM_PeriodElapsedCallback+0x1b8>)
- 80014fc: 6819 ldr r1, [r3, #0]
- 80014fe: 2364 movs r3, #100 ; 0x64
- 8001500: 2204 movs r2, #4
- 8001502: 480c ldr r0, [pc, #48] ; (8001534 <HAL_TIM_PeriodElapsedCallback+0x1bc>)
- 8001504: f003 f91a bl 800473c <HAL_UART_Transmit>
- }
-
- //TIMER 2Hz Transmit
- if (htim->Instance == TIM6) {
- }
-}
- 8001508: bf00 nop
- 800150a: 3710 adds r7, #16
- 800150c: 46bd mov sp, r7
- 800150e: bd80 pop {r7, pc}
- 8001510: 40000400 .word 0x40000400
- 8001514: 20000304 .word 0x20000304
- 8001518: 20000200 .word 0x20000200
- 800151c: 2000021c .word 0x2000021c
- 8001520: 200002f8 .word 0x200002f8
- 8001524: 20000224 .word 0x20000224
- 8001528: 2000029c .word 0x2000029c
- 800152c: 200002bc .word 0x200002bc
- 8001530: 200002d4 .word 0x200002d4
- 8001534: 2000016c .word 0x2000016c
- 8001538: 200001ec .word 0x200001ec
- 800153c: 20000220 .word 0x20000220
- 8001540: 20000248 .word 0x20000248
- 8001544: 200002a0 .word 0x200002a0
- 8001548: 200002a4 .word 0x200002a4
- 800154c: 2000026c .word 0x2000026c
-
-08001550 <HAL_UART_RxCpltCallback>:
-
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *UartHandle) {
- 8001550: b580 push {r7, lr}
- 8001552: b082 sub sp, #8
- 8001554: af00 add r7, sp, #0
- 8001556: 6078 str r0, [r7, #4]
-
- if (input_msg.pid_select == 1) {
- 8001558: 4b6b ldr r3, [pc, #428] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 800155a: edd3 7a00 vldr s15, [r3]
- 800155e: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0
- 8001562: eef4 7a47 vcmp.f32 s15, s14
- 8001566: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800156a: d11a bne.n 80015a2 <HAL_UART_RxCpltCallback+0x52>
-
- left_pid.config(input_msg.pid_kp, input_msg.pid_ki, input_msg.pid_kd);
- 800156c: 4b66 ldr r3, [pc, #408] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 800156e: edd3 7a04 vldr s15, [r3, #16]
- 8001572: 4b65 ldr r3, [pc, #404] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 8001574: ed93 7a05 vldr s14, [r3, #20]
- 8001578: 4b63 ldr r3, [pc, #396] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 800157a: edd3 6a06 vldr s13, [r3, #24]
- 800157e: eeb0 1a66 vmov.f32 s2, s13
- 8001582: eef0 0a47 vmov.f32 s1, s14
- 8001586: eeb0 0a67 vmov.f32 s0, s15
- 800158a: 4860 ldr r0, [pc, #384] ; (800170c <HAL_UART_RxCpltCallback+0x1bc>)
- 800158c: f7ff fa70 bl 8000a70 <_ZN3Pid6configEfff>
- left_pid.set(input_msg.pid_setpoint_fixed);
- 8001590: 4b5d ldr r3, [pc, #372] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 8001592: edd3 7a01 vldr s15, [r3, #4]
- 8001596: eeb0 0a67 vmov.f32 s0, s15
- 800159a: 485c ldr r0, [pc, #368] ; (800170c <HAL_UART_RxCpltCallback+0x1bc>)
- 800159c: f7ff fa91 bl 8000ac2 <_ZN3Pid3setEf>
-
- cross_setpoint = left_setpoint - right_setpoint;
- cross_pid.set(cross_setpoint);
- }
-
-}
- 80015a0: e0a8 b.n 80016f4 <HAL_UART_RxCpltCallback+0x1a4>
- } else if (input_msg.pid_select == 2) {
- 80015a2: 4b59 ldr r3, [pc, #356] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 80015a4: edd3 7a00 vldr s15, [r3]
- 80015a8: eeb0 7a00 vmov.f32 s14, #0 ; 0x40000000 2.0
- 80015ac: eef4 7a47 vcmp.f32 s15, s14
- 80015b0: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80015b4: d11a bne.n 80015ec <HAL_UART_RxCpltCallback+0x9c>
- right_pid.config(input_msg.pid_kp, input_msg.pid_ki, input_msg.pid_kd);
- 80015b6: 4b54 ldr r3, [pc, #336] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 80015b8: edd3 7a04 vldr s15, [r3, #16]
- 80015bc: 4b52 ldr r3, [pc, #328] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 80015be: ed93 7a05 vldr s14, [r3, #20]
- 80015c2: 4b51 ldr r3, [pc, #324] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 80015c4: edd3 6a06 vldr s13, [r3, #24]
- 80015c8: eeb0 1a66 vmov.f32 s2, s13
- 80015cc: eef0 0a47 vmov.f32 s1, s14
- 80015d0: eeb0 0a67 vmov.f32 s0, s15
- 80015d4: 484e ldr r0, [pc, #312] ; (8001710 <HAL_UART_RxCpltCallback+0x1c0>)
- 80015d6: f7ff fa4b bl 8000a70 <_ZN3Pid6configEfff>
- right_pid.set(input_msg.pid_setpoint_fixed);
- 80015da: 4b4b ldr r3, [pc, #300] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 80015dc: edd3 7a01 vldr s15, [r3, #4]
- 80015e0: eeb0 0a67 vmov.f32 s0, s15
- 80015e4: 484a ldr r0, [pc, #296] ; (8001710 <HAL_UART_RxCpltCallback+0x1c0>)
- 80015e6: f7ff fa6c bl 8000ac2 <_ZN3Pid3setEf>
-}
- 80015ea: e083 b.n 80016f4 <HAL_UART_RxCpltCallback+0x1a4>
- } else if (input_msg.pid_select == 3) {
- 80015ec: 4b46 ldr r3, [pc, #280] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 80015ee: edd3 7a00 vldr s15, [r3]
- 80015f2: eeb0 7a08 vmov.f32 s14, #8 ; 0x40400000 3.0
- 80015f6: eef4 7a47 vcmp.f32 s15, s14
- 80015fa: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80015fe: d179 bne.n 80016f4 <HAL_UART_RxCpltCallback+0x1a4>
- left_pid.config(180, 200, 0);
- 8001600: ed9f 1a44 vldr s2, [pc, #272] ; 8001714 <HAL_UART_RxCpltCallback+0x1c4>
- 8001604: eddf 0a44 vldr s1, [pc, #272] ; 8001718 <HAL_UART_RxCpltCallback+0x1c8>
- 8001608: ed9f 0a44 vldr s0, [pc, #272] ; 800171c <HAL_UART_RxCpltCallback+0x1cc>
- 800160c: 483f ldr r0, [pc, #252] ; (800170c <HAL_UART_RxCpltCallback+0x1bc>)
- 800160e: f7ff fa2f bl 8000a70 <_ZN3Pid6configEfff>
- right_pid.config(185, 195, 0);
- 8001612: ed9f 1a40 vldr s2, [pc, #256] ; 8001714 <HAL_UART_RxCpltCallback+0x1c4>
- 8001616: eddf 0a42 vldr s1, [pc, #264] ; 8001720 <HAL_UART_RxCpltCallback+0x1d0>
- 800161a: ed9f 0a42 vldr s0, [pc, #264] ; 8001724 <HAL_UART_RxCpltCallback+0x1d4>
- 800161e: 483c ldr r0, [pc, #240] ; (8001710 <HAL_UART_RxCpltCallback+0x1c0>)
- 8001620: f7ff fa26 bl 8000a70 <_ZN3Pid6configEfff>
- cross_pid.config(input_msg.pid_kp, input_msg.pid_ki, input_msg.pid_kd);
- 8001624: 4b38 ldr r3, [pc, #224] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 8001626: edd3 7a04 vldr s15, [r3, #16]
- 800162a: 4b37 ldr r3, [pc, #220] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 800162c: ed93 7a05 vldr s14, [r3, #20]
- 8001630: 4b35 ldr r3, [pc, #212] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 8001632: edd3 6a06 vldr s13, [r3, #24]
- 8001636: eeb0 1a66 vmov.f32 s2, s13
- 800163a: eef0 0a47 vmov.f32 s1, s14
- 800163e: eeb0 0a67 vmov.f32 s0, s15
- 8001642: 4839 ldr r0, [pc, #228] ; (8001728 <HAL_UART_RxCpltCallback+0x1d8>)
- 8001644: f7ff fa14 bl 8000a70 <_ZN3Pid6configEfff>
- odom.UpdateValues(input_msg.pid_setpoint_lin, input_msg.pid_setpoint_ang);
- 8001648: 4b2f ldr r3, [pc, #188] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 800164a: edd3 7a02 vldr s15, [r3, #8]
- 800164e: 4b2e ldr r3, [pc, #184] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 8001650: ed93 7a03 vldr s14, [r3, #12]
- 8001654: eef0 0a47 vmov.f32 s1, s14
- 8001658: eeb0 0a67 vmov.f32 s0, s15
- 800165c: 4833 ldr r0, [pc, #204] ; (800172c <HAL_UART_RxCpltCallback+0x1dc>)
- 800165e: f7ff f833 bl 80006c8 <_ZN8Odometry12UpdateValuesEff>
- left_setpoint = input_msg.pid_setpoint_lin
- 8001662: 4b29 ldr r3, [pc, #164] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 8001664: edd3 7a02 vldr s15, [r3, #8]
- 8001668: eeb7 6ae7 vcvt.f64.f32 d6, s15
- - (BASELINE * input_msg.pid_setpoint_ang) / 2;
- 800166c: 4b26 ldr r3, [pc, #152] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 800166e: edd3 7a03 vldr s15, [r3, #12]
- 8001672: eeb7 7ae7 vcvt.f64.f32 d7, s15
- 8001676: ed9f 5b22 vldr d5, [pc, #136] ; 8001700 <HAL_UART_RxCpltCallback+0x1b0>
- 800167a: ee27 5b05 vmul.f64 d5, d7, d5
- 800167e: eeb0 4b00 vmov.f64 d4, #0 ; 0x40000000 2.0
- 8001682: ee85 7b04 vdiv.f64 d7, d5, d4
- 8001686: ee36 7b47 vsub.f64 d7, d6, d7
- 800168a: eef7 7bc7 vcvt.f32.f64 s15, d7
- left_setpoint = input_msg.pid_setpoint_lin
- 800168e: 4b28 ldr r3, [pc, #160] ; (8001730 <HAL_UART_RxCpltCallback+0x1e0>)
- 8001690: edc3 7a00 vstr s15, [r3]
- right_setpoint = 2 * input_msg.pid_setpoint_lin - left_setpoint;
- 8001694: 4b1c ldr r3, [pc, #112] ; (8001708 <HAL_UART_RxCpltCallback+0x1b8>)
- 8001696: edd3 7a02 vldr s15, [r3, #8]
- 800169a: ee37 7aa7 vadd.f32 s14, s15, s15
- 800169e: 4b24 ldr r3, [pc, #144] ; (8001730 <HAL_UART_RxCpltCallback+0x1e0>)
- 80016a0: edd3 7a00 vldr s15, [r3]
- 80016a4: ee77 7a67 vsub.f32 s15, s14, s15
- 80016a8: 4b22 ldr r3, [pc, #136] ; (8001734 <HAL_UART_RxCpltCallback+0x1e4>)
- 80016aa: edc3 7a00 vstr s15, [r3]
- left_pid.set(left_setpoint);
- 80016ae: 4b20 ldr r3, [pc, #128] ; (8001730 <HAL_UART_RxCpltCallback+0x1e0>)
- 80016b0: edd3 7a00 vldr s15, [r3]
- 80016b4: eeb0 0a67 vmov.f32 s0, s15
- 80016b8: 4814 ldr r0, [pc, #80] ; (800170c <HAL_UART_RxCpltCallback+0x1bc>)
- 80016ba: f7ff fa02 bl 8000ac2 <_ZN3Pid3setEf>
- right_pid.set(right_setpoint);
- 80016be: 4b1d ldr r3, [pc, #116] ; (8001734 <HAL_UART_RxCpltCallback+0x1e4>)
- 80016c0: edd3 7a00 vldr s15, [r3]
- 80016c4: eeb0 0a67 vmov.f32 s0, s15
- 80016c8: 4811 ldr r0, [pc, #68] ; (8001710 <HAL_UART_RxCpltCallback+0x1c0>)
- 80016ca: f7ff f9fa bl 8000ac2 <_ZN3Pid3setEf>
- cross_setpoint = left_setpoint - right_setpoint;
- 80016ce: 4b18 ldr r3, [pc, #96] ; (8001730 <HAL_UART_RxCpltCallback+0x1e0>)
- 80016d0: ed93 7a00 vldr s14, [r3]
- 80016d4: 4b17 ldr r3, [pc, #92] ; (8001734 <HAL_UART_RxCpltCallback+0x1e4>)
- 80016d6: edd3 7a00 vldr s15, [r3]
- 80016da: ee77 7a67 vsub.f32 s15, s14, s15
- 80016de: 4b16 ldr r3, [pc, #88] ; (8001738 <HAL_UART_RxCpltCallback+0x1e8>)
- 80016e0: edc3 7a00 vstr s15, [r3]
- cross_pid.set(cross_setpoint);
- 80016e4: 4b14 ldr r3, [pc, #80] ; (8001738 <HAL_UART_RxCpltCallback+0x1e8>)
- 80016e6: edd3 7a00 vldr s15, [r3]
- 80016ea: eeb0 0a67 vmov.f32 s0, s15
- 80016ee: 480e ldr r0, [pc, #56] ; (8001728 <HAL_UART_RxCpltCallback+0x1d8>)
- 80016f0: f7ff f9e7 bl 8000ac2 <_ZN3Pid3setEf>
-}
- 80016f4: bf00 nop
- 80016f6: 3708 adds r7, #8
- 80016f8: 46bd mov sp, r7
- 80016fa: bd80 pop {r7, pc}
- 80016fc: f3af 8000 nop.w
- 8001700: 33333333 .word 0x33333333
- 8001704: 3fd33333 .word 0x3fd33333
- 8001708: 200002dc .word 0x200002dc
- 800170c: 20000224 .word 0x20000224
- 8001710: 20000248 .word 0x20000248
- 8001714: 00000000 .word 0x00000000
- 8001718: 43480000 .word 0x43480000
- 800171c: 43340000 .word 0x43340000
- 8001720: 43430000 .word 0x43430000
- 8001724: 43390000 .word 0x43390000
- 8001728: 2000026c .word 0x2000026c
- 800172c: 20000214 .word 0x20000214
- 8001730: 20000290 .word 0x20000290
- 8001734: 20000294 .word 0x20000294
- 8001738: 20000298 .word 0x20000298
-
-0800173c <HAL_GPIO_EXTI_Callback>:
-
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
- 800173c: b580 push {r7, lr}
- 800173e: b082 sub sp, #8
- 8001740: af00 add r7, sp, #0
- 8001742: 4603 mov r3, r0
- 8001744: 80fb strh r3, [r7, #6]
- //Blue user button
- if (GPIO_Pin == GPIO_PIN_13) {
- 8001746: 88fb ldrh r3, [r7, #6]
- 8001748: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 800174c: d12a bne.n 80017a4 <HAL_GPIO_EXTI_Callback+0x68>
- previous_millis = current_millis;
- 800174e: 4b17 ldr r3, [pc, #92] ; (80017ac <HAL_GPIO_EXTI_Callback+0x70>)
- 8001750: 681b ldr r3, [r3, #0]
- 8001752: 4a17 ldr r2, [pc, #92] ; (80017b0 <HAL_GPIO_EXTI_Callback+0x74>)
- 8001754: 6013 str r3, [r2, #0]
- current_millis = HAL_GetTick();
- 8001756: f000 fb37 bl 8001dc8 <HAL_GetTick>
- 800175a: 4603 mov r3, r0
- 800175c: 461a mov r2, r3
- 800175e: 4b13 ldr r3, [pc, #76] ; (80017ac <HAL_GPIO_EXTI_Callback+0x70>)
- 8001760: 601a str r2, [r3, #0]
- if (current_millis - previous_millis < 200)
- 8001762: 4b12 ldr r3, [pc, #72] ; (80017ac <HAL_GPIO_EXTI_Callback+0x70>)
- 8001764: 681a ldr r2, [r3, #0]
- 8001766: 4b12 ldr r3, [pc, #72] ; (80017b0 <HAL_GPIO_EXTI_Callback+0x74>)
- 8001768: 681b ldr r3, [r3, #0]
- 800176a: 1ad3 subs r3, r2, r3
- 800176c: 2bc7 cmp r3, #199 ; 0xc7
- 800176e: dc03 bgt.n 8001778 <HAL_GPIO_EXTI_Callback+0x3c>
- debounce = false;
- 8001770: 4b10 ldr r3, [pc, #64] ; (80017b4 <HAL_GPIO_EXTI_Callback+0x78>)
- 8001772: 2200 movs r2, #0
- 8001774: 701a strb r2, [r3, #0]
- 8001776: e002 b.n 800177e <HAL_GPIO_EXTI_Callback+0x42>
- else
- debounce = true;
- 8001778: 4b0e ldr r3, [pc, #56] ; (80017b4 <HAL_GPIO_EXTI_Callback+0x78>)
- 800177a: 2201 movs r2, #1
- 800177c: 701a strb r2, [r3, #0]
- if (mode == 0 && debounce) {
- 800177e: 4b0e ldr r3, [pc, #56] ; (80017b8 <HAL_GPIO_EXTI_Callback+0x7c>)
- 8001780: edd3 7a00 vldr s15, [r3]
- 8001784: eef5 7a40 vcmp.f32 s15, #0.0
- 8001788: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800178c: d10a bne.n 80017a4 <HAL_GPIO_EXTI_Callback+0x68>
- 800178e: 4b09 ldr r3, [pc, #36] ; (80017b4 <HAL_GPIO_EXTI_Callback+0x78>)
- 8001790: 781b ldrb r3, [r3, #0]
- 8001792: 2b00 cmp r3, #0
- 8001794: d006 beq.n 80017a4 <HAL_GPIO_EXTI_Callback+0x68>
- mode = input_msg.pid_select;
- 8001796: 4b09 ldr r3, [pc, #36] ; (80017bc <HAL_GPIO_EXTI_Callback+0x80>)
- 8001798: 681b ldr r3, [r3, #0]
- 800179a: 4a07 ldr r2, [pc, #28] ; (80017b8 <HAL_GPIO_EXTI_Callback+0x7c>)
- 800179c: 6013 str r3, [r2, #0]
- //Enables TIM3 interrupt (used for PID control)
- HAL_TIM_Base_Start_IT(&htim3);
- 800179e: 4808 ldr r0, [pc, #32] ; (80017c0 <HAL_GPIO_EXTI_Callback+0x84>)
- 80017a0: f001 fec0 bl 8003524 <HAL_TIM_Base_Start_IT>
- }
- }
-}
- 80017a4: bf00 nop
- 80017a6: 3708 adds r7, #8
- 80017a8: 46bd mov sp, r7
- 80017aa: bd80 pop {r7, pc}
- 80017ac: 20000300 .word 0x20000300
- 80017b0: 200002fc .word 0x200002fc
- 80017b4: 20000000 .word 0x20000000
- 80017b8: 20000304 .word 0x20000304
- 80017bc: 200002dc .word 0x200002dc
- 80017c0: 2000006c .word 0x2000006c
-
-080017c4 <Error_Handler>:
-/**
- * @brief This function is executed in case of error occurrence.
- * @retval None
- */
-void Error_Handler(void)
-{
- 80017c4: b480 push {r7}
- 80017c6: af00 add r7, sp, #0
- /* USER CODE BEGIN Error_Handler_Debug */
- /* User can add his own implementation to report the HAL error return state */
-
- /* USER CODE END Error_Handler_Debug */
-}
- 80017c8: bf00 nop
- 80017ca: 46bd mov sp, r7
- 80017cc: f85d 7b04 ldr.w r7, [sp], #4
- 80017d0: 4770 bx lr
- ...
-
-080017d4 <_Z41__static_initialization_and_destruction_0ii>:
- 80017d4: b580 push {r7, lr}
- 80017d6: b086 sub sp, #24
- 80017d8: af04 add r7, sp, #16
- 80017da: 6078 str r0, [r7, #4]
- 80017dc: 6039 str r1, [r7, #0]
- 80017de: 687b ldr r3, [r7, #4]
- 80017e0: 2b01 cmp r3, #1
- 80017e2: d14a bne.n 800187a <_Z41__static_initialization_and_destruction_0ii+0xa6>
- 80017e4: 683b ldr r3, [r7, #0]
- 80017e6: f64f 72ff movw r2, #65535 ; 0xffff
- 80017ea: 4293 cmp r3, r2
- 80017ec: d145 bne.n 800187a <_Z41__static_initialization_and_destruction_0ii+0xa6>
-Encoder right_encoder = Encoder(&htim5, RIGHT_WHEEL_CIRCUMFERENCE);
- 80017ee: ed9f 0a25 vldr s0, [pc, #148] ; 8001884 <_Z41__static_initialization_and_destruction_0ii+0xb0>
- 80017f2: 4925 ldr r1, [pc, #148] ; (8001888 <_Z41__static_initialization_and_destruction_0ii+0xb4>)
- 80017f4: 4825 ldr r0, [pc, #148] ; (800188c <_Z41__static_initialization_and_destruction_0ii+0xb8>)
- 80017f6: f7fe fec6 bl 8000586 <_ZN7EncoderC1EP17TIM_HandleTypeDeff>
-Encoder left_encoder = Encoder(&htim2, LEFT_WHEEL_CIRCUMFERENCE);
- 80017fa: ed9f 0a25 vldr s0, [pc, #148] ; 8001890 <_Z41__static_initialization_and_destruction_0ii+0xbc>
- 80017fe: 4925 ldr r1, [pc, #148] ; (8001894 <_Z41__static_initialization_and_destruction_0ii+0xc0>)
- 8001800: 4825 ldr r0, [pc, #148] ; (8001898 <_Z41__static_initialization_and_destruction_0ii+0xc4>)
- 8001802: f7fe fec0 bl 8000586 <_ZN7EncoderC1EP17TIM_HandleTypeDeff>
-Odometry odom = Odometry();
- 8001806: 4825 ldr r0, [pc, #148] ; (800189c <_Z41__static_initialization_and_destruction_0ii+0xc8>)
- 8001808: f7fe ff4a bl 80006a0 <_ZN8OdometryC1Ev>
-Pid left_pid(0, 0, 0);
- 800180c: ed9f 1a24 vldr s2, [pc, #144] ; 80018a0 <_Z41__static_initialization_and_destruction_0ii+0xcc>
- 8001810: eddf 0a23 vldr s1, [pc, #140] ; 80018a0 <_Z41__static_initialization_and_destruction_0ii+0xcc>
- 8001814: ed9f 0a22 vldr s0, [pc, #136] ; 80018a0 <_Z41__static_initialization_and_destruction_0ii+0xcc>
- 8001818: 4822 ldr r0, [pc, #136] ; (80018a4 <_Z41__static_initialization_and_destruction_0ii+0xd0>)
- 800181a: f7ff f8f5 bl 8000a08 <_ZN3PidC1Efff>
-Pid right_pid(0, 0, 0);
- 800181e: ed9f 1a20 vldr s2, [pc, #128] ; 80018a0 <_Z41__static_initialization_and_destruction_0ii+0xcc>
- 8001822: eddf 0a1f vldr s1, [pc, #124] ; 80018a0 <_Z41__static_initialization_and_destruction_0ii+0xcc>
- 8001826: ed9f 0a1e vldr s0, [pc, #120] ; 80018a0 <_Z41__static_initialization_and_destruction_0ii+0xcc>
- 800182a: 481f ldr r0, [pc, #124] ; (80018a8 <_Z41__static_initialization_and_destruction_0ii+0xd4>)
- 800182c: f7ff f8ec bl 8000a08 <_ZN3PidC1Efff>
-Pid cross_pid(0, 0, 0);
- 8001830: ed9f 1a1b vldr s2, [pc, #108] ; 80018a0 <_Z41__static_initialization_and_destruction_0ii+0xcc>
- 8001834: eddf 0a1a vldr s1, [pc, #104] ; 80018a0 <_Z41__static_initialization_and_destruction_0ii+0xcc>
- 8001838: ed9f 0a19 vldr s0, [pc, #100] ; 80018a0 <_Z41__static_initialization_and_destruction_0ii+0xcc>
- 800183c: 481b ldr r0, [pc, #108] ; (80018ac <_Z41__static_initialization_and_destruction_0ii+0xd8>)
- 800183e: f7ff f8e3 bl 8000a08 <_ZN3PidC1Efff>
- TIM_CHANNEL_4);
- 8001842: 230c movs r3, #12
- 8001844: 9302 str r3, [sp, #8]
- 8001846: 4b1a ldr r3, [pc, #104] ; (80018b0 <_Z41__static_initialization_and_destruction_0ii+0xdc>)
- 8001848: 9301 str r3, [sp, #4]
- 800184a: f44f 5300 mov.w r3, #8192 ; 0x2000
- 800184e: 9300 str r3, [sp, #0]
- 8001850: 4b18 ldr r3, [pc, #96] ; (80018b4 <_Z41__static_initialization_and_destruction_0ii+0xe0>)
- 8001852: f44f 4200 mov.w r2, #32768 ; 0x8000
- 8001856: 4917 ldr r1, [pc, #92] ; (80018b4 <_Z41__static_initialization_and_destruction_0ii+0xe0>)
- 8001858: 4817 ldr r0, [pc, #92] ; (80018b8 <_Z41__static_initialization_and_destruction_0ii+0xe4>)
- 800185a: f7fe ff6d bl 8000738 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>
- TIM_CHANNEL_3);
- 800185e: 2308 movs r3, #8
- 8001860: 9302 str r3, [sp, #8]
- 8001862: 4b13 ldr r3, [pc, #76] ; (80018b0 <_Z41__static_initialization_and_destruction_0ii+0xdc>)
- 8001864: 9301 str r3, [sp, #4]
- 8001866: f44f 5380 mov.w r3, #4096 ; 0x1000
- 800186a: 9300 str r3, [sp, #0]
- 800186c: 4b11 ldr r3, [pc, #68] ; (80018b4 <_Z41__static_initialization_and_destruction_0ii+0xe0>)
- 800186e: f44f 4280 mov.w r2, #16384 ; 0x4000
- 8001872: 4910 ldr r1, [pc, #64] ; (80018b4 <_Z41__static_initialization_and_destruction_0ii+0xe0>)
- 8001874: 4811 ldr r0, [pc, #68] ; (80018bc <_Z41__static_initialization_and_destruction_0ii+0xe8>)
- 8001876: f7fe ff5f bl 8000738 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>
-}
- 800187a: bf00 nop
- 800187c: 3708 adds r7, #8
- 800187e: 46bd mov sp, r7
- 8001880: bd80 pop {r7, pc}
- 8001882: bf00 nop
- 8001884: 3f4ccccd .word 0x3f4ccccd
- 8001888: 200000ec .word 0x200000ec
- 800188c: 200001ec .word 0x200001ec
- 8001890: 3f47ae14 .word 0x3f47ae14
- 8001894: 2000002c .word 0x2000002c
- 8001898: 20000200 .word 0x20000200
- 800189c: 20000214 .word 0x20000214
- 80018a0: 00000000 .word 0x00000000
- 80018a4: 20000224 .word 0x20000224
- 80018a8: 20000248 .word 0x20000248
- 80018ac: 2000026c .word 0x2000026c
- 80018b0: 200000ac .word 0x200000ac
- 80018b4: 40021400 .word 0x40021400
- 80018b8: 200002a4 .word 0x200002a4
- 80018bc: 200002bc .word 0x200002bc
-
-080018c0 <_GLOBAL__sub_I_htim2>:
- 80018c0: b580 push {r7, lr}
- 80018c2: af00 add r7, sp, #0
- 80018c4: f64f 71ff movw r1, #65535 ; 0xffff
- 80018c8: 2001 movs r0, #1
- 80018ca: f7ff ff83 bl 80017d4 <_Z41__static_initialization_and_destruction_0ii>
- 80018ce: bd80 pop {r7, pc}
-
-080018d0 <HAL_MspInit>:
-void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
- /**
- * Initializes the Global MSP.
- */
-void HAL_MspInit(void)
-{
- 80018d0: b480 push {r7}
- 80018d2: b083 sub sp, #12
- 80018d4: af00 add r7, sp, #0
- /* USER CODE BEGIN MspInit 0 */
-
- /* USER CODE END MspInit 0 */
-
- __HAL_RCC_PWR_CLK_ENABLE();
- 80018d6: 4b0f ldr r3, [pc, #60] ; (8001914 <HAL_MspInit+0x44>)
- 80018d8: 6c1b ldr r3, [r3, #64] ; 0x40
- 80018da: 4a0e ldr r2, [pc, #56] ; (8001914 <HAL_MspInit+0x44>)
- 80018dc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 80018e0: 6413 str r3, [r2, #64] ; 0x40
- 80018e2: 4b0c ldr r3, [pc, #48] ; (8001914 <HAL_MspInit+0x44>)
- 80018e4: 6c1b ldr r3, [r3, #64] ; 0x40
- 80018e6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80018ea: 607b str r3, [r7, #4]
- 80018ec: 687b ldr r3, [r7, #4]
- __HAL_RCC_SYSCFG_CLK_ENABLE();
- 80018ee: 4b09 ldr r3, [pc, #36] ; (8001914 <HAL_MspInit+0x44>)
- 80018f0: 6c5b ldr r3, [r3, #68] ; 0x44
- 80018f2: 4a08 ldr r2, [pc, #32] ; (8001914 <HAL_MspInit+0x44>)
- 80018f4: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 80018f8: 6453 str r3, [r2, #68] ; 0x44
- 80018fa: 4b06 ldr r3, [pc, #24] ; (8001914 <HAL_MspInit+0x44>)
- 80018fc: 6c5b ldr r3, [r3, #68] ; 0x44
- 80018fe: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 8001902: 603b str r3, [r7, #0]
- 8001904: 683b ldr r3, [r7, #0]
- /* System interrupt init*/
-
- /* USER CODE BEGIN MspInit 1 */
-
- /* USER CODE END MspInit 1 */
-}
- 8001906: bf00 nop
- 8001908: 370c adds r7, #12
- 800190a: 46bd mov sp, r7
- 800190c: f85d 7b04 ldr.w r7, [sp], #4
- 8001910: 4770 bx lr
- 8001912: bf00 nop
- 8001914: 40023800 .word 0x40023800
-
-08001918 <HAL_TIM_Encoder_MspInit>:
-* This function configures the hardware resources used in this example
-* @param htim_encoder: TIM_Encoder handle pointer
-* @retval None
-*/
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
-{
- 8001918: b580 push {r7, lr}
- 800191a: b08c sub sp, #48 ; 0x30
- 800191c: af00 add r7, sp, #0
- 800191e: 6078 str r0, [r7, #4]
- GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8001920: f107 031c add.w r3, r7, #28
- 8001924: 2200 movs r2, #0
- 8001926: 601a str r2, [r3, #0]
- 8001928: 605a str r2, [r3, #4]
- 800192a: 609a str r2, [r3, #8]
- 800192c: 60da str r2, [r3, #12]
- 800192e: 611a str r2, [r3, #16]
- if(htim_encoder->Instance==TIM2)
- 8001930: 687b ldr r3, [r7, #4]
- 8001932: 681b ldr r3, [r3, #0]
- 8001934: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 8001938: d144 bne.n 80019c4 <HAL_TIM_Encoder_MspInit+0xac>
- {
- /* USER CODE BEGIN TIM2_MspInit 0 */
-
- /* USER CODE END TIM2_MspInit 0 */
- /* Peripheral clock enable */
- __HAL_RCC_TIM2_CLK_ENABLE();
- 800193a: 4b3b ldr r3, [pc, #236] ; (8001a28 <HAL_TIM_Encoder_MspInit+0x110>)
- 800193c: 6c1b ldr r3, [r3, #64] ; 0x40
- 800193e: 4a3a ldr r2, [pc, #232] ; (8001a28 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001940: f043 0301 orr.w r3, r3, #1
- 8001944: 6413 str r3, [r2, #64] ; 0x40
- 8001946: 4b38 ldr r3, [pc, #224] ; (8001a28 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001948: 6c1b ldr r3, [r3, #64] ; 0x40
- 800194a: f003 0301 and.w r3, r3, #1
- 800194e: 61bb str r3, [r7, #24]
- 8001950: 69bb ldr r3, [r7, #24]
-
- __HAL_RCC_GPIOA_CLK_ENABLE();
- 8001952: 4b35 ldr r3, [pc, #212] ; (8001a28 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001954: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001956: 4a34 ldr r2, [pc, #208] ; (8001a28 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001958: f043 0301 orr.w r3, r3, #1
- 800195c: 6313 str r3, [r2, #48] ; 0x30
- 800195e: 4b32 ldr r3, [pc, #200] ; (8001a28 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001960: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001962: f003 0301 and.w r3, r3, #1
- 8001966: 617b str r3, [r7, #20]
- 8001968: 697b ldr r3, [r7, #20]
- __HAL_RCC_GPIOB_CLK_ENABLE();
- 800196a: 4b2f ldr r3, [pc, #188] ; (8001a28 <HAL_TIM_Encoder_MspInit+0x110>)
- 800196c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800196e: 4a2e ldr r2, [pc, #184] ; (8001a28 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001970: f043 0302 orr.w r3, r3, #2
- 8001974: 6313 str r3, [r2, #48] ; 0x30
- 8001976: 4b2c ldr r3, [pc, #176] ; (8001a28 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001978: 6b1b ldr r3, [r3, #48] ; 0x30
- 800197a: f003 0302 and.w r3, r3, #2
- 800197e: 613b str r3, [r7, #16]
- 8001980: 693b ldr r3, [r7, #16]
- /**TIM2 GPIO Configuration
- PA5 ------> TIM2_CH1
- PB3 ------> TIM2_CH2
- */
- GPIO_InitStruct.Pin = encoder_sx1_Pin;
- 8001982: 2320 movs r3, #32
- 8001984: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8001986: 2302 movs r3, #2
- 8001988: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 800198a: 2300 movs r3, #0
- 800198c: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 800198e: 2300 movs r3, #0
- 8001990: 62bb str r3, [r7, #40] ; 0x28
- GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
- 8001992: 2301 movs r3, #1
- 8001994: 62fb str r3, [r7, #44] ; 0x2c
- HAL_GPIO_Init(encoder_sx1_GPIO_Port, &GPIO_InitStruct);
- 8001996: f107 031c add.w r3, r7, #28
- 800199a: 4619 mov r1, r3
- 800199c: 4823 ldr r0, [pc, #140] ; (8001a2c <HAL_TIM_Encoder_MspInit+0x114>)
- 800199e: f000 fb53 bl 8002048 <HAL_GPIO_Init>
-
- GPIO_InitStruct.Pin = encoder_sx2_Pin;
- 80019a2: 2308 movs r3, #8
- 80019a4: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 80019a6: 2302 movs r3, #2
- 80019a8: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80019aa: 2300 movs r3, #0
- 80019ac: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 80019ae: 2300 movs r3, #0
- 80019b0: 62bb str r3, [r7, #40] ; 0x28
- GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
- 80019b2: 2301 movs r3, #1
- 80019b4: 62fb str r3, [r7, #44] ; 0x2c
- HAL_GPIO_Init(encoder_sx2_GPIO_Port, &GPIO_InitStruct);
- 80019b6: f107 031c add.w r3, r7, #28
- 80019ba: 4619 mov r1, r3
- 80019bc: 481c ldr r0, [pc, #112] ; (8001a30 <HAL_TIM_Encoder_MspInit+0x118>)
- 80019be: f000 fb43 bl 8002048 <HAL_GPIO_Init>
- /* USER CODE BEGIN TIM5_MspInit 1 */
-
- /* USER CODE END TIM5_MspInit 1 */
- }
-
-}
- 80019c2: e02c b.n 8001a1e <HAL_TIM_Encoder_MspInit+0x106>
- else if(htim_encoder->Instance==TIM5)
- 80019c4: 687b ldr r3, [r7, #4]
- 80019c6: 681b ldr r3, [r3, #0]
- 80019c8: 4a1a ldr r2, [pc, #104] ; (8001a34 <HAL_TIM_Encoder_MspInit+0x11c>)
- 80019ca: 4293 cmp r3, r2
- 80019cc: d127 bne.n 8001a1e <HAL_TIM_Encoder_MspInit+0x106>
- __HAL_RCC_TIM5_CLK_ENABLE();
- 80019ce: 4b16 ldr r3, [pc, #88] ; (8001a28 <HAL_TIM_Encoder_MspInit+0x110>)
- 80019d0: 6c1b ldr r3, [r3, #64] ; 0x40
- 80019d2: 4a15 ldr r2, [pc, #84] ; (8001a28 <HAL_TIM_Encoder_MspInit+0x110>)
- 80019d4: f043 0308 orr.w r3, r3, #8
- 80019d8: 6413 str r3, [r2, #64] ; 0x40
- 80019da: 4b13 ldr r3, [pc, #76] ; (8001a28 <HAL_TIM_Encoder_MspInit+0x110>)
- 80019dc: 6c1b ldr r3, [r3, #64] ; 0x40
- 80019de: f003 0308 and.w r3, r3, #8
- 80019e2: 60fb str r3, [r7, #12]
- 80019e4: 68fb ldr r3, [r7, #12]
- __HAL_RCC_GPIOA_CLK_ENABLE();
- 80019e6: 4b10 ldr r3, [pc, #64] ; (8001a28 <HAL_TIM_Encoder_MspInit+0x110>)
- 80019e8: 6b1b ldr r3, [r3, #48] ; 0x30
- 80019ea: 4a0f ldr r2, [pc, #60] ; (8001a28 <HAL_TIM_Encoder_MspInit+0x110>)
- 80019ec: f043 0301 orr.w r3, r3, #1
- 80019f0: 6313 str r3, [r2, #48] ; 0x30
- 80019f2: 4b0d ldr r3, [pc, #52] ; (8001a28 <HAL_TIM_Encoder_MspInit+0x110>)
- 80019f4: 6b1b ldr r3, [r3, #48] ; 0x30
- 80019f6: f003 0301 and.w r3, r3, #1
- 80019fa: 60bb str r3, [r7, #8]
- 80019fc: 68bb ldr r3, [r7, #8]
- GPIO_InitStruct.Pin = encoder_dx1_Pin|encoder_dx2_Pin;
- 80019fe: 2303 movs r3, #3
- 8001a00: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8001a02: 2302 movs r3, #2
- 8001a04: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001a06: 2300 movs r3, #0
- 8001a08: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001a0a: 2300 movs r3, #0
- 8001a0c: 62bb str r3, [r7, #40] ; 0x28
- GPIO_InitStruct.Alternate = GPIO_AF2_TIM5;
- 8001a0e: 2302 movs r3, #2
- 8001a10: 62fb str r3, [r7, #44] ; 0x2c
- HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 8001a12: f107 031c add.w r3, r7, #28
- 8001a16: 4619 mov r1, r3
- 8001a18: 4804 ldr r0, [pc, #16] ; (8001a2c <HAL_TIM_Encoder_MspInit+0x114>)
- 8001a1a: f000 fb15 bl 8002048 <HAL_GPIO_Init>
-}
- 8001a1e: bf00 nop
- 8001a20: 3730 adds r7, #48 ; 0x30
- 8001a22: 46bd mov sp, r7
- 8001a24: bd80 pop {r7, pc}
- 8001a26: bf00 nop
- 8001a28: 40023800 .word 0x40023800
- 8001a2c: 40020000 .word 0x40020000
- 8001a30: 40020400 .word 0x40020400
- 8001a34: 40000c00 .word 0x40000c00
-
-08001a38 <HAL_TIM_Base_MspInit>:
-* This function configures the hardware resources used in this example
-* @param htim_base: TIM_Base handle pointer
-* @retval None
-*/
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
-{
- 8001a38: b480 push {r7}
- 8001a3a: b087 sub sp, #28
- 8001a3c: af00 add r7, sp, #0
- 8001a3e: 6078 str r0, [r7, #4]
- if(htim_base->Instance==TIM3)
- 8001a40: 687b ldr r3, [r7, #4]
- 8001a42: 681b ldr r3, [r3, #0]
- 8001a44: 4a1c ldr r2, [pc, #112] ; (8001ab8 <HAL_TIM_Base_MspInit+0x80>)
- 8001a46: 4293 cmp r3, r2
- 8001a48: d10c bne.n 8001a64 <HAL_TIM_Base_MspInit+0x2c>
- {
- /* USER CODE BEGIN TIM3_MspInit 0 */
-
- /* USER CODE END TIM3_MspInit 0 */
- /* Peripheral clock enable */
- __HAL_RCC_TIM3_CLK_ENABLE();
- 8001a4a: 4b1c ldr r3, [pc, #112] ; (8001abc <HAL_TIM_Base_MspInit+0x84>)
- 8001a4c: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001a4e: 4a1b ldr r2, [pc, #108] ; (8001abc <HAL_TIM_Base_MspInit+0x84>)
- 8001a50: f043 0302 orr.w r3, r3, #2
- 8001a54: 6413 str r3, [r2, #64] ; 0x40
- 8001a56: 4b19 ldr r3, [pc, #100] ; (8001abc <HAL_TIM_Base_MspInit+0x84>)
- 8001a58: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001a5a: f003 0302 and.w r3, r3, #2
- 8001a5e: 617b str r3, [r7, #20]
- 8001a60: 697b ldr r3, [r7, #20]
- /* USER CODE BEGIN TIM6_MspInit 1 */
-
- /* USER CODE END TIM6_MspInit 1 */
- }
-
-}
- 8001a62: e022 b.n 8001aaa <HAL_TIM_Base_MspInit+0x72>
- else if(htim_base->Instance==TIM4)
- 8001a64: 687b ldr r3, [r7, #4]
- 8001a66: 681b ldr r3, [r3, #0]
- 8001a68: 4a15 ldr r2, [pc, #84] ; (8001ac0 <HAL_TIM_Base_MspInit+0x88>)
- 8001a6a: 4293 cmp r3, r2
- 8001a6c: d10c bne.n 8001a88 <HAL_TIM_Base_MspInit+0x50>
- __HAL_RCC_TIM4_CLK_ENABLE();
- 8001a6e: 4b13 ldr r3, [pc, #76] ; (8001abc <HAL_TIM_Base_MspInit+0x84>)
- 8001a70: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001a72: 4a12 ldr r2, [pc, #72] ; (8001abc <HAL_TIM_Base_MspInit+0x84>)
- 8001a74: f043 0304 orr.w r3, r3, #4
- 8001a78: 6413 str r3, [r2, #64] ; 0x40
- 8001a7a: 4b10 ldr r3, [pc, #64] ; (8001abc <HAL_TIM_Base_MspInit+0x84>)
- 8001a7c: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001a7e: f003 0304 and.w r3, r3, #4
- 8001a82: 613b str r3, [r7, #16]
- 8001a84: 693b ldr r3, [r7, #16]
-}
- 8001a86: e010 b.n 8001aaa <HAL_TIM_Base_MspInit+0x72>
- else if(htim_base->Instance==TIM6)
- 8001a88: 687b ldr r3, [r7, #4]
- 8001a8a: 681b ldr r3, [r3, #0]
- 8001a8c: 4a0d ldr r2, [pc, #52] ; (8001ac4 <HAL_TIM_Base_MspInit+0x8c>)
- 8001a8e: 4293 cmp r3, r2
- 8001a90: d10b bne.n 8001aaa <HAL_TIM_Base_MspInit+0x72>
- __HAL_RCC_TIM6_CLK_ENABLE();
- 8001a92: 4b0a ldr r3, [pc, #40] ; (8001abc <HAL_TIM_Base_MspInit+0x84>)
- 8001a94: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001a96: 4a09 ldr r2, [pc, #36] ; (8001abc <HAL_TIM_Base_MspInit+0x84>)
- 8001a98: f043 0310 orr.w r3, r3, #16
- 8001a9c: 6413 str r3, [r2, #64] ; 0x40
- 8001a9e: 4b07 ldr r3, [pc, #28] ; (8001abc <HAL_TIM_Base_MspInit+0x84>)
- 8001aa0: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001aa2: f003 0310 and.w r3, r3, #16
- 8001aa6: 60fb str r3, [r7, #12]
- 8001aa8: 68fb ldr r3, [r7, #12]
-}
- 8001aaa: bf00 nop
- 8001aac: 371c adds r7, #28
- 8001aae: 46bd mov sp, r7
- 8001ab0: f85d 7b04 ldr.w r7, [sp], #4
- 8001ab4: 4770 bx lr
- 8001ab6: bf00 nop
- 8001ab8: 40000400 .word 0x40000400
- 8001abc: 40023800 .word 0x40023800
- 8001ac0: 40000800 .word 0x40000800
- 8001ac4: 40001000 .word 0x40001000
-
-08001ac8 <HAL_TIM_MspPostInit>:
-
-void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
-{
- 8001ac8: b580 push {r7, lr}
- 8001aca: b088 sub sp, #32
- 8001acc: af00 add r7, sp, #0
- 8001ace: 6078 str r0, [r7, #4]
- GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8001ad0: f107 030c add.w r3, r7, #12
- 8001ad4: 2200 movs r2, #0
- 8001ad6: 601a str r2, [r3, #0]
- 8001ad8: 605a str r2, [r3, #4]
- 8001ada: 609a str r2, [r3, #8]
- 8001adc: 60da str r2, [r3, #12]
- 8001ade: 611a str r2, [r3, #16]
- if(htim->Instance==TIM4)
- 8001ae0: 687b ldr r3, [r7, #4]
- 8001ae2: 681b ldr r3, [r3, #0]
- 8001ae4: 4a11 ldr r2, [pc, #68] ; (8001b2c <HAL_TIM_MspPostInit+0x64>)
- 8001ae6: 4293 cmp r3, r2
- 8001ae8: d11c bne.n 8001b24 <HAL_TIM_MspPostInit+0x5c>
- {
- /* USER CODE BEGIN TIM4_MspPostInit 0 */
-
- /* USER CODE END TIM4_MspPostInit 0 */
-
- __HAL_RCC_GPIOD_CLK_ENABLE();
- 8001aea: 4b11 ldr r3, [pc, #68] ; (8001b30 <HAL_TIM_MspPostInit+0x68>)
- 8001aec: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001aee: 4a10 ldr r2, [pc, #64] ; (8001b30 <HAL_TIM_MspPostInit+0x68>)
- 8001af0: f043 0308 orr.w r3, r3, #8
- 8001af4: 6313 str r3, [r2, #48] ; 0x30
- 8001af6: 4b0e ldr r3, [pc, #56] ; (8001b30 <HAL_TIM_MspPostInit+0x68>)
- 8001af8: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001afa: f003 0308 and.w r3, r3, #8
- 8001afe: 60bb str r3, [r7, #8]
- 8001b00: 68bb ldr r3, [r7, #8]
- /**TIM4 GPIO Configuration
- PD14 ------> TIM4_CH3
- PD15 ------> TIM4_CH4
- */
- GPIO_InitStruct.Pin = pwm2_Pin|pwm1_Pin;
- 8001b02: f44f 4340 mov.w r3, #49152 ; 0xc000
- 8001b06: 60fb str r3, [r7, #12]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8001b08: 2302 movs r3, #2
- 8001b0a: 613b str r3, [r7, #16]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001b0c: 2300 movs r3, #0
- 8001b0e: 617b str r3, [r7, #20]
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001b10: 2300 movs r3, #0
- 8001b12: 61bb str r3, [r7, #24]
- GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
- 8001b14: 2302 movs r3, #2
- 8001b16: 61fb str r3, [r7, #28]
- HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
- 8001b18: f107 030c add.w r3, r7, #12
- 8001b1c: 4619 mov r1, r3
- 8001b1e: 4805 ldr r0, [pc, #20] ; (8001b34 <HAL_TIM_MspPostInit+0x6c>)
- 8001b20: f000 fa92 bl 8002048 <HAL_GPIO_Init>
- /* USER CODE BEGIN TIM4_MspPostInit 1 */
-
- /* USER CODE END TIM4_MspPostInit 1 */
- }
-
-}
- 8001b24: bf00 nop
- 8001b26: 3720 adds r7, #32
- 8001b28: 46bd mov sp, r7
- 8001b2a: bd80 pop {r7, pc}
- 8001b2c: 40000800 .word 0x40000800
- 8001b30: 40023800 .word 0x40023800
- 8001b34: 40020c00 .word 0x40020c00
-
-08001b38 <HAL_UART_MspInit>:
-* This function configures the hardware resources used in this example
-* @param huart: UART handle pointer
-* @retval None
-*/
-void HAL_UART_MspInit(UART_HandleTypeDef* huart)
-{
- 8001b38: b580 push {r7, lr}
- 8001b3a: b08a sub sp, #40 ; 0x28
- 8001b3c: af00 add r7, sp, #0
- 8001b3e: 6078 str r0, [r7, #4]
- GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8001b40: f107 0314 add.w r3, r7, #20
- 8001b44: 2200 movs r2, #0
- 8001b46: 601a str r2, [r3, #0]
- 8001b48: 605a str r2, [r3, #4]
- 8001b4a: 609a str r2, [r3, #8]
- 8001b4c: 60da str r2, [r3, #12]
- 8001b4e: 611a str r2, [r3, #16]
- if(huart->Instance==USART6)
- 8001b50: 687b ldr r3, [r7, #4]
- 8001b52: 681b ldr r3, [r3, #0]
- 8001b54: 4a17 ldr r2, [pc, #92] ; (8001bb4 <HAL_UART_MspInit+0x7c>)
- 8001b56: 4293 cmp r3, r2
- 8001b58: d127 bne.n 8001baa <HAL_UART_MspInit+0x72>
- {
- /* USER CODE BEGIN USART6_MspInit 0 */
-
- /* USER CODE END USART6_MspInit 0 */
- /* Peripheral clock enable */
- __HAL_RCC_USART6_CLK_ENABLE();
- 8001b5a: 4b17 ldr r3, [pc, #92] ; (8001bb8 <HAL_UART_MspInit+0x80>)
- 8001b5c: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001b5e: 4a16 ldr r2, [pc, #88] ; (8001bb8 <HAL_UART_MspInit+0x80>)
- 8001b60: f043 0320 orr.w r3, r3, #32
- 8001b64: 6453 str r3, [r2, #68] ; 0x44
- 8001b66: 4b14 ldr r3, [pc, #80] ; (8001bb8 <HAL_UART_MspInit+0x80>)
- 8001b68: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001b6a: f003 0320 and.w r3, r3, #32
- 8001b6e: 613b str r3, [r7, #16]
- 8001b70: 693b ldr r3, [r7, #16]
-
- __HAL_RCC_GPIOC_CLK_ENABLE();
- 8001b72: 4b11 ldr r3, [pc, #68] ; (8001bb8 <HAL_UART_MspInit+0x80>)
- 8001b74: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001b76: 4a10 ldr r2, [pc, #64] ; (8001bb8 <HAL_UART_MspInit+0x80>)
- 8001b78: f043 0304 orr.w r3, r3, #4
- 8001b7c: 6313 str r3, [r2, #48] ; 0x30
- 8001b7e: 4b0e ldr r3, [pc, #56] ; (8001bb8 <HAL_UART_MspInit+0x80>)
- 8001b80: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001b82: f003 0304 and.w r3, r3, #4
- 8001b86: 60fb str r3, [r7, #12]
- 8001b88: 68fb ldr r3, [r7, #12]
- /**USART6 GPIO Configuration
- PC6 ------> USART6_TX
- PC7 ------> USART6_RX
- */
- GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
- 8001b8a: 23c0 movs r3, #192 ; 0xc0
- 8001b8c: 617b str r3, [r7, #20]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8001b8e: 2302 movs r3, #2
- 8001b90: 61bb str r3, [r7, #24]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001b92: 2300 movs r3, #0
- 8001b94: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- 8001b96: 2303 movs r3, #3
- 8001b98: 623b str r3, [r7, #32]
- GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
- 8001b9a: 2308 movs r3, #8
- 8001b9c: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
- 8001b9e: f107 0314 add.w r3, r7, #20
- 8001ba2: 4619 mov r1, r3
- 8001ba4: 4805 ldr r0, [pc, #20] ; (8001bbc <HAL_UART_MspInit+0x84>)
- 8001ba6: f000 fa4f bl 8002048 <HAL_GPIO_Init>
- /* USER CODE BEGIN USART6_MspInit 1 */
-
- /* USER CODE END USART6_MspInit 1 */
- }
-
-}
- 8001baa: bf00 nop
- 8001bac: 3728 adds r7, #40 ; 0x28
- 8001bae: 46bd mov sp, r7
- 8001bb0: bd80 pop {r7, pc}
- 8001bb2: bf00 nop
- 8001bb4: 40011400 .word 0x40011400
- 8001bb8: 40023800 .word 0x40023800
- 8001bbc: 40020800 .word 0x40020800
-
-08001bc0 <NMI_Handler>:
-/******************************************************************************/
-/**
- * @brief This function handles Non maskable interrupt.
- */
-void NMI_Handler(void)
-{
- 8001bc0: b480 push {r7}
- 8001bc2: af00 add r7, sp, #0
-
- /* USER CODE END NonMaskableInt_IRQn 0 */
- /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
-
- /* USER CODE END NonMaskableInt_IRQn 1 */
-}
- 8001bc4: bf00 nop
- 8001bc6: 46bd mov sp, r7
- 8001bc8: f85d 7b04 ldr.w r7, [sp], #4
- 8001bcc: 4770 bx lr
-
-08001bce <HardFault_Handler>:
-
-/**
- * @brief This function handles Hard fault interrupt.
- */
-void HardFault_Handler(void)
-{
- 8001bce: b480 push {r7}
- 8001bd0: af00 add r7, sp, #0
- /* USER CODE BEGIN HardFault_IRQn 0 */
-
- /* USER CODE END HardFault_IRQn 0 */
- while (1)
- 8001bd2: e7fe b.n 8001bd2 <HardFault_Handler+0x4>
-
-08001bd4 <MemManage_Handler>:
-
-/**
- * @brief This function handles Memory management fault.
- */
-void MemManage_Handler(void)
-{
- 8001bd4: b480 push {r7}
- 8001bd6: af00 add r7, sp, #0
- /* USER CODE BEGIN MemoryManagement_IRQn 0 */
-
- /* USER CODE END MemoryManagement_IRQn 0 */
- while (1)
- 8001bd8: e7fe b.n 8001bd8 <MemManage_Handler+0x4>
-
-08001bda <BusFault_Handler>:
-
-/**
- * @brief This function handles Pre-fetch fault, memory access fault.
- */
-void BusFault_Handler(void)
-{
- 8001bda: b480 push {r7}
- 8001bdc: af00 add r7, sp, #0
- /* USER CODE BEGIN BusFault_IRQn 0 */
-
- /* USER CODE END BusFault_IRQn 0 */
- while (1)
- 8001bde: e7fe b.n 8001bde <BusFault_Handler+0x4>
-
-08001be0 <UsageFault_Handler>:
-
-/**
- * @brief This function handles Undefined instruction or illegal state.
- */
-void UsageFault_Handler(void)
-{
- 8001be0: b480 push {r7}
- 8001be2: af00 add r7, sp, #0
- /* USER CODE BEGIN UsageFault_IRQn 0 */
-
- /* USER CODE END UsageFault_IRQn 0 */
- while (1)
- 8001be4: e7fe b.n 8001be4 <UsageFault_Handler+0x4>
-
-08001be6 <SVC_Handler>:
-
-/**
- * @brief This function handles System service call via SWI instruction.
- */
-void SVC_Handler(void)
-{
- 8001be6: b480 push {r7}
- 8001be8: af00 add r7, sp, #0
-
- /* USER CODE END SVCall_IRQn 0 */
- /* USER CODE BEGIN SVCall_IRQn 1 */
-
- /* USER CODE END SVCall_IRQn 1 */
-}
- 8001bea: bf00 nop
- 8001bec: 46bd mov sp, r7
- 8001bee: f85d 7b04 ldr.w r7, [sp], #4
- 8001bf2: 4770 bx lr
-
-08001bf4 <DebugMon_Handler>:
-
-/**
- * @brief This function handles Debug monitor.
- */
-void DebugMon_Handler(void)
-{
- 8001bf4: b480 push {r7}
- 8001bf6: af00 add r7, sp, #0
-
- /* USER CODE END DebugMonitor_IRQn 0 */
- /* USER CODE BEGIN DebugMonitor_IRQn 1 */
-
- /* USER CODE END DebugMonitor_IRQn 1 */
-}
- 8001bf8: bf00 nop
- 8001bfa: 46bd mov sp, r7
- 8001bfc: f85d 7b04 ldr.w r7, [sp], #4
- 8001c00: 4770 bx lr
-
-08001c02 <PendSV_Handler>:
-
-/**
- * @brief This function handles Pendable request for system service.
- */
-void PendSV_Handler(void)
-{
- 8001c02: b480 push {r7}
- 8001c04: af00 add r7, sp, #0
-
- /* USER CODE END PendSV_IRQn 0 */
- /* USER CODE BEGIN PendSV_IRQn 1 */
-
- /* USER CODE END PendSV_IRQn 1 */
-}
- 8001c06: bf00 nop
- 8001c08: 46bd mov sp, r7
- 8001c0a: f85d 7b04 ldr.w r7, [sp], #4
- 8001c0e: 4770 bx lr
-
-08001c10 <SysTick_Handler>:
-
-/**
- * @brief This function handles System tick timer.
- */
-void SysTick_Handler(void)
-{
- 8001c10: b580 push {r7, lr}
- 8001c12: af00 add r7, sp, #0
- /* USER CODE BEGIN SysTick_IRQn 0 */
-
- /* USER CODE END SysTick_IRQn 0 */
- HAL_IncTick();
- 8001c14: f000 f8c4 bl 8001da0 <HAL_IncTick>
- /* USER CODE BEGIN SysTick_IRQn 1 */
-
- /* USER CODE END SysTick_IRQn 1 */
-}
- 8001c18: bf00 nop
- 8001c1a: bd80 pop {r7, pc}
-
-08001c1c <TIM3_IRQHandler>:
-
-/**
- * @brief This function handles TIM3 global interrupt.
- */
-void TIM3_IRQHandler(void)
-{
- 8001c1c: b580 push {r7, lr}
- 8001c1e: af00 add r7, sp, #0
- /* USER CODE BEGIN TIM3_IRQn 0 */
-
- /* USER CODE END TIM3_IRQn 0 */
- HAL_TIM_IRQHandler(&htim3);
- 8001c20: 4802 ldr r0, [pc, #8] ; (8001c2c <TIM3_IRQHandler+0x10>)
- 8001c22: f001 fdec bl 80037fe <HAL_TIM_IRQHandler>
- /* USER CODE BEGIN TIM3_IRQn 1 */
-
- /* USER CODE END TIM3_IRQn 1 */
-}
- 8001c26: bf00 nop
- 8001c28: bd80 pop {r7, pc}
- 8001c2a: bf00 nop
- 8001c2c: 2000006c .word 0x2000006c
-
-08001c30 <EXTI15_10_IRQHandler>:
-
-/**
- * @brief This function handles EXTI line[15:10] interrupts.
- */
-void EXTI15_10_IRQHandler(void)
-{
- 8001c30: b580 push {r7, lr}
- 8001c32: af00 add r7, sp, #0
- /* USER CODE BEGIN EXTI15_10_IRQn 0 */
-
- /* USER CODE END EXTI15_10_IRQn 0 */
- HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
- 8001c34: f44f 5000 mov.w r0, #8192 ; 0x2000
- 8001c38: f000 fbca bl 80023d0 <HAL_GPIO_EXTI_IRQHandler>
- /* USER CODE BEGIN EXTI15_10_IRQn 1 */
-
- /* USER CODE END EXTI15_10_IRQn 1 */
-}
- 8001c3c: bf00 nop
- 8001c3e: bd80 pop {r7, pc}
-
-08001c40 <TIM6_DAC_IRQHandler>:
-
-/**
- * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
- */
-void TIM6_DAC_IRQHandler(void)
-{
- 8001c40: b580 push {r7, lr}
- 8001c42: af00 add r7, sp, #0
- /* USER CODE BEGIN TIM6_DAC_IRQn 0 */
-
- /* USER CODE END TIM6_DAC_IRQn 0 */
- HAL_TIM_IRQHandler(&htim6);
- 8001c44: 4802 ldr r0, [pc, #8] ; (8001c50 <TIM6_DAC_IRQHandler+0x10>)
- 8001c46: f001 fdda bl 80037fe <HAL_TIM_IRQHandler>
- /* USER CODE BEGIN TIM6_DAC_IRQn 1 */
-
- /* USER CODE END TIM6_DAC_IRQn 1 */
-}
- 8001c4a: bf00 nop
- 8001c4c: bd80 pop {r7, pc}
- 8001c4e: bf00 nop
- 8001c50: 2000012c .word 0x2000012c
-
-08001c54 <USART6_IRQHandler>:
-
-/**
- * @brief This function handles USART6 global interrupt.
- */
-void USART6_IRQHandler(void)
-{
- 8001c54: b580 push {r7, lr}
- 8001c56: af00 add r7, sp, #0
- /* USER CODE BEGIN USART6_IRQn 0 */
-
- /* USER CODE END USART6_IRQn 0 */
- HAL_UART_IRQHandler(&huart6);
- 8001c58: 4802 ldr r0, [pc, #8] ; (8001c64 <USART6_IRQHandler+0x10>)
- 8001c5a: f002 fea3 bl 80049a4 <HAL_UART_IRQHandler>
- /* USER CODE BEGIN USART6_IRQn 1 */
-
- /* USER CODE END USART6_IRQn 1 */
-}
- 8001c5e: bf00 nop
- 8001c60: bd80 pop {r7, pc}
- 8001c62: bf00 nop
- 8001c64: 2000016c .word 0x2000016c
-
-08001c68 <SystemInit>:
- * SystemFrequency variable.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- 8001c68: b480 push {r7}
- 8001c6a: af00 add r7, sp, #0
- /* FPU settings ------------------------------------------------------------*/
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- 8001c6c: 4b15 ldr r3, [pc, #84] ; (8001cc4 <SystemInit+0x5c>)
- 8001c6e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8001c72: 4a14 ldr r2, [pc, #80] ; (8001cc4 <SystemInit+0x5c>)
- 8001c74: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
- 8001c78: f8c2 3088 str.w r3, [r2, #136] ; 0x88
- #endif
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
- 8001c7c: 4b12 ldr r3, [pc, #72] ; (8001cc8 <SystemInit+0x60>)
- 8001c7e: 681b ldr r3, [r3, #0]
- 8001c80: 4a11 ldr r2, [pc, #68] ; (8001cc8 <SystemInit+0x60>)
- 8001c82: f043 0301 orr.w r3, r3, #1
- 8001c86: 6013 str r3, [r2, #0]
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
- 8001c88: 4b0f ldr r3, [pc, #60] ; (8001cc8 <SystemInit+0x60>)
- 8001c8a: 2200 movs r2, #0
- 8001c8c: 609a str r2, [r3, #8]
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
- 8001c8e: 4b0e ldr r3, [pc, #56] ; (8001cc8 <SystemInit+0x60>)
- 8001c90: 681a ldr r2, [r3, #0]
- 8001c92: 490d ldr r1, [pc, #52] ; (8001cc8 <SystemInit+0x60>)
- 8001c94: 4b0d ldr r3, [pc, #52] ; (8001ccc <SystemInit+0x64>)
- 8001c96: 4013 ands r3, r2
- 8001c98: 600b str r3, [r1, #0]
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
- 8001c9a: 4b0b ldr r3, [pc, #44] ; (8001cc8 <SystemInit+0x60>)
- 8001c9c: 4a0c ldr r2, [pc, #48] ; (8001cd0 <SystemInit+0x68>)
- 8001c9e: 605a str r2, [r3, #4]
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
- 8001ca0: 4b09 ldr r3, [pc, #36] ; (8001cc8 <SystemInit+0x60>)
- 8001ca2: 681b ldr r3, [r3, #0]
- 8001ca4: 4a08 ldr r2, [pc, #32] ; (8001cc8 <SystemInit+0x60>)
- 8001ca6: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 8001caa: 6013 str r3, [r2, #0]
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
- 8001cac: 4b06 ldr r3, [pc, #24] ; (8001cc8 <SystemInit+0x60>)
- 8001cae: 2200 movs r2, #0
- 8001cb0: 60da str r2, [r3, #12]
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
- 8001cb2: 4b04 ldr r3, [pc, #16] ; (8001cc4 <SystemInit+0x5c>)
- 8001cb4: f04f 6200 mov.w r2, #134217728 ; 0x8000000
- 8001cb8: 609a str r2, [r3, #8]
-#endif
-}
- 8001cba: bf00 nop
- 8001cbc: 46bd mov sp, r7
- 8001cbe: f85d 7b04 ldr.w r7, [sp], #4
- 8001cc2: 4770 bx lr
- 8001cc4: e000ed00 .word 0xe000ed00
- 8001cc8: 40023800 .word 0x40023800
- 8001ccc: fef6ffff .word 0xfef6ffff
- 8001cd0: 24003010 .word 0x24003010
-
-08001cd4 <Reset_Handler>:
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr sp, =_estack /* set stack pointer */
- 8001cd4: f8df d034 ldr.w sp, [pc, #52] ; 8001d0c <LoopFillZerobss+0x14>
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- 8001cd8: 2100 movs r1, #0
- b LoopCopyDataInit
- 8001cda: e003 b.n 8001ce4 <LoopCopyDataInit>
-
-08001cdc <CopyDataInit>:
-
-CopyDataInit:
- ldr r3, =_sidata
- 8001cdc: 4b0c ldr r3, [pc, #48] ; (8001d10 <LoopFillZerobss+0x18>)
- ldr r3, [r3, r1]
- 8001cde: 585b ldr r3, [r3, r1]
- str r3, [r0, r1]
- 8001ce0: 5043 str r3, [r0, r1]
- adds r1, r1, #4
- 8001ce2: 3104 adds r1, #4
-
-08001ce4 <LoopCopyDataInit>:
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- 8001ce4: 480b ldr r0, [pc, #44] ; (8001d14 <LoopFillZerobss+0x1c>)
- ldr r3, =_edata
- 8001ce6: 4b0c ldr r3, [pc, #48] ; (8001d18 <LoopFillZerobss+0x20>)
- adds r2, r0, r1
- 8001ce8: 1842 adds r2, r0, r1
- cmp r2, r3
- 8001cea: 429a cmp r2, r3
- bcc CopyDataInit
- 8001cec: d3f6 bcc.n 8001cdc <CopyDataInit>
- ldr r2, =_sbss
- 8001cee: 4a0b ldr r2, [pc, #44] ; (8001d1c <LoopFillZerobss+0x24>)
- b LoopFillZerobss
- 8001cf0: e002 b.n 8001cf8 <LoopFillZerobss>
-
-08001cf2 <FillZerobss>:
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- 8001cf2: 2300 movs r3, #0
- str r3, [r2], #4
- 8001cf4: f842 3b04 str.w r3, [r2], #4
-
-08001cf8 <LoopFillZerobss>:
-
-LoopFillZerobss:
- ldr r3, = _ebss
- 8001cf8: 4b09 ldr r3, [pc, #36] ; (8001d20 <LoopFillZerobss+0x28>)
- cmp r2, r3
- 8001cfa: 429a cmp r2, r3
- bcc FillZerobss
- 8001cfc: d3f9 bcc.n 8001cf2 <FillZerobss>
-
-/* Call the clock system initialization function.*/
- bl SystemInit
- 8001cfe: f7ff ffb3 bl 8001c68 <SystemInit>
-/* Call static constructors */
- bl __libc_init_array
- 8001d02: f003 fc31 bl 8005568 <__libc_init_array>
-/* Call the application's entry point.*/
- bl main
- 8001d06: f7fe ff43 bl 8000b90 <main>
- bx lr
- 8001d0a: 4770 bx lr
- ldr sp, =_estack /* set stack pointer */
- 8001d0c: 20080000 .word 0x20080000
- ldr r3, =_sidata
- 8001d10: 08005604 .word 0x08005604
- ldr r0, =_sdata
- 8001d14: 20000000 .word 0x20000000
- ldr r3, =_edata
- 8001d18: 20000010 .word 0x20000010
- ldr r2, =_sbss
- 8001d1c: 20000010 .word 0x20000010
- ldr r3, = _ebss
- 8001d20: 2000030c .word 0x2000030c
-
-08001d24 <ADC_IRQHandler>:
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- 8001d24: e7fe b.n 8001d24 <ADC_IRQHandler>
-
-08001d26 <HAL_Init>:
- * need to ensure that the SysTick time base is always set to 1 millisecond
- * to have correct HAL operation.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_Init(void)
-{
- 8001d26: b580 push {r7, lr}
- 8001d28: af00 add r7, sp, #0
-#if (PREFETCH_ENABLE != 0U)
- __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
-#endif /* PREFETCH_ENABLE */
-
- /* Set Interrupt Group Priority */
- HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
- 8001d2a: 2003 movs r0, #3
- 8001d2c: f000 f928 bl 8001f80 <HAL_NVIC_SetPriorityGrouping>
-
- /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
- HAL_InitTick(TICK_INT_PRIORITY);
- 8001d30: 2000 movs r0, #0
- 8001d32: f000 f805 bl 8001d40 <HAL_InitTick>
-
- /* Init the low level hardware */
- HAL_MspInit();
- 8001d36: f7ff fdcb bl 80018d0 <HAL_MspInit>
-
- /* Return function status */
- return HAL_OK;
- 8001d3a: 2300 movs r3, #0
-}
- 8001d3c: 4618 mov r0, r3
- 8001d3e: bd80 pop {r7, pc}
-
-08001d40 <HAL_InitTick>:
- * implementation in user file.
- * @param TickPriority Tick interrupt priority.
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
- 8001d40: b580 push {r7, lr}
- 8001d42: b082 sub sp, #8
- 8001d44: af00 add r7, sp, #0
- 8001d46: 6078 str r0, [r7, #4]
- /* Configure the SysTick to have interrupt in 1ms time basis*/
- if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
- 8001d48: 4b12 ldr r3, [pc, #72] ; (8001d94 <HAL_InitTick+0x54>)
- 8001d4a: 681a ldr r2, [r3, #0]
- 8001d4c: 4b12 ldr r3, [pc, #72] ; (8001d98 <HAL_InitTick+0x58>)
- 8001d4e: 781b ldrb r3, [r3, #0]
- 8001d50: 4619 mov r1, r3
- 8001d52: f44f 737a mov.w r3, #1000 ; 0x3e8
- 8001d56: fbb3 f3f1 udiv r3, r3, r1
- 8001d5a: fbb2 f3f3 udiv r3, r2, r3
- 8001d5e: 4618 mov r0, r3
- 8001d60: f000 f943 bl 8001fea <HAL_SYSTICK_Config>
- 8001d64: 4603 mov r3, r0
- 8001d66: 2b00 cmp r3, #0
- 8001d68: d001 beq.n 8001d6e <HAL_InitTick+0x2e>
- {
- return HAL_ERROR;
- 8001d6a: 2301 movs r3, #1
- 8001d6c: e00e b.n 8001d8c <HAL_InitTick+0x4c>
- }
-
- /* Configure the SysTick IRQ priority */
- if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- 8001d6e: 687b ldr r3, [r7, #4]
- 8001d70: 2b0f cmp r3, #15
- 8001d72: d80a bhi.n 8001d8a <HAL_InitTick+0x4a>
- {
- HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
- 8001d74: 2200 movs r2, #0
- 8001d76: 6879 ldr r1, [r7, #4]
- 8001d78: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 8001d7c: f000 f90b bl 8001f96 <HAL_NVIC_SetPriority>
- uwTickPrio = TickPriority;
- 8001d80: 4a06 ldr r2, [pc, #24] ; (8001d9c <HAL_InitTick+0x5c>)
- 8001d82: 687b ldr r3, [r7, #4]
- 8001d84: 6013 str r3, [r2, #0]
- {
- return HAL_ERROR;
- }
-
- /* Return function status */
- return HAL_OK;
- 8001d86: 2300 movs r3, #0
- 8001d88: e000 b.n 8001d8c <HAL_InitTick+0x4c>
- return HAL_ERROR;
- 8001d8a: 2301 movs r3, #1
-}
- 8001d8c: 4618 mov r0, r3
- 8001d8e: 3708 adds r7, #8
- 8001d90: 46bd mov sp, r7
- 8001d92: bd80 pop {r7, pc}
- 8001d94: 20000004 .word 0x20000004
- 8001d98: 2000000c .word 0x2000000c
- 8001d9c: 20000008 .word 0x20000008
-
-08001da0 <HAL_IncTick>:
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_IncTick(void)
-{
- 8001da0: b480 push {r7}
- 8001da2: af00 add r7, sp, #0
- uwTick += uwTickFreq;
- 8001da4: 4b06 ldr r3, [pc, #24] ; (8001dc0 <HAL_IncTick+0x20>)
- 8001da6: 781b ldrb r3, [r3, #0]
- 8001da8: 461a mov r2, r3
- 8001daa: 4b06 ldr r3, [pc, #24] ; (8001dc4 <HAL_IncTick+0x24>)
- 8001dac: 681b ldr r3, [r3, #0]
- 8001dae: 4413 add r3, r2
- 8001db0: 4a04 ldr r2, [pc, #16] ; (8001dc4 <HAL_IncTick+0x24>)
- 8001db2: 6013 str r3, [r2, #0]
-}
- 8001db4: bf00 nop
- 8001db6: 46bd mov sp, r7
- 8001db8: f85d 7b04 ldr.w r7, [sp], #4
- 8001dbc: 4770 bx lr
- 8001dbe: bf00 nop
- 8001dc0: 2000000c .word 0x2000000c
- 8001dc4: 20000308 .word 0x20000308
-
-08001dc8 <HAL_GetTick>:
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval tick value
- */
-__weak uint32_t HAL_GetTick(void)
-{
- 8001dc8: b480 push {r7}
- 8001dca: af00 add r7, sp, #0
- return uwTick;
- 8001dcc: 4b03 ldr r3, [pc, #12] ; (8001ddc <HAL_GetTick+0x14>)
- 8001dce: 681b ldr r3, [r3, #0]
-}
- 8001dd0: 4618 mov r0, r3
- 8001dd2: 46bd mov sp, r7
- 8001dd4: f85d 7b04 ldr.w r7, [sp], #4
- 8001dd8: 4770 bx lr
- 8001dda: bf00 nop
- 8001ddc: 20000308 .word 0x20000308
-
-08001de0 <__NVIC_SetPriorityGrouping>:
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- 8001de0: b480 push {r7}
- 8001de2: b085 sub sp, #20
- 8001de4: af00 add r7, sp, #0
- 8001de6: 6078 str r0, [r7, #4]
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- 8001de8: 687b ldr r3, [r7, #4]
- 8001dea: f003 0307 and.w r3, r3, #7
- 8001dee: 60fb str r3, [r7, #12]
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- 8001df0: 4b0b ldr r3, [pc, #44] ; (8001e20 <__NVIC_SetPriorityGrouping+0x40>)
- 8001df2: 68db ldr r3, [r3, #12]
- 8001df4: 60bb str r3, [r7, #8]
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- 8001df6: 68ba ldr r2, [r7, #8]
- 8001df8: f64f 03ff movw r3, #63743 ; 0xf8ff
- 8001dfc: 4013 ands r3, r2
- 8001dfe: 60bb str r3, [r7, #8]
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
- 8001e00: 68fb ldr r3, [r7, #12]
- 8001e02: 021a lsls r2, r3, #8
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- 8001e04: 68bb ldr r3, [r7, #8]
- 8001e06: 431a orrs r2, r3
- reg_value = (reg_value |
- 8001e08: 4b06 ldr r3, [pc, #24] ; (8001e24 <__NVIC_SetPriorityGrouping+0x44>)
- 8001e0a: 4313 orrs r3, r2
- 8001e0c: 60bb str r3, [r7, #8]
- SCB->AIRCR = reg_value;
- 8001e0e: 4a04 ldr r2, [pc, #16] ; (8001e20 <__NVIC_SetPriorityGrouping+0x40>)
- 8001e10: 68bb ldr r3, [r7, #8]
- 8001e12: 60d3 str r3, [r2, #12]
-}
- 8001e14: bf00 nop
- 8001e16: 3714 adds r7, #20
- 8001e18: 46bd mov sp, r7
- 8001e1a: f85d 7b04 ldr.w r7, [sp], #4
- 8001e1e: 4770 bx lr
- 8001e20: e000ed00 .word 0xe000ed00
- 8001e24: 05fa0000 .word 0x05fa0000
-
-08001e28 <__NVIC_GetPriorityGrouping>:
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- 8001e28: b480 push {r7}
- 8001e2a: af00 add r7, sp, #0
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
- 8001e2c: 4b04 ldr r3, [pc, #16] ; (8001e40 <__NVIC_GetPriorityGrouping+0x18>)
- 8001e2e: 68db ldr r3, [r3, #12]
- 8001e30: 0a1b lsrs r3, r3, #8
- 8001e32: f003 0307 and.w r3, r3, #7
-}
- 8001e36: 4618 mov r0, r3
- 8001e38: 46bd mov sp, r7
- 8001e3a: f85d 7b04 ldr.w r7, [sp], #4
- 8001e3e: 4770 bx lr
- 8001e40: e000ed00 .word 0xe000ed00
-
-08001e44 <__NVIC_EnableIRQ>:
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- 8001e44: b480 push {r7}
- 8001e46: b083 sub sp, #12
- 8001e48: af00 add r7, sp, #0
- 8001e4a: 4603 mov r3, r0
- 8001e4c: 71fb strb r3, [r7, #7]
- if ((int32_t)(IRQn) >= 0)
- 8001e4e: f997 3007 ldrsb.w r3, [r7, #7]
- 8001e52: 2b00 cmp r3, #0
- 8001e54: db0b blt.n 8001e6e <__NVIC_EnableIRQ+0x2a>
- {
- NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- 8001e56: 79fb ldrb r3, [r7, #7]
- 8001e58: f003 021f and.w r2, r3, #31
- 8001e5c: 4907 ldr r1, [pc, #28] ; (8001e7c <__NVIC_EnableIRQ+0x38>)
- 8001e5e: f997 3007 ldrsb.w r3, [r7, #7]
- 8001e62: 095b lsrs r3, r3, #5
- 8001e64: 2001 movs r0, #1
- 8001e66: fa00 f202 lsl.w r2, r0, r2
- 8001e6a: f841 2023 str.w r2, [r1, r3, lsl #2]
- }
-}
- 8001e6e: bf00 nop
- 8001e70: 370c adds r7, #12
- 8001e72: 46bd mov sp, r7
- 8001e74: f85d 7b04 ldr.w r7, [sp], #4
- 8001e78: 4770 bx lr
- 8001e7a: bf00 nop
- 8001e7c: e000e100 .word 0xe000e100
-
-08001e80 <__NVIC_SetPriority>:
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- 8001e80: b480 push {r7}
- 8001e82: b083 sub sp, #12
- 8001e84: af00 add r7, sp, #0
- 8001e86: 4603 mov r3, r0
- 8001e88: 6039 str r1, [r7, #0]
- 8001e8a: 71fb strb r3, [r7, #7]
- if ((int32_t)(IRQn) >= 0)
- 8001e8c: f997 3007 ldrsb.w r3, [r7, #7]
- 8001e90: 2b00 cmp r3, #0
- 8001e92: db0a blt.n 8001eaa <__NVIC_SetPriority+0x2a>
- {
- NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8001e94: 683b ldr r3, [r7, #0]
- 8001e96: b2da uxtb r2, r3
- 8001e98: 490c ldr r1, [pc, #48] ; (8001ecc <__NVIC_SetPriority+0x4c>)
- 8001e9a: f997 3007 ldrsb.w r3, [r7, #7]
- 8001e9e: 0112 lsls r2, r2, #4
- 8001ea0: b2d2 uxtb r2, r2
- 8001ea2: 440b add r3, r1
- 8001ea4: f883 2300 strb.w r2, [r3, #768] ; 0x300
- }
- else
- {
- SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
- 8001ea8: e00a b.n 8001ec0 <__NVIC_SetPriority+0x40>
- SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8001eaa: 683b ldr r3, [r7, #0]
- 8001eac: b2da uxtb r2, r3
- 8001eae: 4908 ldr r1, [pc, #32] ; (8001ed0 <__NVIC_SetPriority+0x50>)
- 8001eb0: 79fb ldrb r3, [r7, #7]
- 8001eb2: f003 030f and.w r3, r3, #15
- 8001eb6: 3b04 subs r3, #4
- 8001eb8: 0112 lsls r2, r2, #4
- 8001eba: b2d2 uxtb r2, r2
- 8001ebc: 440b add r3, r1
- 8001ebe: 761a strb r2, [r3, #24]
-}
- 8001ec0: bf00 nop
- 8001ec2: 370c adds r7, #12
- 8001ec4: 46bd mov sp, r7
- 8001ec6: f85d 7b04 ldr.w r7, [sp], #4
- 8001eca: 4770 bx lr
- 8001ecc: e000e100 .word 0xe000e100
- 8001ed0: e000ed00 .word 0xe000ed00
-
-08001ed4 <NVIC_EncodePriority>:
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- 8001ed4: b480 push {r7}
- 8001ed6: b089 sub sp, #36 ; 0x24
- 8001ed8: af00 add r7, sp, #0
- 8001eda: 60f8 str r0, [r7, #12]
- 8001edc: 60b9 str r1, [r7, #8]
- 8001ede: 607a str r2, [r7, #4]
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- 8001ee0: 68fb ldr r3, [r7, #12]
- 8001ee2: f003 0307 and.w r3, r3, #7
- 8001ee6: 61fb str r3, [r7, #28]
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- 8001ee8: 69fb ldr r3, [r7, #28]
- 8001eea: f1c3 0307 rsb r3, r3, #7
- 8001eee: 2b04 cmp r3, #4
- 8001ef0: bf28 it cs
- 8001ef2: 2304 movcs r3, #4
- 8001ef4: 61bb str r3, [r7, #24]
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
- 8001ef6: 69fb ldr r3, [r7, #28]
- 8001ef8: 3304 adds r3, #4
- 8001efa: 2b06 cmp r3, #6
- 8001efc: d902 bls.n 8001f04 <NVIC_EncodePriority+0x30>
- 8001efe: 69fb ldr r3, [r7, #28]
- 8001f00: 3b03 subs r3, #3
- 8001f02: e000 b.n 8001f06 <NVIC_EncodePriority+0x32>
- 8001f04: 2300 movs r3, #0
- 8001f06: 617b str r3, [r7, #20]
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8001f08: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 8001f0c: 69bb ldr r3, [r7, #24]
- 8001f0e: fa02 f303 lsl.w r3, r2, r3
- 8001f12: 43da mvns r2, r3
- 8001f14: 68bb ldr r3, [r7, #8]
- 8001f16: 401a ands r2, r3
- 8001f18: 697b ldr r3, [r7, #20]
- 8001f1a: 409a lsls r2, r3
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- 8001f1c: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
- 8001f20: 697b ldr r3, [r7, #20]
- 8001f22: fa01 f303 lsl.w r3, r1, r3
- 8001f26: 43d9 mvns r1, r3
- 8001f28: 687b ldr r3, [r7, #4]
- 8001f2a: 400b ands r3, r1
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8001f2c: 4313 orrs r3, r2
- );
-}
- 8001f2e: 4618 mov r0, r3
- 8001f30: 3724 adds r7, #36 ; 0x24
- 8001f32: 46bd mov sp, r7
- 8001f34: f85d 7b04 ldr.w r7, [sp], #4
- 8001f38: 4770 bx lr
- ...
-
-08001f3c <SysTick_Config>:
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- 8001f3c: b580 push {r7, lr}
- 8001f3e: b082 sub sp, #8
- 8001f40: af00 add r7, sp, #0
- 8001f42: 6078 str r0, [r7, #4]
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- 8001f44: 687b ldr r3, [r7, #4]
- 8001f46: 3b01 subs r3, #1
- 8001f48: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
- 8001f4c: d301 bcc.n 8001f52 <SysTick_Config+0x16>
- {
- return (1UL); /* Reload value impossible */
- 8001f4e: 2301 movs r3, #1
- 8001f50: e00f b.n 8001f72 <SysTick_Config+0x36>
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- 8001f52: 4a0a ldr r2, [pc, #40] ; (8001f7c <SysTick_Config+0x40>)
- 8001f54: 687b ldr r3, [r7, #4]
- 8001f56: 3b01 subs r3, #1
- 8001f58: 6053 str r3, [r2, #4]
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- 8001f5a: 210f movs r1, #15
- 8001f5c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 8001f60: f7ff ff8e bl 8001e80 <__NVIC_SetPriority>
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- 8001f64: 4b05 ldr r3, [pc, #20] ; (8001f7c <SysTick_Config+0x40>)
- 8001f66: 2200 movs r2, #0
- 8001f68: 609a str r2, [r3, #8]
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- 8001f6a: 4b04 ldr r3, [pc, #16] ; (8001f7c <SysTick_Config+0x40>)
- 8001f6c: 2207 movs r2, #7
- 8001f6e: 601a str r2, [r3, #0]
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
- 8001f70: 2300 movs r3, #0
-}
- 8001f72: 4618 mov r0, r3
- 8001f74: 3708 adds r7, #8
- 8001f76: 46bd mov sp, r7
- 8001f78: bd80 pop {r7, pc}
- 8001f7a: bf00 nop
- 8001f7c: e000e010 .word 0xe000e010
-
-08001f80 <HAL_NVIC_SetPriorityGrouping>:
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
- * The pending IRQ priority will be managed only by the subpriority.
- * @retval None
- */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- 8001f80: b580 push {r7, lr}
- 8001f82: b082 sub sp, #8
- 8001f84: af00 add r7, sp, #0
- 8001f86: 6078 str r0, [r7, #4]
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-
- /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
- NVIC_SetPriorityGrouping(PriorityGroup);
- 8001f88: 6878 ldr r0, [r7, #4]
- 8001f8a: f7ff ff29 bl 8001de0 <__NVIC_SetPriorityGrouping>
-}
- 8001f8e: bf00 nop
- 8001f90: 3708 adds r7, #8
- 8001f92: 46bd mov sp, r7
- 8001f94: bd80 pop {r7, pc}
-
-08001f96 <HAL_NVIC_SetPriority>:
- * This parameter can be a value between 0 and 15
- * A lower priority value indicates a higher priority.
- * @retval None
- */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- 8001f96: b580 push {r7, lr}
- 8001f98: b086 sub sp, #24
- 8001f9a: af00 add r7, sp, #0
- 8001f9c: 4603 mov r3, r0
- 8001f9e: 60b9 str r1, [r7, #8]
- 8001fa0: 607a str r2, [r7, #4]
- 8001fa2: 73fb strb r3, [r7, #15]
- uint32_t prioritygroup = 0x00;
- 8001fa4: 2300 movs r3, #0
- 8001fa6: 617b str r3, [r7, #20]
-
- /* Check the parameters */
- assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-
- prioritygroup = NVIC_GetPriorityGrouping();
- 8001fa8: f7ff ff3e bl 8001e28 <__NVIC_GetPriorityGrouping>
- 8001fac: 6178 str r0, [r7, #20]
-
- NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
- 8001fae: 687a ldr r2, [r7, #4]
- 8001fb0: 68b9 ldr r1, [r7, #8]
- 8001fb2: 6978 ldr r0, [r7, #20]
- 8001fb4: f7ff ff8e bl 8001ed4 <NVIC_EncodePriority>
- 8001fb8: 4602 mov r2, r0
- 8001fba: f997 300f ldrsb.w r3, [r7, #15]
- 8001fbe: 4611 mov r1, r2
- 8001fc0: 4618 mov r0, r3
- 8001fc2: f7ff ff5d bl 8001e80 <__NVIC_SetPriority>
-}
- 8001fc6: bf00 nop
- 8001fc8: 3718 adds r7, #24
- 8001fca: 46bd mov sp, r7
- 8001fcc: bd80 pop {r7, pc}
-
-08001fce <HAL_NVIC_EnableIRQ>:
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
- * @retval None
- */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- 8001fce: b580 push {r7, lr}
- 8001fd0: b082 sub sp, #8
- 8001fd2: af00 add r7, sp, #0
- 8001fd4: 4603 mov r3, r0
- 8001fd6: 71fb strb r3, [r7, #7]
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Enable interrupt */
- NVIC_EnableIRQ(IRQn);
- 8001fd8: f997 3007 ldrsb.w r3, [r7, #7]
- 8001fdc: 4618 mov r0, r3
- 8001fde: f7ff ff31 bl 8001e44 <__NVIC_EnableIRQ>
-}
- 8001fe2: bf00 nop
- 8001fe4: 3708 adds r7, #8
- 8001fe6: 46bd mov sp, r7
- 8001fe8: bd80 pop {r7, pc}
-
-08001fea <HAL_SYSTICK_Config>:
- * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
- * @retval status: - 0 Function succeeded.
- * - 1 Function failed.
- */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
- 8001fea: b580 push {r7, lr}
- 8001fec: b082 sub sp, #8
- 8001fee: af00 add r7, sp, #0
- 8001ff0: 6078 str r0, [r7, #4]
- return SysTick_Config(TicksNumb);
- 8001ff2: 6878 ldr r0, [r7, #4]
- 8001ff4: f7ff ffa2 bl 8001f3c <SysTick_Config>
- 8001ff8: 4603 mov r3, r0
-}
- 8001ffa: 4618 mov r0, r3
- 8001ffc: 3708 adds r7, #8
- 8001ffe: 46bd mov sp, r7
- 8002000: bd80 pop {r7, pc}
-
-08002002 <HAL_DMA_Abort_IT>:
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{
- 8002002: b480 push {r7}
- 8002004: b083 sub sp, #12
- 8002006: af00 add r7, sp, #0
- 8002008: 6078 str r0, [r7, #4]
- if(hdma->State != HAL_DMA_STATE_BUSY)
- 800200a: 687b ldr r3, [r7, #4]
- 800200c: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
- 8002010: b2db uxtb r3, r3
- 8002012: 2b02 cmp r3, #2
- 8002014: d004 beq.n 8002020 <HAL_DMA_Abort_IT+0x1e>
- {
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
- 8002016: 687b ldr r3, [r7, #4]
- 8002018: 2280 movs r2, #128 ; 0x80
- 800201a: 655a str r2, [r3, #84] ; 0x54
- return HAL_ERROR;
- 800201c: 2301 movs r3, #1
- 800201e: e00c b.n 800203a <HAL_DMA_Abort_IT+0x38>
- }
- else
- {
- /* Set Abort State */
- hdma->State = HAL_DMA_STATE_ABORT;
- 8002020: 687b ldr r3, [r7, #4]
- 8002022: 2205 movs r2, #5
- 8002024: f883 2035 strb.w r2, [r3, #53] ; 0x35
-
- /* Disable the stream */
- __HAL_DMA_DISABLE(hdma);
- 8002028: 687b ldr r3, [r7, #4]
- 800202a: 681b ldr r3, [r3, #0]
- 800202c: 681a ldr r2, [r3, #0]
- 800202e: 687b ldr r3, [r7, #4]
- 8002030: 681b ldr r3, [r3, #0]
- 8002032: f022 0201 bic.w r2, r2, #1
- 8002036: 601a str r2, [r3, #0]
- }
-
- return HAL_OK;
- 8002038: 2300 movs r3, #0
-}
- 800203a: 4618 mov r0, r3
- 800203c: 370c adds r7, #12
- 800203e: 46bd mov sp, r7
- 8002040: f85d 7b04 ldr.w r7, [sp], #4
- 8002044: 4770 bx lr
- ...
-
-08002048 <HAL_GPIO_Init>:
- * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
- * the configuration information for the specified GPIO peripheral.
- * @retval None
- */
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
- 8002048: b480 push {r7}
- 800204a: b089 sub sp, #36 ; 0x24
- 800204c: af00 add r7, sp, #0
- 800204e: 6078 str r0, [r7, #4]
- 8002050: 6039 str r1, [r7, #0]
- uint32_t position = 0x00;
- 8002052: 2300 movs r3, #0
- 8002054: 61fb str r3, [r7, #28]
- uint32_t ioposition = 0x00;
- 8002056: 2300 movs r3, #0
- 8002058: 617b str r3, [r7, #20]
- uint32_t iocurrent = 0x00;
- 800205a: 2300 movs r3, #0
- 800205c: 613b str r3, [r7, #16]
- uint32_t temp = 0x00;
- 800205e: 2300 movs r3, #0
- 8002060: 61bb str r3, [r7, #24]
- assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
- assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
- assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
-
- /* Configure the port pins */
- for(position = 0; position < GPIO_NUMBER; position++)
- 8002062: 2300 movs r3, #0
- 8002064: 61fb str r3, [r7, #28]
- 8002066: e175 b.n 8002354 <HAL_GPIO_Init+0x30c>
- {
- /* Get the IO position */
- ioposition = ((uint32_t)0x01) << position;
- 8002068: 2201 movs r2, #1
- 800206a: 69fb ldr r3, [r7, #28]
- 800206c: fa02 f303 lsl.w r3, r2, r3
- 8002070: 617b str r3, [r7, #20]
- /* Get the current IO position */
- iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
- 8002072: 683b ldr r3, [r7, #0]
- 8002074: 681b ldr r3, [r3, #0]
- 8002076: 697a ldr r2, [r7, #20]
- 8002078: 4013 ands r3, r2
- 800207a: 613b str r3, [r7, #16]
-
- if(iocurrent == ioposition)
- 800207c: 693a ldr r2, [r7, #16]
- 800207e: 697b ldr r3, [r7, #20]
- 8002080: 429a cmp r2, r3
- 8002082: f040 8164 bne.w 800234e <HAL_GPIO_Init+0x306>
- {
- /*--------------------- GPIO Mode Configuration ------------------------*/
- /* In case of Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 8002086: 683b ldr r3, [r7, #0]
- 8002088: 685b ldr r3, [r3, #4]
- 800208a: 2b02 cmp r3, #2
- 800208c: d003 beq.n 8002096 <HAL_GPIO_Init+0x4e>
- 800208e: 683b ldr r3, [r7, #0]
- 8002090: 685b ldr r3, [r3, #4]
- 8002092: 2b12 cmp r3, #18
- 8002094: d123 bne.n 80020de <HAL_GPIO_Init+0x96>
- {
- /* Check the Alternate function parameter */
- assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
- /* Configure Alternate function mapped with the current IO */
- temp = GPIOx->AFR[position >> 3];
- 8002096: 69fb ldr r3, [r7, #28]
- 8002098: 08da lsrs r2, r3, #3
- 800209a: 687b ldr r3, [r7, #4]
- 800209c: 3208 adds r2, #8
- 800209e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
- 80020a2: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
- 80020a4: 69fb ldr r3, [r7, #28]
- 80020a6: f003 0307 and.w r3, r3, #7
- 80020aa: 009b lsls r3, r3, #2
- 80020ac: 220f movs r2, #15
- 80020ae: fa02 f303 lsl.w r3, r2, r3
- 80020b2: 43db mvns r3, r3
- 80020b4: 69ba ldr r2, [r7, #24]
- 80020b6: 4013 ands r3, r2
- 80020b8: 61bb str r3, [r7, #24]
- temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
- 80020ba: 683b ldr r3, [r7, #0]
- 80020bc: 691a ldr r2, [r3, #16]
- 80020be: 69fb ldr r3, [r7, #28]
- 80020c0: f003 0307 and.w r3, r3, #7
- 80020c4: 009b lsls r3, r3, #2
- 80020c6: fa02 f303 lsl.w r3, r2, r3
- 80020ca: 69ba ldr r2, [r7, #24]
- 80020cc: 4313 orrs r3, r2
- 80020ce: 61bb str r3, [r7, #24]
- GPIOx->AFR[position >> 3] = temp;
- 80020d0: 69fb ldr r3, [r7, #28]
- 80020d2: 08da lsrs r2, r3, #3
- 80020d4: 687b ldr r3, [r7, #4]
- 80020d6: 3208 adds r2, #8
- 80020d8: 69b9 ldr r1, [r7, #24]
- 80020da: f843 1022 str.w r1, [r3, r2, lsl #2]
- }
-
- /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
- temp = GPIOx->MODER;
- 80020de: 687b ldr r3, [r7, #4]
- 80020e0: 681b ldr r3, [r3, #0]
- 80020e2: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_MODER_MODER0 << (position * 2));
- 80020e4: 69fb ldr r3, [r7, #28]
- 80020e6: 005b lsls r3, r3, #1
- 80020e8: 2203 movs r2, #3
- 80020ea: fa02 f303 lsl.w r3, r2, r3
- 80020ee: 43db mvns r3, r3
- 80020f0: 69ba ldr r2, [r7, #24]
- 80020f2: 4013 ands r3, r2
- 80020f4: 61bb str r3, [r7, #24]
- temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
- 80020f6: 683b ldr r3, [r7, #0]
- 80020f8: 685b ldr r3, [r3, #4]
- 80020fa: f003 0203 and.w r2, r3, #3
- 80020fe: 69fb ldr r3, [r7, #28]
- 8002100: 005b lsls r3, r3, #1
- 8002102: fa02 f303 lsl.w r3, r2, r3
- 8002106: 69ba ldr r2, [r7, #24]
- 8002108: 4313 orrs r3, r2
- 800210a: 61bb str r3, [r7, #24]
- GPIOx->MODER = temp;
- 800210c: 687b ldr r3, [r7, #4]
- 800210e: 69ba ldr r2, [r7, #24]
- 8002110: 601a str r2, [r3, #0]
-
- /* In case of Output or Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- 8002112: 683b ldr r3, [r7, #0]
- 8002114: 685b ldr r3, [r3, #4]
- 8002116: 2b01 cmp r3, #1
- 8002118: d00b beq.n 8002132 <HAL_GPIO_Init+0xea>
- 800211a: 683b ldr r3, [r7, #0]
- 800211c: 685b ldr r3, [r3, #4]
- 800211e: 2b02 cmp r3, #2
- 8002120: d007 beq.n 8002132 <HAL_GPIO_Init+0xea>
- (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 8002122: 683b ldr r3, [r7, #0]
- 8002124: 685b ldr r3, [r3, #4]
- if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- 8002126: 2b11 cmp r3, #17
- 8002128: d003 beq.n 8002132 <HAL_GPIO_Init+0xea>
- (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 800212a: 683b ldr r3, [r7, #0]
- 800212c: 685b ldr r3, [r3, #4]
- 800212e: 2b12 cmp r3, #18
- 8002130: d130 bne.n 8002194 <HAL_GPIO_Init+0x14c>
- {
- /* Check the Speed parameter */
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
- /* Configure the IO Speed */
- temp = GPIOx->OSPEEDR;
- 8002132: 687b ldr r3, [r7, #4]
- 8002134: 689b ldr r3, [r3, #8]
- 8002136: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
- 8002138: 69fb ldr r3, [r7, #28]
- 800213a: 005b lsls r3, r3, #1
- 800213c: 2203 movs r2, #3
- 800213e: fa02 f303 lsl.w r3, r2, r3
- 8002142: 43db mvns r3, r3
- 8002144: 69ba ldr r2, [r7, #24]
- 8002146: 4013 ands r3, r2
- 8002148: 61bb str r3, [r7, #24]
- temp |= (GPIO_Init->Speed << (position * 2));
- 800214a: 683b ldr r3, [r7, #0]
- 800214c: 68da ldr r2, [r3, #12]
- 800214e: 69fb ldr r3, [r7, #28]
- 8002150: 005b lsls r3, r3, #1
- 8002152: fa02 f303 lsl.w r3, r2, r3
- 8002156: 69ba ldr r2, [r7, #24]
- 8002158: 4313 orrs r3, r2
- 800215a: 61bb str r3, [r7, #24]
- GPIOx->OSPEEDR = temp;
- 800215c: 687b ldr r3, [r7, #4]
- 800215e: 69ba ldr r2, [r7, #24]
- 8002160: 609a str r2, [r3, #8]
-
- /* Configure the IO Output Type */
- temp = GPIOx->OTYPER;
- 8002162: 687b ldr r3, [r7, #4]
- 8002164: 685b ldr r3, [r3, #4]
- 8002166: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_OTYPER_OT_0 << position) ;
- 8002168: 2201 movs r2, #1
- 800216a: 69fb ldr r3, [r7, #28]
- 800216c: fa02 f303 lsl.w r3, r2, r3
- 8002170: 43db mvns r3, r3
- 8002172: 69ba ldr r2, [r7, #24]
- 8002174: 4013 ands r3, r2
- 8002176: 61bb str r3, [r7, #24]
- temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
- 8002178: 683b ldr r3, [r7, #0]
- 800217a: 685b ldr r3, [r3, #4]
- 800217c: 091b lsrs r3, r3, #4
- 800217e: f003 0201 and.w r2, r3, #1
- 8002182: 69fb ldr r3, [r7, #28]
- 8002184: fa02 f303 lsl.w r3, r2, r3
- 8002188: 69ba ldr r2, [r7, #24]
- 800218a: 4313 orrs r3, r2
- 800218c: 61bb str r3, [r7, #24]
- GPIOx->OTYPER = temp;
- 800218e: 687b ldr r3, [r7, #4]
- 8002190: 69ba ldr r2, [r7, #24]
- 8002192: 605a str r2, [r3, #4]
- }
-
- /* Activate the Pull-up or Pull down resistor for the current IO */
- temp = GPIOx->PUPDR;
- 8002194: 687b ldr r3, [r7, #4]
- 8002196: 68db ldr r3, [r3, #12]
- 8002198: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
- 800219a: 69fb ldr r3, [r7, #28]
- 800219c: 005b lsls r3, r3, #1
- 800219e: 2203 movs r2, #3
- 80021a0: fa02 f303 lsl.w r3, r2, r3
- 80021a4: 43db mvns r3, r3
- 80021a6: 69ba ldr r2, [r7, #24]
- 80021a8: 4013 ands r3, r2
- 80021aa: 61bb str r3, [r7, #24]
- temp |= ((GPIO_Init->Pull) << (position * 2));
- 80021ac: 683b ldr r3, [r7, #0]
- 80021ae: 689a ldr r2, [r3, #8]
- 80021b0: 69fb ldr r3, [r7, #28]
- 80021b2: 005b lsls r3, r3, #1
- 80021b4: fa02 f303 lsl.w r3, r2, r3
- 80021b8: 69ba ldr r2, [r7, #24]
- 80021ba: 4313 orrs r3, r2
- 80021bc: 61bb str r3, [r7, #24]
- GPIOx->PUPDR = temp;
- 80021be: 687b ldr r3, [r7, #4]
- 80021c0: 69ba ldr r2, [r7, #24]
- 80021c2: 60da str r2, [r3, #12]
-
- /*--------------------- EXTI Mode Configuration ------------------------*/
- /* Configure the External Interrupt or event for the current IO */
- if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
- 80021c4: 683b ldr r3, [r7, #0]
- 80021c6: 685b ldr r3, [r3, #4]
- 80021c8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80021cc: 2b00 cmp r3, #0
- 80021ce: f000 80be beq.w 800234e <HAL_GPIO_Init+0x306>
- {
- /* Enable SYSCFG Clock */
- __HAL_RCC_SYSCFG_CLK_ENABLE();
- 80021d2: 4b65 ldr r3, [pc, #404] ; (8002368 <HAL_GPIO_Init+0x320>)
- 80021d4: 6c5b ldr r3, [r3, #68] ; 0x44
- 80021d6: 4a64 ldr r2, [pc, #400] ; (8002368 <HAL_GPIO_Init+0x320>)
- 80021d8: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 80021dc: 6453 str r3, [r2, #68] ; 0x44
- 80021de: 4b62 ldr r3, [pc, #392] ; (8002368 <HAL_GPIO_Init+0x320>)
- 80021e0: 6c5b ldr r3, [r3, #68] ; 0x44
- 80021e2: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 80021e6: 60fb str r3, [r7, #12]
- 80021e8: 68fb ldr r3, [r7, #12]
-
- temp = SYSCFG->EXTICR[position >> 2];
- 80021ea: 4a60 ldr r2, [pc, #384] ; (800236c <HAL_GPIO_Init+0x324>)
- 80021ec: 69fb ldr r3, [r7, #28]
- 80021ee: 089b lsrs r3, r3, #2
- 80021f0: 3302 adds r3, #2
- 80021f2: f852 3023 ldr.w r3, [r2, r3, lsl #2]
- 80021f6: 61bb str r3, [r7, #24]
- temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
- 80021f8: 69fb ldr r3, [r7, #28]
- 80021fa: f003 0303 and.w r3, r3, #3
- 80021fe: 009b lsls r3, r3, #2
- 8002200: 220f movs r2, #15
- 8002202: fa02 f303 lsl.w r3, r2, r3
- 8002206: 43db mvns r3, r3
- 8002208: 69ba ldr r2, [r7, #24]
- 800220a: 4013 ands r3, r2
- 800220c: 61bb str r3, [r7, #24]
- temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
- 800220e: 687b ldr r3, [r7, #4]
- 8002210: 4a57 ldr r2, [pc, #348] ; (8002370 <HAL_GPIO_Init+0x328>)
- 8002212: 4293 cmp r3, r2
- 8002214: d037 beq.n 8002286 <HAL_GPIO_Init+0x23e>
- 8002216: 687b ldr r3, [r7, #4]
- 8002218: 4a56 ldr r2, [pc, #344] ; (8002374 <HAL_GPIO_Init+0x32c>)
- 800221a: 4293 cmp r3, r2
- 800221c: d031 beq.n 8002282 <HAL_GPIO_Init+0x23a>
- 800221e: 687b ldr r3, [r7, #4]
- 8002220: 4a55 ldr r2, [pc, #340] ; (8002378 <HAL_GPIO_Init+0x330>)
- 8002222: 4293 cmp r3, r2
- 8002224: d02b beq.n 800227e <HAL_GPIO_Init+0x236>
- 8002226: 687b ldr r3, [r7, #4]
- 8002228: 4a54 ldr r2, [pc, #336] ; (800237c <HAL_GPIO_Init+0x334>)
- 800222a: 4293 cmp r3, r2
- 800222c: d025 beq.n 800227a <HAL_GPIO_Init+0x232>
- 800222e: 687b ldr r3, [r7, #4]
- 8002230: 4a53 ldr r2, [pc, #332] ; (8002380 <HAL_GPIO_Init+0x338>)
- 8002232: 4293 cmp r3, r2
- 8002234: d01f beq.n 8002276 <HAL_GPIO_Init+0x22e>
- 8002236: 687b ldr r3, [r7, #4]
- 8002238: 4a52 ldr r2, [pc, #328] ; (8002384 <HAL_GPIO_Init+0x33c>)
- 800223a: 4293 cmp r3, r2
- 800223c: d019 beq.n 8002272 <HAL_GPIO_Init+0x22a>
- 800223e: 687b ldr r3, [r7, #4]
- 8002240: 4a51 ldr r2, [pc, #324] ; (8002388 <HAL_GPIO_Init+0x340>)
- 8002242: 4293 cmp r3, r2
- 8002244: d013 beq.n 800226e <HAL_GPIO_Init+0x226>
- 8002246: 687b ldr r3, [r7, #4]
- 8002248: 4a50 ldr r2, [pc, #320] ; (800238c <HAL_GPIO_Init+0x344>)
- 800224a: 4293 cmp r3, r2
- 800224c: d00d beq.n 800226a <HAL_GPIO_Init+0x222>
- 800224e: 687b ldr r3, [r7, #4]
- 8002250: 4a4f ldr r2, [pc, #316] ; (8002390 <HAL_GPIO_Init+0x348>)
- 8002252: 4293 cmp r3, r2
- 8002254: d007 beq.n 8002266 <HAL_GPIO_Init+0x21e>
- 8002256: 687b ldr r3, [r7, #4]
- 8002258: 4a4e ldr r2, [pc, #312] ; (8002394 <HAL_GPIO_Init+0x34c>)
- 800225a: 4293 cmp r3, r2
- 800225c: d101 bne.n 8002262 <HAL_GPIO_Init+0x21a>
- 800225e: 2309 movs r3, #9
- 8002260: e012 b.n 8002288 <HAL_GPIO_Init+0x240>
- 8002262: 230a movs r3, #10
- 8002264: e010 b.n 8002288 <HAL_GPIO_Init+0x240>
- 8002266: 2308 movs r3, #8
- 8002268: e00e b.n 8002288 <HAL_GPIO_Init+0x240>
- 800226a: 2307 movs r3, #7
- 800226c: e00c b.n 8002288 <HAL_GPIO_Init+0x240>
- 800226e: 2306 movs r3, #6
- 8002270: e00a b.n 8002288 <HAL_GPIO_Init+0x240>
- 8002272: 2305 movs r3, #5
- 8002274: e008 b.n 8002288 <HAL_GPIO_Init+0x240>
- 8002276: 2304 movs r3, #4
- 8002278: e006 b.n 8002288 <HAL_GPIO_Init+0x240>
- 800227a: 2303 movs r3, #3
- 800227c: e004 b.n 8002288 <HAL_GPIO_Init+0x240>
- 800227e: 2302 movs r3, #2
- 8002280: e002 b.n 8002288 <HAL_GPIO_Init+0x240>
- 8002282: 2301 movs r3, #1
- 8002284: e000 b.n 8002288 <HAL_GPIO_Init+0x240>
- 8002286: 2300 movs r3, #0
- 8002288: 69fa ldr r2, [r7, #28]
- 800228a: f002 0203 and.w r2, r2, #3
- 800228e: 0092 lsls r2, r2, #2
- 8002290: 4093 lsls r3, r2
- 8002292: 69ba ldr r2, [r7, #24]
- 8002294: 4313 orrs r3, r2
- 8002296: 61bb str r3, [r7, #24]
- SYSCFG->EXTICR[position >> 2] = temp;
- 8002298: 4934 ldr r1, [pc, #208] ; (800236c <HAL_GPIO_Init+0x324>)
- 800229a: 69fb ldr r3, [r7, #28]
- 800229c: 089b lsrs r3, r3, #2
- 800229e: 3302 adds r3, #2
- 80022a0: 69ba ldr r2, [r7, #24]
- 80022a2: f841 2023 str.w r2, [r1, r3, lsl #2]
-
- /* Clear EXTI line configuration */
- temp = EXTI->IMR;
- 80022a6: 4b3c ldr r3, [pc, #240] ; (8002398 <HAL_GPIO_Init+0x350>)
- 80022a8: 681b ldr r3, [r3, #0]
- 80022aa: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 80022ac: 693b ldr r3, [r7, #16]
- 80022ae: 43db mvns r3, r3
- 80022b0: 69ba ldr r2, [r7, #24]
- 80022b2: 4013 ands r3, r2
- 80022b4: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
- 80022b6: 683b ldr r3, [r7, #0]
- 80022b8: 685b ldr r3, [r3, #4]
- 80022ba: f403 3380 and.w r3, r3, #65536 ; 0x10000
- 80022be: 2b00 cmp r3, #0
- 80022c0: d003 beq.n 80022ca <HAL_GPIO_Init+0x282>
- {
- temp |= iocurrent;
- 80022c2: 69ba ldr r2, [r7, #24]
- 80022c4: 693b ldr r3, [r7, #16]
- 80022c6: 4313 orrs r3, r2
- 80022c8: 61bb str r3, [r7, #24]
- }
- EXTI->IMR = temp;
- 80022ca: 4a33 ldr r2, [pc, #204] ; (8002398 <HAL_GPIO_Init+0x350>)
- 80022cc: 69bb ldr r3, [r7, #24]
- 80022ce: 6013 str r3, [r2, #0]
-
- temp = EXTI->EMR;
- 80022d0: 4b31 ldr r3, [pc, #196] ; (8002398 <HAL_GPIO_Init+0x350>)
- 80022d2: 685b ldr r3, [r3, #4]
- 80022d4: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 80022d6: 693b ldr r3, [r7, #16]
- 80022d8: 43db mvns r3, r3
- 80022da: 69ba ldr r2, [r7, #24]
- 80022dc: 4013 ands r3, r2
- 80022de: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
- 80022e0: 683b ldr r3, [r7, #0]
- 80022e2: 685b ldr r3, [r3, #4]
- 80022e4: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 80022e8: 2b00 cmp r3, #0
- 80022ea: d003 beq.n 80022f4 <HAL_GPIO_Init+0x2ac>
- {
- temp |= iocurrent;
- 80022ec: 69ba ldr r2, [r7, #24]
- 80022ee: 693b ldr r3, [r7, #16]
- 80022f0: 4313 orrs r3, r2
- 80022f2: 61bb str r3, [r7, #24]
- }
- EXTI->EMR = temp;
- 80022f4: 4a28 ldr r2, [pc, #160] ; (8002398 <HAL_GPIO_Init+0x350>)
- 80022f6: 69bb ldr r3, [r7, #24]
- 80022f8: 6053 str r3, [r2, #4]
-
- /* Clear Rising Falling edge configuration */
- temp = EXTI->RTSR;
- 80022fa: 4b27 ldr r3, [pc, #156] ; (8002398 <HAL_GPIO_Init+0x350>)
- 80022fc: 689b ldr r3, [r3, #8]
- 80022fe: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 8002300: 693b ldr r3, [r7, #16]
- 8002302: 43db mvns r3, r3
- 8002304: 69ba ldr r2, [r7, #24]
- 8002306: 4013 ands r3, r2
- 8002308: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
- 800230a: 683b ldr r3, [r7, #0]
- 800230c: 685b ldr r3, [r3, #4]
- 800230e: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- 8002312: 2b00 cmp r3, #0
- 8002314: d003 beq.n 800231e <HAL_GPIO_Init+0x2d6>
- {
- temp |= iocurrent;
- 8002316: 69ba ldr r2, [r7, #24]
- 8002318: 693b ldr r3, [r7, #16]
- 800231a: 4313 orrs r3, r2
- 800231c: 61bb str r3, [r7, #24]
- }
- EXTI->RTSR = temp;
- 800231e: 4a1e ldr r2, [pc, #120] ; (8002398 <HAL_GPIO_Init+0x350>)
- 8002320: 69bb ldr r3, [r7, #24]
- 8002322: 6093 str r3, [r2, #8]
-
- temp = EXTI->FTSR;
- 8002324: 4b1c ldr r3, [pc, #112] ; (8002398 <HAL_GPIO_Init+0x350>)
- 8002326: 68db ldr r3, [r3, #12]
- 8002328: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 800232a: 693b ldr r3, [r7, #16]
- 800232c: 43db mvns r3, r3
- 800232e: 69ba ldr r2, [r7, #24]
- 8002330: 4013 ands r3, r2
- 8002332: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
- 8002334: 683b ldr r3, [r7, #0]
- 8002336: 685b ldr r3, [r3, #4]
- 8002338: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 800233c: 2b00 cmp r3, #0
- 800233e: d003 beq.n 8002348 <HAL_GPIO_Init+0x300>
- {
- temp |= iocurrent;
- 8002340: 69ba ldr r2, [r7, #24]
- 8002342: 693b ldr r3, [r7, #16]
- 8002344: 4313 orrs r3, r2
- 8002346: 61bb str r3, [r7, #24]
- }
- EXTI->FTSR = temp;
- 8002348: 4a13 ldr r2, [pc, #76] ; (8002398 <HAL_GPIO_Init+0x350>)
- 800234a: 69bb ldr r3, [r7, #24]
- 800234c: 60d3 str r3, [r2, #12]
- for(position = 0; position < GPIO_NUMBER; position++)
- 800234e: 69fb ldr r3, [r7, #28]
- 8002350: 3301 adds r3, #1
- 8002352: 61fb str r3, [r7, #28]
- 8002354: 69fb ldr r3, [r7, #28]
- 8002356: 2b0f cmp r3, #15
- 8002358: f67f ae86 bls.w 8002068 <HAL_GPIO_Init+0x20>
- }
- }
- }
-}
- 800235c: bf00 nop
- 800235e: 3724 adds r7, #36 ; 0x24
- 8002360: 46bd mov sp, r7
- 8002362: f85d 7b04 ldr.w r7, [sp], #4
- 8002366: 4770 bx lr
- 8002368: 40023800 .word 0x40023800
- 800236c: 40013800 .word 0x40013800
- 8002370: 40020000 .word 0x40020000
- 8002374: 40020400 .word 0x40020400
- 8002378: 40020800 .word 0x40020800
- 800237c: 40020c00 .word 0x40020c00
- 8002380: 40021000 .word 0x40021000
- 8002384: 40021400 .word 0x40021400
- 8002388: 40021800 .word 0x40021800
- 800238c: 40021c00 .word 0x40021c00
- 8002390: 40022000 .word 0x40022000
- 8002394: 40022400 .word 0x40022400
- 8002398: 40013c00 .word 0x40013c00
-
-0800239c <HAL_GPIO_WritePin>:
- * @arg GPIO_PIN_RESET: to clear the port pin
- * @arg GPIO_PIN_SET: to set the port pin
- * @retval None
- */
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
-{
- 800239c: b480 push {r7}
- 800239e: b083 sub sp, #12
- 80023a0: af00 add r7, sp, #0
- 80023a2: 6078 str r0, [r7, #4]
- 80023a4: 460b mov r3, r1
- 80023a6: 807b strh r3, [r7, #2]
- 80023a8: 4613 mov r3, r2
- 80023aa: 707b strb r3, [r7, #1]
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_PIN_ACTION(PinState));
-
- if(PinState != GPIO_PIN_RESET)
- 80023ac: 787b ldrb r3, [r7, #1]
- 80023ae: 2b00 cmp r3, #0
- 80023b0: d003 beq.n 80023ba <HAL_GPIO_WritePin+0x1e>
- {
- GPIOx->BSRR = GPIO_Pin;
- 80023b2: 887a ldrh r2, [r7, #2]
- 80023b4: 687b ldr r3, [r7, #4]
- 80023b6: 619a str r2, [r3, #24]
- }
- else
- {
- GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
- }
-}
- 80023b8: e003 b.n 80023c2 <HAL_GPIO_WritePin+0x26>
- GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
- 80023ba: 887b ldrh r3, [r7, #2]
- 80023bc: 041a lsls r2, r3, #16
- 80023be: 687b ldr r3, [r7, #4]
- 80023c0: 619a str r2, [r3, #24]
-}
- 80023c2: bf00 nop
- 80023c4: 370c adds r7, #12
- 80023c6: 46bd mov sp, r7
- 80023c8: f85d 7b04 ldr.w r7, [sp], #4
- 80023cc: 4770 bx lr
- ...
-
-080023d0 <HAL_GPIO_EXTI_IRQHandler>:
- * @brief This function handles EXTI interrupt request.
- * @param GPIO_Pin Specifies the pins connected EXTI line
- * @retval None
- */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
-{
- 80023d0: b580 push {r7, lr}
- 80023d2: b082 sub sp, #8
- 80023d4: af00 add r7, sp, #0
- 80023d6: 4603 mov r3, r0
- 80023d8: 80fb strh r3, [r7, #6]
- /* EXTI line interrupt detected */
- if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
- 80023da: 4b08 ldr r3, [pc, #32] ; (80023fc <HAL_GPIO_EXTI_IRQHandler+0x2c>)
- 80023dc: 695a ldr r2, [r3, #20]
- 80023de: 88fb ldrh r3, [r7, #6]
- 80023e0: 4013 ands r3, r2
- 80023e2: 2b00 cmp r3, #0
- 80023e4: d006 beq.n 80023f4 <HAL_GPIO_EXTI_IRQHandler+0x24>
- {
- __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
- 80023e6: 4a05 ldr r2, [pc, #20] ; (80023fc <HAL_GPIO_EXTI_IRQHandler+0x2c>)
- 80023e8: 88fb ldrh r3, [r7, #6]
- 80023ea: 6153 str r3, [r2, #20]
- HAL_GPIO_EXTI_Callback(GPIO_Pin);
- 80023ec: 88fb ldrh r3, [r7, #6]
- 80023ee: 4618 mov r0, r3
- 80023f0: f7ff f9a4 bl 800173c <HAL_GPIO_EXTI_Callback>
- }
-}
- 80023f4: bf00 nop
- 80023f6: 3708 adds r7, #8
- 80023f8: 46bd mov sp, r7
- 80023fa: bd80 pop {r7, pc}
- 80023fc: 40013c00 .word 0x40013c00
-
-08002400 <HAL_RCC_OscConfig>:
- * supported by this function. User should request a transition to HSE Off
- * first and then HSE On or HSE Bypass.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
-{
- 8002400: b580 push {r7, lr}
- 8002402: b086 sub sp, #24
- 8002404: af00 add r7, sp, #0
- 8002406: 6078 str r0, [r7, #4]
- uint32_t tickstart;
- FlagStatus pwrclkchanged = RESET;
- 8002408: 2300 movs r3, #0
- 800240a: 75fb strb r3, [r7, #23]
-
- /* Check Null pointer */
- if(RCC_OscInitStruct == NULL)
- 800240c: 687b ldr r3, [r7, #4]
- 800240e: 2b00 cmp r3, #0
- 8002410: d101 bne.n 8002416 <HAL_RCC_OscConfig+0x16>
- {
- return HAL_ERROR;
- 8002412: 2301 movs r3, #1
- 8002414: e25e b.n 80028d4 <HAL_RCC_OscConfig+0x4d4>
-
- /* Check the parameters */
- assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-
- /*------------------------------- HSE Configuration ------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- 8002416: 687b ldr r3, [r7, #4]
- 8002418: 681b ldr r3, [r3, #0]
- 800241a: f003 0301 and.w r3, r3, #1
- 800241e: 2b00 cmp r3, #0
- 8002420: f000 8087 beq.w 8002532 <HAL_RCC_OscConfig+0x132>
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
- /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
- 8002424: 4b96 ldr r3, [pc, #600] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 8002426: 689b ldr r3, [r3, #8]
- 8002428: f003 030c and.w r3, r3, #12
- 800242c: 2b04 cmp r3, #4
- 800242e: d00c beq.n 800244a <HAL_RCC_OscConfig+0x4a>
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
- 8002430: 4b93 ldr r3, [pc, #588] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 8002432: 689b ldr r3, [r3, #8]
- 8002434: f003 030c and.w r3, r3, #12
- 8002438: 2b08 cmp r3, #8
- 800243a: d112 bne.n 8002462 <HAL_RCC_OscConfig+0x62>
- 800243c: 4b90 ldr r3, [pc, #576] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 800243e: 685b ldr r3, [r3, #4]
- 8002440: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8002444: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8002448: d10b bne.n 8002462 <HAL_RCC_OscConfig+0x62>
- {
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 800244a: 4b8d ldr r3, [pc, #564] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 800244c: 681b ldr r3, [r3, #0]
- 800244e: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8002452: 2b00 cmp r3, #0
- 8002454: d06c beq.n 8002530 <HAL_RCC_OscConfig+0x130>
- 8002456: 687b ldr r3, [r7, #4]
- 8002458: 685b ldr r3, [r3, #4]
- 800245a: 2b00 cmp r3, #0
- 800245c: d168 bne.n 8002530 <HAL_RCC_OscConfig+0x130>
- {
- return HAL_ERROR;
- 800245e: 2301 movs r3, #1
- 8002460: e238 b.n 80028d4 <HAL_RCC_OscConfig+0x4d4>
- }
- }
- else
- {
- /* Set the new HSE configuration ---------------------------------------*/
- __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
- 8002462: 687b ldr r3, [r7, #4]
- 8002464: 685b ldr r3, [r3, #4]
- 8002466: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 800246a: d106 bne.n 800247a <HAL_RCC_OscConfig+0x7a>
- 800246c: 4b84 ldr r3, [pc, #528] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 800246e: 681b ldr r3, [r3, #0]
- 8002470: 4a83 ldr r2, [pc, #524] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 8002472: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 8002476: 6013 str r3, [r2, #0]
- 8002478: e02e b.n 80024d8 <HAL_RCC_OscConfig+0xd8>
- 800247a: 687b ldr r3, [r7, #4]
- 800247c: 685b ldr r3, [r3, #4]
- 800247e: 2b00 cmp r3, #0
- 8002480: d10c bne.n 800249c <HAL_RCC_OscConfig+0x9c>
- 8002482: 4b7f ldr r3, [pc, #508] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 8002484: 681b ldr r3, [r3, #0]
- 8002486: 4a7e ldr r2, [pc, #504] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 8002488: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 800248c: 6013 str r3, [r2, #0]
- 800248e: 4b7c ldr r3, [pc, #496] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 8002490: 681b ldr r3, [r3, #0]
- 8002492: 4a7b ldr r2, [pc, #492] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 8002494: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 8002498: 6013 str r3, [r2, #0]
- 800249a: e01d b.n 80024d8 <HAL_RCC_OscConfig+0xd8>
- 800249c: 687b ldr r3, [r7, #4]
- 800249e: 685b ldr r3, [r3, #4]
- 80024a0: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
- 80024a4: d10c bne.n 80024c0 <HAL_RCC_OscConfig+0xc0>
- 80024a6: 4b76 ldr r3, [pc, #472] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 80024a8: 681b ldr r3, [r3, #0]
- 80024aa: 4a75 ldr r2, [pc, #468] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 80024ac: f443 2380 orr.w r3, r3, #262144 ; 0x40000
- 80024b0: 6013 str r3, [r2, #0]
- 80024b2: 4b73 ldr r3, [pc, #460] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 80024b4: 681b ldr r3, [r3, #0]
- 80024b6: 4a72 ldr r2, [pc, #456] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 80024b8: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 80024bc: 6013 str r3, [r2, #0]
- 80024be: e00b b.n 80024d8 <HAL_RCC_OscConfig+0xd8>
- 80024c0: 4b6f ldr r3, [pc, #444] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 80024c2: 681b ldr r3, [r3, #0]
- 80024c4: 4a6e ldr r2, [pc, #440] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 80024c6: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 80024ca: 6013 str r3, [r2, #0]
- 80024cc: 4b6c ldr r3, [pc, #432] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 80024ce: 681b ldr r3, [r3, #0]
- 80024d0: 4a6b ldr r2, [pc, #428] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 80024d2: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 80024d6: 6013 str r3, [r2, #0]
-
- /* Check the HSE State */
- if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- 80024d8: 687b ldr r3, [r7, #4]
- 80024da: 685b ldr r3, [r3, #4]
- 80024dc: 2b00 cmp r3, #0
- 80024de: d013 beq.n 8002508 <HAL_RCC_OscConfig+0x108>
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80024e0: f7ff fc72 bl 8001dc8 <HAL_GetTick>
- 80024e4: 6138 str r0, [r7, #16]
-
- /* Wait till HSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 80024e6: e008 b.n 80024fa <HAL_RCC_OscConfig+0xfa>
- {
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 80024e8: f7ff fc6e bl 8001dc8 <HAL_GetTick>
- 80024ec: 4602 mov r2, r0
- 80024ee: 693b ldr r3, [r7, #16]
- 80024f0: 1ad3 subs r3, r2, r3
- 80024f2: 2b64 cmp r3, #100 ; 0x64
- 80024f4: d901 bls.n 80024fa <HAL_RCC_OscConfig+0xfa>
- {
- return HAL_TIMEOUT;
- 80024f6: 2303 movs r3, #3
- 80024f8: e1ec b.n 80028d4 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 80024fa: 4b61 ldr r3, [pc, #388] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 80024fc: 681b ldr r3, [r3, #0]
- 80024fe: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8002502: 2b00 cmp r3, #0
- 8002504: d0f0 beq.n 80024e8 <HAL_RCC_OscConfig+0xe8>
- 8002506: e014 b.n 8002532 <HAL_RCC_OscConfig+0x132>
- }
- }
- else
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002508: f7ff fc5e bl 8001dc8 <HAL_GetTick>
- 800250c: 6138 str r0, [r7, #16]
-
- /* Wait till HSE is bypassed or disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 800250e: e008 b.n 8002522 <HAL_RCC_OscConfig+0x122>
- {
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 8002510: f7ff fc5a bl 8001dc8 <HAL_GetTick>
- 8002514: 4602 mov r2, r0
- 8002516: 693b ldr r3, [r7, #16]
- 8002518: 1ad3 subs r3, r2, r3
- 800251a: 2b64 cmp r3, #100 ; 0x64
- 800251c: d901 bls.n 8002522 <HAL_RCC_OscConfig+0x122>
- {
- return HAL_TIMEOUT;
- 800251e: 2303 movs r3, #3
- 8002520: e1d8 b.n 80028d4 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 8002522: 4b57 ldr r3, [pc, #348] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 8002524: 681b ldr r3, [r3, #0]
- 8002526: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 800252a: 2b00 cmp r3, #0
- 800252c: d1f0 bne.n 8002510 <HAL_RCC_OscConfig+0x110>
- 800252e: e000 b.n 8002532 <HAL_RCC_OscConfig+0x132>
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 8002530: bf00 nop
- }
- }
- }
- }
- /*----------------------------- HSI Configuration --------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- 8002532: 687b ldr r3, [r7, #4]
- 8002534: 681b ldr r3, [r3, #0]
- 8002536: f003 0302 and.w r3, r3, #2
- 800253a: 2b00 cmp r3, #0
- 800253c: d069 beq.n 8002612 <HAL_RCC_OscConfig+0x212>
- /* Check the parameters */
- assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
- assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
- /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
- 800253e: 4b50 ldr r3, [pc, #320] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 8002540: 689b ldr r3, [r3, #8]
- 8002542: f003 030c and.w r3, r3, #12
- 8002546: 2b00 cmp r3, #0
- 8002548: d00b beq.n 8002562 <HAL_RCC_OscConfig+0x162>
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
- 800254a: 4b4d ldr r3, [pc, #308] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 800254c: 689b ldr r3, [r3, #8]
- 800254e: f003 030c and.w r3, r3, #12
- 8002552: 2b08 cmp r3, #8
- 8002554: d11c bne.n 8002590 <HAL_RCC_OscConfig+0x190>
- 8002556: 4b4a ldr r3, [pc, #296] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 8002558: 685b ldr r3, [r3, #4]
- 800255a: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 800255e: 2b00 cmp r3, #0
- 8002560: d116 bne.n 8002590 <HAL_RCC_OscConfig+0x190>
- {
- /* When HSI is used as system clock it will not disabled */
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 8002562: 4b47 ldr r3, [pc, #284] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 8002564: 681b ldr r3, [r3, #0]
- 8002566: f003 0302 and.w r3, r3, #2
- 800256a: 2b00 cmp r3, #0
- 800256c: d005 beq.n 800257a <HAL_RCC_OscConfig+0x17a>
- 800256e: 687b ldr r3, [r7, #4]
- 8002570: 68db ldr r3, [r3, #12]
- 8002572: 2b01 cmp r3, #1
- 8002574: d001 beq.n 800257a <HAL_RCC_OscConfig+0x17a>
- {
- return HAL_ERROR;
- 8002576: 2301 movs r3, #1
- 8002578: e1ac b.n 80028d4 <HAL_RCC_OscConfig+0x4d4>
- }
- /* Otherwise, just the calibration is allowed */
- else
- {
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 800257a: 4b41 ldr r3, [pc, #260] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 800257c: 681b ldr r3, [r3, #0]
- 800257e: f023 02f8 bic.w r2, r3, #248 ; 0xf8
- 8002582: 687b ldr r3, [r7, #4]
- 8002584: 691b ldr r3, [r3, #16]
- 8002586: 00db lsls r3, r3, #3
- 8002588: 493d ldr r1, [pc, #244] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 800258a: 4313 orrs r3, r2
- 800258c: 600b str r3, [r1, #0]
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 800258e: e040 b.n 8002612 <HAL_RCC_OscConfig+0x212>
- }
- }
- else
- {
- /* Check the HSI State */
- if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
- 8002590: 687b ldr r3, [r7, #4]
- 8002592: 68db ldr r3, [r3, #12]
- 8002594: 2b00 cmp r3, #0
- 8002596: d023 beq.n 80025e0 <HAL_RCC_OscConfig+0x1e0>
- {
- /* Enable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_ENABLE();
- 8002598: 4b39 ldr r3, [pc, #228] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 800259a: 681b ldr r3, [r3, #0]
- 800259c: 4a38 ldr r2, [pc, #224] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 800259e: f043 0301 orr.w r3, r3, #1
- 80025a2: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80025a4: f7ff fc10 bl 8001dc8 <HAL_GetTick>
- 80025a8: 6138 str r0, [r7, #16]
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80025aa: e008 b.n 80025be <HAL_RCC_OscConfig+0x1be>
- {
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 80025ac: f7ff fc0c bl 8001dc8 <HAL_GetTick>
- 80025b0: 4602 mov r2, r0
- 80025b2: 693b ldr r3, [r7, #16]
- 80025b4: 1ad3 subs r3, r2, r3
- 80025b6: 2b02 cmp r3, #2
- 80025b8: d901 bls.n 80025be <HAL_RCC_OscConfig+0x1be>
- {
- return HAL_TIMEOUT;
- 80025ba: 2303 movs r3, #3
- 80025bc: e18a b.n 80028d4 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80025be: 4b30 ldr r3, [pc, #192] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 80025c0: 681b ldr r3, [r3, #0]
- 80025c2: f003 0302 and.w r3, r3, #2
- 80025c6: 2b00 cmp r3, #0
- 80025c8: d0f0 beq.n 80025ac <HAL_RCC_OscConfig+0x1ac>
- }
- }
-
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 80025ca: 4b2d ldr r3, [pc, #180] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 80025cc: 681b ldr r3, [r3, #0]
- 80025ce: f023 02f8 bic.w r2, r3, #248 ; 0xf8
- 80025d2: 687b ldr r3, [r7, #4]
- 80025d4: 691b ldr r3, [r3, #16]
- 80025d6: 00db lsls r3, r3, #3
- 80025d8: 4929 ldr r1, [pc, #164] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 80025da: 4313 orrs r3, r2
- 80025dc: 600b str r3, [r1, #0]
- 80025de: e018 b.n 8002612 <HAL_RCC_OscConfig+0x212>
- }
- else
- {
- /* Disable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_DISABLE();
- 80025e0: 4b27 ldr r3, [pc, #156] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 80025e2: 681b ldr r3, [r3, #0]
- 80025e4: 4a26 ldr r2, [pc, #152] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 80025e6: f023 0301 bic.w r3, r3, #1
- 80025ea: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80025ec: f7ff fbec bl 8001dc8 <HAL_GetTick>
- 80025f0: 6138 str r0, [r7, #16]
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 80025f2: e008 b.n 8002606 <HAL_RCC_OscConfig+0x206>
- {
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 80025f4: f7ff fbe8 bl 8001dc8 <HAL_GetTick>
- 80025f8: 4602 mov r2, r0
- 80025fa: 693b ldr r3, [r7, #16]
- 80025fc: 1ad3 subs r3, r2, r3
- 80025fe: 2b02 cmp r3, #2
- 8002600: d901 bls.n 8002606 <HAL_RCC_OscConfig+0x206>
- {
- return HAL_TIMEOUT;
- 8002602: 2303 movs r3, #3
- 8002604: e166 b.n 80028d4 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 8002606: 4b1e ldr r3, [pc, #120] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 8002608: 681b ldr r3, [r3, #0]
- 800260a: f003 0302 and.w r3, r3, #2
- 800260e: 2b00 cmp r3, #0
- 8002610: d1f0 bne.n 80025f4 <HAL_RCC_OscConfig+0x1f4>
- }
- }
- }
- }
- /*------------------------------ LSI Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- 8002612: 687b ldr r3, [r7, #4]
- 8002614: 681b ldr r3, [r3, #0]
- 8002616: f003 0308 and.w r3, r3, #8
- 800261a: 2b00 cmp r3, #0
- 800261c: d038 beq.n 8002690 <HAL_RCC_OscConfig+0x290>
- {
- /* Check the parameters */
- assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
- /* Check the LSI State */
- if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
- 800261e: 687b ldr r3, [r7, #4]
- 8002620: 695b ldr r3, [r3, #20]
- 8002622: 2b00 cmp r3, #0
- 8002624: d019 beq.n 800265a <HAL_RCC_OscConfig+0x25a>
- {
- /* Enable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_ENABLE();
- 8002626: 4b16 ldr r3, [pc, #88] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 8002628: 6f5b ldr r3, [r3, #116] ; 0x74
- 800262a: 4a15 ldr r2, [pc, #84] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 800262c: f043 0301 orr.w r3, r3, #1
- 8002630: 6753 str r3, [r2, #116] ; 0x74
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002632: f7ff fbc9 bl 8001dc8 <HAL_GetTick>
- 8002636: 6138 str r0, [r7, #16]
-
- /* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 8002638: e008 b.n 800264c <HAL_RCC_OscConfig+0x24c>
- {
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 800263a: f7ff fbc5 bl 8001dc8 <HAL_GetTick>
- 800263e: 4602 mov r2, r0
- 8002640: 693b ldr r3, [r7, #16]
- 8002642: 1ad3 subs r3, r2, r3
- 8002644: 2b02 cmp r3, #2
- 8002646: d901 bls.n 800264c <HAL_RCC_OscConfig+0x24c>
- {
- return HAL_TIMEOUT;
- 8002648: 2303 movs r3, #3
- 800264a: e143 b.n 80028d4 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 800264c: 4b0c ldr r3, [pc, #48] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 800264e: 6f5b ldr r3, [r3, #116] ; 0x74
- 8002650: f003 0302 and.w r3, r3, #2
- 8002654: 2b00 cmp r3, #0
- 8002656: d0f0 beq.n 800263a <HAL_RCC_OscConfig+0x23a>
- 8002658: e01a b.n 8002690 <HAL_RCC_OscConfig+0x290>
- }
- }
- else
- {
- /* Disable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_DISABLE();
- 800265a: 4b09 ldr r3, [pc, #36] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 800265c: 6f5b ldr r3, [r3, #116] ; 0x74
- 800265e: 4a08 ldr r2, [pc, #32] ; (8002680 <HAL_RCC_OscConfig+0x280>)
- 8002660: f023 0301 bic.w r3, r3, #1
- 8002664: 6753 str r3, [r2, #116] ; 0x74
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002666: f7ff fbaf bl 8001dc8 <HAL_GetTick>
- 800266a: 6138 str r0, [r7, #16]
-
- /* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 800266c: e00a b.n 8002684 <HAL_RCC_OscConfig+0x284>
- {
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 800266e: f7ff fbab bl 8001dc8 <HAL_GetTick>
- 8002672: 4602 mov r2, r0
- 8002674: 693b ldr r3, [r7, #16]
- 8002676: 1ad3 subs r3, r2, r3
- 8002678: 2b02 cmp r3, #2
- 800267a: d903 bls.n 8002684 <HAL_RCC_OscConfig+0x284>
- {
- return HAL_TIMEOUT;
- 800267c: 2303 movs r3, #3
- 800267e: e129 b.n 80028d4 <HAL_RCC_OscConfig+0x4d4>
- 8002680: 40023800 .word 0x40023800
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 8002684: 4b95 ldr r3, [pc, #596] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 8002686: 6f5b ldr r3, [r3, #116] ; 0x74
- 8002688: f003 0302 and.w r3, r3, #2
- 800268c: 2b00 cmp r3, #0
- 800268e: d1ee bne.n 800266e <HAL_RCC_OscConfig+0x26e>
- }
- }
- }
- }
- /*------------------------------ LSE Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- 8002690: 687b ldr r3, [r7, #4]
- 8002692: 681b ldr r3, [r3, #0]
- 8002694: f003 0304 and.w r3, r3, #4
- 8002698: 2b00 cmp r3, #0
- 800269a: f000 80a4 beq.w 80027e6 <HAL_RCC_OscConfig+0x3e6>
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
- /* Update LSE configuration in Backup Domain control register */
- /* Requires to enable write access to Backup Domain of necessary */
- if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- 800269e: 4b8f ldr r3, [pc, #572] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 80026a0: 6c1b ldr r3, [r3, #64] ; 0x40
- 80026a2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80026a6: 2b00 cmp r3, #0
- 80026a8: d10d bne.n 80026c6 <HAL_RCC_OscConfig+0x2c6>
- {
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
- 80026aa: 4b8c ldr r3, [pc, #560] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 80026ac: 6c1b ldr r3, [r3, #64] ; 0x40
- 80026ae: 4a8b ldr r2, [pc, #556] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 80026b0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 80026b4: 6413 str r3, [r2, #64] ; 0x40
- 80026b6: 4b89 ldr r3, [pc, #548] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 80026b8: 6c1b ldr r3, [r3, #64] ; 0x40
- 80026ba: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80026be: 60fb str r3, [r7, #12]
- 80026c0: 68fb ldr r3, [r7, #12]
- pwrclkchanged = SET;
- 80026c2: 2301 movs r3, #1
- 80026c4: 75fb strb r3, [r7, #23]
- }
-
- if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 80026c6: 4b86 ldr r3, [pc, #536] ; (80028e0 <HAL_RCC_OscConfig+0x4e0>)
- 80026c8: 681b ldr r3, [r3, #0]
- 80026ca: f403 7380 and.w r3, r3, #256 ; 0x100
- 80026ce: 2b00 cmp r3, #0
- 80026d0: d118 bne.n 8002704 <HAL_RCC_OscConfig+0x304>
- {
- /* Enable write access to Backup domain */
- PWR->CR1 |= PWR_CR1_DBP;
- 80026d2: 4b83 ldr r3, [pc, #524] ; (80028e0 <HAL_RCC_OscConfig+0x4e0>)
- 80026d4: 681b ldr r3, [r3, #0]
- 80026d6: 4a82 ldr r2, [pc, #520] ; (80028e0 <HAL_RCC_OscConfig+0x4e0>)
- 80026d8: f443 7380 orr.w r3, r3, #256 ; 0x100
- 80026dc: 6013 str r3, [r2, #0]
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
- 80026de: f7ff fb73 bl 8001dc8 <HAL_GetTick>
- 80026e2: 6138 str r0, [r7, #16]
-
- while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 80026e4: e008 b.n 80026f8 <HAL_RCC_OscConfig+0x2f8>
- {
- if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
- 80026e6: f7ff fb6f bl 8001dc8 <HAL_GetTick>
- 80026ea: 4602 mov r2, r0
- 80026ec: 693b ldr r3, [r7, #16]
- 80026ee: 1ad3 subs r3, r2, r3
- 80026f0: 2b64 cmp r3, #100 ; 0x64
- 80026f2: d901 bls.n 80026f8 <HAL_RCC_OscConfig+0x2f8>
- {
- return HAL_TIMEOUT;
- 80026f4: 2303 movs r3, #3
- 80026f6: e0ed b.n 80028d4 <HAL_RCC_OscConfig+0x4d4>
- while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 80026f8: 4b79 ldr r3, [pc, #484] ; (80028e0 <HAL_RCC_OscConfig+0x4e0>)
- 80026fa: 681b ldr r3, [r3, #0]
- 80026fc: f403 7380 and.w r3, r3, #256 ; 0x100
- 8002700: 2b00 cmp r3, #0
- 8002702: d0f0 beq.n 80026e6 <HAL_RCC_OscConfig+0x2e6>
- }
- }
- }
-
- /* Set the new LSE configuration -----------------------------------------*/
- __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- 8002704: 687b ldr r3, [r7, #4]
- 8002706: 689b ldr r3, [r3, #8]
- 8002708: 2b01 cmp r3, #1
- 800270a: d106 bne.n 800271a <HAL_RCC_OscConfig+0x31a>
- 800270c: 4b73 ldr r3, [pc, #460] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 800270e: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002710: 4a72 ldr r2, [pc, #456] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 8002712: f043 0301 orr.w r3, r3, #1
- 8002716: 6713 str r3, [r2, #112] ; 0x70
- 8002718: e02d b.n 8002776 <HAL_RCC_OscConfig+0x376>
- 800271a: 687b ldr r3, [r7, #4]
- 800271c: 689b ldr r3, [r3, #8]
- 800271e: 2b00 cmp r3, #0
- 8002720: d10c bne.n 800273c <HAL_RCC_OscConfig+0x33c>
- 8002722: 4b6e ldr r3, [pc, #440] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 8002724: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002726: 4a6d ldr r2, [pc, #436] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 8002728: f023 0301 bic.w r3, r3, #1
- 800272c: 6713 str r3, [r2, #112] ; 0x70
- 800272e: 4b6b ldr r3, [pc, #428] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 8002730: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002732: 4a6a ldr r2, [pc, #424] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 8002734: f023 0304 bic.w r3, r3, #4
- 8002738: 6713 str r3, [r2, #112] ; 0x70
- 800273a: e01c b.n 8002776 <HAL_RCC_OscConfig+0x376>
- 800273c: 687b ldr r3, [r7, #4]
- 800273e: 689b ldr r3, [r3, #8]
- 8002740: 2b05 cmp r3, #5
- 8002742: d10c bne.n 800275e <HAL_RCC_OscConfig+0x35e>
- 8002744: 4b65 ldr r3, [pc, #404] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 8002746: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002748: 4a64 ldr r2, [pc, #400] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 800274a: f043 0304 orr.w r3, r3, #4
- 800274e: 6713 str r3, [r2, #112] ; 0x70
- 8002750: 4b62 ldr r3, [pc, #392] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 8002752: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002754: 4a61 ldr r2, [pc, #388] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 8002756: f043 0301 orr.w r3, r3, #1
- 800275a: 6713 str r3, [r2, #112] ; 0x70
- 800275c: e00b b.n 8002776 <HAL_RCC_OscConfig+0x376>
- 800275e: 4b5f ldr r3, [pc, #380] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 8002760: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002762: 4a5e ldr r2, [pc, #376] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 8002764: f023 0301 bic.w r3, r3, #1
- 8002768: 6713 str r3, [r2, #112] ; 0x70
- 800276a: 4b5c ldr r3, [pc, #368] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 800276c: 6f1b ldr r3, [r3, #112] ; 0x70
- 800276e: 4a5b ldr r2, [pc, #364] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 8002770: f023 0304 bic.w r3, r3, #4
- 8002774: 6713 str r3, [r2, #112] ; 0x70
- /* Check the LSE State */
- if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
- 8002776: 687b ldr r3, [r7, #4]
- 8002778: 689b ldr r3, [r3, #8]
- 800277a: 2b00 cmp r3, #0
- 800277c: d015 beq.n 80027aa <HAL_RCC_OscConfig+0x3aa>
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 800277e: f7ff fb23 bl 8001dc8 <HAL_GetTick>
- 8002782: 6138 str r0, [r7, #16]
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8002784: e00a b.n 800279c <HAL_RCC_OscConfig+0x39c>
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8002786: f7ff fb1f bl 8001dc8 <HAL_GetTick>
- 800278a: 4602 mov r2, r0
- 800278c: 693b ldr r3, [r7, #16]
- 800278e: 1ad3 subs r3, r2, r3
- 8002790: f241 3288 movw r2, #5000 ; 0x1388
- 8002794: 4293 cmp r3, r2
- 8002796: d901 bls.n 800279c <HAL_RCC_OscConfig+0x39c>
- {
- return HAL_TIMEOUT;
- 8002798: 2303 movs r3, #3
- 800279a: e09b b.n 80028d4 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 800279c: 4b4f ldr r3, [pc, #316] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 800279e: 6f1b ldr r3, [r3, #112] ; 0x70
- 80027a0: f003 0302 and.w r3, r3, #2
- 80027a4: 2b00 cmp r3, #0
- 80027a6: d0ee beq.n 8002786 <HAL_RCC_OscConfig+0x386>
- 80027a8: e014 b.n 80027d4 <HAL_RCC_OscConfig+0x3d4>
- }
- }
- else
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80027aa: f7ff fb0d bl 8001dc8 <HAL_GetTick>
- 80027ae: 6138 str r0, [r7, #16]
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 80027b0: e00a b.n 80027c8 <HAL_RCC_OscConfig+0x3c8>
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 80027b2: f7ff fb09 bl 8001dc8 <HAL_GetTick>
- 80027b6: 4602 mov r2, r0
- 80027b8: 693b ldr r3, [r7, #16]
- 80027ba: 1ad3 subs r3, r2, r3
- 80027bc: f241 3288 movw r2, #5000 ; 0x1388
- 80027c0: 4293 cmp r3, r2
- 80027c2: d901 bls.n 80027c8 <HAL_RCC_OscConfig+0x3c8>
- {
- return HAL_TIMEOUT;
- 80027c4: 2303 movs r3, #3
- 80027c6: e085 b.n 80028d4 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 80027c8: 4b44 ldr r3, [pc, #272] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 80027ca: 6f1b ldr r3, [r3, #112] ; 0x70
- 80027cc: f003 0302 and.w r3, r3, #2
- 80027d0: 2b00 cmp r3, #0
- 80027d2: d1ee bne.n 80027b2 <HAL_RCC_OscConfig+0x3b2>
- }
- }
- }
-
- /* Restore clock configuration if changed */
- if(pwrclkchanged == SET)
- 80027d4: 7dfb ldrb r3, [r7, #23]
- 80027d6: 2b01 cmp r3, #1
- 80027d8: d105 bne.n 80027e6 <HAL_RCC_OscConfig+0x3e6>
- {
- __HAL_RCC_PWR_CLK_DISABLE();
- 80027da: 4b40 ldr r3, [pc, #256] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 80027dc: 6c1b ldr r3, [r3, #64] ; 0x40
- 80027de: 4a3f ldr r2, [pc, #252] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 80027e0: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
- 80027e4: 6413 str r3, [r2, #64] ; 0x40
- }
- }
- /*-------------------------------- PLL Configuration -----------------------*/
- /* Check the parameters */
- assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
- if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- 80027e6: 687b ldr r3, [r7, #4]
- 80027e8: 699b ldr r3, [r3, #24]
- 80027ea: 2b00 cmp r3, #0
- 80027ec: d071 beq.n 80028d2 <HAL_RCC_OscConfig+0x4d2>
- {
- /* Check if the PLL is used as system clock or not */
- if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- 80027ee: 4b3b ldr r3, [pc, #236] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 80027f0: 689b ldr r3, [r3, #8]
- 80027f2: f003 030c and.w r3, r3, #12
- 80027f6: 2b08 cmp r3, #8
- 80027f8: d069 beq.n 80028ce <HAL_RCC_OscConfig+0x4ce>
- {
- if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- 80027fa: 687b ldr r3, [r7, #4]
- 80027fc: 699b ldr r3, [r3, #24]
- 80027fe: 2b02 cmp r3, #2
- 8002800: d14b bne.n 800289a <HAL_RCC_OscConfig+0x49a>
-#if defined (RCC_PLLCFGR_PLLR)
- assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
-#endif
-
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
- 8002802: 4b36 ldr r3, [pc, #216] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 8002804: 681b ldr r3, [r3, #0]
- 8002806: 4a35 ldr r2, [pc, #212] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 8002808: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 800280c: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 800280e: f7ff fadb bl 8001dc8 <HAL_GetTick>
- 8002812: 6138 str r0, [r7, #16]
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8002814: e008 b.n 8002828 <HAL_RCC_OscConfig+0x428>
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8002816: f7ff fad7 bl 8001dc8 <HAL_GetTick>
- 800281a: 4602 mov r2, r0
- 800281c: 693b ldr r3, [r7, #16]
- 800281e: 1ad3 subs r3, r2, r3
- 8002820: 2b02 cmp r3, #2
- 8002822: d901 bls.n 8002828 <HAL_RCC_OscConfig+0x428>
- {
- return HAL_TIMEOUT;
- 8002824: 2303 movs r3, #3
- 8002826: e055 b.n 80028d4 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8002828: 4b2c ldr r3, [pc, #176] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 800282a: 681b ldr r3, [r3, #0]
- 800282c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 8002830: 2b00 cmp r3, #0
- 8002832: d1f0 bne.n 8002816 <HAL_RCC_OscConfig+0x416>
- }
- }
-
- /* Configure the main PLL clock source, multiplication and division factors. */
-#if defined (RCC_PLLCFGR_PLLR)
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- 8002834: 687b ldr r3, [r7, #4]
- 8002836: 69da ldr r2, [r3, #28]
- 8002838: 687b ldr r3, [r7, #4]
- 800283a: 6a1b ldr r3, [r3, #32]
- 800283c: 431a orrs r2, r3
- 800283e: 687b ldr r3, [r7, #4]
- 8002840: 6a5b ldr r3, [r3, #36] ; 0x24
- 8002842: 019b lsls r3, r3, #6
- 8002844: 431a orrs r2, r3
- 8002846: 687b ldr r3, [r7, #4]
- 8002848: 6a9b ldr r3, [r3, #40] ; 0x28
- 800284a: 085b lsrs r3, r3, #1
- 800284c: 3b01 subs r3, #1
- 800284e: 041b lsls r3, r3, #16
- 8002850: 431a orrs r2, r3
- 8002852: 687b ldr r3, [r7, #4]
- 8002854: 6adb ldr r3, [r3, #44] ; 0x2c
- 8002856: 061b lsls r3, r3, #24
- 8002858: 431a orrs r2, r3
- 800285a: 687b ldr r3, [r7, #4]
- 800285c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800285e: 071b lsls r3, r3, #28
- 8002860: 491e ldr r1, [pc, #120] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 8002862: 4313 orrs r3, r2
- 8002864: 604b str r3, [r1, #4]
- RCC_OscInitStruct->PLL.PLLP,
- RCC_OscInitStruct->PLL.PLLQ);
-#endif
-
- /* Enable the main PLL. */
- __HAL_RCC_PLL_ENABLE();
- 8002866: 4b1d ldr r3, [pc, #116] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 8002868: 681b ldr r3, [r3, #0]
- 800286a: 4a1c ldr r2, [pc, #112] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 800286c: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
- 8002870: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002872: f7ff faa9 bl 8001dc8 <HAL_GetTick>
- 8002876: 6138 str r0, [r7, #16]
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 8002878: e008 b.n 800288c <HAL_RCC_OscConfig+0x48c>
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 800287a: f7ff faa5 bl 8001dc8 <HAL_GetTick>
- 800287e: 4602 mov r2, r0
- 8002880: 693b ldr r3, [r7, #16]
- 8002882: 1ad3 subs r3, r2, r3
- 8002884: 2b02 cmp r3, #2
- 8002886: d901 bls.n 800288c <HAL_RCC_OscConfig+0x48c>
- {
- return HAL_TIMEOUT;
- 8002888: 2303 movs r3, #3
- 800288a: e023 b.n 80028d4 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 800288c: 4b13 ldr r3, [pc, #76] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 800288e: 681b ldr r3, [r3, #0]
- 8002890: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 8002894: 2b00 cmp r3, #0
- 8002896: d0f0 beq.n 800287a <HAL_RCC_OscConfig+0x47a>
- 8002898: e01b b.n 80028d2 <HAL_RCC_OscConfig+0x4d2>
- }
- }
- else
- {
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
- 800289a: 4b10 ldr r3, [pc, #64] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 800289c: 681b ldr r3, [r3, #0]
- 800289e: 4a0f ldr r2, [pc, #60] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 80028a0: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 80028a4: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80028a6: f7ff fa8f bl 8001dc8 <HAL_GetTick>
- 80028aa: 6138 str r0, [r7, #16]
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 80028ac: e008 b.n 80028c0 <HAL_RCC_OscConfig+0x4c0>
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 80028ae: f7ff fa8b bl 8001dc8 <HAL_GetTick>
- 80028b2: 4602 mov r2, r0
- 80028b4: 693b ldr r3, [r7, #16]
- 80028b6: 1ad3 subs r3, r2, r3
- 80028b8: 2b02 cmp r3, #2
- 80028ba: d901 bls.n 80028c0 <HAL_RCC_OscConfig+0x4c0>
- {
- return HAL_TIMEOUT;
- 80028bc: 2303 movs r3, #3
- 80028be: e009 b.n 80028d4 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 80028c0: 4b06 ldr r3, [pc, #24] ; (80028dc <HAL_RCC_OscConfig+0x4dc>)
- 80028c2: 681b ldr r3, [r3, #0]
- 80028c4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80028c8: 2b00 cmp r3, #0
- 80028ca: d1f0 bne.n 80028ae <HAL_RCC_OscConfig+0x4ae>
- 80028cc: e001 b.n 80028d2 <HAL_RCC_OscConfig+0x4d2>
- }
- }
- }
- else
- {
- return HAL_ERROR;
- 80028ce: 2301 movs r3, #1
- 80028d0: e000 b.n 80028d4 <HAL_RCC_OscConfig+0x4d4>
- }
- }
- return HAL_OK;
- 80028d2: 2300 movs r3, #0
-}
- 80028d4: 4618 mov r0, r3
- 80028d6: 3718 adds r7, #24
- 80028d8: 46bd mov sp, r7
- 80028da: bd80 pop {r7, pc}
- 80028dc: 40023800 .word 0x40023800
- 80028e0: 40007000 .word 0x40007000
-
-080028e4 <HAL_RCC_ClockConfig>:
- * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
- * (for more details refer to section above "Initialization/de-initialization functions")
- * @retval None
- */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
-{
- 80028e4: b580 push {r7, lr}
- 80028e6: b084 sub sp, #16
- 80028e8: af00 add r7, sp, #0
- 80028ea: 6078 str r0, [r7, #4]
- 80028ec: 6039 str r1, [r7, #0]
- uint32_t tickstart = 0;
- 80028ee: 2300 movs r3, #0
- 80028f0: 60fb str r3, [r7, #12]
-
- /* Check Null pointer */
- if(RCC_ClkInitStruct == NULL)
- 80028f2: 687b ldr r3, [r7, #4]
- 80028f4: 2b00 cmp r3, #0
- 80028f6: d101 bne.n 80028fc <HAL_RCC_ClockConfig+0x18>
- {
- return HAL_ERROR;
- 80028f8: 2301 movs r3, #1
- 80028fa: e0ce b.n 8002a9a <HAL_RCC_ClockConfig+0x1b6>
- /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
- (HCLK) and the supply voltage of the device. */
-
- /* Increasing the CPU frequency */
- if(FLatency > __HAL_FLASH_GET_LATENCY())
- 80028fc: 4b69 ldr r3, [pc, #420] ; (8002aa4 <HAL_RCC_ClockConfig+0x1c0>)
- 80028fe: 681b ldr r3, [r3, #0]
- 8002900: f003 030f and.w r3, r3, #15
- 8002904: 683a ldr r2, [r7, #0]
- 8002906: 429a cmp r2, r3
- 8002908: d910 bls.n 800292c <HAL_RCC_ClockConfig+0x48>
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
- 800290a: 4b66 ldr r3, [pc, #408] ; (8002aa4 <HAL_RCC_ClockConfig+0x1c0>)
- 800290c: 681b ldr r3, [r3, #0]
- 800290e: f023 020f bic.w r2, r3, #15
- 8002912: 4964 ldr r1, [pc, #400] ; (8002aa4 <HAL_RCC_ClockConfig+0x1c0>)
- 8002914: 683b ldr r3, [r7, #0]
- 8002916: 4313 orrs r3, r2
- 8002918: 600b str r3, [r1, #0]
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 800291a: 4b62 ldr r3, [pc, #392] ; (8002aa4 <HAL_RCC_ClockConfig+0x1c0>)
- 800291c: 681b ldr r3, [r3, #0]
- 800291e: f003 030f and.w r3, r3, #15
- 8002922: 683a ldr r2, [r7, #0]
- 8002924: 429a cmp r2, r3
- 8002926: d001 beq.n 800292c <HAL_RCC_ClockConfig+0x48>
- {
- return HAL_ERROR;
- 8002928: 2301 movs r3, #1
- 800292a: e0b6 b.n 8002a9a <HAL_RCC_ClockConfig+0x1b6>
- }
- }
-
- /*-------------------------- HCLK Configuration --------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- 800292c: 687b ldr r3, [r7, #4]
- 800292e: 681b ldr r3, [r3, #0]
- 8002930: f003 0302 and.w r3, r3, #2
- 8002934: 2b00 cmp r3, #0
- 8002936: d020 beq.n 800297a <HAL_RCC_ClockConfig+0x96>
- {
- /* Set the highest APBx dividers in order to ensure that we do not go through
- a non-spec phase whatever we decrease or increase HCLK. */
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8002938: 687b ldr r3, [r7, #4]
- 800293a: 681b ldr r3, [r3, #0]
- 800293c: f003 0304 and.w r3, r3, #4
- 8002940: 2b00 cmp r3, #0
- 8002942: d005 beq.n 8002950 <HAL_RCC_ClockConfig+0x6c>
- {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
- 8002944: 4b58 ldr r3, [pc, #352] ; (8002aa8 <HAL_RCC_ClockConfig+0x1c4>)
- 8002946: 689b ldr r3, [r3, #8]
- 8002948: 4a57 ldr r2, [pc, #348] ; (8002aa8 <HAL_RCC_ClockConfig+0x1c4>)
- 800294a: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
- 800294e: 6093 str r3, [r2, #8]
- }
-
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 8002950: 687b ldr r3, [r7, #4]
- 8002952: 681b ldr r3, [r3, #0]
- 8002954: f003 0308 and.w r3, r3, #8
- 8002958: 2b00 cmp r3, #0
- 800295a: d005 beq.n 8002968 <HAL_RCC_ClockConfig+0x84>
- {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
- 800295c: 4b52 ldr r3, [pc, #328] ; (8002aa8 <HAL_RCC_ClockConfig+0x1c4>)
- 800295e: 689b ldr r3, [r3, #8]
- 8002960: 4a51 ldr r2, [pc, #324] ; (8002aa8 <HAL_RCC_ClockConfig+0x1c4>)
- 8002962: f443 4360 orr.w r3, r3, #57344 ; 0xe000
- 8002966: 6093 str r3, [r2, #8]
- }
-
- /* Set the new HCLK clock divider */
- assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- 8002968: 4b4f ldr r3, [pc, #316] ; (8002aa8 <HAL_RCC_ClockConfig+0x1c4>)
- 800296a: 689b ldr r3, [r3, #8]
- 800296c: f023 02f0 bic.w r2, r3, #240 ; 0xf0
- 8002970: 687b ldr r3, [r7, #4]
- 8002972: 689b ldr r3, [r3, #8]
- 8002974: 494c ldr r1, [pc, #304] ; (8002aa8 <HAL_RCC_ClockConfig+0x1c4>)
- 8002976: 4313 orrs r3, r2
- 8002978: 608b str r3, [r1, #8]
- }
-
- /*------------------------- SYSCLK Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- 800297a: 687b ldr r3, [r7, #4]
- 800297c: 681b ldr r3, [r3, #0]
- 800297e: f003 0301 and.w r3, r3, #1
- 8002982: 2b00 cmp r3, #0
- 8002984: d040 beq.n 8002a08 <HAL_RCC_ClockConfig+0x124>
- {
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
- /* HSE is selected as System Clock Source */
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- 8002986: 687b ldr r3, [r7, #4]
- 8002988: 685b ldr r3, [r3, #4]
- 800298a: 2b01 cmp r3, #1
- 800298c: d107 bne.n 800299e <HAL_RCC_ClockConfig+0xba>
- {
- /* Check the HSE ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 800298e: 4b46 ldr r3, [pc, #280] ; (8002aa8 <HAL_RCC_ClockConfig+0x1c4>)
- 8002990: 681b ldr r3, [r3, #0]
- 8002992: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8002996: 2b00 cmp r3, #0
- 8002998: d115 bne.n 80029c6 <HAL_RCC_ClockConfig+0xe2>
- {
- return HAL_ERROR;
- 800299a: 2301 movs r3, #1
- 800299c: e07d b.n 8002a9a <HAL_RCC_ClockConfig+0x1b6>
- }
- }
- /* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- 800299e: 687b ldr r3, [r7, #4]
- 80029a0: 685b ldr r3, [r3, #4]
- 80029a2: 2b02 cmp r3, #2
- 80029a4: d107 bne.n 80029b6 <HAL_RCC_ClockConfig+0xd2>
- {
- /* Check the PLL ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 80029a6: 4b40 ldr r3, [pc, #256] ; (8002aa8 <HAL_RCC_ClockConfig+0x1c4>)
- 80029a8: 681b ldr r3, [r3, #0]
- 80029aa: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80029ae: 2b00 cmp r3, #0
- 80029b0: d109 bne.n 80029c6 <HAL_RCC_ClockConfig+0xe2>
- {
- return HAL_ERROR;
- 80029b2: 2301 movs r3, #1
- 80029b4: e071 b.n 8002a9a <HAL_RCC_ClockConfig+0x1b6>
- }
- /* HSI is selected as System Clock Source */
- else
- {
- /* Check the HSI ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80029b6: 4b3c ldr r3, [pc, #240] ; (8002aa8 <HAL_RCC_ClockConfig+0x1c4>)
- 80029b8: 681b ldr r3, [r3, #0]
- 80029ba: f003 0302 and.w r3, r3, #2
- 80029be: 2b00 cmp r3, #0
- 80029c0: d101 bne.n 80029c6 <HAL_RCC_ClockConfig+0xe2>
- {
- return HAL_ERROR;
- 80029c2: 2301 movs r3, #1
- 80029c4: e069 b.n 8002a9a <HAL_RCC_ClockConfig+0x1b6>
- }
- }
-
- __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
- 80029c6: 4b38 ldr r3, [pc, #224] ; (8002aa8 <HAL_RCC_ClockConfig+0x1c4>)
- 80029c8: 689b ldr r3, [r3, #8]
- 80029ca: f023 0203 bic.w r2, r3, #3
- 80029ce: 687b ldr r3, [r7, #4]
- 80029d0: 685b ldr r3, [r3, #4]
- 80029d2: 4935 ldr r1, [pc, #212] ; (8002aa8 <HAL_RCC_ClockConfig+0x1c4>)
- 80029d4: 4313 orrs r3, r2
- 80029d6: 608b str r3, [r1, #8]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80029d8: f7ff f9f6 bl 8001dc8 <HAL_GetTick>
- 80029dc: 60f8 str r0, [r7, #12]
-
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 80029de: e00a b.n 80029f6 <HAL_RCC_ClockConfig+0x112>
- {
- if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- 80029e0: f7ff f9f2 bl 8001dc8 <HAL_GetTick>
- 80029e4: 4602 mov r2, r0
- 80029e6: 68fb ldr r3, [r7, #12]
- 80029e8: 1ad3 subs r3, r2, r3
- 80029ea: f241 3288 movw r2, #5000 ; 0x1388
- 80029ee: 4293 cmp r3, r2
- 80029f0: d901 bls.n 80029f6 <HAL_RCC_ClockConfig+0x112>
- {
- return HAL_TIMEOUT;
- 80029f2: 2303 movs r3, #3
- 80029f4: e051 b.n 8002a9a <HAL_RCC_ClockConfig+0x1b6>
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 80029f6: 4b2c ldr r3, [pc, #176] ; (8002aa8 <HAL_RCC_ClockConfig+0x1c4>)
- 80029f8: 689b ldr r3, [r3, #8]
- 80029fa: f003 020c and.w r2, r3, #12
- 80029fe: 687b ldr r3, [r7, #4]
- 8002a00: 685b ldr r3, [r3, #4]
- 8002a02: 009b lsls r3, r3, #2
- 8002a04: 429a cmp r2, r3
- 8002a06: d1eb bne.n 80029e0 <HAL_RCC_ClockConfig+0xfc>
- }
- }
- }
-
- /* Decreasing the number of wait states because of lower CPU frequency */
- if(FLatency < __HAL_FLASH_GET_LATENCY())
- 8002a08: 4b26 ldr r3, [pc, #152] ; (8002aa4 <HAL_RCC_ClockConfig+0x1c0>)
- 8002a0a: 681b ldr r3, [r3, #0]
- 8002a0c: f003 030f and.w r3, r3, #15
- 8002a10: 683a ldr r2, [r7, #0]
- 8002a12: 429a cmp r2, r3
- 8002a14: d210 bcs.n 8002a38 <HAL_RCC_ClockConfig+0x154>
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
- 8002a16: 4b23 ldr r3, [pc, #140] ; (8002aa4 <HAL_RCC_ClockConfig+0x1c0>)
- 8002a18: 681b ldr r3, [r3, #0]
- 8002a1a: f023 020f bic.w r2, r3, #15
- 8002a1e: 4921 ldr r1, [pc, #132] ; (8002aa4 <HAL_RCC_ClockConfig+0x1c0>)
- 8002a20: 683b ldr r3, [r7, #0]
- 8002a22: 4313 orrs r3, r2
- 8002a24: 600b str r3, [r1, #0]
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 8002a26: 4b1f ldr r3, [pc, #124] ; (8002aa4 <HAL_RCC_ClockConfig+0x1c0>)
- 8002a28: 681b ldr r3, [r3, #0]
- 8002a2a: f003 030f and.w r3, r3, #15
- 8002a2e: 683a ldr r2, [r7, #0]
- 8002a30: 429a cmp r2, r3
- 8002a32: d001 beq.n 8002a38 <HAL_RCC_ClockConfig+0x154>
- {
- return HAL_ERROR;
- 8002a34: 2301 movs r3, #1
- 8002a36: e030 b.n 8002a9a <HAL_RCC_ClockConfig+0x1b6>
- }
- }
-
- /*-------------------------- PCLK1 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8002a38: 687b ldr r3, [r7, #4]
- 8002a3a: 681b ldr r3, [r3, #0]
- 8002a3c: f003 0304 and.w r3, r3, #4
- 8002a40: 2b00 cmp r3, #0
- 8002a42: d008 beq.n 8002a56 <HAL_RCC_ClockConfig+0x172>
- {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
- 8002a44: 4b18 ldr r3, [pc, #96] ; (8002aa8 <HAL_RCC_ClockConfig+0x1c4>)
- 8002a46: 689b ldr r3, [r3, #8]
- 8002a48: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
- 8002a4c: 687b ldr r3, [r7, #4]
- 8002a4e: 68db ldr r3, [r3, #12]
- 8002a50: 4915 ldr r1, [pc, #84] ; (8002aa8 <HAL_RCC_ClockConfig+0x1c4>)
- 8002a52: 4313 orrs r3, r2
- 8002a54: 608b str r3, [r1, #8]
- }
-
- /*-------------------------- PCLK2 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 8002a56: 687b ldr r3, [r7, #4]
- 8002a58: 681b ldr r3, [r3, #0]
- 8002a5a: f003 0308 and.w r3, r3, #8
- 8002a5e: 2b00 cmp r3, #0
- 8002a60: d009 beq.n 8002a76 <HAL_RCC_ClockConfig+0x192>
- {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
- 8002a62: 4b11 ldr r3, [pc, #68] ; (8002aa8 <HAL_RCC_ClockConfig+0x1c4>)
- 8002a64: 689b ldr r3, [r3, #8]
- 8002a66: f423 4260 bic.w r2, r3, #57344 ; 0xe000
- 8002a6a: 687b ldr r3, [r7, #4]
- 8002a6c: 691b ldr r3, [r3, #16]
- 8002a6e: 00db lsls r3, r3, #3
- 8002a70: 490d ldr r1, [pc, #52] ; (8002aa8 <HAL_RCC_ClockConfig+0x1c4>)
- 8002a72: 4313 orrs r3, r2
- 8002a74: 608b str r3, [r1, #8]
- }
-
- /* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
- 8002a76: f000 f81d bl 8002ab4 <HAL_RCC_GetSysClockFreq>
- 8002a7a: 4601 mov r1, r0
- 8002a7c: 4b0a ldr r3, [pc, #40] ; (8002aa8 <HAL_RCC_ClockConfig+0x1c4>)
- 8002a7e: 689b ldr r3, [r3, #8]
- 8002a80: 091b lsrs r3, r3, #4
- 8002a82: f003 030f and.w r3, r3, #15
- 8002a86: 4a09 ldr r2, [pc, #36] ; (8002aac <HAL_RCC_ClockConfig+0x1c8>)
- 8002a88: 5cd3 ldrb r3, [r2, r3]
- 8002a8a: fa21 f303 lsr.w r3, r1, r3
- 8002a8e: 4a08 ldr r2, [pc, #32] ; (8002ab0 <HAL_RCC_ClockConfig+0x1cc>)
- 8002a90: 6013 str r3, [r2, #0]
-
- /* Configure the source of time base considering new system clocks settings*/
- HAL_InitTick (TICK_INT_PRIORITY);
- 8002a92: 2000 movs r0, #0
- 8002a94: f7ff f954 bl 8001d40 <HAL_InitTick>
-
- return HAL_OK;
- 8002a98: 2300 movs r3, #0
-}
- 8002a9a: 4618 mov r0, r3
- 8002a9c: 3710 adds r7, #16
- 8002a9e: 46bd mov sp, r7
- 8002aa0: bd80 pop {r7, pc}
- 8002aa2: bf00 nop
- 8002aa4: 40023c00 .word 0x40023c00
- 8002aa8: 40023800 .word 0x40023800
- 8002aac: 080055d8 .word 0x080055d8
- 8002ab0: 20000004 .word 0x20000004
-
-08002ab4 <HAL_RCC_GetSysClockFreq>:
- *
- *
- * @retval SYSCLK frequency
- */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
- 8002ab4: b5f0 push {r4, r5, r6, r7, lr}
- 8002ab6: b085 sub sp, #20
- 8002ab8: af00 add r7, sp, #0
- uint32_t pllm = 0, pllvco = 0, pllp = 0;
- 8002aba: 2300 movs r3, #0
- 8002abc: 607b str r3, [r7, #4]
- 8002abe: 2300 movs r3, #0
- 8002ac0: 60fb str r3, [r7, #12]
- 8002ac2: 2300 movs r3, #0
- 8002ac4: 603b str r3, [r7, #0]
- uint32_t sysclockfreq = 0;
- 8002ac6: 2300 movs r3, #0
- 8002ac8: 60bb str r3, [r7, #8]
-
- /* Get SYSCLK source -------------------------------------------------------*/
- switch (RCC->CFGR & RCC_CFGR_SWS)
- 8002aca: 4b50 ldr r3, [pc, #320] ; (8002c0c <HAL_RCC_GetSysClockFreq+0x158>)
- 8002acc: 689b ldr r3, [r3, #8]
- 8002ace: f003 030c and.w r3, r3, #12
- 8002ad2: 2b04 cmp r3, #4
- 8002ad4: d007 beq.n 8002ae6 <HAL_RCC_GetSysClockFreq+0x32>
- 8002ad6: 2b08 cmp r3, #8
- 8002ad8: d008 beq.n 8002aec <HAL_RCC_GetSysClockFreq+0x38>
- 8002ada: 2b00 cmp r3, #0
- 8002adc: f040 808d bne.w 8002bfa <HAL_RCC_GetSysClockFreq+0x146>
- {
- case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
- {
- sysclockfreq = HSI_VALUE;
- 8002ae0: 4b4b ldr r3, [pc, #300] ; (8002c10 <HAL_RCC_GetSysClockFreq+0x15c>)
- 8002ae2: 60bb str r3, [r7, #8]
- break;
- 8002ae4: e08c b.n 8002c00 <HAL_RCC_GetSysClockFreq+0x14c>
- }
- case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
- {
- sysclockfreq = HSE_VALUE;
- 8002ae6: 4b4b ldr r3, [pc, #300] ; (8002c14 <HAL_RCC_GetSysClockFreq+0x160>)
- 8002ae8: 60bb str r3, [r7, #8]
- break;
- 8002aea: e089 b.n 8002c00 <HAL_RCC_GetSysClockFreq+0x14c>
- }
- case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
- {
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLP */
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
- 8002aec: 4b47 ldr r3, [pc, #284] ; (8002c0c <HAL_RCC_GetSysClockFreq+0x158>)
- 8002aee: 685b ldr r3, [r3, #4]
- 8002af0: f003 033f and.w r3, r3, #63 ; 0x3f
- 8002af4: 607b str r3, [r7, #4]
- if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
- 8002af6: 4b45 ldr r3, [pc, #276] ; (8002c0c <HAL_RCC_GetSysClockFreq+0x158>)
- 8002af8: 685b ldr r3, [r3, #4]
- 8002afa: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8002afe: 2b00 cmp r3, #0
- 8002b00: d023 beq.n 8002b4a <HAL_RCC_GetSysClockFreq+0x96>
- {
- /* HSE used as PLL clock source */
- pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 8002b02: 4b42 ldr r3, [pc, #264] ; (8002c0c <HAL_RCC_GetSysClockFreq+0x158>)
- 8002b04: 685b ldr r3, [r3, #4]
- 8002b06: 099b lsrs r3, r3, #6
- 8002b08: f04f 0400 mov.w r4, #0
- 8002b0c: f240 11ff movw r1, #511 ; 0x1ff
- 8002b10: f04f 0200 mov.w r2, #0
- 8002b14: ea03 0501 and.w r5, r3, r1
- 8002b18: ea04 0602 and.w r6, r4, r2
- 8002b1c: 4a3d ldr r2, [pc, #244] ; (8002c14 <HAL_RCC_GetSysClockFreq+0x160>)
- 8002b1e: fb02 f106 mul.w r1, r2, r6
- 8002b22: 2200 movs r2, #0
- 8002b24: fb02 f205 mul.w r2, r2, r5
- 8002b28: 440a add r2, r1
- 8002b2a: 493a ldr r1, [pc, #232] ; (8002c14 <HAL_RCC_GetSysClockFreq+0x160>)
- 8002b2c: fba5 0101 umull r0, r1, r5, r1
- 8002b30: 1853 adds r3, r2, r1
- 8002b32: 4619 mov r1, r3
- 8002b34: 687b ldr r3, [r7, #4]
- 8002b36: f04f 0400 mov.w r4, #0
- 8002b3a: 461a mov r2, r3
- 8002b3c: 4623 mov r3, r4
- 8002b3e: f7fd fb7b bl 8000238 <__aeabi_uldivmod>
- 8002b42: 4603 mov r3, r0
- 8002b44: 460c mov r4, r1
- 8002b46: 60fb str r3, [r7, #12]
- 8002b48: e049 b.n 8002bde <HAL_RCC_GetSysClockFreq+0x12a>
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 8002b4a: 4b30 ldr r3, [pc, #192] ; (8002c0c <HAL_RCC_GetSysClockFreq+0x158>)
- 8002b4c: 685b ldr r3, [r3, #4]
- 8002b4e: 099b lsrs r3, r3, #6
- 8002b50: f04f 0400 mov.w r4, #0
- 8002b54: f240 11ff movw r1, #511 ; 0x1ff
- 8002b58: f04f 0200 mov.w r2, #0
- 8002b5c: ea03 0501 and.w r5, r3, r1
- 8002b60: ea04 0602 and.w r6, r4, r2
- 8002b64: 4629 mov r1, r5
- 8002b66: 4632 mov r2, r6
- 8002b68: f04f 0300 mov.w r3, #0
- 8002b6c: f04f 0400 mov.w r4, #0
- 8002b70: 0154 lsls r4, r2, #5
- 8002b72: ea44 64d1 orr.w r4, r4, r1, lsr #27
- 8002b76: 014b lsls r3, r1, #5
- 8002b78: 4619 mov r1, r3
- 8002b7a: 4622 mov r2, r4
- 8002b7c: 1b49 subs r1, r1, r5
- 8002b7e: eb62 0206 sbc.w r2, r2, r6
- 8002b82: f04f 0300 mov.w r3, #0
- 8002b86: f04f 0400 mov.w r4, #0
- 8002b8a: 0194 lsls r4, r2, #6
- 8002b8c: ea44 6491 orr.w r4, r4, r1, lsr #26
- 8002b90: 018b lsls r3, r1, #6
- 8002b92: 1a5b subs r3, r3, r1
- 8002b94: eb64 0402 sbc.w r4, r4, r2
- 8002b98: f04f 0100 mov.w r1, #0
- 8002b9c: f04f 0200 mov.w r2, #0
- 8002ba0: 00e2 lsls r2, r4, #3
- 8002ba2: ea42 7253 orr.w r2, r2, r3, lsr #29
- 8002ba6: 00d9 lsls r1, r3, #3
- 8002ba8: 460b mov r3, r1
- 8002baa: 4614 mov r4, r2
- 8002bac: 195b adds r3, r3, r5
- 8002bae: eb44 0406 adc.w r4, r4, r6
- 8002bb2: f04f 0100 mov.w r1, #0
- 8002bb6: f04f 0200 mov.w r2, #0
- 8002bba: 02a2 lsls r2, r4, #10
- 8002bbc: ea42 5293 orr.w r2, r2, r3, lsr #22
- 8002bc0: 0299 lsls r1, r3, #10
- 8002bc2: 460b mov r3, r1
- 8002bc4: 4614 mov r4, r2
- 8002bc6: 4618 mov r0, r3
- 8002bc8: 4621 mov r1, r4
- 8002bca: 687b ldr r3, [r7, #4]
- 8002bcc: f04f 0400 mov.w r4, #0
- 8002bd0: 461a mov r2, r3
- 8002bd2: 4623 mov r3, r4
- 8002bd4: f7fd fb30 bl 8000238 <__aeabi_uldivmod>
- 8002bd8: 4603 mov r3, r0
- 8002bda: 460c mov r4, r1
- 8002bdc: 60fb str r3, [r7, #12]
- }
- pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2);
- 8002bde: 4b0b ldr r3, [pc, #44] ; (8002c0c <HAL_RCC_GetSysClockFreq+0x158>)
- 8002be0: 685b ldr r3, [r3, #4]
- 8002be2: 0c1b lsrs r3, r3, #16
- 8002be4: f003 0303 and.w r3, r3, #3
- 8002be8: 3301 adds r3, #1
- 8002bea: 005b lsls r3, r3, #1
- 8002bec: 603b str r3, [r7, #0]
-
- sysclockfreq = pllvco/pllp;
- 8002bee: 68fa ldr r2, [r7, #12]
- 8002bf0: 683b ldr r3, [r7, #0]
- 8002bf2: fbb2 f3f3 udiv r3, r2, r3
- 8002bf6: 60bb str r3, [r7, #8]
- break;
- 8002bf8: e002 b.n 8002c00 <HAL_RCC_GetSysClockFreq+0x14c>
- }
- default:
- {
- sysclockfreq = HSI_VALUE;
- 8002bfa: 4b05 ldr r3, [pc, #20] ; (8002c10 <HAL_RCC_GetSysClockFreq+0x15c>)
- 8002bfc: 60bb str r3, [r7, #8]
- break;
- 8002bfe: bf00 nop
- }
- }
- return sysclockfreq;
- 8002c00: 68bb ldr r3, [r7, #8]
-}
- 8002c02: 4618 mov r0, r3
- 8002c04: 3714 adds r7, #20
- 8002c06: 46bd mov sp, r7
- 8002c08: bdf0 pop {r4, r5, r6, r7, pc}
- 8002c0a: bf00 nop
- 8002c0c: 40023800 .word 0x40023800
- 8002c10: 00f42400 .word 0x00f42400
- 8002c14: 017d7840 .word 0x017d7840
-
-08002c18 <HAL_RCC_GetHCLKFreq>:
- * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
- * @retval HCLK frequency
- */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
- 8002c18: b480 push {r7}
- 8002c1a: af00 add r7, sp, #0
- return SystemCoreClock;
- 8002c1c: 4b03 ldr r3, [pc, #12] ; (8002c2c <HAL_RCC_GetHCLKFreq+0x14>)
- 8002c1e: 681b ldr r3, [r3, #0]
-}
- 8002c20: 4618 mov r0, r3
- 8002c22: 46bd mov sp, r7
- 8002c24: f85d 7b04 ldr.w r7, [sp], #4
- 8002c28: 4770 bx lr
- 8002c2a: bf00 nop
- 8002c2c: 20000004 .word 0x20000004
-
-08002c30 <HAL_RCC_GetPCLK1Freq>:
- * @note Each time PCLK1 changes, this function must be called to update the
- * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK1 frequency
- */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
- 8002c30: b580 push {r7, lr}
- 8002c32: af00 add r7, sp, #0
- /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
- 8002c34: f7ff fff0 bl 8002c18 <HAL_RCC_GetHCLKFreq>
- 8002c38: 4601 mov r1, r0
- 8002c3a: 4b05 ldr r3, [pc, #20] ; (8002c50 <HAL_RCC_GetPCLK1Freq+0x20>)
- 8002c3c: 689b ldr r3, [r3, #8]
- 8002c3e: 0a9b lsrs r3, r3, #10
- 8002c40: f003 0307 and.w r3, r3, #7
- 8002c44: 4a03 ldr r2, [pc, #12] ; (8002c54 <HAL_RCC_GetPCLK1Freq+0x24>)
- 8002c46: 5cd3 ldrb r3, [r2, r3]
- 8002c48: fa21 f303 lsr.w r3, r1, r3
-}
- 8002c4c: 4618 mov r0, r3
- 8002c4e: bd80 pop {r7, pc}
- 8002c50: 40023800 .word 0x40023800
- 8002c54: 080055e8 .word 0x080055e8
-
-08002c58 <HAL_RCC_GetPCLK2Freq>:
- * @note Each time PCLK2 changes, this function must be called to update the
- * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK2 frequency
- */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
-{
- 8002c58: b580 push {r7, lr}
- 8002c5a: af00 add r7, sp, #0
- /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
- 8002c5c: f7ff ffdc bl 8002c18 <HAL_RCC_GetHCLKFreq>
- 8002c60: 4601 mov r1, r0
- 8002c62: 4b05 ldr r3, [pc, #20] ; (8002c78 <HAL_RCC_GetPCLK2Freq+0x20>)
- 8002c64: 689b ldr r3, [r3, #8]
- 8002c66: 0b5b lsrs r3, r3, #13
- 8002c68: f003 0307 and.w r3, r3, #7
- 8002c6c: 4a03 ldr r2, [pc, #12] ; (8002c7c <HAL_RCC_GetPCLK2Freq+0x24>)
- 8002c6e: 5cd3 ldrb r3, [r2, r3]
- 8002c70: fa21 f303 lsr.w r3, r1, r3
-}
- 8002c74: 4618 mov r0, r3
- 8002c76: bd80 pop {r7, pc}
- 8002c78: 40023800 .word 0x40023800
- 8002c7c: 080055e8 .word 0x080055e8
-
-08002c80 <HAL_RCCEx_PeriphCLKConfig>:
- * the backup registers) are set to their reset values.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
-{
- 8002c80: b580 push {r7, lr}
- 8002c82: b088 sub sp, #32
- 8002c84: af00 add r7, sp, #0
- 8002c86: 6078 str r0, [r7, #4]
- uint32_t tickstart = 0;
- 8002c88: 2300 movs r3, #0
- 8002c8a: 617b str r3, [r7, #20]
- uint32_t tmpreg0 = 0;
- 8002c8c: 2300 movs r3, #0
- 8002c8e: 613b str r3, [r7, #16]
- uint32_t tmpreg1 = 0;
- 8002c90: 2300 movs r3, #0
- 8002c92: 60fb str r3, [r7, #12]
- uint32_t plli2sused = 0;
- 8002c94: 2300 movs r3, #0
- 8002c96: 61fb str r3, [r7, #28]
- uint32_t pllsaiused = 0;
- 8002c98: 2300 movs r3, #0
- 8002c9a: 61bb str r3, [r7, #24]
-
- /* Check the parameters */
- assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
- /*----------------------------------- I2S configuration ----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
- 8002c9c: 687b ldr r3, [r7, #4]
- 8002c9e: 681b ldr r3, [r3, #0]
- 8002ca0: f003 0301 and.w r3, r3, #1
- 8002ca4: 2b00 cmp r3, #0
- 8002ca6: d012 beq.n 8002cce <HAL_RCCEx_PeriphCLKConfig+0x4e>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
-
- /* Configure I2S Clock source */
- __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
- 8002ca8: 4b69 ldr r3, [pc, #420] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002caa: 689b ldr r3, [r3, #8]
- 8002cac: 4a68 ldr r2, [pc, #416] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002cae: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
- 8002cb2: 6093 str r3, [r2, #8]
- 8002cb4: 4b66 ldr r3, [pc, #408] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002cb6: 689a ldr r2, [r3, #8]
- 8002cb8: 687b ldr r3, [r7, #4]
- 8002cba: 6b5b ldr r3, [r3, #52] ; 0x34
- 8002cbc: 4964 ldr r1, [pc, #400] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002cbe: 4313 orrs r3, r2
- 8002cc0: 608b str r3, [r1, #8]
-
- /* Enable the PLLI2S when it's used as clock source for I2S */
- if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
- 8002cc2: 687b ldr r3, [r7, #4]
- 8002cc4: 6b5b ldr r3, [r3, #52] ; 0x34
- 8002cc6: 2b00 cmp r3, #0
- 8002cc8: d101 bne.n 8002cce <HAL_RCCEx_PeriphCLKConfig+0x4e>
- {
- plli2sused = 1;
- 8002cca: 2301 movs r3, #1
- 8002ccc: 61fb str r3, [r7, #28]
- }
- }
-
- /*------------------------------------ SAI1 configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
- 8002cce: 687b ldr r3, [r7, #4]
- 8002cd0: 681b ldr r3, [r3, #0]
- 8002cd2: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 8002cd6: 2b00 cmp r3, #0
- 8002cd8: d017 beq.n 8002d0a <HAL_RCCEx_PeriphCLKConfig+0x8a>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
-
- /* Configure SAI1 Clock source */
- __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
- 8002cda: 4b5d ldr r3, [pc, #372] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002cdc: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002ce0: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
- 8002ce4: 687b ldr r3, [r7, #4]
- 8002ce6: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8002ce8: 4959 ldr r1, [pc, #356] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002cea: 4313 orrs r3, r2
- 8002cec: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- /* Enable the PLLI2S when it's used as clock source for SAI */
- if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
- 8002cf0: 687b ldr r3, [r7, #4]
- 8002cf2: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8002cf4: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 8002cf8: d101 bne.n 8002cfe <HAL_RCCEx_PeriphCLKConfig+0x7e>
- {
- plli2sused = 1;
- 8002cfa: 2301 movs r3, #1
- 8002cfc: 61fb str r3, [r7, #28]
- }
- /* Enable the PLLSAI when it's used as clock source for SAI */
- if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
- 8002cfe: 687b ldr r3, [r7, #4]
- 8002d00: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8002d02: 2b00 cmp r3, #0
- 8002d04: d101 bne.n 8002d0a <HAL_RCCEx_PeriphCLKConfig+0x8a>
- {
- pllsaiused = 1;
- 8002d06: 2301 movs r3, #1
- 8002d08: 61bb str r3, [r7, #24]
- }
- }
-
- /*------------------------------------ SAI2 configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
- 8002d0a: 687b ldr r3, [r7, #4]
- 8002d0c: 681b ldr r3, [r3, #0]
- 8002d0e: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- 8002d12: 2b00 cmp r3, #0
- 8002d14: d017 beq.n 8002d46 <HAL_RCCEx_PeriphCLKConfig+0xc6>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
-
- /* Configure SAI2 Clock source */
- __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
- 8002d16: 4b4e ldr r3, [pc, #312] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002d18: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002d1c: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
- 8002d20: 687b ldr r3, [r7, #4]
- 8002d22: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002d24: 494a ldr r1, [pc, #296] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002d26: 4313 orrs r3, r2
- 8002d28: f8c1 308c str.w r3, [r1, #140] ; 0x8c
-
- /* Enable the PLLI2S when it's used as clock source for SAI */
- if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
- 8002d2c: 687b ldr r3, [r7, #4]
- 8002d2e: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002d30: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8002d34: d101 bne.n 8002d3a <HAL_RCCEx_PeriphCLKConfig+0xba>
- {
- plli2sused = 1;
- 8002d36: 2301 movs r3, #1
- 8002d38: 61fb str r3, [r7, #28]
- }
- /* Enable the PLLSAI when it's used as clock source for SAI */
- if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
- 8002d3a: 687b ldr r3, [r7, #4]
- 8002d3c: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002d3e: 2b00 cmp r3, #0
- 8002d40: d101 bne.n 8002d46 <HAL_RCCEx_PeriphCLKConfig+0xc6>
- {
- pllsaiused = 1;
- 8002d42: 2301 movs r3, #1
- 8002d44: 61bb str r3, [r7, #24]
- }
- }
-
- /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
- 8002d46: 687b ldr r3, [r7, #4]
- 8002d48: 681b ldr r3, [r3, #0]
- 8002d4a: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
- 8002d4e: 2b00 cmp r3, #0
- 8002d50: d001 beq.n 8002d56 <HAL_RCCEx_PeriphCLKConfig+0xd6>
- {
- plli2sused = 1;
- 8002d52: 2301 movs r3, #1
- 8002d54: 61fb str r3, [r7, #28]
- }
-
- /*------------------------------------ RTC configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
- 8002d56: 687b ldr r3, [r7, #4]
- 8002d58: 681b ldr r3, [r3, #0]
- 8002d5a: f003 0320 and.w r3, r3, #32
- 8002d5e: 2b00 cmp r3, #0
- 8002d60: f000 808b beq.w 8002e7a <HAL_RCCEx_PeriphCLKConfig+0x1fa>
- {
- /* Check for RTC Parameters used to output RTCCLK */
- assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
- 8002d64: 4b3a ldr r3, [pc, #232] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002d66: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002d68: 4a39 ldr r2, [pc, #228] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002d6a: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8002d6e: 6413 str r3, [r2, #64] ; 0x40
- 8002d70: 4b37 ldr r3, [pc, #220] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002d72: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002d74: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8002d78: 60bb str r3, [r7, #8]
- 8002d7a: 68bb ldr r3, [r7, #8]
-
- /* Enable write access to Backup domain */
- PWR->CR1 |= PWR_CR1_DBP;
- 8002d7c: 4b35 ldr r3, [pc, #212] ; (8002e54 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8002d7e: 681b ldr r3, [r3, #0]
- 8002d80: 4a34 ldr r2, [pc, #208] ; (8002e54 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8002d82: f443 7380 orr.w r3, r3, #256 ; 0x100
- 8002d86: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002d88: f7ff f81e bl 8001dc8 <HAL_GetTick>
- 8002d8c: 6178 str r0, [r7, #20]
-
- /* Wait for Backup domain Write protection disable */
- while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- 8002d8e: e008 b.n 8002da2 <HAL_RCCEx_PeriphCLKConfig+0x122>
- {
- if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- 8002d90: f7ff f81a bl 8001dc8 <HAL_GetTick>
- 8002d94: 4602 mov r2, r0
- 8002d96: 697b ldr r3, [r7, #20]
- 8002d98: 1ad3 subs r3, r2, r3
- 8002d9a: 2b64 cmp r3, #100 ; 0x64
- 8002d9c: d901 bls.n 8002da2 <HAL_RCCEx_PeriphCLKConfig+0x122>
- {
- return HAL_TIMEOUT;
- 8002d9e: 2303 movs r3, #3
- 8002da0: e38d b.n 80034be <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- 8002da2: 4b2c ldr r3, [pc, #176] ; (8002e54 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8002da4: 681b ldr r3, [r3, #0]
- 8002da6: f403 7380 and.w r3, r3, #256 ; 0x100
- 8002daa: 2b00 cmp r3, #0
- 8002dac: d0f0 beq.n 8002d90 <HAL_RCCEx_PeriphCLKConfig+0x110>
- }
- }
-
- /* Reset the Backup domain only if the RTC Clock source selection is modified */
- tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
- 8002dae: 4b28 ldr r3, [pc, #160] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002db0: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002db2: f403 7340 and.w r3, r3, #768 ; 0x300
- 8002db6: 613b str r3, [r7, #16]
-
- if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
- 8002db8: 693b ldr r3, [r7, #16]
- 8002dba: 2b00 cmp r3, #0
- 8002dbc: d035 beq.n 8002e2a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- 8002dbe: 687b ldr r3, [r7, #4]
- 8002dc0: 6b1b ldr r3, [r3, #48] ; 0x30
- 8002dc2: f403 7340 and.w r3, r3, #768 ; 0x300
- 8002dc6: 693a ldr r2, [r7, #16]
- 8002dc8: 429a cmp r2, r3
- 8002dca: d02e beq.n 8002e2a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- {
- /* Store the content of BDCR register before the reset of Backup Domain */
- tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
- 8002dcc: 4b20 ldr r3, [pc, #128] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002dce: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002dd0: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8002dd4: 613b str r3, [r7, #16]
-
- /* RTC Clock selection can be changed only if the Backup Domain is reset */
- __HAL_RCC_BACKUPRESET_FORCE();
- 8002dd6: 4b1e ldr r3, [pc, #120] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002dd8: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002dda: 4a1d ldr r2, [pc, #116] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002ddc: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 8002de0: 6713 str r3, [r2, #112] ; 0x70
- __HAL_RCC_BACKUPRESET_RELEASE();
- 8002de2: 4b1b ldr r3, [pc, #108] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002de4: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002de6: 4a1a ldr r2, [pc, #104] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002de8: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8002dec: 6713 str r3, [r2, #112] ; 0x70
-
- /* Restore the Content of BDCR register */
- RCC->BDCR = tmpreg0;
- 8002dee: 4a18 ldr r2, [pc, #96] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002df0: 693b ldr r3, [r7, #16]
- 8002df2: 6713 str r3, [r2, #112] ; 0x70
-
- /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
- if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
- 8002df4: 4b16 ldr r3, [pc, #88] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002df6: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002df8: f003 0301 and.w r3, r3, #1
- 8002dfc: 2b01 cmp r3, #1
- 8002dfe: d114 bne.n 8002e2a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002e00: f7fe ffe2 bl 8001dc8 <HAL_GetTick>
- 8002e04: 6178 str r0, [r7, #20]
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8002e06: e00a b.n 8002e1e <HAL_RCCEx_PeriphCLKConfig+0x19e>
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8002e08: f7fe ffde bl 8001dc8 <HAL_GetTick>
- 8002e0c: 4602 mov r2, r0
- 8002e0e: 697b ldr r3, [r7, #20]
- 8002e10: 1ad3 subs r3, r2, r3
- 8002e12: f241 3288 movw r2, #5000 ; 0x1388
- 8002e16: 4293 cmp r3, r2
- 8002e18: d901 bls.n 8002e1e <HAL_RCCEx_PeriphCLKConfig+0x19e>
- {
- return HAL_TIMEOUT;
- 8002e1a: 2303 movs r3, #3
- 8002e1c: e34f b.n 80034be <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8002e1e: 4b0c ldr r3, [pc, #48] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002e20: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002e22: f003 0302 and.w r3, r3, #2
- 8002e26: 2b00 cmp r3, #0
- 8002e28: d0ee beq.n 8002e08 <HAL_RCCEx_PeriphCLKConfig+0x188>
- }
- }
- }
- }
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
- 8002e2a: 687b ldr r3, [r7, #4]
- 8002e2c: 6b1b ldr r3, [r3, #48] ; 0x30
- 8002e2e: f403 7340 and.w r3, r3, #768 ; 0x300
- 8002e32: f5b3 7f40 cmp.w r3, #768 ; 0x300
- 8002e36: d111 bne.n 8002e5c <HAL_RCCEx_PeriphCLKConfig+0x1dc>
- 8002e38: 4b05 ldr r3, [pc, #20] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002e3a: 689b ldr r3, [r3, #8]
- 8002e3c: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000
- 8002e40: 687b ldr r3, [r7, #4]
- 8002e42: 6b19 ldr r1, [r3, #48] ; 0x30
- 8002e44: 4b04 ldr r3, [pc, #16] ; (8002e58 <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
- 8002e46: 400b ands r3, r1
- 8002e48: 4901 ldr r1, [pc, #4] ; (8002e50 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002e4a: 4313 orrs r3, r2
- 8002e4c: 608b str r3, [r1, #8]
- 8002e4e: e00b b.n 8002e68 <HAL_RCCEx_PeriphCLKConfig+0x1e8>
- 8002e50: 40023800 .word 0x40023800
- 8002e54: 40007000 .word 0x40007000
- 8002e58: 0ffffcff .word 0x0ffffcff
- 8002e5c: 4bb3 ldr r3, [pc, #716] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e5e: 689b ldr r3, [r3, #8]
- 8002e60: 4ab2 ldr r2, [pc, #712] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e62: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000
- 8002e66: 6093 str r3, [r2, #8]
- 8002e68: 4bb0 ldr r3, [pc, #704] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e6a: 6f1a ldr r2, [r3, #112] ; 0x70
- 8002e6c: 687b ldr r3, [r7, #4]
- 8002e6e: 6b1b ldr r3, [r3, #48] ; 0x30
- 8002e70: f3c3 030b ubfx r3, r3, #0, #12
- 8002e74: 49ad ldr r1, [pc, #692] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e76: 4313 orrs r3, r2
- 8002e78: 670b str r3, [r1, #112] ; 0x70
- }
-
- /*------------------------------------ TIM configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
- 8002e7a: 687b ldr r3, [r7, #4]
- 8002e7c: 681b ldr r3, [r3, #0]
- 8002e7e: f003 0310 and.w r3, r3, #16
- 8002e82: 2b00 cmp r3, #0
- 8002e84: d010 beq.n 8002ea8 <HAL_RCCEx_PeriphCLKConfig+0x228>
- {
- /* Check the parameters */
- assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
-
- /* Configure Timer Prescaler */
- __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
- 8002e86: 4ba9 ldr r3, [pc, #676] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e88: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002e8c: 4aa7 ldr r2, [pc, #668] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e8e: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 8002e92: f8c2 308c str.w r3, [r2, #140] ; 0x8c
- 8002e96: 4ba5 ldr r3, [pc, #660] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e98: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c
- 8002e9c: 687b ldr r3, [r7, #4]
- 8002e9e: 6b9b ldr r3, [r3, #56] ; 0x38
- 8002ea0: 49a2 ldr r1, [pc, #648] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ea2: 4313 orrs r3, r2
- 8002ea4: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*-------------------------------------- I2C1 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
- 8002ea8: 687b ldr r3, [r7, #4]
- 8002eaa: 681b ldr r3, [r3, #0]
- 8002eac: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 8002eb0: 2b00 cmp r3, #0
- 8002eb2: d00a beq.n 8002eca <HAL_RCCEx_PeriphCLKConfig+0x24a>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
-
- /* Configure the I2C1 clock source */
- __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
- 8002eb4: 4b9d ldr r3, [pc, #628] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002eb6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002eba: f423 3240 bic.w r2, r3, #196608 ; 0x30000
- 8002ebe: 687b ldr r3, [r7, #4]
- 8002ec0: 6e5b ldr r3, [r3, #100] ; 0x64
- 8002ec2: 499a ldr r1, [pc, #616] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ec4: 4313 orrs r3, r2
- 8002ec6: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- I2C2 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
- 8002eca: 687b ldr r3, [r7, #4]
- 8002ecc: 681b ldr r3, [r3, #0]
- 8002ece: f403 4300 and.w r3, r3, #32768 ; 0x8000
- 8002ed2: 2b00 cmp r3, #0
- 8002ed4: d00a beq.n 8002eec <HAL_RCCEx_PeriphCLKConfig+0x26c>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
-
- /* Configure the I2C2 clock source */
- __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
- 8002ed6: 4b95 ldr r3, [pc, #596] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ed8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002edc: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
- 8002ee0: 687b ldr r3, [r7, #4]
- 8002ee2: 6e9b ldr r3, [r3, #104] ; 0x68
- 8002ee4: 4991 ldr r1, [pc, #580] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ee6: 4313 orrs r3, r2
- 8002ee8: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- I2C3 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
- 8002eec: 687b ldr r3, [r7, #4]
- 8002eee: 681b ldr r3, [r3, #0]
- 8002ef0: f403 3380 and.w r3, r3, #65536 ; 0x10000
- 8002ef4: 2b00 cmp r3, #0
- 8002ef6: d00a beq.n 8002f0e <HAL_RCCEx_PeriphCLKConfig+0x28e>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
-
- /* Configure the I2C3 clock source */
- __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
- 8002ef8: 4b8c ldr r3, [pc, #560] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002efa: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002efe: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
- 8002f02: 687b ldr r3, [r7, #4]
- 8002f04: 6edb ldr r3, [r3, #108] ; 0x6c
- 8002f06: 4989 ldr r1, [pc, #548] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f08: 4313 orrs r3, r2
- 8002f0a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- I2C4 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
- 8002f0e: 687b ldr r3, [r7, #4]
- 8002f10: 681b ldr r3, [r3, #0]
- 8002f12: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8002f16: 2b00 cmp r3, #0
- 8002f18: d00a beq.n 8002f30 <HAL_RCCEx_PeriphCLKConfig+0x2b0>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
-
- /* Configure the I2C4 clock source */
- __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
- 8002f1a: 4b84 ldr r3, [pc, #528] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f1c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002f20: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
- 8002f24: 687b ldr r3, [r7, #4]
- 8002f26: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002f28: 4980 ldr r1, [pc, #512] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f2a: 4313 orrs r3, r2
- 8002f2c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART1 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
- 8002f30: 687b ldr r3, [r7, #4]
- 8002f32: 681b ldr r3, [r3, #0]
- 8002f34: f003 0340 and.w r3, r3, #64 ; 0x40
- 8002f38: 2b00 cmp r3, #0
- 8002f3a: d00a beq.n 8002f52 <HAL_RCCEx_PeriphCLKConfig+0x2d2>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
-
- /* Configure the USART1 clock source */
- __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
- 8002f3c: 4b7b ldr r3, [pc, #492] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f3e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002f42: f023 0203 bic.w r2, r3, #3
- 8002f46: 687b ldr r3, [r7, #4]
- 8002f48: 6c5b ldr r3, [r3, #68] ; 0x44
- 8002f4a: 4978 ldr r1, [pc, #480] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f4c: 4313 orrs r3, r2
- 8002f4e: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART2 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
- 8002f52: 687b ldr r3, [r7, #4]
- 8002f54: 681b ldr r3, [r3, #0]
- 8002f56: f003 0380 and.w r3, r3, #128 ; 0x80
- 8002f5a: 2b00 cmp r3, #0
- 8002f5c: d00a beq.n 8002f74 <HAL_RCCEx_PeriphCLKConfig+0x2f4>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
-
- /* Configure the USART2 clock source */
- __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
- 8002f5e: 4b73 ldr r3, [pc, #460] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f60: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002f64: f023 020c bic.w r2, r3, #12
- 8002f68: 687b ldr r3, [r7, #4]
- 8002f6a: 6c9b ldr r3, [r3, #72] ; 0x48
- 8002f6c: 496f ldr r1, [pc, #444] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f6e: 4313 orrs r3, r2
- 8002f70: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART3 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
- 8002f74: 687b ldr r3, [r7, #4]
- 8002f76: 681b ldr r3, [r3, #0]
- 8002f78: f403 7380 and.w r3, r3, #256 ; 0x100
- 8002f7c: 2b00 cmp r3, #0
- 8002f7e: d00a beq.n 8002f96 <HAL_RCCEx_PeriphCLKConfig+0x316>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
-
- /* Configure the USART3 clock source */
- __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
- 8002f80: 4b6a ldr r3, [pc, #424] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f82: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002f86: f023 0230 bic.w r2, r3, #48 ; 0x30
- 8002f8a: 687b ldr r3, [r7, #4]
- 8002f8c: 6cdb ldr r3, [r3, #76] ; 0x4c
- 8002f8e: 4967 ldr r1, [pc, #412] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f90: 4313 orrs r3, r2
- 8002f92: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART4 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
- 8002f96: 687b ldr r3, [r7, #4]
- 8002f98: 681b ldr r3, [r3, #0]
- 8002f9a: f403 7300 and.w r3, r3, #512 ; 0x200
- 8002f9e: 2b00 cmp r3, #0
- 8002fa0: d00a beq.n 8002fb8 <HAL_RCCEx_PeriphCLKConfig+0x338>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
-
- /* Configure the UART4 clock source */
- __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
- 8002fa2: 4b62 ldr r3, [pc, #392] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002fa4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002fa8: f023 02c0 bic.w r2, r3, #192 ; 0xc0
- 8002fac: 687b ldr r3, [r7, #4]
- 8002fae: 6d1b ldr r3, [r3, #80] ; 0x50
- 8002fb0: 495e ldr r1, [pc, #376] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002fb2: 4313 orrs r3, r2
- 8002fb4: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART5 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
- 8002fb8: 687b ldr r3, [r7, #4]
- 8002fba: 681b ldr r3, [r3, #0]
- 8002fbc: f403 6380 and.w r3, r3, #1024 ; 0x400
- 8002fc0: 2b00 cmp r3, #0
- 8002fc2: d00a beq.n 8002fda <HAL_RCCEx_PeriphCLKConfig+0x35a>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
-
- /* Configure the UART5 clock source */
- __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
- 8002fc4: 4b59 ldr r3, [pc, #356] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002fc6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002fca: f423 7240 bic.w r2, r3, #768 ; 0x300
- 8002fce: 687b ldr r3, [r7, #4]
- 8002fd0: 6d5b ldr r3, [r3, #84] ; 0x54
- 8002fd2: 4956 ldr r1, [pc, #344] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002fd4: 4313 orrs r3, r2
- 8002fd6: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART6 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
- 8002fda: 687b ldr r3, [r7, #4]
- 8002fdc: 681b ldr r3, [r3, #0]
- 8002fde: f403 6300 and.w r3, r3, #2048 ; 0x800
- 8002fe2: 2b00 cmp r3, #0
- 8002fe4: d00a beq.n 8002ffc <HAL_RCCEx_PeriphCLKConfig+0x37c>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
-
- /* Configure the USART6 clock source */
- __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
- 8002fe6: 4b51 ldr r3, [pc, #324] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002fe8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002fec: f423 6240 bic.w r2, r3, #3072 ; 0xc00
- 8002ff0: 687b ldr r3, [r7, #4]
- 8002ff2: 6d9b ldr r3, [r3, #88] ; 0x58
- 8002ff4: 494d ldr r1, [pc, #308] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ff6: 4313 orrs r3, r2
- 8002ff8: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART7 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
- 8002ffc: 687b ldr r3, [r7, #4]
- 8002ffe: 681b ldr r3, [r3, #0]
- 8003000: f403 5380 and.w r3, r3, #4096 ; 0x1000
- 8003004: 2b00 cmp r3, #0
- 8003006: d00a beq.n 800301e <HAL_RCCEx_PeriphCLKConfig+0x39e>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
-
- /* Configure the UART7 clock source */
- __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
- 8003008: 4b48 ldr r3, [pc, #288] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 800300a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 800300e: f423 5240 bic.w r2, r3, #12288 ; 0x3000
- 8003012: 687b ldr r3, [r7, #4]
- 8003014: 6ddb ldr r3, [r3, #92] ; 0x5c
- 8003016: 4945 ldr r1, [pc, #276] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8003018: 4313 orrs r3, r2
- 800301a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART8 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
- 800301e: 687b ldr r3, [r7, #4]
- 8003020: 681b ldr r3, [r3, #0]
- 8003022: f403 5300 and.w r3, r3, #8192 ; 0x2000
- 8003026: 2b00 cmp r3, #0
- 8003028: d00a beq.n 8003040 <HAL_RCCEx_PeriphCLKConfig+0x3c0>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
-
- /* Configure the UART8 clock source */
- __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
- 800302a: 4b40 ldr r3, [pc, #256] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 800302c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8003030: f423 4240 bic.w r2, r3, #49152 ; 0xc000
- 8003034: 687b ldr r3, [r7, #4]
- 8003036: 6e1b ldr r3, [r3, #96] ; 0x60
- 8003038: 493c ldr r1, [pc, #240] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 800303a: 4313 orrs r3, r2
- 800303c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*--------------------------------------- CEC Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
- 8003040: 687b ldr r3, [r7, #4]
- 8003042: 681b ldr r3, [r3, #0]
- 8003044: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8003048: 2b00 cmp r3, #0
- 800304a: d00a beq.n 8003062 <HAL_RCCEx_PeriphCLKConfig+0x3e2>
- {
- /* Check the parameters */
- assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
-
- /* Configure the CEC clock source */
- __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
- 800304c: 4b37 ldr r3, [pc, #220] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 800304e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8003052: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
- 8003056: 687b ldr r3, [r7, #4]
- 8003058: 6f9b ldr r3, [r3, #120] ; 0x78
- 800305a: 4934 ldr r1, [pc, #208] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 800305c: 4313 orrs r3, r2
- 800305e: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- CK48 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
- 8003062: 687b ldr r3, [r7, #4]
- 8003064: 681b ldr r3, [r3, #0]
- 8003066: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 800306a: 2b00 cmp r3, #0
- 800306c: d011 beq.n 8003092 <HAL_RCCEx_PeriphCLKConfig+0x412>
- {
- /* Check the parameters */
- assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
-
- /* Configure the CLK48 source */
- __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
- 800306e: 4b2f ldr r3, [pc, #188] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8003070: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8003074: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000
- 8003078: 687b ldr r3, [r7, #4]
- 800307a: 6fdb ldr r3, [r3, #124] ; 0x7c
- 800307c: 492b ldr r1, [pc, #172] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 800307e: 4313 orrs r3, r2
- 8003080: f8c1 3090 str.w r3, [r1, #144] ; 0x90
-
- /* Enable the PLLSAI when it's used as clock source for CK48 */
- if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
- 8003084: 687b ldr r3, [r7, #4]
- 8003086: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8003088: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
- 800308c: d101 bne.n 8003092 <HAL_RCCEx_PeriphCLKConfig+0x412>
- {
- pllsaiused = 1;
- 800308e: 2301 movs r3, #1
- 8003090: 61bb str r3, [r7, #24]
- }
- }
-
- /*-------------------------------------- LTDC Configuration -----------------------------------*/
-#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
- 8003092: 687b ldr r3, [r7, #4]
- 8003094: 681b ldr r3, [r3, #0]
- 8003096: f003 0308 and.w r3, r3, #8
- 800309a: 2b00 cmp r3, #0
- 800309c: d001 beq.n 80030a2 <HAL_RCCEx_PeriphCLKConfig+0x422>
- {
- pllsaiused = 1;
- 800309e: 2301 movs r3, #1
- 80030a0: 61bb str r3, [r7, #24]
- }
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
-
- /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
- 80030a2: 687b ldr r3, [r7, #4]
- 80030a4: 681b ldr r3, [r3, #0]
- 80030a6: f403 2380 and.w r3, r3, #262144 ; 0x40000
- 80030aa: 2b00 cmp r3, #0
- 80030ac: d00a beq.n 80030c4 <HAL_RCCEx_PeriphCLKConfig+0x444>
- {
- /* Check the parameters */
- assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
-
- /* Configure the LTPIM1 clock source */
- __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
- 80030ae: 4b1f ldr r3, [pc, #124] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 80030b0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 80030b4: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000
- 80030b8: 687b ldr r3, [r7, #4]
- 80030ba: 6f5b ldr r3, [r3, #116] ; 0x74
- 80030bc: 491b ldr r1, [pc, #108] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 80030be: 4313 orrs r3, r2
- 80030c0: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
- 80030c4: 687b ldr r3, [r7, #4]
- 80030c6: 681b ldr r3, [r3, #0]
- 80030c8: f403 0300 and.w r3, r3, #8388608 ; 0x800000
- 80030cc: 2b00 cmp r3, #0
- 80030ce: d00b beq.n 80030e8 <HAL_RCCEx_PeriphCLKConfig+0x468>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
-
- /* Configure the SDMMC1 clock source */
- __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
- 80030d0: 4b16 ldr r3, [pc, #88] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 80030d2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 80030d6: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000
- 80030da: 687b ldr r3, [r7, #4]
- 80030dc: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
- 80030e0: 4912 ldr r1, [pc, #72] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 80030e2: 4313 orrs r3, r2
- 80030e4: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
- /*------------------------------------- SDMMC2 Configuration ------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
- 80030e8: 687b ldr r3, [r7, #4]
- 80030ea: 681b ldr r3, [r3, #0]
- 80030ec: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
- 80030f0: 2b00 cmp r3, #0
- 80030f2: d00b beq.n 800310c <HAL_RCCEx_PeriphCLKConfig+0x48c>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
-
- /* Configure the SDMMC2 clock source */
- __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
- 80030f4: 4b0d ldr r3, [pc, #52] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 80030f6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 80030fa: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000
- 80030fe: 687b ldr r3, [r7, #4]
- 8003100: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8003104: 4909 ldr r1, [pc, #36] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8003106: 4313 orrs r3, r2
- 8003108: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*------------------------------------- DFSDM1 Configuration -------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
- 800310c: 687b ldr r3, [r7, #4]
- 800310e: 681b ldr r3, [r3, #0]
- 8003110: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 8003114: 2b00 cmp r3, #0
- 8003116: d00f beq.n 8003138 <HAL_RCCEx_PeriphCLKConfig+0x4b8>
- {
- /* Check the parameters */
- assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
-
- /* Configure the DFSDM1 interface clock source */
- __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
- 8003118: 4b04 ldr r3, [pc, #16] ; (800312c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 800311a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 800311e: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000
- 8003122: 687b ldr r3, [r7, #4]
- 8003124: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8003128: e002 b.n 8003130 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
- 800312a: bf00 nop
- 800312c: 40023800 .word 0x40023800
- 8003130: 4985 ldr r1, [pc, #532] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003132: 4313 orrs r3, r2
- 8003134: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
- 8003138: 687b ldr r3, [r7, #4]
- 800313a: 681b ldr r3, [r3, #0]
- 800313c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8003140: 2b00 cmp r3, #0
- 8003142: d00b beq.n 800315c <HAL_RCCEx_PeriphCLKConfig+0x4dc>
- {
- /* Check the parameters */
- assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
-
- /* Configure the DFSDM interface clock source */
- __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
- 8003144: 4b80 ldr r3, [pc, #512] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003146: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 800314a: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
- 800314e: 687b ldr r3, [r7, #4]
- 8003150: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8003154: 497c ldr r1, [pc, #496] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003156: 4313 orrs r3, r2
- 8003158: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
- /*-------------------------------------- PLLI2S Configuration ---------------------------------*/
- /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
- if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
- 800315c: 69fb ldr r3, [r7, #28]
- 800315e: 2b01 cmp r3, #1
- 8003160: d005 beq.n 800316e <HAL_RCCEx_PeriphCLKConfig+0x4ee>
- 8003162: 687b ldr r3, [r7, #4]
- 8003164: 681b ldr r3, [r3, #0]
- 8003166: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
- 800316a: f040 80d6 bne.w 800331a <HAL_RCCEx_PeriphCLKConfig+0x69a>
- {
- /* Disable the PLLI2S */
- __HAL_RCC_PLLI2S_DISABLE();
- 800316e: 4b76 ldr r3, [pc, #472] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003170: 681b ldr r3, [r3, #0]
- 8003172: 4a75 ldr r2, [pc, #468] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003174: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
- 8003178: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 800317a: f7fe fe25 bl 8001dc8 <HAL_GetTick>
- 800317e: 6178 str r0, [r7, #20]
-
- /* Wait till PLLI2S is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
- 8003180: e008 b.n 8003194 <HAL_RCCEx_PeriphCLKConfig+0x514>
- {
- if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- 8003182: f7fe fe21 bl 8001dc8 <HAL_GetTick>
- 8003186: 4602 mov r2, r0
- 8003188: 697b ldr r3, [r7, #20]
- 800318a: 1ad3 subs r3, r2, r3
- 800318c: 2b64 cmp r3, #100 ; 0x64
- 800318e: d901 bls.n 8003194 <HAL_RCCEx_PeriphCLKConfig+0x514>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 8003190: 2303 movs r3, #3
- 8003192: e194 b.n 80034be <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
- 8003194: 4b6c ldr r3, [pc, #432] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003196: 681b ldr r3, [r3, #0]
- 8003198: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 800319c: 2b00 cmp r3, #0
- 800319e: d1f0 bne.n 8003182 <HAL_RCCEx_PeriphCLKConfig+0x502>
-
- /* check for common PLLI2S Parameters */
- assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-
- /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
- 80031a0: 687b ldr r3, [r7, #4]
- 80031a2: 681b ldr r3, [r3, #0]
- 80031a4: f003 0301 and.w r3, r3, #1
- 80031a8: 2b00 cmp r3, #0
- 80031aa: d021 beq.n 80031f0 <HAL_RCCEx_PeriphCLKConfig+0x570>
- 80031ac: 687b ldr r3, [r7, #4]
- 80031ae: 6b5b ldr r3, [r3, #52] ; 0x34
- 80031b0: 2b00 cmp r3, #0
- 80031b2: d11d bne.n 80031f0 <HAL_RCCEx_PeriphCLKConfig+0x570>
- {
- /* check for Parameters */
- assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-
- /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
- 80031b4: 4b64 ldr r3, [pc, #400] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80031b6: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 80031ba: 0c1b lsrs r3, r3, #16
- 80031bc: f003 0303 and.w r3, r3, #3
- 80031c0: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
- 80031c2: 4b61 ldr r3, [pc, #388] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80031c4: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 80031c8: 0e1b lsrs r3, r3, #24
- 80031ca: f003 030f and.w r3, r3, #15
- 80031ce: 60fb str r3, [r7, #12]
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
- /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
- 80031d0: 687b ldr r3, [r7, #4]
- 80031d2: 685b ldr r3, [r3, #4]
- 80031d4: 019a lsls r2, r3, #6
- 80031d6: 693b ldr r3, [r7, #16]
- 80031d8: 041b lsls r3, r3, #16
- 80031da: 431a orrs r2, r3
- 80031dc: 68fb ldr r3, [r7, #12]
- 80031de: 061b lsls r3, r3, #24
- 80031e0: 431a orrs r2, r3
- 80031e2: 687b ldr r3, [r7, #4]
- 80031e4: 689b ldr r3, [r3, #8]
- 80031e6: 071b lsls r3, r3, #28
- 80031e8: 4957 ldr r1, [pc, #348] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80031ea: 4313 orrs r3, r2
- 80031ec: f8c1 3084 str.w r3, [r1, #132] ; 0x84
- }
-
- /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
- 80031f0: 687b ldr r3, [r7, #4]
- 80031f2: 681b ldr r3, [r3, #0]
- 80031f4: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 80031f8: 2b00 cmp r3, #0
- 80031fa: d004 beq.n 8003206 <HAL_RCCEx_PeriphCLKConfig+0x586>
- 80031fc: 687b ldr r3, [r7, #4]
- 80031fe: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8003200: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 8003204: d00a beq.n 800321c <HAL_RCCEx_PeriphCLKConfig+0x59c>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
- 8003206: 687b ldr r3, [r7, #4]
- 8003208: 681b ldr r3, [r3, #0]
- 800320a: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
- 800320e: 2b00 cmp r3, #0
- 8003210: d02e beq.n 8003270 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
- 8003212: 687b ldr r3, [r7, #4]
- 8003214: 6c1b ldr r3, [r3, #64] ; 0x40
- 8003216: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 800321a: d129 bne.n 8003270 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
- assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
- /* Check for PLLI2S/DIVQ parameters */
- assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
-
- /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
- 800321c: 4b4a ldr r3, [pc, #296] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800321e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8003222: 0c1b lsrs r3, r3, #16
- 8003224: f003 0303 and.w r3, r3, #3
- 8003228: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
- 800322a: 4b47 ldr r3, [pc, #284] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800322c: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8003230: 0f1b lsrs r3, r3, #28
- 8003232: f003 0307 and.w r3, r3, #7
- 8003236: 60fb str r3, [r7, #12]
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
- /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
- /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
- 8003238: 687b ldr r3, [r7, #4]
- 800323a: 685b ldr r3, [r3, #4]
- 800323c: 019a lsls r2, r3, #6
- 800323e: 693b ldr r3, [r7, #16]
- 8003240: 041b lsls r3, r3, #16
- 8003242: 431a orrs r2, r3
- 8003244: 687b ldr r3, [r7, #4]
- 8003246: 68db ldr r3, [r3, #12]
- 8003248: 061b lsls r3, r3, #24
- 800324a: 431a orrs r2, r3
- 800324c: 68fb ldr r3, [r7, #12]
- 800324e: 071b lsls r3, r3, #28
- 8003250: 493d ldr r1, [pc, #244] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003252: 4313 orrs r3, r2
- 8003254: f8c1 3084 str.w r3, [r1, #132] ; 0x84
-
- /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
- __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
- 8003258: 4b3b ldr r3, [pc, #236] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800325a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 800325e: f023 021f bic.w r2, r3, #31
- 8003262: 687b ldr r3, [r7, #4]
- 8003264: 6a5b ldr r3, [r3, #36] ; 0x24
- 8003266: 3b01 subs r3, #1
- 8003268: 4937 ldr r1, [pc, #220] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800326a: 4313 orrs r3, r2
- 800326c: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
- 8003270: 687b ldr r3, [r7, #4]
- 8003272: 681b ldr r3, [r3, #0]
- 8003274: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
- 8003278: 2b00 cmp r3, #0
- 800327a: d01d beq.n 80032b8 <HAL_RCCEx_PeriphCLKConfig+0x638>
- {
- /* check for Parameters */
- assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
-
- /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
- 800327c: 4b32 ldr r3, [pc, #200] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800327e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8003282: 0e1b lsrs r3, r3, #24
- 8003284: f003 030f and.w r3, r3, #15
- 8003288: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
- 800328a: 4b2f ldr r3, [pc, #188] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800328c: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8003290: 0f1b lsrs r3, r3, #28
- 8003292: f003 0307 and.w r3, r3, #7
- 8003296: 60fb str r3, [r7, #12]
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
- /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
- 8003298: 687b ldr r3, [r7, #4]
- 800329a: 685b ldr r3, [r3, #4]
- 800329c: 019a lsls r2, r3, #6
- 800329e: 687b ldr r3, [r7, #4]
- 80032a0: 691b ldr r3, [r3, #16]
- 80032a2: 041b lsls r3, r3, #16
- 80032a4: 431a orrs r2, r3
- 80032a6: 693b ldr r3, [r7, #16]
- 80032a8: 061b lsls r3, r3, #24
- 80032aa: 431a orrs r2, r3
- 80032ac: 68fb ldr r3, [r7, #12]
- 80032ae: 071b lsls r3, r3, #28
- 80032b0: 4925 ldr r1, [pc, #148] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80032b2: 4313 orrs r3, r2
- 80032b4: f8c1 3084 str.w r3, [r1, #132] ; 0x84
- }
-
- /*----------------- In Case of PLLI2S is just selected -----------------*/
- if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
- 80032b8: 687b ldr r3, [r7, #4]
- 80032ba: 681b ldr r3, [r3, #0]
- 80032bc: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80032c0: 2b00 cmp r3, #0
- 80032c2: d011 beq.n 80032e8 <HAL_RCCEx_PeriphCLKConfig+0x668>
- assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
- /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
- 80032c4: 687b ldr r3, [r7, #4]
- 80032c6: 685b ldr r3, [r3, #4]
- 80032c8: 019a lsls r2, r3, #6
- 80032ca: 687b ldr r3, [r7, #4]
- 80032cc: 691b ldr r3, [r3, #16]
- 80032ce: 041b lsls r3, r3, #16
- 80032d0: 431a orrs r2, r3
- 80032d2: 687b ldr r3, [r7, #4]
- 80032d4: 68db ldr r3, [r3, #12]
- 80032d6: 061b lsls r3, r3, #24
- 80032d8: 431a orrs r2, r3
- 80032da: 687b ldr r3, [r7, #4]
- 80032dc: 689b ldr r3, [r3, #8]
- 80032de: 071b lsls r3, r3, #28
- 80032e0: 4919 ldr r1, [pc, #100] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80032e2: 4313 orrs r3, r2
- 80032e4: f8c1 3084 str.w r3, [r1, #132] ; 0x84
- }
-
- /* Enable the PLLI2S */
- __HAL_RCC_PLLI2S_ENABLE();
- 80032e8: 4b17 ldr r3, [pc, #92] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80032ea: 681b ldr r3, [r3, #0]
- 80032ec: 4a16 ldr r2, [pc, #88] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80032ee: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
- 80032f2: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80032f4: f7fe fd68 bl 8001dc8 <HAL_GetTick>
- 80032f8: 6178 str r0, [r7, #20]
-
- /* Wait till PLLI2S is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
- 80032fa: e008 b.n 800330e <HAL_RCCEx_PeriphCLKConfig+0x68e>
- {
- if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- 80032fc: f7fe fd64 bl 8001dc8 <HAL_GetTick>
- 8003300: 4602 mov r2, r0
- 8003302: 697b ldr r3, [r7, #20]
- 8003304: 1ad3 subs r3, r2, r3
- 8003306: 2b64 cmp r3, #100 ; 0x64
- 8003308: d901 bls.n 800330e <HAL_RCCEx_PeriphCLKConfig+0x68e>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 800330a: 2303 movs r3, #3
- 800330c: e0d7 b.n 80034be <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
- 800330e: 4b0e ldr r3, [pc, #56] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003310: 681b ldr r3, [r3, #0]
- 8003312: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 8003316: 2b00 cmp r3, #0
- 8003318: d0f0 beq.n 80032fc <HAL_RCCEx_PeriphCLKConfig+0x67c>
- }
- }
-
- /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
- /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
- if(pllsaiused == 1)
- 800331a: 69bb ldr r3, [r7, #24]
- 800331c: 2b01 cmp r3, #1
- 800331e: f040 80cd bne.w 80034bc <HAL_RCCEx_PeriphCLKConfig+0x83c>
- {
- /* Disable PLLSAI Clock */
- __HAL_RCC_PLLSAI_DISABLE();
- 8003322: 4b09 ldr r3, [pc, #36] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003324: 681b ldr r3, [r3, #0]
- 8003326: 4a08 ldr r2, [pc, #32] ; (8003348 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003328: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
- 800332c: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 800332e: f7fe fd4b bl 8001dc8 <HAL_GetTick>
- 8003332: 6178 str r0, [r7, #20]
-
- /* Wait till PLLSAI is disabled */
- while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
- 8003334: e00a b.n 800334c <HAL_RCCEx_PeriphCLKConfig+0x6cc>
- {
- if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
- 8003336: f7fe fd47 bl 8001dc8 <HAL_GetTick>
- 800333a: 4602 mov r2, r0
- 800333c: 697b ldr r3, [r7, #20]
- 800333e: 1ad3 subs r3, r2, r3
- 8003340: 2b64 cmp r3, #100 ; 0x64
- 8003342: d903 bls.n 800334c <HAL_RCCEx_PeriphCLKConfig+0x6cc>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 8003344: 2303 movs r3, #3
- 8003346: e0ba b.n 80034be <HAL_RCCEx_PeriphCLKConfig+0x83e>
- 8003348: 40023800 .word 0x40023800
- while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
- 800334c: 4b5e ldr r3, [pc, #376] ; (80034c8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800334e: 681b ldr r3, [r3, #0]
- 8003350: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
- 8003354: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
- 8003358: d0ed beq.n 8003336 <HAL_RCCEx_PeriphCLKConfig+0x6b6>
-
- /* Check the PLLSAI division factors */
- assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
-
- /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
- 800335a: 687b ldr r3, [r7, #4]
- 800335c: 681b ldr r3, [r3, #0]
- 800335e: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 8003362: 2b00 cmp r3, #0
- 8003364: d003 beq.n 800336e <HAL_RCCEx_PeriphCLKConfig+0x6ee>
- 8003366: 687b ldr r3, [r7, #4]
- 8003368: 6bdb ldr r3, [r3, #60] ; 0x3c
- 800336a: 2b00 cmp r3, #0
- 800336c: d009 beq.n 8003382 <HAL_RCCEx_PeriphCLKConfig+0x702>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
- 800336e: 687b ldr r3, [r7, #4]
- 8003370: 681b ldr r3, [r3, #0]
- 8003372: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
- 8003376: 2b00 cmp r3, #0
- 8003378: d02e beq.n 80033d8 <HAL_RCCEx_PeriphCLKConfig+0x758>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
- 800337a: 687b ldr r3, [r7, #4]
- 800337c: 6c1b ldr r3, [r3, #64] ; 0x40
- 800337e: 2b00 cmp r3, #0
- 8003380: d12a bne.n 80033d8 <HAL_RCCEx_PeriphCLKConfig+0x758>
- assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
- /* check for PLLSAI/DIVQ Parameter */
- assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
-
- /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
- 8003382: 4b51 ldr r3, [pc, #324] ; (80034c8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003384: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8003388: 0c1b lsrs r3, r3, #16
- 800338a: f003 0303 and.w r3, r3, #3
- 800338e: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
- 8003390: 4b4d ldr r3, [pc, #308] ; (80034c8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003392: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8003396: 0f1b lsrs r3, r3, #28
- 8003398: f003 0307 and.w r3, r3, #7
- 800339c: 60fb str r3, [r7, #12]
- /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
- /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
- /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
- 800339e: 687b ldr r3, [r7, #4]
- 80033a0: 695b ldr r3, [r3, #20]
- 80033a2: 019a lsls r2, r3, #6
- 80033a4: 693b ldr r3, [r7, #16]
- 80033a6: 041b lsls r3, r3, #16
- 80033a8: 431a orrs r2, r3
- 80033aa: 687b ldr r3, [r7, #4]
- 80033ac: 699b ldr r3, [r3, #24]
- 80033ae: 061b lsls r3, r3, #24
- 80033b0: 431a orrs r2, r3
- 80033b2: 68fb ldr r3, [r7, #12]
- 80033b4: 071b lsls r3, r3, #28
- 80033b6: 4944 ldr r1, [pc, #272] ; (80034c8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80033b8: 4313 orrs r3, r2
- 80033ba: f8c1 3088 str.w r3, [r1, #136] ; 0x88
-
- /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
- __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
- 80033be: 4b42 ldr r3, [pc, #264] ; (80034c8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80033c0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 80033c4: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00
- 80033c8: 687b ldr r3, [r7, #4]
- 80033ca: 6a9b ldr r3, [r3, #40] ; 0x28
- 80033cc: 3b01 subs r3, #1
- 80033ce: 021b lsls r3, r3, #8
- 80033d0: 493d ldr r1, [pc, #244] ; (80034c8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80033d2: 4313 orrs r3, r2
- 80033d4: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
- /* In Case of PLLI2S is selected as source clock for CK48 */
- if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
- 80033d8: 687b ldr r3, [r7, #4]
- 80033da: 681b ldr r3, [r3, #0]
- 80033dc: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 80033e0: 2b00 cmp r3, #0
- 80033e2: d022 beq.n 800342a <HAL_RCCEx_PeriphCLKConfig+0x7aa>
- 80033e4: 687b ldr r3, [r7, #4]
- 80033e6: 6fdb ldr r3, [r3, #124] ; 0x7c
- 80033e8: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
- 80033ec: d11d bne.n 800342a <HAL_RCCEx_PeriphCLKConfig+0x7aa>
- {
- /* check for Parameters */
- assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
- /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
- 80033ee: 4b36 ldr r3, [pc, #216] ; (80034c8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80033f0: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 80033f4: 0e1b lsrs r3, r3, #24
- 80033f6: f003 030f and.w r3, r3, #15
- 80033fa: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
- 80033fc: 4b32 ldr r3, [pc, #200] ; (80034c8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80033fe: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8003402: 0f1b lsrs r3, r3, #28
- 8003404: f003 0307 and.w r3, r3, #7
- 8003408: 60fb str r3, [r7, #12]
-
- /* Configure the PLLSAI division factors */
- /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
- /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
- 800340a: 687b ldr r3, [r7, #4]
- 800340c: 695b ldr r3, [r3, #20]
- 800340e: 019a lsls r2, r3, #6
- 8003410: 687b ldr r3, [r7, #4]
- 8003412: 6a1b ldr r3, [r3, #32]
- 8003414: 041b lsls r3, r3, #16
- 8003416: 431a orrs r2, r3
- 8003418: 693b ldr r3, [r7, #16]
- 800341a: 061b lsls r3, r3, #24
- 800341c: 431a orrs r2, r3
- 800341e: 68fb ldr r3, [r7, #12]
- 8003420: 071b lsls r3, r3, #28
- 8003422: 4929 ldr r1, [pc, #164] ; (80034c8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003424: 4313 orrs r3, r2
- 8003426: f8c1 3088 str.w r3, [r1, #136] ; 0x88
- }
-
-#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
- /*---------------------------- LTDC configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
- 800342a: 687b ldr r3, [r7, #4]
- 800342c: 681b ldr r3, [r3, #0]
- 800342e: f003 0308 and.w r3, r3, #8
- 8003432: 2b00 cmp r3, #0
- 8003434: d028 beq.n 8003488 <HAL_RCCEx_PeriphCLKConfig+0x808>
- {
- assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
- assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
-
- /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
- 8003436: 4b24 ldr r3, [pc, #144] ; (80034c8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003438: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 800343c: 0e1b lsrs r3, r3, #24
- 800343e: f003 030f and.w r3, r3, #15
- 8003442: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
- 8003444: 4b20 ldr r3, [pc, #128] ; (80034c8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003446: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 800344a: 0c1b lsrs r3, r3, #16
- 800344c: f003 0303 and.w r3, r3, #3
- 8003450: 60fb str r3, [r7, #12]
-
- /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
- /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
- /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
- 8003452: 687b ldr r3, [r7, #4]
- 8003454: 695b ldr r3, [r3, #20]
- 8003456: 019a lsls r2, r3, #6
- 8003458: 68fb ldr r3, [r7, #12]
- 800345a: 041b lsls r3, r3, #16
- 800345c: 431a orrs r2, r3
- 800345e: 693b ldr r3, [r7, #16]
- 8003460: 061b lsls r3, r3, #24
- 8003462: 431a orrs r2, r3
- 8003464: 687b ldr r3, [r7, #4]
- 8003466: 69db ldr r3, [r3, #28]
- 8003468: 071b lsls r3, r3, #28
- 800346a: 4917 ldr r1, [pc, #92] ; (80034c8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800346c: 4313 orrs r3, r2
- 800346e: f8c1 3088 str.w r3, [r1, #136] ; 0x88
-
- /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
- __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
- 8003472: 4b15 ldr r3, [pc, #84] ; (80034c8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003474: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8003478: f423 3240 bic.w r2, r3, #196608 ; 0x30000
- 800347c: 687b ldr r3, [r7, #4]
- 800347e: 6adb ldr r3, [r3, #44] ; 0x2c
- 8003480: 4911 ldr r1, [pc, #68] ; (80034c8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003482: 4313 orrs r3, r2
- 8003484: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
-
- /* Enable PLLSAI Clock */
- __HAL_RCC_PLLSAI_ENABLE();
- 8003488: 4b0f ldr r3, [pc, #60] ; (80034c8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800348a: 681b ldr r3, [r3, #0]
- 800348c: 4a0e ldr r2, [pc, #56] ; (80034c8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800348e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8003492: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8003494: f7fe fc98 bl 8001dc8 <HAL_GetTick>
- 8003498: 6178 str r0, [r7, #20]
-
- /* Wait till PLLSAI is ready */
- while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
- 800349a: e008 b.n 80034ae <HAL_RCCEx_PeriphCLKConfig+0x82e>
- {
- if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
- 800349c: f7fe fc94 bl 8001dc8 <HAL_GetTick>
- 80034a0: 4602 mov r2, r0
- 80034a2: 697b ldr r3, [r7, #20]
- 80034a4: 1ad3 subs r3, r2, r3
- 80034a6: 2b64 cmp r3, #100 ; 0x64
- 80034a8: d901 bls.n 80034ae <HAL_RCCEx_PeriphCLKConfig+0x82e>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 80034aa: 2303 movs r3, #3
- 80034ac: e007 b.n 80034be <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
- 80034ae: 4b06 ldr r3, [pc, #24] ; (80034c8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80034b0: 681b ldr r3, [r3, #0]
- 80034b2: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
- 80034b6: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
- 80034ba: d1ef bne.n 800349c <HAL_RCCEx_PeriphCLKConfig+0x81c>
- }
- }
- }
- return HAL_OK;
- 80034bc: 2300 movs r3, #0
-}
- 80034be: 4618 mov r0, r3
- 80034c0: 3720 adds r7, #32
- 80034c2: 46bd mov sp, r7
- 80034c4: bd80 pop {r7, pc}
- 80034c6: bf00 nop
- 80034c8: 40023800 .word 0x40023800
-
-080034cc <HAL_TIM_Base_Init>:
- * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{
- 80034cc: b580 push {r7, lr}
- 80034ce: b082 sub sp, #8
- 80034d0: af00 add r7, sp, #0
- 80034d2: 6078 str r0, [r7, #4]
- /* Check the TIM handle allocation */
- if (htim == NULL)
- 80034d4: 687b ldr r3, [r7, #4]
- 80034d6: 2b00 cmp r3, #0
- 80034d8: d101 bne.n 80034de <HAL_TIM_Base_Init+0x12>
- {
- return HAL_ERROR;
- 80034da: 2301 movs r3, #1
- 80034dc: e01d b.n 800351a <HAL_TIM_Base_Init+0x4e>
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- 80034de: 687b ldr r3, [r7, #4]
- 80034e0: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
- 80034e4: b2db uxtb r3, r3
- 80034e6: 2b00 cmp r3, #0
- 80034e8: d106 bne.n 80034f8 <HAL_TIM_Base_Init+0x2c>
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
- 80034ea: 687b ldr r3, [r7, #4]
- 80034ec: 2200 movs r2, #0
- 80034ee: f883 203c strb.w r2, [r3, #60] ; 0x3c
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->Base_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- HAL_TIM_Base_MspInit(htim);
- 80034f2: 6878 ldr r0, [r7, #4]
- 80034f4: f7fe faa0 bl 8001a38 <HAL_TIM_Base_MspInit>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
- 80034f8: 687b ldr r3, [r7, #4]
- 80034fa: 2202 movs r2, #2
- 80034fc: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Set the Time Base configuration */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 8003500: 687b ldr r3, [r7, #4]
- 8003502: 681a ldr r2, [r3, #0]
- 8003504: 687b ldr r3, [r7, #4]
- 8003506: 3304 adds r3, #4
- 8003508: 4619 mov r1, r3
- 800350a: 4610 mov r0, r2
- 800350c: f000 fc90 bl 8003e30 <TIM_Base_SetConfig>
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
- 8003510: 687b ldr r3, [r7, #4]
- 8003512: 2201 movs r2, #1
- 8003514: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- return HAL_OK;
- 8003518: 2300 movs r3, #0
-}
- 800351a: 4618 mov r0, r3
- 800351c: 3708 adds r7, #8
- 800351e: 46bd mov sp, r7
- 8003520: bd80 pop {r7, pc}
- ...
-
-08003524 <HAL_TIM_Base_Start_IT>:
- * @brief Starts the TIM Base generation in interrupt mode.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
-{
- 8003524: b480 push {r7}
- 8003526: b085 sub sp, #20
- 8003528: af00 add r7, sp, #0
- 800352a: 6078 str r0, [r7, #4]
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Enable the TIM Update interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
- 800352c: 687b ldr r3, [r7, #4]
- 800352e: 681b ldr r3, [r3, #0]
- 8003530: 68da ldr r2, [r3, #12]
- 8003532: 687b ldr r3, [r7, #4]
- 8003534: 681b ldr r3, [r3, #0]
- 8003536: f042 0201 orr.w r2, r2, #1
- 800353a: 60da str r2, [r3, #12]
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- 800353c: 687b ldr r3, [r7, #4]
- 800353e: 681b ldr r3, [r3, #0]
- 8003540: 689a ldr r2, [r3, #8]
- 8003542: 4b0c ldr r3, [pc, #48] ; (8003574 <HAL_TIM_Base_Start_IT+0x50>)
- 8003544: 4013 ands r3, r2
- 8003546: 60fb str r3, [r7, #12]
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- 8003548: 68fb ldr r3, [r7, #12]
- 800354a: 2b06 cmp r3, #6
- 800354c: d00b beq.n 8003566 <HAL_TIM_Base_Start_IT+0x42>
- 800354e: 68fb ldr r3, [r7, #12]
- 8003550: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8003554: d007 beq.n 8003566 <HAL_TIM_Base_Start_IT+0x42>
- {
- __HAL_TIM_ENABLE(htim);
- 8003556: 687b ldr r3, [r7, #4]
- 8003558: 681b ldr r3, [r3, #0]
- 800355a: 681a ldr r2, [r3, #0]
- 800355c: 687b ldr r3, [r7, #4]
- 800355e: 681b ldr r3, [r3, #0]
- 8003560: f042 0201 orr.w r2, r2, #1
- 8003564: 601a str r2, [r3, #0]
- }
-
- /* Return function status */
- return HAL_OK;
- 8003566: 2300 movs r3, #0
-}
- 8003568: 4618 mov r0, r3
- 800356a: 3714 adds r7, #20
- 800356c: 46bd mov sp, r7
- 800356e: f85d 7b04 ldr.w r7, [sp], #4
- 8003572: 4770 bx lr
- 8003574: 00010007 .word 0x00010007
-
-08003578 <HAL_TIM_PWM_Init>:
- * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
- * @param htim TIM PWM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
-{
- 8003578: b580 push {r7, lr}
- 800357a: b082 sub sp, #8
- 800357c: af00 add r7, sp, #0
- 800357e: 6078 str r0, [r7, #4]
- /* Check the TIM handle allocation */
- if (htim == NULL)
- 8003580: 687b ldr r3, [r7, #4]
- 8003582: 2b00 cmp r3, #0
- 8003584: d101 bne.n 800358a <HAL_TIM_PWM_Init+0x12>
- {
- return HAL_ERROR;
- 8003586: 2301 movs r3, #1
- 8003588: e01d b.n 80035c6 <HAL_TIM_PWM_Init+0x4e>
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- 800358a: 687b ldr r3, [r7, #4]
- 800358c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
- 8003590: b2db uxtb r3, r3
- 8003592: 2b00 cmp r3, #0
- 8003594: d106 bne.n 80035a4 <HAL_TIM_PWM_Init+0x2c>
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
- 8003596: 687b ldr r3, [r7, #4]
- 8003598: 2200 movs r2, #0
- 800359a: f883 203c strb.w r2, [r3, #60] ; 0x3c
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->PWM_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_PWM_MspInit(htim);
- 800359e: 6878 ldr r0, [r7, #4]
- 80035a0: f000 f815 bl 80035ce <HAL_TIM_PWM_MspInit>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
- 80035a4: 687b ldr r3, [r7, #4]
- 80035a6: 2202 movs r2, #2
- 80035a8: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Init the base time for the PWM */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 80035ac: 687b ldr r3, [r7, #4]
- 80035ae: 681a ldr r2, [r3, #0]
- 80035b0: 687b ldr r3, [r7, #4]
- 80035b2: 3304 adds r3, #4
- 80035b4: 4619 mov r1, r3
- 80035b6: 4610 mov r0, r2
- 80035b8: f000 fc3a bl 8003e30 <TIM_Base_SetConfig>
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
- 80035bc: 687b ldr r3, [r7, #4]
- 80035be: 2201 movs r2, #1
- 80035c0: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- return HAL_OK;
- 80035c4: 2300 movs r3, #0
-}
- 80035c6: 4618 mov r0, r3
- 80035c8: 3708 adds r7, #8
- 80035ca: 46bd mov sp, r7
- 80035cc: bd80 pop {r7, pc}
-
-080035ce <HAL_TIM_PWM_MspInit>:
- * @brief Initializes the TIM PWM MSP.
- * @param htim TIM PWM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
-{
- 80035ce: b480 push {r7}
- 80035d0: b083 sub sp, #12
- 80035d2: af00 add r7, sp, #0
- 80035d4: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_MspInit could be implemented in the user file
- */
-}
- 80035d6: bf00 nop
- 80035d8: 370c adds r7, #12
- 80035da: 46bd mov sp, r7
- 80035dc: f85d 7b04 ldr.w r7, [sp], #4
- 80035e0: 4770 bx lr
- ...
-
-080035e4 <HAL_TIM_PWM_Start>:
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- 80035e4: b580 push {r7, lr}
- 80035e6: b084 sub sp, #16
- 80035e8: af00 add r7, sp, #0
- 80035ea: 6078 str r0, [r7, #4]
- 80035ec: 6039 str r1, [r7, #0]
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- 80035ee: 687b ldr r3, [r7, #4]
- 80035f0: 681b ldr r3, [r3, #0]
- 80035f2: 2201 movs r2, #1
- 80035f4: 6839 ldr r1, [r7, #0]
- 80035f6: 4618 mov r0, r3
- 80035f8: f000 ffb2 bl 8004560 <TIM_CCxChannelCmd>
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- 80035fc: 687b ldr r3, [r7, #4]
- 80035fe: 681b ldr r3, [r3, #0]
- 8003600: 4a17 ldr r2, [pc, #92] ; (8003660 <HAL_TIM_PWM_Start+0x7c>)
- 8003602: 4293 cmp r3, r2
- 8003604: d004 beq.n 8003610 <HAL_TIM_PWM_Start+0x2c>
- 8003606: 687b ldr r3, [r7, #4]
- 8003608: 681b ldr r3, [r3, #0]
- 800360a: 4a16 ldr r2, [pc, #88] ; (8003664 <HAL_TIM_PWM_Start+0x80>)
- 800360c: 4293 cmp r3, r2
- 800360e: d101 bne.n 8003614 <HAL_TIM_PWM_Start+0x30>
- 8003610: 2301 movs r3, #1
- 8003612: e000 b.n 8003616 <HAL_TIM_PWM_Start+0x32>
- 8003614: 2300 movs r3, #0
- 8003616: 2b00 cmp r3, #0
- 8003618: d007 beq.n 800362a <HAL_TIM_PWM_Start+0x46>
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- 800361a: 687b ldr r3, [r7, #4]
- 800361c: 681b ldr r3, [r3, #0]
- 800361e: 6c5a ldr r2, [r3, #68] ; 0x44
- 8003620: 687b ldr r3, [r7, #4]
- 8003622: 681b ldr r3, [r3, #0]
- 8003624: f442 4200 orr.w r2, r2, #32768 ; 0x8000
- 8003628: 645a str r2, [r3, #68] ; 0x44
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- 800362a: 687b ldr r3, [r7, #4]
- 800362c: 681b ldr r3, [r3, #0]
- 800362e: 689a ldr r2, [r3, #8]
- 8003630: 4b0d ldr r3, [pc, #52] ; (8003668 <HAL_TIM_PWM_Start+0x84>)
- 8003632: 4013 ands r3, r2
- 8003634: 60fb str r3, [r7, #12]
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- 8003636: 68fb ldr r3, [r7, #12]
- 8003638: 2b06 cmp r3, #6
- 800363a: d00b beq.n 8003654 <HAL_TIM_PWM_Start+0x70>
- 800363c: 68fb ldr r3, [r7, #12]
- 800363e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8003642: d007 beq.n 8003654 <HAL_TIM_PWM_Start+0x70>
- {
- __HAL_TIM_ENABLE(htim);
- 8003644: 687b ldr r3, [r7, #4]
- 8003646: 681b ldr r3, [r3, #0]
- 8003648: 681a ldr r2, [r3, #0]
- 800364a: 687b ldr r3, [r7, #4]
- 800364c: 681b ldr r3, [r3, #0]
- 800364e: f042 0201 orr.w r2, r2, #1
- 8003652: 601a str r2, [r3, #0]
- }
-
- /* Return function status */
- return HAL_OK;
- 8003654: 2300 movs r3, #0
-}
- 8003656: 4618 mov r0, r3
- 8003658: 3710 adds r7, #16
- 800365a: 46bd mov sp, r7
- 800365c: bd80 pop {r7, pc}
- 800365e: bf00 nop
- 8003660: 40010000 .word 0x40010000
- 8003664: 40010400 .word 0x40010400
- 8003668: 00010007 .word 0x00010007
-
-0800366c <HAL_TIM_Encoder_Init>:
- * @param htim TIM Encoder Interface handle
- * @param sConfig TIM Encoder Interface configuration structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
-{
- 800366c: b580 push {r7, lr}
- 800366e: b086 sub sp, #24
- 8003670: af00 add r7, sp, #0
- 8003672: 6078 str r0, [r7, #4]
- 8003674: 6039 str r1, [r7, #0]
- uint32_t tmpsmcr;
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Check the TIM handle allocation */
- if (htim == NULL)
- 8003676: 687b ldr r3, [r7, #4]
- 8003678: 2b00 cmp r3, #0
- 800367a: d101 bne.n 8003680 <HAL_TIM_Encoder_Init+0x14>
- {
- return HAL_ERROR;
- 800367c: 2301 movs r3, #1
- 800367e: e07b b.n 8003778 <HAL_TIM_Encoder_Init+0x10c>
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- 8003680: 687b ldr r3, [r7, #4]
- 8003682: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
- 8003686: b2db uxtb r3, r3
- 8003688: 2b00 cmp r3, #0
- 800368a: d106 bne.n 800369a <HAL_TIM_Encoder_Init+0x2e>
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
- 800368c: 687b ldr r3, [r7, #4]
- 800368e: 2200 movs r2, #0
- 8003690: f883 203c strb.w r2, [r3, #60] ; 0x3c
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->Encoder_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_Encoder_MspInit(htim);
- 8003694: 6878 ldr r0, [r7, #4]
- 8003696: f7fe f93f bl 8001918 <HAL_TIM_Encoder_MspInit>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
- 800369a: 687b ldr r3, [r7, #4]
- 800369c: 2202 movs r2, #2
- 800369e: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Reset the SMS and ECE bits */
- htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
- 80036a2: 687b ldr r3, [r7, #4]
- 80036a4: 681b ldr r3, [r3, #0]
- 80036a6: 6899 ldr r1, [r3, #8]
- 80036a8: 687b ldr r3, [r7, #4]
- 80036aa: 681a ldr r2, [r3, #0]
- 80036ac: 4b34 ldr r3, [pc, #208] ; (8003780 <HAL_TIM_Encoder_Init+0x114>)
- 80036ae: 400b ands r3, r1
- 80036b0: 6093 str r3, [r2, #8]
-
- /* Configure the Time base in the Encoder Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 80036b2: 687b ldr r3, [r7, #4]
- 80036b4: 681a ldr r2, [r3, #0]
- 80036b6: 687b ldr r3, [r7, #4]
- 80036b8: 3304 adds r3, #4
- 80036ba: 4619 mov r1, r3
- 80036bc: 4610 mov r0, r2
- 80036be: f000 fbb7 bl 8003e30 <TIM_Base_SetConfig>
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
- 80036c2: 687b ldr r3, [r7, #4]
- 80036c4: 681b ldr r3, [r3, #0]
- 80036c6: 689b ldr r3, [r3, #8]
- 80036c8: 617b str r3, [r7, #20]
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = htim->Instance->CCMR1;
- 80036ca: 687b ldr r3, [r7, #4]
- 80036cc: 681b ldr r3, [r3, #0]
- 80036ce: 699b ldr r3, [r3, #24]
- 80036d0: 613b str r3, [r7, #16]
-
- /* Get the TIMx CCER register value */
- tmpccer = htim->Instance->CCER;
- 80036d2: 687b ldr r3, [r7, #4]
- 80036d4: 681b ldr r3, [r3, #0]
- 80036d6: 6a1b ldr r3, [r3, #32]
- 80036d8: 60fb str r3, [r7, #12]
-
- /* Set the encoder Mode */
- tmpsmcr |= sConfig->EncoderMode;
- 80036da: 683b ldr r3, [r7, #0]
- 80036dc: 681b ldr r3, [r3, #0]
- 80036de: 697a ldr r2, [r7, #20]
- 80036e0: 4313 orrs r3, r2
- 80036e2: 617b str r3, [r7, #20]
-
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
- 80036e4: 693a ldr r2, [r7, #16]
- 80036e6: 4b27 ldr r3, [pc, #156] ; (8003784 <HAL_TIM_Encoder_Init+0x118>)
- 80036e8: 4013 ands r3, r2
- 80036ea: 613b str r3, [r7, #16]
- tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
- 80036ec: 683b ldr r3, [r7, #0]
- 80036ee: 689a ldr r2, [r3, #8]
- 80036f0: 683b ldr r3, [r7, #0]
- 80036f2: 699b ldr r3, [r3, #24]
- 80036f4: 021b lsls r3, r3, #8
- 80036f6: 4313 orrs r3, r2
- 80036f8: 693a ldr r2, [r7, #16]
- 80036fa: 4313 orrs r3, r2
- 80036fc: 613b str r3, [r7, #16]
-
- /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
- tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
- 80036fe: 693a ldr r2, [r7, #16]
- 8003700: 4b21 ldr r3, [pc, #132] ; (8003788 <HAL_TIM_Encoder_Init+0x11c>)
- 8003702: 4013 ands r3, r2
- 8003704: 613b str r3, [r7, #16]
- tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
- 8003706: 693a ldr r2, [r7, #16]
- 8003708: 4b20 ldr r3, [pc, #128] ; (800378c <HAL_TIM_Encoder_Init+0x120>)
- 800370a: 4013 ands r3, r2
- 800370c: 613b str r3, [r7, #16]
- tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
- 800370e: 683b ldr r3, [r7, #0]
- 8003710: 68da ldr r2, [r3, #12]
- 8003712: 683b ldr r3, [r7, #0]
- 8003714: 69db ldr r3, [r3, #28]
- 8003716: 021b lsls r3, r3, #8
- 8003718: 4313 orrs r3, r2
- 800371a: 693a ldr r2, [r7, #16]
- 800371c: 4313 orrs r3, r2
- 800371e: 613b str r3, [r7, #16]
- tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
- 8003720: 683b ldr r3, [r7, #0]
- 8003722: 691b ldr r3, [r3, #16]
- 8003724: 011a lsls r2, r3, #4
- 8003726: 683b ldr r3, [r7, #0]
- 8003728: 6a1b ldr r3, [r3, #32]
- 800372a: 031b lsls r3, r3, #12
- 800372c: 4313 orrs r3, r2
- 800372e: 693a ldr r2, [r7, #16]
- 8003730: 4313 orrs r3, r2
- 8003732: 613b str r3, [r7, #16]
-
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
- 8003734: 68fb ldr r3, [r7, #12]
- 8003736: f023 0322 bic.w r3, r3, #34 ; 0x22
- 800373a: 60fb str r3, [r7, #12]
- tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
- 800373c: 68fb ldr r3, [r7, #12]
- 800373e: f023 0388 bic.w r3, r3, #136 ; 0x88
- 8003742: 60fb str r3, [r7, #12]
- tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
- 8003744: 683b ldr r3, [r7, #0]
- 8003746: 685a ldr r2, [r3, #4]
- 8003748: 683b ldr r3, [r7, #0]
- 800374a: 695b ldr r3, [r3, #20]
- 800374c: 011b lsls r3, r3, #4
- 800374e: 4313 orrs r3, r2
- 8003750: 68fa ldr r2, [r7, #12]
- 8003752: 4313 orrs r3, r2
- 8003754: 60fb str r3, [r7, #12]
-
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
- 8003756: 687b ldr r3, [r7, #4]
- 8003758: 681b ldr r3, [r3, #0]
- 800375a: 697a ldr r2, [r7, #20]
- 800375c: 609a str r2, [r3, #8]
-
- /* Write to TIMx CCMR1 */
- htim->Instance->CCMR1 = tmpccmr1;
- 800375e: 687b ldr r3, [r7, #4]
- 8003760: 681b ldr r3, [r3, #0]
- 8003762: 693a ldr r2, [r7, #16]
- 8003764: 619a str r2, [r3, #24]
-
- /* Write to TIMx CCER */
- htim->Instance->CCER = tmpccer;
- 8003766: 687b ldr r3, [r7, #4]
- 8003768: 681b ldr r3, [r3, #0]
- 800376a: 68fa ldr r2, [r7, #12]
- 800376c: 621a str r2, [r3, #32]
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
- 800376e: 687b ldr r3, [r7, #4]
- 8003770: 2201 movs r2, #1
- 8003772: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- return HAL_OK;
- 8003776: 2300 movs r3, #0
-}
- 8003778: 4618 mov r0, r3
- 800377a: 3718 adds r7, #24
- 800377c: 46bd mov sp, r7
- 800377e: bd80 pop {r7, pc}
- 8003780: fffebff8 .word 0xfffebff8
- 8003784: fffffcfc .word 0xfffffcfc
- 8003788: fffff3f3 .word 0xfffff3f3
- 800378c: ffff0f0f .word 0xffff0f0f
-
-08003790 <HAL_TIM_Encoder_Start>:
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- 8003790: b580 push {r7, lr}
- 8003792: b082 sub sp, #8
- 8003794: af00 add r7, sp, #0
- 8003796: 6078 str r0, [r7, #4]
- 8003798: 6039 str r1, [r7, #0]
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Enable the encoder interface channels */
- switch (Channel)
- 800379a: 683b ldr r3, [r7, #0]
- 800379c: 2b00 cmp r3, #0
- 800379e: d002 beq.n 80037a6 <HAL_TIM_Encoder_Start+0x16>
- 80037a0: 2b04 cmp r3, #4
- 80037a2: d008 beq.n 80037b6 <HAL_TIM_Encoder_Start+0x26>
- 80037a4: e00f b.n 80037c6 <HAL_TIM_Encoder_Start+0x36>
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- 80037a6: 687b ldr r3, [r7, #4]
- 80037a8: 681b ldr r3, [r3, #0]
- 80037aa: 2201 movs r2, #1
- 80037ac: 2100 movs r1, #0
- 80037ae: 4618 mov r0, r3
- 80037b0: f000 fed6 bl 8004560 <TIM_CCxChannelCmd>
- break;
- 80037b4: e016 b.n 80037e4 <HAL_TIM_Encoder_Start+0x54>
- }
-
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- 80037b6: 687b ldr r3, [r7, #4]
- 80037b8: 681b ldr r3, [r3, #0]
- 80037ba: 2201 movs r2, #1
- 80037bc: 2104 movs r1, #4
- 80037be: 4618 mov r0, r3
- 80037c0: f000 fece bl 8004560 <TIM_CCxChannelCmd>
- break;
- 80037c4: e00e b.n 80037e4 <HAL_TIM_Encoder_Start+0x54>
- }
-
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- 80037c6: 687b ldr r3, [r7, #4]
- 80037c8: 681b ldr r3, [r3, #0]
- 80037ca: 2201 movs r2, #1
- 80037cc: 2100 movs r1, #0
- 80037ce: 4618 mov r0, r3
- 80037d0: f000 fec6 bl 8004560 <TIM_CCxChannelCmd>
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- 80037d4: 687b ldr r3, [r7, #4]
- 80037d6: 681b ldr r3, [r3, #0]
- 80037d8: 2201 movs r2, #1
- 80037da: 2104 movs r1, #4
- 80037dc: 4618 mov r0, r3
- 80037de: f000 febf bl 8004560 <TIM_CCxChannelCmd>
- break;
- 80037e2: bf00 nop
- }
- }
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
- 80037e4: 687b ldr r3, [r7, #4]
- 80037e6: 681b ldr r3, [r3, #0]
- 80037e8: 681a ldr r2, [r3, #0]
- 80037ea: 687b ldr r3, [r7, #4]
- 80037ec: 681b ldr r3, [r3, #0]
- 80037ee: f042 0201 orr.w r2, r2, #1
- 80037f2: 601a str r2, [r3, #0]
-
- /* Return function status */
- return HAL_OK;
- 80037f4: 2300 movs r3, #0
-}
- 80037f6: 4618 mov r0, r3
- 80037f8: 3708 adds r7, #8
- 80037fa: 46bd mov sp, r7
- 80037fc: bd80 pop {r7, pc}
-
-080037fe <HAL_TIM_IRQHandler>:
- * @brief This function handles TIM interrupts requests.
- * @param htim TIM handle
- * @retval None
- */
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
-{
- 80037fe: b580 push {r7, lr}
- 8003800: b082 sub sp, #8
- 8003802: af00 add r7, sp, #0
- 8003804: 6078 str r0, [r7, #4]
- /* Capture compare 1 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
- 8003806: 687b ldr r3, [r7, #4]
- 8003808: 681b ldr r3, [r3, #0]
- 800380a: 691b ldr r3, [r3, #16]
- 800380c: f003 0302 and.w r3, r3, #2
- 8003810: 2b02 cmp r3, #2
- 8003812: d122 bne.n 800385a <HAL_TIM_IRQHandler+0x5c>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
- 8003814: 687b ldr r3, [r7, #4]
- 8003816: 681b ldr r3, [r3, #0]
- 8003818: 68db ldr r3, [r3, #12]
- 800381a: f003 0302 and.w r3, r3, #2
- 800381e: 2b02 cmp r3, #2
- 8003820: d11b bne.n 800385a <HAL_TIM_IRQHandler+0x5c>
- {
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
- 8003822: 687b ldr r3, [r7, #4]
- 8003824: 681b ldr r3, [r3, #0]
- 8003826: f06f 0202 mvn.w r2, #2
- 800382a: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- 800382c: 687b ldr r3, [r7, #4]
- 800382e: 2201 movs r2, #1
- 8003830: 771a strb r2, [r3, #28]
-
- /* Input capture event */
- if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
- 8003832: 687b ldr r3, [r7, #4]
- 8003834: 681b ldr r3, [r3, #0]
- 8003836: 699b ldr r3, [r3, #24]
- 8003838: f003 0303 and.w r3, r3, #3
- 800383c: 2b00 cmp r3, #0
- 800383e: d003 beq.n 8003848 <HAL_TIM_IRQHandler+0x4a>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 8003840: 6878 ldr r0, [r7, #4]
- 8003842: f000 fad7 bl 8003df4 <HAL_TIM_IC_CaptureCallback>
- 8003846: e005 b.n 8003854 <HAL_TIM_IRQHandler+0x56>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 8003848: 6878 ldr r0, [r7, #4]
- 800384a: f000 fac9 bl 8003de0 <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 800384e: 6878 ldr r0, [r7, #4]
- 8003850: f000 fada bl 8003e08 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 8003854: 687b ldr r3, [r7, #4]
- 8003856: 2200 movs r2, #0
- 8003858: 771a strb r2, [r3, #28]
- }
- }
- }
- /* Capture compare 2 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
- 800385a: 687b ldr r3, [r7, #4]
- 800385c: 681b ldr r3, [r3, #0]
- 800385e: 691b ldr r3, [r3, #16]
- 8003860: f003 0304 and.w r3, r3, #4
- 8003864: 2b04 cmp r3, #4
- 8003866: d122 bne.n 80038ae <HAL_TIM_IRQHandler+0xb0>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
- 8003868: 687b ldr r3, [r7, #4]
- 800386a: 681b ldr r3, [r3, #0]
- 800386c: 68db ldr r3, [r3, #12]
- 800386e: f003 0304 and.w r3, r3, #4
- 8003872: 2b04 cmp r3, #4
- 8003874: d11b bne.n 80038ae <HAL_TIM_IRQHandler+0xb0>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
- 8003876: 687b ldr r3, [r7, #4]
- 8003878: 681b ldr r3, [r3, #0]
- 800387a: f06f 0204 mvn.w r2, #4
- 800387e: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- 8003880: 687b ldr r3, [r7, #4]
- 8003882: 2202 movs r2, #2
- 8003884: 771a strb r2, [r3, #28]
- /* Input capture event */
- if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
- 8003886: 687b ldr r3, [r7, #4]
- 8003888: 681b ldr r3, [r3, #0]
- 800388a: 699b ldr r3, [r3, #24]
- 800388c: f403 7340 and.w r3, r3, #768 ; 0x300
- 8003890: 2b00 cmp r3, #0
- 8003892: d003 beq.n 800389c <HAL_TIM_IRQHandler+0x9e>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 8003894: 6878 ldr r0, [r7, #4]
- 8003896: f000 faad bl 8003df4 <HAL_TIM_IC_CaptureCallback>
- 800389a: e005 b.n 80038a8 <HAL_TIM_IRQHandler+0xaa>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 800389c: 6878 ldr r0, [r7, #4]
- 800389e: f000 fa9f bl 8003de0 <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 80038a2: 6878 ldr r0, [r7, #4]
- 80038a4: f000 fab0 bl 8003e08 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 80038a8: 687b ldr r3, [r7, #4]
- 80038aa: 2200 movs r2, #0
- 80038ac: 771a strb r2, [r3, #28]
- }
- }
- /* Capture compare 3 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
- 80038ae: 687b ldr r3, [r7, #4]
- 80038b0: 681b ldr r3, [r3, #0]
- 80038b2: 691b ldr r3, [r3, #16]
- 80038b4: f003 0308 and.w r3, r3, #8
- 80038b8: 2b08 cmp r3, #8
- 80038ba: d122 bne.n 8003902 <HAL_TIM_IRQHandler+0x104>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
- 80038bc: 687b ldr r3, [r7, #4]
- 80038be: 681b ldr r3, [r3, #0]
- 80038c0: 68db ldr r3, [r3, #12]
- 80038c2: f003 0308 and.w r3, r3, #8
- 80038c6: 2b08 cmp r3, #8
- 80038c8: d11b bne.n 8003902 <HAL_TIM_IRQHandler+0x104>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
- 80038ca: 687b ldr r3, [r7, #4]
- 80038cc: 681b ldr r3, [r3, #0]
- 80038ce: f06f 0208 mvn.w r2, #8
- 80038d2: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- 80038d4: 687b ldr r3, [r7, #4]
- 80038d6: 2204 movs r2, #4
- 80038d8: 771a strb r2, [r3, #28]
- /* Input capture event */
- if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
- 80038da: 687b ldr r3, [r7, #4]
- 80038dc: 681b ldr r3, [r3, #0]
- 80038de: 69db ldr r3, [r3, #28]
- 80038e0: f003 0303 and.w r3, r3, #3
- 80038e4: 2b00 cmp r3, #0
- 80038e6: d003 beq.n 80038f0 <HAL_TIM_IRQHandler+0xf2>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 80038e8: 6878 ldr r0, [r7, #4]
- 80038ea: f000 fa83 bl 8003df4 <HAL_TIM_IC_CaptureCallback>
- 80038ee: e005 b.n 80038fc <HAL_TIM_IRQHandler+0xfe>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 80038f0: 6878 ldr r0, [r7, #4]
- 80038f2: f000 fa75 bl 8003de0 <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 80038f6: 6878 ldr r0, [r7, #4]
- 80038f8: f000 fa86 bl 8003e08 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 80038fc: 687b ldr r3, [r7, #4]
- 80038fe: 2200 movs r2, #0
- 8003900: 771a strb r2, [r3, #28]
- }
- }
- /* Capture compare 4 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
- 8003902: 687b ldr r3, [r7, #4]
- 8003904: 681b ldr r3, [r3, #0]
- 8003906: 691b ldr r3, [r3, #16]
- 8003908: f003 0310 and.w r3, r3, #16
- 800390c: 2b10 cmp r3, #16
- 800390e: d122 bne.n 8003956 <HAL_TIM_IRQHandler+0x158>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
- 8003910: 687b ldr r3, [r7, #4]
- 8003912: 681b ldr r3, [r3, #0]
- 8003914: 68db ldr r3, [r3, #12]
- 8003916: f003 0310 and.w r3, r3, #16
- 800391a: 2b10 cmp r3, #16
- 800391c: d11b bne.n 8003956 <HAL_TIM_IRQHandler+0x158>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
- 800391e: 687b ldr r3, [r7, #4]
- 8003920: 681b ldr r3, [r3, #0]
- 8003922: f06f 0210 mvn.w r2, #16
- 8003926: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- 8003928: 687b ldr r3, [r7, #4]
- 800392a: 2208 movs r2, #8
- 800392c: 771a strb r2, [r3, #28]
- /* Input capture event */
- if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
- 800392e: 687b ldr r3, [r7, #4]
- 8003930: 681b ldr r3, [r3, #0]
- 8003932: 69db ldr r3, [r3, #28]
- 8003934: f403 7340 and.w r3, r3, #768 ; 0x300
- 8003938: 2b00 cmp r3, #0
- 800393a: d003 beq.n 8003944 <HAL_TIM_IRQHandler+0x146>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 800393c: 6878 ldr r0, [r7, #4]
- 800393e: f000 fa59 bl 8003df4 <HAL_TIM_IC_CaptureCallback>
- 8003942: e005 b.n 8003950 <HAL_TIM_IRQHandler+0x152>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 8003944: 6878 ldr r0, [r7, #4]
- 8003946: f000 fa4b bl 8003de0 <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 800394a: 6878 ldr r0, [r7, #4]
- 800394c: f000 fa5c bl 8003e08 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 8003950: 687b ldr r3, [r7, #4]
- 8003952: 2200 movs r2, #0
- 8003954: 771a strb r2, [r3, #28]
- }
- }
- /* TIM Update event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
- 8003956: 687b ldr r3, [r7, #4]
- 8003958: 681b ldr r3, [r3, #0]
- 800395a: 691b ldr r3, [r3, #16]
- 800395c: f003 0301 and.w r3, r3, #1
- 8003960: 2b01 cmp r3, #1
- 8003962: d10e bne.n 8003982 <HAL_TIM_IRQHandler+0x184>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
- 8003964: 687b ldr r3, [r7, #4]
- 8003966: 681b ldr r3, [r3, #0]
- 8003968: 68db ldr r3, [r3, #12]
- 800396a: f003 0301 and.w r3, r3, #1
- 800396e: 2b01 cmp r3, #1
- 8003970: d107 bne.n 8003982 <HAL_TIM_IRQHandler+0x184>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
- 8003972: 687b ldr r3, [r7, #4]
- 8003974: 681b ldr r3, [r3, #0]
- 8003976: f06f 0201 mvn.w r2, #1
- 800397a: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PeriodElapsedCallback(htim);
-#else
- HAL_TIM_PeriodElapsedCallback(htim);
- 800397c: 6878 ldr r0, [r7, #4]
- 800397e: f7fd fcfb bl 8001378 <HAL_TIM_PeriodElapsedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Break input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
- 8003982: 687b ldr r3, [r7, #4]
- 8003984: 681b ldr r3, [r3, #0]
- 8003986: 691b ldr r3, [r3, #16]
- 8003988: f003 0380 and.w r3, r3, #128 ; 0x80
- 800398c: 2b80 cmp r3, #128 ; 0x80
- 800398e: d10e bne.n 80039ae <HAL_TIM_IRQHandler+0x1b0>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
- 8003990: 687b ldr r3, [r7, #4]
- 8003992: 681b ldr r3, [r3, #0]
- 8003994: 68db ldr r3, [r3, #12]
- 8003996: f003 0380 and.w r3, r3, #128 ; 0x80
- 800399a: 2b80 cmp r3, #128 ; 0x80
- 800399c: d107 bne.n 80039ae <HAL_TIM_IRQHandler+0x1b0>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
- 800399e: 687b ldr r3, [r7, #4]
- 80039a0: 681b ldr r3, [r3, #0]
- 80039a2: f06f 0280 mvn.w r2, #128 ; 0x80
- 80039a6: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->BreakCallback(htim);
-#else
- HAL_TIMEx_BreakCallback(htim);
- 80039a8: 6878 ldr r0, [r7, #4]
- 80039aa: f000 fe65 bl 8004678 <HAL_TIMEx_BreakCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Break2 input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
- 80039ae: 687b ldr r3, [r7, #4]
- 80039b0: 681b ldr r3, [r3, #0]
- 80039b2: 691b ldr r3, [r3, #16]
- 80039b4: f403 7380 and.w r3, r3, #256 ; 0x100
- 80039b8: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 80039bc: d10e bne.n 80039dc <HAL_TIM_IRQHandler+0x1de>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
- 80039be: 687b ldr r3, [r7, #4]
- 80039c0: 681b ldr r3, [r3, #0]
- 80039c2: 68db ldr r3, [r3, #12]
- 80039c4: f003 0380 and.w r3, r3, #128 ; 0x80
- 80039c8: 2b80 cmp r3, #128 ; 0x80
- 80039ca: d107 bne.n 80039dc <HAL_TIM_IRQHandler+0x1de>
- {
- __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
- 80039cc: 687b ldr r3, [r7, #4]
- 80039ce: 681b ldr r3, [r3, #0]
- 80039d0: f46f 7280 mvn.w r2, #256 ; 0x100
- 80039d4: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->Break2Callback(htim);
-#else
- HAL_TIMEx_Break2Callback(htim);
- 80039d6: 6878 ldr r0, [r7, #4]
- 80039d8: f000 fe58 bl 800468c <HAL_TIMEx_Break2Callback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Trigger detection event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
- 80039dc: 687b ldr r3, [r7, #4]
- 80039de: 681b ldr r3, [r3, #0]
- 80039e0: 691b ldr r3, [r3, #16]
- 80039e2: f003 0340 and.w r3, r3, #64 ; 0x40
- 80039e6: 2b40 cmp r3, #64 ; 0x40
- 80039e8: d10e bne.n 8003a08 <HAL_TIM_IRQHandler+0x20a>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
- 80039ea: 687b ldr r3, [r7, #4]
- 80039ec: 681b ldr r3, [r3, #0]
- 80039ee: 68db ldr r3, [r3, #12]
- 80039f0: f003 0340 and.w r3, r3, #64 ; 0x40
- 80039f4: 2b40 cmp r3, #64 ; 0x40
- 80039f6: d107 bne.n 8003a08 <HAL_TIM_IRQHandler+0x20a>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
- 80039f8: 687b ldr r3, [r7, #4]
- 80039fa: 681b ldr r3, [r3, #0]
- 80039fc: f06f 0240 mvn.w r2, #64 ; 0x40
- 8003a00: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->TriggerCallback(htim);
-#else
- HAL_TIM_TriggerCallback(htim);
- 8003a02: 6878 ldr r0, [r7, #4]
- 8003a04: f000 fa0a bl 8003e1c <HAL_TIM_TriggerCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM commutation event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
- 8003a08: 687b ldr r3, [r7, #4]
- 8003a0a: 681b ldr r3, [r3, #0]
- 8003a0c: 691b ldr r3, [r3, #16]
- 8003a0e: f003 0320 and.w r3, r3, #32
- 8003a12: 2b20 cmp r3, #32
- 8003a14: d10e bne.n 8003a34 <HAL_TIM_IRQHandler+0x236>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
- 8003a16: 687b ldr r3, [r7, #4]
- 8003a18: 681b ldr r3, [r3, #0]
- 8003a1a: 68db ldr r3, [r3, #12]
- 8003a1c: f003 0320 and.w r3, r3, #32
- 8003a20: 2b20 cmp r3, #32
- 8003a22: d107 bne.n 8003a34 <HAL_TIM_IRQHandler+0x236>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
- 8003a24: 687b ldr r3, [r7, #4]
- 8003a26: 681b ldr r3, [r3, #0]
- 8003a28: f06f 0220 mvn.w r2, #32
- 8003a2c: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->CommutationCallback(htim);
-#else
- HAL_TIMEx_CommutCallback(htim);
- 8003a2e: 6878 ldr r0, [r7, #4]
- 8003a30: f000 fe18 bl 8004664 <HAL_TIMEx_CommutCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
-}
- 8003a34: bf00 nop
- 8003a36: 3708 adds r7, #8
- 8003a38: 46bd mov sp, r7
- 8003a3a: bd80 pop {r7, pc}
-
-08003a3c <HAL_TIM_PWM_ConfigChannel>:
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef *sConfig,
- uint32_t Channel)
-{
- 8003a3c: b580 push {r7, lr}
- 8003a3e: b084 sub sp, #16
- 8003a40: af00 add r7, sp, #0
- 8003a42: 60f8 str r0, [r7, #12]
- 8003a44: 60b9 str r1, [r7, #8]
- 8003a46: 607a str r2, [r7, #4]
- assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
- /* Process Locked */
- __HAL_LOCK(htim);
- 8003a48: 68fb ldr r3, [r7, #12]
- 8003a4a: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 8003a4e: 2b01 cmp r3, #1
- 8003a50: d101 bne.n 8003a56 <HAL_TIM_PWM_ConfigChannel+0x1a>
- 8003a52: 2302 movs r3, #2
- 8003a54: e105 b.n 8003c62 <HAL_TIM_PWM_ConfigChannel+0x226>
- 8003a56: 68fb ldr r3, [r7, #12]
- 8003a58: 2201 movs r2, #1
- 8003a5a: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- htim->State = HAL_TIM_STATE_BUSY;
- 8003a5e: 68fb ldr r3, [r7, #12]
- 8003a60: 2202 movs r2, #2
- 8003a62: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- switch (Channel)
- 8003a66: 687b ldr r3, [r7, #4]
- 8003a68: 2b14 cmp r3, #20
- 8003a6a: f200 80f0 bhi.w 8003c4e <HAL_TIM_PWM_ConfigChannel+0x212>
- 8003a6e: a201 add r2, pc, #4 ; (adr r2, 8003a74 <HAL_TIM_PWM_ConfigChannel+0x38>)
- 8003a70: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8003a74: 08003ac9 .word 0x08003ac9
- 8003a78: 08003c4f .word 0x08003c4f
- 8003a7c: 08003c4f .word 0x08003c4f
- 8003a80: 08003c4f .word 0x08003c4f
- 8003a84: 08003b09 .word 0x08003b09
- 8003a88: 08003c4f .word 0x08003c4f
- 8003a8c: 08003c4f .word 0x08003c4f
- 8003a90: 08003c4f .word 0x08003c4f
- 8003a94: 08003b4b .word 0x08003b4b
- 8003a98: 08003c4f .word 0x08003c4f
- 8003a9c: 08003c4f .word 0x08003c4f
- 8003aa0: 08003c4f .word 0x08003c4f
- 8003aa4: 08003b8b .word 0x08003b8b
- 8003aa8: 08003c4f .word 0x08003c4f
- 8003aac: 08003c4f .word 0x08003c4f
- 8003ab0: 08003c4f .word 0x08003c4f
- 8003ab4: 08003bcd .word 0x08003bcd
- 8003ab8: 08003c4f .word 0x08003c4f
- 8003abc: 08003c4f .word 0x08003c4f
- 8003ac0: 08003c4f .word 0x08003c4f
- 8003ac4: 08003c0d .word 0x08003c0d
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Configure the Channel 1 in PWM mode */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
- 8003ac8: 68fb ldr r3, [r7, #12]
- 8003aca: 681b ldr r3, [r3, #0]
- 8003acc: 68b9 ldr r1, [r7, #8]
- 8003ace: 4618 mov r0, r3
- 8003ad0: f000 fa4e bl 8003f70 <TIM_OC1_SetConfig>
-
- /* Set the Preload enable bit for channel1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
- 8003ad4: 68fb ldr r3, [r7, #12]
- 8003ad6: 681b ldr r3, [r3, #0]
- 8003ad8: 699a ldr r2, [r3, #24]
- 8003ada: 68fb ldr r3, [r7, #12]
- 8003adc: 681b ldr r3, [r3, #0]
- 8003ade: f042 0208 orr.w r2, r2, #8
- 8003ae2: 619a str r2, [r3, #24]
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
- 8003ae4: 68fb ldr r3, [r7, #12]
- 8003ae6: 681b ldr r3, [r3, #0]
- 8003ae8: 699a ldr r2, [r3, #24]
- 8003aea: 68fb ldr r3, [r7, #12]
- 8003aec: 681b ldr r3, [r3, #0]
- 8003aee: f022 0204 bic.w r2, r2, #4
- 8003af2: 619a str r2, [r3, #24]
- htim->Instance->CCMR1 |= sConfig->OCFastMode;
- 8003af4: 68fb ldr r3, [r7, #12]
- 8003af6: 681b ldr r3, [r3, #0]
- 8003af8: 6999 ldr r1, [r3, #24]
- 8003afa: 68bb ldr r3, [r7, #8]
- 8003afc: 691a ldr r2, [r3, #16]
- 8003afe: 68fb ldr r3, [r7, #12]
- 8003b00: 681b ldr r3, [r3, #0]
- 8003b02: 430a orrs r2, r1
- 8003b04: 619a str r2, [r3, #24]
- break;
- 8003b06: e0a3 b.n 8003c50 <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Configure the Channel 2 in PWM mode */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
- 8003b08: 68fb ldr r3, [r7, #12]
- 8003b0a: 681b ldr r3, [r3, #0]
- 8003b0c: 68b9 ldr r1, [r7, #8]
- 8003b0e: 4618 mov r0, r3
- 8003b10: f000 faa0 bl 8004054 <TIM_OC2_SetConfig>
-
- /* Set the Preload enable bit for channel2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
- 8003b14: 68fb ldr r3, [r7, #12]
- 8003b16: 681b ldr r3, [r3, #0]
- 8003b18: 699a ldr r2, [r3, #24]
- 8003b1a: 68fb ldr r3, [r7, #12]
- 8003b1c: 681b ldr r3, [r3, #0]
- 8003b1e: f442 6200 orr.w r2, r2, #2048 ; 0x800
- 8003b22: 619a str r2, [r3, #24]
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- 8003b24: 68fb ldr r3, [r7, #12]
- 8003b26: 681b ldr r3, [r3, #0]
- 8003b28: 699a ldr r2, [r3, #24]
- 8003b2a: 68fb ldr r3, [r7, #12]
- 8003b2c: 681b ldr r3, [r3, #0]
- 8003b2e: f422 6280 bic.w r2, r2, #1024 ; 0x400
- 8003b32: 619a str r2, [r3, #24]
- htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
- 8003b34: 68fb ldr r3, [r7, #12]
- 8003b36: 681b ldr r3, [r3, #0]
- 8003b38: 6999 ldr r1, [r3, #24]
- 8003b3a: 68bb ldr r3, [r7, #8]
- 8003b3c: 691b ldr r3, [r3, #16]
- 8003b3e: 021a lsls r2, r3, #8
- 8003b40: 68fb ldr r3, [r7, #12]
- 8003b42: 681b ldr r3, [r3, #0]
- 8003b44: 430a orrs r2, r1
- 8003b46: 619a str r2, [r3, #24]
- break;
- 8003b48: e082 b.n 8003c50 <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Configure the Channel 3 in PWM mode */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
- 8003b4a: 68fb ldr r3, [r7, #12]
- 8003b4c: 681b ldr r3, [r3, #0]
- 8003b4e: 68b9 ldr r1, [r7, #8]
- 8003b50: 4618 mov r0, r3
- 8003b52: f000 faf7 bl 8004144 <TIM_OC3_SetConfig>
-
- /* Set the Preload enable bit for channel3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
- 8003b56: 68fb ldr r3, [r7, #12]
- 8003b58: 681b ldr r3, [r3, #0]
- 8003b5a: 69da ldr r2, [r3, #28]
- 8003b5c: 68fb ldr r3, [r7, #12]
- 8003b5e: 681b ldr r3, [r3, #0]
- 8003b60: f042 0208 orr.w r2, r2, #8
- 8003b64: 61da str r2, [r3, #28]
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
- 8003b66: 68fb ldr r3, [r7, #12]
- 8003b68: 681b ldr r3, [r3, #0]
- 8003b6a: 69da ldr r2, [r3, #28]
- 8003b6c: 68fb ldr r3, [r7, #12]
- 8003b6e: 681b ldr r3, [r3, #0]
- 8003b70: f022 0204 bic.w r2, r2, #4
- 8003b74: 61da str r2, [r3, #28]
- htim->Instance->CCMR2 |= sConfig->OCFastMode;
- 8003b76: 68fb ldr r3, [r7, #12]
- 8003b78: 681b ldr r3, [r3, #0]
- 8003b7a: 69d9 ldr r1, [r3, #28]
- 8003b7c: 68bb ldr r3, [r7, #8]
- 8003b7e: 691a ldr r2, [r3, #16]
- 8003b80: 68fb ldr r3, [r7, #12]
- 8003b82: 681b ldr r3, [r3, #0]
- 8003b84: 430a orrs r2, r1
- 8003b86: 61da str r2, [r3, #28]
- break;
- 8003b88: e062 b.n 8003c50 <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Configure the Channel 4 in PWM mode */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
- 8003b8a: 68fb ldr r3, [r7, #12]
- 8003b8c: 681b ldr r3, [r3, #0]
- 8003b8e: 68b9 ldr r1, [r7, #8]
- 8003b90: 4618 mov r0, r3
- 8003b92: f000 fb4d bl 8004230 <TIM_OC4_SetConfig>
-
- /* Set the Preload enable bit for channel4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
- 8003b96: 68fb ldr r3, [r7, #12]
- 8003b98: 681b ldr r3, [r3, #0]
- 8003b9a: 69da ldr r2, [r3, #28]
- 8003b9c: 68fb ldr r3, [r7, #12]
- 8003b9e: 681b ldr r3, [r3, #0]
- 8003ba0: f442 6200 orr.w r2, r2, #2048 ; 0x800
- 8003ba4: 61da str r2, [r3, #28]
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- 8003ba6: 68fb ldr r3, [r7, #12]
- 8003ba8: 681b ldr r3, [r3, #0]
- 8003baa: 69da ldr r2, [r3, #28]
- 8003bac: 68fb ldr r3, [r7, #12]
- 8003bae: 681b ldr r3, [r3, #0]
- 8003bb0: f422 6280 bic.w r2, r2, #1024 ; 0x400
- 8003bb4: 61da str r2, [r3, #28]
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
- 8003bb6: 68fb ldr r3, [r7, #12]
- 8003bb8: 681b ldr r3, [r3, #0]
- 8003bba: 69d9 ldr r1, [r3, #28]
- 8003bbc: 68bb ldr r3, [r7, #8]
- 8003bbe: 691b ldr r3, [r3, #16]
- 8003bc0: 021a lsls r2, r3, #8
- 8003bc2: 68fb ldr r3, [r7, #12]
- 8003bc4: 681b ldr r3, [r3, #0]
- 8003bc6: 430a orrs r2, r1
- 8003bc8: 61da str r2, [r3, #28]
- break;
- 8003bca: e041 b.n 8003c50 <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
- /* Configure the Channel 5 in PWM mode */
- TIM_OC5_SetConfig(htim->Instance, sConfig);
- 8003bcc: 68fb ldr r3, [r7, #12]
- 8003bce: 681b ldr r3, [r3, #0]
- 8003bd0: 68b9 ldr r1, [r7, #8]
- 8003bd2: 4618 mov r0, r3
- 8003bd4: f000 fb84 bl 80042e0 <TIM_OC5_SetConfig>
-
- /* Set the Preload enable bit for channel5*/
- htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
- 8003bd8: 68fb ldr r3, [r7, #12]
- 8003bda: 681b ldr r3, [r3, #0]
- 8003bdc: 6d5a ldr r2, [r3, #84] ; 0x54
- 8003bde: 68fb ldr r3, [r7, #12]
- 8003be0: 681b ldr r3, [r3, #0]
- 8003be2: f042 0208 orr.w r2, r2, #8
- 8003be6: 655a str r2, [r3, #84] ; 0x54
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
- 8003be8: 68fb ldr r3, [r7, #12]
- 8003bea: 681b ldr r3, [r3, #0]
- 8003bec: 6d5a ldr r2, [r3, #84] ; 0x54
- 8003bee: 68fb ldr r3, [r7, #12]
- 8003bf0: 681b ldr r3, [r3, #0]
- 8003bf2: f022 0204 bic.w r2, r2, #4
- 8003bf6: 655a str r2, [r3, #84] ; 0x54
- htim->Instance->CCMR3 |= sConfig->OCFastMode;
- 8003bf8: 68fb ldr r3, [r7, #12]
- 8003bfa: 681b ldr r3, [r3, #0]
- 8003bfc: 6d59 ldr r1, [r3, #84] ; 0x54
- 8003bfe: 68bb ldr r3, [r7, #8]
- 8003c00: 691a ldr r2, [r3, #16]
- 8003c02: 68fb ldr r3, [r7, #12]
- 8003c04: 681b ldr r3, [r3, #0]
- 8003c06: 430a orrs r2, r1
- 8003c08: 655a str r2, [r3, #84] ; 0x54
- break;
- 8003c0a: e021 b.n 8003c50 <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
- /* Configure the Channel 6 in PWM mode */
- TIM_OC6_SetConfig(htim->Instance, sConfig);
- 8003c0c: 68fb ldr r3, [r7, #12]
- 8003c0e: 681b ldr r3, [r3, #0]
- 8003c10: 68b9 ldr r1, [r7, #8]
- 8003c12: 4618 mov r0, r3
- 8003c14: f000 fbb6 bl 8004384 <TIM_OC6_SetConfig>
-
- /* Set the Preload enable bit for channel6 */
- htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
- 8003c18: 68fb ldr r3, [r7, #12]
- 8003c1a: 681b ldr r3, [r3, #0]
- 8003c1c: 6d5a ldr r2, [r3, #84] ; 0x54
- 8003c1e: 68fb ldr r3, [r7, #12]
- 8003c20: 681b ldr r3, [r3, #0]
- 8003c22: f442 6200 orr.w r2, r2, #2048 ; 0x800
- 8003c26: 655a str r2, [r3, #84] ; 0x54
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
- 8003c28: 68fb ldr r3, [r7, #12]
- 8003c2a: 681b ldr r3, [r3, #0]
- 8003c2c: 6d5a ldr r2, [r3, #84] ; 0x54
- 8003c2e: 68fb ldr r3, [r7, #12]
- 8003c30: 681b ldr r3, [r3, #0]
- 8003c32: f422 6280 bic.w r2, r2, #1024 ; 0x400
- 8003c36: 655a str r2, [r3, #84] ; 0x54
- htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
- 8003c38: 68fb ldr r3, [r7, #12]
- 8003c3a: 681b ldr r3, [r3, #0]
- 8003c3c: 6d59 ldr r1, [r3, #84] ; 0x54
- 8003c3e: 68bb ldr r3, [r7, #8]
- 8003c40: 691b ldr r3, [r3, #16]
- 8003c42: 021a lsls r2, r3, #8
- 8003c44: 68fb ldr r3, [r7, #12]
- 8003c46: 681b ldr r3, [r3, #0]
- 8003c48: 430a orrs r2, r1
- 8003c4a: 655a str r2, [r3, #84] ; 0x54
- break;
- 8003c4c: e000 b.n 8003c50 <HAL_TIM_PWM_ConfigChannel+0x214>
- }
-
- default:
- break;
- 8003c4e: bf00 nop
- }
-
- htim->State = HAL_TIM_STATE_READY;
- 8003c50: 68fb ldr r3, [r7, #12]
- 8003c52: 2201 movs r2, #1
- 8003c54: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- __HAL_UNLOCK(htim);
- 8003c58: 68fb ldr r3, [r7, #12]
- 8003c5a: 2200 movs r2, #0
- 8003c5c: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- return HAL_OK;
- 8003c60: 2300 movs r3, #0
-}
- 8003c62: 4618 mov r0, r3
- 8003c64: 3710 adds r7, #16
- 8003c66: 46bd mov sp, r7
- 8003c68: bd80 pop {r7, pc}
- 8003c6a: bf00 nop
-
-08003c6c <HAL_TIM_ConfigClockSource>:
- * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
- * contains the clock source information for the TIM peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
-{
- 8003c6c: b580 push {r7, lr}
- 8003c6e: b084 sub sp, #16
- 8003c70: af00 add r7, sp, #0
- 8003c72: 6078 str r0, [r7, #4]
- 8003c74: 6039 str r1, [r7, #0]
- uint32_t tmpsmcr;
-
- /* Process Locked */
- __HAL_LOCK(htim);
- 8003c76: 687b ldr r3, [r7, #4]
- 8003c78: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 8003c7c: 2b01 cmp r3, #1
- 8003c7e: d101 bne.n 8003c84 <HAL_TIM_ConfigClockSource+0x18>
- 8003c80: 2302 movs r3, #2
- 8003c82: e0a6 b.n 8003dd2 <HAL_TIM_ConfigClockSource+0x166>
- 8003c84: 687b ldr r3, [r7, #4]
- 8003c86: 2201 movs r2, #1
- 8003c88: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- htim->State = HAL_TIM_STATE_BUSY;
- 8003c8c: 687b ldr r3, [r7, #4]
- 8003c8e: 2202 movs r2, #2
- 8003c90: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Check the parameters */
- assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-
- /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
- tmpsmcr = htim->Instance->SMCR;
- 8003c94: 687b ldr r3, [r7, #4]
- 8003c96: 681b ldr r3, [r3, #0]
- 8003c98: 689b ldr r3, [r3, #8]
- 8003c9a: 60fb str r3, [r7, #12]
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
- 8003c9c: 68fa ldr r2, [r7, #12]
- 8003c9e: 4b4f ldr r3, [pc, #316] ; (8003ddc <HAL_TIM_ConfigClockSource+0x170>)
- 8003ca0: 4013 ands r3, r2
- 8003ca2: 60fb str r3, [r7, #12]
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- 8003ca4: 68fb ldr r3, [r7, #12]
- 8003ca6: f423 437f bic.w r3, r3, #65280 ; 0xff00
- 8003caa: 60fb str r3, [r7, #12]
- htim->Instance->SMCR = tmpsmcr;
- 8003cac: 687b ldr r3, [r7, #4]
- 8003cae: 681b ldr r3, [r3, #0]
- 8003cb0: 68fa ldr r2, [r7, #12]
- 8003cb2: 609a str r2, [r3, #8]
-
- switch (sClockSourceConfig->ClockSource)
- 8003cb4: 683b ldr r3, [r7, #0]
- 8003cb6: 681b ldr r3, [r3, #0]
- 8003cb8: 2b40 cmp r3, #64 ; 0x40
- 8003cba: d067 beq.n 8003d8c <HAL_TIM_ConfigClockSource+0x120>
- 8003cbc: 2b40 cmp r3, #64 ; 0x40
- 8003cbe: d80b bhi.n 8003cd8 <HAL_TIM_ConfigClockSource+0x6c>
- 8003cc0: 2b10 cmp r3, #16
- 8003cc2: d073 beq.n 8003dac <HAL_TIM_ConfigClockSource+0x140>
- 8003cc4: 2b10 cmp r3, #16
- 8003cc6: d802 bhi.n 8003cce <HAL_TIM_ConfigClockSource+0x62>
- 8003cc8: 2b00 cmp r3, #0
- 8003cca: d06f beq.n 8003dac <HAL_TIM_ConfigClockSource+0x140>
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- break;
- }
-
- default:
- break;
- 8003ccc: e078 b.n 8003dc0 <HAL_TIM_ConfigClockSource+0x154>
- switch (sClockSourceConfig->ClockSource)
- 8003cce: 2b20 cmp r3, #32
- 8003cd0: d06c beq.n 8003dac <HAL_TIM_ConfigClockSource+0x140>
- 8003cd2: 2b30 cmp r3, #48 ; 0x30
- 8003cd4: d06a beq.n 8003dac <HAL_TIM_ConfigClockSource+0x140>
- break;
- 8003cd6: e073 b.n 8003dc0 <HAL_TIM_ConfigClockSource+0x154>
- switch (sClockSourceConfig->ClockSource)
- 8003cd8: 2b70 cmp r3, #112 ; 0x70
- 8003cda: d00d beq.n 8003cf8 <HAL_TIM_ConfigClockSource+0x8c>
- 8003cdc: 2b70 cmp r3, #112 ; 0x70
- 8003cde: d804 bhi.n 8003cea <HAL_TIM_ConfigClockSource+0x7e>
- 8003ce0: 2b50 cmp r3, #80 ; 0x50
- 8003ce2: d033 beq.n 8003d4c <HAL_TIM_ConfigClockSource+0xe0>
- 8003ce4: 2b60 cmp r3, #96 ; 0x60
- 8003ce6: d041 beq.n 8003d6c <HAL_TIM_ConfigClockSource+0x100>
- break;
- 8003ce8: e06a b.n 8003dc0 <HAL_TIM_ConfigClockSource+0x154>
- switch (sClockSourceConfig->ClockSource)
- 8003cea: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8003cee: d066 beq.n 8003dbe <HAL_TIM_ConfigClockSource+0x152>
- 8003cf0: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 8003cf4: d017 beq.n 8003d26 <HAL_TIM_ConfigClockSource+0xba>
- break;
- 8003cf6: e063 b.n 8003dc0 <HAL_TIM_ConfigClockSource+0x154>
- TIM_ETR_SetConfig(htim->Instance,
- 8003cf8: 687b ldr r3, [r7, #4]
- 8003cfa: 6818 ldr r0, [r3, #0]
- 8003cfc: 683b ldr r3, [r7, #0]
- 8003cfe: 6899 ldr r1, [r3, #8]
- 8003d00: 683b ldr r3, [r7, #0]
- 8003d02: 685a ldr r2, [r3, #4]
- 8003d04: 683b ldr r3, [r7, #0]
- 8003d06: 68db ldr r3, [r3, #12]
- 8003d08: f000 fc0a bl 8004520 <TIM_ETR_SetConfig>
- tmpsmcr = htim->Instance->SMCR;
- 8003d0c: 687b ldr r3, [r7, #4]
- 8003d0e: 681b ldr r3, [r3, #0]
- 8003d10: 689b ldr r3, [r3, #8]
- 8003d12: 60fb str r3, [r7, #12]
- tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
- 8003d14: 68fb ldr r3, [r7, #12]
- 8003d16: f043 0377 orr.w r3, r3, #119 ; 0x77
- 8003d1a: 60fb str r3, [r7, #12]
- htim->Instance->SMCR = tmpsmcr;
- 8003d1c: 687b ldr r3, [r7, #4]
- 8003d1e: 681b ldr r3, [r3, #0]
- 8003d20: 68fa ldr r2, [r7, #12]
- 8003d22: 609a str r2, [r3, #8]
- break;
- 8003d24: e04c b.n 8003dc0 <HAL_TIM_ConfigClockSource+0x154>
- TIM_ETR_SetConfig(htim->Instance,
- 8003d26: 687b ldr r3, [r7, #4]
- 8003d28: 6818 ldr r0, [r3, #0]
- 8003d2a: 683b ldr r3, [r7, #0]
- 8003d2c: 6899 ldr r1, [r3, #8]
- 8003d2e: 683b ldr r3, [r7, #0]
- 8003d30: 685a ldr r2, [r3, #4]
- 8003d32: 683b ldr r3, [r7, #0]
- 8003d34: 68db ldr r3, [r3, #12]
- 8003d36: f000 fbf3 bl 8004520 <TIM_ETR_SetConfig>
- htim->Instance->SMCR |= TIM_SMCR_ECE;
- 8003d3a: 687b ldr r3, [r7, #4]
- 8003d3c: 681b ldr r3, [r3, #0]
- 8003d3e: 689a ldr r2, [r3, #8]
- 8003d40: 687b ldr r3, [r7, #4]
- 8003d42: 681b ldr r3, [r3, #0]
- 8003d44: f442 4280 orr.w r2, r2, #16384 ; 0x4000
- 8003d48: 609a str r2, [r3, #8]
- break;
- 8003d4a: e039 b.n 8003dc0 <HAL_TIM_ConfigClockSource+0x154>
- TIM_TI1_ConfigInputStage(htim->Instance,
- 8003d4c: 687b ldr r3, [r7, #4]
- 8003d4e: 6818 ldr r0, [r3, #0]
- 8003d50: 683b ldr r3, [r7, #0]
- 8003d52: 6859 ldr r1, [r3, #4]
- 8003d54: 683b ldr r3, [r7, #0]
- 8003d56: 68db ldr r3, [r3, #12]
- 8003d58: 461a mov r2, r3
- 8003d5a: f000 fb67 bl 800442c <TIM_TI1_ConfigInputStage>
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
- 8003d5e: 687b ldr r3, [r7, #4]
- 8003d60: 681b ldr r3, [r3, #0]
- 8003d62: 2150 movs r1, #80 ; 0x50
- 8003d64: 4618 mov r0, r3
- 8003d66: f000 fbc0 bl 80044ea <TIM_ITRx_SetConfig>
- break;
- 8003d6a: e029 b.n 8003dc0 <HAL_TIM_ConfigClockSource+0x154>
- TIM_TI2_ConfigInputStage(htim->Instance,
- 8003d6c: 687b ldr r3, [r7, #4]
- 8003d6e: 6818 ldr r0, [r3, #0]
- 8003d70: 683b ldr r3, [r7, #0]
- 8003d72: 6859 ldr r1, [r3, #4]
- 8003d74: 683b ldr r3, [r7, #0]
- 8003d76: 68db ldr r3, [r3, #12]
- 8003d78: 461a mov r2, r3
- 8003d7a: f000 fb86 bl 800448a <TIM_TI2_ConfigInputStage>
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
- 8003d7e: 687b ldr r3, [r7, #4]
- 8003d80: 681b ldr r3, [r3, #0]
- 8003d82: 2160 movs r1, #96 ; 0x60
- 8003d84: 4618 mov r0, r3
- 8003d86: f000 fbb0 bl 80044ea <TIM_ITRx_SetConfig>
- break;
- 8003d8a: e019 b.n 8003dc0 <HAL_TIM_ConfigClockSource+0x154>
- TIM_TI1_ConfigInputStage(htim->Instance,
- 8003d8c: 687b ldr r3, [r7, #4]
- 8003d8e: 6818 ldr r0, [r3, #0]
- 8003d90: 683b ldr r3, [r7, #0]
- 8003d92: 6859 ldr r1, [r3, #4]
- 8003d94: 683b ldr r3, [r7, #0]
- 8003d96: 68db ldr r3, [r3, #12]
- 8003d98: 461a mov r2, r3
- 8003d9a: f000 fb47 bl 800442c <TIM_TI1_ConfigInputStage>
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
- 8003d9e: 687b ldr r3, [r7, #4]
- 8003da0: 681b ldr r3, [r3, #0]
- 8003da2: 2140 movs r1, #64 ; 0x40
- 8003da4: 4618 mov r0, r3
- 8003da6: f000 fba0 bl 80044ea <TIM_ITRx_SetConfig>
- break;
- 8003daa: e009 b.n 8003dc0 <HAL_TIM_ConfigClockSource+0x154>
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- 8003dac: 687b ldr r3, [r7, #4]
- 8003dae: 681a ldr r2, [r3, #0]
- 8003db0: 683b ldr r3, [r7, #0]
- 8003db2: 681b ldr r3, [r3, #0]
- 8003db4: 4619 mov r1, r3
- 8003db6: 4610 mov r0, r2
- 8003db8: f000 fb97 bl 80044ea <TIM_ITRx_SetConfig>
- break;
- 8003dbc: e000 b.n 8003dc0 <HAL_TIM_ConfigClockSource+0x154>
- break;
- 8003dbe: bf00 nop
- }
- htim->State = HAL_TIM_STATE_READY;
- 8003dc0: 687b ldr r3, [r7, #4]
- 8003dc2: 2201 movs r2, #1
- 8003dc4: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- __HAL_UNLOCK(htim);
- 8003dc8: 687b ldr r3, [r7, #4]
- 8003dca: 2200 movs r2, #0
- 8003dcc: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- return HAL_OK;
- 8003dd0: 2300 movs r3, #0
-}
- 8003dd2: 4618 mov r0, r3
- 8003dd4: 3710 adds r7, #16
- 8003dd6: 46bd mov sp, r7
- 8003dd8: bd80 pop {r7, pc}
- 8003dda: bf00 nop
- 8003ddc: fffeff88 .word 0xfffeff88
-
-08003de0 <HAL_TIM_OC_DelayElapsedCallback>:
- * @brief Output Compare callback in non-blocking mode
- * @param htim TIM OC handle
- * @retval None
- */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
-{
- 8003de0: b480 push {r7}
- 8003de2: b083 sub sp, #12
- 8003de4: af00 add r7, sp, #0
- 8003de6: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
- */
-}
- 8003de8: bf00 nop
- 8003dea: 370c adds r7, #12
- 8003dec: 46bd mov sp, r7
- 8003dee: f85d 7b04 ldr.w r7, [sp], #4
- 8003df2: 4770 bx lr
-
-08003df4 <HAL_TIM_IC_CaptureCallback>:
- * @brief Input Capture callback in non-blocking mode
- * @param htim TIM IC handle
- * @retval None
- */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
-{
- 8003df4: b480 push {r7}
- 8003df6: b083 sub sp, #12
- 8003df8: af00 add r7, sp, #0
- 8003dfa: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_IC_CaptureCallback could be implemented in the user file
- */
-}
- 8003dfc: bf00 nop
- 8003dfe: 370c adds r7, #12
- 8003e00: 46bd mov sp, r7
- 8003e02: f85d 7b04 ldr.w r7, [sp], #4
- 8003e06: 4770 bx lr
-
-08003e08 <HAL_TIM_PWM_PulseFinishedCallback>:
- * @brief PWM Pulse finished callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
-{
- 8003e08: b480 push {r7}
- 8003e0a: b083 sub sp, #12
- 8003e0c: af00 add r7, sp, #0
- 8003e0e: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
- */
-}
- 8003e10: bf00 nop
- 8003e12: 370c adds r7, #12
- 8003e14: 46bd mov sp, r7
- 8003e16: f85d 7b04 ldr.w r7, [sp], #4
- 8003e1a: 4770 bx lr
-
-08003e1c <HAL_TIM_TriggerCallback>:
- * @brief Hall Trigger detection callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
-{
- 8003e1c: b480 push {r7}
- 8003e1e: b083 sub sp, #12
- 8003e20: af00 add r7, sp, #0
- 8003e22: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_TriggerCallback could be implemented in the user file
- */
-}
- 8003e24: bf00 nop
- 8003e26: 370c adds r7, #12
- 8003e28: 46bd mov sp, r7
- 8003e2a: f85d 7b04 ldr.w r7, [sp], #4
- 8003e2e: 4770 bx lr
-
-08003e30 <TIM_Base_SetConfig>:
- * @param TIMx TIM peripheral
- * @param Structure TIM Base configuration structure
- * @retval None
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
-{
- 8003e30: b480 push {r7}
- 8003e32: b085 sub sp, #20
- 8003e34: af00 add r7, sp, #0
- 8003e36: 6078 str r0, [r7, #4]
- 8003e38: 6039 str r1, [r7, #0]
- uint32_t tmpcr1;
- tmpcr1 = TIMx->CR1;
- 8003e3a: 687b ldr r3, [r7, #4]
- 8003e3c: 681b ldr r3, [r3, #0]
- 8003e3e: 60fb str r3, [r7, #12]
-
- /* Set TIM Time Base Unit parameters ---------------------------------------*/
- if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- 8003e40: 687b ldr r3, [r7, #4]
- 8003e42: 4a40 ldr r2, [pc, #256] ; (8003f44 <TIM_Base_SetConfig+0x114>)
- 8003e44: 4293 cmp r3, r2
- 8003e46: d013 beq.n 8003e70 <TIM_Base_SetConfig+0x40>
- 8003e48: 687b ldr r3, [r7, #4]
- 8003e4a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 8003e4e: d00f beq.n 8003e70 <TIM_Base_SetConfig+0x40>
- 8003e50: 687b ldr r3, [r7, #4]
- 8003e52: 4a3d ldr r2, [pc, #244] ; (8003f48 <TIM_Base_SetConfig+0x118>)
- 8003e54: 4293 cmp r3, r2
- 8003e56: d00b beq.n 8003e70 <TIM_Base_SetConfig+0x40>
- 8003e58: 687b ldr r3, [r7, #4]
- 8003e5a: 4a3c ldr r2, [pc, #240] ; (8003f4c <TIM_Base_SetConfig+0x11c>)
- 8003e5c: 4293 cmp r3, r2
- 8003e5e: d007 beq.n 8003e70 <TIM_Base_SetConfig+0x40>
- 8003e60: 687b ldr r3, [r7, #4]
- 8003e62: 4a3b ldr r2, [pc, #236] ; (8003f50 <TIM_Base_SetConfig+0x120>)
- 8003e64: 4293 cmp r3, r2
- 8003e66: d003 beq.n 8003e70 <TIM_Base_SetConfig+0x40>
- 8003e68: 687b ldr r3, [r7, #4]
- 8003e6a: 4a3a ldr r2, [pc, #232] ; (8003f54 <TIM_Base_SetConfig+0x124>)
- 8003e6c: 4293 cmp r3, r2
- 8003e6e: d108 bne.n 8003e82 <TIM_Base_SetConfig+0x52>
- {
- /* Select the Counter Mode */
- tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
- 8003e70: 68fb ldr r3, [r7, #12]
- 8003e72: f023 0370 bic.w r3, r3, #112 ; 0x70
- 8003e76: 60fb str r3, [r7, #12]
- tmpcr1 |= Structure->CounterMode;
- 8003e78: 683b ldr r3, [r7, #0]
- 8003e7a: 685b ldr r3, [r3, #4]
- 8003e7c: 68fa ldr r2, [r7, #12]
- 8003e7e: 4313 orrs r3, r2
- 8003e80: 60fb str r3, [r7, #12]
- }
-
- if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- 8003e82: 687b ldr r3, [r7, #4]
- 8003e84: 4a2f ldr r2, [pc, #188] ; (8003f44 <TIM_Base_SetConfig+0x114>)
- 8003e86: 4293 cmp r3, r2
- 8003e88: d02b beq.n 8003ee2 <TIM_Base_SetConfig+0xb2>
- 8003e8a: 687b ldr r3, [r7, #4]
- 8003e8c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 8003e90: d027 beq.n 8003ee2 <TIM_Base_SetConfig+0xb2>
- 8003e92: 687b ldr r3, [r7, #4]
- 8003e94: 4a2c ldr r2, [pc, #176] ; (8003f48 <TIM_Base_SetConfig+0x118>)
- 8003e96: 4293 cmp r3, r2
- 8003e98: d023 beq.n 8003ee2 <TIM_Base_SetConfig+0xb2>
- 8003e9a: 687b ldr r3, [r7, #4]
- 8003e9c: 4a2b ldr r2, [pc, #172] ; (8003f4c <TIM_Base_SetConfig+0x11c>)
- 8003e9e: 4293 cmp r3, r2
- 8003ea0: d01f beq.n 8003ee2 <TIM_Base_SetConfig+0xb2>
- 8003ea2: 687b ldr r3, [r7, #4]
- 8003ea4: 4a2a ldr r2, [pc, #168] ; (8003f50 <TIM_Base_SetConfig+0x120>)
- 8003ea6: 4293 cmp r3, r2
- 8003ea8: d01b beq.n 8003ee2 <TIM_Base_SetConfig+0xb2>
- 8003eaa: 687b ldr r3, [r7, #4]
- 8003eac: 4a29 ldr r2, [pc, #164] ; (8003f54 <TIM_Base_SetConfig+0x124>)
- 8003eae: 4293 cmp r3, r2
- 8003eb0: d017 beq.n 8003ee2 <TIM_Base_SetConfig+0xb2>
- 8003eb2: 687b ldr r3, [r7, #4]
- 8003eb4: 4a28 ldr r2, [pc, #160] ; (8003f58 <TIM_Base_SetConfig+0x128>)
- 8003eb6: 4293 cmp r3, r2
- 8003eb8: d013 beq.n 8003ee2 <TIM_Base_SetConfig+0xb2>
- 8003eba: 687b ldr r3, [r7, #4]
- 8003ebc: 4a27 ldr r2, [pc, #156] ; (8003f5c <TIM_Base_SetConfig+0x12c>)
- 8003ebe: 4293 cmp r3, r2
- 8003ec0: d00f beq.n 8003ee2 <TIM_Base_SetConfig+0xb2>
- 8003ec2: 687b ldr r3, [r7, #4]
- 8003ec4: 4a26 ldr r2, [pc, #152] ; (8003f60 <TIM_Base_SetConfig+0x130>)
- 8003ec6: 4293 cmp r3, r2
- 8003ec8: d00b beq.n 8003ee2 <TIM_Base_SetConfig+0xb2>
- 8003eca: 687b ldr r3, [r7, #4]
- 8003ecc: 4a25 ldr r2, [pc, #148] ; (8003f64 <TIM_Base_SetConfig+0x134>)
- 8003ece: 4293 cmp r3, r2
- 8003ed0: d007 beq.n 8003ee2 <TIM_Base_SetConfig+0xb2>
- 8003ed2: 687b ldr r3, [r7, #4]
- 8003ed4: 4a24 ldr r2, [pc, #144] ; (8003f68 <TIM_Base_SetConfig+0x138>)
- 8003ed6: 4293 cmp r3, r2
- 8003ed8: d003 beq.n 8003ee2 <TIM_Base_SetConfig+0xb2>
- 8003eda: 687b ldr r3, [r7, #4]
- 8003edc: 4a23 ldr r2, [pc, #140] ; (8003f6c <TIM_Base_SetConfig+0x13c>)
- 8003ede: 4293 cmp r3, r2
- 8003ee0: d108 bne.n 8003ef4 <TIM_Base_SetConfig+0xc4>
- {
- /* Set the clock division */
- tmpcr1 &= ~TIM_CR1_CKD;
- 8003ee2: 68fb ldr r3, [r7, #12]
- 8003ee4: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8003ee8: 60fb str r3, [r7, #12]
- tmpcr1 |= (uint32_t)Structure->ClockDivision;
- 8003eea: 683b ldr r3, [r7, #0]
- 8003eec: 68db ldr r3, [r3, #12]
- 8003eee: 68fa ldr r2, [r7, #12]
- 8003ef0: 4313 orrs r3, r2
- 8003ef2: 60fb str r3, [r7, #12]
- }
-
- /* Set the auto-reload preload */
- MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
- 8003ef4: 68fb ldr r3, [r7, #12]
- 8003ef6: f023 0280 bic.w r2, r3, #128 ; 0x80
- 8003efa: 683b ldr r3, [r7, #0]
- 8003efc: 695b ldr r3, [r3, #20]
- 8003efe: 4313 orrs r3, r2
- 8003f00: 60fb str r3, [r7, #12]
-
- TIMx->CR1 = tmpcr1;
- 8003f02: 687b ldr r3, [r7, #4]
- 8003f04: 68fa ldr r2, [r7, #12]
- 8003f06: 601a str r2, [r3, #0]
-
- /* Set the Autoreload value */
- TIMx->ARR = (uint32_t)Structure->Period ;
- 8003f08: 683b ldr r3, [r7, #0]
- 8003f0a: 689a ldr r2, [r3, #8]
- 8003f0c: 687b ldr r3, [r7, #4]
- 8003f0e: 62da str r2, [r3, #44] ; 0x2c
-
- /* Set the Prescaler value */
- TIMx->PSC = Structure->Prescaler;
- 8003f10: 683b ldr r3, [r7, #0]
- 8003f12: 681a ldr r2, [r3, #0]
- 8003f14: 687b ldr r3, [r7, #4]
- 8003f16: 629a str r2, [r3, #40] ; 0x28
-
- if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
- 8003f18: 687b ldr r3, [r7, #4]
- 8003f1a: 4a0a ldr r2, [pc, #40] ; (8003f44 <TIM_Base_SetConfig+0x114>)
- 8003f1c: 4293 cmp r3, r2
- 8003f1e: d003 beq.n 8003f28 <TIM_Base_SetConfig+0xf8>
- 8003f20: 687b ldr r3, [r7, #4]
- 8003f22: 4a0c ldr r2, [pc, #48] ; (8003f54 <TIM_Base_SetConfig+0x124>)
- 8003f24: 4293 cmp r3, r2
- 8003f26: d103 bne.n 8003f30 <TIM_Base_SetConfig+0x100>
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = Structure->RepetitionCounter;
- 8003f28: 683b ldr r3, [r7, #0]
- 8003f2a: 691a ldr r2, [r3, #16]
- 8003f2c: 687b ldr r3, [r7, #4]
- 8003f2e: 631a str r2, [r3, #48] ; 0x30
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter (only for advanced timer) value immediately */
- TIMx->EGR = TIM_EGR_UG;
- 8003f30: 687b ldr r3, [r7, #4]
- 8003f32: 2201 movs r2, #1
- 8003f34: 615a str r2, [r3, #20]
-}
- 8003f36: bf00 nop
- 8003f38: 3714 adds r7, #20
- 8003f3a: 46bd mov sp, r7
- 8003f3c: f85d 7b04 ldr.w r7, [sp], #4
- 8003f40: 4770 bx lr
- 8003f42: bf00 nop
- 8003f44: 40010000 .word 0x40010000
- 8003f48: 40000400 .word 0x40000400
- 8003f4c: 40000800 .word 0x40000800
- 8003f50: 40000c00 .word 0x40000c00
- 8003f54: 40010400 .word 0x40010400
- 8003f58: 40014000 .word 0x40014000
- 8003f5c: 40014400 .word 0x40014400
- 8003f60: 40014800 .word 0x40014800
- 8003f64: 40001800 .word 0x40001800
- 8003f68: 40001c00 .word 0x40001c00
- 8003f6c: 40002000 .word 0x40002000
-
-08003f70 <TIM_OC1_SetConfig>:
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- 8003f70: b480 push {r7}
- 8003f72: b087 sub sp, #28
- 8003f74: af00 add r7, sp, #0
- 8003f76: 6078 str r0, [r7, #4]
- 8003f78: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
- 8003f7a: 687b ldr r3, [r7, #4]
- 8003f7c: 6a1b ldr r3, [r3, #32]
- 8003f7e: f023 0201 bic.w r2, r3, #1
- 8003f82: 687b ldr r3, [r7, #4]
- 8003f84: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 8003f86: 687b ldr r3, [r7, #4]
- 8003f88: 6a1b ldr r3, [r3, #32]
- 8003f8a: 617b str r3, [r7, #20]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 8003f8c: 687b ldr r3, [r7, #4]
- 8003f8e: 685b ldr r3, [r3, #4]
- 8003f90: 613b str r3, [r7, #16]
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
- 8003f92: 687b ldr r3, [r7, #4]
- 8003f94: 699b ldr r3, [r3, #24]
- 8003f96: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~TIM_CCMR1_OC1M;
- 8003f98: 68fa ldr r2, [r7, #12]
- 8003f9a: 4b2b ldr r3, [pc, #172] ; (8004048 <TIM_OC1_SetConfig+0xd8>)
- 8003f9c: 4013 ands r3, r2
- 8003f9e: 60fb str r3, [r7, #12]
- tmpccmrx &= ~TIM_CCMR1_CC1S;
- 8003fa0: 68fb ldr r3, [r7, #12]
- 8003fa2: f023 0303 bic.w r3, r3, #3
- 8003fa6: 60fb str r3, [r7, #12]
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
- 8003fa8: 683b ldr r3, [r7, #0]
- 8003faa: 681b ldr r3, [r3, #0]
- 8003fac: 68fa ldr r2, [r7, #12]
- 8003fae: 4313 orrs r3, r2
- 8003fb0: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC1P;
- 8003fb2: 697b ldr r3, [r7, #20]
- 8003fb4: f023 0302 bic.w r3, r3, #2
- 8003fb8: 617b str r3, [r7, #20]
- /* Set the Output Compare Polarity */
- tmpccer |= OC_Config->OCPolarity;
- 8003fba: 683b ldr r3, [r7, #0]
- 8003fbc: 689b ldr r3, [r3, #8]
- 8003fbe: 697a ldr r2, [r7, #20]
- 8003fc0: 4313 orrs r3, r2
- 8003fc2: 617b str r3, [r7, #20]
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
- 8003fc4: 687b ldr r3, [r7, #4]
- 8003fc6: 4a21 ldr r2, [pc, #132] ; (800404c <TIM_OC1_SetConfig+0xdc>)
- 8003fc8: 4293 cmp r3, r2
- 8003fca: d003 beq.n 8003fd4 <TIM_OC1_SetConfig+0x64>
- 8003fcc: 687b ldr r3, [r7, #4]
- 8003fce: 4a20 ldr r2, [pc, #128] ; (8004050 <TIM_OC1_SetConfig+0xe0>)
- 8003fd0: 4293 cmp r3, r2
- 8003fd2: d10c bne.n 8003fee <TIM_OC1_SetConfig+0x7e>
- {
- /* Check parameters */
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC1NP;
- 8003fd4: 697b ldr r3, [r7, #20]
- 8003fd6: f023 0308 bic.w r3, r3, #8
- 8003fda: 617b str r3, [r7, #20]
- /* Set the Output N Polarity */
- tmpccer |= OC_Config->OCNPolarity;
- 8003fdc: 683b ldr r3, [r7, #0]
- 8003fde: 68db ldr r3, [r3, #12]
- 8003fe0: 697a ldr r2, [r7, #20]
- 8003fe2: 4313 orrs r3, r2
- 8003fe4: 617b str r3, [r7, #20]
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC1NE;
- 8003fe6: 697b ldr r3, [r7, #20]
- 8003fe8: f023 0304 bic.w r3, r3, #4
- 8003fec: 617b str r3, [r7, #20]
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8003fee: 687b ldr r3, [r7, #4]
- 8003ff0: 4a16 ldr r2, [pc, #88] ; (800404c <TIM_OC1_SetConfig+0xdc>)
- 8003ff2: 4293 cmp r3, r2
- 8003ff4: d003 beq.n 8003ffe <TIM_OC1_SetConfig+0x8e>
- 8003ff6: 687b ldr r3, [r7, #4]
- 8003ff8: 4a15 ldr r2, [pc, #84] ; (8004050 <TIM_OC1_SetConfig+0xe0>)
- 8003ffa: 4293 cmp r3, r2
- 8003ffc: d111 bne.n 8004022 <TIM_OC1_SetConfig+0xb2>
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS1;
- 8003ffe: 693b ldr r3, [r7, #16]
- 8004000: f423 7380 bic.w r3, r3, #256 ; 0x100
- 8004004: 613b str r3, [r7, #16]
- tmpcr2 &= ~TIM_CR2_OIS1N;
- 8004006: 693b ldr r3, [r7, #16]
- 8004008: f423 7300 bic.w r3, r3, #512 ; 0x200
- 800400c: 613b str r3, [r7, #16]
- /* Set the Output Idle state */
- tmpcr2 |= OC_Config->OCIdleState;
- 800400e: 683b ldr r3, [r7, #0]
- 8004010: 695b ldr r3, [r3, #20]
- 8004012: 693a ldr r2, [r7, #16]
- 8004014: 4313 orrs r3, r2
- 8004016: 613b str r3, [r7, #16]
- /* Set the Output N Idle state */
- tmpcr2 |= OC_Config->OCNIdleState;
- 8004018: 683b ldr r3, [r7, #0]
- 800401a: 699b ldr r3, [r3, #24]
- 800401c: 693a ldr r2, [r7, #16]
- 800401e: 4313 orrs r3, r2
- 8004020: 613b str r3, [r7, #16]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 8004022: 687b ldr r3, [r7, #4]
- 8004024: 693a ldr r2, [r7, #16]
- 8004026: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
- 8004028: 687b ldr r3, [r7, #4]
- 800402a: 68fa ldr r2, [r7, #12]
- 800402c: 619a str r2, [r3, #24]
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = OC_Config->Pulse;
- 800402e: 683b ldr r3, [r7, #0]
- 8004030: 685a ldr r2, [r3, #4]
- 8004032: 687b ldr r3, [r7, #4]
- 8004034: 635a str r2, [r3, #52] ; 0x34
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 8004036: 687b ldr r3, [r7, #4]
- 8004038: 697a ldr r2, [r7, #20]
- 800403a: 621a str r2, [r3, #32]
-}
- 800403c: bf00 nop
- 800403e: 371c adds r7, #28
- 8004040: 46bd mov sp, r7
- 8004042: f85d 7b04 ldr.w r7, [sp], #4
- 8004046: 4770 bx lr
- 8004048: fffeff8f .word 0xfffeff8f
- 800404c: 40010000 .word 0x40010000
- 8004050: 40010400 .word 0x40010400
-
-08004054 <TIM_OC2_SetConfig>:
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- 8004054: b480 push {r7}
- 8004056: b087 sub sp, #28
- 8004058: af00 add r7, sp, #0
- 800405a: 6078 str r0, [r7, #4]
- 800405c: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- 800405e: 687b ldr r3, [r7, #4]
- 8004060: 6a1b ldr r3, [r3, #32]
- 8004062: f023 0210 bic.w r2, r3, #16
- 8004066: 687b ldr r3, [r7, #4]
- 8004068: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 800406a: 687b ldr r3, [r7, #4]
- 800406c: 6a1b ldr r3, [r3, #32]
- 800406e: 617b str r3, [r7, #20]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 8004070: 687b ldr r3, [r7, #4]
- 8004072: 685b ldr r3, [r3, #4]
- 8004074: 613b str r3, [r7, #16]
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
- 8004076: 687b ldr r3, [r7, #4]
- 8004078: 699b ldr r3, [r3, #24]
- 800407a: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR1_OC2M;
- 800407c: 68fa ldr r2, [r7, #12]
- 800407e: 4b2e ldr r3, [pc, #184] ; (8004138 <TIM_OC2_SetConfig+0xe4>)
- 8004080: 4013 ands r3, r2
- 8004082: 60fb str r3, [r7, #12]
- tmpccmrx &= ~TIM_CCMR1_CC2S;
- 8004084: 68fb ldr r3, [r7, #12]
- 8004086: f423 7340 bic.w r3, r3, #768 ; 0x300
- 800408a: 60fb str r3, [r7, #12]
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
- 800408c: 683b ldr r3, [r7, #0]
- 800408e: 681b ldr r3, [r3, #0]
- 8004090: 021b lsls r3, r3, #8
- 8004092: 68fa ldr r2, [r7, #12]
- 8004094: 4313 orrs r3, r2
- 8004096: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC2P;
- 8004098: 697b ldr r3, [r7, #20]
- 800409a: f023 0320 bic.w r3, r3, #32
- 800409e: 617b str r3, [r7, #20]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 4U);
- 80040a0: 683b ldr r3, [r7, #0]
- 80040a2: 689b ldr r3, [r3, #8]
- 80040a4: 011b lsls r3, r3, #4
- 80040a6: 697a ldr r2, [r7, #20]
- 80040a8: 4313 orrs r3, r2
- 80040aa: 617b str r3, [r7, #20]
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
- 80040ac: 687b ldr r3, [r7, #4]
- 80040ae: 4a23 ldr r2, [pc, #140] ; (800413c <TIM_OC2_SetConfig+0xe8>)
- 80040b0: 4293 cmp r3, r2
- 80040b2: d003 beq.n 80040bc <TIM_OC2_SetConfig+0x68>
- 80040b4: 687b ldr r3, [r7, #4]
- 80040b6: 4a22 ldr r2, [pc, #136] ; (8004140 <TIM_OC2_SetConfig+0xec>)
- 80040b8: 4293 cmp r3, r2
- 80040ba: d10d bne.n 80040d8 <TIM_OC2_SetConfig+0x84>
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC2NP;
- 80040bc: 697b ldr r3, [r7, #20]
- 80040be: f023 0380 bic.w r3, r3, #128 ; 0x80
- 80040c2: 617b str r3, [r7, #20]
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 4U);
- 80040c4: 683b ldr r3, [r7, #0]
- 80040c6: 68db ldr r3, [r3, #12]
- 80040c8: 011b lsls r3, r3, #4
- 80040ca: 697a ldr r2, [r7, #20]
- 80040cc: 4313 orrs r3, r2
- 80040ce: 617b str r3, [r7, #20]
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC2NE;
- 80040d0: 697b ldr r3, [r7, #20]
- 80040d2: f023 0340 bic.w r3, r3, #64 ; 0x40
- 80040d6: 617b str r3, [r7, #20]
-
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 80040d8: 687b ldr r3, [r7, #4]
- 80040da: 4a18 ldr r2, [pc, #96] ; (800413c <TIM_OC2_SetConfig+0xe8>)
- 80040dc: 4293 cmp r3, r2
- 80040de: d003 beq.n 80040e8 <TIM_OC2_SetConfig+0x94>
- 80040e0: 687b ldr r3, [r7, #4]
- 80040e2: 4a17 ldr r2, [pc, #92] ; (8004140 <TIM_OC2_SetConfig+0xec>)
- 80040e4: 4293 cmp r3, r2
- 80040e6: d113 bne.n 8004110 <TIM_OC2_SetConfig+0xbc>
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS2;
- 80040e8: 693b ldr r3, [r7, #16]
- 80040ea: f423 6380 bic.w r3, r3, #1024 ; 0x400
- 80040ee: 613b str r3, [r7, #16]
- tmpcr2 &= ~TIM_CR2_OIS2N;
- 80040f0: 693b ldr r3, [r7, #16]
- 80040f2: f423 6300 bic.w r3, r3, #2048 ; 0x800
- 80040f6: 613b str r3, [r7, #16]
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 2U);
- 80040f8: 683b ldr r3, [r7, #0]
- 80040fa: 695b ldr r3, [r3, #20]
- 80040fc: 009b lsls r3, r3, #2
- 80040fe: 693a ldr r2, [r7, #16]
- 8004100: 4313 orrs r3, r2
- 8004102: 613b str r3, [r7, #16]
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 2U);
- 8004104: 683b ldr r3, [r7, #0]
- 8004106: 699b ldr r3, [r3, #24]
- 8004108: 009b lsls r3, r3, #2
- 800410a: 693a ldr r2, [r7, #16]
- 800410c: 4313 orrs r3, r2
- 800410e: 613b str r3, [r7, #16]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 8004110: 687b ldr r3, [r7, #4]
- 8004112: 693a ldr r2, [r7, #16]
- 8004114: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
- 8004116: 687b ldr r3, [r7, #4]
- 8004118: 68fa ldr r2, [r7, #12]
- 800411a: 619a str r2, [r3, #24]
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = OC_Config->Pulse;
- 800411c: 683b ldr r3, [r7, #0]
- 800411e: 685a ldr r2, [r3, #4]
- 8004120: 687b ldr r3, [r7, #4]
- 8004122: 639a str r2, [r3, #56] ; 0x38
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 8004124: 687b ldr r3, [r7, #4]
- 8004126: 697a ldr r2, [r7, #20]
- 8004128: 621a str r2, [r3, #32]
-}
- 800412a: bf00 nop
- 800412c: 371c adds r7, #28
- 800412e: 46bd mov sp, r7
- 8004130: f85d 7b04 ldr.w r7, [sp], #4
- 8004134: 4770 bx lr
- 8004136: bf00 nop
- 8004138: feff8fff .word 0xfeff8fff
- 800413c: 40010000 .word 0x40010000
- 8004140: 40010400 .word 0x40010400
-
-08004144 <TIM_OC3_SetConfig>:
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- 8004144: b480 push {r7}
- 8004146: b087 sub sp, #28
- 8004148: af00 add r7, sp, #0
- 800414a: 6078 str r0, [r7, #4]
- 800414c: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 3: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC3E;
- 800414e: 687b ldr r3, [r7, #4]
- 8004150: 6a1b ldr r3, [r3, #32]
- 8004152: f423 7280 bic.w r2, r3, #256 ; 0x100
- 8004156: 687b ldr r3, [r7, #4]
- 8004158: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 800415a: 687b ldr r3, [r7, #4]
- 800415c: 6a1b ldr r3, [r3, #32]
- 800415e: 617b str r3, [r7, #20]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 8004160: 687b ldr r3, [r7, #4]
- 8004162: 685b ldr r3, [r3, #4]
- 8004164: 613b str r3, [r7, #16]
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
- 8004166: 687b ldr r3, [r7, #4]
- 8004168: 69db ldr r3, [r3, #28]
- 800416a: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC3M;
- 800416c: 68fa ldr r2, [r7, #12]
- 800416e: 4b2d ldr r3, [pc, #180] ; (8004224 <TIM_OC3_SetConfig+0xe0>)
- 8004170: 4013 ands r3, r2
- 8004172: 60fb str r3, [r7, #12]
- tmpccmrx &= ~TIM_CCMR2_CC3S;
- 8004174: 68fb ldr r3, [r7, #12]
- 8004176: f023 0303 bic.w r3, r3, #3
- 800417a: 60fb str r3, [r7, #12]
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
- 800417c: 683b ldr r3, [r7, #0]
- 800417e: 681b ldr r3, [r3, #0]
- 8004180: 68fa ldr r2, [r7, #12]
- 8004182: 4313 orrs r3, r2
- 8004184: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC3P;
- 8004186: 697b ldr r3, [r7, #20]
- 8004188: f423 7300 bic.w r3, r3, #512 ; 0x200
- 800418c: 617b str r3, [r7, #20]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 8U);
- 800418e: 683b ldr r3, [r7, #0]
- 8004190: 689b ldr r3, [r3, #8]
- 8004192: 021b lsls r3, r3, #8
- 8004194: 697a ldr r2, [r7, #20]
- 8004196: 4313 orrs r3, r2
- 8004198: 617b str r3, [r7, #20]
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
- 800419a: 687b ldr r3, [r7, #4]
- 800419c: 4a22 ldr r2, [pc, #136] ; (8004228 <TIM_OC3_SetConfig+0xe4>)
- 800419e: 4293 cmp r3, r2
- 80041a0: d003 beq.n 80041aa <TIM_OC3_SetConfig+0x66>
- 80041a2: 687b ldr r3, [r7, #4]
- 80041a4: 4a21 ldr r2, [pc, #132] ; (800422c <TIM_OC3_SetConfig+0xe8>)
- 80041a6: 4293 cmp r3, r2
- 80041a8: d10d bne.n 80041c6 <TIM_OC3_SetConfig+0x82>
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC3NP;
- 80041aa: 697b ldr r3, [r7, #20]
- 80041ac: f423 6300 bic.w r3, r3, #2048 ; 0x800
- 80041b0: 617b str r3, [r7, #20]
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 8U);
- 80041b2: 683b ldr r3, [r7, #0]
- 80041b4: 68db ldr r3, [r3, #12]
- 80041b6: 021b lsls r3, r3, #8
- 80041b8: 697a ldr r2, [r7, #20]
- 80041ba: 4313 orrs r3, r2
- 80041bc: 617b str r3, [r7, #20]
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC3NE;
- 80041be: 697b ldr r3, [r7, #20]
- 80041c0: f423 6380 bic.w r3, r3, #1024 ; 0x400
- 80041c4: 617b str r3, [r7, #20]
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 80041c6: 687b ldr r3, [r7, #4]
- 80041c8: 4a17 ldr r2, [pc, #92] ; (8004228 <TIM_OC3_SetConfig+0xe4>)
- 80041ca: 4293 cmp r3, r2
- 80041cc: d003 beq.n 80041d6 <TIM_OC3_SetConfig+0x92>
- 80041ce: 687b ldr r3, [r7, #4]
- 80041d0: 4a16 ldr r2, [pc, #88] ; (800422c <TIM_OC3_SetConfig+0xe8>)
- 80041d2: 4293 cmp r3, r2
- 80041d4: d113 bne.n 80041fe <TIM_OC3_SetConfig+0xba>
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS3;
- 80041d6: 693b ldr r3, [r7, #16]
- 80041d8: f423 5380 bic.w r3, r3, #4096 ; 0x1000
- 80041dc: 613b str r3, [r7, #16]
- tmpcr2 &= ~TIM_CR2_OIS3N;
- 80041de: 693b ldr r3, [r7, #16]
- 80041e0: f423 5300 bic.w r3, r3, #8192 ; 0x2000
- 80041e4: 613b str r3, [r7, #16]
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 4U);
- 80041e6: 683b ldr r3, [r7, #0]
- 80041e8: 695b ldr r3, [r3, #20]
- 80041ea: 011b lsls r3, r3, #4
- 80041ec: 693a ldr r2, [r7, #16]
- 80041ee: 4313 orrs r3, r2
- 80041f0: 613b str r3, [r7, #16]
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 4U);
- 80041f2: 683b ldr r3, [r7, #0]
- 80041f4: 699b ldr r3, [r3, #24]
- 80041f6: 011b lsls r3, r3, #4
- 80041f8: 693a ldr r2, [r7, #16]
- 80041fa: 4313 orrs r3, r2
- 80041fc: 613b str r3, [r7, #16]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 80041fe: 687b ldr r3, [r7, #4]
- 8004200: 693a ldr r2, [r7, #16]
- 8004202: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
- 8004204: 687b ldr r3, [r7, #4]
- 8004206: 68fa ldr r2, [r7, #12]
- 8004208: 61da str r2, [r3, #28]
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = OC_Config->Pulse;
- 800420a: 683b ldr r3, [r7, #0]
- 800420c: 685a ldr r2, [r3, #4]
- 800420e: 687b ldr r3, [r7, #4]
- 8004210: 63da str r2, [r3, #60] ; 0x3c
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 8004212: 687b ldr r3, [r7, #4]
- 8004214: 697a ldr r2, [r7, #20]
- 8004216: 621a str r2, [r3, #32]
-}
- 8004218: bf00 nop
- 800421a: 371c adds r7, #28
- 800421c: 46bd mov sp, r7
- 800421e: f85d 7b04 ldr.w r7, [sp], #4
- 8004222: 4770 bx lr
- 8004224: fffeff8f .word 0xfffeff8f
- 8004228: 40010000 .word 0x40010000
- 800422c: 40010400 .word 0x40010400
-
-08004230 <TIM_OC4_SetConfig>:
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- 8004230: b480 push {r7}
- 8004232: b087 sub sp, #28
- 8004234: af00 add r7, sp, #0
- 8004236: 6078 str r0, [r7, #4]
- 8004238: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= ~TIM_CCER_CC4E;
- 800423a: 687b ldr r3, [r7, #4]
- 800423c: 6a1b ldr r3, [r3, #32]
- 800423e: f423 5280 bic.w r2, r3, #4096 ; 0x1000
- 8004242: 687b ldr r3, [r7, #4]
- 8004244: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 8004246: 687b ldr r3, [r7, #4]
- 8004248: 6a1b ldr r3, [r3, #32]
- 800424a: 613b str r3, [r7, #16]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 800424c: 687b ldr r3, [r7, #4]
- 800424e: 685b ldr r3, [r3, #4]
- 8004250: 617b str r3, [r7, #20]
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
- 8004252: 687b ldr r3, [r7, #4]
- 8004254: 69db ldr r3, [r3, #28]
- 8004256: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC4M;
- 8004258: 68fa ldr r2, [r7, #12]
- 800425a: 4b1e ldr r3, [pc, #120] ; (80042d4 <TIM_OC4_SetConfig+0xa4>)
- 800425c: 4013 ands r3, r2
- 800425e: 60fb str r3, [r7, #12]
- tmpccmrx &= ~TIM_CCMR2_CC4S;
- 8004260: 68fb ldr r3, [r7, #12]
- 8004262: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8004266: 60fb str r3, [r7, #12]
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
- 8004268: 683b ldr r3, [r7, #0]
- 800426a: 681b ldr r3, [r3, #0]
- 800426c: 021b lsls r3, r3, #8
- 800426e: 68fa ldr r2, [r7, #12]
- 8004270: 4313 orrs r3, r2
- 8004272: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC4P;
- 8004274: 693b ldr r3, [r7, #16]
- 8004276: f423 5300 bic.w r3, r3, #8192 ; 0x2000
- 800427a: 613b str r3, [r7, #16]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 12U);
- 800427c: 683b ldr r3, [r7, #0]
- 800427e: 689b ldr r3, [r3, #8]
- 8004280: 031b lsls r3, r3, #12
- 8004282: 693a ldr r2, [r7, #16]
- 8004284: 4313 orrs r3, r2
- 8004286: 613b str r3, [r7, #16]
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8004288: 687b ldr r3, [r7, #4]
- 800428a: 4a13 ldr r2, [pc, #76] ; (80042d8 <TIM_OC4_SetConfig+0xa8>)
- 800428c: 4293 cmp r3, r2
- 800428e: d003 beq.n 8004298 <TIM_OC4_SetConfig+0x68>
- 8004290: 687b ldr r3, [r7, #4]
- 8004292: 4a12 ldr r2, [pc, #72] ; (80042dc <TIM_OC4_SetConfig+0xac>)
- 8004294: 4293 cmp r3, r2
- 8004296: d109 bne.n 80042ac <TIM_OC4_SetConfig+0x7c>
- {
- /* Check parameters */
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS4;
- 8004298: 697b ldr r3, [r7, #20]
- 800429a: f423 4380 bic.w r3, r3, #16384 ; 0x4000
- 800429e: 617b str r3, [r7, #20]
-
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 6U);
- 80042a0: 683b ldr r3, [r7, #0]
- 80042a2: 695b ldr r3, [r3, #20]
- 80042a4: 019b lsls r3, r3, #6
- 80042a6: 697a ldr r2, [r7, #20]
- 80042a8: 4313 orrs r3, r2
- 80042aa: 617b str r3, [r7, #20]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 80042ac: 687b ldr r3, [r7, #4]
- 80042ae: 697a ldr r2, [r7, #20]
- 80042b0: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
- 80042b2: 687b ldr r3, [r7, #4]
- 80042b4: 68fa ldr r2, [r7, #12]
- 80042b6: 61da str r2, [r3, #28]
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = OC_Config->Pulse;
- 80042b8: 683b ldr r3, [r7, #0]
- 80042ba: 685a ldr r2, [r3, #4]
- 80042bc: 687b ldr r3, [r7, #4]
- 80042be: 641a str r2, [r3, #64] ; 0x40
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 80042c0: 687b ldr r3, [r7, #4]
- 80042c2: 693a ldr r2, [r7, #16]
- 80042c4: 621a str r2, [r3, #32]
-}
- 80042c6: bf00 nop
- 80042c8: 371c adds r7, #28
- 80042ca: 46bd mov sp, r7
- 80042cc: f85d 7b04 ldr.w r7, [sp], #4
- 80042d0: 4770 bx lr
- 80042d2: bf00 nop
- 80042d4: feff8fff .word 0xfeff8fff
- 80042d8: 40010000 .word 0x40010000
- 80042dc: 40010400 .word 0x40010400
-
-080042e0 <TIM_OC5_SetConfig>:
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config)
-{
- 80042e0: b480 push {r7}
- 80042e2: b087 sub sp, #28
- 80042e4: af00 add r7, sp, #0
- 80042e6: 6078 str r0, [r7, #4]
- 80042e8: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the output: Reset the CCxE Bit */
- TIMx->CCER &= ~TIM_CCER_CC5E;
- 80042ea: 687b ldr r3, [r7, #4]
- 80042ec: 6a1b ldr r3, [r3, #32]
- 80042ee: f423 3280 bic.w r2, r3, #65536 ; 0x10000
- 80042f2: 687b ldr r3, [r7, #4]
- 80042f4: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 80042f6: 687b ldr r3, [r7, #4]
- 80042f8: 6a1b ldr r3, [r3, #32]
- 80042fa: 613b str r3, [r7, #16]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 80042fc: 687b ldr r3, [r7, #4]
- 80042fe: 685b ldr r3, [r3, #4]
- 8004300: 617b str r3, [r7, #20]
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR3;
- 8004302: 687b ldr r3, [r7, #4]
- 8004304: 6d5b ldr r3, [r3, #84] ; 0x54
- 8004306: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~(TIM_CCMR3_OC5M);
- 8004308: 68fa ldr r2, [r7, #12]
- 800430a: 4b1b ldr r3, [pc, #108] ; (8004378 <TIM_OC5_SetConfig+0x98>)
- 800430c: 4013 ands r3, r2
- 800430e: 60fb str r3, [r7, #12]
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
- 8004310: 683b ldr r3, [r7, #0]
- 8004312: 681b ldr r3, [r3, #0]
- 8004314: 68fa ldr r2, [r7, #12]
- 8004316: 4313 orrs r3, r2
- 8004318: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC5P;
- 800431a: 693b ldr r3, [r7, #16]
- 800431c: f423 3300 bic.w r3, r3, #131072 ; 0x20000
- 8004320: 613b str r3, [r7, #16]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 16U);
- 8004322: 683b ldr r3, [r7, #0]
- 8004324: 689b ldr r3, [r3, #8]
- 8004326: 041b lsls r3, r3, #16
- 8004328: 693a ldr r2, [r7, #16]
- 800432a: 4313 orrs r3, r2
- 800432c: 613b str r3, [r7, #16]
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 800432e: 687b ldr r3, [r7, #4]
- 8004330: 4a12 ldr r2, [pc, #72] ; (800437c <TIM_OC5_SetConfig+0x9c>)
- 8004332: 4293 cmp r3, r2
- 8004334: d003 beq.n 800433e <TIM_OC5_SetConfig+0x5e>
- 8004336: 687b ldr r3, [r7, #4]
- 8004338: 4a11 ldr r2, [pc, #68] ; (8004380 <TIM_OC5_SetConfig+0xa0>)
- 800433a: 4293 cmp r3, r2
- 800433c: d109 bne.n 8004352 <TIM_OC5_SetConfig+0x72>
- {
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS5;
- 800433e: 697b ldr r3, [r7, #20]
- 8004340: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8004344: 617b str r3, [r7, #20]
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 8U);
- 8004346: 683b ldr r3, [r7, #0]
- 8004348: 695b ldr r3, [r3, #20]
- 800434a: 021b lsls r3, r3, #8
- 800434c: 697a ldr r2, [r7, #20]
- 800434e: 4313 orrs r3, r2
- 8004350: 617b str r3, [r7, #20]
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 8004352: 687b ldr r3, [r7, #4]
- 8004354: 697a ldr r2, [r7, #20]
- 8004356: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR3 */
- TIMx->CCMR3 = tmpccmrx;
- 8004358: 687b ldr r3, [r7, #4]
- 800435a: 68fa ldr r2, [r7, #12]
- 800435c: 655a str r2, [r3, #84] ; 0x54
-
- /* Set the Capture Compare Register value */
- TIMx->CCR5 = OC_Config->Pulse;
- 800435e: 683b ldr r3, [r7, #0]
- 8004360: 685a ldr r2, [r3, #4]
- 8004362: 687b ldr r3, [r7, #4]
- 8004364: 659a str r2, [r3, #88] ; 0x58
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 8004366: 687b ldr r3, [r7, #4]
- 8004368: 693a ldr r2, [r7, #16]
- 800436a: 621a str r2, [r3, #32]
-}
- 800436c: bf00 nop
- 800436e: 371c adds r7, #28
- 8004370: 46bd mov sp, r7
- 8004372: f85d 7b04 ldr.w r7, [sp], #4
- 8004376: 4770 bx lr
- 8004378: fffeff8f .word 0xfffeff8f
- 800437c: 40010000 .word 0x40010000
- 8004380: 40010400 .word 0x40010400
-
-08004384 <TIM_OC6_SetConfig>:
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config)
-{
- 8004384: b480 push {r7}
- 8004386: b087 sub sp, #28
- 8004388: af00 add r7, sp, #0
- 800438a: 6078 str r0, [r7, #4]
- 800438c: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the output: Reset the CCxE Bit */
- TIMx->CCER &= ~TIM_CCER_CC6E;
- 800438e: 687b ldr r3, [r7, #4]
- 8004390: 6a1b ldr r3, [r3, #32]
- 8004392: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
- 8004396: 687b ldr r3, [r7, #4]
- 8004398: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 800439a: 687b ldr r3, [r7, #4]
- 800439c: 6a1b ldr r3, [r3, #32]
- 800439e: 613b str r3, [r7, #16]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 80043a0: 687b ldr r3, [r7, #4]
- 80043a2: 685b ldr r3, [r3, #4]
- 80043a4: 617b str r3, [r7, #20]
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR3;
- 80043a6: 687b ldr r3, [r7, #4]
- 80043a8: 6d5b ldr r3, [r3, #84] ; 0x54
- 80043aa: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~(TIM_CCMR3_OC6M);
- 80043ac: 68fa ldr r2, [r7, #12]
- 80043ae: 4b1c ldr r3, [pc, #112] ; (8004420 <TIM_OC6_SetConfig+0x9c>)
- 80043b0: 4013 ands r3, r2
- 80043b2: 60fb str r3, [r7, #12]
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
- 80043b4: 683b ldr r3, [r7, #0]
- 80043b6: 681b ldr r3, [r3, #0]
- 80043b8: 021b lsls r3, r3, #8
- 80043ba: 68fa ldr r2, [r7, #12]
- 80043bc: 4313 orrs r3, r2
- 80043be: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint32_t)~TIM_CCER_CC6P;
- 80043c0: 693b ldr r3, [r7, #16]
- 80043c2: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
- 80043c6: 613b str r3, [r7, #16]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 20U);
- 80043c8: 683b ldr r3, [r7, #0]
- 80043ca: 689b ldr r3, [r3, #8]
- 80043cc: 051b lsls r3, r3, #20
- 80043ce: 693a ldr r2, [r7, #16]
- 80043d0: 4313 orrs r3, r2
- 80043d2: 613b str r3, [r7, #16]
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 80043d4: 687b ldr r3, [r7, #4]
- 80043d6: 4a13 ldr r2, [pc, #76] ; (8004424 <TIM_OC6_SetConfig+0xa0>)
- 80043d8: 4293 cmp r3, r2
- 80043da: d003 beq.n 80043e4 <TIM_OC6_SetConfig+0x60>
- 80043dc: 687b ldr r3, [r7, #4]
- 80043de: 4a12 ldr r2, [pc, #72] ; (8004428 <TIM_OC6_SetConfig+0xa4>)
- 80043e0: 4293 cmp r3, r2
- 80043e2: d109 bne.n 80043f8 <TIM_OC6_SetConfig+0x74>
- {
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS6;
- 80043e4: 697b ldr r3, [r7, #20]
- 80043e6: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 80043ea: 617b str r3, [r7, #20]
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 10U);
- 80043ec: 683b ldr r3, [r7, #0]
- 80043ee: 695b ldr r3, [r3, #20]
- 80043f0: 029b lsls r3, r3, #10
- 80043f2: 697a ldr r2, [r7, #20]
- 80043f4: 4313 orrs r3, r2
- 80043f6: 617b str r3, [r7, #20]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 80043f8: 687b ldr r3, [r7, #4]
- 80043fa: 697a ldr r2, [r7, #20]
- 80043fc: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR3 */
- TIMx->CCMR3 = tmpccmrx;
- 80043fe: 687b ldr r3, [r7, #4]
- 8004400: 68fa ldr r2, [r7, #12]
- 8004402: 655a str r2, [r3, #84] ; 0x54
-
- /* Set the Capture Compare Register value */
- TIMx->CCR6 = OC_Config->Pulse;
- 8004404: 683b ldr r3, [r7, #0]
- 8004406: 685a ldr r2, [r3, #4]
- 8004408: 687b ldr r3, [r7, #4]
- 800440a: 65da str r2, [r3, #92] ; 0x5c
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 800440c: 687b ldr r3, [r7, #4]
- 800440e: 693a ldr r2, [r7, #16]
- 8004410: 621a str r2, [r3, #32]
-}
- 8004412: bf00 nop
- 8004414: 371c adds r7, #28
- 8004416: 46bd mov sp, r7
- 8004418: f85d 7b04 ldr.w r7, [sp], #4
- 800441c: 4770 bx lr
- 800441e: bf00 nop
- 8004420: feff8fff .word 0xfeff8fff
- 8004424: 40010000 .word 0x40010000
- 8004428: 40010400 .word 0x40010400
-
-0800442c <TIM_TI1_ConfigInputStage>:
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- 800442c: b480 push {r7}
- 800442e: b087 sub sp, #28
- 8004430: af00 add r7, sp, #0
- 8004432: 60f8 str r0, [r7, #12]
- 8004434: 60b9 str r1, [r7, #8]
- 8004436: 607a str r2, [r7, #4]
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = TIMx->CCER;
- 8004438: 68fb ldr r3, [r7, #12]
- 800443a: 6a1b ldr r3, [r3, #32]
- 800443c: 617b str r3, [r7, #20]
- TIMx->CCER &= ~TIM_CCER_CC1E;
- 800443e: 68fb ldr r3, [r7, #12]
- 8004440: 6a1b ldr r3, [r3, #32]
- 8004442: f023 0201 bic.w r2, r3, #1
- 8004446: 68fb ldr r3, [r7, #12]
- 8004448: 621a str r2, [r3, #32]
- tmpccmr1 = TIMx->CCMR1;
- 800444a: 68fb ldr r3, [r7, #12]
- 800444c: 699b ldr r3, [r3, #24]
- 800444e: 613b str r3, [r7, #16]
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- 8004450: 693b ldr r3, [r7, #16]
- 8004452: f023 03f0 bic.w r3, r3, #240 ; 0xf0
- 8004456: 613b str r3, [r7, #16]
- tmpccmr1 |= (TIM_ICFilter << 4U);
- 8004458: 687b ldr r3, [r7, #4]
- 800445a: 011b lsls r3, r3, #4
- 800445c: 693a ldr r2, [r7, #16]
- 800445e: 4313 orrs r3, r2
- 8004460: 613b str r3, [r7, #16]
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- 8004462: 697b ldr r3, [r7, #20]
- 8004464: f023 030a bic.w r3, r3, #10
- 8004468: 617b str r3, [r7, #20]
- tmpccer |= TIM_ICPolarity;
- 800446a: 697a ldr r2, [r7, #20]
- 800446c: 68bb ldr r3, [r7, #8]
- 800446e: 4313 orrs r3, r2
- 8004470: 617b str r3, [r7, #20]
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- 8004472: 68fb ldr r3, [r7, #12]
- 8004474: 693a ldr r2, [r7, #16]
- 8004476: 619a str r2, [r3, #24]
- TIMx->CCER = tmpccer;
- 8004478: 68fb ldr r3, [r7, #12]
- 800447a: 697a ldr r2, [r7, #20]
- 800447c: 621a str r2, [r3, #32]
-}
- 800447e: bf00 nop
- 8004480: 371c adds r7, #28
- 8004482: 46bd mov sp, r7
- 8004484: f85d 7b04 ldr.w r7, [sp], #4
- 8004488: 4770 bx lr
-
-0800448a <TIM_TI2_ConfigInputStage>:
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- 800448a: b480 push {r7}
- 800448c: b087 sub sp, #28
- 800448e: af00 add r7, sp, #0
- 8004490: 60f8 str r0, [r7, #12]
- 8004492: 60b9 str r1, [r7, #8]
- 8004494: 607a str r2, [r7, #4]
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- 8004496: 68fb ldr r3, [r7, #12]
- 8004498: 6a1b ldr r3, [r3, #32]
- 800449a: f023 0210 bic.w r2, r3, #16
- 800449e: 68fb ldr r3, [r7, #12]
- 80044a0: 621a str r2, [r3, #32]
- tmpccmr1 = TIMx->CCMR1;
- 80044a2: 68fb ldr r3, [r7, #12]
- 80044a4: 699b ldr r3, [r3, #24]
- 80044a6: 617b str r3, [r7, #20]
- tmpccer = TIMx->CCER;
- 80044a8: 68fb ldr r3, [r7, #12]
- 80044aa: 6a1b ldr r3, [r3, #32]
- 80044ac: 613b str r3, [r7, #16]
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC2F;
- 80044ae: 697b ldr r3, [r7, #20]
- 80044b0: f423 4370 bic.w r3, r3, #61440 ; 0xf000
- 80044b4: 617b str r3, [r7, #20]
- tmpccmr1 |= (TIM_ICFilter << 12U);
- 80044b6: 687b ldr r3, [r7, #4]
- 80044b8: 031b lsls r3, r3, #12
- 80044ba: 697a ldr r2, [r7, #20]
- 80044bc: 4313 orrs r3, r2
- 80044be: 617b str r3, [r7, #20]
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- 80044c0: 693b ldr r3, [r7, #16]
- 80044c2: f023 03a0 bic.w r3, r3, #160 ; 0xa0
- 80044c6: 613b str r3, [r7, #16]
- tmpccer |= (TIM_ICPolarity << 4U);
- 80044c8: 68bb ldr r3, [r7, #8]
- 80044ca: 011b lsls r3, r3, #4
- 80044cc: 693a ldr r2, [r7, #16]
- 80044ce: 4313 orrs r3, r2
- 80044d0: 613b str r3, [r7, #16]
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- 80044d2: 68fb ldr r3, [r7, #12]
- 80044d4: 697a ldr r2, [r7, #20]
- 80044d6: 619a str r2, [r3, #24]
- TIMx->CCER = tmpccer;
- 80044d8: 68fb ldr r3, [r7, #12]
- 80044da: 693a ldr r2, [r7, #16]
- 80044dc: 621a str r2, [r3, #32]
-}
- 80044de: bf00 nop
- 80044e0: 371c adds r7, #28
- 80044e2: 46bd mov sp, r7
- 80044e4: f85d 7b04 ldr.w r7, [sp], #4
- 80044e8: 4770 bx lr
-
-080044ea <TIM_ITRx_SetConfig>:
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
-{
- 80044ea: b480 push {r7}
- 80044ec: b085 sub sp, #20
- 80044ee: af00 add r7, sp, #0
- 80044f0: 6078 str r0, [r7, #4]
- 80044f2: 6039 str r1, [r7, #0]
- uint32_t tmpsmcr;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- 80044f4: 687b ldr r3, [r7, #4]
- 80044f6: 689b ldr r3, [r3, #8]
- 80044f8: 60fb str r3, [r7, #12]
- /* Reset the TS Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- 80044fa: 68fb ldr r3, [r7, #12]
- 80044fc: f023 0370 bic.w r3, r3, #112 ; 0x70
- 8004500: 60fb str r3, [r7, #12]
- /* Set the Input Trigger source and the slave mode*/
- tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
- 8004502: 683a ldr r2, [r7, #0]
- 8004504: 68fb ldr r3, [r7, #12]
- 8004506: 4313 orrs r3, r2
- 8004508: f043 0307 orr.w r3, r3, #7
- 800450c: 60fb str r3, [r7, #12]
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
- 800450e: 687b ldr r3, [r7, #4]
- 8004510: 68fa ldr r2, [r7, #12]
- 8004512: 609a str r2, [r3, #8]
-}
- 8004514: bf00 nop
- 8004516: 3714 adds r7, #20
- 8004518: 46bd mov sp, r7
- 800451a: f85d 7b04 ldr.w r7, [sp], #4
- 800451e: 4770 bx lr
-
-08004520 <TIM_ETR_SetConfig>:
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
-{
- 8004520: b480 push {r7}
- 8004522: b087 sub sp, #28
- 8004524: af00 add r7, sp, #0
- 8004526: 60f8 str r0, [r7, #12]
- 8004528: 60b9 str r1, [r7, #8]
- 800452a: 607a str r2, [r7, #4]
- 800452c: 603b str r3, [r7, #0]
- uint32_t tmpsmcr;
-
- tmpsmcr = TIMx->SMCR;
- 800452e: 68fb ldr r3, [r7, #12]
- 8004530: 689b ldr r3, [r3, #8]
- 8004532: 617b str r3, [r7, #20]
-
- /* Reset the ETR Bits */
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- 8004534: 697b ldr r3, [r7, #20]
- 8004536: f423 437f bic.w r3, r3, #65280 ; 0xff00
- 800453a: 617b str r3, [r7, #20]
-
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
- 800453c: 683b ldr r3, [r7, #0]
- 800453e: 021a lsls r2, r3, #8
- 8004540: 687b ldr r3, [r7, #4]
- 8004542: 431a orrs r2, r3
- 8004544: 68bb ldr r3, [r7, #8]
- 8004546: 4313 orrs r3, r2
- 8004548: 697a ldr r2, [r7, #20]
- 800454a: 4313 orrs r3, r2
- 800454c: 617b str r3, [r7, #20]
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
- 800454e: 68fb ldr r3, [r7, #12]
- 8004550: 697a ldr r2, [r7, #20]
- 8004552: 609a str r2, [r3, #8]
-}
- 8004554: bf00 nop
- 8004556: 371c adds r7, #28
- 8004558: 46bd mov sp, r7
- 800455a: f85d 7b04 ldr.w r7, [sp], #4
- 800455e: 4770 bx lr
-
-08004560 <TIM_CCxChannelCmd>:
- * @param ChannelState specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
- * @retval None
- */
-void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
-{
- 8004560: b480 push {r7}
- 8004562: b087 sub sp, #28
- 8004564: af00 add r7, sp, #0
- 8004566: 60f8 str r0, [r7, #12]
- 8004568: 60b9 str r1, [r7, #8]
- 800456a: 607a str r2, [r7, #4]
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_TIM_CHANNELS(Channel));
-
- tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
- 800456c: 68bb ldr r3, [r7, #8]
- 800456e: f003 031f and.w r3, r3, #31
- 8004572: 2201 movs r2, #1
- 8004574: fa02 f303 lsl.w r3, r2, r3
- 8004578: 617b str r3, [r7, #20]
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= ~tmp;
- 800457a: 68fb ldr r3, [r7, #12]
- 800457c: 6a1a ldr r2, [r3, #32]
- 800457e: 697b ldr r3, [r7, #20]
- 8004580: 43db mvns r3, r3
- 8004582: 401a ands r2, r3
- 8004584: 68fb ldr r3, [r7, #12]
- 8004586: 621a str r2, [r3, #32]
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
- 8004588: 68fb ldr r3, [r7, #12]
- 800458a: 6a1a ldr r2, [r3, #32]
- 800458c: 68bb ldr r3, [r7, #8]
- 800458e: f003 031f and.w r3, r3, #31
- 8004592: 6879 ldr r1, [r7, #4]
- 8004594: fa01 f303 lsl.w r3, r1, r3
- 8004598: 431a orrs r2, r3
- 800459a: 68fb ldr r3, [r7, #12]
- 800459c: 621a str r2, [r3, #32]
-}
- 800459e: bf00 nop
- 80045a0: 371c adds r7, #28
- 80045a2: 46bd mov sp, r7
- 80045a4: f85d 7b04 ldr.w r7, [sp], #4
- 80045a8: 4770 bx lr
- ...
-
-080045ac <HAL_TIMEx_MasterConfigSynchronization>:
- * mode.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
- TIM_MasterConfigTypeDef *sMasterConfig)
-{
- 80045ac: b480 push {r7}
- 80045ae: b085 sub sp, #20
- 80045b0: af00 add r7, sp, #0
- 80045b2: 6078 str r0, [r7, #4]
- 80045b4: 6039 str r1, [r7, #0]
- assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
- assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-
- /* Check input state */
- __HAL_LOCK(htim);
- 80045b6: 687b ldr r3, [r7, #4]
- 80045b8: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 80045bc: 2b01 cmp r3, #1
- 80045be: d101 bne.n 80045c4 <HAL_TIMEx_MasterConfigSynchronization+0x18>
- 80045c0: 2302 movs r3, #2
- 80045c2: e045 b.n 8004650 <HAL_TIMEx_MasterConfigSynchronization+0xa4>
- 80045c4: 687b ldr r3, [r7, #4]
- 80045c6: 2201 movs r2, #1
- 80045c8: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- /* Change the handler state */
- htim->State = HAL_TIM_STATE_BUSY;
- 80045cc: 687b ldr r3, [r7, #4]
- 80045ce: 2202 movs r2, #2
- 80045d0: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = htim->Instance->CR2;
- 80045d4: 687b ldr r3, [r7, #4]
- 80045d6: 681b ldr r3, [r3, #0]
- 80045d8: 685b ldr r3, [r3, #4]
- 80045da: 60fb str r3, [r7, #12]
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
- 80045dc: 687b ldr r3, [r7, #4]
- 80045de: 681b ldr r3, [r3, #0]
- 80045e0: 689b ldr r3, [r3, #8]
- 80045e2: 60bb str r3, [r7, #8]
-
- /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
- if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
- 80045e4: 687b ldr r3, [r7, #4]
- 80045e6: 681b ldr r3, [r3, #0]
- 80045e8: 4a1c ldr r2, [pc, #112] ; (800465c <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
- 80045ea: 4293 cmp r3, r2
- 80045ec: d004 beq.n 80045f8 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
- 80045ee: 687b ldr r3, [r7, #4]
- 80045f0: 681b ldr r3, [r3, #0]
- 80045f2: 4a1b ldr r2, [pc, #108] ; (8004660 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
- 80045f4: 4293 cmp r3, r2
- 80045f6: d108 bne.n 800460a <HAL_TIMEx_MasterConfigSynchronization+0x5e>
- {
- /* Check the parameters */
- assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
-
- /* Clear the MMS2 bits */
- tmpcr2 &= ~TIM_CR2_MMS2;
- 80045f8: 68fb ldr r3, [r7, #12]
- 80045fa: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
- 80045fe: 60fb str r3, [r7, #12]
- /* Select the TRGO2 source*/
- tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
- 8004600: 683b ldr r3, [r7, #0]
- 8004602: 685b ldr r3, [r3, #4]
- 8004604: 68fa ldr r2, [r7, #12]
- 8004606: 4313 orrs r3, r2
- 8004608: 60fb str r3, [r7, #12]
- }
-
- /* Reset the MMS Bits */
- tmpcr2 &= ~TIM_CR2_MMS;
- 800460a: 68fb ldr r3, [r7, #12]
- 800460c: f023 0370 bic.w r3, r3, #112 ; 0x70
- 8004610: 60fb str r3, [r7, #12]
- /* Select the TRGO source */
- tmpcr2 |= sMasterConfig->MasterOutputTrigger;
- 8004612: 683b ldr r3, [r7, #0]
- 8004614: 681b ldr r3, [r3, #0]
- 8004616: 68fa ldr r2, [r7, #12]
- 8004618: 4313 orrs r3, r2
- 800461a: 60fb str r3, [r7, #12]
-
- /* Reset the MSM Bit */
- tmpsmcr &= ~TIM_SMCR_MSM;
- 800461c: 68bb ldr r3, [r7, #8]
- 800461e: f023 0380 bic.w r3, r3, #128 ; 0x80
- 8004622: 60bb str r3, [r7, #8]
- /* Set master mode */
- tmpsmcr |= sMasterConfig->MasterSlaveMode;
- 8004624: 683b ldr r3, [r7, #0]
- 8004626: 689b ldr r3, [r3, #8]
- 8004628: 68ba ldr r2, [r7, #8]
- 800462a: 4313 orrs r3, r2
- 800462c: 60bb str r3, [r7, #8]
-
- /* Update TIMx CR2 */
- htim->Instance->CR2 = tmpcr2;
- 800462e: 687b ldr r3, [r7, #4]
- 8004630: 681b ldr r3, [r3, #0]
- 8004632: 68fa ldr r2, [r7, #12]
- 8004634: 605a str r2, [r3, #4]
-
- /* Update TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
- 8004636: 687b ldr r3, [r7, #4]
- 8004638: 681b ldr r3, [r3, #0]
- 800463a: 68ba ldr r2, [r7, #8]
- 800463c: 609a str r2, [r3, #8]
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
- 800463e: 687b ldr r3, [r7, #4]
- 8004640: 2201 movs r2, #1
- 8004642: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- __HAL_UNLOCK(htim);
- 8004646: 687b ldr r3, [r7, #4]
- 8004648: 2200 movs r2, #0
- 800464a: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- return HAL_OK;
- 800464e: 2300 movs r3, #0
-}
- 8004650: 4618 mov r0, r3
- 8004652: 3714 adds r7, #20
- 8004654: 46bd mov sp, r7
- 8004656: f85d 7b04 ldr.w r7, [sp], #4
- 800465a: 4770 bx lr
- 800465c: 40010000 .word 0x40010000
- 8004660: 40010400 .word 0x40010400
-
-08004664 <HAL_TIMEx_CommutCallback>:
- * @brief Hall commutation changed callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
-{
- 8004664: b480 push {r7}
- 8004666: b083 sub sp, #12
- 8004668: af00 add r7, sp, #0
- 800466a: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_CommutCallback could be implemented in the user file
- */
-}
- 800466c: bf00 nop
- 800466e: 370c adds r7, #12
- 8004670: 46bd mov sp, r7
- 8004672: f85d 7b04 ldr.w r7, [sp], #4
- 8004676: 4770 bx lr
-
-08004678 <HAL_TIMEx_BreakCallback>:
- * @brief Hall Break detection callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
-{
- 8004678: b480 push {r7}
- 800467a: b083 sub sp, #12
- 800467c: af00 add r7, sp, #0
- 800467e: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_BreakCallback could be implemented in the user file
- */
-}
- 8004680: bf00 nop
- 8004682: 370c adds r7, #12
- 8004684: 46bd mov sp, r7
- 8004686: f85d 7b04 ldr.w r7, [sp], #4
- 800468a: 4770 bx lr
-
-0800468c <HAL_TIMEx_Break2Callback>:
- * @brief Hall Break2 detection callback in non blocking mode
- * @param htim: TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
-{
- 800468c: b480 push {r7}
- 800468e: b083 sub sp, #12
- 8004690: af00 add r7, sp, #0
- 8004692: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_Break2Callback could be implemented in the user file
- */
-}
- 8004694: bf00 nop
- 8004696: 370c adds r7, #12
- 8004698: 46bd mov sp, r7
- 800469a: f85d 7b04 ldr.w r7, [sp], #4
- 800469e: 4770 bx lr
-
-080046a0 <HAL_UART_Init>:
- * parameters in the UART_InitTypeDef and initialize the associated handle.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
-{
- 80046a0: b580 push {r7, lr}
- 80046a2: b082 sub sp, #8
- 80046a4: af00 add r7, sp, #0
- 80046a6: 6078 str r0, [r7, #4]
- /* Check the UART handle allocation */
- if (huart == NULL)
- 80046a8: 687b ldr r3, [r7, #4]
- 80046aa: 2b00 cmp r3, #0
- 80046ac: d101 bne.n 80046b2 <HAL_UART_Init+0x12>
- {
- return HAL_ERROR;
- 80046ae: 2301 movs r3, #1
- 80046b0: e040 b.n 8004734 <HAL_UART_Init+0x94>
- {
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(huart->Instance));
- }
-
- if (huart->gState == HAL_UART_STATE_RESET)
- 80046b2: 687b ldr r3, [r7, #4]
- 80046b4: 6f5b ldr r3, [r3, #116] ; 0x74
- 80046b6: 2b00 cmp r3, #0
- 80046b8: d106 bne.n 80046c8 <HAL_UART_Init+0x28>
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
- 80046ba: 687b ldr r3, [r7, #4]
- 80046bc: 2200 movs r2, #0
- 80046be: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- /* Init the low level hardware */
- huart->MspInitCallback(huart);
-#else
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_UART_MspInit(huart);
- 80046c2: 6878 ldr r0, [r7, #4]
- 80046c4: f7fd fa38 bl 8001b38 <HAL_UART_MspInit>
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
- 80046c8: 687b ldr r3, [r7, #4]
- 80046ca: 2224 movs r2, #36 ; 0x24
- 80046cc: 675a str r2, [r3, #116] ; 0x74
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
- 80046ce: 687b ldr r3, [r7, #4]
- 80046d0: 681b ldr r3, [r3, #0]
- 80046d2: 681a ldr r2, [r3, #0]
- 80046d4: 687b ldr r3, [r7, #4]
- 80046d6: 681b ldr r3, [r3, #0]
- 80046d8: f022 0201 bic.w r2, r2, #1
- 80046dc: 601a str r2, [r3, #0]
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
- 80046de: 6878 ldr r0, [r7, #4]
- 80046e0: f000 fa90 bl 8004c04 <UART_SetConfig>
- 80046e4: 4603 mov r3, r0
- 80046e6: 2b01 cmp r3, #1
- 80046e8: d101 bne.n 80046ee <HAL_UART_Init+0x4e>
- {
- return HAL_ERROR;
- 80046ea: 2301 movs r3, #1
- 80046ec: e022 b.n 8004734 <HAL_UART_Init+0x94>
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- 80046ee: 687b ldr r3, [r7, #4]
- 80046f0: 6a5b ldr r3, [r3, #36] ; 0x24
- 80046f2: 2b00 cmp r3, #0
- 80046f4: d002 beq.n 80046fc <HAL_UART_Init+0x5c>
- {
- UART_AdvFeatureConfig(huart);
- 80046f6: 6878 ldr r0, [r7, #4]
- 80046f8: f000 fd28 bl 800514c <UART_AdvFeatureConfig>
- }
-
- /* In asynchronous mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- 80046fc: 687b ldr r3, [r7, #4]
- 80046fe: 681b ldr r3, [r3, #0]
- 8004700: 685a ldr r2, [r3, #4]
- 8004702: 687b ldr r3, [r7, #4]
- 8004704: 681b ldr r3, [r3, #0]
- 8004706: f422 4290 bic.w r2, r2, #18432 ; 0x4800
- 800470a: 605a str r2, [r3, #4]
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
- 800470c: 687b ldr r3, [r7, #4]
- 800470e: 681b ldr r3, [r3, #0]
- 8004710: 689a ldr r2, [r3, #8]
- 8004712: 687b ldr r3, [r7, #4]
- 8004714: 681b ldr r3, [r3, #0]
- 8004716: f022 022a bic.w r2, r2, #42 ; 0x2a
- 800471a: 609a str r2, [r3, #8]
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
- 800471c: 687b ldr r3, [r7, #4]
- 800471e: 681b ldr r3, [r3, #0]
- 8004720: 681a ldr r2, [r3, #0]
- 8004722: 687b ldr r3, [r7, #4]
- 8004724: 681b ldr r3, [r3, #0]
- 8004726: f042 0201 orr.w r2, r2, #1
- 800472a: 601a str r2, [r3, #0]
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
- return (UART_CheckIdleState(huart));
- 800472c: 6878 ldr r0, [r7, #4]
- 800472e: f000 fdaf bl 8005290 <UART_CheckIdleState>
- 8004732: 4603 mov r3, r0
-}
- 8004734: 4618 mov r0, r3
- 8004736: 3708 adds r7, #8
- 8004738: 46bd mov sp, r7
- 800473a: bd80 pop {r7, pc}
-
-0800473c <HAL_UART_Transmit>:
- * @param Size Amount of data to be sent.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- 800473c: b580 push {r7, lr}
- 800473e: b08a sub sp, #40 ; 0x28
- 8004740: af02 add r7, sp, #8
- 8004742: 60f8 str r0, [r7, #12]
- 8004744: 60b9 str r1, [r7, #8]
- 8004746: 603b str r3, [r7, #0]
- 8004748: 4613 mov r3, r2
- 800474a: 80fb strh r3, [r7, #6]
- uint8_t *pdata8bits;
- uint16_t *pdata16bits;
- uint32_t tickstart;
-
- /* Check that a Tx process is not already ongoing */
- if (huart->gState == HAL_UART_STATE_READY)
- 800474c: 68fb ldr r3, [r7, #12]
- 800474e: 6f5b ldr r3, [r3, #116] ; 0x74
- 8004750: 2b20 cmp r3, #32
- 8004752: d17f bne.n 8004854 <HAL_UART_Transmit+0x118>
- {
- if ((pData == NULL) || (Size == 0U))
- 8004754: 68bb ldr r3, [r7, #8]
- 8004756: 2b00 cmp r3, #0
- 8004758: d002 beq.n 8004760 <HAL_UART_Transmit+0x24>
- 800475a: 88fb ldrh r3, [r7, #6]
- 800475c: 2b00 cmp r3, #0
- 800475e: d101 bne.n 8004764 <HAL_UART_Transmit+0x28>
- {
- return HAL_ERROR;
- 8004760: 2301 movs r3, #1
- 8004762: e078 b.n 8004856 <HAL_UART_Transmit+0x11a>
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
- 8004764: 68fb ldr r3, [r7, #12]
- 8004766: f893 3070 ldrb.w r3, [r3, #112] ; 0x70
- 800476a: 2b01 cmp r3, #1
- 800476c: d101 bne.n 8004772 <HAL_UART_Transmit+0x36>
- 800476e: 2302 movs r3, #2
- 8004770: e071 b.n 8004856 <HAL_UART_Transmit+0x11a>
- 8004772: 68fb ldr r3, [r7, #12]
- 8004774: 2201 movs r2, #1
- 8004776: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 800477a: 68fb ldr r3, [r7, #12]
- 800477c: 2200 movs r2, #0
- 800477e: 67da str r2, [r3, #124] ; 0x7c
- huart->gState = HAL_UART_STATE_BUSY_TX;
- 8004780: 68fb ldr r3, [r7, #12]
- 8004782: 2221 movs r2, #33 ; 0x21
- 8004784: 675a str r2, [r3, #116] ; 0x74
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
- 8004786: f7fd fb1f bl 8001dc8 <HAL_GetTick>
- 800478a: 6178 str r0, [r7, #20]
-
- huart->TxXferSize = Size;
- 800478c: 68fb ldr r3, [r7, #12]
- 800478e: 88fa ldrh r2, [r7, #6]
- 8004790: f8a3 2050 strh.w r2, [r3, #80] ; 0x50
- huart->TxXferCount = Size;
- 8004794: 68fb ldr r3, [r7, #12]
- 8004796: 88fa ldrh r2, [r7, #6]
- 8004798: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
-
- /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- 800479c: 68fb ldr r3, [r7, #12]
- 800479e: 689b ldr r3, [r3, #8]
- 80047a0: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 80047a4: d108 bne.n 80047b8 <HAL_UART_Transmit+0x7c>
- 80047a6: 68fb ldr r3, [r7, #12]
- 80047a8: 691b ldr r3, [r3, #16]
- 80047aa: 2b00 cmp r3, #0
- 80047ac: d104 bne.n 80047b8 <HAL_UART_Transmit+0x7c>
- {
- pdata8bits = NULL;
- 80047ae: 2300 movs r3, #0
- 80047b0: 61fb str r3, [r7, #28]
- pdata16bits = (uint16_t *) pData;
- 80047b2: 68bb ldr r3, [r7, #8]
- 80047b4: 61bb str r3, [r7, #24]
- 80047b6: e003 b.n 80047c0 <HAL_UART_Transmit+0x84>
- }
- else
- {
- pdata8bits = pData;
- 80047b8: 68bb ldr r3, [r7, #8]
- 80047ba: 61fb str r3, [r7, #28]
- pdata16bits = NULL;
- 80047bc: 2300 movs r3, #0
- 80047be: 61bb str r3, [r7, #24]
- }
-
- while (huart->TxXferCount > 0U)
- 80047c0: e02c b.n 800481c <HAL_UART_Transmit+0xe0>
- {
- if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- 80047c2: 683b ldr r3, [r7, #0]
- 80047c4: 9300 str r3, [sp, #0]
- 80047c6: 697b ldr r3, [r7, #20]
- 80047c8: 2200 movs r2, #0
- 80047ca: 2180 movs r1, #128 ; 0x80
- 80047cc: 68f8 ldr r0, [r7, #12]
- 80047ce: f000 fd8e bl 80052ee <UART_WaitOnFlagUntilTimeout>
- 80047d2: 4603 mov r3, r0
- 80047d4: 2b00 cmp r3, #0
- 80047d6: d001 beq.n 80047dc <HAL_UART_Transmit+0xa0>
- {
- return HAL_TIMEOUT;
- 80047d8: 2303 movs r3, #3
- 80047da: e03c b.n 8004856 <HAL_UART_Transmit+0x11a>
- }
- if (pdata8bits == NULL)
- 80047dc: 69fb ldr r3, [r7, #28]
- 80047de: 2b00 cmp r3, #0
- 80047e0: d10b bne.n 80047fa <HAL_UART_Transmit+0xbe>
- {
- huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
- 80047e2: 69bb ldr r3, [r7, #24]
- 80047e4: 881b ldrh r3, [r3, #0]
- 80047e6: 461a mov r2, r3
- 80047e8: 68fb ldr r3, [r7, #12]
- 80047ea: 681b ldr r3, [r3, #0]
- 80047ec: f3c2 0208 ubfx r2, r2, #0, #9
- 80047f0: 629a str r2, [r3, #40] ; 0x28
- pdata16bits++;
- 80047f2: 69bb ldr r3, [r7, #24]
- 80047f4: 3302 adds r3, #2
- 80047f6: 61bb str r3, [r7, #24]
- 80047f8: e007 b.n 800480a <HAL_UART_Transmit+0xce>
- }
- else
- {
- huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
- 80047fa: 69fb ldr r3, [r7, #28]
- 80047fc: 781a ldrb r2, [r3, #0]
- 80047fe: 68fb ldr r3, [r7, #12]
- 8004800: 681b ldr r3, [r3, #0]
- 8004802: 629a str r2, [r3, #40] ; 0x28
- pdata8bits++;
- 8004804: 69fb ldr r3, [r7, #28]
- 8004806: 3301 adds r3, #1
- 8004808: 61fb str r3, [r7, #28]
- }
- huart->TxXferCount--;
- 800480a: 68fb ldr r3, [r7, #12]
- 800480c: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
- 8004810: b29b uxth r3, r3
- 8004812: 3b01 subs r3, #1
- 8004814: b29a uxth r2, r3
- 8004816: 68fb ldr r3, [r7, #12]
- 8004818: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
- while (huart->TxXferCount > 0U)
- 800481c: 68fb ldr r3, [r7, #12]
- 800481e: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
- 8004822: b29b uxth r3, r3
- 8004824: 2b00 cmp r3, #0
- 8004826: d1cc bne.n 80047c2 <HAL_UART_Transmit+0x86>
- }
-
- if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- 8004828: 683b ldr r3, [r7, #0]
- 800482a: 9300 str r3, [sp, #0]
- 800482c: 697b ldr r3, [r7, #20]
- 800482e: 2200 movs r2, #0
- 8004830: 2140 movs r1, #64 ; 0x40
- 8004832: 68f8 ldr r0, [r7, #12]
- 8004834: f000 fd5b bl 80052ee <UART_WaitOnFlagUntilTimeout>
- 8004838: 4603 mov r3, r0
- 800483a: 2b00 cmp r3, #0
- 800483c: d001 beq.n 8004842 <HAL_UART_Transmit+0x106>
- {
- return HAL_TIMEOUT;
- 800483e: 2303 movs r3, #3
- 8004840: e009 b.n 8004856 <HAL_UART_Transmit+0x11a>
- }
-
- /* At end of Tx process, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- 8004842: 68fb ldr r3, [r7, #12]
- 8004844: 2220 movs r2, #32
- 8004846: 675a str r2, [r3, #116] ; 0x74
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 8004848: 68fb ldr r3, [r7, #12]
- 800484a: 2200 movs r2, #0
- 800484c: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- return HAL_OK;
- 8004850: 2300 movs r3, #0
- 8004852: e000 b.n 8004856 <HAL_UART_Transmit+0x11a>
- }
- else
- {
- return HAL_BUSY;
- 8004854: 2302 movs r3, #2
- }
-}
- 8004856: 4618 mov r0, r3
- 8004858: 3720 adds r7, #32
- 800485a: 46bd mov sp, r7
- 800485c: bd80 pop {r7, pc}
- ...
-
-08004860 <HAL_UART_Receive_IT>:
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- 8004860: b480 push {r7}
- 8004862: b085 sub sp, #20
- 8004864: af00 add r7, sp, #0
- 8004866: 60f8 str r0, [r7, #12]
- 8004868: 60b9 str r1, [r7, #8]
- 800486a: 4613 mov r3, r2
- 800486c: 80fb strh r3, [r7, #6]
- /* Check that a Rx process is not already ongoing */
- if (huart->RxState == HAL_UART_STATE_READY)
- 800486e: 68fb ldr r3, [r7, #12]
- 8004870: 6f9b ldr r3, [r3, #120] ; 0x78
- 8004872: 2b20 cmp r3, #32
- 8004874: f040 808a bne.w 800498c <HAL_UART_Receive_IT+0x12c>
- {
- if ((pData == NULL) || (Size == 0U))
- 8004878: 68bb ldr r3, [r7, #8]
- 800487a: 2b00 cmp r3, #0
- 800487c: d002 beq.n 8004884 <HAL_UART_Receive_IT+0x24>
- 800487e: 88fb ldrh r3, [r7, #6]
- 8004880: 2b00 cmp r3, #0
- 8004882: d101 bne.n 8004888 <HAL_UART_Receive_IT+0x28>
- {
- return HAL_ERROR;
- 8004884: 2301 movs r3, #1
- 8004886: e082 b.n 800498e <HAL_UART_Receive_IT+0x12e>
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
- 8004888: 68fb ldr r3, [r7, #12]
- 800488a: f893 3070 ldrb.w r3, [r3, #112] ; 0x70
- 800488e: 2b01 cmp r3, #1
- 8004890: d101 bne.n 8004896 <HAL_UART_Receive_IT+0x36>
- 8004892: 2302 movs r3, #2
- 8004894: e07b b.n 800498e <HAL_UART_Receive_IT+0x12e>
- 8004896: 68fb ldr r3, [r7, #12]
- 8004898: 2201 movs r2, #1
- 800489a: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- huart->pRxBuffPtr = pData;
- 800489e: 68fb ldr r3, [r7, #12]
- 80048a0: 68ba ldr r2, [r7, #8]
- 80048a2: 655a str r2, [r3, #84] ; 0x54
- huart->RxXferSize = Size;
- 80048a4: 68fb ldr r3, [r7, #12]
- 80048a6: 88fa ldrh r2, [r7, #6]
- 80048a8: f8a3 2058 strh.w r2, [r3, #88] ; 0x58
- huart->RxXferCount = Size;
- 80048ac: 68fb ldr r3, [r7, #12]
- 80048ae: 88fa ldrh r2, [r7, #6]
- 80048b0: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
- huart->RxISR = NULL;
- 80048b4: 68fb ldr r3, [r7, #12]
- 80048b6: 2200 movs r2, #0
- 80048b8: 661a str r2, [r3, #96] ; 0x60
-
- /* Computation of UART mask to apply to RDR register */
- UART_MASK_COMPUTATION(huart);
- 80048ba: 68fb ldr r3, [r7, #12]
- 80048bc: 689b ldr r3, [r3, #8]
- 80048be: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 80048c2: d10e bne.n 80048e2 <HAL_UART_Receive_IT+0x82>
- 80048c4: 68fb ldr r3, [r7, #12]
- 80048c6: 691b ldr r3, [r3, #16]
- 80048c8: 2b00 cmp r3, #0
- 80048ca: d105 bne.n 80048d8 <HAL_UART_Receive_IT+0x78>
- 80048cc: 68fb ldr r3, [r7, #12]
- 80048ce: f240 12ff movw r2, #511 ; 0x1ff
- 80048d2: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 80048d6: e02d b.n 8004934 <HAL_UART_Receive_IT+0xd4>
- 80048d8: 68fb ldr r3, [r7, #12]
- 80048da: 22ff movs r2, #255 ; 0xff
- 80048dc: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 80048e0: e028 b.n 8004934 <HAL_UART_Receive_IT+0xd4>
- 80048e2: 68fb ldr r3, [r7, #12]
- 80048e4: 689b ldr r3, [r3, #8]
- 80048e6: 2b00 cmp r3, #0
- 80048e8: d10d bne.n 8004906 <HAL_UART_Receive_IT+0xa6>
- 80048ea: 68fb ldr r3, [r7, #12]
- 80048ec: 691b ldr r3, [r3, #16]
- 80048ee: 2b00 cmp r3, #0
- 80048f0: d104 bne.n 80048fc <HAL_UART_Receive_IT+0x9c>
- 80048f2: 68fb ldr r3, [r7, #12]
- 80048f4: 22ff movs r2, #255 ; 0xff
- 80048f6: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 80048fa: e01b b.n 8004934 <HAL_UART_Receive_IT+0xd4>
- 80048fc: 68fb ldr r3, [r7, #12]
- 80048fe: 227f movs r2, #127 ; 0x7f
- 8004900: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 8004904: e016 b.n 8004934 <HAL_UART_Receive_IT+0xd4>
- 8004906: 68fb ldr r3, [r7, #12]
- 8004908: 689b ldr r3, [r3, #8]
- 800490a: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
- 800490e: d10d bne.n 800492c <HAL_UART_Receive_IT+0xcc>
- 8004910: 68fb ldr r3, [r7, #12]
- 8004912: 691b ldr r3, [r3, #16]
- 8004914: 2b00 cmp r3, #0
- 8004916: d104 bne.n 8004922 <HAL_UART_Receive_IT+0xc2>
- 8004918: 68fb ldr r3, [r7, #12]
- 800491a: 227f movs r2, #127 ; 0x7f
- 800491c: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 8004920: e008 b.n 8004934 <HAL_UART_Receive_IT+0xd4>
- 8004922: 68fb ldr r3, [r7, #12]
- 8004924: 223f movs r2, #63 ; 0x3f
- 8004926: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 800492a: e003 b.n 8004934 <HAL_UART_Receive_IT+0xd4>
- 800492c: 68fb ldr r3, [r7, #12]
- 800492e: 2200 movs r2, #0
- 8004930: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8004934: 68fb ldr r3, [r7, #12]
- 8004936: 2200 movs r2, #0
- 8004938: 67da str r2, [r3, #124] ; 0x7c
- huart->RxState = HAL_UART_STATE_BUSY_RX;
- 800493a: 68fb ldr r3, [r7, #12]
- 800493c: 2222 movs r2, #34 ; 0x22
- 800493e: 679a str r2, [r3, #120] ; 0x78
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 8004940: 68fb ldr r3, [r7, #12]
- 8004942: 681b ldr r3, [r3, #0]
- 8004944: 689a ldr r2, [r3, #8]
- 8004946: 68fb ldr r3, [r7, #12]
- 8004948: 681b ldr r3, [r3, #0]
- 800494a: f042 0201 orr.w r2, r2, #1
- 800494e: 609a str r2, [r3, #8]
-
- /* Set the Rx ISR function pointer according to the data word length */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- 8004950: 68fb ldr r3, [r7, #12]
- 8004952: 689b ldr r3, [r3, #8]
- 8004954: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8004958: d107 bne.n 800496a <HAL_UART_Receive_IT+0x10a>
- 800495a: 68fb ldr r3, [r7, #12]
- 800495c: 691b ldr r3, [r3, #16]
- 800495e: 2b00 cmp r3, #0
- 8004960: d103 bne.n 800496a <HAL_UART_Receive_IT+0x10a>
- {
- huart->RxISR = UART_RxISR_16BIT;
- 8004962: 68fb ldr r3, [r7, #12]
- 8004964: 4a0d ldr r2, [pc, #52] ; (800499c <HAL_UART_Receive_IT+0x13c>)
- 8004966: 661a str r2, [r3, #96] ; 0x60
- 8004968: e002 b.n 8004970 <HAL_UART_Receive_IT+0x110>
- }
- else
- {
- huart->RxISR = UART_RxISR_8BIT;
- 800496a: 68fb ldr r3, [r7, #12]
- 800496c: 4a0c ldr r2, [pc, #48] ; (80049a0 <HAL_UART_Receive_IT+0x140>)
- 800496e: 661a str r2, [r3, #96] ; 0x60
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 8004970: 68fb ldr r3, [r7, #12]
- 8004972: 2200 movs r2, #0
- 8004974: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
- 8004978: 68fb ldr r3, [r7, #12]
- 800497a: 681b ldr r3, [r3, #0]
- 800497c: 681a ldr r2, [r3, #0]
- 800497e: 68fb ldr r3, [r7, #12]
- 8004980: 681b ldr r3, [r3, #0]
- 8004982: f442 7290 orr.w r2, r2, #288 ; 0x120
- 8004986: 601a str r2, [r3, #0]
-
- return HAL_OK;
- 8004988: 2300 movs r3, #0
- 800498a: e000 b.n 800498e <HAL_UART_Receive_IT+0x12e>
- }
- else
- {
- return HAL_BUSY;
- 800498c: 2302 movs r3, #2
- }
-}
- 800498e: 4618 mov r0, r3
- 8004990: 3714 adds r7, #20
- 8004992: 46bd mov sp, r7
- 8004994: f85d 7b04 ldr.w r7, [sp], #4
- 8004998: 4770 bx lr
- 800499a: bf00 nop
- 800499c: 080054c3 .word 0x080054c3
- 80049a0: 0800541d .word 0x0800541d
-
-080049a4 <HAL_UART_IRQHandler>:
- * @brief Handle UART interrupt request.
- * @param huart UART handle.
- * @retval None
- */
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
-{
- 80049a4: b580 push {r7, lr}
- 80049a6: b088 sub sp, #32
- 80049a8: af00 add r7, sp, #0
- 80049aa: 6078 str r0, [r7, #4]
- uint32_t isrflags = READ_REG(huart->Instance->ISR);
- 80049ac: 687b ldr r3, [r7, #4]
- 80049ae: 681b ldr r3, [r3, #0]
- 80049b0: 69db ldr r3, [r3, #28]
- 80049b2: 61fb str r3, [r7, #28]
- uint32_t cr1its = READ_REG(huart->Instance->CR1);
- 80049b4: 687b ldr r3, [r7, #4]
- 80049b6: 681b ldr r3, [r3, #0]
- 80049b8: 681b ldr r3, [r3, #0]
- 80049ba: 61bb str r3, [r7, #24]
- uint32_t cr3its = READ_REG(huart->Instance->CR3);
- 80049bc: 687b ldr r3, [r7, #4]
- 80049be: 681b ldr r3, [r3, #0]
- 80049c0: 689b ldr r3, [r3, #8]
- 80049c2: 617b str r3, [r7, #20]
-
- uint32_t errorflags;
- uint32_t errorcode;
-
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- 80049c4: 69fb ldr r3, [r7, #28]
- 80049c6: f003 030f and.w r3, r3, #15
- 80049ca: 613b str r3, [r7, #16]
- if (errorflags == 0U)
- 80049cc: 693b ldr r3, [r7, #16]
- 80049ce: 2b00 cmp r3, #0
- 80049d0: d113 bne.n 80049fa <HAL_UART_IRQHandler+0x56>
- {
- /* UART in mode Receiver ---------------------------------------------------*/
- if (((isrflags & USART_ISR_RXNE) != 0U)
- 80049d2: 69fb ldr r3, [r7, #28]
- 80049d4: f003 0320 and.w r3, r3, #32
- 80049d8: 2b00 cmp r3, #0
- 80049da: d00e beq.n 80049fa <HAL_UART_IRQHandler+0x56>
- && ((cr1its & USART_CR1_RXNEIE) != 0U))
- 80049dc: 69bb ldr r3, [r7, #24]
- 80049de: f003 0320 and.w r3, r3, #32
- 80049e2: 2b00 cmp r3, #0
- 80049e4: d009 beq.n 80049fa <HAL_UART_IRQHandler+0x56>
- {
- if (huart->RxISR != NULL)
- 80049e6: 687b ldr r3, [r7, #4]
- 80049e8: 6e1b ldr r3, [r3, #96] ; 0x60
- 80049ea: 2b00 cmp r3, #0
- 80049ec: f000 80eb beq.w 8004bc6 <HAL_UART_IRQHandler+0x222>
- {
- huart->RxISR(huart);
- 80049f0: 687b ldr r3, [r7, #4]
- 80049f2: 6e1b ldr r3, [r3, #96] ; 0x60
- 80049f4: 6878 ldr r0, [r7, #4]
- 80049f6: 4798 blx r3
- }
- return;
- 80049f8: e0e5 b.n 8004bc6 <HAL_UART_IRQHandler+0x222>
- }
- }
-
- /* If some errors occur */
- if ((errorflags != 0U)
- 80049fa: 693b ldr r3, [r7, #16]
- 80049fc: 2b00 cmp r3, #0
- 80049fe: f000 80c0 beq.w 8004b82 <HAL_UART_IRQHandler+0x1de>
- && (((cr3its & USART_CR3_EIE) != 0U)
- 8004a02: 697b ldr r3, [r7, #20]
- 8004a04: f003 0301 and.w r3, r3, #1
- 8004a08: 2b00 cmp r3, #0
- 8004a0a: d105 bne.n 8004a18 <HAL_UART_IRQHandler+0x74>
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
- 8004a0c: 69bb ldr r3, [r7, #24]
- 8004a0e: f403 7390 and.w r3, r3, #288 ; 0x120
- 8004a12: 2b00 cmp r3, #0
- 8004a14: f000 80b5 beq.w 8004b82 <HAL_UART_IRQHandler+0x1de>
- {
- /* UART parity error interrupt occurred -------------------------------------*/
- if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
- 8004a18: 69fb ldr r3, [r7, #28]
- 8004a1a: f003 0301 and.w r3, r3, #1
- 8004a1e: 2b00 cmp r3, #0
- 8004a20: d00e beq.n 8004a40 <HAL_UART_IRQHandler+0x9c>
- 8004a22: 69bb ldr r3, [r7, #24]
- 8004a24: f403 7380 and.w r3, r3, #256 ; 0x100
- 8004a28: 2b00 cmp r3, #0
- 8004a2a: d009 beq.n 8004a40 <HAL_UART_IRQHandler+0x9c>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
- 8004a2c: 687b ldr r3, [r7, #4]
- 8004a2e: 681b ldr r3, [r3, #0]
- 8004a30: 2201 movs r2, #1
- 8004a32: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_PE;
- 8004a34: 687b ldr r3, [r7, #4]
- 8004a36: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004a38: f043 0201 orr.w r2, r3, #1
- 8004a3c: 687b ldr r3, [r7, #4]
- 8004a3e: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* UART frame error interrupt occurred --------------------------------------*/
- if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
- 8004a40: 69fb ldr r3, [r7, #28]
- 8004a42: f003 0302 and.w r3, r3, #2
- 8004a46: 2b00 cmp r3, #0
- 8004a48: d00e beq.n 8004a68 <HAL_UART_IRQHandler+0xc4>
- 8004a4a: 697b ldr r3, [r7, #20]
- 8004a4c: f003 0301 and.w r3, r3, #1
- 8004a50: 2b00 cmp r3, #0
- 8004a52: d009 beq.n 8004a68 <HAL_UART_IRQHandler+0xc4>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
- 8004a54: 687b ldr r3, [r7, #4]
- 8004a56: 681b ldr r3, [r3, #0]
- 8004a58: 2202 movs r2, #2
- 8004a5a: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_FE;
- 8004a5c: 687b ldr r3, [r7, #4]
- 8004a5e: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004a60: f043 0204 orr.w r2, r3, #4
- 8004a64: 687b ldr r3, [r7, #4]
- 8004a66: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* UART noise error interrupt occurred --------------------------------------*/
- if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
- 8004a68: 69fb ldr r3, [r7, #28]
- 8004a6a: f003 0304 and.w r3, r3, #4
- 8004a6e: 2b00 cmp r3, #0
- 8004a70: d00e beq.n 8004a90 <HAL_UART_IRQHandler+0xec>
- 8004a72: 697b ldr r3, [r7, #20]
- 8004a74: f003 0301 and.w r3, r3, #1
- 8004a78: 2b00 cmp r3, #0
- 8004a7a: d009 beq.n 8004a90 <HAL_UART_IRQHandler+0xec>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
- 8004a7c: 687b ldr r3, [r7, #4]
- 8004a7e: 681b ldr r3, [r3, #0]
- 8004a80: 2204 movs r2, #4
- 8004a82: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_NE;
- 8004a84: 687b ldr r3, [r7, #4]
- 8004a86: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004a88: f043 0202 orr.w r2, r3, #2
- 8004a8c: 687b ldr r3, [r7, #4]
- 8004a8e: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* UART Over-Run interrupt occurred -----------------------------------------*/
- if (((isrflags & USART_ISR_ORE) != 0U)
- 8004a90: 69fb ldr r3, [r7, #28]
- 8004a92: f003 0308 and.w r3, r3, #8
- 8004a96: 2b00 cmp r3, #0
- 8004a98: d013 beq.n 8004ac2 <HAL_UART_IRQHandler+0x11e>
- && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
- 8004a9a: 69bb ldr r3, [r7, #24]
- 8004a9c: f003 0320 and.w r3, r3, #32
- 8004aa0: 2b00 cmp r3, #0
- 8004aa2: d104 bne.n 8004aae <HAL_UART_IRQHandler+0x10a>
- ((cr3its & USART_CR3_EIE) != 0U)))
- 8004aa4: 697b ldr r3, [r7, #20]
- 8004aa6: f003 0301 and.w r3, r3, #1
- && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
- 8004aaa: 2b00 cmp r3, #0
- 8004aac: d009 beq.n 8004ac2 <HAL_UART_IRQHandler+0x11e>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
- 8004aae: 687b ldr r3, [r7, #4]
- 8004ab0: 681b ldr r3, [r3, #0]
- 8004ab2: 2208 movs r2, #8
- 8004ab4: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_ORE;
- 8004ab6: 687b ldr r3, [r7, #4]
- 8004ab8: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004aba: f043 0208 orr.w r2, r3, #8
- 8004abe: 687b ldr r3, [r7, #4]
- 8004ac0: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* Call UART Error Call back function if need be --------------------------*/
- if (huart->ErrorCode != HAL_UART_ERROR_NONE)
- 8004ac2: 687b ldr r3, [r7, #4]
- 8004ac4: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004ac6: 2b00 cmp r3, #0
- 8004ac8: d07f beq.n 8004bca <HAL_UART_IRQHandler+0x226>
- {
- /* UART in mode Receiver ---------------------------------------------------*/
- if (((isrflags & USART_ISR_RXNE) != 0U)
- 8004aca: 69fb ldr r3, [r7, #28]
- 8004acc: f003 0320 and.w r3, r3, #32
- 8004ad0: 2b00 cmp r3, #0
- 8004ad2: d00c beq.n 8004aee <HAL_UART_IRQHandler+0x14a>
- && ((cr1its & USART_CR1_RXNEIE) != 0U))
- 8004ad4: 69bb ldr r3, [r7, #24]
- 8004ad6: f003 0320 and.w r3, r3, #32
- 8004ada: 2b00 cmp r3, #0
- 8004adc: d007 beq.n 8004aee <HAL_UART_IRQHandler+0x14a>
- {
- if (huart->RxISR != NULL)
- 8004ade: 687b ldr r3, [r7, #4]
- 8004ae0: 6e1b ldr r3, [r3, #96] ; 0x60
- 8004ae2: 2b00 cmp r3, #0
- 8004ae4: d003 beq.n 8004aee <HAL_UART_IRQHandler+0x14a>
- {
- huart->RxISR(huart);
- 8004ae6: 687b ldr r3, [r7, #4]
- 8004ae8: 6e1b ldr r3, [r3, #96] ; 0x60
- 8004aea: 6878 ldr r0, [r7, #4]
- 8004aec: 4798 blx r3
- }
- }
-
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- errorcode = huart->ErrorCode;
- 8004aee: 687b ldr r3, [r7, #4]
- 8004af0: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004af2: 60fb str r3, [r7, #12]
- if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
- 8004af4: 687b ldr r3, [r7, #4]
- 8004af6: 681b ldr r3, [r3, #0]
- 8004af8: 689b ldr r3, [r3, #8]
- 8004afa: f003 0340 and.w r3, r3, #64 ; 0x40
- 8004afe: 2b40 cmp r3, #64 ; 0x40
- 8004b00: d004 beq.n 8004b0c <HAL_UART_IRQHandler+0x168>
- ((errorcode & HAL_UART_ERROR_ORE) != 0U))
- 8004b02: 68fb ldr r3, [r7, #12]
- 8004b04: f003 0308 and.w r3, r3, #8
- if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
- 8004b08: 2b00 cmp r3, #0
- 8004b0a: d031 beq.n 8004b70 <HAL_UART_IRQHandler+0x1cc>
- {
- /* Blocking error : transfer is aborted
- Set the UART state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- UART_EndRxTransfer(huart);
- 8004b0c: 6878 ldr r0, [r7, #4]
- 8004b0e: f000 fc36 bl 800537e <UART_EndRxTransfer>
-
- /* Disable the UART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8004b12: 687b ldr r3, [r7, #4]
- 8004b14: 681b ldr r3, [r3, #0]
- 8004b16: 689b ldr r3, [r3, #8]
- 8004b18: f003 0340 and.w r3, r3, #64 ; 0x40
- 8004b1c: 2b40 cmp r3, #64 ; 0x40
- 8004b1e: d123 bne.n 8004b68 <HAL_UART_IRQHandler+0x1c4>
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- 8004b20: 687b ldr r3, [r7, #4]
- 8004b22: 681b ldr r3, [r3, #0]
- 8004b24: 689a ldr r2, [r3, #8]
- 8004b26: 687b ldr r3, [r7, #4]
- 8004b28: 681b ldr r3, [r3, #0]
- 8004b2a: f022 0240 bic.w r2, r2, #64 ; 0x40
- 8004b2e: 609a str r2, [r3, #8]
-
- /* Abort the UART DMA Rx channel */
- if (huart->hdmarx != NULL)
- 8004b30: 687b ldr r3, [r7, #4]
- 8004b32: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004b34: 2b00 cmp r3, #0
- 8004b36: d013 beq.n 8004b60 <HAL_UART_IRQHandler+0x1bc>
- {
- /* Set the UART DMA Abort callback :
- will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
- 8004b38: 687b ldr r3, [r7, #4]
- 8004b3a: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004b3c: 4a26 ldr r2, [pc, #152] ; (8004bd8 <HAL_UART_IRQHandler+0x234>)
- 8004b3e: 651a str r2, [r3, #80] ; 0x50
-
- /* Abort DMA RX */
- if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
- 8004b40: 687b ldr r3, [r7, #4]
- 8004b42: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004b44: 4618 mov r0, r3
- 8004b46: f7fd fa5c bl 8002002 <HAL_DMA_Abort_IT>
- 8004b4a: 4603 mov r3, r0
- 8004b4c: 2b00 cmp r3, #0
- 8004b4e: d016 beq.n 8004b7e <HAL_UART_IRQHandler+0x1da>
- {
- /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
- huart->hdmarx->XferAbortCallback(huart->hdmarx);
- 8004b50: 687b ldr r3, [r7, #4]
- 8004b52: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004b54: 6d1b ldr r3, [r3, #80] ; 0x50
- 8004b56: 687a ldr r2, [r7, #4]
- 8004b58: 6ed2 ldr r2, [r2, #108] ; 0x6c
- 8004b5a: 4610 mov r0, r2
- 8004b5c: 4798 blx r3
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8004b5e: e00e b.n 8004b7e <HAL_UART_IRQHandler+0x1da>
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 8004b60: 6878 ldr r0, [r7, #4]
- 8004b62: f000 f845 bl 8004bf0 <HAL_UART_ErrorCallback>
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8004b66: e00a b.n 8004b7e <HAL_UART_IRQHandler+0x1da>
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 8004b68: 6878 ldr r0, [r7, #4]
- 8004b6a: f000 f841 bl 8004bf0 <HAL_UART_ErrorCallback>
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8004b6e: e006 b.n 8004b7e <HAL_UART_IRQHandler+0x1da>
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 8004b70: 6878 ldr r0, [r7, #4]
- 8004b72: f000 f83d bl 8004bf0 <HAL_UART_ErrorCallback>
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8004b76: 687b ldr r3, [r7, #4]
- 8004b78: 2200 movs r2, #0
- 8004b7a: 67da str r2, [r3, #124] ; 0x7c
- }
- }
- return;
- 8004b7c: e025 b.n 8004bca <HAL_UART_IRQHandler+0x226>
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8004b7e: bf00 nop
- return;
- 8004b80: e023 b.n 8004bca <HAL_UART_IRQHandler+0x226>
-
- } /* End if some error occurs */
-
- /* UART in mode Transmitter ------------------------------------------------*/
- if (((isrflags & USART_ISR_TXE) != 0U)
- 8004b82: 69fb ldr r3, [r7, #28]
- 8004b84: f003 0380 and.w r3, r3, #128 ; 0x80
- 8004b88: 2b00 cmp r3, #0
- 8004b8a: d00d beq.n 8004ba8 <HAL_UART_IRQHandler+0x204>
- && ((cr1its & USART_CR1_TXEIE) != 0U))
- 8004b8c: 69bb ldr r3, [r7, #24]
- 8004b8e: f003 0380 and.w r3, r3, #128 ; 0x80
- 8004b92: 2b00 cmp r3, #0
- 8004b94: d008 beq.n 8004ba8 <HAL_UART_IRQHandler+0x204>
- {
- if (huart->TxISR != NULL)
- 8004b96: 687b ldr r3, [r7, #4]
- 8004b98: 6e5b ldr r3, [r3, #100] ; 0x64
- 8004b9a: 2b00 cmp r3, #0
- 8004b9c: d017 beq.n 8004bce <HAL_UART_IRQHandler+0x22a>
- {
- huart->TxISR(huart);
- 8004b9e: 687b ldr r3, [r7, #4]
- 8004ba0: 6e5b ldr r3, [r3, #100] ; 0x64
- 8004ba2: 6878 ldr r0, [r7, #4]
- 8004ba4: 4798 blx r3
- }
- return;
- 8004ba6: e012 b.n 8004bce <HAL_UART_IRQHandler+0x22a>
- }
-
- /* UART in mode Transmitter (transmission end) -----------------------------*/
- if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
- 8004ba8: 69fb ldr r3, [r7, #28]
- 8004baa: f003 0340 and.w r3, r3, #64 ; 0x40
- 8004bae: 2b00 cmp r3, #0
- 8004bb0: d00e beq.n 8004bd0 <HAL_UART_IRQHandler+0x22c>
- 8004bb2: 69bb ldr r3, [r7, #24]
- 8004bb4: f003 0340 and.w r3, r3, #64 ; 0x40
- 8004bb8: 2b00 cmp r3, #0
- 8004bba: d009 beq.n 8004bd0 <HAL_UART_IRQHandler+0x22c>
- {
- UART_EndTransmit_IT(huart);
- 8004bbc: 6878 ldr r0, [r7, #4]
- 8004bbe: f000 fc14 bl 80053ea <UART_EndTransmit_IT>
- return;
- 8004bc2: bf00 nop
- 8004bc4: e004 b.n 8004bd0 <HAL_UART_IRQHandler+0x22c>
- return;
- 8004bc6: bf00 nop
- 8004bc8: e002 b.n 8004bd0 <HAL_UART_IRQHandler+0x22c>
- return;
- 8004bca: bf00 nop
- 8004bcc: e000 b.n 8004bd0 <HAL_UART_IRQHandler+0x22c>
- return;
- 8004bce: bf00 nop
- }
-
-}
- 8004bd0: 3720 adds r7, #32
- 8004bd2: 46bd mov sp, r7
- 8004bd4: bd80 pop {r7, pc}
- 8004bd6: bf00 nop
- 8004bd8: 080053bf .word 0x080053bf
-
-08004bdc <HAL_UART_TxCpltCallback>:
- * @brief Tx Transfer completed callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
-{
- 8004bdc: b480 push {r7}
- 8004bde: b083 sub sp, #12
- 8004be0: af00 add r7, sp, #0
- 8004be2: 6078 str r0, [r7, #4]
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_TxCpltCallback can be implemented in the user file.
- */
-}
- 8004be4: bf00 nop
- 8004be6: 370c adds r7, #12
- 8004be8: 46bd mov sp, r7
- 8004bea: f85d 7b04 ldr.w r7, [sp], #4
- 8004bee: 4770 bx lr
-
-08004bf0 <HAL_UART_ErrorCallback>:
- * @brief UART error callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
-{
- 8004bf0: b480 push {r7}
- 8004bf2: b083 sub sp, #12
- 8004bf4: af00 add r7, sp, #0
- 8004bf6: 6078 str r0, [r7, #4]
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_ErrorCallback can be implemented in the user file.
- */
-}
- 8004bf8: bf00 nop
- 8004bfa: 370c adds r7, #12
- 8004bfc: 46bd mov sp, r7
- 8004bfe: f85d 7b04 ldr.w r7, [sp], #4
- 8004c02: 4770 bx lr
-
-08004c04 <UART_SetConfig>:
- * @brief Configure the UART peripheral.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
-{
- 8004c04: b580 push {r7, lr}
- 8004c06: b088 sub sp, #32
- 8004c08: af00 add r7, sp, #0
- 8004c0a: 6078 str r0, [r7, #4]
- uint32_t tmpreg;
- uint16_t brrtemp;
- UART_ClockSourceTypeDef clocksource;
- uint32_t usartdiv = 0x00000000U;
- 8004c0c: 2300 movs r3, #0
- 8004c0e: 61bb str r3, [r7, #24]
- HAL_StatusTypeDef ret = HAL_OK;
- 8004c10: 2300 movs r3, #0
- 8004c12: 75fb strb r3, [r7, #23]
- * the UART Word Length, Parity, Mode and oversampling:
- * set the M bits according to huart->Init.WordLength value
- * set PCE and PS bits according to huart->Init.Parity value
- * set TE and RE bits according to huart->Init.Mode value
- * set OVER8 bit according to huart->Init.OverSampling value */
- tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
- 8004c14: 687b ldr r3, [r7, #4]
- 8004c16: 689a ldr r2, [r3, #8]
- 8004c18: 687b ldr r3, [r7, #4]
- 8004c1a: 691b ldr r3, [r3, #16]
- 8004c1c: 431a orrs r2, r3
- 8004c1e: 687b ldr r3, [r7, #4]
- 8004c20: 695b ldr r3, [r3, #20]
- 8004c22: 431a orrs r2, r3
- 8004c24: 687b ldr r3, [r7, #4]
- 8004c26: 69db ldr r3, [r3, #28]
- 8004c28: 4313 orrs r3, r2
- 8004c2a: 613b str r3, [r7, #16]
- MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
- 8004c2c: 687b ldr r3, [r7, #4]
- 8004c2e: 681b ldr r3, [r3, #0]
- 8004c30: 681a ldr r2, [r3, #0]
- 8004c32: 4bb1 ldr r3, [pc, #708] ; (8004ef8 <UART_SetConfig+0x2f4>)
- 8004c34: 4013 ands r3, r2
- 8004c36: 687a ldr r2, [r7, #4]
- 8004c38: 6812 ldr r2, [r2, #0]
- 8004c3a: 6939 ldr r1, [r7, #16]
- 8004c3c: 430b orrs r3, r1
- 8004c3e: 6013 str r3, [r2, #0]
-
- /*-------------------------- USART CR2 Configuration -----------------------*/
- /* Configure the UART Stop Bits: Set STOP[13:12] bits according
- * to huart->Init.StopBits value */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
- 8004c40: 687b ldr r3, [r7, #4]
- 8004c42: 681b ldr r3, [r3, #0]
- 8004c44: 685b ldr r3, [r3, #4]
- 8004c46: f423 5140 bic.w r1, r3, #12288 ; 0x3000
- 8004c4a: 687b ldr r3, [r7, #4]
- 8004c4c: 68da ldr r2, [r3, #12]
- 8004c4e: 687b ldr r3, [r7, #4]
- 8004c50: 681b ldr r3, [r3, #0]
- 8004c52: 430a orrs r2, r1
- 8004c54: 605a str r2, [r3, #4]
- /* Configure
- * - UART HardWare Flow Control: set CTSE and RTSE bits according
- * to huart->Init.HwFlowCtl value
- * - one-bit sampling method versus three samples' majority rule according
- * to huart->Init.OneBitSampling (not applicable to LPUART) */
- tmpreg = (uint32_t)huart->Init.HwFlowCtl;
- 8004c56: 687b ldr r3, [r7, #4]
- 8004c58: 699b ldr r3, [r3, #24]
- 8004c5a: 613b str r3, [r7, #16]
-
- tmpreg |= huart->Init.OneBitSampling;
- 8004c5c: 687b ldr r3, [r7, #4]
- 8004c5e: 6a1b ldr r3, [r3, #32]
- 8004c60: 693a ldr r2, [r7, #16]
- 8004c62: 4313 orrs r3, r2
- 8004c64: 613b str r3, [r7, #16]
- MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
- 8004c66: 687b ldr r3, [r7, #4]
- 8004c68: 681b ldr r3, [r3, #0]
- 8004c6a: 689b ldr r3, [r3, #8]
- 8004c6c: f423 6130 bic.w r1, r3, #2816 ; 0xb00
- 8004c70: 687b ldr r3, [r7, #4]
- 8004c72: 681b ldr r3, [r3, #0]
- 8004c74: 693a ldr r2, [r7, #16]
- 8004c76: 430a orrs r2, r1
- 8004c78: 609a str r2, [r3, #8]
-
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- UART_GETCLOCKSOURCE(huart, clocksource);
- 8004c7a: 687b ldr r3, [r7, #4]
- 8004c7c: 681b ldr r3, [r3, #0]
- 8004c7e: 4a9f ldr r2, [pc, #636] ; (8004efc <UART_SetConfig+0x2f8>)
- 8004c80: 4293 cmp r3, r2
- 8004c82: d121 bne.n 8004cc8 <UART_SetConfig+0xc4>
- 8004c84: 4b9e ldr r3, [pc, #632] ; (8004f00 <UART_SetConfig+0x2fc>)
- 8004c86: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004c8a: f003 0303 and.w r3, r3, #3
- 8004c8e: 2b03 cmp r3, #3
- 8004c90: d816 bhi.n 8004cc0 <UART_SetConfig+0xbc>
- 8004c92: a201 add r2, pc, #4 ; (adr r2, 8004c98 <UART_SetConfig+0x94>)
- 8004c94: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8004c98: 08004ca9 .word 0x08004ca9
- 8004c9c: 08004cb5 .word 0x08004cb5
- 8004ca0: 08004caf .word 0x08004caf
- 8004ca4: 08004cbb .word 0x08004cbb
- 8004ca8: 2301 movs r3, #1
- 8004caa: 77fb strb r3, [r7, #31]
- 8004cac: e151 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004cae: 2302 movs r3, #2
- 8004cb0: 77fb strb r3, [r7, #31]
- 8004cb2: e14e b.n 8004f52 <UART_SetConfig+0x34e>
- 8004cb4: 2304 movs r3, #4
- 8004cb6: 77fb strb r3, [r7, #31]
- 8004cb8: e14b b.n 8004f52 <UART_SetConfig+0x34e>
- 8004cba: 2308 movs r3, #8
- 8004cbc: 77fb strb r3, [r7, #31]
- 8004cbe: e148 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004cc0: 2310 movs r3, #16
- 8004cc2: 77fb strb r3, [r7, #31]
- 8004cc4: bf00 nop
- 8004cc6: e144 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004cc8: 687b ldr r3, [r7, #4]
- 8004cca: 681b ldr r3, [r3, #0]
- 8004ccc: 4a8d ldr r2, [pc, #564] ; (8004f04 <UART_SetConfig+0x300>)
- 8004cce: 4293 cmp r3, r2
- 8004cd0: d134 bne.n 8004d3c <UART_SetConfig+0x138>
- 8004cd2: 4b8b ldr r3, [pc, #556] ; (8004f00 <UART_SetConfig+0x2fc>)
- 8004cd4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004cd8: f003 030c and.w r3, r3, #12
- 8004cdc: 2b0c cmp r3, #12
- 8004cde: d829 bhi.n 8004d34 <UART_SetConfig+0x130>
- 8004ce0: a201 add r2, pc, #4 ; (adr r2, 8004ce8 <UART_SetConfig+0xe4>)
- 8004ce2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8004ce6: bf00 nop
- 8004ce8: 08004d1d .word 0x08004d1d
- 8004cec: 08004d35 .word 0x08004d35
- 8004cf0: 08004d35 .word 0x08004d35
- 8004cf4: 08004d35 .word 0x08004d35
- 8004cf8: 08004d29 .word 0x08004d29
- 8004cfc: 08004d35 .word 0x08004d35
- 8004d00: 08004d35 .word 0x08004d35
- 8004d04: 08004d35 .word 0x08004d35
- 8004d08: 08004d23 .word 0x08004d23
- 8004d0c: 08004d35 .word 0x08004d35
- 8004d10: 08004d35 .word 0x08004d35
- 8004d14: 08004d35 .word 0x08004d35
- 8004d18: 08004d2f .word 0x08004d2f
- 8004d1c: 2300 movs r3, #0
- 8004d1e: 77fb strb r3, [r7, #31]
- 8004d20: e117 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004d22: 2302 movs r3, #2
- 8004d24: 77fb strb r3, [r7, #31]
- 8004d26: e114 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004d28: 2304 movs r3, #4
- 8004d2a: 77fb strb r3, [r7, #31]
- 8004d2c: e111 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004d2e: 2308 movs r3, #8
- 8004d30: 77fb strb r3, [r7, #31]
- 8004d32: e10e b.n 8004f52 <UART_SetConfig+0x34e>
- 8004d34: 2310 movs r3, #16
- 8004d36: 77fb strb r3, [r7, #31]
- 8004d38: bf00 nop
- 8004d3a: e10a b.n 8004f52 <UART_SetConfig+0x34e>
- 8004d3c: 687b ldr r3, [r7, #4]
- 8004d3e: 681b ldr r3, [r3, #0]
- 8004d40: 4a71 ldr r2, [pc, #452] ; (8004f08 <UART_SetConfig+0x304>)
- 8004d42: 4293 cmp r3, r2
- 8004d44: d120 bne.n 8004d88 <UART_SetConfig+0x184>
- 8004d46: 4b6e ldr r3, [pc, #440] ; (8004f00 <UART_SetConfig+0x2fc>)
- 8004d48: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004d4c: f003 0330 and.w r3, r3, #48 ; 0x30
- 8004d50: 2b10 cmp r3, #16
- 8004d52: d00f beq.n 8004d74 <UART_SetConfig+0x170>
- 8004d54: 2b10 cmp r3, #16
- 8004d56: d802 bhi.n 8004d5e <UART_SetConfig+0x15a>
- 8004d58: 2b00 cmp r3, #0
- 8004d5a: d005 beq.n 8004d68 <UART_SetConfig+0x164>
- 8004d5c: e010 b.n 8004d80 <UART_SetConfig+0x17c>
- 8004d5e: 2b20 cmp r3, #32
- 8004d60: d005 beq.n 8004d6e <UART_SetConfig+0x16a>
- 8004d62: 2b30 cmp r3, #48 ; 0x30
- 8004d64: d009 beq.n 8004d7a <UART_SetConfig+0x176>
- 8004d66: e00b b.n 8004d80 <UART_SetConfig+0x17c>
- 8004d68: 2300 movs r3, #0
- 8004d6a: 77fb strb r3, [r7, #31]
- 8004d6c: e0f1 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004d6e: 2302 movs r3, #2
- 8004d70: 77fb strb r3, [r7, #31]
- 8004d72: e0ee b.n 8004f52 <UART_SetConfig+0x34e>
- 8004d74: 2304 movs r3, #4
- 8004d76: 77fb strb r3, [r7, #31]
- 8004d78: e0eb b.n 8004f52 <UART_SetConfig+0x34e>
- 8004d7a: 2308 movs r3, #8
- 8004d7c: 77fb strb r3, [r7, #31]
- 8004d7e: e0e8 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004d80: 2310 movs r3, #16
- 8004d82: 77fb strb r3, [r7, #31]
- 8004d84: bf00 nop
- 8004d86: e0e4 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004d88: 687b ldr r3, [r7, #4]
- 8004d8a: 681b ldr r3, [r3, #0]
- 8004d8c: 4a5f ldr r2, [pc, #380] ; (8004f0c <UART_SetConfig+0x308>)
- 8004d8e: 4293 cmp r3, r2
- 8004d90: d120 bne.n 8004dd4 <UART_SetConfig+0x1d0>
- 8004d92: 4b5b ldr r3, [pc, #364] ; (8004f00 <UART_SetConfig+0x2fc>)
- 8004d94: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004d98: f003 03c0 and.w r3, r3, #192 ; 0xc0
- 8004d9c: 2b40 cmp r3, #64 ; 0x40
- 8004d9e: d00f beq.n 8004dc0 <UART_SetConfig+0x1bc>
- 8004da0: 2b40 cmp r3, #64 ; 0x40
- 8004da2: d802 bhi.n 8004daa <UART_SetConfig+0x1a6>
- 8004da4: 2b00 cmp r3, #0
- 8004da6: d005 beq.n 8004db4 <UART_SetConfig+0x1b0>
- 8004da8: e010 b.n 8004dcc <UART_SetConfig+0x1c8>
- 8004daa: 2b80 cmp r3, #128 ; 0x80
- 8004dac: d005 beq.n 8004dba <UART_SetConfig+0x1b6>
- 8004dae: 2bc0 cmp r3, #192 ; 0xc0
- 8004db0: d009 beq.n 8004dc6 <UART_SetConfig+0x1c2>
- 8004db2: e00b b.n 8004dcc <UART_SetConfig+0x1c8>
- 8004db4: 2300 movs r3, #0
- 8004db6: 77fb strb r3, [r7, #31]
- 8004db8: e0cb b.n 8004f52 <UART_SetConfig+0x34e>
- 8004dba: 2302 movs r3, #2
- 8004dbc: 77fb strb r3, [r7, #31]
- 8004dbe: e0c8 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004dc0: 2304 movs r3, #4
- 8004dc2: 77fb strb r3, [r7, #31]
- 8004dc4: e0c5 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004dc6: 2308 movs r3, #8
- 8004dc8: 77fb strb r3, [r7, #31]
- 8004dca: e0c2 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004dcc: 2310 movs r3, #16
- 8004dce: 77fb strb r3, [r7, #31]
- 8004dd0: bf00 nop
- 8004dd2: e0be b.n 8004f52 <UART_SetConfig+0x34e>
- 8004dd4: 687b ldr r3, [r7, #4]
- 8004dd6: 681b ldr r3, [r3, #0]
- 8004dd8: 4a4d ldr r2, [pc, #308] ; (8004f10 <UART_SetConfig+0x30c>)
- 8004dda: 4293 cmp r3, r2
- 8004ddc: d124 bne.n 8004e28 <UART_SetConfig+0x224>
- 8004dde: 4b48 ldr r3, [pc, #288] ; (8004f00 <UART_SetConfig+0x2fc>)
- 8004de0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004de4: f403 7340 and.w r3, r3, #768 ; 0x300
- 8004de8: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 8004dec: d012 beq.n 8004e14 <UART_SetConfig+0x210>
- 8004dee: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 8004df2: d802 bhi.n 8004dfa <UART_SetConfig+0x1f6>
- 8004df4: 2b00 cmp r3, #0
- 8004df6: d007 beq.n 8004e08 <UART_SetConfig+0x204>
- 8004df8: e012 b.n 8004e20 <UART_SetConfig+0x21c>
- 8004dfa: f5b3 7f00 cmp.w r3, #512 ; 0x200
- 8004dfe: d006 beq.n 8004e0e <UART_SetConfig+0x20a>
- 8004e00: f5b3 7f40 cmp.w r3, #768 ; 0x300
- 8004e04: d009 beq.n 8004e1a <UART_SetConfig+0x216>
- 8004e06: e00b b.n 8004e20 <UART_SetConfig+0x21c>
- 8004e08: 2300 movs r3, #0
- 8004e0a: 77fb strb r3, [r7, #31]
- 8004e0c: e0a1 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004e0e: 2302 movs r3, #2
- 8004e10: 77fb strb r3, [r7, #31]
- 8004e12: e09e b.n 8004f52 <UART_SetConfig+0x34e>
- 8004e14: 2304 movs r3, #4
- 8004e16: 77fb strb r3, [r7, #31]
- 8004e18: e09b b.n 8004f52 <UART_SetConfig+0x34e>
- 8004e1a: 2308 movs r3, #8
- 8004e1c: 77fb strb r3, [r7, #31]
- 8004e1e: e098 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004e20: 2310 movs r3, #16
- 8004e22: 77fb strb r3, [r7, #31]
- 8004e24: bf00 nop
- 8004e26: e094 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004e28: 687b ldr r3, [r7, #4]
- 8004e2a: 681b ldr r3, [r3, #0]
- 8004e2c: 4a39 ldr r2, [pc, #228] ; (8004f14 <UART_SetConfig+0x310>)
- 8004e2e: 4293 cmp r3, r2
- 8004e30: d124 bne.n 8004e7c <UART_SetConfig+0x278>
- 8004e32: 4b33 ldr r3, [pc, #204] ; (8004f00 <UART_SetConfig+0x2fc>)
- 8004e34: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004e38: f403 6340 and.w r3, r3, #3072 ; 0xc00
- 8004e3c: f5b3 6f80 cmp.w r3, #1024 ; 0x400
- 8004e40: d012 beq.n 8004e68 <UART_SetConfig+0x264>
- 8004e42: f5b3 6f80 cmp.w r3, #1024 ; 0x400
- 8004e46: d802 bhi.n 8004e4e <UART_SetConfig+0x24a>
- 8004e48: 2b00 cmp r3, #0
- 8004e4a: d007 beq.n 8004e5c <UART_SetConfig+0x258>
- 8004e4c: e012 b.n 8004e74 <UART_SetConfig+0x270>
- 8004e4e: f5b3 6f00 cmp.w r3, #2048 ; 0x800
- 8004e52: d006 beq.n 8004e62 <UART_SetConfig+0x25e>
- 8004e54: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
- 8004e58: d009 beq.n 8004e6e <UART_SetConfig+0x26a>
- 8004e5a: e00b b.n 8004e74 <UART_SetConfig+0x270>
- 8004e5c: 2301 movs r3, #1
- 8004e5e: 77fb strb r3, [r7, #31]
- 8004e60: e077 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004e62: 2302 movs r3, #2
- 8004e64: 77fb strb r3, [r7, #31]
- 8004e66: e074 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004e68: 2304 movs r3, #4
- 8004e6a: 77fb strb r3, [r7, #31]
- 8004e6c: e071 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004e6e: 2308 movs r3, #8
- 8004e70: 77fb strb r3, [r7, #31]
- 8004e72: e06e b.n 8004f52 <UART_SetConfig+0x34e>
- 8004e74: 2310 movs r3, #16
- 8004e76: 77fb strb r3, [r7, #31]
- 8004e78: bf00 nop
- 8004e7a: e06a b.n 8004f52 <UART_SetConfig+0x34e>
- 8004e7c: 687b ldr r3, [r7, #4]
- 8004e7e: 681b ldr r3, [r3, #0]
- 8004e80: 4a25 ldr r2, [pc, #148] ; (8004f18 <UART_SetConfig+0x314>)
- 8004e82: 4293 cmp r3, r2
- 8004e84: d124 bne.n 8004ed0 <UART_SetConfig+0x2cc>
- 8004e86: 4b1e ldr r3, [pc, #120] ; (8004f00 <UART_SetConfig+0x2fc>)
- 8004e88: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004e8c: f403 5340 and.w r3, r3, #12288 ; 0x3000
- 8004e90: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8004e94: d012 beq.n 8004ebc <UART_SetConfig+0x2b8>
- 8004e96: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8004e9a: d802 bhi.n 8004ea2 <UART_SetConfig+0x29e>
- 8004e9c: 2b00 cmp r3, #0
- 8004e9e: d007 beq.n 8004eb0 <UART_SetConfig+0x2ac>
- 8004ea0: e012 b.n 8004ec8 <UART_SetConfig+0x2c4>
- 8004ea2: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 8004ea6: d006 beq.n 8004eb6 <UART_SetConfig+0x2b2>
- 8004ea8: f5b3 5f40 cmp.w r3, #12288 ; 0x3000
- 8004eac: d009 beq.n 8004ec2 <UART_SetConfig+0x2be>
- 8004eae: e00b b.n 8004ec8 <UART_SetConfig+0x2c4>
- 8004eb0: 2300 movs r3, #0
- 8004eb2: 77fb strb r3, [r7, #31]
- 8004eb4: e04d b.n 8004f52 <UART_SetConfig+0x34e>
- 8004eb6: 2302 movs r3, #2
- 8004eb8: 77fb strb r3, [r7, #31]
- 8004eba: e04a b.n 8004f52 <UART_SetConfig+0x34e>
- 8004ebc: 2304 movs r3, #4
- 8004ebe: 77fb strb r3, [r7, #31]
- 8004ec0: e047 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004ec2: 2308 movs r3, #8
- 8004ec4: 77fb strb r3, [r7, #31]
- 8004ec6: e044 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004ec8: 2310 movs r3, #16
- 8004eca: 77fb strb r3, [r7, #31]
- 8004ecc: bf00 nop
- 8004ece: e040 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004ed0: 687b ldr r3, [r7, #4]
- 8004ed2: 681b ldr r3, [r3, #0]
- 8004ed4: 4a11 ldr r2, [pc, #68] ; (8004f1c <UART_SetConfig+0x318>)
- 8004ed6: 4293 cmp r3, r2
- 8004ed8: d139 bne.n 8004f4e <UART_SetConfig+0x34a>
- 8004eda: 4b09 ldr r3, [pc, #36] ; (8004f00 <UART_SetConfig+0x2fc>)
- 8004edc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004ee0: f403 4340 and.w r3, r3, #49152 ; 0xc000
- 8004ee4: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
- 8004ee8: d027 beq.n 8004f3a <UART_SetConfig+0x336>
- 8004eea: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
- 8004eee: d817 bhi.n 8004f20 <UART_SetConfig+0x31c>
- 8004ef0: 2b00 cmp r3, #0
- 8004ef2: d01c beq.n 8004f2e <UART_SetConfig+0x32a>
- 8004ef4: e027 b.n 8004f46 <UART_SetConfig+0x342>
- 8004ef6: bf00 nop
- 8004ef8: efff69f3 .word 0xefff69f3
- 8004efc: 40011000 .word 0x40011000
- 8004f00: 40023800 .word 0x40023800
- 8004f04: 40004400 .word 0x40004400
- 8004f08: 40004800 .word 0x40004800
- 8004f0c: 40004c00 .word 0x40004c00
- 8004f10: 40005000 .word 0x40005000
- 8004f14: 40011400 .word 0x40011400
- 8004f18: 40007800 .word 0x40007800
- 8004f1c: 40007c00 .word 0x40007c00
- 8004f20: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
- 8004f24: d006 beq.n 8004f34 <UART_SetConfig+0x330>
- 8004f26: f5b3 4f40 cmp.w r3, #49152 ; 0xc000
- 8004f2a: d009 beq.n 8004f40 <UART_SetConfig+0x33c>
- 8004f2c: e00b b.n 8004f46 <UART_SetConfig+0x342>
- 8004f2e: 2300 movs r3, #0
- 8004f30: 77fb strb r3, [r7, #31]
- 8004f32: e00e b.n 8004f52 <UART_SetConfig+0x34e>
- 8004f34: 2302 movs r3, #2
- 8004f36: 77fb strb r3, [r7, #31]
- 8004f38: e00b b.n 8004f52 <UART_SetConfig+0x34e>
- 8004f3a: 2304 movs r3, #4
- 8004f3c: 77fb strb r3, [r7, #31]
- 8004f3e: e008 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004f40: 2308 movs r3, #8
- 8004f42: 77fb strb r3, [r7, #31]
- 8004f44: e005 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004f46: 2310 movs r3, #16
- 8004f48: 77fb strb r3, [r7, #31]
- 8004f4a: bf00 nop
- 8004f4c: e001 b.n 8004f52 <UART_SetConfig+0x34e>
- 8004f4e: 2310 movs r3, #16
- 8004f50: 77fb strb r3, [r7, #31]
-
- if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
- 8004f52: 687b ldr r3, [r7, #4]
- 8004f54: 69db ldr r3, [r3, #28]
- 8004f56: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
- 8004f5a: d17c bne.n 8005056 <UART_SetConfig+0x452>
- {
- switch (clocksource)
- 8004f5c: 7ffb ldrb r3, [r7, #31]
- 8004f5e: 2b08 cmp r3, #8
- 8004f60: d859 bhi.n 8005016 <UART_SetConfig+0x412>
- 8004f62: a201 add r2, pc, #4 ; (adr r2, 8004f68 <UART_SetConfig+0x364>)
- 8004f64: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8004f68: 08004f8d .word 0x08004f8d
- 8004f6c: 08004fab .word 0x08004fab
- 8004f70: 08004fc9 .word 0x08004fc9
- 8004f74: 08005017 .word 0x08005017
- 8004f78: 08004fe1 .word 0x08004fe1
- 8004f7c: 08005017 .word 0x08005017
- 8004f80: 08005017 .word 0x08005017
- 8004f84: 08005017 .word 0x08005017
- 8004f88: 08004fff .word 0x08004fff
- {
- case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- 8004f8c: f7fd fe50 bl 8002c30 <HAL_RCC_GetPCLK1Freq>
- 8004f90: 4603 mov r3, r0
- 8004f92: 005a lsls r2, r3, #1
- 8004f94: 687b ldr r3, [r7, #4]
- 8004f96: 685b ldr r3, [r3, #4]
- 8004f98: 085b lsrs r3, r3, #1
- 8004f9a: 441a add r2, r3
- 8004f9c: 687b ldr r3, [r7, #4]
- 8004f9e: 685b ldr r3, [r3, #4]
- 8004fa0: fbb2 f3f3 udiv r3, r2, r3
- 8004fa4: b29b uxth r3, r3
- 8004fa6: 61bb str r3, [r7, #24]
- break;
- 8004fa8: e038 b.n 800501c <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- 8004faa: f7fd fe55 bl 8002c58 <HAL_RCC_GetPCLK2Freq>
- 8004fae: 4603 mov r3, r0
- 8004fb0: 005a lsls r2, r3, #1
- 8004fb2: 687b ldr r3, [r7, #4]
- 8004fb4: 685b ldr r3, [r3, #4]
- 8004fb6: 085b lsrs r3, r3, #1
- 8004fb8: 441a add r2, r3
- 8004fba: 687b ldr r3, [r7, #4]
- 8004fbc: 685b ldr r3, [r3, #4]
- 8004fbe: fbb2 f3f3 udiv r3, r2, r3
- 8004fc2: b29b uxth r3, r3
- 8004fc4: 61bb str r3, [r7, #24]
- break;
- 8004fc6: e029 b.n 800501c <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
- 8004fc8: 687b ldr r3, [r7, #4]
- 8004fca: 685b ldr r3, [r3, #4]
- 8004fcc: 085a lsrs r2, r3, #1
- 8004fce: 4b5d ldr r3, [pc, #372] ; (8005144 <UART_SetConfig+0x540>)
- 8004fd0: 4413 add r3, r2
- 8004fd2: 687a ldr r2, [r7, #4]
- 8004fd4: 6852 ldr r2, [r2, #4]
- 8004fd6: fbb3 f3f2 udiv r3, r3, r2
- 8004fda: b29b uxth r3, r3
- 8004fdc: 61bb str r3, [r7, #24]
- break;
- 8004fde: e01d b.n 800501c <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- 8004fe0: f7fd fd68 bl 8002ab4 <HAL_RCC_GetSysClockFreq>
- 8004fe4: 4603 mov r3, r0
- 8004fe6: 005a lsls r2, r3, #1
- 8004fe8: 687b ldr r3, [r7, #4]
- 8004fea: 685b ldr r3, [r3, #4]
- 8004fec: 085b lsrs r3, r3, #1
- 8004fee: 441a add r2, r3
- 8004ff0: 687b ldr r3, [r7, #4]
- 8004ff2: 685b ldr r3, [r3, #4]
- 8004ff4: fbb2 f3f3 udiv r3, r2, r3
- 8004ff8: b29b uxth r3, r3
- 8004ffa: 61bb str r3, [r7, #24]
- break;
- 8004ffc: e00e b.n 800501c <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
- 8004ffe: 687b ldr r3, [r7, #4]
- 8005000: 685b ldr r3, [r3, #4]
- 8005002: 085b lsrs r3, r3, #1
- 8005004: f503 3280 add.w r2, r3, #65536 ; 0x10000
- 8005008: 687b ldr r3, [r7, #4]
- 800500a: 685b ldr r3, [r3, #4]
- 800500c: fbb2 f3f3 udiv r3, r2, r3
- 8005010: b29b uxth r3, r3
- 8005012: 61bb str r3, [r7, #24]
- break;
- 8005014: e002 b.n 800501c <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- 8005016: 2301 movs r3, #1
- 8005018: 75fb strb r3, [r7, #23]
- break;
- 800501a: bf00 nop
- }
-
- /* USARTDIV must be greater than or equal to 0d16 */
- if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 800501c: 69bb ldr r3, [r7, #24]
- 800501e: 2b0f cmp r3, #15
- 8005020: d916 bls.n 8005050 <UART_SetConfig+0x44c>
- 8005022: 69bb ldr r3, [r7, #24]
- 8005024: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8005028: d212 bcs.n 8005050 <UART_SetConfig+0x44c>
- {
- brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
- 800502a: 69bb ldr r3, [r7, #24]
- 800502c: b29b uxth r3, r3
- 800502e: f023 030f bic.w r3, r3, #15
- 8005032: 81fb strh r3, [r7, #14]
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- 8005034: 69bb ldr r3, [r7, #24]
- 8005036: 085b lsrs r3, r3, #1
- 8005038: b29b uxth r3, r3
- 800503a: f003 0307 and.w r3, r3, #7
- 800503e: b29a uxth r2, r3
- 8005040: 89fb ldrh r3, [r7, #14]
- 8005042: 4313 orrs r3, r2
- 8005044: 81fb strh r3, [r7, #14]
- huart->Instance->BRR = brrtemp;
- 8005046: 687b ldr r3, [r7, #4]
- 8005048: 681b ldr r3, [r3, #0]
- 800504a: 89fa ldrh r2, [r7, #14]
- 800504c: 60da str r2, [r3, #12]
- 800504e: e06e b.n 800512e <UART_SetConfig+0x52a>
- }
- else
- {
- ret = HAL_ERROR;
- 8005050: 2301 movs r3, #1
- 8005052: 75fb strb r3, [r7, #23]
- 8005054: e06b b.n 800512e <UART_SetConfig+0x52a>
- }
- }
- else
- {
- switch (clocksource)
- 8005056: 7ffb ldrb r3, [r7, #31]
- 8005058: 2b08 cmp r3, #8
- 800505a: d857 bhi.n 800510c <UART_SetConfig+0x508>
- 800505c: a201 add r2, pc, #4 ; (adr r2, 8005064 <UART_SetConfig+0x460>)
- 800505e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8005062: bf00 nop
- 8005064: 08005089 .word 0x08005089
- 8005068: 080050a5 .word 0x080050a5
- 800506c: 080050c1 .word 0x080050c1
- 8005070: 0800510d .word 0x0800510d
- 8005074: 080050d9 .word 0x080050d9
- 8005078: 0800510d .word 0x0800510d
- 800507c: 0800510d .word 0x0800510d
- 8005080: 0800510d .word 0x0800510d
- 8005084: 080050f5 .word 0x080050f5
- {
- case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- 8005088: f7fd fdd2 bl 8002c30 <HAL_RCC_GetPCLK1Freq>
- 800508c: 4602 mov r2, r0
- 800508e: 687b ldr r3, [r7, #4]
- 8005090: 685b ldr r3, [r3, #4]
- 8005092: 085b lsrs r3, r3, #1
- 8005094: 441a add r2, r3
- 8005096: 687b ldr r3, [r7, #4]
- 8005098: 685b ldr r3, [r3, #4]
- 800509a: fbb2 f3f3 udiv r3, r2, r3
- 800509e: b29b uxth r3, r3
- 80050a0: 61bb str r3, [r7, #24]
- break;
- 80050a2: e036 b.n 8005112 <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- 80050a4: f7fd fdd8 bl 8002c58 <HAL_RCC_GetPCLK2Freq>
- 80050a8: 4602 mov r2, r0
- 80050aa: 687b ldr r3, [r7, #4]
- 80050ac: 685b ldr r3, [r3, #4]
- 80050ae: 085b lsrs r3, r3, #1
- 80050b0: 441a add r2, r3
- 80050b2: 687b ldr r3, [r7, #4]
- 80050b4: 685b ldr r3, [r3, #4]
- 80050b6: fbb2 f3f3 udiv r3, r2, r3
- 80050ba: b29b uxth r3, r3
- 80050bc: 61bb str r3, [r7, #24]
- break;
- 80050be: e028 b.n 8005112 <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
- 80050c0: 687b ldr r3, [r7, #4]
- 80050c2: 685b ldr r3, [r3, #4]
- 80050c4: 085a lsrs r2, r3, #1
- 80050c6: 4b20 ldr r3, [pc, #128] ; (8005148 <UART_SetConfig+0x544>)
- 80050c8: 4413 add r3, r2
- 80050ca: 687a ldr r2, [r7, #4]
- 80050cc: 6852 ldr r2, [r2, #4]
- 80050ce: fbb3 f3f2 udiv r3, r3, r2
- 80050d2: b29b uxth r3, r3
- 80050d4: 61bb str r3, [r7, #24]
- break;
- 80050d6: e01c b.n 8005112 <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- 80050d8: f7fd fcec bl 8002ab4 <HAL_RCC_GetSysClockFreq>
- 80050dc: 4602 mov r2, r0
- 80050de: 687b ldr r3, [r7, #4]
- 80050e0: 685b ldr r3, [r3, #4]
- 80050e2: 085b lsrs r3, r3, #1
- 80050e4: 441a add r2, r3
- 80050e6: 687b ldr r3, [r7, #4]
- 80050e8: 685b ldr r3, [r3, #4]
- 80050ea: fbb2 f3f3 udiv r3, r2, r3
- 80050ee: b29b uxth r3, r3
- 80050f0: 61bb str r3, [r7, #24]
- break;
- 80050f2: e00e b.n 8005112 <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
- 80050f4: 687b ldr r3, [r7, #4]
- 80050f6: 685b ldr r3, [r3, #4]
- 80050f8: 085b lsrs r3, r3, #1
- 80050fa: f503 4200 add.w r2, r3, #32768 ; 0x8000
- 80050fe: 687b ldr r3, [r7, #4]
- 8005100: 685b ldr r3, [r3, #4]
- 8005102: fbb2 f3f3 udiv r3, r2, r3
- 8005106: b29b uxth r3, r3
- 8005108: 61bb str r3, [r7, #24]
- break;
- 800510a: e002 b.n 8005112 <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- 800510c: 2301 movs r3, #1
- 800510e: 75fb strb r3, [r7, #23]
- break;
- 8005110: bf00 nop
- }
-
- /* USARTDIV must be greater than or equal to 0d16 */
- if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 8005112: 69bb ldr r3, [r7, #24]
- 8005114: 2b0f cmp r3, #15
- 8005116: d908 bls.n 800512a <UART_SetConfig+0x526>
- 8005118: 69bb ldr r3, [r7, #24]
- 800511a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 800511e: d204 bcs.n 800512a <UART_SetConfig+0x526>
- {
- huart->Instance->BRR = usartdiv;
- 8005120: 687b ldr r3, [r7, #4]
- 8005122: 681b ldr r3, [r3, #0]
- 8005124: 69ba ldr r2, [r7, #24]
- 8005126: 60da str r2, [r3, #12]
- 8005128: e001 b.n 800512e <UART_SetConfig+0x52a>
- }
- else
- {
- ret = HAL_ERROR;
- 800512a: 2301 movs r3, #1
- 800512c: 75fb strb r3, [r7, #23]
- }
- }
-
-
- /* Clear ISR function pointers */
- huart->RxISR = NULL;
- 800512e: 687b ldr r3, [r7, #4]
- 8005130: 2200 movs r2, #0
- 8005132: 661a str r2, [r3, #96] ; 0x60
- huart->TxISR = NULL;
- 8005134: 687b ldr r3, [r7, #4]
- 8005136: 2200 movs r2, #0
- 8005138: 665a str r2, [r3, #100] ; 0x64
-
- return ret;
- 800513a: 7dfb ldrb r3, [r7, #23]
-}
- 800513c: 4618 mov r0, r3
- 800513e: 3720 adds r7, #32
- 8005140: 46bd mov sp, r7
- 8005142: bd80 pop {r7, pc}
- 8005144: 01e84800 .word 0x01e84800
- 8005148: 00f42400 .word 0x00f42400
-
-0800514c <UART_AdvFeatureConfig>:
- * @brief Configure the UART peripheral advanced features.
- * @param huart UART handle.
- * @retval None
- */
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
-{
- 800514c: b480 push {r7}
- 800514e: b083 sub sp, #12
- 8005150: af00 add r7, sp, #0
- 8005152: 6078 str r0, [r7, #4]
- /* Check whether the set of advanced features to configure is properly set */
- assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
-
- /* if required, configure TX pin active level inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
- 8005154: 687b ldr r3, [r7, #4]
- 8005156: 6a5b ldr r3, [r3, #36] ; 0x24
- 8005158: f003 0301 and.w r3, r3, #1
- 800515c: 2b00 cmp r3, #0
- 800515e: d00a beq.n 8005176 <UART_AdvFeatureConfig+0x2a>
- {
- assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
- 8005160: 687b ldr r3, [r7, #4]
- 8005162: 681b ldr r3, [r3, #0]
- 8005164: 685b ldr r3, [r3, #4]
- 8005166: f423 3100 bic.w r1, r3, #131072 ; 0x20000
- 800516a: 687b ldr r3, [r7, #4]
- 800516c: 6a9a ldr r2, [r3, #40] ; 0x28
- 800516e: 687b ldr r3, [r7, #4]
- 8005170: 681b ldr r3, [r3, #0]
- 8005172: 430a orrs r2, r1
- 8005174: 605a str r2, [r3, #4]
- }
-
- /* if required, configure RX pin active level inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
- 8005176: 687b ldr r3, [r7, #4]
- 8005178: 6a5b ldr r3, [r3, #36] ; 0x24
- 800517a: f003 0302 and.w r3, r3, #2
- 800517e: 2b00 cmp r3, #0
- 8005180: d00a beq.n 8005198 <UART_AdvFeatureConfig+0x4c>
- {
- assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
- 8005182: 687b ldr r3, [r7, #4]
- 8005184: 681b ldr r3, [r3, #0]
- 8005186: 685b ldr r3, [r3, #4]
- 8005188: f423 3180 bic.w r1, r3, #65536 ; 0x10000
- 800518c: 687b ldr r3, [r7, #4]
- 800518e: 6ada ldr r2, [r3, #44] ; 0x2c
- 8005190: 687b ldr r3, [r7, #4]
- 8005192: 681b ldr r3, [r3, #0]
- 8005194: 430a orrs r2, r1
- 8005196: 605a str r2, [r3, #4]
- }
-
- /* if required, configure data inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
- 8005198: 687b ldr r3, [r7, #4]
- 800519a: 6a5b ldr r3, [r3, #36] ; 0x24
- 800519c: f003 0304 and.w r3, r3, #4
- 80051a0: 2b00 cmp r3, #0
- 80051a2: d00a beq.n 80051ba <UART_AdvFeatureConfig+0x6e>
- {
- assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
- 80051a4: 687b ldr r3, [r7, #4]
- 80051a6: 681b ldr r3, [r3, #0]
- 80051a8: 685b ldr r3, [r3, #4]
- 80051aa: f423 2180 bic.w r1, r3, #262144 ; 0x40000
- 80051ae: 687b ldr r3, [r7, #4]
- 80051b0: 6b1a ldr r2, [r3, #48] ; 0x30
- 80051b2: 687b ldr r3, [r7, #4]
- 80051b4: 681b ldr r3, [r3, #0]
- 80051b6: 430a orrs r2, r1
- 80051b8: 605a str r2, [r3, #4]
- }
-
- /* if required, configure RX/TX pins swap */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
- 80051ba: 687b ldr r3, [r7, #4]
- 80051bc: 6a5b ldr r3, [r3, #36] ; 0x24
- 80051be: f003 0308 and.w r3, r3, #8
- 80051c2: 2b00 cmp r3, #0
- 80051c4: d00a beq.n 80051dc <UART_AdvFeatureConfig+0x90>
- {
- assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
- 80051c6: 687b ldr r3, [r7, #4]
- 80051c8: 681b ldr r3, [r3, #0]
- 80051ca: 685b ldr r3, [r3, #4]
- 80051cc: f423 4100 bic.w r1, r3, #32768 ; 0x8000
- 80051d0: 687b ldr r3, [r7, #4]
- 80051d2: 6b5a ldr r2, [r3, #52] ; 0x34
- 80051d4: 687b ldr r3, [r7, #4]
- 80051d6: 681b ldr r3, [r3, #0]
- 80051d8: 430a orrs r2, r1
- 80051da: 605a str r2, [r3, #4]
- }
-
- /* if required, configure RX overrun detection disabling */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
- 80051dc: 687b ldr r3, [r7, #4]
- 80051de: 6a5b ldr r3, [r3, #36] ; 0x24
- 80051e0: f003 0310 and.w r3, r3, #16
- 80051e4: 2b00 cmp r3, #0
- 80051e6: d00a beq.n 80051fe <UART_AdvFeatureConfig+0xb2>
- {
- assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
- 80051e8: 687b ldr r3, [r7, #4]
- 80051ea: 681b ldr r3, [r3, #0]
- 80051ec: 689b ldr r3, [r3, #8]
- 80051ee: f423 5180 bic.w r1, r3, #4096 ; 0x1000
- 80051f2: 687b ldr r3, [r7, #4]
- 80051f4: 6b9a ldr r2, [r3, #56] ; 0x38
- 80051f6: 687b ldr r3, [r7, #4]
- 80051f8: 681b ldr r3, [r3, #0]
- 80051fa: 430a orrs r2, r1
- 80051fc: 609a str r2, [r3, #8]
- }
-
- /* if required, configure DMA disabling on reception error */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
- 80051fe: 687b ldr r3, [r7, #4]
- 8005200: 6a5b ldr r3, [r3, #36] ; 0x24
- 8005202: f003 0320 and.w r3, r3, #32
- 8005206: 2b00 cmp r3, #0
- 8005208: d00a beq.n 8005220 <UART_AdvFeatureConfig+0xd4>
- {
- assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
- 800520a: 687b ldr r3, [r7, #4]
- 800520c: 681b ldr r3, [r3, #0]
- 800520e: 689b ldr r3, [r3, #8]
- 8005210: f423 5100 bic.w r1, r3, #8192 ; 0x2000
- 8005214: 687b ldr r3, [r7, #4]
- 8005216: 6bda ldr r2, [r3, #60] ; 0x3c
- 8005218: 687b ldr r3, [r7, #4]
- 800521a: 681b ldr r3, [r3, #0]
- 800521c: 430a orrs r2, r1
- 800521e: 609a str r2, [r3, #8]
- }
-
- /* if required, configure auto Baud rate detection scheme */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
- 8005220: 687b ldr r3, [r7, #4]
- 8005222: 6a5b ldr r3, [r3, #36] ; 0x24
- 8005224: f003 0340 and.w r3, r3, #64 ; 0x40
- 8005228: 2b00 cmp r3, #0
- 800522a: d01a beq.n 8005262 <UART_AdvFeatureConfig+0x116>
- {
- assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
- 800522c: 687b ldr r3, [r7, #4]
- 800522e: 681b ldr r3, [r3, #0]
- 8005230: 685b ldr r3, [r3, #4]
- 8005232: f423 1180 bic.w r1, r3, #1048576 ; 0x100000
- 8005236: 687b ldr r3, [r7, #4]
- 8005238: 6c1a ldr r2, [r3, #64] ; 0x40
- 800523a: 687b ldr r3, [r7, #4]
- 800523c: 681b ldr r3, [r3, #0]
- 800523e: 430a orrs r2, r1
- 8005240: 605a str r2, [r3, #4]
- /* set auto Baudrate detection parameters if detection is enabled */
- if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
- 8005242: 687b ldr r3, [r7, #4]
- 8005244: 6c1b ldr r3, [r3, #64] ; 0x40
- 8005246: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 800524a: d10a bne.n 8005262 <UART_AdvFeatureConfig+0x116>
- {
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
- 800524c: 687b ldr r3, [r7, #4]
- 800524e: 681b ldr r3, [r3, #0]
- 8005250: 685b ldr r3, [r3, #4]
- 8005252: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000
- 8005256: 687b ldr r3, [r7, #4]
- 8005258: 6c5a ldr r2, [r3, #68] ; 0x44
- 800525a: 687b ldr r3, [r7, #4]
- 800525c: 681b ldr r3, [r3, #0]
- 800525e: 430a orrs r2, r1
- 8005260: 605a str r2, [r3, #4]
- }
- }
-
- /* if required, configure MSB first on communication line */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
- 8005262: 687b ldr r3, [r7, #4]
- 8005264: 6a5b ldr r3, [r3, #36] ; 0x24
- 8005266: f003 0380 and.w r3, r3, #128 ; 0x80
- 800526a: 2b00 cmp r3, #0
- 800526c: d00a beq.n 8005284 <UART_AdvFeatureConfig+0x138>
- {
- assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
- 800526e: 687b ldr r3, [r7, #4]
- 8005270: 681b ldr r3, [r3, #0]
- 8005272: 685b ldr r3, [r3, #4]
- 8005274: f423 2100 bic.w r1, r3, #524288 ; 0x80000
- 8005278: 687b ldr r3, [r7, #4]
- 800527a: 6c9a ldr r2, [r3, #72] ; 0x48
- 800527c: 687b ldr r3, [r7, #4]
- 800527e: 681b ldr r3, [r3, #0]
- 8005280: 430a orrs r2, r1
- 8005282: 605a str r2, [r3, #4]
- }
-}
- 8005284: bf00 nop
- 8005286: 370c adds r7, #12
- 8005288: 46bd mov sp, r7
- 800528a: f85d 7b04 ldr.w r7, [sp], #4
- 800528e: 4770 bx lr
-
-08005290 <UART_CheckIdleState>:
- * @brief Check the UART Idle State.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
-{
- 8005290: b580 push {r7, lr}
- 8005292: b086 sub sp, #24
- 8005294: af02 add r7, sp, #8
- 8005296: 6078 str r0, [r7, #4]
- uint32_t tickstart;
-
- /* Initialize the UART ErrorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8005298: 687b ldr r3, [r7, #4]
- 800529a: 2200 movs r2, #0
- 800529c: 67da str r2, [r3, #124] ; 0x7c
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
- 800529e: f7fc fd93 bl 8001dc8 <HAL_GetTick>
- 80052a2: 60f8 str r0, [r7, #12]
-
- /* Check if the Transmitter is enabled */
- if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- 80052a4: 687b ldr r3, [r7, #4]
- 80052a6: 681b ldr r3, [r3, #0]
- 80052a8: 681b ldr r3, [r3, #0]
- 80052aa: f003 0308 and.w r3, r3, #8
- 80052ae: 2b08 cmp r3, #8
- 80052b0: d10e bne.n 80052d0 <UART_CheckIdleState+0x40>
- {
- /* Wait until TEACK flag is set */
- if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- 80052b2: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
- 80052b6: 9300 str r3, [sp, #0]
- 80052b8: 68fb ldr r3, [r7, #12]
- 80052ba: 2200 movs r2, #0
- 80052bc: f44f 1100 mov.w r1, #2097152 ; 0x200000
- 80052c0: 6878 ldr r0, [r7, #4]
- 80052c2: f000 f814 bl 80052ee <UART_WaitOnFlagUntilTimeout>
- 80052c6: 4603 mov r3, r0
- 80052c8: 2b00 cmp r3, #0
- 80052ca: d001 beq.n 80052d0 <UART_CheckIdleState+0x40>
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- 80052cc: 2303 movs r3, #3
- 80052ce: e00a b.n 80052e6 <UART_CheckIdleState+0x56>
- }
- }
-
- /* Initialize the UART State */
- huart->gState = HAL_UART_STATE_READY;
- 80052d0: 687b ldr r3, [r7, #4]
- 80052d2: 2220 movs r2, #32
- 80052d4: 675a str r2, [r3, #116] ; 0x74
- huart->RxState = HAL_UART_STATE_READY;
- 80052d6: 687b ldr r3, [r7, #4]
- 80052d8: 2220 movs r2, #32
- 80052da: 679a str r2, [r3, #120] ; 0x78
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 80052dc: 687b ldr r3, [r7, #4]
- 80052de: 2200 movs r2, #0
- 80052e0: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- return HAL_OK;
- 80052e4: 2300 movs r3, #0
-}
- 80052e6: 4618 mov r0, r3
- 80052e8: 3710 adds r7, #16
- 80052ea: 46bd mov sp, r7
- 80052ec: bd80 pop {r7, pc}
-
-080052ee <UART_WaitOnFlagUntilTimeout>:
- * @param Tickstart Tick start value
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
- 80052ee: b580 push {r7, lr}
- 80052f0: b084 sub sp, #16
- 80052f2: af00 add r7, sp, #0
- 80052f4: 60f8 str r0, [r7, #12]
- 80052f6: 60b9 str r1, [r7, #8]
- 80052f8: 603b str r3, [r7, #0]
- 80052fa: 4613 mov r3, r2
- 80052fc: 71fb strb r3, [r7, #7]
- /* Wait until flag is set */
- while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 80052fe: e02a b.n 8005356 <UART_WaitOnFlagUntilTimeout+0x68>
- {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- 8005300: 69bb ldr r3, [r7, #24]
- 8005302: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
- 8005306: d026 beq.n 8005356 <UART_WaitOnFlagUntilTimeout+0x68>
- {
- if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 8005308: f7fc fd5e bl 8001dc8 <HAL_GetTick>
- 800530c: 4602 mov r2, r0
- 800530e: 683b ldr r3, [r7, #0]
- 8005310: 1ad3 subs r3, r2, r3
- 8005312: 69ba ldr r2, [r7, #24]
- 8005314: 429a cmp r2, r3
- 8005316: d302 bcc.n 800531e <UART_WaitOnFlagUntilTimeout+0x30>
- 8005318: 69bb ldr r3, [r7, #24]
- 800531a: 2b00 cmp r3, #0
- 800531c: d11b bne.n 8005356 <UART_WaitOnFlagUntilTimeout+0x68>
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- 800531e: 68fb ldr r3, [r7, #12]
- 8005320: 681b ldr r3, [r3, #0]
- 8005322: 681a ldr r2, [r3, #0]
- 8005324: 68fb ldr r3, [r7, #12]
- 8005326: 681b ldr r3, [r3, #0]
- 8005328: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
- 800532c: 601a str r2, [r3, #0]
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 800532e: 68fb ldr r3, [r7, #12]
- 8005330: 681b ldr r3, [r3, #0]
- 8005332: 689a ldr r2, [r3, #8]
- 8005334: 68fb ldr r3, [r7, #12]
- 8005336: 681b ldr r3, [r3, #0]
- 8005338: f022 0201 bic.w r2, r2, #1
- 800533c: 609a str r2, [r3, #8]
-
- huart->gState = HAL_UART_STATE_READY;
- 800533e: 68fb ldr r3, [r7, #12]
- 8005340: 2220 movs r2, #32
- 8005342: 675a str r2, [r3, #116] ; 0x74
- huart->RxState = HAL_UART_STATE_READY;
- 8005344: 68fb ldr r3, [r7, #12]
- 8005346: 2220 movs r2, #32
- 8005348: 679a str r2, [r3, #120] ; 0x78
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 800534a: 68fb ldr r3, [r7, #12]
- 800534c: 2200 movs r2, #0
- 800534e: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- return HAL_TIMEOUT;
- 8005352: 2303 movs r3, #3
- 8005354: e00f b.n 8005376 <UART_WaitOnFlagUntilTimeout+0x88>
- while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 8005356: 68fb ldr r3, [r7, #12]
- 8005358: 681b ldr r3, [r3, #0]
- 800535a: 69da ldr r2, [r3, #28]
- 800535c: 68bb ldr r3, [r7, #8]
- 800535e: 4013 ands r3, r2
- 8005360: 68ba ldr r2, [r7, #8]
- 8005362: 429a cmp r2, r3
- 8005364: bf0c ite eq
- 8005366: 2301 moveq r3, #1
- 8005368: 2300 movne r3, #0
- 800536a: b2db uxtb r3, r3
- 800536c: 461a mov r2, r3
- 800536e: 79fb ldrb r3, [r7, #7]
- 8005370: 429a cmp r2, r3
- 8005372: d0c5 beq.n 8005300 <UART_WaitOnFlagUntilTimeout+0x12>
- }
- }
- }
- return HAL_OK;
- 8005374: 2300 movs r3, #0
-}
- 8005376: 4618 mov r0, r3
- 8005378: 3710 adds r7, #16
- 800537a: 46bd mov sp, r7
- 800537c: bd80 pop {r7, pc}
-
-0800537e <UART_EndRxTransfer>:
- * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
- * @param huart UART handle.
- * @retval None
- */
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
-{
- 800537e: b480 push {r7}
- 8005380: b083 sub sp, #12
- 8005382: af00 add r7, sp, #0
- 8005384: 6078 str r0, [r7, #4]
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 8005386: 687b ldr r3, [r7, #4]
- 8005388: 681b ldr r3, [r3, #0]
- 800538a: 681a ldr r2, [r3, #0]
- 800538c: 687b ldr r3, [r7, #4]
- 800538e: 681b ldr r3, [r3, #0]
- 8005390: f422 7290 bic.w r2, r2, #288 ; 0x120
- 8005394: 601a str r2, [r3, #0]
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 8005396: 687b ldr r3, [r7, #4]
- 8005398: 681b ldr r3, [r3, #0]
- 800539a: 689a ldr r2, [r3, #8]
- 800539c: 687b ldr r3, [r7, #4]
- 800539e: 681b ldr r3, [r3, #0]
- 80053a0: f022 0201 bic.w r2, r2, #1
- 80053a4: 609a str r2, [r3, #8]
-
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- 80053a6: 687b ldr r3, [r7, #4]
- 80053a8: 2220 movs r2, #32
- 80053aa: 679a str r2, [r3, #120] ; 0x78
-
- /* Reset RxIsr function pointer */
- huart->RxISR = NULL;
- 80053ac: 687b ldr r3, [r7, #4]
- 80053ae: 2200 movs r2, #0
- 80053b0: 661a str r2, [r3, #96] ; 0x60
-}
- 80053b2: bf00 nop
- 80053b4: 370c adds r7, #12
- 80053b6: 46bd mov sp, r7
- 80053b8: f85d 7b04 ldr.w r7, [sp], #4
- 80053bc: 4770 bx lr
-
-080053be <UART_DMAAbortOnError>:
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- 80053be: b580 push {r7, lr}
- 80053c0: b084 sub sp, #16
- 80053c2: af00 add r7, sp, #0
- 80053c4: 6078 str r0, [r7, #4]
- UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
- 80053c6: 687b ldr r3, [r7, #4]
- 80053c8: 6b9b ldr r3, [r3, #56] ; 0x38
- 80053ca: 60fb str r3, [r7, #12]
- huart->RxXferCount = 0U;
- 80053cc: 68fb ldr r3, [r7, #12]
- 80053ce: 2200 movs r2, #0
- 80053d0: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
- huart->TxXferCount = 0U;
- 80053d4: 68fb ldr r3, [r7, #12]
- 80053d6: 2200 movs r2, #0
- 80053d8: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 80053dc: 68f8 ldr r0, [r7, #12]
- 80053de: f7ff fc07 bl 8004bf0 <HAL_UART_ErrorCallback>
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
- 80053e2: bf00 nop
- 80053e4: 3710 adds r7, #16
- 80053e6: 46bd mov sp, r7
- 80053e8: bd80 pop {r7, pc}
-
-080053ea <UART_EndTransmit_IT>:
- * @param huart pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval None
- */
-static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
-{
- 80053ea: b580 push {r7, lr}
- 80053ec: b082 sub sp, #8
- 80053ee: af00 add r7, sp, #0
- 80053f0: 6078 str r0, [r7, #4]
- /* Disable the UART Transmit Complete Interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
- 80053f2: 687b ldr r3, [r7, #4]
- 80053f4: 681b ldr r3, [r3, #0]
- 80053f6: 681a ldr r2, [r3, #0]
- 80053f8: 687b ldr r3, [r7, #4]
- 80053fa: 681b ldr r3, [r3, #0]
- 80053fc: f022 0240 bic.w r2, r2, #64 ; 0x40
- 8005400: 601a str r2, [r3, #0]
-
- /* Tx process is ended, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- 8005402: 687b ldr r3, [r7, #4]
- 8005404: 2220 movs r2, #32
- 8005406: 675a str r2, [r3, #116] ; 0x74
-
- /* Cleat TxISR function pointer */
- huart->TxISR = NULL;
- 8005408: 687b ldr r3, [r7, #4]
- 800540a: 2200 movs r2, #0
- 800540c: 665a str r2, [r3, #100] ; 0x64
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Tx complete callback*/
- huart->TxCpltCallback(huart);
-#else
- /*Call legacy weak Tx complete callback*/
- HAL_UART_TxCpltCallback(huart);
- 800540e: 6878 ldr r0, [r7, #4]
- 8005410: f7ff fbe4 bl 8004bdc <HAL_UART_TxCpltCallback>
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
- 8005414: bf00 nop
- 8005416: 3708 adds r7, #8
- 8005418: 46bd mov sp, r7
- 800541a: bd80 pop {r7, pc}
-
-0800541c <UART_RxISR_8BIT>:
- * @brief RX interrrupt handler for 7 or 8 bits data word length .
- * @param huart UART handle.
- * @retval None
- */
-static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
-{
- 800541c: b580 push {r7, lr}
- 800541e: b084 sub sp, #16
- 8005420: af00 add r7, sp, #0
- 8005422: 6078 str r0, [r7, #4]
- uint16_t uhMask = huart->Mask;
- 8005424: 687b ldr r3, [r7, #4]
- 8005426: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
- 800542a: 81fb strh r3, [r7, #14]
- uint16_t uhdata;
-
- /* Check that a Rx process is ongoing */
- if (huart->RxState == HAL_UART_STATE_BUSY_RX)
- 800542c: 687b ldr r3, [r7, #4]
- 800542e: 6f9b ldr r3, [r3, #120] ; 0x78
- 8005430: 2b22 cmp r3, #34 ; 0x22
- 8005432: d13a bne.n 80054aa <UART_RxISR_8BIT+0x8e>
- {
- uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
- 8005434: 687b ldr r3, [r7, #4]
- 8005436: 681b ldr r3, [r3, #0]
- 8005438: 6a5b ldr r3, [r3, #36] ; 0x24
- 800543a: 81bb strh r3, [r7, #12]
- *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
- 800543c: 89bb ldrh r3, [r7, #12]
- 800543e: b2d9 uxtb r1, r3
- 8005440: 89fb ldrh r3, [r7, #14]
- 8005442: b2da uxtb r2, r3
- 8005444: 687b ldr r3, [r7, #4]
- 8005446: 6d5b ldr r3, [r3, #84] ; 0x54
- 8005448: 400a ands r2, r1
- 800544a: b2d2 uxtb r2, r2
- 800544c: 701a strb r2, [r3, #0]
- huart->pRxBuffPtr++;
- 800544e: 687b ldr r3, [r7, #4]
- 8005450: 6d5b ldr r3, [r3, #84] ; 0x54
- 8005452: 1c5a adds r2, r3, #1
- 8005454: 687b ldr r3, [r7, #4]
- 8005456: 655a str r2, [r3, #84] ; 0x54
- huart->RxXferCount--;
- 8005458: 687b ldr r3, [r7, #4]
- 800545a: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 800545e: b29b uxth r3, r3
- 8005460: 3b01 subs r3, #1
- 8005462: b29a uxth r2, r3
- 8005464: 687b ldr r3, [r7, #4]
- 8005466: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
-
- if (huart->RxXferCount == 0U)
- 800546a: 687b ldr r3, [r7, #4]
- 800546c: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 8005470: b29b uxth r3, r3
- 8005472: 2b00 cmp r3, #0
- 8005474: d121 bne.n 80054ba <UART_RxISR_8BIT+0x9e>
- {
- /* Disable the UART Parity Error Interrupt and RXNE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 8005476: 687b ldr r3, [r7, #4]
- 8005478: 681b ldr r3, [r3, #0]
- 800547a: 681a ldr r2, [r3, #0]
- 800547c: 687b ldr r3, [r7, #4]
- 800547e: 681b ldr r3, [r3, #0]
- 8005480: f422 7290 bic.w r2, r2, #288 ; 0x120
- 8005484: 601a str r2, [r3, #0]
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 8005486: 687b ldr r3, [r7, #4]
- 8005488: 681b ldr r3, [r3, #0]
- 800548a: 689a ldr r2, [r3, #8]
- 800548c: 687b ldr r3, [r7, #4]
- 800548e: 681b ldr r3, [r3, #0]
- 8005490: f022 0201 bic.w r2, r2, #1
- 8005494: 609a str r2, [r3, #8]
-
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- 8005496: 687b ldr r3, [r7, #4]
- 8005498: 2220 movs r2, #32
- 800549a: 679a str r2, [r3, #120] ; 0x78
-
- /* Clear RxISR function pointer */
- huart->RxISR = NULL;
- 800549c: 687b ldr r3, [r7, #4]
- 800549e: 2200 movs r2, #0
- 80054a0: 661a str r2, [r3, #96] ; 0x60
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
-#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
- 80054a2: 6878 ldr r0, [r7, #4]
- 80054a4: f7fc f854 bl 8001550 <HAL_UART_RxCpltCallback>
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- }
-}
- 80054a8: e007 b.n 80054ba <UART_RxISR_8BIT+0x9e>
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- 80054aa: 687b ldr r3, [r7, #4]
- 80054ac: 681b ldr r3, [r3, #0]
- 80054ae: 699a ldr r2, [r3, #24]
- 80054b0: 687b ldr r3, [r7, #4]
- 80054b2: 681b ldr r3, [r3, #0]
- 80054b4: f042 0208 orr.w r2, r2, #8
- 80054b8: 619a str r2, [r3, #24]
-}
- 80054ba: bf00 nop
- 80054bc: 3710 adds r7, #16
- 80054be: 46bd mov sp, r7
- 80054c0: bd80 pop {r7, pc}
-
-080054c2 <UART_RxISR_16BIT>:
- * interruptions have been enabled by HAL_UART_Receive_IT()
- * @param huart UART handle.
- * @retval None
- */
-static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
-{
- 80054c2: b580 push {r7, lr}
- 80054c4: b084 sub sp, #16
- 80054c6: af00 add r7, sp, #0
- 80054c8: 6078 str r0, [r7, #4]
- uint16_t *tmp;
- uint16_t uhMask = huart->Mask;
- 80054ca: 687b ldr r3, [r7, #4]
- 80054cc: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
- 80054d0: 81fb strh r3, [r7, #14]
- uint16_t uhdata;
-
- /* Check that a Rx process is ongoing */
- if (huart->RxState == HAL_UART_STATE_BUSY_RX)
- 80054d2: 687b ldr r3, [r7, #4]
- 80054d4: 6f9b ldr r3, [r3, #120] ; 0x78
- 80054d6: 2b22 cmp r3, #34 ; 0x22
- 80054d8: d13a bne.n 8005550 <UART_RxISR_16BIT+0x8e>
- {
- uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
- 80054da: 687b ldr r3, [r7, #4]
- 80054dc: 681b ldr r3, [r3, #0]
- 80054de: 6a5b ldr r3, [r3, #36] ; 0x24
- 80054e0: 81bb strh r3, [r7, #12]
- tmp = (uint16_t *) huart->pRxBuffPtr ;
- 80054e2: 687b ldr r3, [r7, #4]
- 80054e4: 6d5b ldr r3, [r3, #84] ; 0x54
- 80054e6: 60bb str r3, [r7, #8]
- *tmp = (uint16_t)(uhdata & uhMask);
- 80054e8: 89ba ldrh r2, [r7, #12]
- 80054ea: 89fb ldrh r3, [r7, #14]
- 80054ec: 4013 ands r3, r2
- 80054ee: b29a uxth r2, r3
- 80054f0: 68bb ldr r3, [r7, #8]
- 80054f2: 801a strh r2, [r3, #0]
- huart->pRxBuffPtr += 2U;
- 80054f4: 687b ldr r3, [r7, #4]
- 80054f6: 6d5b ldr r3, [r3, #84] ; 0x54
- 80054f8: 1c9a adds r2, r3, #2
- 80054fa: 687b ldr r3, [r7, #4]
- 80054fc: 655a str r2, [r3, #84] ; 0x54
- huart->RxXferCount--;
- 80054fe: 687b ldr r3, [r7, #4]
- 8005500: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 8005504: b29b uxth r3, r3
- 8005506: 3b01 subs r3, #1
- 8005508: b29a uxth r2, r3
- 800550a: 687b ldr r3, [r7, #4]
- 800550c: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
-
- if (huart->RxXferCount == 0U)
- 8005510: 687b ldr r3, [r7, #4]
- 8005512: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 8005516: b29b uxth r3, r3
- 8005518: 2b00 cmp r3, #0
- 800551a: d121 bne.n 8005560 <UART_RxISR_16BIT+0x9e>
- {
- /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 800551c: 687b ldr r3, [r7, #4]
- 800551e: 681b ldr r3, [r3, #0]
- 8005520: 681a ldr r2, [r3, #0]
- 8005522: 687b ldr r3, [r7, #4]
- 8005524: 681b ldr r3, [r3, #0]
- 8005526: f422 7290 bic.w r2, r2, #288 ; 0x120
- 800552a: 601a str r2, [r3, #0]
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 800552c: 687b ldr r3, [r7, #4]
- 800552e: 681b ldr r3, [r3, #0]
- 8005530: 689a ldr r2, [r3, #8]
- 8005532: 687b ldr r3, [r7, #4]
- 8005534: 681b ldr r3, [r3, #0]
- 8005536: f022 0201 bic.w r2, r2, #1
- 800553a: 609a str r2, [r3, #8]
-
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- 800553c: 687b ldr r3, [r7, #4]
- 800553e: 2220 movs r2, #32
- 8005540: 679a str r2, [r3, #120] ; 0x78
-
- /* Clear RxISR function pointer */
- huart->RxISR = NULL;
- 8005542: 687b ldr r3, [r7, #4]
- 8005544: 2200 movs r2, #0
- 8005546: 661a str r2, [r3, #96] ; 0x60
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
-#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
- 8005548: 6878 ldr r0, [r7, #4]
- 800554a: f7fc f801 bl 8001550 <HAL_UART_RxCpltCallback>
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- }
-}
- 800554e: e007 b.n 8005560 <UART_RxISR_16BIT+0x9e>
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- 8005550: 687b ldr r3, [r7, #4]
- 8005552: 681b ldr r3, [r3, #0]
- 8005554: 699a ldr r2, [r3, #24]
- 8005556: 687b ldr r3, [r7, #4]
- 8005558: 681b ldr r3, [r3, #0]
- 800555a: f042 0208 orr.w r2, r2, #8
- 800555e: 619a str r2, [r3, #24]
-}
- 8005560: bf00 nop
- 8005562: 3710 adds r7, #16
- 8005564: 46bd mov sp, r7
- 8005566: bd80 pop {r7, pc}
-
-08005568 <__libc_init_array>:
- 8005568: b570 push {r4, r5, r6, lr}
- 800556a: 4e0d ldr r6, [pc, #52] ; (80055a0 <__libc_init_array+0x38>)
- 800556c: 4c0d ldr r4, [pc, #52] ; (80055a4 <__libc_init_array+0x3c>)
- 800556e: 1ba4 subs r4, r4, r6
- 8005570: 10a4 asrs r4, r4, #2
- 8005572: 2500 movs r5, #0
- 8005574: 42a5 cmp r5, r4
- 8005576: d109 bne.n 800558c <__libc_init_array+0x24>
- 8005578: 4e0b ldr r6, [pc, #44] ; (80055a8 <__libc_init_array+0x40>)
- 800557a: 4c0c ldr r4, [pc, #48] ; (80055ac <__libc_init_array+0x44>)
- 800557c: f000 f820 bl 80055c0 <_init>
- 8005580: 1ba4 subs r4, r4, r6
- 8005582: 10a4 asrs r4, r4, #2
- 8005584: 2500 movs r5, #0
- 8005586: 42a5 cmp r5, r4
- 8005588: d105 bne.n 8005596 <__libc_init_array+0x2e>
- 800558a: bd70 pop {r4, r5, r6, pc}
- 800558c: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 8005590: 4798 blx r3
- 8005592: 3501 adds r5, #1
- 8005594: e7ee b.n 8005574 <__libc_init_array+0xc>
- 8005596: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 800559a: 4798 blx r3
- 800559c: 3501 adds r5, #1
- 800559e: e7f2 b.n 8005586 <__libc_init_array+0x1e>
- 80055a0: 080055f8 .word 0x080055f8
- 80055a4: 080055f8 .word 0x080055f8
- 80055a8: 080055f8 .word 0x080055f8
- 80055ac: 08005600 .word 0x08005600
-
-080055b0 <memset>:
- 80055b0: 4402 add r2, r0
- 80055b2: 4603 mov r3, r0
- 80055b4: 4293 cmp r3, r2
- 80055b6: d100 bne.n 80055ba <memset+0xa>
- 80055b8: 4770 bx lr
- 80055ba: f803 1b01 strb.w r1, [r3], #1
- 80055be: e7f9 b.n 80055b4 <memset+0x4>
-
-080055c0 <_init>:
- 80055c0: b5f8 push {r3, r4, r5, r6, r7, lr}
- 80055c2: bf00 nop
- 80055c4: bcf8 pop {r3, r4, r5, r6, r7}
- 80055c6: bc08 pop {r3}
- 80055c8: 469e mov lr, r3
- 80055ca: 4770 bx lr
-
-080055cc <_fini>:
- 80055cc: b5f8 push {r3, r4, r5, r6, r7, lr}
- 80055ce: bf00 nop
- 80055d0: bcf8 pop {r3, r4, r5, r6, r7}
- 80055d2: bc08 pop {r3}
- 80055d4: 469e mov lr, r3
- 80055d6: 4770 bx lr
projects / pioneer-stm32 / commitdiff